[mirror_qemu.git] / include / qemu / atomic.h

/*
 * Simple interface for atomic operations.
 *
 * Copyright (C) 2013 Red Hat, Inc.
 *
 * Author: Paolo Bonzini <pbonzini@redhat.com>
 *
 * This work is licensed under the terms of the GNU GPL, version 2 or later.
 * See the COPYING file in the top-level directory.
 *
 * See docs/atomics.txt for discussion about the guarantees each
 * atomic primitive is meant to provide.
 */

#ifndef QEMU_ATOMIC_H
#define QEMU_ATOMIC_H

/* Compiler barrier */
#define barrier()   ({ asm volatile("" ::: "memory"); (void)0; })

/* The variable that receives the old value of an atomically-accessed
 * variable must be non-qualified, because atomic builtins return values
 * through a pointer-type argument as in __atomic_load(&var, &old, MODEL).
 *
 * This macro has to handle types smaller than int manually, because of
 * implicit promotion.  int and larger types, as well as pointers, can be
 * converted to a non-qualified type just by applying a binary operator.
 */
#define typeof_strip_qual(expr)                                                    \
  typeof(                                                                          \
    __builtin_choose_expr(                                                         \
      __builtin_types_compatible_p(typeof(expr), bool) ||                          \
        __builtin_types_compatible_p(typeof(expr), const bool) ||                  \
        __builtin_types_compatible_p(typeof(expr), volatile bool) ||               \
        __builtin_types_compatible_p(typeof(expr), const volatile bool),           \
        (bool)1,                                                                   \
    __builtin_choose_expr(                                                         \
      __builtin_types_compatible_p(typeof(expr), signed char) ||                   \
        __builtin_types_compatible_p(typeof(expr), const signed char) ||           \
        __builtin_types_compatible_p(typeof(expr), volatile signed char) ||        \
        __builtin_types_compatible_p(typeof(expr), const volatile signed char),    \
        (signed char)1,                                                            \
    __builtin_choose_expr(                                                         \
      __builtin_types_compatible_p(typeof(expr), unsigned char) ||                 \
        __builtin_types_compatible_p(typeof(expr), const unsigned char) ||         \
        __builtin_types_compatible_p(typeof(expr), volatile unsigned char) ||      \
        __builtin_types_compatible_p(typeof(expr), const volatile unsigned char),  \
        (unsigned char)1,                                                          \
    __builtin_choose_expr(                                                         \
      __builtin_types_compatible_p(typeof(expr), signed short) ||                  \
        __builtin_types_compatible_p(typeof(expr), const signed short) ||          \
        __builtin_types_compatible_p(typeof(expr), volatile signed short) ||       \
        __builtin_types_compatible_p(typeof(expr), const volatile signed short),   \
        (signed short)1,                                                           \
    __builtin_choose_expr(                                                         \
      __builtin_types_compatible_p(typeof(expr), unsigned short) ||                \
        __builtin_types_compatible_p(typeof(expr), const unsigned short) ||        \
        __builtin_types_compatible_p(typeof(expr), volatile unsigned short) ||     \
        __builtin_types_compatible_p(typeof(expr), const volatile unsigned short), \
        (unsigned short)1,                                                         \
      (expr)+0))))))

#ifdef __ATOMIC_RELAXED
/* For C11 atomic ops */

/* Manual memory barriers
 *
 *__atomic_thread_fence does not include a compiler barrier; instead,
 * the barrier is part of __atomic_load/__atomic_store's "volatile-like"
 * semantics. If smp_wmb() is a no-op, absence of the barrier means that
 * the compiler is free to reorder stores on each side of the barrier.
 * Add one here, and similarly in smp_rmb() and smp_read_barrier_depends().
 */

#define smp_mb()    ({ barrier(); __atomic_thread_fence(__ATOMIC_SEQ_CST); })
#define smp_wmb()   ({ barrier(); __atomic_thread_fence(__ATOMIC_RELEASE); })
#define smp_rmb()   ({ barrier(); __atomic_thread_fence(__ATOMIC_ACQUIRE); })

/* Most compilers currently treat consume and acquire the same, but really
 * no processors except Alpha need a barrier here.  Leave it in if
 * using Thread Sanitizer to avoid warnings, otherwise optimize it away.
 */
#if defined(__SANITIZE_THREAD__)
#define smp_read_barrier_depends() ({ barrier(); __atomic_thread_fence(__ATOMIC_CONSUME); })
#elif defined(__alpha__)
#define smp_read_barrier_depends()   asm volatile("mb":::"memory")
#else
#define smp_read_barrier_depends()   barrier()
#endif


/* Weak atomic operations prevent the compiler moving other
 * loads/stores past the atomic operation load/store. However there is
 * no explicit memory barrier for the processor.
 *
 * The C11 memory model says that variables that are accessed from
 * different threads should at least be done with __ATOMIC_RELAXED
 * primitives or the result is undefined. Generally this has little to
 * no effect on the generated code but not using the atomic primitives
 * will get flagged by sanitizers as a violation.
 */
#define atomic_read(ptr)                              \
    ({                                                \
    QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *)); \
    __atomic_load_n(ptr, __ATOMIC_RELAXED);           \
    })

#define atomic_set(ptr, i)  do {                      \
    QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *)); \
    __atomic_store_n(ptr, i, __ATOMIC_RELAXED);       \
} while(0)

/* See above: most compilers currently treat consume and acquire the
 * same, but this slows down atomic_rcu_read unnecessarily.
 */
#ifdef __SANITIZE_THREAD__
#define atomic_rcu_read__nocheck(ptr, valptr)           \
    __atomic_load(ptr, valptr, __ATOMIC_CONSUME);
#else
#define atomic_rcu_read__nocheck(ptr, valptr)           \
    __atomic_load(ptr, valptr, __ATOMIC_RELAXED);       \
    smp_read_barrier_depends();
#endif

#define atomic_rcu_read(ptr)                          \
    ({                                                \
    QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *)); \
    typeof_strip_qual(*ptr) _val;                     \
    atomic_rcu_read__nocheck(ptr, &_val);             \
    _val;                                             \
    })

#define atomic_rcu_set(ptr, i) do {                   \
    QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *)); \
    __atomic_store_n(ptr, i, __ATOMIC_RELEASE);       \
} while(0)

/* atomic_mb_read/set semantics map Java volatile variables. They are
 * less expensive on some platforms (notably POWER & ARMv7) than fully
 * sequentially consistent operations.
 *
 * As long as they are used as paired operations they are safe to
 * use. See docs/atomic.txt for more discussion.
 */

#if defined(_ARCH_PPC)
#define atomic_mb_read(ptr)                             \
    ({                                                  \
    QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *));   \
    typeof_strip_qual(*ptr) _val;                       \
     __atomic_load(ptr, &_val, __ATOMIC_RELAXED);       \
     smp_rmb();                                         \
    _val;                                               \
    })

#define atomic_mb_set(ptr, i)  do {                     \
    QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *));   \
    smp_wmb();                                          \
    __atomic_store_n(ptr, i, __ATOMIC_RELAXED);         \
    smp_mb();                                           \
} while(0)
#else
#define atomic_mb_read(ptr)                             \
    ({                                                  \
    QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *));   \
    typeof_strip_qual(*ptr) _val;                       \
    __atomic_load(ptr, &_val, __ATOMIC_SEQ_CST);        \
    _val;                                               \
    })

#define atomic_mb_set(ptr, i)  do {                     \
    QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *));   \
    __atomic_store_n(ptr, i, __ATOMIC_SEQ_CST);         \
} while(0)
#endif


/* All the remaining operations are fully sequentially consistent */

#define atomic_xchg(ptr, i)    ({                           \
    QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *));       \
    __atomic_exchange_n(ptr, i, __ATOMIC_SEQ_CST);          \
})

/* Returns the eventual value, failed or not */
#define atomic_cmpxchg(ptr, old, new)                                   \
    ({                                                                  \
    QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *));                   \
    typeof_strip_qual(*ptr) _old = (old);                               \
    __atomic_compare_exchange_n(ptr, &_old, new, false,                 \
                              __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST);      \
    _old;                                                               \
    })

/* Provide shorter names for GCC atomic builtins, return old value */
#define atomic_fetch_inc(ptr)  __atomic_fetch_add(ptr, 1, __ATOMIC_SEQ_CST)
#define atomic_fetch_dec(ptr)  __atomic_fetch_sub(ptr, 1, __ATOMIC_SEQ_CST)
#define atomic_fetch_add(ptr, n) __atomic_fetch_add(ptr, n, __ATOMIC_SEQ_CST)
#define atomic_fetch_sub(ptr, n) __atomic_fetch_sub(ptr, n, __ATOMIC_SEQ_CST)
#define atomic_fetch_and(ptr, n) __atomic_fetch_and(ptr, n, __ATOMIC_SEQ_CST)
#define atomic_fetch_or(ptr, n)  __atomic_fetch_or(ptr, n, __ATOMIC_SEQ_CST)

/* And even shorter names that return void.  */
#define atomic_inc(ptr)    ((void) __atomic_fetch_add(ptr, 1, __ATOMIC_SEQ_CST))
#define atomic_dec(ptr)    ((void) __atomic_fetch_sub(ptr, 1, __ATOMIC_SEQ_CST))
#define atomic_add(ptr, n) ((void) __atomic_fetch_add(ptr, n, __ATOMIC_SEQ_CST))
#define atomic_sub(ptr, n) ((void) __atomic_fetch_sub(ptr, n, __ATOMIC_SEQ_CST))
#define atomic_and(ptr, n) ((void) __atomic_fetch_and(ptr, n, __ATOMIC_SEQ_CST))
#define atomic_or(ptr, n)  ((void) __atomic_fetch_or(ptr, n, __ATOMIC_SEQ_CST))

#else /* __ATOMIC_RELAXED */

/*
 * We use GCC builtin if it's available, as that can use mfence on
 * 32-bit as well, e.g. if built with -march=pentium-m. However, on
 * i386 the spec is buggy, and the implementation followed it until
 * 4.3 (http://gcc.gnu.org/bugzilla/show_bug.cgi?id=36793).
 */
#if defined(__i386__) || defined(__x86_64__)
#if !QEMU_GNUC_PREREQ(4, 4)
#if defined __x86_64__
#define smp_mb()    ({ asm volatile("mfence" ::: "memory"); (void)0; })
#else
#define smp_mb()    ({ asm volatile("lock; addl $0,0(%%esp) " ::: "memory"); (void)0; })
#endif
#endif
#endif


#ifdef __alpha__
#define smp_read_barrier_depends()   asm volatile("mb":::"memory")
#endif

#if defined(__i386__) || defined(__x86_64__) || defined(__s390x__)

/*
 * Because of the strongly ordered storage model, wmb() and rmb() are nops
 * here (a compiler barrier only).  QEMU doesn't do accesses to write-combining
 * qemu memory or non-temporal load/stores from C code.
 */
#define smp_wmb()   barrier()
#define smp_rmb()   barrier()

/*
 * __sync_lock_test_and_set() is documented to be an acquire barrier only,
 * but it is a full barrier at the hardware level.  Add a compiler barrier
 * to make it a full barrier also at the compiler level.
 */
#define atomic_xchg(ptr, i)    (barrier(), __sync_lock_test_and_set(ptr, i))

/*
 * Load/store with Java volatile semantics.
 */
#define atomic_mb_set(ptr, i)  ((void)atomic_xchg(ptr, i))

#elif defined(_ARCH_PPC)

/*
 * We use an eieio() for wmb() on powerpc.  This assumes we don't
 * need to order cacheable and non-cacheable stores with respect to
 * each other.
 *
 * smp_mb has the same problem as on x86 for not-very-new GCC
 * (http://patchwork.ozlabs.org/patch/126184/, Nov 2011).
 */
#define smp_wmb()   ({ asm volatile("eieio" ::: "memory"); (void)0; })
#if defined(__powerpc64__)
#define smp_rmb()   ({ asm volatile("lwsync" ::: "memory"); (void)0; })
#else
#define smp_rmb()   ({ asm volatile("sync" ::: "memory"); (void)0; })
#endif
#define smp_mb()    ({ asm volatile("sync" ::: "memory"); (void)0; })

#endif /* _ARCH_PPC */

/*
 * For (host) platforms we don't have explicit barrier definitions
 * for, we use the gcc __sync_synchronize() primitive to generate a
 * full barrier.  This should be safe on all platforms, though it may
 * be overkill for smp_wmb() and smp_rmb().
 */
#ifndef smp_mb
#define smp_mb()    __sync_synchronize()
#endif

#ifndef smp_wmb
#define smp_wmb()   __sync_synchronize()
#endif

#ifndef smp_rmb
#define smp_rmb()   __sync_synchronize()
#endif

#ifndef smp_read_barrier_depends
#define smp_read_barrier_depends()   barrier()
#endif

/* These will only be atomic if the processor does the fetch or store
 * in a single issue memory operation
 */
#define atomic_read(ptr)       (*(__typeof__(*ptr) volatile*) (ptr))
#define atomic_set(ptr, i)     ((*(__typeof__(*ptr) volatile*) (ptr)) = (i))

/**
 * atomic_rcu_read - reads a RCU-protected pointer to a local variable
 * into a RCU read-side critical section. The pointer can later be safely
 * dereferenced within the critical section.
 *
 * This ensures that the pointer copy is invariant thorough the whole critical
 * section.
 *
 * Inserts memory barriers on architectures that require them (currently only
 * Alpha) and documents which pointers are protected by RCU.
 *
 * atomic_rcu_read also includes a compiler barrier to ensure that
 * value-speculative optimizations (e.g. VSS: Value Speculation
 * Scheduling) does not perform the data read before the pointer read
 * by speculating the value of the pointer.
 *
 * Should match atomic_rcu_set(), atomic_xchg(), atomic_cmpxchg().
 */
#define atomic_rcu_read(ptr)    ({                \
    typeof(*ptr) _val = atomic_read(ptr);         \
    smp_read_barrier_depends();                   \
    _val;                                         \
})

/**
 * atomic_rcu_set - assigns (publicizes) a pointer to a new data structure
 * meant to be read by RCU read-side critical sections.
 *
 * Documents which pointers will be dereferenced by RCU read-side critical
 * sections and adds the required memory barriers on architectures requiring
 * them. It also makes sure the compiler does not reorder code initializing the
 * data structure before its publication.
 *
 * Should match atomic_rcu_read().
 */
#define atomic_rcu_set(ptr, i)  do {              \
    smp_wmb();                                    \
    atomic_set(ptr, i);                           \
} while (0)

/* These have the same semantics as Java volatile variables.
 * See http://gee.cs.oswego.edu/dl/jmm/cookbook.html:
 * "1. Issue a StoreStore barrier (wmb) before each volatile store."
 *  2. Issue a StoreLoad barrier after each volatile store.
 *     Note that you could instead issue one before each volatile load, but
 *     this would be slower for typical programs using volatiles in which
 *     reads greatly outnumber writes. Alternatively, if available, you
 *     can implement volatile store as an atomic instruction (for example
 *     XCHG on x86) and omit the barrier. This may be more efficient if
 *     atomic instructions are cheaper than StoreLoad barriers.
 *  3. Issue LoadLoad and LoadStore barriers after each volatile load."
 *
 * If you prefer to think in terms of "pairing" of memory barriers,
 * an atomic_mb_read pairs with an atomic_mb_set.
 *
 * And for the few ia64 lovers that exist, an atomic_mb_read is a ld.acq,
 * while an atomic_mb_set is a st.rel followed by a memory barrier.
 *
 * These are a bit weaker than __atomic_load/store with __ATOMIC_SEQ_CST
 * (see docs/atomics.txt), and I'm not sure that __ATOMIC_ACQ_REL is enough.
 * Just always use the barriers manually by the rules above.
 */
#define atomic_mb_read(ptr)    ({           \
    typeof(*ptr) _val = atomic_read(ptr);   \
    smp_rmb();                              \
    _val;                                   \
})

#ifndef atomic_mb_set
#define atomic_mb_set(ptr, i)  do {         \
    smp_wmb();                              \
    atomic_set(ptr, i);                     \
    smp_mb();                               \
} while (0)
#endif

#ifndef atomic_xchg
#if defined(__clang__)
#define atomic_xchg(ptr, i)    __sync_swap(ptr, i)
#else
/* __sync_lock_test_and_set() is documented to be an acquire barrier only.  */
#define atomic_xchg(ptr, i)    (smp_mb(), __sync_lock_test_and_set(ptr, i))
#endif
#endif

/* Provide shorter names for GCC atomic builtins.  */
#define atomic_fetch_inc(ptr)  __sync_fetch_and_add(ptr, 1)
#define atomic_fetch_dec(ptr)  __sync_fetch_and_add(ptr, -1)
#define atomic_fetch_add       __sync_fetch_and_add
#define atomic_fetch_sub       __sync_fetch_and_sub
#define atomic_fetch_and       __sync_fetch_and_and
#define atomic_fetch_or        __sync_fetch_and_or
#define atomic_cmpxchg         __sync_val_compare_and_swap

/* And even shorter names that return void.  */
#define atomic_inc(ptr)        ((void) __sync_fetch_and_add(ptr, 1))
#define atomic_dec(ptr)        ((void) __sync_fetch_and_add(ptr, -1))
#define atomic_add(ptr, n)     ((void) __sync_fetch_and_add(ptr, n))
#define atomic_sub(ptr, n)     ((void) __sync_fetch_and_sub(ptr, n))
#define atomic_and(ptr, n)     ((void) __sync_fetch_and_and(ptr, n))
#define atomic_or(ptr, n)      ((void) __sync_fetch_and_or(ptr, n))

#endif /* __ATOMIC_RELAXED */
#endif /* QEMU_ATOMIC_H */
Commit	Line	Data
5444e768 PB	1	/*
	2	* Simple interface for atomic operations.
	3	*
	4	* Copyright (C) 2013 Red Hat, Inc.
	5	*
	6	* Author: Paolo Bonzini <pbonzini@redhat.com>
	7	*
	8	* This work is licensed under the terms of the GNU GPL, version 2 or later.
	9	* See the COPYING file in the top-level directory.
	10	*
a0aa44b4 AB	11	* See docs/atomics.txt for discussion about the guarantees each
a0aa44b4 AB	12	* atomic primitive is meant to provide.
5444e768	13	*/
85199474	14
2a6a4076 MA	15	#ifndef QEMU_ATOMIC_H
2a6a4076 MA	16	#define QEMU_ATOMIC_H
1d31fca4	17
5444e768 PB	18	/* Compiler barrier */
	19	#define barrier() ({ asm volatile("" ::: "memory"); (void)0; })
	20
5927ed84 PB	21	/* The variable that receives the old value of an atomically-accessed
	22	* variable must be non-qualified, because atomic builtins return values
	23	* through a pointer-type argument as in __atomic_load(&var, &old, MODEL).
	24	*
	25	* This macro has to handle types smaller than int manually, because of
	26	* implicit promotion. int and larger types, as well as pointers, can be
	27	* converted to a non-qualified type just by applying a binary operator.
	28	*/
	29	#define typeof_strip_qual(expr) \
	30	typeof( \
	31	__builtin_choose_expr( \
	32	__builtin_types_compatible_p(typeof(expr), bool) \|\| \
	33	__builtin_types_compatible_p(typeof(expr), const bool) \|\| \
	34	__builtin_types_compatible_p(typeof(expr), volatile bool) \|\| \
	35	__builtin_types_compatible_p(typeof(expr), const volatile bool), \
	36	(bool)1, \
	37	__builtin_choose_expr( \
	38	__builtin_types_compatible_p(typeof(expr), signed char) \|\| \
	39	__builtin_types_compatible_p(typeof(expr), const signed char) \|\| \
	40	__builtin_types_compatible_p(typeof(expr), volatile signed char) \|\| \
	41	__builtin_types_compatible_p(typeof(expr), const volatile signed char), \
	42	(signed char)1, \
	43	__builtin_choose_expr( \
	44	__builtin_types_compatible_p(typeof(expr), unsigned char) \|\| \
	45	__builtin_types_compatible_p(typeof(expr), const unsigned char) \|\| \
	46	__builtin_types_compatible_p(typeof(expr), volatile unsigned char) \|\| \
	47	__builtin_types_compatible_p(typeof(expr), const volatile unsigned char), \
	48	(unsigned char)1, \
	49	__builtin_choose_expr( \
	50	__builtin_types_compatible_p(typeof(expr), signed short) \|\| \
	51	__builtin_types_compatible_p(typeof(expr), const signed short) \|\| \
	52	__builtin_types_compatible_p(typeof(expr), volatile signed short) \|\| \
	53	__builtin_types_compatible_p(typeof(expr), const volatile signed short), \
	54	(signed short)1, \
	55	__builtin_choose_expr( \
	56	__builtin_types_compatible_p(typeof(expr), unsigned short) \|\| \
	57	__builtin_types_compatible_p(typeof(expr), const unsigned short) \|\| \
	58	__builtin_types_compatible_p(typeof(expr), volatile unsigned short) \|\| \
	59	__builtin_types_compatible_p(typeof(expr), const volatile unsigned short), \
	60	(unsigned short)1, \
	61	(expr)+0))))))
	62
a0aa44b4 AB	63	#ifdef __ATOMIC_RELAXED
	64	/* For C11 atomic ops */
	65
	66	/* Manual memory barriers
	67	*
	68	*__atomic_thread_fence does not include a compiler barrier; instead,
	69	* the barrier is part of __atomic_load/__atomic_store's "volatile-like"
	70	* semantics. If smp_wmb() is a no-op, absence of the barrier means that
	71	* the compiler is free to reorder stores on each side of the barrier.
	72	* Add one here, and similarly in smp_rmb() and smp_read_barrier_depends().
	73	*/
	74
705ac1ca PK	75	#define smp_mb() ({ barrier(); __atomic_thread_fence(__ATOMIC_SEQ_CST); })
	76	#define smp_wmb() ({ barrier(); __atomic_thread_fence(__ATOMIC_RELEASE); })
	77	#define smp_rmb() ({ barrier(); __atomic_thread_fence(__ATOMIC_ACQUIRE); })
a0aa44b4	78
c9838952 EC	79	/* Most compilers currently treat consume and acquire the same, but really
	80	* no processors except Alpha need a barrier here. Leave it in if
	81	* using Thread Sanitizer to avoid warnings, otherwise optimize it away.
	82	*/
	83	#if defined(__SANITIZE_THREAD__)
705ac1ca	84	#define smp_read_barrier_depends() ({ barrier(); __atomic_thread_fence(__ATOMIC_CONSUME); })
23ea7f57	85	#elif defined(__alpha__)
c9838952 EC	86	#define smp_read_barrier_depends() asm volatile("mb":::"memory")
	87	#else
	88	#define smp_read_barrier_depends() barrier()
	89	#endif
	90
a0aa44b4 AB	91
	92	/* Weak atomic operations prevent the compiler moving other
	93	* loads/stores past the atomic operation load/store. However there is
	94	* no explicit memory barrier for the processor.
e653bc6b AB	95	*
	96	* The C11 memory model says that variables that are accessed from
	97	* different threads should at least be done with __ATOMIC_RELAXED
	98	* primitives or the result is undefined. Generally this has little to
	99	* no effect on the generated code but not using the atomic primitives
	100	* will get flagged by sanitizers as a violation.
a0aa44b4	101	*/
ca47a926 AB	102	#define atomic_read(ptr) \
	103	({ \
	104	QEMU_BUILD_BUG_ON(sizeof(ptr) > sizeof(void )); \
89943de1	105	__atomic_load_n(ptr, __ATOMIC_RELAXED); \
a0aa44b4 AB	106	})
a0aa44b4 AB	107
ca47a926 AB	108	#define atomic_set(ptr, i) do { \
ca47a926 AB	109	QEMU_BUILD_BUG_ON(sizeof(ptr) > sizeof(void )); \
89943de1	110	__atomic_store_n(ptr, i, __ATOMIC_RELAXED); \
a0aa44b4 AB	111	} while(0)
a0aa44b4 AB	112
15487aa1 EC	113	/* See above: most compilers currently treat consume and acquire the
	114	* same, but this slows down atomic_rcu_read unnecessarily.
	115	*/
	116	#ifdef __SANITIZE_THREAD__
	117	#define atomic_rcu_read__nocheck(ptr, valptr) \
	118	__atomic_load(ptr, valptr, __ATOMIC_CONSUME);
	119	#else
	120	#define atomic_rcu_read__nocheck(ptr, valptr) \
	121	__atomic_load(ptr, valptr, __ATOMIC_RELAXED); \
	122	smp_read_barrier_depends();
	123	#endif
a0aa44b4	124
ca47a926 AB	125	#define atomic_rcu_read(ptr) \
	126	({ \
	127	QEMU_BUILD_BUG_ON(sizeof(ptr) > sizeof(void )); \
5927ed84	128	typeof_strip_qual(*ptr) _val; \
15487aa1	129	atomic_rcu_read__nocheck(ptr, &_val); \
ca47a926	130	_val; \
a0aa44b4 AB	131	})
a0aa44b4 AB	132
ca47a926 AB	133	#define atomic_rcu_set(ptr, i) do { \
ca47a926 AB	134	QEMU_BUILD_BUG_ON(sizeof(ptr) > sizeof(void )); \
89943de1	135	__atomic_store_n(ptr, i, __ATOMIC_RELEASE); \
a0aa44b4 AB	136	} while(0)
	137
	138	/* atomic_mb_read/set semantics map Java volatile variables. They are
	139	* less expensive on some platforms (notably POWER & ARMv7) than fully
	140	* sequentially consistent operations.
	141	*
	142	* As long as they are used as paired operations they are safe to
	143	* use. See docs/atomic.txt for more discussion.
	144	*/
	145
	146	#if defined(_ARCH_PPC)
	147	#define atomic_mb_read(ptr) \
	148	({ \
ca47a926	149	QEMU_BUILD_BUG_ON(sizeof(ptr) > sizeof(void )); \
5927ed84	150	typeof_strip_qual(*ptr) _val; \
a0aa44b4 AB	151	__atomic_load(ptr, &_val, __ATOMIC_RELAXED); \
	152	smp_rmb(); \
	153	_val; \
	154	})
	155
	156	#define atomic_mb_set(ptr, i) do { \
ca47a926	157	QEMU_BUILD_BUG_ON(sizeof(ptr) > sizeof(void )); \
a0aa44b4	158	smp_wmb(); \
89943de1	159	__atomic_store_n(ptr, i, __ATOMIC_RELAXED); \
a0aa44b4 AB	160	smp_mb(); \
	161	} while(0)
	162	#else
ca47a926 AB	163	#define atomic_mb_read(ptr) \
	164	({ \
	165	QEMU_BUILD_BUG_ON(sizeof(ptr) > sizeof(void )); \
5927ed84	166	typeof_strip_qual(*ptr) _val; \
ca47a926 AB	167	__atomic_load(ptr, &_val, __ATOMIC_SEQ_CST); \
ca47a926 AB	168	_val; \
a0aa44b4 AB	169	})
a0aa44b4 AB	170
ca47a926 AB	171	#define atomic_mb_set(ptr, i) do { \
ca47a926 AB	172	QEMU_BUILD_BUG_ON(sizeof(ptr) > sizeof(void )); \
89943de1	173	__atomic_store_n(ptr, i, __ATOMIC_SEQ_CST); \
a0aa44b4 AB	174	} while(0)
	175	#endif
	176
	177
	178	/* All the remaining operations are fully sequentially consistent */
	179
	180	#define atomic_xchg(ptr, i) ({ \
ca47a926	181	QEMU_BUILD_BUG_ON(sizeof(ptr) > sizeof(void )); \
89943de1	182	__atomic_exchange_n(ptr, i, __ATOMIC_SEQ_CST); \
a0aa44b4 AB	183	})
	184
	185	/* Returns the eventual value, failed or not */
	186	#define atomic_cmpxchg(ptr, old, new) \
	187	({ \
ca47a926	188	QEMU_BUILD_BUG_ON(sizeof(ptr) > sizeof(void )); \
89943de1 PK	189	typeof_strip_qual(*ptr) _old = (old); \
89943de1 PK	190	__atomic_compare_exchange_n(ptr, &_old, new, false, \
a0aa44b4 AB	191	__ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST); \
	192	_old; \
	193	})
	194
	195	/* Provide shorter names for GCC atomic builtins, return old value */
	196	#define atomic_fetch_inc(ptr) __atomic_fetch_add(ptr, 1, __ATOMIC_SEQ_CST)
	197	#define atomic_fetch_dec(ptr) __atomic_fetch_sub(ptr, 1, __ATOMIC_SEQ_CST)
	198	#define atomic_fetch_add(ptr, n) __atomic_fetch_add(ptr, n, __ATOMIC_SEQ_CST)
	199	#define atomic_fetch_sub(ptr, n) __atomic_fetch_sub(ptr, n, __ATOMIC_SEQ_CST)
	200	#define atomic_fetch_and(ptr, n) __atomic_fetch_and(ptr, n, __ATOMIC_SEQ_CST)
	201	#define atomic_fetch_or(ptr, n) __atomic_fetch_or(ptr, n, __ATOMIC_SEQ_CST)
	202
	203	/* And even shorter names that return void. */
	204	#define atomic_inc(ptr) ((void) __atomic_fetch_add(ptr, 1, __ATOMIC_SEQ_CST))
	205	#define atomic_dec(ptr) ((void) __atomic_fetch_sub(ptr, 1, __ATOMIC_SEQ_CST))
	206	#define atomic_add(ptr, n) ((void) __atomic_fetch_add(ptr, n, __ATOMIC_SEQ_CST))
	207	#define atomic_sub(ptr, n) ((void) __atomic_fetch_sub(ptr, n, __ATOMIC_SEQ_CST))
	208	#define atomic_and(ptr, n) ((void) __atomic_fetch_and(ptr, n, __ATOMIC_SEQ_CST))
	209	#define atomic_or(ptr, n) ((void) __atomic_fetch_or(ptr, n, __ATOMIC_SEQ_CST))
	210
	211	#else /* __ATOMIC_RELAXED */
52e850de	212
a281ebc1	213	/*
5444e768 PB	214	* We use GCC builtin if it's available, as that can use mfence on
	215	* 32-bit as well, e.g. if built with -march=pentium-m. However, on
	216	* i386 the spec is buggy, and the implementation followed it until
	217	* 4.3 (http://gcc.gnu.org/bugzilla/show_bug.cgi?id=36793).
	218	*/
	219	#if defined(__i386__) \|\| defined(__x86_64__)
	220	#if !QEMU_GNUC_PREREQ(4, 4)
	221	#if defined __x86_64__
	222	#define smp_mb() ({ asm volatile("mfence" ::: "memory"); (void)0; })
a281ebc1	223	#else
5444e768 PB	224	#define smp_mb() ({ asm volatile("lock; addl $0,0(%%esp) " ::: "memory"); (void)0; })
	225	#endif
	226	#endif
	227	#endif
	228
	229
	230	#ifdef __alpha__
	231	#define smp_read_barrier_depends() asm volatile("mb":::"memory")
a281ebc1 MT	232	#endif
a281ebc1 MT	233
5444e768	234	#if defined(__i386__) \|\| defined(__x86_64__) \|\| defined(__s390x__)
a281ebc1	235
5444e768 PB	236	/*
	237	* Because of the strongly ordered storage model, wmb() and rmb() are nops
	238	* here (a compiler barrier only). QEMU doesn't do accesses to write-combining
	239	* qemu memory or non-temporal load/stores from C code.
	240	*/
a281ebc1	241	#define smp_wmb() barrier()
a821ce59	242	#define smp_rmb() barrier()
5444e768 PB	243
	244	/*
	245	* __sync_lock_test_and_set() is documented to be an acquire barrier only,
	246	* but it is a full barrier at the hardware level. Add a compiler barrier
	247	* to make it a full barrier also at the compiler level.
	248	*/
	249	#define atomic_xchg(ptr, i) (barrier(), __sync_lock_test_and_set(ptr, i))
	250
	251	/*
	252	* Load/store with Java volatile semantics.
	253	*/
	254	#define atomic_mb_set(ptr, i) ((void)atomic_xchg(ptr, i))
e2251708	255
463ce4ae	256	#elif defined(_ARCH_PPC)
e2251708 DG	257
e2251708 DG	258	/*
a281ebc1	259	* We use an eieio() for wmb() on powerpc. This assumes we don't
e2251708	260	* need to order cacheable and non-cacheable stores with respect to
5444e768 PB	261	* each other.
	262	*
	263	* smp_mb has the same problem as on x86 for not-very-new GCC
	264	* (http://patchwork.ozlabs.org/patch/126184/, Nov 2011).
e2251708	265	*/
5444e768	266	#define smp_wmb() ({ asm volatile("eieio" ::: "memory"); (void)0; })
a821ce59	267	#if defined(__powerpc64__)
5444e768	268	#define smp_rmb() ({ asm volatile("lwsync" ::: "memory"); (void)0; })
a821ce59	269	#else
5444e768	270	#define smp_rmb() ({ asm volatile("sync" ::: "memory"); (void)0; })
a821ce59	271	#endif
5444e768	272	#define smp_mb() ({ asm volatile("sync" ::: "memory"); (void)0; })
a821ce59	273
5444e768	274	#endif /* _ARCH_PPC */
e2251708	275
e2251708 DG	276	/*
	277	* For (host) platforms we don't have explicit barrier definitions
	278	* for, we use the gcc __sync_synchronize() primitive to generate a
	279	* full barrier. This should be safe on all platforms, though it may
5444e768	280	* be overkill for smp_wmb() and smp_rmb().
e2251708	281	*/
5444e768 PB	282	#ifndef smp_mb
	283	#define smp_mb() __sync_synchronize()
	284	#endif
	285
	286	#ifndef smp_wmb
e2251708	287	#define smp_wmb() __sync_synchronize()
5444e768	288	#endif
5444e768 PB	289
5444e768 PB	290	#ifndef smp_rmb
a821ce59	291	#define smp_rmb() __sync_synchronize()
5444e768	292	#endif
5444e768 PB	293
5444e768 PB	294	#ifndef smp_read_barrier_depends
5444e768 PB	295	#define smp_read_barrier_depends() barrier()
5444e768 PB	296	#endif
e2251708	297
a0aa44b4 AB	298	/* These will only be atomic if the processor does the fetch or store
	299	* in a single issue memory operation
	300	*/
2cbcfb28	301	#define atomic_read(ptr) ((__typeof__(ptr) volatile*) (ptr))
2cbcfb28	302	#define atomic_set(ptr, i) (((__typeof__(ptr) volatile*) (ptr)) = (i))
5444e768	303
7911747b PB	304	/**
	305	* atomic_rcu_read - reads a RCU-protected pointer to a local variable
	306	* into a RCU read-side critical section. The pointer can later be safely
	307	* dereferenced within the critical section.
	308	*
	309	* This ensures that the pointer copy is invariant thorough the whole critical
	310	* section.
	311	*
	312	* Inserts memory barriers on architectures that require them (currently only
	313	* Alpha) and documents which pointers are protected by RCU.
	314	*
a0aa44b4 AB	315	* atomic_rcu_read also includes a compiler barrier to ensure that
	316	* value-speculative optimizations (e.g. VSS: Value Speculation
	317	* Scheduling) does not perform the data read before the pointer read
	318	* by speculating the value of the pointer.
7911747b PB	319	*
	320	* Should match atomic_rcu_set(), atomic_xchg(), atomic_cmpxchg().
	321	*/
7911747b PB	322	#define atomic_rcu_read(ptr) ({ \
	323	typeof(*ptr) _val = atomic_read(ptr); \
	324	smp_read_barrier_depends(); \
	325	_val; \
	326	})
7911747b PB	327
	328	/**
	329	* atomic_rcu_set - assigns (publicizes) a pointer to a new data structure
	330	* meant to be read by RCU read-side critical sections.
	331	*
	332	* Documents which pointers will be dereferenced by RCU read-side critical
	333	* sections and adds the required memory barriers on architectures requiring
	334	* them. It also makes sure the compiler does not reorder code initializing the
	335	* data structure before its publication.
	336	*
	337	* Should match atomic_rcu_read().
	338	*/
7911747b PB	339	#define atomic_rcu_set(ptr, i) do { \
	340	smp_wmb(); \
	341	atomic_set(ptr, i); \
	342	} while (0)
7911747b	343
5444e768 PB	344	/* These have the same semantics as Java volatile variables.
	345	* See http://gee.cs.oswego.edu/dl/jmm/cookbook.html:
	346	* "1. Issue a StoreStore barrier (wmb) before each volatile store."
	347	* 2. Issue a StoreLoad barrier after each volatile store.
	348	* Note that you could instead issue one before each volatile load, but
	349	* this would be slower for typical programs using volatiles in which
	350	* reads greatly outnumber writes. Alternatively, if available, you
	351	* can implement volatile store as an atomic instruction (for example
	352	* XCHG on x86) and omit the barrier. This may be more efficient if
	353	* atomic instructions are cheaper than StoreLoad barriers.
	354	* 3. Issue LoadLoad and LoadStore barriers after each volatile load."
	355	*
	356	* If you prefer to think in terms of "pairing" of memory barriers,
	357	* an atomic_mb_read pairs with an atomic_mb_set.
	358	*
	359	* And for the few ia64 lovers that exist, an atomic_mb_read is a ld.acq,
	360	* while an atomic_mb_set is a st.rel followed by a memory barrier.
	361	*
	362	* These are a bit weaker than __atomic_load/store with __ATOMIC_SEQ_CST
	363	* (see docs/atomics.txt), and I'm not sure that __ATOMIC_ACQ_REL is enough.
	364	* Just always use the barriers manually by the rules above.
	365	*/
5444e768 PB	366	#define atomic_mb_read(ptr) ({ \
	367	typeof(*ptr) _val = atomic_read(ptr); \
	368	smp_rmb(); \
	369	_val; \
	370	})
5444e768 PB	371
	372	#ifndef atomic_mb_set
	373	#define atomic_mb_set(ptr, i) do { \
	374	smp_wmb(); \
	375	atomic_set(ptr, i); \
	376	smp_mb(); \
	377	} while (0)
	378	#endif
	379
	380	#ifndef atomic_xchg
33effd3a PM	381	#if defined(__clang__)
33effd3a PM	382	#define atomic_xchg(ptr, i) __sync_swap(ptr, i)
5444e768 PB	383	#else
	384	/* __sync_lock_test_and_set() is documented to be an acquire barrier only. */
	385	#define atomic_xchg(ptr, i) (smp_mb(), __sync_lock_test_and_set(ptr, i))
	386	#endif
	387	#endif
	388
	389	/* Provide shorter names for GCC atomic builtins. */
	390	#define atomic_fetch_inc(ptr) __sync_fetch_and_add(ptr, 1)
	391	#define atomic_fetch_dec(ptr) __sync_fetch_and_add(ptr, -1)
	392	#define atomic_fetch_add __sync_fetch_and_add
	393	#define atomic_fetch_sub __sync_fetch_and_sub
	394	#define atomic_fetch_and __sync_fetch_and_and
	395	#define atomic_fetch_or __sync_fetch_and_or
	396	#define atomic_cmpxchg __sync_val_compare_and_swap
	397
	398	/* And even shorter names that return void. */
	399	#define atomic_inc(ptr) ((void) __sync_fetch_and_add(ptr, 1))
	400	#define atomic_dec(ptr) ((void) __sync_fetch_and_add(ptr, -1))
	401	#define atomic_add(ptr, n) ((void) __sync_fetch_and_add(ptr, n))
	402	#define atomic_sub(ptr, n) ((void) __sync_fetch_and_sub(ptr, n))
	403	#define atomic_and(ptr, n) ((void) __sync_fetch_and_and(ptr, n))
	404	#define atomic_or(ptr, n) ((void) __sync_fetch_and_or(ptr, n))
	405
a0aa44b4	406	#endif /* __ATOMIC_RELAXED */
2a6a4076	407	#endif /* QEMU_ATOMIC_H */