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dd83b06a AF |
1 | /* |
2 | * QEMU CPU model | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | #ifndef QEMU_CPU_H | |
21 | #define QEMU_CPU_H | |
22 | ||
961f8395 | 23 | #include "hw/qdev-core.h" |
37b9de46 | 24 | #include "disas/bfd.h" |
c658b94f | 25 | #include "exec/hwaddr.h" |
66b9b43c | 26 | #include "exec/memattrs.h" |
48151859 | 27 | #include "qemu/bitmap.h" |
bdc44640 | 28 | #include "qemu/queue.h" |
1de7afc9 | 29 | #include "qemu/thread.h" |
dd83b06a | 30 | |
b5ba1cc6 QN |
31 | typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size, |
32 | void *opaque); | |
c72bf468 | 33 | |
577f42c0 AF |
34 | /** |
35 | * vaddr: | |
36 | * Type wide enough to contain any #target_ulong virtual address. | |
37 | */ | |
38 | typedef uint64_t vaddr; | |
39 | #define VADDR_PRId PRId64 | |
40 | #define VADDR_PRIu PRIu64 | |
41 | #define VADDR_PRIo PRIo64 | |
42 | #define VADDR_PRIx PRIx64 | |
43 | #define VADDR_PRIX PRIX64 | |
44 | #define VADDR_MAX UINT64_MAX | |
45 | ||
dd83b06a AF |
46 | /** |
47 | * SECTION:cpu | |
48 | * @section_id: QEMU-cpu | |
49 | * @title: CPU Class | |
50 | * @short_description: Base class for all CPUs | |
51 | */ | |
52 | ||
53 | #define TYPE_CPU "cpu" | |
54 | ||
0d6d1ab4 AF |
55 | /* Since this macro is used a lot in hot code paths and in conjunction with |
56 | * FooCPU *foo_env_get_cpu(), we deviate from usual QOM practice by using | |
57 | * an unchecked cast. | |
58 | */ | |
59 | #define CPU(obj) ((CPUState *)(obj)) | |
60 | ||
dd83b06a AF |
61 | #define CPU_CLASS(class) OBJECT_CLASS_CHECK(CPUClass, (class), TYPE_CPU) |
62 | #define CPU_GET_CLASS(obj) OBJECT_GET_CLASS(CPUClass, (obj), TYPE_CPU) | |
63 | ||
b35399bb SS |
64 | typedef enum MMUAccessType { |
65 | MMU_DATA_LOAD = 0, | |
66 | MMU_DATA_STORE = 1, | |
67 | MMU_INST_FETCH = 2 | |
68 | } MMUAccessType; | |
69 | ||
568496c0 | 70 | typedef struct CPUWatchpoint CPUWatchpoint; |
dd83b06a | 71 | |
c658b94f AF |
72 | typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr, |
73 | bool is_write, bool is_exec, int opaque, | |
74 | unsigned size); | |
75 | ||
bdf7ae5b AF |
76 | struct TranslationBlock; |
77 | ||
dd83b06a AF |
78 | /** |
79 | * CPUClass: | |
2b8c2754 AF |
80 | * @class_by_name: Callback to map -cpu command line model name to an |
81 | * instantiatable CPU type. | |
94a444b2 | 82 | * @parse_features: Callback to parse command line arguments. |
f5df5baf | 83 | * @reset: Callback to reset the #CPUState to its initial state. |
91b1df8c | 84 | * @reset_dump_flags: #CPUDumpFlags to use for reset logging. |
8c2e1b00 | 85 | * @has_work: Callback for checking if there is work to do. |
97a8ea5a | 86 | * @do_interrupt: Callback for interrupt handling. |
c658b94f | 87 | * @do_unassigned_access: Callback for unassigned access handling. |
0dff0939 | 88 | * (this is deprecated: new targets should use do_transaction_failed instead) |
93e22326 PB |
89 | * @do_unaligned_access: Callback for unaligned access handling, if |
90 | * the target defines #ALIGNED_ONLY. | |
0dff0939 PM |
91 | * @do_transaction_failed: Callback for handling failed memory transactions |
92 | * (ie bus faults or external aborts; not MMU faults) | |
c08295d4 PM |
93 | * @virtio_is_big_endian: Callback to return %true if a CPU which supports |
94 | * runtime configurable endianness is currently big-endian. Non-configurable | |
95 | * CPUs can use the default implementation of this method. This method should | |
96 | * not be used by any callers other than the pre-1.0 virtio devices. | |
f3659eee | 97 | * @memory_rw_debug: Callback for GDB memory access. |
878096ee AF |
98 | * @dump_state: Callback for dumping state. |
99 | * @dump_statistics: Callback for dumping statistics. | |
997395d3 | 100 | * @get_arch_id: Callback for getting architecture-dependent CPU ID. |
444d5590 | 101 | * @get_paging_enabled: Callback for inquiring whether paging is enabled. |
a23bbfda | 102 | * @get_memory_mapping: Callback for obtaining the memory mappings. |
f45748f1 | 103 | * @set_pc: Callback for setting the Program Counter register. |
bdf7ae5b AF |
104 | * @synchronize_from_tb: Callback for synchronizing state from a TCG |
105 | * #TranslationBlock. | |
7510454e | 106 | * @handle_mmu_fault: Callback for handling an MMU fault. |
00b941e5 | 107 | * @get_phys_page_debug: Callback for obtaining a physical address. |
1dc6fb1f PM |
108 | * @get_phys_page_attrs_debug: Callback for obtaining a physical address and the |
109 | * associated memory transaction attributes to use for the access. | |
110 | * CPUs which use memory transaction attributes should implement this | |
111 | * instead of get_phys_page_debug. | |
d7f25a9e PM |
112 | * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for |
113 | * a memory access with the specified memory transaction attributes. | |
5b50e790 AF |
114 | * @gdb_read_register: Callback for letting GDB read a register. |
115 | * @gdb_write_register: Callback for letting GDB write a register. | |
568496c0 SF |
116 | * @debug_check_watchpoint: Callback: return true if the architectural |
117 | * watchpoint whose address has matched should really fire. | |
86025ee4 | 118 | * @debug_excp_handler: Callback for handling debug exceptions. |
c08295d4 PM |
119 | * @write_elf64_note: Callback for writing a CPU-specific ELF note to a |
120 | * 64-bit VM coredump. | |
121 | * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF | |
122 | * note to a 32-bit VM coredump. | |
123 | * @write_elf32_note: Callback for writing a CPU-specific ELF note to a | |
124 | * 32-bit VM coredump. | |
125 | * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF | |
126 | * note to a 32-bit VM coredump. | |
b170fce3 | 127 | * @vmsd: State description for migration. |
a0e372f0 | 128 | * @gdb_num_core_regs: Number of core registers accessible to GDB. |
5b24c641 | 129 | * @gdb_core_xml_file: File name for core registers GDB XML description. |
2472b6c0 PM |
130 | * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop |
131 | * before the insn which triggers a watchpoint rather than after it. | |
b3820e6c DH |
132 | * @gdb_arch_name: Optional callback that returns the architecture name known |
133 | * to GDB. The caller must free the returned string with g_free. | |
cffe7b32 RH |
134 | * @cpu_exec_enter: Callback for cpu_exec preparation. |
135 | * @cpu_exec_exit: Callback for cpu_exec cleanup. | |
9585db68 | 136 | * @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec. |
37b9de46 | 137 | * @disas_set_info: Setup architecture specific components of disassembly info |
40612000 JB |
138 | * @adjust_watchpoint_address: Perform a target-specific adjustment to an |
139 | * address before attempting to match it against watchpoints. | |
dd83b06a AF |
140 | * |
141 | * Represents a CPU family or model. | |
142 | */ | |
143 | typedef struct CPUClass { | |
144 | /*< private >*/ | |
961f8395 | 145 | DeviceClass parent_class; |
dd83b06a AF |
146 | /*< public >*/ |
147 | ||
2b8c2754 | 148 | ObjectClass *(*class_by_name)(const char *cpu_model); |
62a48a2a | 149 | void (*parse_features)(const char *typename, char *str, Error **errp); |
2b8c2754 | 150 | |
dd83b06a | 151 | void (*reset)(CPUState *cpu); |
91b1df8c | 152 | int reset_dump_flags; |
8c2e1b00 | 153 | bool (*has_work)(CPUState *cpu); |
97a8ea5a | 154 | void (*do_interrupt)(CPUState *cpu); |
c658b94f | 155 | CPUUnassignedAccess do_unassigned_access; |
93e22326 | 156 | void (*do_unaligned_access)(CPUState *cpu, vaddr addr, |
b35399bb SS |
157 | MMUAccessType access_type, |
158 | int mmu_idx, uintptr_t retaddr); | |
0dff0939 PM |
159 | void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr, |
160 | unsigned size, MMUAccessType access_type, | |
161 | int mmu_idx, MemTxAttrs attrs, | |
162 | MemTxResult response, uintptr_t retaddr); | |
bf7663c4 | 163 | bool (*virtio_is_big_endian)(CPUState *cpu); |
f3659eee AF |
164 | int (*memory_rw_debug)(CPUState *cpu, vaddr addr, |
165 | uint8_t *buf, int len, bool is_write); | |
878096ee AF |
166 | void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, |
167 | int flags); | |
c86f106b | 168 | GuestPanicInformation* (*get_crash_info)(CPUState *cpu); |
878096ee AF |
169 | void (*dump_statistics)(CPUState *cpu, FILE *f, |
170 | fprintf_function cpu_fprintf, int flags); | |
997395d3 | 171 | int64_t (*get_arch_id)(CPUState *cpu); |
444d5590 | 172 | bool (*get_paging_enabled)(const CPUState *cpu); |
a23bbfda AF |
173 | void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, |
174 | Error **errp); | |
f45748f1 | 175 | void (*set_pc)(CPUState *cpu, vaddr value); |
bdf7ae5b | 176 | void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb); |
7510454e AF |
177 | int (*handle_mmu_fault)(CPUState *cpu, vaddr address, int rw, |
178 | int mmu_index); | |
00b941e5 | 179 | hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); |
1dc6fb1f PM |
180 | hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, |
181 | MemTxAttrs *attrs); | |
d7f25a9e | 182 | int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs); |
5b50e790 AF |
183 | int (*gdb_read_register)(CPUState *cpu, uint8_t *buf, int reg); |
184 | int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); | |
568496c0 | 185 | bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp); |
86025ee4 | 186 | void (*debug_excp_handler)(CPUState *cpu); |
b170fce3 | 187 | |
c72bf468 JF |
188 | int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu, |
189 | int cpuid, void *opaque); | |
190 | int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, | |
191 | void *opaque); | |
192 | int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu, | |
193 | int cpuid, void *opaque); | |
194 | int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, | |
195 | void *opaque); | |
a0e372f0 AF |
196 | |
197 | const struct VMStateDescription *vmsd; | |
198 | int gdb_num_core_regs; | |
5b24c641 | 199 | const char *gdb_core_xml_file; |
b3820e6c | 200 | gchar * (*gdb_arch_name)(CPUState *cpu); |
2472b6c0 | 201 | bool gdb_stop_before_watchpoint; |
cffe7b32 RH |
202 | |
203 | void (*cpu_exec_enter)(CPUState *cpu); | |
204 | void (*cpu_exec_exit)(CPUState *cpu); | |
9585db68 | 205 | bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); |
37b9de46 PC |
206 | |
207 | void (*disas_set_info)(CPUState *cpu, disassemble_info *info); | |
40612000 | 208 | vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len); |
dd83b06a AF |
209 | } CPUClass; |
210 | ||
28ecfd7a AF |
211 | #ifdef HOST_WORDS_BIGENDIAN |
212 | typedef struct icount_decr_u16 { | |
213 | uint16_t high; | |
214 | uint16_t low; | |
215 | } icount_decr_u16; | |
216 | #else | |
217 | typedef struct icount_decr_u16 { | |
218 | uint16_t low; | |
219 | uint16_t high; | |
220 | } icount_decr_u16; | |
221 | #endif | |
222 | ||
f0c3c505 AF |
223 | typedef struct CPUBreakpoint { |
224 | vaddr pc; | |
225 | int flags; /* BP_* */ | |
226 | QTAILQ_ENTRY(CPUBreakpoint) entry; | |
227 | } CPUBreakpoint; | |
228 | ||
568496c0 | 229 | struct CPUWatchpoint { |
ff4700b0 | 230 | vaddr vaddr; |
05068c0d | 231 | vaddr len; |
08225676 | 232 | vaddr hitaddr; |
66b9b43c | 233 | MemTxAttrs hitattrs; |
ff4700b0 AF |
234 | int flags; /* BP_* */ |
235 | QTAILQ_ENTRY(CPUWatchpoint) entry; | |
568496c0 | 236 | }; |
ff4700b0 | 237 | |
a60f24b5 | 238 | struct KVMState; |
f7575c96 | 239 | struct kvm_run; |
a60f24b5 | 240 | |
b0cb0a66 VP |
241 | struct hax_vcpu_state; |
242 | ||
8cd70437 AF |
243 | #define TB_JMP_CACHE_BITS 12 |
244 | #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) | |
245 | ||
4b4629d9 | 246 | /* work queue */ |
14e6fe12 PB |
247 | |
248 | /* The union type allows passing of 64 bit target pointers on 32 bit | |
249 | * hosts in a single parameter | |
250 | */ | |
251 | typedef union { | |
252 | int host_int; | |
253 | unsigned long host_ulong; | |
254 | void *host_ptr; | |
255 | vaddr target_ptr; | |
256 | } run_on_cpu_data; | |
257 | ||
258 | #define RUN_ON_CPU_HOST_PTR(p) ((run_on_cpu_data){.host_ptr = (p)}) | |
259 | #define RUN_ON_CPU_HOST_INT(i) ((run_on_cpu_data){.host_int = (i)}) | |
260 | #define RUN_ON_CPU_HOST_ULONG(ul) ((run_on_cpu_data){.host_ulong = (ul)}) | |
261 | #define RUN_ON_CPU_TARGET_PTR(v) ((run_on_cpu_data){.target_ptr = (v)}) | |
262 | #define RUN_ON_CPU_NULL RUN_ON_CPU_HOST_PTR(NULL) | |
263 | ||
264 | typedef void (*run_on_cpu_func)(CPUState *cpu, run_on_cpu_data data); | |
265 | ||
d148d90e | 266 | struct qemu_work_item; |
4b4629d9 | 267 | |
0b8497f0 | 268 | #define CPU_UNSET_NUMA_NODE_ID -1 |
d01c05c9 | 269 | #define CPU_TRACE_DSTATE_MAX_EVENTS 32 |
0b8497f0 | 270 | |
dd83b06a AF |
271 | /** |
272 | * CPUState: | |
55e5c285 | 273 | * @cpu_index: CPU index (informative). |
ce3960eb AF |
274 | * @nr_cores: Number of cores within this CPU package. |
275 | * @nr_threads: Number of threads within this CPU. | |
c265e976 PB |
276 | * @running: #true if CPU is currently running (lockless). |
277 | * @has_waiter: #true if a CPU is currently waiting for the cpu_exec_end; | |
ab129972 | 278 | * valid under cpu_list_lock. |
61a46217 | 279 | * @created: Indicates whether the CPU thread has been successfully created. |
259186a7 AF |
280 | * @interrupt_request: Indicates a pending interrupt request. |
281 | * @halted: Nonzero if the CPU is in suspended state. | |
4fdeee7c | 282 | * @stop: Indicates a pending stop request. |
f324e766 | 283 | * @stopped: Indicates the CPU has been artificially stopped. |
4c055ab5 | 284 | * @unplug: Indicates a pending CPU unplug request. |
bac05aa9 | 285 | * @crash_occurred: Indicates the OS reported a crash (panic) for this CPU |
ed2803da | 286 | * @singlestep_enabled: Flags for single-stepping. |
efee7340 | 287 | * @icount_extra: Instructions until next timer event. |
1aab16c2 PB |
288 | * @icount_decr: Low 16 bits: number of cycles left, only used in icount mode. |
289 | * High 16 bits: Set to -1 to force TCG to stop executing linked TBs for this | |
290 | * CPU and return to its top level loop (even in non-icount mode). | |
28ecfd7a AF |
291 | * This allows a single read-compare-cbranch-write sequence to test |
292 | * for both decrementer underflow and exceptions. | |
414b15c9 PB |
293 | * @can_do_io: Nonzero if memory-mapped IO is safe. Deterministic execution |
294 | * requires that IO only be performed on the last instruction of a TB | |
295 | * so that interrupts take effect immediately. | |
32857f4d PM |
296 | * @cpu_ases: Pointer to array of CPUAddressSpaces (which define the |
297 | * AddressSpaces this CPU has) | |
12ebc9a7 | 298 | * @num_ases: number of CPUAddressSpaces in @cpu_ases |
32857f4d PM |
299 | * @as: Pointer to the first AddressSpace, for the convenience of targets which |
300 | * only have a single AddressSpace | |
c05efcb1 | 301 | * @env_ptr: Pointer to subclass-specific CPUArchState field. |
eac8b355 | 302 | * @gdb_regs: Additional GDB registers. |
a0e372f0 | 303 | * @gdb_num_regs: Number of total registers accessible to GDB. |
35143f01 | 304 | * @gdb_num_g_regs: Number of registers in GDB 'g' packets. |
182735ef | 305 | * @next_cpu: Next CPU sharing TB cache. |
0429a971 | 306 | * @opaque: User data. |
93afeade AF |
307 | * @mem_io_pc: Host Program Counter at which the memory was accessed. |
308 | * @mem_io_vaddr: Target virtual address at which the memory was accessed. | |
8737c51c | 309 | * @kvm_fd: vCPU file descriptor for KVM. |
376692b9 PB |
310 | * @work_mutex: Lock to prevent multiple access to queued_work_*. |
311 | * @queued_work_first: First asynchronous work pending. | |
d4381116 LV |
312 | * @trace_dstate_delayed: Delayed changes to trace_dstate (includes all changes |
313 | * to @trace_dstate). | |
48151859 | 314 | * @trace_dstate: Dynamic tracing state of events for this vCPU (bitmask). |
ed860129 PM |
315 | * @ignore_memory_transaction_failures: Cached copy of the MachineState |
316 | * flag of the same name: allows the board to suppress calling of the | |
317 | * CPU do_transaction_failed hook function. | |
dd83b06a AF |
318 | * |
319 | * State of one CPU core or thread. | |
320 | */ | |
321 | struct CPUState { | |
322 | /*< private >*/ | |
961f8395 | 323 | DeviceState parent_obj; |
dd83b06a AF |
324 | /*< public >*/ |
325 | ||
ce3960eb AF |
326 | int nr_cores; |
327 | int nr_threads; | |
328 | ||
814e612e | 329 | struct QemuThread *thread; |
bcba2a72 AF |
330 | #ifdef _WIN32 |
331 | HANDLE hThread; | |
332 | #endif | |
9f09e18a | 333 | int thread_id; |
c265e976 | 334 | bool running, has_waiter; |
f5c121b8 | 335 | struct QemuCond *halt_cond; |
216fc9a4 | 336 | bool thread_kicked; |
61a46217 | 337 | bool created; |
4fdeee7c | 338 | bool stop; |
f324e766 | 339 | bool stopped; |
4c055ab5 | 340 | bool unplug; |
bac05aa9 | 341 | bool crash_occurred; |
e0c38211 | 342 | bool exit_request; |
8d04fb55 | 343 | /* updates protected by BQL */ |
259186a7 | 344 | uint32_t interrupt_request; |
ed2803da | 345 | int singlestep_enabled; |
e4cd9657 | 346 | int64_t icount_budget; |
efee7340 | 347 | int64_t icount_extra; |
6f03bef0 | 348 | sigjmp_buf jmp_env; |
bcba2a72 | 349 | |
376692b9 PB |
350 | QemuMutex work_mutex; |
351 | struct qemu_work_item *queued_work_first, *queued_work_last; | |
352 | ||
32857f4d | 353 | CPUAddressSpace *cpu_ases; |
12ebc9a7 | 354 | int num_ases; |
09daed84 | 355 | AddressSpace *as; |
6731d864 | 356 | MemoryRegion *memory; |
09daed84 | 357 | |
c05efcb1 | 358 | void *env_ptr; /* CPUArchState */ |
7d7500d9 | 359 | |
f3ced3c5 | 360 | /* Accessed in parallel; all accesses must be atomic */ |
8cd70437 | 361 | struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; |
7d7500d9 | 362 | |
eac8b355 | 363 | struct GDBRegisterState *gdb_regs; |
a0e372f0 | 364 | int gdb_num_regs; |
35143f01 | 365 | int gdb_num_g_regs; |
bdc44640 | 366 | QTAILQ_ENTRY(CPUState) node; |
d77953b9 | 367 | |
f0c3c505 AF |
368 | /* ice debug support */ |
369 | QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; | |
370 | ||
ff4700b0 AF |
371 | QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; |
372 | CPUWatchpoint *watchpoint_hit; | |
373 | ||
0429a971 AF |
374 | void *opaque; |
375 | ||
93afeade AF |
376 | /* In order to avoid passing too many arguments to the MMIO helpers, |
377 | * we store some rarely used information in the CPU context. | |
378 | */ | |
379 | uintptr_t mem_io_pc; | |
380 | vaddr mem_io_vaddr; | |
381 | ||
8737c51c | 382 | int kvm_fd; |
a60f24b5 | 383 | struct KVMState *kvm_state; |
f7575c96 | 384 | struct kvm_run *kvm_run; |
8737c51c | 385 | |
d01c05c9 | 386 | /* Used for events with 'vcpu' and *without* the 'disabled' properties */ |
d4381116 | 387 | DECLARE_BITMAP(trace_dstate_delayed, CPU_TRACE_DSTATE_MAX_EVENTS); |
d01c05c9 | 388 | DECLARE_BITMAP(trace_dstate, CPU_TRACE_DSTATE_MAX_EVENTS); |
48151859 | 389 | |
f5df5baf | 390 | /* TODO Move common fields from CPUArchState here. */ |
6fda014e DH |
391 | int cpu_index; |
392 | uint32_t halted; | |
99df7dce | 393 | uint32_t can_do_io; |
6fda014e | 394 | int32_t exception_index; |
7e4fb26d | 395 | |
99f31832 SAGDR |
396 | /* shared by kvm, hax and hvf */ |
397 | bool vcpu_dirty; | |
398 | ||
2adcc85d JH |
399 | /* Used to keep track of an outstanding cpu throttle thread for migration |
400 | * autoconverge | |
401 | */ | |
402 | bool throttle_thread_scheduled; | |
403 | ||
ed860129 PM |
404 | bool ignore_memory_transaction_failures; |
405 | ||
7e4fb26d RH |
406 | /* Note that this is accessed at the start of every TB via a negative |
407 | offset from AREG0. Leave this field at the end so as to make the | |
408 | (absolute value) offset as small as possible. This reduces code | |
409 | size, especially for hosts without large memory offsets. */ | |
1aab16c2 PB |
410 | union { |
411 | uint32_t u32; | |
412 | icount_decr_u16 u16; | |
413 | } icount_decr; | |
b0cb0a66 | 414 | |
b0cb0a66 | 415 | struct hax_vcpu_state *hax_vcpu; |
e3b9ca81 FK |
416 | |
417 | /* The pending_tlb_flush flag is set and cleared atomically to | |
418 | * avoid potential races. The aim of the flag is to avoid | |
419 | * unnecessary flushes. | |
420 | */ | |
e7218445 | 421 | uint16_t pending_tlb_flush; |
dd83b06a AF |
422 | }; |
423 | ||
bdc44640 AF |
424 | QTAILQ_HEAD(CPUTailQ, CPUState); |
425 | extern struct CPUTailQ cpus; | |
426 | #define CPU_NEXT(cpu) QTAILQ_NEXT(cpu, node) | |
427 | #define CPU_FOREACH(cpu) QTAILQ_FOREACH(cpu, &cpus, node) | |
428 | #define CPU_FOREACH_SAFE(cpu, next_cpu) \ | |
429 | QTAILQ_FOREACH_SAFE(cpu, &cpus, node, next_cpu) | |
8487d123 BR |
430 | #define CPU_FOREACH_REVERSE(cpu) \ |
431 | QTAILQ_FOREACH_REVERSE(cpu, &cpus, CPUTailQ, node) | |
bdc44640 | 432 | #define first_cpu QTAILQ_FIRST(&cpus) |
182735ef | 433 | |
f240eb6f | 434 | extern __thread CPUState *current_cpu; |
4917cf44 | 435 | |
f3ced3c5 EC |
436 | static inline void cpu_tb_jmp_cache_clear(CPUState *cpu) |
437 | { | |
438 | unsigned int i; | |
439 | ||
440 | for (i = 0; i < TB_JMP_CACHE_SIZE; i++) { | |
441 | atomic_set(&cpu->tb_jmp_cache[i], NULL); | |
442 | } | |
443 | } | |
444 | ||
8d4e9146 FK |
445 | /** |
446 | * qemu_tcg_mttcg_enabled: | |
447 | * Check whether we are running MultiThread TCG or not. | |
448 | * | |
449 | * Returns: %true if we are in MTTCG mode %false otherwise. | |
450 | */ | |
451 | extern bool mttcg_enabled; | |
452 | #define qemu_tcg_mttcg_enabled() (mttcg_enabled) | |
453 | ||
444d5590 AF |
454 | /** |
455 | * cpu_paging_enabled: | |
456 | * @cpu: The CPU whose state is to be inspected. | |
457 | * | |
458 | * Returns: %true if paging is enabled, %false otherwise. | |
459 | */ | |
460 | bool cpu_paging_enabled(const CPUState *cpu); | |
461 | ||
a23bbfda AF |
462 | /** |
463 | * cpu_get_memory_mapping: | |
464 | * @cpu: The CPU whose memory mappings are to be obtained. | |
465 | * @list: Where to write the memory mappings to. | |
466 | * @errp: Pointer for reporting an #Error. | |
467 | */ | |
468 | void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, | |
469 | Error **errp); | |
470 | ||
c72bf468 JF |
471 | /** |
472 | * cpu_write_elf64_note: | |
473 | * @f: pointer to a function that writes memory to a file | |
474 | * @cpu: The CPU whose memory is to be dumped | |
475 | * @cpuid: ID number of the CPU | |
476 | * @opaque: pointer to the CPUState struct | |
477 | */ | |
478 | int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, | |
479 | int cpuid, void *opaque); | |
480 | ||
481 | /** | |
482 | * cpu_write_elf64_qemunote: | |
483 | * @f: pointer to a function that writes memory to a file | |
484 | * @cpu: The CPU whose memory is to be dumped | |
485 | * @cpuid: ID number of the CPU | |
486 | * @opaque: pointer to the CPUState struct | |
487 | */ | |
488 | int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
489 | void *opaque); | |
490 | ||
491 | /** | |
492 | * cpu_write_elf32_note: | |
493 | * @f: pointer to a function that writes memory to a file | |
494 | * @cpu: The CPU whose memory is to be dumped | |
495 | * @cpuid: ID number of the CPU | |
496 | * @opaque: pointer to the CPUState struct | |
497 | */ | |
498 | int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, | |
499 | int cpuid, void *opaque); | |
500 | ||
501 | /** | |
502 | * cpu_write_elf32_qemunote: | |
503 | * @f: pointer to a function that writes memory to a file | |
504 | * @cpu: The CPU whose memory is to be dumped | |
505 | * @cpuid: ID number of the CPU | |
506 | * @opaque: pointer to the CPUState struct | |
507 | */ | |
508 | int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
509 | void *opaque); | |
dd83b06a | 510 | |
c86f106b AN |
511 | /** |
512 | * cpu_get_crash_info: | |
513 | * @cpu: The CPU to get crash information for | |
514 | * | |
515 | * Gets the previously saved crash information. | |
516 | * Caller is responsible for freeing the data. | |
517 | */ | |
518 | GuestPanicInformation *cpu_get_crash_info(CPUState *cpu); | |
519 | ||
878096ee AF |
520 | /** |
521 | * CPUDumpFlags: | |
522 | * @CPU_DUMP_CODE: | |
523 | * @CPU_DUMP_FPU: dump FPU register state, not just integer | |
524 | * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state | |
525 | */ | |
526 | enum CPUDumpFlags { | |
527 | CPU_DUMP_CODE = 0x00010000, | |
528 | CPU_DUMP_FPU = 0x00020000, | |
529 | CPU_DUMP_CCOP = 0x00040000, | |
530 | }; | |
531 | ||
532 | /** | |
533 | * cpu_dump_state: | |
534 | * @cpu: The CPU whose state is to be dumped. | |
535 | * @f: File to dump to. | |
536 | * @cpu_fprintf: Function to dump with. | |
537 | * @flags: Flags what to dump. | |
538 | * | |
539 | * Dumps CPU state. | |
540 | */ | |
541 | void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, | |
542 | int flags); | |
543 | ||
544 | /** | |
545 | * cpu_dump_statistics: | |
546 | * @cpu: The CPU whose state is to be dumped. | |
547 | * @f: File to dump to. | |
548 | * @cpu_fprintf: Function to dump with. | |
549 | * @flags: Flags what to dump. | |
550 | * | |
551 | * Dumps CPU statistics. | |
552 | */ | |
553 | void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, | |
554 | int flags); | |
555 | ||
00b941e5 | 556 | #ifndef CONFIG_USER_ONLY |
1dc6fb1f PM |
557 | /** |
558 | * cpu_get_phys_page_attrs_debug: | |
559 | * @cpu: The CPU to obtain the physical page address for. | |
560 | * @addr: The virtual address. | |
561 | * @attrs: Updated on return with the memory transaction attributes to use | |
562 | * for this access. | |
563 | * | |
564 | * Obtains the physical page corresponding to a virtual one, together | |
565 | * with the corresponding memory transaction attributes to use for the access. | |
566 | * Use it only for debugging because no protection checks are done. | |
567 | * | |
568 | * Returns: Corresponding physical page address or -1 if no page found. | |
569 | */ | |
570 | static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, | |
571 | MemTxAttrs *attrs) | |
572 | { | |
573 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
574 | ||
575 | if (cc->get_phys_page_attrs_debug) { | |
576 | return cc->get_phys_page_attrs_debug(cpu, addr, attrs); | |
577 | } | |
578 | /* Fallback for CPUs which don't implement the _attrs_ hook */ | |
579 | *attrs = MEMTXATTRS_UNSPECIFIED; | |
580 | return cc->get_phys_page_debug(cpu, addr); | |
581 | } | |
582 | ||
00b941e5 AF |
583 | /** |
584 | * cpu_get_phys_page_debug: | |
585 | * @cpu: The CPU to obtain the physical page address for. | |
586 | * @addr: The virtual address. | |
587 | * | |
588 | * Obtains the physical page corresponding to a virtual one. | |
589 | * Use it only for debugging because no protection checks are done. | |
590 | * | |
591 | * Returns: Corresponding physical page address or -1 if no page found. | |
592 | */ | |
593 | static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) | |
594 | { | |
1dc6fb1f | 595 | MemTxAttrs attrs = {}; |
00b941e5 | 596 | |
1dc6fb1f | 597 | return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs); |
00b941e5 | 598 | } |
d7f25a9e PM |
599 | |
600 | /** cpu_asidx_from_attrs: | |
601 | * @cpu: CPU | |
602 | * @attrs: memory transaction attributes | |
603 | * | |
604 | * Returns the address space index specifying the CPU AddressSpace | |
605 | * to use for a memory access with the given transaction attributes. | |
606 | */ | |
607 | static inline int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs) | |
608 | { | |
609 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
610 | ||
611 | if (cc->asidx_from_attrs) { | |
612 | return cc->asidx_from_attrs(cpu, attrs); | |
613 | } | |
614 | return 0; | |
615 | } | |
00b941e5 AF |
616 | #endif |
617 | ||
267f685b PB |
618 | /** |
619 | * cpu_list_add: | |
620 | * @cpu: The CPU to be added to the list of CPUs. | |
621 | */ | |
622 | void cpu_list_add(CPUState *cpu); | |
623 | ||
624 | /** | |
625 | * cpu_list_remove: | |
626 | * @cpu: The CPU to be removed from the list of CPUs. | |
627 | */ | |
628 | void cpu_list_remove(CPUState *cpu); | |
629 | ||
dd83b06a AF |
630 | /** |
631 | * cpu_reset: | |
632 | * @cpu: The CPU whose state is to be reset. | |
633 | */ | |
634 | void cpu_reset(CPUState *cpu); | |
635 | ||
2b8c2754 AF |
636 | /** |
637 | * cpu_class_by_name: | |
638 | * @typename: The CPU base type. | |
639 | * @cpu_model: The model string without any parameters. | |
640 | * | |
641 | * Looks up a CPU #ObjectClass matching name @cpu_model. | |
642 | * | |
643 | * Returns: A #CPUClass or %NULL if not matching class is found. | |
644 | */ | |
645 | ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model); | |
646 | ||
3c72234c IM |
647 | /** |
648 | * cpu_create: | |
649 | * @typename: The CPU type. | |
650 | * | |
651 | * Instantiates a CPU and realizes the CPU. | |
652 | * | |
653 | * Returns: A #CPUState or %NULL if an error occurred. | |
654 | */ | |
655 | CPUState *cpu_create(const char *typename); | |
656 | ||
657 | /** | |
658 | * cpu_parse_cpu_model: | |
659 | * @typename: The CPU base type or CPU type. | |
660 | * @cpu_model: The model string including optional parameters. | |
661 | * | |
662 | * processes optional parameters and registers them as global properties | |
663 | * | |
4482e05c IM |
664 | * Returns: type of CPU to create or prints error and terminates process |
665 | * if an error occurred. | |
3c72234c IM |
666 | */ |
667 | const char *cpu_parse_cpu_model(const char *typename, const char *cpu_model); | |
668 | ||
9262685b AF |
669 | /** |
670 | * cpu_generic_init: | |
671 | * @typename: The CPU base type. | |
672 | * @cpu_model: The model string including optional parameters. | |
673 | * | |
674 | * Instantiates a CPU, processes optional parameters and realizes the CPU. | |
675 | * | |
676 | * Returns: A #CPUState or %NULL if an error occurred. | |
677 | */ | |
678 | CPUState *cpu_generic_init(const char *typename, const char *cpu_model); | |
679 | ||
3993c6bd | 680 | /** |
8c2e1b00 | 681 | * cpu_has_work: |
3993c6bd AF |
682 | * @cpu: The vCPU to check. |
683 | * | |
684 | * Checks whether the CPU has work to do. | |
685 | * | |
686 | * Returns: %true if the CPU has work, %false otherwise. | |
687 | */ | |
8c2e1b00 AF |
688 | static inline bool cpu_has_work(CPUState *cpu) |
689 | { | |
690 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
691 | ||
692 | g_assert(cc->has_work); | |
693 | return cc->has_work(cpu); | |
694 | } | |
3993c6bd | 695 | |
60e82579 AF |
696 | /** |
697 | * qemu_cpu_is_self: | |
698 | * @cpu: The vCPU to check against. | |
699 | * | |
700 | * Checks whether the caller is executing on the vCPU thread. | |
701 | * | |
702 | * Returns: %true if called from @cpu's thread, %false otherwise. | |
703 | */ | |
704 | bool qemu_cpu_is_self(CPUState *cpu); | |
705 | ||
c08d7424 AF |
706 | /** |
707 | * qemu_cpu_kick: | |
708 | * @cpu: The vCPU to kick. | |
709 | * | |
710 | * Kicks @cpu's thread. | |
711 | */ | |
712 | void qemu_cpu_kick(CPUState *cpu); | |
713 | ||
2fa45344 AF |
714 | /** |
715 | * cpu_is_stopped: | |
716 | * @cpu: The CPU to check. | |
717 | * | |
718 | * Checks whether the CPU is stopped. | |
719 | * | |
720 | * Returns: %true if run state is not running or if artificially stopped; | |
721 | * %false otherwise. | |
722 | */ | |
723 | bool cpu_is_stopped(CPUState *cpu); | |
724 | ||
d148d90e SF |
725 | /** |
726 | * do_run_on_cpu: | |
727 | * @cpu: The vCPU to run on. | |
728 | * @func: The function to be executed. | |
729 | * @data: Data to pass to the function. | |
730 | * @mutex: Mutex to release while waiting for @func to run. | |
731 | * | |
732 | * Used internally in the implementation of run_on_cpu. | |
733 | */ | |
14e6fe12 | 734 | void do_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data, |
d148d90e SF |
735 | QemuMutex *mutex); |
736 | ||
f100f0b3 AF |
737 | /** |
738 | * run_on_cpu: | |
739 | * @cpu: The vCPU to run on. | |
740 | * @func: The function to be executed. | |
741 | * @data: Data to pass to the function. | |
742 | * | |
743 | * Schedules the function @func for execution on the vCPU @cpu. | |
744 | */ | |
14e6fe12 | 745 | void run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data); |
f100f0b3 | 746 | |
3c02270d CV |
747 | /** |
748 | * async_run_on_cpu: | |
749 | * @cpu: The vCPU to run on. | |
750 | * @func: The function to be executed. | |
751 | * @data: Data to pass to the function. | |
752 | * | |
753 | * Schedules the function @func for execution on the vCPU @cpu asynchronously. | |
754 | */ | |
14e6fe12 | 755 | void async_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data); |
3c02270d | 756 | |
53f5ed95 PB |
757 | /** |
758 | * async_safe_run_on_cpu: | |
759 | * @cpu: The vCPU to run on. | |
760 | * @func: The function to be executed. | |
761 | * @data: Data to pass to the function. | |
762 | * | |
763 | * Schedules the function @func for execution on the vCPU @cpu asynchronously, | |
764 | * while all other vCPUs are sleeping. | |
765 | * | |
766 | * Unlike run_on_cpu and async_run_on_cpu, the function is run outside the | |
767 | * BQL. | |
768 | */ | |
14e6fe12 | 769 | void async_safe_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data); |
53f5ed95 | 770 | |
38d8f5c8 AF |
771 | /** |
772 | * qemu_get_cpu: | |
773 | * @index: The CPUState@cpu_index value of the CPU to obtain. | |
774 | * | |
775 | * Gets a CPU matching @index. | |
776 | * | |
777 | * Returns: The CPU or %NULL if there is no matching CPU. | |
778 | */ | |
779 | CPUState *qemu_get_cpu(int index); | |
780 | ||
69e5ff06 IM |
781 | /** |
782 | * cpu_exists: | |
783 | * @id: Guest-exposed CPU ID to lookup. | |
784 | * | |
785 | * Search for CPU with specified ID. | |
786 | * | |
787 | * Returns: %true - CPU is found, %false - CPU isn't found. | |
788 | */ | |
789 | bool cpu_exists(int64_t id); | |
790 | ||
5ce46cb3 EH |
791 | /** |
792 | * cpu_by_arch_id: | |
793 | * @id: Guest-exposed CPU ID of the CPU to obtain. | |
794 | * | |
795 | * Get a CPU with matching @id. | |
796 | * | |
797 | * Returns: The CPU or %NULL if there is no matching CPU. | |
798 | */ | |
799 | CPUState *cpu_by_arch_id(int64_t id); | |
800 | ||
2adcc85d JH |
801 | /** |
802 | * cpu_throttle_set: | |
803 | * @new_throttle_pct: Percent of sleep time. Valid range is 1 to 99. | |
804 | * | |
805 | * Throttles all vcpus by forcing them to sleep for the given percentage of | |
806 | * time. A throttle_percentage of 25 corresponds to a 75% duty cycle roughly. | |
807 | * (example: 10ms sleep for every 30ms awake). | |
808 | * | |
809 | * cpu_throttle_set can be called as needed to adjust new_throttle_pct. | |
810 | * Once the throttling starts, it will remain in effect until cpu_throttle_stop | |
811 | * is called. | |
812 | */ | |
813 | void cpu_throttle_set(int new_throttle_pct); | |
814 | ||
815 | /** | |
816 | * cpu_throttle_stop: | |
817 | * | |
818 | * Stops the vcpu throttling started by cpu_throttle_set. | |
819 | */ | |
820 | void cpu_throttle_stop(void); | |
821 | ||
822 | /** | |
823 | * cpu_throttle_active: | |
824 | * | |
825 | * Returns: %true if the vcpus are currently being throttled, %false otherwise. | |
826 | */ | |
827 | bool cpu_throttle_active(void); | |
828 | ||
829 | /** | |
830 | * cpu_throttle_get_percentage: | |
831 | * | |
832 | * Returns the vcpu throttle percentage. See cpu_throttle_set for details. | |
833 | * | |
834 | * Returns: The throttle percentage in range 1 to 99. | |
835 | */ | |
836 | int cpu_throttle_get_percentage(void); | |
837 | ||
c3affe56 AF |
838 | #ifndef CONFIG_USER_ONLY |
839 | ||
840 | typedef void (*CPUInterruptHandler)(CPUState *, int); | |
841 | ||
842 | extern CPUInterruptHandler cpu_interrupt_handler; | |
843 | ||
844 | /** | |
845 | * cpu_interrupt: | |
846 | * @cpu: The CPU to set an interrupt on. | |
847 | * @mask: The interupts to set. | |
848 | * | |
849 | * Invokes the interrupt handler. | |
850 | */ | |
851 | static inline void cpu_interrupt(CPUState *cpu, int mask) | |
852 | { | |
853 | cpu_interrupt_handler(cpu, mask); | |
854 | } | |
855 | ||
856 | #else /* USER_ONLY */ | |
857 | ||
858 | void cpu_interrupt(CPUState *cpu, int mask); | |
859 | ||
860 | #endif /* USER_ONLY */ | |
861 | ||
47507383 TH |
862 | #ifdef NEED_CPU_H |
863 | ||
93e22326 | 864 | #ifdef CONFIG_SOFTMMU |
c658b94f AF |
865 | static inline void cpu_unassigned_access(CPUState *cpu, hwaddr addr, |
866 | bool is_write, bool is_exec, | |
867 | int opaque, unsigned size) | |
868 | { | |
869 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
870 | ||
871 | if (cc->do_unassigned_access) { | |
872 | cc->do_unassigned_access(cpu, addr, is_write, is_exec, opaque, size); | |
873 | } | |
874 | } | |
875 | ||
93e22326 | 876 | static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr, |
b35399bb SS |
877 | MMUAccessType access_type, |
878 | int mmu_idx, uintptr_t retaddr) | |
93e22326 PB |
879 | { |
880 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
881 | ||
b35399bb | 882 | cc->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr); |
93e22326 | 883 | } |
0dff0939 PM |
884 | |
885 | static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr, | |
886 | vaddr addr, unsigned size, | |
887 | MMUAccessType access_type, | |
888 | int mmu_idx, MemTxAttrs attrs, | |
889 | MemTxResult response, | |
890 | uintptr_t retaddr) | |
891 | { | |
892 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
893 | ||
ed860129 | 894 | if (!cpu->ignore_memory_transaction_failures && cc->do_transaction_failed) { |
0dff0939 PM |
895 | cc->do_transaction_failed(cpu, physaddr, addr, size, access_type, |
896 | mmu_idx, attrs, response, retaddr); | |
897 | } | |
898 | } | |
c658b94f AF |
899 | #endif |
900 | ||
47507383 TH |
901 | #endif /* NEED_CPU_H */ |
902 | ||
2991b890 PC |
903 | /** |
904 | * cpu_set_pc: | |
905 | * @cpu: The CPU to set the program counter for. | |
906 | * @addr: Program counter value. | |
907 | * | |
908 | * Sets the program counter for a CPU. | |
909 | */ | |
910 | static inline void cpu_set_pc(CPUState *cpu, vaddr addr) | |
911 | { | |
912 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
913 | ||
914 | cc->set_pc(cpu, addr); | |
915 | } | |
916 | ||
d8ed887b AF |
917 | /** |
918 | * cpu_reset_interrupt: | |
919 | * @cpu: The CPU to clear the interrupt on. | |
920 | * @mask: The interrupt mask to clear. | |
921 | * | |
922 | * Resets interrupts on the vCPU @cpu. | |
923 | */ | |
924 | void cpu_reset_interrupt(CPUState *cpu, int mask); | |
925 | ||
60a3e17a AF |
926 | /** |
927 | * cpu_exit: | |
928 | * @cpu: The CPU to exit. | |
929 | * | |
930 | * Requests the CPU @cpu to exit execution. | |
931 | */ | |
932 | void cpu_exit(CPUState *cpu); | |
933 | ||
2993683b IM |
934 | /** |
935 | * cpu_resume: | |
936 | * @cpu: The CPU to resume. | |
937 | * | |
938 | * Resumes CPU, i.e. puts CPU into runnable state. | |
939 | */ | |
940 | void cpu_resume(CPUState *cpu); | |
dd83b06a | 941 | |
4c055ab5 GZ |
942 | /** |
943 | * cpu_remove: | |
944 | * @cpu: The CPU to remove. | |
945 | * | |
946 | * Requests the CPU to be removed. | |
947 | */ | |
948 | void cpu_remove(CPUState *cpu); | |
949 | ||
2c579042 BR |
950 | /** |
951 | * cpu_remove_sync: | |
952 | * @cpu: The CPU to remove. | |
953 | * | |
954 | * Requests the CPU to be removed and waits till it is removed. | |
955 | */ | |
956 | void cpu_remove_sync(CPUState *cpu); | |
957 | ||
d148d90e SF |
958 | /** |
959 | * process_queued_cpu_work() - process all items on CPU work queue | |
960 | * @cpu: The CPU which work queue to process. | |
961 | */ | |
962 | void process_queued_cpu_work(CPUState *cpu); | |
963 | ||
ab129972 PB |
964 | /** |
965 | * cpu_exec_start: | |
966 | * @cpu: The CPU for the current thread. | |
967 | * | |
968 | * Record that a CPU has started execution and can be interrupted with | |
969 | * cpu_exit. | |
970 | */ | |
971 | void cpu_exec_start(CPUState *cpu); | |
972 | ||
973 | /** | |
974 | * cpu_exec_end: | |
975 | * @cpu: The CPU for the current thread. | |
976 | * | |
977 | * Record that a CPU has stopped execution and exclusive sections | |
978 | * can be executed without interrupting it. | |
979 | */ | |
980 | void cpu_exec_end(CPUState *cpu); | |
981 | ||
982 | /** | |
983 | * start_exclusive: | |
984 | * | |
985 | * Wait for a concurrent exclusive section to end, and then start | |
986 | * a section of work that is run while other CPUs are not running | |
987 | * between cpu_exec_start and cpu_exec_end. CPUs that are running | |
988 | * cpu_exec are exited immediately. CPUs that call cpu_exec_start | |
989 | * during the exclusive section go to sleep until this CPU calls | |
990 | * end_exclusive. | |
ab129972 PB |
991 | */ |
992 | void start_exclusive(void); | |
993 | ||
994 | /** | |
995 | * end_exclusive: | |
996 | * | |
997 | * Concludes an exclusive execution section started by start_exclusive. | |
ab129972 PB |
998 | */ |
999 | void end_exclusive(void); | |
1000 | ||
c643bed9 AF |
1001 | /** |
1002 | * qemu_init_vcpu: | |
1003 | * @cpu: The vCPU to initialize. | |
1004 | * | |
1005 | * Initializes a vCPU. | |
1006 | */ | |
1007 | void qemu_init_vcpu(CPUState *cpu); | |
1008 | ||
3825b28f AF |
1009 | #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */ |
1010 | #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */ | |
1011 | #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */ | |
1012 | ||
1013 | /** | |
1014 | * cpu_single_step: | |
1015 | * @cpu: CPU to the flags for. | |
1016 | * @enabled: Flags to enable. | |
1017 | * | |
1018 | * Enables or disables single-stepping for @cpu. | |
1019 | */ | |
1020 | void cpu_single_step(CPUState *cpu, int enabled); | |
1021 | ||
b3310ab3 AF |
1022 | /* Breakpoint/watchpoint flags */ |
1023 | #define BP_MEM_READ 0x01 | |
1024 | #define BP_MEM_WRITE 0x02 | |
1025 | #define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE) | |
1026 | #define BP_STOP_BEFORE_ACCESS 0x04 | |
08225676 | 1027 | /* 0x08 currently unused */ |
b3310ab3 AF |
1028 | #define BP_GDB 0x10 |
1029 | #define BP_CPU 0x20 | |
b933066a | 1030 | #define BP_ANY (BP_GDB | BP_CPU) |
08225676 PM |
1031 | #define BP_WATCHPOINT_HIT_READ 0x40 |
1032 | #define BP_WATCHPOINT_HIT_WRITE 0x80 | |
1033 | #define BP_WATCHPOINT_HIT (BP_WATCHPOINT_HIT_READ | BP_WATCHPOINT_HIT_WRITE) | |
b3310ab3 AF |
1034 | |
1035 | int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, | |
1036 | CPUBreakpoint **breakpoint); | |
1037 | int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags); | |
1038 | void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint); | |
1039 | void cpu_breakpoint_remove_all(CPUState *cpu, int mask); | |
1040 | ||
b933066a RH |
1041 | /* Return true if PC matches an installed breakpoint. */ |
1042 | static inline bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, int mask) | |
1043 | { | |
1044 | CPUBreakpoint *bp; | |
1045 | ||
1046 | if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { | |
1047 | QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { | |
1048 | if (bp->pc == pc && (bp->flags & mask)) { | |
1049 | return true; | |
1050 | } | |
1051 | } | |
1052 | } | |
1053 | return false; | |
1054 | } | |
1055 | ||
75a34036 AF |
1056 | int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, |
1057 | int flags, CPUWatchpoint **watchpoint); | |
1058 | int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, | |
1059 | vaddr len, int flags); | |
1060 | void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint); | |
1061 | void cpu_watchpoint_remove_all(CPUState *cpu, int mask); | |
1062 | ||
63c91552 PB |
1063 | /** |
1064 | * cpu_get_address_space: | |
1065 | * @cpu: CPU to get address space from | |
1066 | * @asidx: index identifying which address space to get | |
1067 | * | |
1068 | * Return the requested address space of this CPU. @asidx | |
1069 | * specifies which address space to read. | |
1070 | */ | |
1071 | AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx); | |
1072 | ||
a47dddd7 AF |
1073 | void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...) |
1074 | GCC_FMT_ATTR(2, 3); | |
c7e002c5 | 1075 | extern Property cpu_common_props[]; |
39e329e3 | 1076 | void cpu_exec_initfn(CPUState *cpu); |
ce5b1bbf | 1077 | void cpu_exec_realizefn(CPUState *cpu, Error **errp); |
7bbc124e | 1078 | void cpu_exec_unrealizefn(CPUState *cpu); |
a47dddd7 | 1079 | |
47507383 TH |
1080 | #ifdef NEED_CPU_H |
1081 | ||
1a1562f5 AF |
1082 | #ifdef CONFIG_SOFTMMU |
1083 | extern const struct VMStateDescription vmstate_cpu_common; | |
1084 | #else | |
1085 | #define vmstate_cpu_common vmstate_dummy | |
1086 | #endif | |
1087 | ||
1088 | #define VMSTATE_CPU() { \ | |
1089 | .name = "parent_obj", \ | |
1090 | .size = sizeof(CPUState), \ | |
1091 | .vmsd = &vmstate_cpu_common, \ | |
1092 | .flags = VMS_STRUCT, \ | |
1093 | .offset = 0, \ | |
1094 | } | |
1095 | ||
47507383 TH |
1096 | #endif /* NEED_CPU_H */ |
1097 | ||
a07f953e IM |
1098 | #define UNASSIGNED_CPU_INDEX -1 |
1099 | ||
dd83b06a | 1100 | #endif |