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718dcedd DH |
1 | /* |
2 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sub license, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the | |
14 | * next paragraph) shall be included in all copies or substantial portions | |
15 | * of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
18 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
20 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
21 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
22 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
23 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
24 | * | |
25 | */ | |
26 | ||
27 | #ifndef _UAPI_I915_DRM_H_ | |
28 | #define _UAPI_I915_DRM_H_ | |
29 | ||
1049102f | 30 | #include "drm.h" |
718dcedd | 31 | |
b1c1f5c4 EV |
32 | #if defined(__cplusplus) |
33 | extern "C" { | |
34 | #endif | |
35 | ||
718dcedd DH |
36 | /* Please note that modifications to all structs defined here are |
37 | * subject to backwards-compatibility constraints. | |
38 | */ | |
39 | ||
cce723ed BW |
40 | /** |
41 | * DOC: uevents generated by i915 on it's device node | |
42 | * | |
43 | * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch | |
44 | * event from the gpu l3 cache. Additional information supplied is ROW, | |
35a85ac6 BW |
45 | * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep |
46 | * track of these events and if a specific cache-line seems to have a | |
47 | * persistent error remap it with the l3 remapping tool supplied in | |
48 | * intel-gpu-tools. The value supplied with the event is always 1. | |
cce723ed BW |
49 | * |
50 | * I915_ERROR_UEVENT - Generated upon error detection, currently only via | |
51 | * hangcheck. The error detection event is a good indicator of when things | |
52 | * began to go badly. The value supplied with the event is a 1 upon error | |
53 | * detection, and a 0 upon reset completion, signifying no more error | |
54 | * exists. NOTE: Disabling hangcheck or reset via module parameter will | |
55 | * cause the related events to not be seen. | |
56 | * | |
57 | * I915_RESET_UEVENT - Event is generated just before an attempt to reset the | |
58 | * the GPU. The value supplied with the event is always 1. NOTE: Disable | |
59 | * reset via module parameter will cause this event to not be seen. | |
60 | */ | |
61 | #define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" | |
62 | #define I915_ERROR_UEVENT "ERROR" | |
63 | #define I915_RESET_UEVENT "RESET" | |
718dcedd | 64 | |
3373ce2e ID |
65 | /* |
66 | * MOCS indexes used for GPU surfaces, defining the cacheability of the | |
67 | * surface data and the coherency for this data wrt. CPU vs. GPU accesses. | |
68 | */ | |
69 | enum i915_mocs_table_index { | |
70 | /* | |
71 | * Not cached anywhere, coherency between CPU and GPU accesses is | |
72 | * guaranteed. | |
73 | */ | |
74 | I915_MOCS_UNCACHED, | |
75 | /* | |
76 | * Cacheability and coherency controlled by the kernel automatically | |
77 | * based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current | |
78 | * usage of the surface (used for display scanout or not). | |
79 | */ | |
80 | I915_MOCS_PTE, | |
81 | /* | |
82 | * Cached in all GPU caches available on the platform. | |
83 | * Coherency between CPU and GPU accesses to the surface is not | |
84 | * guaranteed without extra synchronization. | |
85 | */ | |
86 | I915_MOCS_CACHED, | |
87 | }; | |
88 | ||
718dcedd DH |
89 | /* Each region is a minimum of 16k, and there are at most 255 of them. |
90 | */ | |
91 | #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use | |
92 | * of chars for next/prev indices */ | |
93 | #define I915_LOG_MIN_TEX_REGION_SIZE 14 | |
94 | ||
95 | typedef struct _drm_i915_init { | |
96 | enum { | |
97 | I915_INIT_DMA = 0x01, | |
98 | I915_CLEANUP_DMA = 0x02, | |
99 | I915_RESUME_DMA = 0x03 | |
100 | } func; | |
101 | unsigned int mmio_offset; | |
102 | int sarea_priv_offset; | |
103 | unsigned int ring_start; | |
104 | unsigned int ring_end; | |
105 | unsigned int ring_size; | |
106 | unsigned int front_offset; | |
107 | unsigned int back_offset; | |
108 | unsigned int depth_offset; | |
109 | unsigned int w; | |
110 | unsigned int h; | |
111 | unsigned int pitch; | |
112 | unsigned int pitch_bits; | |
113 | unsigned int back_pitch; | |
114 | unsigned int depth_pitch; | |
115 | unsigned int cpp; | |
116 | unsigned int chipset; | |
117 | } drm_i915_init_t; | |
118 | ||
119 | typedef struct _drm_i915_sarea { | |
120 | struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; | |
121 | int last_upload; /* last time texture was uploaded */ | |
122 | int last_enqueue; /* last time a buffer was enqueued */ | |
123 | int last_dispatch; /* age of the most recently dispatched buffer */ | |
124 | int ctxOwner; /* last context to upload state */ | |
125 | int texAge; | |
126 | int pf_enabled; /* is pageflipping allowed? */ | |
127 | int pf_active; | |
128 | int pf_current_page; /* which buffer is being displayed? */ | |
129 | int perf_boxes; /* performance boxes to be displayed */ | |
130 | int width, height; /* screen size in pixels */ | |
131 | ||
132 | drm_handle_t front_handle; | |
133 | int front_offset; | |
134 | int front_size; | |
135 | ||
136 | drm_handle_t back_handle; | |
137 | int back_offset; | |
138 | int back_size; | |
139 | ||
140 | drm_handle_t depth_handle; | |
141 | int depth_offset; | |
142 | int depth_size; | |
143 | ||
144 | drm_handle_t tex_handle; | |
145 | int tex_offset; | |
146 | int tex_size; | |
147 | int log_tex_granularity; | |
148 | int pitch; | |
149 | int rotation; /* 0, 90, 180 or 270 */ | |
150 | int rotated_offset; | |
151 | int rotated_size; | |
152 | int rotated_pitch; | |
153 | int virtualX, virtualY; | |
154 | ||
155 | unsigned int front_tiled; | |
156 | unsigned int back_tiled; | |
157 | unsigned int depth_tiled; | |
158 | unsigned int rotated_tiled; | |
159 | unsigned int rotated2_tiled; | |
160 | ||
161 | int pipeA_x; | |
162 | int pipeA_y; | |
163 | int pipeA_w; | |
164 | int pipeA_h; | |
165 | int pipeB_x; | |
166 | int pipeB_y; | |
167 | int pipeB_w; | |
168 | int pipeB_h; | |
169 | ||
170 | /* fill out some space for old userspace triple buffer */ | |
171 | drm_handle_t unused_handle; | |
172 | __u32 unused1, unused2, unused3; | |
173 | ||
174 | /* buffer object handles for static buffers. May change | |
175 | * over the lifetime of the client. | |
176 | */ | |
177 | __u32 front_bo_handle; | |
178 | __u32 back_bo_handle; | |
179 | __u32 unused_bo_handle; | |
180 | __u32 depth_bo_handle; | |
181 | ||
182 | } drm_i915_sarea_t; | |
183 | ||
184 | /* due to userspace building against these headers we need some compat here */ | |
185 | #define planeA_x pipeA_x | |
186 | #define planeA_y pipeA_y | |
187 | #define planeA_w pipeA_w | |
188 | #define planeA_h pipeA_h | |
189 | #define planeB_x pipeB_x | |
190 | #define planeB_y pipeB_y | |
191 | #define planeB_w pipeB_w | |
192 | #define planeB_h pipeB_h | |
193 | ||
194 | /* Flags for perf_boxes | |
195 | */ | |
196 | #define I915_BOX_RING_EMPTY 0x1 | |
197 | #define I915_BOX_FLIP 0x2 | |
198 | #define I915_BOX_WAIT 0x4 | |
199 | #define I915_BOX_TEXTURE_LOAD 0x8 | |
200 | #define I915_BOX_LOST_CONTEXT 0x10 | |
201 | ||
21631f10 DL |
202 | /* |
203 | * i915 specific ioctls. | |
204 | * | |
205 | * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie | |
206 | * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset | |
207 | * against DRM_COMMAND_BASE and should be between [0x0, 0x60). | |
718dcedd DH |
208 | */ |
209 | #define DRM_I915_INIT 0x00 | |
210 | #define DRM_I915_FLUSH 0x01 | |
211 | #define DRM_I915_FLIP 0x02 | |
212 | #define DRM_I915_BATCHBUFFER 0x03 | |
213 | #define DRM_I915_IRQ_EMIT 0x04 | |
214 | #define DRM_I915_IRQ_WAIT 0x05 | |
215 | #define DRM_I915_GETPARAM 0x06 | |
216 | #define DRM_I915_SETPARAM 0x07 | |
217 | #define DRM_I915_ALLOC 0x08 | |
218 | #define DRM_I915_FREE 0x09 | |
219 | #define DRM_I915_INIT_HEAP 0x0a | |
220 | #define DRM_I915_CMDBUFFER 0x0b | |
221 | #define DRM_I915_DESTROY_HEAP 0x0c | |
222 | #define DRM_I915_SET_VBLANK_PIPE 0x0d | |
223 | #define DRM_I915_GET_VBLANK_PIPE 0x0e | |
224 | #define DRM_I915_VBLANK_SWAP 0x0f | |
225 | #define DRM_I915_HWS_ADDR 0x11 | |
226 | #define DRM_I915_GEM_INIT 0x13 | |
227 | #define DRM_I915_GEM_EXECBUFFER 0x14 | |
228 | #define DRM_I915_GEM_PIN 0x15 | |
229 | #define DRM_I915_GEM_UNPIN 0x16 | |
230 | #define DRM_I915_GEM_BUSY 0x17 | |
231 | #define DRM_I915_GEM_THROTTLE 0x18 | |
232 | #define DRM_I915_GEM_ENTERVT 0x19 | |
233 | #define DRM_I915_GEM_LEAVEVT 0x1a | |
234 | #define DRM_I915_GEM_CREATE 0x1b | |
235 | #define DRM_I915_GEM_PREAD 0x1c | |
236 | #define DRM_I915_GEM_PWRITE 0x1d | |
237 | #define DRM_I915_GEM_MMAP 0x1e | |
238 | #define DRM_I915_GEM_SET_DOMAIN 0x1f | |
239 | #define DRM_I915_GEM_SW_FINISH 0x20 | |
240 | #define DRM_I915_GEM_SET_TILING 0x21 | |
241 | #define DRM_I915_GEM_GET_TILING 0x22 | |
242 | #define DRM_I915_GEM_GET_APERTURE 0x23 | |
243 | #define DRM_I915_GEM_MMAP_GTT 0x24 | |
244 | #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 | |
245 | #define DRM_I915_GEM_MADVISE 0x26 | |
246 | #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 | |
247 | #define DRM_I915_OVERLAY_ATTRS 0x28 | |
248 | #define DRM_I915_GEM_EXECBUFFER2 0x29 | |
fec0445c | 249 | #define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2 |
718dcedd DH |
250 | #define DRM_I915_GET_SPRITE_COLORKEY 0x2a |
251 | #define DRM_I915_SET_SPRITE_COLORKEY 0x2b | |
252 | #define DRM_I915_GEM_WAIT 0x2c | |
253 | #define DRM_I915_GEM_CONTEXT_CREATE 0x2d | |
254 | #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e | |
255 | #define DRM_I915_GEM_SET_CACHING 0x2f | |
256 | #define DRM_I915_GEM_GET_CACHING 0x30 | |
257 | #define DRM_I915_REG_READ 0x31 | |
b6359918 | 258 | #define DRM_I915_GET_RESET_STATS 0x32 |
5cc9ed4b | 259 | #define DRM_I915_GEM_USERPTR 0x33 |
c9dc0f35 CW |
260 | #define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 |
261 | #define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 | |
eec688e1 | 262 | #define DRM_I915_PERF_OPEN 0x36 |
f89823c2 LL |
263 | #define DRM_I915_PERF_ADD_CONFIG 0x37 |
264 | #define DRM_I915_PERF_REMOVE_CONFIG 0x38 | |
718dcedd DH |
265 | |
266 | #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) | |
267 | #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) | |
268 | #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) | |
269 | #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) | |
270 | #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) | |
271 | #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) | |
272 | #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) | |
273 | #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) | |
274 | #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) | |
275 | #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) | |
276 | #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) | |
277 | #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) | |
278 | #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) | |
279 | #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) | |
280 | #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) | |
281 | #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) | |
282 | #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) | |
283 | #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) | |
284 | #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) | |
285 | #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) | |
fec0445c | 286 | #define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2) |
718dcedd DH |
287 | #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) |
288 | #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) | |
289 | #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) | |
290 | #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) | |
291 | #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) | |
292 | #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) | |
293 | #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) | |
294 | #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) | |
295 | #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) | |
296 | #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) | |
297 | #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) | |
298 | #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) | |
299 | #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) | |
300 | #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) | |
301 | #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) | |
302 | #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) | |
303 | #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) | |
304 | #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) | |
305 | #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) | |
306 | #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) | |
307 | #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) | |
308 | #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) | |
309 | #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) | |
2c60fae1 | 310 | #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) |
718dcedd DH |
311 | #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) |
312 | #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) | |
313 | #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) | |
314 | #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) | |
b6359918 | 315 | #define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) |
5cc9ed4b | 316 | #define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) |
c9dc0f35 CW |
317 | #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) |
318 | #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) | |
eec688e1 | 319 | #define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param) |
f89823c2 LL |
320 | #define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config) |
321 | #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64) | |
718dcedd DH |
322 | |
323 | /* Allow drivers to submit batchbuffers directly to hardware, relying | |
324 | * on the security mechanisms provided by hardware. | |
325 | */ | |
326 | typedef struct drm_i915_batchbuffer { | |
327 | int start; /* agp offset */ | |
328 | int used; /* nr bytes in use */ | |
329 | int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ | |
330 | int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ | |
331 | int num_cliprects; /* mulitpass with multiple cliprects? */ | |
332 | struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ | |
333 | } drm_i915_batchbuffer_t; | |
334 | ||
335 | /* As above, but pass a pointer to userspace buffer which can be | |
336 | * validated by the kernel prior to sending to hardware. | |
337 | */ | |
338 | typedef struct _drm_i915_cmdbuffer { | |
339 | char __user *buf; /* pointer to userspace command buffer */ | |
340 | int sz; /* nr bytes in buf */ | |
341 | int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ | |
342 | int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ | |
343 | int num_cliprects; /* mulitpass with multiple cliprects? */ | |
344 | struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ | |
345 | } drm_i915_cmdbuffer_t; | |
346 | ||
347 | /* Userspace can request & wait on irq's: | |
348 | */ | |
349 | typedef struct drm_i915_irq_emit { | |
350 | int __user *irq_seq; | |
351 | } drm_i915_irq_emit_t; | |
352 | ||
353 | typedef struct drm_i915_irq_wait { | |
354 | int irq_seq; | |
355 | } drm_i915_irq_wait_t; | |
356 | ||
357 | /* Ioctl to query kernel params: | |
358 | */ | |
359 | #define I915_PARAM_IRQ_ACTIVE 1 | |
360 | #define I915_PARAM_ALLOW_BATCHBUFFER 2 | |
361 | #define I915_PARAM_LAST_DISPATCH 3 | |
362 | #define I915_PARAM_CHIPSET_ID 4 | |
363 | #define I915_PARAM_HAS_GEM 5 | |
364 | #define I915_PARAM_NUM_FENCES_AVAIL 6 | |
365 | #define I915_PARAM_HAS_OVERLAY 7 | |
366 | #define I915_PARAM_HAS_PAGEFLIPPING 8 | |
367 | #define I915_PARAM_HAS_EXECBUF2 9 | |
368 | #define I915_PARAM_HAS_BSD 10 | |
369 | #define I915_PARAM_HAS_BLT 11 | |
370 | #define I915_PARAM_HAS_RELAXED_FENCING 12 | |
371 | #define I915_PARAM_HAS_COHERENT_RINGS 13 | |
372 | #define I915_PARAM_HAS_EXEC_CONSTANTS 14 | |
373 | #define I915_PARAM_HAS_RELAXED_DELTA 15 | |
374 | #define I915_PARAM_HAS_GEN7_SOL_RESET 16 | |
375 | #define I915_PARAM_HAS_LLC 17 | |
376 | #define I915_PARAM_HAS_ALIASING_PPGTT 18 | |
377 | #define I915_PARAM_HAS_WAIT_TIMEOUT 19 | |
378 | #define I915_PARAM_HAS_SEMAPHORES 20 | |
379 | #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 | |
a1f2cc73 | 380 | #define I915_PARAM_HAS_VEBOX 22 |
c2fb7916 | 381 | #define I915_PARAM_HAS_SECURE_BATCHES 23 |
b45305fc | 382 | #define I915_PARAM_HAS_PINNED_BATCHES 24 |
ed5982e6 | 383 | #define I915_PARAM_HAS_EXEC_NO_RELOC 25 |
eef90ccb | 384 | #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 |
651d794f | 385 | #define I915_PARAM_HAS_WT 27 |
d728c8ef | 386 | #define I915_PARAM_CMD_PARSER_VERSION 28 |
6a2c4232 | 387 | #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 |
1816f923 | 388 | #define I915_PARAM_MMAP_VERSION 30 |
08e16dc8 | 389 | #define I915_PARAM_HAS_BSD2 31 |
27cd4461 | 390 | #define I915_PARAM_REVISION 32 |
a1559ffe JM |
391 | #define I915_PARAM_SUBSLICE_TOTAL 33 |
392 | #define I915_PARAM_EU_TOTAL 34 | |
49e4d842 | 393 | #define I915_PARAM_HAS_GPU_RESET 35 |
a9ed33ca | 394 | #define I915_PARAM_HAS_RESOURCE_STREAMER 36 |
506a8e87 | 395 | #define I915_PARAM_HAS_EXEC_SOFTPIN 37 |
37f501af | 396 | #define I915_PARAM_HAS_POOLED_EU 38 |
397 | #define I915_PARAM_MIN_EU_IN_POOL 39 | |
4cc69075 | 398 | #define I915_PARAM_MMAP_GTT_VERSION 40 |
718dcedd | 399 | |
bf64e0b0 CW |
400 | /* |
401 | * Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution | |
0de9136d | 402 | * priorities and the driver will attempt to execute batches in priority order. |
bf64e0b0 CW |
403 | * The param returns a capability bitmask, nonzero implies that the scheduler |
404 | * is enabled, with different features present according to the mask. | |
ac14fbd4 CW |
405 | * |
406 | * The initial priority for each batch is supplied by the context and is | |
407 | * controlled via I915_CONTEXT_PARAM_PRIORITY. | |
0de9136d CW |
408 | */ |
409 | #define I915_PARAM_HAS_SCHEDULER 41 | |
bf64e0b0 CW |
410 | #define I915_SCHEDULER_CAP_ENABLED (1ul << 0) |
411 | #define I915_SCHEDULER_CAP_PRIORITY (1ul << 1) | |
412 | #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2) | |
413 | ||
5464cd65 | 414 | #define I915_PARAM_HUC_STATUS 42 |
0de9136d | 415 | |
77ae9957 CW |
416 | /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of |
417 | * synchronisation with implicit fencing on individual objects. | |
418 | * See EXEC_OBJECT_ASYNC. | |
419 | */ | |
420 | #define I915_PARAM_HAS_EXEC_ASYNC 43 | |
421 | ||
fec0445c CW |
422 | /* Query whether DRM_I915_GEM_EXECBUFFER2 supports explicit fence support - |
423 | * both being able to pass in a sync_file fd to wait upon before executing, | |
424 | * and being able to return a new sync_file fd that is signaled when the | |
425 | * current request is complete. See I915_EXEC_FENCE_IN and I915_EXEC_FENCE_OUT. | |
426 | */ | |
427 | #define I915_PARAM_HAS_EXEC_FENCE 44 | |
428 | ||
b0fd47ad CW |
429 | /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to capture |
430 | * user specified bufffers for post-mortem debugging of GPU hangs. See | |
431 | * EXEC_OBJECT_CAPTURE. | |
432 | */ | |
433 | #define I915_PARAM_HAS_EXEC_CAPTURE 45 | |
434 | ||
7fed555c RB |
435 | #define I915_PARAM_SLICE_MASK 46 |
436 | ||
f5320233 RB |
437 | /* Assuming it's uniform for each slice, this queries the mask of subslices |
438 | * per-slice for this system. | |
439 | */ | |
440 | #define I915_PARAM_SUBSLICE_MASK 47 | |
441 | ||
1a71cf2f CW |
442 | /* |
443 | * Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying the batch buffer | |
444 | * as the first execobject as opposed to the last. See I915_EXEC_BATCH_FIRST. | |
445 | */ | |
446 | #define I915_PARAM_HAS_EXEC_BATCH_FIRST 48 | |
447 | ||
cf6e7bac JE |
448 | /* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of |
449 | * drm_i915_gem_exec_fence structures. See I915_EXEC_FENCE_ARRAY. | |
450 | */ | |
451 | #define I915_PARAM_HAS_EXEC_FENCE_ARRAY 49 | |
452 | ||
718dcedd | 453 | typedef struct drm_i915_getparam { |
16f7249d | 454 | __s32 param; |
346add78 DV |
455 | /* |
456 | * WARNING: Using pointers instead of fixed-size u64 means we need to write | |
457 | * compat32 code. Don't repeat this mistake. | |
458 | */ | |
718dcedd DH |
459 | int __user *value; |
460 | } drm_i915_getparam_t; | |
461 | ||
462 | /* Ioctl to set kernel params: | |
463 | */ | |
464 | #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 | |
465 | #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 | |
466 | #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 | |
467 | #define I915_SETPARAM_NUM_USED_FENCES 4 | |
468 | ||
469 | typedef struct drm_i915_setparam { | |
470 | int param; | |
471 | int value; | |
472 | } drm_i915_setparam_t; | |
473 | ||
474 | /* A memory manager for regions of shared memory: | |
475 | */ | |
476 | #define I915_MEM_REGION_AGP 1 | |
477 | ||
478 | typedef struct drm_i915_mem_alloc { | |
479 | int region; | |
480 | int alignment; | |
481 | int size; | |
482 | int __user *region_offset; /* offset from start of fb or agp */ | |
483 | } drm_i915_mem_alloc_t; | |
484 | ||
485 | typedef struct drm_i915_mem_free { | |
486 | int region; | |
487 | int region_offset; | |
488 | } drm_i915_mem_free_t; | |
489 | ||
490 | typedef struct drm_i915_mem_init_heap { | |
491 | int region; | |
492 | int size; | |
493 | int start; | |
494 | } drm_i915_mem_init_heap_t; | |
495 | ||
496 | /* Allow memory manager to be torn down and re-initialized (eg on | |
497 | * rotate): | |
498 | */ | |
499 | typedef struct drm_i915_mem_destroy_heap { | |
500 | int region; | |
501 | } drm_i915_mem_destroy_heap_t; | |
502 | ||
503 | /* Allow X server to configure which pipes to monitor for vblank signals | |
504 | */ | |
505 | #define DRM_I915_VBLANK_PIPE_A 1 | |
506 | #define DRM_I915_VBLANK_PIPE_B 2 | |
507 | ||
508 | typedef struct drm_i915_vblank_pipe { | |
509 | int pipe; | |
510 | } drm_i915_vblank_pipe_t; | |
511 | ||
512 | /* Schedule buffer swap at given vertical blank: | |
513 | */ | |
514 | typedef struct drm_i915_vblank_swap { | |
515 | drm_drawable_t drawable; | |
516 | enum drm_vblank_seq_type seqtype; | |
517 | unsigned int sequence; | |
518 | } drm_i915_vblank_swap_t; | |
519 | ||
520 | typedef struct drm_i915_hws_addr { | |
521 | __u64 addr; | |
522 | } drm_i915_hws_addr_t; | |
523 | ||
524 | struct drm_i915_gem_init { | |
525 | /** | |
526 | * Beginning offset in the GTT to be managed by the DRM memory | |
527 | * manager. | |
528 | */ | |
529 | __u64 gtt_start; | |
530 | /** | |
531 | * Ending offset in the GTT to be managed by the DRM memory | |
532 | * manager. | |
533 | */ | |
534 | __u64 gtt_end; | |
535 | }; | |
536 | ||
537 | struct drm_i915_gem_create { | |
538 | /** | |
539 | * Requested size for the object. | |
540 | * | |
541 | * The (page-aligned) allocated size for the object will be returned. | |
542 | */ | |
543 | __u64 size; | |
544 | /** | |
545 | * Returned handle for the object. | |
546 | * | |
547 | * Object handles are nonzero. | |
548 | */ | |
549 | __u32 handle; | |
550 | __u32 pad; | |
551 | }; | |
552 | ||
553 | struct drm_i915_gem_pread { | |
554 | /** Handle for the object being read. */ | |
555 | __u32 handle; | |
556 | __u32 pad; | |
557 | /** Offset into the object to read from */ | |
558 | __u64 offset; | |
559 | /** Length of data to read */ | |
560 | __u64 size; | |
561 | /** | |
562 | * Pointer to write the data into. | |
563 | * | |
564 | * This is a fixed-size type for 32/64 compatibility. | |
565 | */ | |
566 | __u64 data_ptr; | |
567 | }; | |
568 | ||
569 | struct drm_i915_gem_pwrite { | |
570 | /** Handle for the object being written to. */ | |
571 | __u32 handle; | |
572 | __u32 pad; | |
573 | /** Offset into the object to write to */ | |
574 | __u64 offset; | |
575 | /** Length of data to write */ | |
576 | __u64 size; | |
577 | /** | |
578 | * Pointer to read the data from. | |
579 | * | |
580 | * This is a fixed-size type for 32/64 compatibility. | |
581 | */ | |
582 | __u64 data_ptr; | |
583 | }; | |
584 | ||
585 | struct drm_i915_gem_mmap { | |
586 | /** Handle for the object being mapped. */ | |
587 | __u32 handle; | |
588 | __u32 pad; | |
589 | /** Offset in the object to map. */ | |
590 | __u64 offset; | |
591 | /** | |
592 | * Length of data to map. | |
593 | * | |
594 | * The value will be page-aligned. | |
595 | */ | |
596 | __u64 size; | |
597 | /** | |
598 | * Returned pointer the data was mapped at. | |
599 | * | |
600 | * This is a fixed-size type for 32/64 compatibility. | |
601 | */ | |
602 | __u64 addr_ptr; | |
1816f923 AG |
603 | |
604 | /** | |
605 | * Flags for extended behaviour. | |
606 | * | |
607 | * Added in version 2. | |
608 | */ | |
609 | __u64 flags; | |
610 | #define I915_MMAP_WC 0x1 | |
718dcedd DH |
611 | }; |
612 | ||
613 | struct drm_i915_gem_mmap_gtt { | |
614 | /** Handle for the object being mapped. */ | |
615 | __u32 handle; | |
616 | __u32 pad; | |
617 | /** | |
618 | * Fake offset to use for subsequent mmap call | |
619 | * | |
620 | * This is a fixed-size type for 32/64 compatibility. | |
621 | */ | |
622 | __u64 offset; | |
623 | }; | |
624 | ||
625 | struct drm_i915_gem_set_domain { | |
626 | /** Handle for the object */ | |
627 | __u32 handle; | |
628 | ||
629 | /** New read domains */ | |
630 | __u32 read_domains; | |
631 | ||
632 | /** New write domain */ | |
633 | __u32 write_domain; | |
634 | }; | |
635 | ||
636 | struct drm_i915_gem_sw_finish { | |
637 | /** Handle for the object */ | |
638 | __u32 handle; | |
639 | }; | |
640 | ||
641 | struct drm_i915_gem_relocation_entry { | |
642 | /** | |
643 | * Handle of the buffer being pointed to by this relocation entry. | |
644 | * | |
645 | * It's appealing to make this be an index into the mm_validate_entry | |
646 | * list to refer to the buffer, but this allows the driver to create | |
647 | * a relocation list for state buffers and not re-write it per | |
648 | * exec using the buffer. | |
649 | */ | |
650 | __u32 target_handle; | |
651 | ||
652 | /** | |
653 | * Value to be added to the offset of the target buffer to make up | |
654 | * the relocation entry. | |
655 | */ | |
656 | __u32 delta; | |
657 | ||
658 | /** Offset in the buffer the relocation entry will be written into */ | |
659 | __u64 offset; | |
660 | ||
661 | /** | |
662 | * Offset value of the target buffer that the relocation entry was last | |
663 | * written as. | |
664 | * | |
665 | * If the buffer has the same offset as last time, we can skip syncing | |
666 | * and writing the relocation. This value is written back out by | |
667 | * the execbuffer ioctl when the relocation is written. | |
668 | */ | |
669 | __u64 presumed_offset; | |
670 | ||
671 | /** | |
672 | * Target memory domains read by this operation. | |
673 | */ | |
674 | __u32 read_domains; | |
675 | ||
676 | /** | |
677 | * Target memory domains written by this operation. | |
678 | * | |
679 | * Note that only one domain may be written by the whole | |
680 | * execbuffer operation, so that where there are conflicts, | |
681 | * the application will get -EINVAL back. | |
682 | */ | |
683 | __u32 write_domain; | |
684 | }; | |
685 | ||
686 | /** @{ | |
687 | * Intel memory domains | |
688 | * | |
689 | * Most of these just align with the various caches in | |
690 | * the system and are used to flush and invalidate as | |
691 | * objects end up cached in different domains. | |
692 | */ | |
693 | /** CPU cache */ | |
694 | #define I915_GEM_DOMAIN_CPU 0x00000001 | |
695 | /** Render cache, used by 2D and 3D drawing */ | |
696 | #define I915_GEM_DOMAIN_RENDER 0x00000002 | |
697 | /** Sampler cache, used by texture engine */ | |
698 | #define I915_GEM_DOMAIN_SAMPLER 0x00000004 | |
699 | /** Command queue, used to load batch buffers */ | |
700 | #define I915_GEM_DOMAIN_COMMAND 0x00000008 | |
701 | /** Instruction cache, used by shader programs */ | |
702 | #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 | |
703 | /** Vertex address cache */ | |
704 | #define I915_GEM_DOMAIN_VERTEX 0x00000020 | |
705 | /** GTT domain - aperture and scanout */ | |
706 | #define I915_GEM_DOMAIN_GTT 0x00000040 | |
e22d8e3c CW |
707 | /** WC domain - uncached access */ |
708 | #define I915_GEM_DOMAIN_WC 0x00000080 | |
718dcedd DH |
709 | /** @} */ |
710 | ||
711 | struct drm_i915_gem_exec_object { | |
712 | /** | |
713 | * User's handle for a buffer to be bound into the GTT for this | |
714 | * operation. | |
715 | */ | |
716 | __u32 handle; | |
717 | ||
718 | /** Number of relocations to be performed on this buffer */ | |
719 | __u32 relocation_count; | |
720 | /** | |
721 | * Pointer to array of struct drm_i915_gem_relocation_entry containing | |
722 | * the relocations to be performed in this buffer. | |
723 | */ | |
724 | __u64 relocs_ptr; | |
725 | ||
726 | /** Required alignment in graphics aperture */ | |
727 | __u64 alignment; | |
728 | ||
729 | /** | |
730 | * Returned value of the updated offset of the object, for future | |
731 | * presumed_offset writes. | |
732 | */ | |
733 | __u64 offset; | |
734 | }; | |
735 | ||
736 | struct drm_i915_gem_execbuffer { | |
737 | /** | |
738 | * List of buffers to be validated with their relocations to be | |
739 | * performend on them. | |
740 | * | |
741 | * This is a pointer to an array of struct drm_i915_gem_validate_entry. | |
742 | * | |
743 | * These buffers must be listed in an order such that all relocations | |
744 | * a buffer is performing refer to buffers that have already appeared | |
745 | * in the validate list. | |
746 | */ | |
747 | __u64 buffers_ptr; | |
748 | __u32 buffer_count; | |
749 | ||
750 | /** Offset in the batchbuffer to start execution from. */ | |
751 | __u32 batch_start_offset; | |
752 | /** Bytes used in batchbuffer from batch_start_offset */ | |
753 | __u32 batch_len; | |
754 | __u32 DR1; | |
755 | __u32 DR4; | |
756 | __u32 num_cliprects; | |
757 | /** This is a struct drm_clip_rect *cliprects */ | |
758 | __u64 cliprects_ptr; | |
759 | }; | |
760 | ||
761 | struct drm_i915_gem_exec_object2 { | |
762 | /** | |
763 | * User's handle for a buffer to be bound into the GTT for this | |
764 | * operation. | |
765 | */ | |
766 | __u32 handle; | |
767 | ||
768 | /** Number of relocations to be performed on this buffer */ | |
769 | __u32 relocation_count; | |
770 | /** | |
771 | * Pointer to array of struct drm_i915_gem_relocation_entry containing | |
772 | * the relocations to be performed in this buffer. | |
773 | */ | |
774 | __u64 relocs_ptr; | |
775 | ||
776 | /** Required alignment in graphics aperture */ | |
777 | __u64 alignment; | |
778 | ||
779 | /** | |
506a8e87 CW |
780 | * When the EXEC_OBJECT_PINNED flag is specified this is populated by |
781 | * the user with the GTT offset at which this object will be pinned. | |
782 | * When the I915_EXEC_NO_RELOC flag is specified this must contain the | |
783 | * presumed_offset of the object. | |
784 | * During execbuffer2 the kernel populates it with the value of the | |
785 | * current GTT offset of the object, for future presumed_offset writes. | |
718dcedd DH |
786 | */ |
787 | __u64 offset; | |
788 | ||
9e2793f6 DG |
789 | #define EXEC_OBJECT_NEEDS_FENCE (1<<0) |
790 | #define EXEC_OBJECT_NEEDS_GTT (1<<1) | |
791 | #define EXEC_OBJECT_WRITE (1<<2) | |
101b506a | 792 | #define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3) |
9e2793f6 | 793 | #define EXEC_OBJECT_PINNED (1<<4) |
91b2db6f | 794 | #define EXEC_OBJECT_PAD_TO_SIZE (1<<5) |
77ae9957 CW |
795 | /* The kernel implicitly tracks GPU activity on all GEM objects, and |
796 | * synchronises operations with outstanding rendering. This includes | |
797 | * rendering on other devices if exported via dma-buf. However, sometimes | |
798 | * this tracking is too coarse and the user knows better. For example, | |
799 | * if the object is split into non-overlapping ranges shared between different | |
800 | * clients or engines (i.e. suballocating objects), the implicit tracking | |
801 | * by kernel assumes that each operation affects the whole object rather | |
802 | * than an individual range, causing needless synchronisation between clients. | |
803 | * The kernel will also forgo any CPU cache flushes prior to rendering from | |
804 | * the object as the client is expected to be also handling such domain | |
805 | * tracking. | |
806 | * | |
807 | * The kernel maintains the implicit tracking in order to manage resources | |
808 | * used by the GPU - this flag only disables the synchronisation prior to | |
809 | * rendering with this object in this execbuf. | |
810 | * | |
811 | * Opting out of implicit synhronisation requires the user to do its own | |
812 | * explicit tracking to avoid rendering corruption. See, for example, | |
813 | * I915_PARAM_HAS_EXEC_FENCE to order execbufs and execute them asynchronously. | |
814 | */ | |
815 | #define EXEC_OBJECT_ASYNC (1<<6) | |
b0fd47ad CW |
816 | /* Request that the contents of this execobject be copied into the error |
817 | * state upon a GPU hang involving this batch for post-mortem debugging. | |
818 | * These buffers are recorded in no particular order as "user" in | |
819 | * /sys/class/drm/cardN/error. Query I915_PARAM_HAS_EXEC_CAPTURE to see | |
820 | * if the kernel supports this flag. | |
821 | */ | |
822 | #define EXEC_OBJECT_CAPTURE (1<<7) | |
9e2793f6 | 823 | /* All remaining bits are MBZ and RESERVED FOR FUTURE USE */ |
b0fd47ad | 824 | #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_CAPTURE<<1) |
718dcedd | 825 | __u64 flags; |
ed5982e6 | 826 | |
91b2db6f CW |
827 | union { |
828 | __u64 rsvd1; | |
829 | __u64 pad_to_size; | |
830 | }; | |
718dcedd DH |
831 | __u64 rsvd2; |
832 | }; | |
833 | ||
cf6e7bac JE |
834 | struct drm_i915_gem_exec_fence { |
835 | /** | |
836 | * User's handle for a drm_syncobj to wait on or signal. | |
837 | */ | |
838 | __u32 handle; | |
839 | ||
840 | #define I915_EXEC_FENCE_WAIT (1<<0) | |
841 | #define I915_EXEC_FENCE_SIGNAL (1<<1) | |
40a48845 | 842 | #define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1)) |
cf6e7bac JE |
843 | __u32 flags; |
844 | }; | |
845 | ||
718dcedd DH |
846 | struct drm_i915_gem_execbuffer2 { |
847 | /** | |
848 | * List of gem_exec_object2 structs | |
849 | */ | |
850 | __u64 buffers_ptr; | |
851 | __u32 buffer_count; | |
852 | ||
853 | /** Offset in the batchbuffer to start execution from. */ | |
854 | __u32 batch_start_offset; | |
855 | /** Bytes used in batchbuffer from batch_start_offset */ | |
856 | __u32 batch_len; | |
857 | __u32 DR1; | |
858 | __u32 DR4; | |
859 | __u32 num_cliprects; | |
cf6e7bac JE |
860 | /** |
861 | * This is a struct drm_clip_rect *cliprects if I915_EXEC_FENCE_ARRAY | |
862 | * is not set. If I915_EXEC_FENCE_ARRAY is set, then this is a | |
863 | * struct drm_i915_gem_exec_fence *fences. | |
864 | */ | |
718dcedd DH |
865 | __u64 cliprects_ptr; |
866 | #define I915_EXEC_RING_MASK (7<<0) | |
867 | #define I915_EXEC_DEFAULT (0<<0) | |
868 | #define I915_EXEC_RENDER (1<<0) | |
869 | #define I915_EXEC_BSD (2<<0) | |
870 | #define I915_EXEC_BLT (3<<0) | |
82f91b6e | 871 | #define I915_EXEC_VEBOX (4<<0) |
718dcedd DH |
872 | |
873 | /* Used for switching the constants addressing mode on gen4+ RENDER ring. | |
874 | * Gen6+ only supports relative addressing to dynamic state (default) and | |
875 | * absolute addressing. | |
876 | * | |
877 | * These flags are ignored for the BSD and BLT rings. | |
878 | */ | |
879 | #define I915_EXEC_CONSTANTS_MASK (3<<6) | |
880 | #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ | |
881 | #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) | |
882 | #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ | |
883 | __u64 flags; | |
884 | __u64 rsvd1; /* now used for context info */ | |
885 | __u64 rsvd2; | |
886 | }; | |
887 | ||
888 | /** Resets the SO write offset registers for transform feedback on gen7. */ | |
889 | #define I915_EXEC_GEN7_SOL_RESET (1<<8) | |
890 | ||
c2fb7916 DV |
891 | /** Request a privileged ("secure") batch buffer. Note only available for |
892 | * DRM_ROOT_ONLY | DRM_MASTER processes. | |
893 | */ | |
894 | #define I915_EXEC_SECURE (1<<9) | |
895 | ||
b45305fc DV |
896 | /** Inform the kernel that the batch is and will always be pinned. This |
897 | * negates the requirement for a workaround to be performed to avoid | |
898 | * an incoherent CS (such as can be found on 830/845). If this flag is | |
899 | * not passed, the kernel will endeavour to make sure the batch is | |
900 | * coherent with the CS before execution. If this flag is passed, | |
901 | * userspace assumes the responsibility for ensuring the same. | |
902 | */ | |
903 | #define I915_EXEC_IS_PINNED (1<<10) | |
904 | ||
c3d19d3c | 905 | /** Provide a hint to the kernel that the command stream and auxiliary |
ed5982e6 DV |
906 | * state buffers already holds the correct presumed addresses and so the |
907 | * relocation process may be skipped if no buffers need to be moved in | |
908 | * preparation for the execbuffer. | |
909 | */ | |
910 | #define I915_EXEC_NO_RELOC (1<<11) | |
911 | ||
eef90ccb CW |
912 | /** Use the reloc.handle as an index into the exec object array rather |
913 | * than as the per-file handle. | |
914 | */ | |
915 | #define I915_EXEC_HANDLE_LUT (1<<12) | |
916 | ||
8d360dff | 917 | /** Used for switching BSD rings on the platforms with two BSD rings */ |
d9da6aa0 TU |
918 | #define I915_EXEC_BSD_SHIFT (13) |
919 | #define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT) | |
920 | /* default ping-pong mode */ | |
921 | #define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT) | |
922 | #define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT) | |
923 | #define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT) | |
8d360dff | 924 | |
a9ed33ca AJ |
925 | /** Tell the kernel that the batchbuffer is processed by |
926 | * the resource streamer. | |
927 | */ | |
928 | #define I915_EXEC_RESOURCE_STREAMER (1<<15) | |
929 | ||
fec0445c CW |
930 | /* Setting I915_EXEC_FENCE_IN implies that lower_32_bits(rsvd2) represent |
931 | * a sync_file fd to wait upon (in a nonblocking manner) prior to executing | |
932 | * the batch. | |
933 | * | |
934 | * Returns -EINVAL if the sync_file fd cannot be found. | |
935 | */ | |
936 | #define I915_EXEC_FENCE_IN (1<<16) | |
937 | ||
938 | /* Setting I915_EXEC_FENCE_OUT causes the ioctl to return a sync_file fd | |
939 | * in the upper_32_bits(rsvd2) upon success. Ownership of the fd is given | |
940 | * to the caller, and it should be close() after use. (The fd is a regular | |
941 | * file descriptor and will be cleaned up on process termination. It holds | |
942 | * a reference to the request, but nothing else.) | |
943 | * | |
944 | * The sync_file fd can be combined with other sync_file and passed either | |
945 | * to execbuf using I915_EXEC_FENCE_IN, to atomic KMS ioctls (so that a flip | |
946 | * will only occur after this request completes), or to other devices. | |
947 | * | |
948 | * Using I915_EXEC_FENCE_OUT requires use of | |
949 | * DRM_IOCTL_I915_GEM_EXECBUFFER2_WR ioctl so that the result is written | |
950 | * back to userspace. Failure to do so will cause the out-fence to always | |
951 | * be reported as zero, and the real fence fd to be leaked. | |
952 | */ | |
953 | #define I915_EXEC_FENCE_OUT (1<<17) | |
954 | ||
1a71cf2f CW |
955 | /* |
956 | * Traditionally the execbuf ioctl has only considered the final element in | |
957 | * the execobject[] to be the executable batch. Often though, the client | |
958 | * will known the batch object prior to construction and being able to place | |
959 | * it into the execobject[] array first can simplify the relocation tracking. | |
960 | * Setting I915_EXEC_BATCH_FIRST tells execbuf to use element 0 of the | |
961 | * execobject[] as the * batch instead (the default is to use the last | |
962 | * element). | |
963 | */ | |
964 | #define I915_EXEC_BATCH_FIRST (1<<18) | |
cf6e7bac JE |
965 | |
966 | /* Setting I915_FENCE_ARRAY implies that num_cliprects and cliprects_ptr | |
967 | * define an array of i915_gem_exec_fence structures which specify a set of | |
968 | * dma fences to wait upon or signal. | |
969 | */ | |
970 | #define I915_EXEC_FENCE_ARRAY (1<<19) | |
971 | ||
972 | #define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_ARRAY<<1)) | |
ed5982e6 | 973 | |
718dcedd DH |
974 | #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) |
975 | #define i915_execbuffer2_set_context_id(eb2, context) \ | |
976 | (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK | |
977 | #define i915_execbuffer2_get_context_id(eb2) \ | |
978 | ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) | |
979 | ||
980 | struct drm_i915_gem_pin { | |
981 | /** Handle of the buffer to be pinned. */ | |
982 | __u32 handle; | |
983 | __u32 pad; | |
984 | ||
985 | /** alignment required within the aperture */ | |
986 | __u64 alignment; | |
987 | ||
988 | /** Returned GTT offset of the buffer. */ | |
989 | __u64 offset; | |
990 | }; | |
991 | ||
992 | struct drm_i915_gem_unpin { | |
993 | /** Handle of the buffer to be unpinned. */ | |
994 | __u32 handle; | |
995 | __u32 pad; | |
996 | }; | |
997 | ||
998 | struct drm_i915_gem_busy { | |
999 | /** Handle of the buffer to check for busy */ | |
1000 | __u32 handle; | |
1001 | ||
426960be CW |
1002 | /** Return busy status |
1003 | * | |
1004 | * A return of 0 implies that the object is idle (after | |
1005 | * having flushed any pending activity), and a non-zero return that | |
1006 | * the object is still in-flight on the GPU. (The GPU has not yet | |
1007 | * signaled completion for all pending requests that reference the | |
1255501d CW |
1008 | * object.) An object is guaranteed to become idle eventually (so |
1009 | * long as no new GPU commands are executed upon it). Due to the | |
1010 | * asynchronous nature of the hardware, an object reported | |
1011 | * as busy may become idle before the ioctl is completed. | |
1012 | * | |
1013 | * Furthermore, if the object is busy, which engine is busy is only | |
1014 | * provided as a guide. There are race conditions which prevent the | |
1015 | * report of which engines are busy from being always accurate. | |
1016 | * However, the converse is not true. If the object is idle, the | |
1017 | * result of the ioctl, that all engines are idle, is accurate. | |
426960be CW |
1018 | * |
1019 | * The returned dword is split into two fields to indicate both | |
1020 | * the engines on which the object is being read, and the | |
1021 | * engine on which it is currently being written (if any). | |
1022 | * | |
1023 | * The low word (bits 0:15) indicate if the object is being written | |
1024 | * to by any engine (there can only be one, as the GEM implicit | |
1025 | * synchronisation rules force writes to be serialised). Only the | |
1026 | * engine for the last write is reported. | |
1027 | * | |
1028 | * The high word (bits 16:31) are a bitmask of which engines are | |
1029 | * currently reading from the object. Multiple engines may be | |
1030 | * reading from the object simultaneously. | |
1031 | * | |
1032 | * The value of each engine is the same as specified in the | |
1033 | * EXECBUFFER2 ioctl, i.e. I915_EXEC_RENDER, I915_EXEC_BSD etc. | |
1034 | * Note I915_EXEC_DEFAULT is a symbolic value and is mapped to | |
1035 | * the I915_EXEC_RENDER engine for execution, and so it is never | |
1036 | * reported as active itself. Some hardware may have parallel | |
1037 | * execution engines, e.g. multiple media engines, which are | |
1038 | * mapped to the same identifier in the EXECBUFFER2 ioctl and | |
1039 | * so are not separately reported for busyness. | |
1255501d CW |
1040 | * |
1041 | * Caveat emptor: | |
1042 | * Only the boolean result of this query is reliable; that is whether | |
1043 | * the object is idle or busy. The report of which engines are busy | |
1044 | * should be only used as a heuristic. | |
718dcedd DH |
1045 | */ |
1046 | __u32 busy; | |
1047 | }; | |
1048 | ||
35c7ab42 DV |
1049 | /** |
1050 | * I915_CACHING_NONE | |
1051 | * | |
1052 | * GPU access is not coherent with cpu caches. Default for machines without an | |
1053 | * LLC. | |
1054 | */ | |
718dcedd | 1055 | #define I915_CACHING_NONE 0 |
35c7ab42 DV |
1056 | /** |
1057 | * I915_CACHING_CACHED | |
1058 | * | |
1059 | * GPU access is coherent with cpu caches and furthermore the data is cached in | |
1060 | * last-level caches shared between cpu cores and the gpu GT. Default on | |
1061 | * machines with HAS_LLC. | |
1062 | */ | |
718dcedd | 1063 | #define I915_CACHING_CACHED 1 |
35c7ab42 DV |
1064 | /** |
1065 | * I915_CACHING_DISPLAY | |
1066 | * | |
1067 | * Special GPU caching mode which is coherent with the scanout engines. | |
1068 | * Transparently falls back to I915_CACHING_NONE on platforms where no special | |
1069 | * cache mode (like write-through or gfdt flushing) is available. The kernel | |
1070 | * automatically sets this mode when using a buffer as a scanout target. | |
1071 | * Userspace can manually set this mode to avoid a costly stall and clflush in | |
1072 | * the hotpath of drawing the first frame. | |
1073 | */ | |
1074 | #define I915_CACHING_DISPLAY 2 | |
718dcedd DH |
1075 | |
1076 | struct drm_i915_gem_caching { | |
1077 | /** | |
1078 | * Handle of the buffer to set/get the caching level of. */ | |
1079 | __u32 handle; | |
1080 | ||
1081 | /** | |
1082 | * Cacheing level to apply or return value | |
1083 | * | |
1084 | * bits0-15 are for generic caching control (i.e. the above defined | |
1085 | * values). bits16-31 are reserved for platform-specific variations | |
1086 | * (e.g. l3$ caching on gen7). */ | |
1087 | __u32 caching; | |
1088 | }; | |
1089 | ||
1090 | #define I915_TILING_NONE 0 | |
1091 | #define I915_TILING_X 1 | |
1092 | #define I915_TILING_Y 2 | |
deeb1519 | 1093 | #define I915_TILING_LAST I915_TILING_Y |
718dcedd DH |
1094 | |
1095 | #define I915_BIT_6_SWIZZLE_NONE 0 | |
1096 | #define I915_BIT_6_SWIZZLE_9 1 | |
1097 | #define I915_BIT_6_SWIZZLE_9_10 2 | |
1098 | #define I915_BIT_6_SWIZZLE_9_11 3 | |
1099 | #define I915_BIT_6_SWIZZLE_9_10_11 4 | |
1100 | /* Not seen by userland */ | |
1101 | #define I915_BIT_6_SWIZZLE_UNKNOWN 5 | |
1102 | /* Seen by userland. */ | |
1103 | #define I915_BIT_6_SWIZZLE_9_17 6 | |
1104 | #define I915_BIT_6_SWIZZLE_9_10_17 7 | |
1105 | ||
1106 | struct drm_i915_gem_set_tiling { | |
1107 | /** Handle of the buffer to have its tiling state updated */ | |
1108 | __u32 handle; | |
1109 | ||
1110 | /** | |
1111 | * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, | |
1112 | * I915_TILING_Y). | |
1113 | * | |
1114 | * This value is to be set on request, and will be updated by the | |
1115 | * kernel on successful return with the actual chosen tiling layout. | |
1116 | * | |
1117 | * The tiling mode may be demoted to I915_TILING_NONE when the system | |
1118 | * has bit 6 swizzling that can't be managed correctly by GEM. | |
1119 | * | |
1120 | * Buffer contents become undefined when changing tiling_mode. | |
1121 | */ | |
1122 | __u32 tiling_mode; | |
1123 | ||
1124 | /** | |
1125 | * Stride in bytes for the object when in I915_TILING_X or | |
1126 | * I915_TILING_Y. | |
1127 | */ | |
1128 | __u32 stride; | |
1129 | ||
1130 | /** | |
1131 | * Returned address bit 6 swizzling required for CPU access through | |
1132 | * mmap mapping. | |
1133 | */ | |
1134 | __u32 swizzle_mode; | |
1135 | }; | |
1136 | ||
1137 | struct drm_i915_gem_get_tiling { | |
1138 | /** Handle of the buffer to get tiling state for. */ | |
1139 | __u32 handle; | |
1140 | ||
1141 | /** | |
1142 | * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, | |
1143 | * I915_TILING_Y). | |
1144 | */ | |
1145 | __u32 tiling_mode; | |
1146 | ||
1147 | /** | |
1148 | * Returned address bit 6 swizzling required for CPU access through | |
1149 | * mmap mapping. | |
1150 | */ | |
1151 | __u32 swizzle_mode; | |
70f2f5c7 CW |
1152 | |
1153 | /** | |
1154 | * Returned address bit 6 swizzling required for CPU access through | |
1155 | * mmap mapping whilst bound. | |
1156 | */ | |
1157 | __u32 phys_swizzle_mode; | |
718dcedd DH |
1158 | }; |
1159 | ||
1160 | struct drm_i915_gem_get_aperture { | |
1161 | /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ | |
1162 | __u64 aper_size; | |
1163 | ||
1164 | /** | |
1165 | * Available space in the aperture used by i915_gem_execbuffer, in | |
1166 | * bytes | |
1167 | */ | |
1168 | __u64 aper_available_size; | |
1169 | }; | |
1170 | ||
1171 | struct drm_i915_get_pipe_from_crtc_id { | |
1172 | /** ID of CRTC being requested **/ | |
1173 | __u32 crtc_id; | |
1174 | ||
1175 | /** pipe of requested CRTC **/ | |
1176 | __u32 pipe; | |
1177 | }; | |
1178 | ||
1179 | #define I915_MADV_WILLNEED 0 | |
1180 | #define I915_MADV_DONTNEED 1 | |
1181 | #define __I915_MADV_PURGED 2 /* internal state */ | |
1182 | ||
1183 | struct drm_i915_gem_madvise { | |
1184 | /** Handle of the buffer to change the backing store advice */ | |
1185 | __u32 handle; | |
1186 | ||
1187 | /* Advice: either the buffer will be needed again in the near future, | |
1188 | * or wont be and could be discarded under memory pressure. | |
1189 | */ | |
1190 | __u32 madv; | |
1191 | ||
1192 | /** Whether the backing store still exists. */ | |
1193 | __u32 retained; | |
1194 | }; | |
1195 | ||
1196 | /* flags */ | |
1197 | #define I915_OVERLAY_TYPE_MASK 0xff | |
1198 | #define I915_OVERLAY_YUV_PLANAR 0x01 | |
1199 | #define I915_OVERLAY_YUV_PACKED 0x02 | |
1200 | #define I915_OVERLAY_RGB 0x03 | |
1201 | ||
1202 | #define I915_OVERLAY_DEPTH_MASK 0xff00 | |
1203 | #define I915_OVERLAY_RGB24 0x1000 | |
1204 | #define I915_OVERLAY_RGB16 0x2000 | |
1205 | #define I915_OVERLAY_RGB15 0x3000 | |
1206 | #define I915_OVERLAY_YUV422 0x0100 | |
1207 | #define I915_OVERLAY_YUV411 0x0200 | |
1208 | #define I915_OVERLAY_YUV420 0x0300 | |
1209 | #define I915_OVERLAY_YUV410 0x0400 | |
1210 | ||
1211 | #define I915_OVERLAY_SWAP_MASK 0xff0000 | |
1212 | #define I915_OVERLAY_NO_SWAP 0x000000 | |
1213 | #define I915_OVERLAY_UV_SWAP 0x010000 | |
1214 | #define I915_OVERLAY_Y_SWAP 0x020000 | |
1215 | #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 | |
1216 | ||
1217 | #define I915_OVERLAY_FLAGS_MASK 0xff000000 | |
1218 | #define I915_OVERLAY_ENABLE 0x01000000 | |
1219 | ||
1220 | struct drm_intel_overlay_put_image { | |
1221 | /* various flags and src format description */ | |
1222 | __u32 flags; | |
1223 | /* source picture description */ | |
1224 | __u32 bo_handle; | |
1225 | /* stride values and offsets are in bytes, buffer relative */ | |
1226 | __u16 stride_Y; /* stride for packed formats */ | |
1227 | __u16 stride_UV; | |
1228 | __u32 offset_Y; /* offset for packet formats */ | |
1229 | __u32 offset_U; | |
1230 | __u32 offset_V; | |
1231 | /* in pixels */ | |
1232 | __u16 src_width; | |
1233 | __u16 src_height; | |
1234 | /* to compensate the scaling factors for partially covered surfaces */ | |
1235 | __u16 src_scan_width; | |
1236 | __u16 src_scan_height; | |
1237 | /* output crtc description */ | |
1238 | __u32 crtc_id; | |
1239 | __u16 dst_x; | |
1240 | __u16 dst_y; | |
1241 | __u16 dst_width; | |
1242 | __u16 dst_height; | |
1243 | }; | |
1244 | ||
1245 | /* flags */ | |
1246 | #define I915_OVERLAY_UPDATE_ATTRS (1<<0) | |
1247 | #define I915_OVERLAY_UPDATE_GAMMA (1<<1) | |
ea9da4e4 | 1248 | #define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2) |
718dcedd DH |
1249 | struct drm_intel_overlay_attrs { |
1250 | __u32 flags; | |
1251 | __u32 color_key; | |
1252 | __s32 brightness; | |
1253 | __u32 contrast; | |
1254 | __u32 saturation; | |
1255 | __u32 gamma0; | |
1256 | __u32 gamma1; | |
1257 | __u32 gamma2; | |
1258 | __u32 gamma3; | |
1259 | __u32 gamma4; | |
1260 | __u32 gamma5; | |
1261 | }; | |
1262 | ||
1263 | /* | |
1264 | * Intel sprite handling | |
1265 | * | |
1266 | * Color keying works with a min/mask/max tuple. Both source and destination | |
1267 | * color keying is allowed. | |
1268 | * | |
1269 | * Source keying: | |
1270 | * Sprite pixels within the min & max values, masked against the color channels | |
1271 | * specified in the mask field, will be transparent. All other pixels will | |
1272 | * be displayed on top of the primary plane. For RGB surfaces, only the min | |
1273 | * and mask fields will be used; ranged compares are not allowed. | |
1274 | * | |
1275 | * Destination keying: | |
1276 | * Primary plane pixels that match the min value, masked against the color | |
1277 | * channels specified in the mask field, will be replaced by corresponding | |
1278 | * pixels from the sprite plane. | |
1279 | * | |
1280 | * Note that source & destination keying are exclusive; only one can be | |
1281 | * active on a given plane. | |
1282 | */ | |
1283 | ||
1284 | #define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */ | |
1285 | #define I915_SET_COLORKEY_DESTINATION (1<<1) | |
1286 | #define I915_SET_COLORKEY_SOURCE (1<<2) | |
1287 | struct drm_intel_sprite_colorkey { | |
1288 | __u32 plane_id; | |
1289 | __u32 min_value; | |
1290 | __u32 channel_mask; | |
1291 | __u32 max_value; | |
1292 | __u32 flags; | |
1293 | }; | |
1294 | ||
1295 | struct drm_i915_gem_wait { | |
1296 | /** Handle of BO we shall wait on */ | |
1297 | __u32 bo_handle; | |
1298 | __u32 flags; | |
1299 | /** Number of nanoseconds to wait, Returns time remaining. */ | |
1300 | __s64 timeout_ns; | |
1301 | }; | |
1302 | ||
1303 | struct drm_i915_gem_context_create { | |
1304 | /* output: id of new context*/ | |
1305 | __u32 ctx_id; | |
1306 | __u32 pad; | |
1307 | }; | |
1308 | ||
1309 | struct drm_i915_gem_context_destroy { | |
1310 | __u32 ctx_id; | |
1311 | __u32 pad; | |
1312 | }; | |
1313 | ||
1314 | struct drm_i915_reg_read { | |
8697600b VS |
1315 | /* |
1316 | * Register offset. | |
1317 | * For 64bit wide registers where the upper 32bits don't immediately | |
1318 | * follow the lower 32bits, the offset of the lower 32bits must | |
1319 | * be specified | |
1320 | */ | |
718dcedd | 1321 | __u64 offset; |
822a4b67 | 1322 | #define I915_REG_READ_8B_WA (1ul << 0) |
3fd3a6ff | 1323 | |
718dcedd DH |
1324 | __u64 val; /* Return value */ |
1325 | }; | |
648a9bc5 CW |
1326 | /* Known registers: |
1327 | * | |
1328 | * Render engine timestamp - 0x2358 + 64bit - gen7+ | |
1329 | * - Note this register returns an invalid value if using the default | |
3fd3a6ff JL |
1330 | * single instruction 8byte read, in order to workaround that pass |
1331 | * flag I915_REG_READ_8B_WA in offset field. | |
648a9bc5 CW |
1332 | * |
1333 | */ | |
b6359918 MK |
1334 | |
1335 | struct drm_i915_reset_stats { | |
1336 | __u32 ctx_id; | |
1337 | __u32 flags; | |
1338 | ||
1339 | /* All resets since boot/module reload, for all contexts */ | |
1340 | __u32 reset_count; | |
1341 | ||
1342 | /* Number of batches lost when active in GPU, for this context */ | |
1343 | __u32 batch_active; | |
1344 | ||
1345 | /* Number of batches lost pending for execution, for this context */ | |
1346 | __u32 batch_pending; | |
1347 | ||
1348 | __u32 pad; | |
1349 | }; | |
1350 | ||
5cc9ed4b CW |
1351 | struct drm_i915_gem_userptr { |
1352 | __u64 user_ptr; | |
1353 | __u64 user_size; | |
1354 | __u32 flags; | |
1355 | #define I915_USERPTR_READ_ONLY 0x1 | |
1356 | #define I915_USERPTR_UNSYNCHRONIZED 0x80000000 | |
1357 | /** | |
1358 | * Returned handle for the object. | |
1359 | * | |
1360 | * Object handles are nonzero. | |
1361 | */ | |
1362 | __u32 handle; | |
1363 | }; | |
1364 | ||
c9dc0f35 CW |
1365 | struct drm_i915_gem_context_param { |
1366 | __u32 ctx_id; | |
1367 | __u32 size; | |
1368 | __u64 param; | |
fa8848f2 CW |
1369 | #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 |
1370 | #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2 | |
1371 | #define I915_CONTEXT_PARAM_GTT_SIZE 0x3 | |
bc3d6744 | 1372 | #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4 |
84102171 | 1373 | #define I915_CONTEXT_PARAM_BANNABLE 0x5 |
ac14fbd4 CW |
1374 | #define I915_CONTEXT_PARAM_PRIORITY 0x6 |
1375 | #define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */ | |
1376 | #define I915_CONTEXT_DEFAULT_PRIORITY 0 | |
1377 | #define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */ | |
c9dc0f35 CW |
1378 | __u64 value; |
1379 | }; | |
1380 | ||
d7965152 | 1381 | enum drm_i915_oa_format { |
19f81df2 RB |
1382 | I915_OA_FORMAT_A13 = 1, /* HSW only */ |
1383 | I915_OA_FORMAT_A29, /* HSW only */ | |
1384 | I915_OA_FORMAT_A13_B8_C8, /* HSW only */ | |
1385 | I915_OA_FORMAT_B4_C8, /* HSW only */ | |
1386 | I915_OA_FORMAT_A45_B8_C8, /* HSW only */ | |
1387 | I915_OA_FORMAT_B4_C8_A16, /* HSW only */ | |
1388 | I915_OA_FORMAT_C4_B8, /* HSW+ */ | |
1389 | ||
1390 | /* Gen8+ */ | |
1391 | I915_OA_FORMAT_A12, | |
1392 | I915_OA_FORMAT_A12_B8_C8, | |
1393 | I915_OA_FORMAT_A32u40_A4u32_B8_C8, | |
d7965152 RB |
1394 | |
1395 | I915_OA_FORMAT_MAX /* non-ABI */ | |
1396 | }; | |
1397 | ||
eec688e1 RB |
1398 | enum drm_i915_perf_property_id { |
1399 | /** | |
1400 | * Open the stream for a specific context handle (as used with | |
1401 | * execbuffer2). A stream opened for a specific context this way | |
1402 | * won't typically require root privileges. | |
1403 | */ | |
1404 | DRM_I915_PERF_PROP_CTX_HANDLE = 1, | |
1405 | ||
d7965152 RB |
1406 | /** |
1407 | * A value of 1 requests the inclusion of raw OA unit reports as | |
1408 | * part of stream samples. | |
1409 | */ | |
1410 | DRM_I915_PERF_PROP_SAMPLE_OA, | |
1411 | ||
1412 | /** | |
1413 | * The value specifies which set of OA unit metrics should be | |
1414 | * be configured, defining the contents of any OA unit reports. | |
1415 | */ | |
1416 | DRM_I915_PERF_PROP_OA_METRICS_SET, | |
1417 | ||
1418 | /** | |
1419 | * The value specifies the size and layout of OA unit reports. | |
1420 | */ | |
1421 | DRM_I915_PERF_PROP_OA_FORMAT, | |
1422 | ||
1423 | /** | |
1424 | * Specifying this property implicitly requests periodic OA unit | |
1425 | * sampling and (at least on Haswell) the sampling frequency is derived | |
1426 | * from this exponent as follows: | |
1427 | * | |
1428 | * 80ns * 2^(period_exponent + 1) | |
1429 | */ | |
1430 | DRM_I915_PERF_PROP_OA_EXPONENT, | |
1431 | ||
eec688e1 RB |
1432 | DRM_I915_PERF_PROP_MAX /* non-ABI */ |
1433 | }; | |
1434 | ||
1435 | struct drm_i915_perf_open_param { | |
1436 | __u32 flags; | |
1437 | #define I915_PERF_FLAG_FD_CLOEXEC (1<<0) | |
1438 | #define I915_PERF_FLAG_FD_NONBLOCK (1<<1) | |
1439 | #define I915_PERF_FLAG_DISABLED (1<<2) | |
1440 | ||
1441 | /** The number of u64 (id, value) pairs */ | |
1442 | __u32 num_properties; | |
1443 | ||
1444 | /** | |
1445 | * Pointer to array of u64 (id, value) pairs configuring the stream | |
1446 | * to open. | |
1447 | */ | |
cd8bddc4 | 1448 | __u64 properties_ptr; |
eec688e1 RB |
1449 | }; |
1450 | ||
d7965152 RB |
1451 | /** |
1452 | * Enable data capture for a stream that was either opened in a disabled state | |
1453 | * via I915_PERF_FLAG_DISABLED or was later disabled via | |
1454 | * I915_PERF_IOCTL_DISABLE. | |
1455 | * | |
1456 | * It is intended to be cheaper to disable and enable a stream than it may be | |
1457 | * to close and re-open a stream with the same configuration. | |
1458 | * | |
1459 | * It's undefined whether any pending data for the stream will be lost. | |
1460 | */ | |
eec688e1 | 1461 | #define I915_PERF_IOCTL_ENABLE _IO('i', 0x0) |
d7965152 RB |
1462 | |
1463 | /** | |
1464 | * Disable data capture for a stream. | |
1465 | * | |
1466 | * It is an error to try and read a stream that is disabled. | |
1467 | */ | |
eec688e1 RB |
1468 | #define I915_PERF_IOCTL_DISABLE _IO('i', 0x1) |
1469 | ||
1470 | /** | |
1471 | * Common to all i915 perf records | |
1472 | */ | |
1473 | struct drm_i915_perf_record_header { | |
1474 | __u32 type; | |
1475 | __u16 pad; | |
1476 | __u16 size; | |
1477 | }; | |
1478 | ||
1479 | enum drm_i915_perf_record_type { | |
1480 | ||
1481 | /** | |
1482 | * Samples are the work horse record type whose contents are extensible | |
1483 | * and defined when opening an i915 perf stream based on the given | |
1484 | * properties. | |
1485 | * | |
1486 | * Boolean properties following the naming convention | |
1487 | * DRM_I915_PERF_SAMPLE_xyz_PROP request the inclusion of 'xyz' data in | |
1488 | * every sample. | |
1489 | * | |
1490 | * The order of these sample properties given by userspace has no | |
d7965152 | 1491 | * affect on the ordering of data within a sample. The order is |
eec688e1 RB |
1492 | * documented here. |
1493 | * | |
1494 | * struct { | |
1495 | * struct drm_i915_perf_record_header header; | |
1496 | * | |
d7965152 | 1497 | * { u32 oa_report[]; } && DRM_I915_PERF_PROP_SAMPLE_OA |
eec688e1 RB |
1498 | * }; |
1499 | */ | |
1500 | DRM_I915_PERF_RECORD_SAMPLE = 1, | |
1501 | ||
d7965152 RB |
1502 | /* |
1503 | * Indicates that one or more OA reports were not written by the | |
1504 | * hardware. This can happen for example if an MI_REPORT_PERF_COUNT | |
1505 | * command collides with periodic sampling - which would be more likely | |
1506 | * at higher sampling frequencies. | |
1507 | */ | |
1508 | DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2, | |
1509 | ||
1510 | /** | |
1511 | * An error occurred that resulted in all pending OA reports being lost. | |
1512 | */ | |
1513 | DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3, | |
1514 | ||
eec688e1 RB |
1515 | DRM_I915_PERF_RECORD_MAX /* non-ABI */ |
1516 | }; | |
1517 | ||
f89823c2 LL |
1518 | /** |
1519 | * Structure to upload perf dynamic configuration into the kernel. | |
1520 | */ | |
1521 | struct drm_i915_perf_oa_config { | |
1522 | /** String formatted like "%08x-%04x-%04x-%04x-%012x" */ | |
1523 | char uuid[36]; | |
1524 | ||
1525 | __u32 n_mux_regs; | |
1526 | __u32 n_boolean_regs; | |
1527 | __u32 n_flex_regs; | |
1528 | ||
ee427e25 LL |
1529 | /* |
1530 | * These fields are pointers to tuples of u32 values (register | |
1531 | * address, value). For example the expected length of the buffer | |
1532 | * pointed by mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs). | |
1533 | */ | |
17ad4fdd CW |
1534 | __u64 mux_regs_ptr; |
1535 | __u64 boolean_regs_ptr; | |
1536 | __u64 flex_regs_ptr; | |
f89823c2 LL |
1537 | }; |
1538 | ||
b1c1f5c4 EV |
1539 | #if defined(__cplusplus) |
1540 | } | |
1541 | #endif | |
1542 | ||
718dcedd | 1543 | #endif /* _UAPI_I915_DRM_H_ */ |