]>
Commit | Line | Data |
---|---|---|
559d6701 | 1 | /* |
559d6701 TV |
2 | * Copyright (C) 2008 Nokia Corporation |
3 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
a0b38cc4 TV |
18 | #ifndef __OMAP_OMAPDSS_H |
19 | #define __OMAP_OMAPDSS_H | |
559d6701 TV |
20 | |
21 | #include <linux/list.h> | |
22 | #include <linux/kobject.h> | |
23 | #include <linux/device.h> | |
348be69d | 24 | #include <linux/interrupt.h> |
559d6701 TV |
25 | |
26 | #define DISPC_IRQ_FRAMEDONE (1 << 0) | |
27 | #define DISPC_IRQ_VSYNC (1 << 1) | |
28 | #define DISPC_IRQ_EVSYNC_EVEN (1 << 2) | |
29 | #define DISPC_IRQ_EVSYNC_ODD (1 << 3) | |
30 | #define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4) | |
31 | #define DISPC_IRQ_PROG_LINE_NUM (1 << 5) | |
32 | #define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6) | |
33 | #define DISPC_IRQ_GFX_END_WIN (1 << 7) | |
34 | #define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8) | |
35 | #define DISPC_IRQ_OCP_ERR (1 << 9) | |
36 | #define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10) | |
37 | #define DISPC_IRQ_VID1_END_WIN (1 << 11) | |
38 | #define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12) | |
39 | #define DISPC_IRQ_VID2_END_WIN (1 << 13) | |
40 | #define DISPC_IRQ_SYNC_LOST (1 << 14) | |
41 | #define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15) | |
42 | #define DISPC_IRQ_WAKEUP (1 << 16) | |
2a205f34 SS |
43 | #define DISPC_IRQ_SYNC_LOST2 (1 << 17) |
44 | #define DISPC_IRQ_VSYNC2 (1 << 18) | |
b8c095b4 AT |
45 | #define DISPC_IRQ_VID3_END_WIN (1 << 19) |
46 | #define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20) | |
2a205f34 SS |
47 | #define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21) |
48 | #define DISPC_IRQ_FRAMEDONE2 (1 << 22) | |
7f6f3c4b TV |
49 | #define DISPC_IRQ_FRAMEDONEWB (1 << 23) |
50 | #define DISPC_IRQ_FRAMEDONETV (1 << 24) | |
51 | #define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25) | |
14d33d38 CM |
52 | #define DISPC_IRQ_SYNC_LOST3 (1 << 27) |
53 | #define DISPC_IRQ_VSYNC3 (1 << 28) | |
54 | #define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 29) | |
55 | #define DISPC_IRQ_FRAMEDONE3 (1 << 30) | |
559d6701 TV |
56 | |
57 | struct omap_dss_device; | |
58 | struct omap_overlay_manager; | |
a97a9634 | 59 | struct dss_lcd_mgr_config; |
9c0b8420 RN |
60 | struct snd_aes_iec958; |
61 | struct snd_cea_861_aud_if; | |
559d6701 TV |
62 | |
63 | enum omap_display_type { | |
64 | OMAP_DISPLAY_TYPE_NONE = 0, | |
65 | OMAP_DISPLAY_TYPE_DPI = 1 << 0, | |
66 | OMAP_DISPLAY_TYPE_DBI = 1 << 1, | |
67 | OMAP_DISPLAY_TYPE_SDI = 1 << 2, | |
68 | OMAP_DISPLAY_TYPE_DSI = 1 << 3, | |
69 | OMAP_DISPLAY_TYPE_VENC = 1 << 4, | |
b119601d | 70 | OMAP_DISPLAY_TYPE_HDMI = 1 << 5, |
559d6701 TV |
71 | }; |
72 | ||
73 | enum omap_plane { | |
74 | OMAP_DSS_GFX = 0, | |
75 | OMAP_DSS_VIDEO1 = 1, | |
b8c095b4 AT |
76 | OMAP_DSS_VIDEO2 = 2, |
77 | OMAP_DSS_VIDEO3 = 3, | |
66a0f9e4 | 78 | OMAP_DSS_WB = 4, |
559d6701 TV |
79 | }; |
80 | ||
81 | enum omap_channel { | |
82 | OMAP_DSS_CHANNEL_LCD = 0, | |
83 | OMAP_DSS_CHANNEL_DIGIT = 1, | |
8613b000 | 84 | OMAP_DSS_CHANNEL_LCD2 = 2, |
ff6331e2 | 85 | OMAP_DSS_CHANNEL_LCD3 = 3, |
559d6701 TV |
86 | }; |
87 | ||
88 | enum omap_color_mode { | |
89 | OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */ | |
90 | OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */ | |
91 | OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */ | |
92 | OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */ | |
93 | OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */ | |
94 | OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */ | |
95 | OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */ | |
96 | OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */ | |
97 | OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */ | |
98 | OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */ | |
99 | OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */ | |
100 | OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */ | |
101 | OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */ | |
102 | OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */ | |
f20e4220 AJ |
103 | OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */ |
104 | OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */ | |
105 | OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */ | |
106 | OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */ | |
107 | OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */ | |
559d6701 TV |
108 | }; |
109 | ||
559d6701 TV |
110 | enum omap_dss_load_mode { |
111 | OMAP_DSS_LOAD_CLUT_AND_FRAME = 0, | |
112 | OMAP_DSS_LOAD_CLUT_ONLY = 1, | |
113 | OMAP_DSS_LOAD_FRAME_ONLY = 2, | |
114 | OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3, | |
115 | }; | |
116 | ||
117 | enum omap_dss_trans_key_type { | |
118 | OMAP_DSS_COLOR_KEY_GFX_DST = 0, | |
119 | OMAP_DSS_COLOR_KEY_VID_SRC = 1, | |
120 | }; | |
121 | ||
122 | enum omap_rfbi_te_mode { | |
123 | OMAP_DSS_RFBI_TE_MODE_1 = 1, | |
124 | OMAP_DSS_RFBI_TE_MODE_2 = 2, | |
125 | }; | |
126 | ||
a8d5e41c AT |
127 | enum omap_dss_signal_level { |
128 | OMAPDSS_SIG_ACTIVE_HIGH = 0, | |
129 | OMAPDSS_SIG_ACTIVE_LOW = 1, | |
130 | }; | |
131 | ||
132 | enum omap_dss_signal_edge { | |
133 | OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES, | |
134 | OMAPDSS_DRIVE_SIG_RISING_EDGE, | |
135 | OMAPDSS_DRIVE_SIG_FALLING_EDGE, | |
136 | }; | |
137 | ||
559d6701 TV |
138 | enum omap_dss_venc_type { |
139 | OMAP_DSS_VENC_TYPE_COMPOSITE, | |
140 | OMAP_DSS_VENC_TYPE_SVIDEO, | |
141 | }; | |
142 | ||
a3b3cc2b AT |
143 | enum omap_dss_dsi_pixel_format { |
144 | OMAP_DSS_DSI_FMT_RGB888, | |
145 | OMAP_DSS_DSI_FMT_RGB666, | |
146 | OMAP_DSS_DSI_FMT_RGB666_PACKED, | |
147 | OMAP_DSS_DSI_FMT_RGB565, | |
148 | }; | |
149 | ||
7e951ee9 AT |
150 | enum omap_dss_dsi_mode { |
151 | OMAP_DSS_DSI_CMD_MODE = 0, | |
152 | OMAP_DSS_DSI_VIDEO_MODE, | |
153 | }; | |
154 | ||
559d6701 TV |
155 | enum omap_display_caps { |
156 | OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0, | |
157 | OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1, | |
158 | }; | |
159 | ||
559d6701 TV |
160 | enum omap_dss_display_state { |
161 | OMAP_DSS_DISPLAY_DISABLED = 0, | |
162 | OMAP_DSS_DISPLAY_ACTIVE, | |
559d6701 TV |
163 | }; |
164 | ||
9c0b8420 RN |
165 | enum omap_dss_audio_state { |
166 | OMAP_DSS_AUDIO_DISABLED = 0, | |
167 | OMAP_DSS_AUDIO_ENABLED, | |
168 | OMAP_DSS_AUDIO_CONFIGURED, | |
169 | OMAP_DSS_AUDIO_PLAYING, | |
170 | }; | |
171 | ||
559d6701 | 172 | enum omap_dss_rotation_type { |
65e006ff CM |
173 | OMAP_DSS_ROT_DMA = 1 << 0, |
174 | OMAP_DSS_ROT_VRFB = 1 << 1, | |
175 | OMAP_DSS_ROT_TILER = 1 << 2, | |
559d6701 TV |
176 | }; |
177 | ||
178 | /* clockwise rotation angle */ | |
179 | enum omap_dss_rotation_angle { | |
180 | OMAP_DSS_ROT_0 = 0, | |
181 | OMAP_DSS_ROT_90 = 1, | |
182 | OMAP_DSS_ROT_180 = 2, | |
183 | OMAP_DSS_ROT_270 = 3, | |
184 | }; | |
185 | ||
186 | enum omap_overlay_caps { | |
187 | OMAP_DSS_OVL_CAP_SCALE = 1 << 0, | |
f6dc8150 TV |
188 | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1, |
189 | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2, | |
11354dd5 | 190 | OMAP_DSS_OVL_CAP_ZORDER = 1 << 3, |
d79db853 AT |
191 | OMAP_DSS_OVL_CAP_POS = 1 << 4, |
192 | OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5, | |
559d6701 TV |
193 | }; |
194 | ||
195 | enum omap_overlay_manager_caps { | |
4a9e78ab | 196 | OMAP_DSS_DUMMY_VALUE, /* add a dummy value to prevent compiler error */ |
559d6701 TV |
197 | }; |
198 | ||
89a35e51 AT |
199 | enum omap_dss_clk_source { |
200 | OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK | |
201 | * OMAP4: DSS_FCLK */ | |
202 | OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK | |
203 | * OMAP4: PLL1_CLK1 */ | |
204 | OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK | |
205 | * OMAP4: PLL1_CLK2 */ | |
5a8b572d AT |
206 | OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */ |
207 | OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */ | |
89a35e51 AT |
208 | }; |
209 | ||
9a901683 M |
210 | enum omap_hdmi_flags { |
211 | OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP = 1 << 0, | |
212 | }; | |
213 | ||
484dc404 AT |
214 | enum omap_dss_output_id { |
215 | OMAP_DSS_OUTPUT_DPI = 1 << 0, | |
216 | OMAP_DSS_OUTPUT_DBI = 1 << 1, | |
217 | OMAP_DSS_OUTPUT_SDI = 1 << 2, | |
218 | OMAP_DSS_OUTPUT_DSI1 = 1 << 3, | |
219 | OMAP_DSS_OUTPUT_DSI2 = 1 << 4, | |
220 | OMAP_DSS_OUTPUT_VENC = 1 << 5, | |
221 | OMAP_DSS_OUTPUT_HDMI = 1 << 6, | |
222 | }; | |
223 | ||
559d6701 TV |
224 | /* RFBI */ |
225 | ||
226 | struct rfbi_timings { | |
227 | int cs_on_time; | |
228 | int cs_off_time; | |
229 | int we_on_time; | |
230 | int we_off_time; | |
231 | int re_on_time; | |
232 | int re_off_time; | |
233 | int we_cycle_time; | |
234 | int re_cycle_time; | |
235 | int cs_pulse_width; | |
236 | int access_time; | |
237 | ||
238 | int clk_div; | |
239 | ||
240 | u32 tim[5]; /* set by rfbi_convert_timings() */ | |
241 | ||
242 | int converted; | |
243 | }; | |
244 | ||
245 | void omap_rfbi_write_command(const void *buf, u32 len); | |
246 | void omap_rfbi_read_data(void *buf, u32 len); | |
247 | void omap_rfbi_write_data(const void *buf, u32 len); | |
248 | void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width, | |
249 | u16 x, u16 y, | |
250 | u16 w, u16 h); | |
251 | int omap_rfbi_enable_te(bool enable, unsigned line); | |
252 | int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode, | |
253 | unsigned hs_pulse_time, unsigned vs_pulse_time, | |
254 | int hs_pol_inv, int vs_pol_inv, int extif_div); | |
773139f1 TV |
255 | void rfbi_bus_lock(void); |
256 | void rfbi_bus_unlock(void); | |
559d6701 TV |
257 | |
258 | /* DSI */ | |
8af6ff01 | 259 | |
478d7df8 TV |
260 | enum omap_dss_dsi_trans_mode { |
261 | /* Sync Pulses: both sync start and end packets sent */ | |
262 | OMAP_DSS_DSI_PULSE_MODE, | |
263 | /* Sync Events: only sync start packets sent */ | |
264 | OMAP_DSS_DSI_EVENT_MODE, | |
265 | /* Burst: only sync start packets sent, pixels are time compressed */ | |
266 | OMAP_DSS_DSI_BURST_MODE, | |
267 | }; | |
268 | ||
6b849375 | 269 | struct omap_dss_dsi_videomode_timings { |
f1e0001f TV |
270 | unsigned long hsclk; |
271 | ||
272 | unsigned ndl; | |
273 | unsigned bitspp; | |
274 | ||
275 | /* pixels */ | |
276 | u16 hact; | |
277 | /* lines */ | |
278 | u16 vact; | |
279 | ||
8af6ff01 AT |
280 | /* DSI video mode blanking data */ |
281 | /* Unit: byte clock cycles */ | |
f1e0001f | 282 | u16 hss; |
8af6ff01 | 283 | u16 hsa; |
f1e0001f | 284 | u16 hse; |
8af6ff01 AT |
285 | u16 hfp; |
286 | u16 hbp; | |
287 | /* Unit: line clocks */ | |
288 | u16 vsa; | |
289 | u16 vfp; | |
290 | u16 vbp; | |
291 | ||
292 | /* DSI blanking modes */ | |
293 | int blanking_mode; | |
294 | int hsa_blanking_mode; | |
295 | int hbp_blanking_mode; | |
296 | int hfp_blanking_mode; | |
297 | ||
478d7df8 | 298 | enum omap_dss_dsi_trans_mode trans_mode; |
8af6ff01 AT |
299 | |
300 | bool ddr_clk_always_on; | |
301 | int window_sync; | |
302 | }; | |
303 | ||
777f05cc TV |
304 | struct omap_dss_dsi_config { |
305 | enum omap_dss_dsi_mode mode; | |
306 | enum omap_dss_dsi_pixel_format pixel_format; | |
307 | const struct omap_video_timings *timings; | |
777f05cc | 308 | |
f1e0001f TV |
309 | unsigned long hs_clk_min, hs_clk_max; |
310 | unsigned long lp_clk_min, lp_clk_max; | |
311 | ||
312 | bool ddr_clk_always_on; | |
313 | enum omap_dss_dsi_trans_mode trans_mode; | |
777f05cc TV |
314 | }; |
315 | ||
1ffefe75 AT |
316 | void dsi_bus_lock(struct omap_dss_device *dssdev); |
317 | void dsi_bus_unlock(struct omap_dss_device *dssdev); | |
318 | int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data, | |
319 | int len); | |
6ff8aa31 AT |
320 | int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data, |
321 | int len); | |
322 | int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd); | |
323 | int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel); | |
1ffefe75 AT |
324 | int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, |
325 | u8 param); | |
6ff8aa31 AT |
326 | int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel, |
327 | u8 param); | |
328 | int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel, | |
329 | u8 param1, u8 param2); | |
1ffefe75 AT |
330 | int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel, |
331 | u8 *data, int len); | |
6ff8aa31 AT |
332 | int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel, |
333 | u8 *data, int len); | |
1ffefe75 AT |
334 | int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, |
335 | u8 *buf, int buflen); | |
b3b89c05 AT |
336 | int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf, |
337 | int buflen); | |
338 | int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param, | |
339 | u8 *buf, int buflen); | |
340 | int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel, | |
341 | u8 param1, u8 param2, u8 *buf, int buflen); | |
1ffefe75 AT |
342 | int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel, |
343 | u16 len); | |
344 | int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel); | |
345 | int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel); | |
9a147a65 TV |
346 | int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel); |
347 | void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel); | |
559d6701 | 348 | |
acd18af9 TV |
349 | enum omapdss_version { |
350 | OMAPDSS_VER_UNKNOWN = 0, | |
351 | OMAPDSS_VER_OMAP24xx, | |
352 | OMAPDSS_VER_OMAP34xx_ES1, /* OMAP3430 ES1.0, 2.0 */ | |
353 | OMAPDSS_VER_OMAP34xx_ES3, /* OMAP3430 ES3.0+ */ | |
354 | OMAPDSS_VER_OMAP3630, | |
355 | OMAPDSS_VER_AM35xx, | |
356 | OMAPDSS_VER_OMAP4430_ES1, /* OMAP4430 ES1.0 */ | |
357 | OMAPDSS_VER_OMAP4430_ES2, /* OMAP4430 ES2.0, 2.1, 2.2 */ | |
358 | OMAPDSS_VER_OMAP4, /* All other OMAP4s */ | |
359 | OMAPDSS_VER_OMAP5, | |
360 | }; | |
361 | ||
559d6701 TV |
362 | /* Board specific data */ |
363 | struct omap_dss_board_info { | |
aac927c9 | 364 | int (*get_context_loss_count)(struct device *dev); |
559d6701 TV |
365 | int num_devices; |
366 | struct omap_dss_device **devices; | |
367 | struct omap_dss_device *default_device; | |
5bc416cb TV |
368 | int (*dsi_enable_pads)(int dsi_id, unsigned lane_mask); |
369 | void (*dsi_disable_pads)(int dsi_id, unsigned lane_mask); | |
62c1dcfc | 370 | int (*set_min_bus_tput)(struct device *dev, unsigned long r); |
acd18af9 | 371 | enum omapdss_version version; |
559d6701 TV |
372 | }; |
373 | ||
b7ee79ab SS |
374 | /* Init with the board info */ |
375 | extern int omap_display_init(struct omap_dss_board_info *board_data); | |
ee9dfd82 | 376 | /* HDMI mux init*/ |
9a901683 | 377 | extern int omap_hdmi_init(enum omap_hdmi_flags flags); |
b7ee79ab | 378 | |
559d6701 TV |
379 | struct omap_video_timings { |
380 | /* Unit: pixels */ | |
381 | u16 x_res; | |
382 | /* Unit: pixels */ | |
383 | u16 y_res; | |
384 | /* Unit: KHz */ | |
385 | u32 pixel_clock; | |
386 | /* Unit: pixel clocks */ | |
387 | u16 hsw; /* Horizontal synchronization pulse width */ | |
388 | /* Unit: pixel clocks */ | |
389 | u16 hfp; /* Horizontal front porch */ | |
390 | /* Unit: pixel clocks */ | |
391 | u16 hbp; /* Horizontal back porch */ | |
392 | /* Unit: line clocks */ | |
393 | u16 vsw; /* Vertical synchronization pulse width */ | |
394 | /* Unit: line clocks */ | |
395 | u16 vfp; /* Vertical front porch */ | |
396 | /* Unit: line clocks */ | |
397 | u16 vbp; /* Vertical back porch */ | |
a8d5e41c AT |
398 | |
399 | /* Vsync logic level */ | |
400 | enum omap_dss_signal_level vsync_level; | |
401 | /* Hsync logic level */ | |
402 | enum omap_dss_signal_level hsync_level; | |
23c8f88e AT |
403 | /* Interlaced or Progressive timings */ |
404 | bool interlace; | |
a8d5e41c AT |
405 | /* Pixel clock edge to drive LCD data */ |
406 | enum omap_dss_signal_edge data_pclk_edge; | |
407 | /* Data enable logic level */ | |
408 | enum omap_dss_signal_level de_level; | |
409 | /* Pixel clock edges to drive HSYNC and VSYNC signals */ | |
410 | enum omap_dss_signal_edge sync_pclk_edge; | |
559d6701 TV |
411 | }; |
412 | ||
413 | #ifdef CONFIG_OMAP2_DSS_VENC | |
414 | /* Hardcoded timings for tv modes. Venc only uses these to | |
415 | * identify the mode, and does not actually use the configs | |
416 | * itself. However, the configs should be something that | |
417 | * a normal monitor can also show */ | |
5a1819e3 TK |
418 | extern const struct omap_video_timings omap_dss_pal_timings; |
419 | extern const struct omap_video_timings omap_dss_ntsc_timings; | |
559d6701 TV |
420 | #endif |
421 | ||
3c07cae2 TV |
422 | struct omap_dss_cpr_coefs { |
423 | s16 rr, rg, rb; | |
424 | s16 gr, gg, gb; | |
425 | s16 br, bg, bb; | |
426 | }; | |
427 | ||
559d6701 | 428 | struct omap_overlay_info { |
559d6701 | 429 | u32 paddr; |
0d66cbb5 | 430 | u32 p_uv_addr; /* for NV12 format */ |
559d6701 TV |
431 | u16 screen_width; |
432 | u16 width; | |
433 | u16 height; | |
434 | enum omap_color_mode color_mode; | |
435 | u8 rotation; | |
436 | enum omap_dss_rotation_type rotation_type; | |
437 | bool mirror; | |
438 | ||
439 | u16 pos_x; | |
440 | u16 pos_y; | |
441 | u16 out_width; /* if 0, out_width == width */ | |
442 | u16 out_height; /* if 0, out_height == height */ | |
443 | u8 global_alpha; | |
fd28a390 | 444 | u8 pre_mult_alpha; |
54128701 | 445 | u8 zorder; |
559d6701 TV |
446 | }; |
447 | ||
448 | struct omap_overlay { | |
449 | struct kobject kobj; | |
450 | struct list_head list; | |
451 | ||
452 | /* static fields */ | |
453 | const char *name; | |
4a9e78ab | 454 | enum omap_plane id; |
559d6701 TV |
455 | enum omap_color_mode supported_modes; |
456 | enum omap_overlay_caps caps; | |
457 | ||
458 | /* dynamic fields */ | |
459 | struct omap_overlay_manager *manager; | |
559d6701 | 460 | |
9d11c321 TV |
461 | /* |
462 | * The following functions do not block: | |
463 | * | |
464 | * is_enabled | |
465 | * set_overlay_info | |
466 | * get_overlay_info | |
467 | * | |
468 | * The rest of the functions may block and cannot be called from | |
469 | * interrupt context | |
470 | */ | |
471 | ||
aaa874a9 TV |
472 | int (*enable)(struct omap_overlay *ovl); |
473 | int (*disable)(struct omap_overlay *ovl); | |
474 | bool (*is_enabled)(struct omap_overlay *ovl); | |
475 | ||
559d6701 TV |
476 | int (*set_manager)(struct omap_overlay *ovl, |
477 | struct omap_overlay_manager *mgr); | |
478 | int (*unset_manager)(struct omap_overlay *ovl); | |
479 | ||
480 | int (*set_overlay_info)(struct omap_overlay *ovl, | |
481 | struct omap_overlay_info *info); | |
482 | void (*get_overlay_info)(struct omap_overlay *ovl, | |
483 | struct omap_overlay_info *info); | |
484 | ||
485 | int (*wait_for_go)(struct omap_overlay *ovl); | |
794bc4ee AT |
486 | |
487 | struct omap_dss_device *(*get_device)(struct omap_overlay *ovl); | |
559d6701 TV |
488 | }; |
489 | ||
490 | struct omap_overlay_manager_info { | |
491 | u32 default_color; | |
492 | ||
493 | enum omap_dss_trans_key_type trans_key_type; | |
494 | u32 trans_key; | |
495 | bool trans_enabled; | |
496 | ||
11354dd5 | 497 | bool partial_alpha_enabled; |
3c07cae2 TV |
498 | |
499 | bool cpr_enable; | |
500 | struct omap_dss_cpr_coefs cpr_coefs; | |
559d6701 TV |
501 | }; |
502 | ||
503 | struct omap_overlay_manager { | |
504 | struct kobject kobj; | |
559d6701 TV |
505 | |
506 | /* static fields */ | |
507 | const char *name; | |
4a9e78ab | 508 | enum omap_channel id; |
559d6701 | 509 | enum omap_overlay_manager_caps caps; |
07e327c9 | 510 | struct list_head overlays; |
559d6701 | 511 | enum omap_display_type supported_displays; |
97f01b3a | 512 | enum omap_dss_output_id supported_outputs; |
559d6701 TV |
513 | |
514 | /* dynamic fields */ | |
97f01b3a | 515 | struct omap_dss_output *output; |
559d6701 | 516 | |
9d11c321 TV |
517 | /* |
518 | * The following functions do not block: | |
519 | * | |
520 | * set_manager_info | |
521 | * get_manager_info | |
522 | * apply | |
523 | * | |
524 | * The rest of the functions may block and cannot be called from | |
525 | * interrupt context | |
526 | */ | |
527 | ||
97f01b3a AT |
528 | int (*set_output)(struct omap_overlay_manager *mgr, |
529 | struct omap_dss_output *output); | |
530 | int (*unset_output)(struct omap_overlay_manager *mgr); | |
559d6701 TV |
531 | |
532 | int (*set_manager_info)(struct omap_overlay_manager *mgr, | |
533 | struct omap_overlay_manager_info *info); | |
534 | void (*get_manager_info)(struct omap_overlay_manager *mgr, | |
535 | struct omap_overlay_manager_info *info); | |
536 | ||
537 | int (*apply)(struct omap_overlay_manager *mgr); | |
538 | int (*wait_for_go)(struct omap_overlay_manager *mgr); | |
3f71cbe7 | 539 | int (*wait_for_vsync)(struct omap_overlay_manager *mgr); |
794bc4ee AT |
540 | |
541 | struct omap_dss_device *(*get_device)(struct omap_overlay_manager *mgr); | |
559d6701 TV |
542 | }; |
543 | ||
e4a9e94c TV |
544 | /* 22 pins means 1 clk lane and 10 data lanes */ |
545 | #define OMAP_DSS_MAX_DSI_PINS 22 | |
546 | ||
547 | struct omap_dsi_pin_config { | |
548 | int num_pins; | |
549 | /* | |
550 | * pin numbers in the following order: | |
551 | * clk+, clk- | |
552 | * data1+, data1- | |
553 | * data2+, data2- | |
554 | * ... | |
555 | */ | |
556 | int pins[OMAP_DSS_MAX_DSI_PINS]; | |
557 | }; | |
558 | ||
749feffa AT |
559 | struct omap_dss_writeback_info { |
560 | u32 paddr; | |
561 | u32 p_uv_addr; | |
562 | u16 buf_width; | |
563 | u16 width; | |
564 | u16 height; | |
565 | enum omap_color_mode color_mode; | |
566 | u8 rotation; | |
567 | enum omap_dss_rotation_type rotation_type; | |
568 | bool mirror; | |
569 | u8 pre_mult_alpha; | |
570 | }; | |
571 | ||
484dc404 AT |
572 | struct omap_dss_output { |
573 | struct list_head list; | |
574 | ||
7286a08f TV |
575 | const char *name; |
576 | ||
484dc404 AT |
577 | /* display type supported by the output */ |
578 | enum omap_display_type type; | |
579 | ||
2eea5ae6 TV |
580 | /* DISPC channel for this output */ |
581 | enum omap_channel dispc_channel; | |
582 | ||
484dc404 AT |
583 | /* output instance */ |
584 | enum omap_dss_output_id id; | |
585 | ||
586 | /* output's platform device pointer */ | |
587 | struct platform_device *pdev; | |
588 | ||
589 | /* dynamic fields */ | |
590 | struct omap_overlay_manager *manager; | |
591 | ||
592 | struct omap_dss_device *device; | |
593 | }; | |
594 | ||
559d6701 TV |
595 | struct omap_dss_device { |
596 | struct device dev; | |
597 | ||
598 | enum omap_display_type type; | |
599 | ||
2eea5ae6 | 600 | /* obsolete, to be removed */ |
18faa1b6 SS |
601 | enum omap_channel channel; |
602 | ||
559d6701 TV |
603 | union { |
604 | struct { | |
605 | u8 data_lines; | |
606 | } dpi; | |
607 | ||
608 | struct { | |
609 | u8 channel; | |
610 | u8 data_lines; | |
611 | } rfbi; | |
612 | ||
613 | struct { | |
614 | u8 datapairs; | |
615 | } sdi; | |
616 | ||
617 | struct { | |
a72b64b9 AT |
618 | int module; |
619 | ||
559d6701 TV |
620 | bool ext_te; |
621 | u8 ext_te_gpio; | |
622 | } dsi; | |
623 | ||
624 | struct { | |
625 | enum omap_dss_venc_type type; | |
626 | bool invert_polarity; | |
627 | } venc; | |
628 | } phy; | |
629 | ||
630 | struct { | |
631 | struct omap_video_timings timings; | |
632 | ||
a3b3cc2b | 633 | enum omap_dss_dsi_pixel_format dsi_pix_fmt; |
7e951ee9 | 634 | enum omap_dss_dsi_mode dsi_mode; |
559d6701 TV |
635 | } panel; |
636 | ||
637 | struct { | |
638 | u8 pixel_size; | |
639 | struct rfbi_timings rfbi_timings; | |
559d6701 TV |
640 | } ctrl; |
641 | ||
642 | int reset_gpio; | |
643 | ||
644 | int max_backlight_level; | |
645 | ||
646 | const char *name; | |
647 | ||
648 | /* used to match device to driver */ | |
649 | const char *driver_name; | |
650 | ||
651 | void *data; | |
652 | ||
653 | struct omap_dss_driver *driver; | |
654 | ||
655 | /* helper variable for driver suspend/resume */ | |
656 | bool activate_after_resume; | |
657 | ||
658 | enum omap_display_caps caps; | |
659 | ||
6d71b923 | 660 | struct omap_dss_output *output; |
559d6701 TV |
661 | |
662 | enum omap_dss_display_state state; | |
663 | ||
9c0b8420 RN |
664 | enum omap_dss_audio_state audio_state; |
665 | ||
559d6701 TV |
666 | /* platform specific */ |
667 | int (*platform_enable)(struct omap_dss_device *dssdev); | |
668 | void (*platform_disable)(struct omap_dss_device *dssdev); | |
669 | int (*set_backlight)(struct omap_dss_device *dssdev, int level); | |
670 | int (*get_backlight)(struct omap_dss_device *dssdev); | |
671 | }; | |
672 | ||
c49d005b TV |
673 | struct omap_dss_hdmi_data |
674 | { | |
cca35017 TV |
675 | int ct_cp_hpd_gpio; |
676 | int ls_oe_gpio; | |
c49d005b TV |
677 | int hpd_gpio; |
678 | }; | |
679 | ||
9c0b8420 RN |
680 | struct omap_dss_audio { |
681 | struct snd_aes_iec958 *iec; | |
682 | struct snd_cea_861_aud_if *cea; | |
683 | }; | |
684 | ||
559d6701 TV |
685 | struct omap_dss_driver { |
686 | struct device_driver driver; | |
687 | ||
688 | int (*probe)(struct omap_dss_device *); | |
689 | void (*remove)(struct omap_dss_device *); | |
690 | ||
691 | int (*enable)(struct omap_dss_device *display); | |
692 | void (*disable)(struct omap_dss_device *display); | |
559d6701 TV |
693 | int (*run_test)(struct omap_dss_device *display, int test); |
694 | ||
18946f62 TV |
695 | int (*update)(struct omap_dss_device *dssdev, |
696 | u16 x, u16 y, u16 w, u16 h); | |
697 | int (*sync)(struct omap_dss_device *dssdev); | |
698 | ||
559d6701 | 699 | int (*enable_te)(struct omap_dss_device *dssdev, bool enable); |
225b650d | 700 | int (*get_te)(struct omap_dss_device *dssdev); |
559d6701 TV |
701 | |
702 | u8 (*get_rotate)(struct omap_dss_device *dssdev); | |
703 | int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate); | |
704 | ||
705 | bool (*get_mirror)(struct omap_dss_device *dssdev); | |
706 | int (*set_mirror)(struct omap_dss_device *dssdev, bool enable); | |
707 | ||
708 | int (*memory_read)(struct omap_dss_device *dssdev, | |
709 | void *buf, size_t size, | |
710 | u16 x, u16 y, u16 w, u16 h); | |
96adcece TV |
711 | |
712 | void (*get_resolution)(struct omap_dss_device *dssdev, | |
713 | u16 *xres, u16 *yres); | |
7a0987bf JN |
714 | void (*get_dimensions)(struct omap_dss_device *dssdev, |
715 | u32 *width, u32 *height); | |
a2699504 | 716 | int (*get_recommended_bpp)(struct omap_dss_device *dssdev); |
36511312 | 717 | |
69b2048f TV |
718 | int (*check_timings)(struct omap_dss_device *dssdev, |
719 | struct omap_video_timings *timings); | |
720 | void (*set_timings)(struct omap_dss_device *dssdev, | |
721 | struct omap_video_timings *timings); | |
722 | void (*get_timings)(struct omap_dss_device *dssdev, | |
723 | struct omap_video_timings *timings); | |
724 | ||
36511312 TV |
725 | int (*set_wss)(struct omap_dss_device *dssdev, u32 wss); |
726 | u32 (*get_wss)(struct omap_dss_device *dssdev); | |
3d5e0ef7 TV |
727 | |
728 | int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len); | |
df4769c9 | 729 | bool (*detect)(struct omap_dss_device *dssdev); |
9c0b8420 RN |
730 | |
731 | /* | |
732 | * For display drivers that support audio. This encompasses | |
733 | * HDMI and DisplayPort at the moment. | |
734 | */ | |
735 | /* | |
736 | * Note: These functions might sleep. Do not call while | |
737 | * holding a spinlock/readlock. | |
738 | */ | |
739 | int (*audio_enable)(struct omap_dss_device *dssdev); | |
740 | void (*audio_disable)(struct omap_dss_device *dssdev); | |
741 | bool (*audio_supported)(struct omap_dss_device *dssdev); | |
742 | int (*audio_config)(struct omap_dss_device *dssdev, | |
743 | struct omap_dss_audio *audio); | |
744 | /* Note: These functions may not sleep */ | |
745 | int (*audio_start)(struct omap_dss_device *dssdev); | |
746 | void (*audio_stop)(struct omap_dss_device *dssdev); | |
747 | ||
559d6701 TV |
748 | }; |
749 | ||
b2c7d54f | 750 | enum omapdss_version omapdss_get_version(void); |
591a0ac7 | 751 | bool omapdss_is_initialized(void); |
b2c7d54f | 752 | |
559d6701 TV |
753 | int omap_dss_register_driver(struct omap_dss_driver *); |
754 | void omap_dss_unregister_driver(struct omap_dss_driver *); | |
755 | ||
559d6701 TV |
756 | void omap_dss_get_device(struct omap_dss_device *dssdev); |
757 | void omap_dss_put_device(struct omap_dss_device *dssdev); | |
758 | #define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL) | |
759 | struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from); | |
760 | struct omap_dss_device *omap_dss_find_device(void *data, | |
761 | int (*match)(struct omap_dss_device *dssdev, void *data)); | |
2bbcce5e | 762 | const char *omapdss_get_default_display_name(void); |
559d6701 TV |
763 | |
764 | int omap_dss_start_device(struct omap_dss_device *dssdev); | |
765 | void omap_dss_stop_device(struct omap_dss_device *dssdev); | |
766 | ||
eda34273 TV |
767 | int dss_feat_get_num_mgrs(void); |
768 | int dss_feat_get_num_ovls(void); | |
769 | enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel); | |
770 | enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel); | |
771 | enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane); | |
772 | ||
773 | ||
774 | ||
559d6701 TV |
775 | int omap_dss_get_num_overlay_managers(void); |
776 | struct omap_overlay_manager *omap_dss_get_overlay_manager(int num); | |
777 | ||
778 | int omap_dss_get_num_overlays(void); | |
779 | struct omap_overlay *omap_dss_get_overlay(int num); | |
780 | ||
484dc404 | 781 | struct omap_dss_output *omap_dss_get_output(enum omap_dss_output_id id); |
6d71b923 AT |
782 | int omapdss_output_set_device(struct omap_dss_output *out, |
783 | struct omap_dss_device *dssdev); | |
784 | int omapdss_output_unset_device(struct omap_dss_output *out); | |
484dc404 | 785 | |
96adcece TV |
786 | void omapdss_default_get_resolution(struct omap_dss_device *dssdev, |
787 | u16 *xres, u16 *yres); | |
a2699504 | 788 | int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev); |
4b6430fc GI |
789 | void omapdss_default_get_timings(struct omap_dss_device *dssdev, |
790 | struct omap_video_timings *timings); | |
a2699504 | 791 | |
559d6701 TV |
792 | typedef void (*omap_dispc_isr_t) (void *arg, u32 mask); |
793 | int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask); | |
794 | int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask); | |
795 | ||
348be69d TV |
796 | u32 dispc_read_irqstatus(void); |
797 | void dispc_clear_irqstatus(u32 mask); | |
798 | u32 dispc_read_irqenable(void); | |
799 | void dispc_write_irqenable(u32 mask); | |
800 | ||
801 | int dispc_request_irq(irq_handler_t handler, void *dev_id); | |
802 | void dispc_free_irq(void *dev_id); | |
803 | ||
804 | int dispc_runtime_get(void); | |
805 | void dispc_runtime_put(void); | |
806 | ||
807 | void dispc_mgr_enable(enum omap_channel channel, bool enable); | |
808 | bool dispc_mgr_is_enabled(enum omap_channel channel); | |
809 | u32 dispc_mgr_get_vsync_irq(enum omap_channel channel); | |
810 | u32 dispc_mgr_get_framedone_irq(enum omap_channel channel); | |
811 | u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel); | |
812 | bool dispc_mgr_go_busy(enum omap_channel channel); | |
813 | void dispc_mgr_go(enum omap_channel channel); | |
814 | void dispc_mgr_set_lcd_config(enum omap_channel channel, | |
815 | const struct dss_lcd_mgr_config *config); | |
816 | void dispc_mgr_set_timings(enum omap_channel channel, | |
817 | const struct omap_video_timings *timings); | |
818 | void dispc_mgr_setup(enum omap_channel channel, | |
819 | const struct omap_overlay_manager_info *info); | |
820 | ||
821 | int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel, | |
822 | const struct omap_overlay_info *oi, | |
823 | const struct omap_video_timings *timings, | |
824 | int *x_predecim, int *y_predecim); | |
825 | ||
826 | int dispc_ovl_enable(enum omap_plane plane, bool enable); | |
827 | bool dispc_ovl_enabled(enum omap_plane plane); | |
828 | void dispc_ovl_set_channel_out(enum omap_plane plane, | |
829 | enum omap_channel channel); | |
830 | int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi, | |
831 | bool replication, const struct omap_video_timings *mgr_timings, | |
832 | bool mem_to_mem); | |
833 | ||
559d6701 TV |
834 | #define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver) |
835 | #define to_dss_device(x) container_of((x), struct omap_dss_device, dev) | |
836 | ||
1ffefe75 AT |
837 | void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel, |
838 | bool enable); | |
225b650d | 839 | int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable); |
777f05cc TV |
840 | int omapdss_dsi_set_config(struct omap_dss_device *dssdev, |
841 | const struct omap_dss_dsi_config *config); | |
61140c9a | 842 | |
5476e74a | 843 | int omap_dsi_update(struct omap_dss_device *dssdev, int channel, |
18946f62 | 844 | void (*callback)(int, void *), void *data); |
5ee3c144 AT |
845 | int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel); |
846 | int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id); | |
847 | void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel); | |
e4a9e94c TV |
848 | int omapdss_dsi_configure_pins(struct omap_dss_device *dssdev, |
849 | const struct omap_dsi_pin_config *pin_cfg); | |
18946f62 | 850 | |
37ac60e4 | 851 | int omapdss_dsi_display_enable(struct omap_dss_device *dssdev); |
2a89dc15 | 852 | void omapdss_dsi_display_disable(struct omap_dss_device *dssdev, |
22d6d676 | 853 | bool disconnect_lanes, bool enter_ulps); |
37ac60e4 TV |
854 | |
855 | int omapdss_dpi_display_enable(struct omap_dss_device *dssdev); | |
856 | void omapdss_dpi_display_disable(struct omap_dss_device *dssdev); | |
c499144c AT |
857 | void omapdss_dpi_set_timings(struct omap_dss_device *dssdev, |
858 | struct omap_video_timings *timings); | |
69b2048f TV |
859 | int dpi_check_timings(struct omap_dss_device *dssdev, |
860 | struct omap_video_timings *timings); | |
c6b393d4 | 861 | void omapdss_dpi_set_data_lines(struct omap_dss_device *dssdev, int data_lines); |
37ac60e4 TV |
862 | |
863 | int omapdss_sdi_display_enable(struct omap_dss_device *dssdev); | |
864 | void omapdss_sdi_display_disable(struct omap_dss_device *dssdev); | |
c7833f7b AT |
865 | void omapdss_sdi_set_timings(struct omap_dss_device *dssdev, |
866 | struct omap_video_timings *timings); | |
889b4fd7 | 867 | void omapdss_sdi_set_datapairs(struct omap_dss_device *dssdev, int datapairs); |
37ac60e4 TV |
868 | |
869 | int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev); | |
870 | void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev); | |
43eab861 AT |
871 | int omap_rfbi_update(struct omap_dss_device *dssdev, void (*callback)(void *), |
872 | void *data); | |
475989b7 | 873 | int omap_rfbi_configure(struct omap_dss_device *dssdev); |
6ff9dd5a | 874 | void omapdss_rfbi_set_size(struct omap_dss_device *dssdev, u16 w, u16 h); |
b02875be AT |
875 | void omapdss_rfbi_set_pixel_size(struct omap_dss_device *dssdev, |
876 | int pixel_size); | |
475989b7 AT |
877 | void omapdss_rfbi_set_data_lines(struct omap_dss_device *dssdev, |
878 | int data_lines); | |
6e883324 AT |
879 | void omapdss_rfbi_set_interface_timings(struct omap_dss_device *dssdev, |
880 | struct rfbi_timings *timings); | |
18946f62 | 881 | |
8dd2491a TV |
882 | int omapdss_compat_init(void); |
883 | void omapdss_compat_uninit(void); | |
884 | ||
a97a9634 TV |
885 | struct dss_mgr_ops { |
886 | void (*start_update)(struct omap_overlay_manager *mgr); | |
887 | int (*enable)(struct omap_overlay_manager *mgr); | |
888 | void (*disable)(struct omap_overlay_manager *mgr); | |
889 | void (*set_timings)(struct omap_overlay_manager *mgr, | |
890 | const struct omap_video_timings *timings); | |
891 | void (*set_lcd_config)(struct omap_overlay_manager *mgr, | |
892 | const struct dss_lcd_mgr_config *config); | |
893 | int (*register_framedone_handler)(struct omap_overlay_manager *mgr, | |
894 | void (*handler)(void *), void *data); | |
895 | void (*unregister_framedone_handler)(struct omap_overlay_manager *mgr, | |
896 | void (*handler)(void *), void *data); | |
897 | }; | |
898 | ||
899 | int dss_install_mgr_ops(const struct dss_mgr_ops *mgr_ops); | |
900 | void dss_uninstall_mgr_ops(void); | |
901 | ||
902 | void dss_mgr_set_timings(struct omap_overlay_manager *mgr, | |
903 | const struct omap_video_timings *timings); | |
904 | void dss_mgr_set_lcd_config(struct omap_overlay_manager *mgr, | |
905 | const struct dss_lcd_mgr_config *config); | |
906 | int dss_mgr_enable(struct omap_overlay_manager *mgr); | |
907 | void dss_mgr_disable(struct omap_overlay_manager *mgr); | |
908 | void dss_mgr_start_update(struct omap_overlay_manager *mgr); | |
909 | int dss_mgr_register_framedone_handler(struct omap_overlay_manager *mgr, | |
910 | void (*handler)(void *), void *data); | |
911 | void dss_mgr_unregister_framedone_handler(struct omap_overlay_manager *mgr, | |
912 | void (*handler)(void *), void *data); | |
559d6701 | 913 | #endif |