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Commit | Line | Data |
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457c8996 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
1da177e4 LT |
2 | /* |
3 | * Dynamic DMA mapping support. | |
4 | * | |
563aaf06 | 5 | * This implementation is a fallback for platforms that do not support |
1da177e4 LT |
6 | * I/O TLBs (aka DMA address translation hardware). |
7 | * Copyright (C) 2000 Asit Mallick <Asit.K.Mallick@intel.com> | |
8 | * Copyright (C) 2000 Goutham Rao <goutham.rao@intel.com> | |
9 | * Copyright (C) 2000, 2003 Hewlett-Packard Co | |
10 | * David Mosberger-Tang <davidm@hpl.hp.com> | |
11 | * | |
12 | * 03/05/07 davidm Switch from PCI-DMA to generic device DMA API. | |
13 | * 00/12/13 davidm Rename to swiotlb.c and add mark_clean() to avoid | |
14 | * unnecessary i-cache flushing. | |
569c8bf5 JL |
15 | * 04/07/.. ak Better overflow handling. Assorted fixes. |
16 | * 05/09/10 linville Add support for syncing ranges, support syncing for | |
17 | * DMA_BIDIRECTIONAL mappings, miscellaneous cleanup. | |
fb05a379 | 18 | * 08/12/11 beckyb Add highmem support |
1da177e4 LT |
19 | */ |
20 | ||
7d63fb3a KC |
21 | #define pr_fmt(fmt) "software IO TLB: " fmt |
22 | ||
1da177e4 | 23 | #include <linux/cache.h> |
ea8c64ac | 24 | #include <linux/dma-direct.h> |
4a47cbae | 25 | #include <linux/dma-noncoherent.h> |
1da177e4 | 26 | #include <linux/mm.h> |
8bc3bcc9 | 27 | #include <linux/export.h> |
1da177e4 LT |
28 | #include <linux/spinlock.h> |
29 | #include <linux/string.h> | |
0016fdee | 30 | #include <linux/swiotlb.h> |
fb05a379 | 31 | #include <linux/pfn.h> |
1da177e4 LT |
32 | #include <linux/types.h> |
33 | #include <linux/ctype.h> | |
ef9b1893 | 34 | #include <linux/highmem.h> |
5a0e3ad6 | 35 | #include <linux/gfp.h> |
84be456f | 36 | #include <linux/scatterlist.h> |
c7753208 | 37 | #include <linux/mem_encrypt.h> |
e7de6c7c | 38 | #include <linux/set_memory.h> |
71602fe6 DZ |
39 | #ifdef CONFIG_DEBUG_FS |
40 | #include <linux/debugfs.h> | |
41 | #endif | |
1da177e4 LT |
42 | |
43 | #include <asm/io.h> | |
1da177e4 LT |
44 | #include <asm/dma.h> |
45 | ||
46 | #include <linux/init.h> | |
57c8a661 | 47 | #include <linux/memblock.h> |
a8522509 | 48 | #include <linux/iommu-helper.h> |
1da177e4 | 49 | |
ce5be5a1 | 50 | #define CREATE_TRACE_POINTS |
2b2b614d ZK |
51 | #include <trace/events/swiotlb.h> |
52 | ||
1da177e4 LT |
53 | #define OFFSET(val,align) ((unsigned long) \ |
54 | ( (val) & ( (align) - 1))) | |
55 | ||
0b9afede AW |
56 | #define SLABS_PER_PAGE (1 << (PAGE_SHIFT - IO_TLB_SHIFT)) |
57 | ||
58 | /* | |
59 | * Minimum IO TLB size to bother booting with. Systems with mainly | |
60 | * 64bit capable cards will only lightly use the swiotlb. If we can't | |
61 | * allocate a contiguous 1MB, we're probably in trouble anyway. | |
62 | */ | |
63 | #define IO_TLB_MIN_SLABS ((1<<20) >> IO_TLB_SHIFT) | |
64 | ||
ae7871be | 65 | enum swiotlb_force swiotlb_force; |
1da177e4 LT |
66 | |
67 | /* | |
bfc5501f KRW |
68 | * Used to do a quick range check in swiotlb_tbl_unmap_single and |
69 | * swiotlb_tbl_sync_single_*, to see if the memory was in fact allocated by this | |
1da177e4 LT |
70 | * API. |
71 | */ | |
55897af6 | 72 | phys_addr_t io_tlb_start, io_tlb_end; |
1da177e4 LT |
73 | |
74 | /* | |
b595076a | 75 | * The number of IO TLB blocks (in groups of 64) between io_tlb_start and |
1da177e4 LT |
76 | * io_tlb_end. This is command line adjustable via setup_io_tlb_npages. |
77 | */ | |
78 | static unsigned long io_tlb_nslabs; | |
79 | ||
71602fe6 DZ |
80 | /* |
81 | * The number of used IO TLB block | |
82 | */ | |
83 | static unsigned long io_tlb_used; | |
84 | ||
1da177e4 LT |
85 | /* |
86 | * This is a free list describing the number of free entries available from | |
87 | * each index | |
88 | */ | |
89 | static unsigned int *io_tlb_list; | |
90 | static unsigned int io_tlb_index; | |
91 | ||
7453c549 KRW |
92 | /* |
93 | * Max segment that we can provide which (if pages are contingous) will | |
94 | * not be bounced (unless SWIOTLB_FORCE is set). | |
95 | */ | |
96 | unsigned int max_segment; | |
97 | ||
1da177e4 LT |
98 | /* |
99 | * We need to save away the original address corresponding to a mapped entry | |
100 | * for the sync operations. | |
101 | */ | |
8e0629c1 | 102 | #define INVALID_PHYS_ADDR (~(phys_addr_t)0) |
bc40ac66 | 103 | static phys_addr_t *io_tlb_orig_addr; |
1da177e4 LT |
104 | |
105 | /* | |
106 | * Protect the above data structures in the map and unmap calls | |
107 | */ | |
108 | static DEFINE_SPINLOCK(io_tlb_lock); | |
109 | ||
5740afdb FT |
110 | static int late_alloc; |
111 | ||
1da177e4 LT |
112 | static int __init |
113 | setup_io_tlb_npages(char *str) | |
114 | { | |
115 | if (isdigit(*str)) { | |
e8579e72 | 116 | io_tlb_nslabs = simple_strtoul(str, &str, 0); |
1da177e4 LT |
117 | /* avoid tail segment of size < IO_TLB_SEGSIZE */ |
118 | io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE); | |
119 | } | |
120 | if (*str == ',') | |
121 | ++str; | |
fff5d992 | 122 | if (!strcmp(str, "force")) { |
ae7871be | 123 | swiotlb_force = SWIOTLB_FORCE; |
fff5d992 GU |
124 | } else if (!strcmp(str, "noforce")) { |
125 | swiotlb_force = SWIOTLB_NO_FORCE; | |
126 | io_tlb_nslabs = 1; | |
127 | } | |
b18485e7 | 128 | |
c729de8f | 129 | return 0; |
1da177e4 | 130 | } |
c729de8f | 131 | early_param("swiotlb", setup_io_tlb_npages); |
1da177e4 | 132 | |
4aa095ea FF |
133 | static bool no_iotlb_memory; |
134 | ||
f21ffe9f | 135 | unsigned long swiotlb_nr_tbl(void) |
5f98ecdb | 136 | { |
4aa095ea | 137 | return unlikely(no_iotlb_memory) ? 0 : io_tlb_nslabs; |
5f98ecdb | 138 | } |
f21ffe9f | 139 | EXPORT_SYMBOL_GPL(swiotlb_nr_tbl); |
c729de8f | 140 | |
7453c549 KRW |
141 | unsigned int swiotlb_max_segment(void) |
142 | { | |
4aa095ea | 143 | return unlikely(no_iotlb_memory) ? 0 : max_segment; |
7453c549 KRW |
144 | } |
145 | EXPORT_SYMBOL_GPL(swiotlb_max_segment); | |
146 | ||
147 | void swiotlb_set_max_segment(unsigned int val) | |
148 | { | |
149 | if (swiotlb_force == SWIOTLB_FORCE) | |
150 | max_segment = 1; | |
151 | else | |
152 | max_segment = rounddown(val, PAGE_SIZE); | |
153 | } | |
154 | ||
c729de8f YL |
155 | /* default to 64MB */ |
156 | #define IO_TLB_DEFAULT_SIZE (64UL<<20) | |
157 | unsigned long swiotlb_size_or_default(void) | |
158 | { | |
159 | unsigned long size; | |
160 | ||
161 | size = io_tlb_nslabs << IO_TLB_SHIFT; | |
162 | ||
163 | return size ? size : (IO_TLB_DEFAULT_SIZE); | |
164 | } | |
165 | ||
ad32e8cb | 166 | void swiotlb_print_info(void) |
2e5b2b86 | 167 | { |
ad32e8cb | 168 | unsigned long bytes = io_tlb_nslabs << IO_TLB_SHIFT; |
2e5b2b86 | 169 | |
ac2cbab2 | 170 | if (no_iotlb_memory) { |
7d63fb3a | 171 | pr_warn("No low mem\n"); |
ac2cbab2 YL |
172 | return; |
173 | } | |
174 | ||
7d63fb3a | 175 | pr_info("mapped [mem %#010llx-%#010llx] (%luMB)\n", |
ff7204a7 | 176 | (unsigned long long)io_tlb_start, |
c40dba06 | 177 | (unsigned long long)io_tlb_end, |
7d63fb3a | 178 | bytes >> 20); |
2e5b2b86 IC |
179 | } |
180 | ||
c7753208 TL |
181 | /* |
182 | * Early SWIOTLB allocation may be too early to allow an architecture to | |
183 | * perform the desired operations. This function allows the architecture to | |
184 | * call SWIOTLB when the operations are possible. It needs to be called | |
185 | * before the SWIOTLB memory is used. | |
186 | */ | |
187 | void __init swiotlb_update_mem_attributes(void) | |
188 | { | |
189 | void *vaddr; | |
190 | unsigned long bytes; | |
191 | ||
192 | if (no_iotlb_memory || late_alloc) | |
193 | return; | |
194 | ||
195 | vaddr = phys_to_virt(io_tlb_start); | |
196 | bytes = PAGE_ALIGN(io_tlb_nslabs << IO_TLB_SHIFT); | |
e7de6c7c | 197 | set_memory_decrypted((unsigned long)vaddr, bytes >> PAGE_SHIFT); |
c7753208 | 198 | memset(vaddr, 0, bytes); |
c7753208 TL |
199 | } |
200 | ||
ac2cbab2 | 201 | int __init swiotlb_init_with_tbl(char *tlb, unsigned long nslabs, int verbose) |
1da177e4 | 202 | { |
563aaf06 | 203 | unsigned long i, bytes; |
a0bf842e | 204 | size_t alloc_size; |
1da177e4 | 205 | |
abbceff7 | 206 | bytes = nslabs << IO_TLB_SHIFT; |
1da177e4 | 207 | |
abbceff7 | 208 | io_tlb_nslabs = nslabs; |
ff7204a7 AD |
209 | io_tlb_start = __pa(tlb); |
210 | io_tlb_end = io_tlb_start + bytes; | |
1da177e4 LT |
211 | |
212 | /* | |
213 | * Allocate and initialize the free list array. This array is used | |
214 | * to find contiguous free memory regions of size up to IO_TLB_SEGSIZE | |
215 | * between io_tlb_start and io_tlb_end. | |
216 | */ | |
a0bf842e MR |
217 | alloc_size = PAGE_ALIGN(io_tlb_nslabs * sizeof(int)); |
218 | io_tlb_list = memblock_alloc(alloc_size, PAGE_SIZE); | |
219 | if (!io_tlb_list) | |
8a7f97b9 | 220 | panic("%s: Failed to allocate %zu bytes align=0x%lx\n", |
a0bf842e MR |
221 | __func__, alloc_size, PAGE_SIZE); |
222 | ||
223 | alloc_size = PAGE_ALIGN(io_tlb_nslabs * sizeof(phys_addr_t)); | |
224 | io_tlb_orig_addr = memblock_alloc(alloc_size, PAGE_SIZE); | |
225 | if (!io_tlb_orig_addr) | |
8a7f97b9 | 226 | panic("%s: Failed to allocate %zu bytes align=0x%lx\n", |
a0bf842e MR |
227 | __func__, alloc_size, PAGE_SIZE); |
228 | ||
8e0629c1 JB |
229 | for (i = 0; i < io_tlb_nslabs; i++) { |
230 | io_tlb_list[i] = IO_TLB_SEGSIZE - OFFSET(i, IO_TLB_SEGSIZE); | |
231 | io_tlb_orig_addr[i] = INVALID_PHYS_ADDR; | |
232 | } | |
233 | io_tlb_index = 0; | |
1da177e4 | 234 | |
ad32e8cb FT |
235 | if (verbose) |
236 | swiotlb_print_info(); | |
ac2cbab2 | 237 | |
7453c549 | 238 | swiotlb_set_max_segment(io_tlb_nslabs << IO_TLB_SHIFT); |
ac2cbab2 | 239 | return 0; |
1da177e4 LT |
240 | } |
241 | ||
abbceff7 FT |
242 | /* |
243 | * Statically reserve bounce buffer space and initialize bounce buffer data | |
244 | * structures for the software IO TLB used to implement the DMA API. | |
245 | */ | |
ac2cbab2 YL |
246 | void __init |
247 | swiotlb_init(int verbose) | |
abbceff7 | 248 | { |
c729de8f | 249 | size_t default_size = IO_TLB_DEFAULT_SIZE; |
ff7204a7 | 250 | unsigned char *vstart; |
abbceff7 FT |
251 | unsigned long bytes; |
252 | ||
253 | if (!io_tlb_nslabs) { | |
254 | io_tlb_nslabs = (default_size >> IO_TLB_SHIFT); | |
255 | io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE); | |
256 | } | |
257 | ||
258 | bytes = io_tlb_nslabs << IO_TLB_SHIFT; | |
259 | ||
ac2cbab2 | 260 | /* Get IO TLB memory from the low pages */ |
26fb3dae | 261 | vstart = memblock_alloc_low(PAGE_ALIGN(bytes), PAGE_SIZE); |
ac2cbab2 YL |
262 | if (vstart && !swiotlb_init_with_tbl(vstart, io_tlb_nslabs, verbose)) |
263 | return; | |
abbceff7 | 264 | |
ac2cbab2 | 265 | if (io_tlb_start) |
457ff1de SS |
266 | memblock_free_early(io_tlb_start, |
267 | PAGE_ALIGN(io_tlb_nslabs << IO_TLB_SHIFT)); | |
7d63fb3a | 268 | pr_warn("Cannot allocate buffer"); |
ac2cbab2 | 269 | no_iotlb_memory = true; |
1da177e4 LT |
270 | } |
271 | ||
0b9afede AW |
272 | /* |
273 | * Systems with larger DMA zones (those that don't support ISA) can | |
274 | * initialize the swiotlb later using the slab allocator if needed. | |
275 | * This should be just like above, but with some error catching. | |
276 | */ | |
277 | int | |
563aaf06 | 278 | swiotlb_late_init_with_default_size(size_t default_size) |
0b9afede | 279 | { |
74838b75 | 280 | unsigned long bytes, req_nslabs = io_tlb_nslabs; |
ff7204a7 | 281 | unsigned char *vstart = NULL; |
0b9afede | 282 | unsigned int order; |
74838b75 | 283 | int rc = 0; |
0b9afede AW |
284 | |
285 | if (!io_tlb_nslabs) { | |
286 | io_tlb_nslabs = (default_size >> IO_TLB_SHIFT); | |
287 | io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE); | |
288 | } | |
289 | ||
290 | /* | |
291 | * Get IO TLB memory from the low pages | |
292 | */ | |
563aaf06 | 293 | order = get_order(io_tlb_nslabs << IO_TLB_SHIFT); |
0b9afede | 294 | io_tlb_nslabs = SLABS_PER_PAGE << order; |
563aaf06 | 295 | bytes = io_tlb_nslabs << IO_TLB_SHIFT; |
0b9afede AW |
296 | |
297 | while ((SLABS_PER_PAGE << order) > IO_TLB_MIN_SLABS) { | |
ff7204a7 AD |
298 | vstart = (void *)__get_free_pages(GFP_DMA | __GFP_NOWARN, |
299 | order); | |
300 | if (vstart) | |
0b9afede AW |
301 | break; |
302 | order--; | |
303 | } | |
304 | ||
ff7204a7 | 305 | if (!vstart) { |
74838b75 KRW |
306 | io_tlb_nslabs = req_nslabs; |
307 | return -ENOMEM; | |
308 | } | |
563aaf06 | 309 | if (order != get_order(bytes)) { |
7d63fb3a KC |
310 | pr_warn("only able to allocate %ld MB\n", |
311 | (PAGE_SIZE << order) >> 20); | |
0b9afede AW |
312 | io_tlb_nslabs = SLABS_PER_PAGE << order; |
313 | } | |
ff7204a7 | 314 | rc = swiotlb_late_init_with_tbl(vstart, io_tlb_nslabs); |
74838b75 | 315 | if (rc) |
ff7204a7 | 316 | free_pages((unsigned long)vstart, order); |
7453c549 | 317 | |
74838b75 KRW |
318 | return rc; |
319 | } | |
320 | ||
0bfaffbf FF |
321 | static void swiotlb_cleanup(void) |
322 | { | |
323 | io_tlb_end = 0; | |
324 | io_tlb_start = 0; | |
325 | io_tlb_nslabs = 0; | |
326 | max_segment = 0; | |
327 | } | |
328 | ||
74838b75 KRW |
329 | int |
330 | swiotlb_late_init_with_tbl(char *tlb, unsigned long nslabs) | |
331 | { | |
332 | unsigned long i, bytes; | |
333 | ||
334 | bytes = nslabs << IO_TLB_SHIFT; | |
335 | ||
336 | io_tlb_nslabs = nslabs; | |
ff7204a7 AD |
337 | io_tlb_start = virt_to_phys(tlb); |
338 | io_tlb_end = io_tlb_start + bytes; | |
74838b75 | 339 | |
e7de6c7c | 340 | set_memory_decrypted((unsigned long)tlb, bytes >> PAGE_SHIFT); |
ff7204a7 | 341 | memset(tlb, 0, bytes); |
0b9afede AW |
342 | |
343 | /* | |
344 | * Allocate and initialize the free list array. This array is used | |
345 | * to find contiguous free memory regions of size up to IO_TLB_SEGSIZE | |
346 | * between io_tlb_start and io_tlb_end. | |
347 | */ | |
348 | io_tlb_list = (unsigned int *)__get_free_pages(GFP_KERNEL, | |
349 | get_order(io_tlb_nslabs * sizeof(int))); | |
350 | if (!io_tlb_list) | |
ee3f6ba8 | 351 | goto cleanup3; |
0b9afede | 352 | |
bc40ac66 BB |
353 | io_tlb_orig_addr = (phys_addr_t *) |
354 | __get_free_pages(GFP_KERNEL, | |
355 | get_order(io_tlb_nslabs * | |
356 | sizeof(phys_addr_t))); | |
0b9afede | 357 | if (!io_tlb_orig_addr) |
ee3f6ba8 | 358 | goto cleanup4; |
0b9afede | 359 | |
8e0629c1 JB |
360 | for (i = 0; i < io_tlb_nslabs; i++) { |
361 | io_tlb_list[i] = IO_TLB_SEGSIZE - OFFSET(i, IO_TLB_SEGSIZE); | |
362 | io_tlb_orig_addr[i] = INVALID_PHYS_ADDR; | |
363 | } | |
364 | io_tlb_index = 0; | |
0b9afede | 365 | |
ad32e8cb | 366 | swiotlb_print_info(); |
0b9afede | 367 | |
5740afdb FT |
368 | late_alloc = 1; |
369 | ||
7453c549 KRW |
370 | swiotlb_set_max_segment(io_tlb_nslabs << IO_TLB_SHIFT); |
371 | ||
0b9afede AW |
372 | return 0; |
373 | ||
374 | cleanup4: | |
25667d67 TL |
375 | free_pages((unsigned long)io_tlb_list, get_order(io_tlb_nslabs * |
376 | sizeof(int))); | |
0b9afede | 377 | io_tlb_list = NULL; |
ee3f6ba8 | 378 | cleanup3: |
0bfaffbf | 379 | swiotlb_cleanup(); |
0b9afede AW |
380 | return -ENOMEM; |
381 | } | |
382 | ||
7f2c8bbd | 383 | void __init swiotlb_exit(void) |
5740afdb | 384 | { |
ee3f6ba8 | 385 | if (!io_tlb_orig_addr) |
5740afdb FT |
386 | return; |
387 | ||
388 | if (late_alloc) { | |
5740afdb FT |
389 | free_pages((unsigned long)io_tlb_orig_addr, |
390 | get_order(io_tlb_nslabs * sizeof(phys_addr_t))); | |
391 | free_pages((unsigned long)io_tlb_list, get_order(io_tlb_nslabs * | |
392 | sizeof(int))); | |
ff7204a7 | 393 | free_pages((unsigned long)phys_to_virt(io_tlb_start), |
5740afdb FT |
394 | get_order(io_tlb_nslabs << IO_TLB_SHIFT)); |
395 | } else { | |
457ff1de SS |
396 | memblock_free_late(__pa(io_tlb_orig_addr), |
397 | PAGE_ALIGN(io_tlb_nslabs * sizeof(phys_addr_t))); | |
398 | memblock_free_late(__pa(io_tlb_list), | |
399 | PAGE_ALIGN(io_tlb_nslabs * sizeof(int))); | |
400 | memblock_free_late(io_tlb_start, | |
401 | PAGE_ALIGN(io_tlb_nslabs << IO_TLB_SHIFT)); | |
5740afdb | 402 | } |
0bfaffbf | 403 | swiotlb_cleanup(); |
5740afdb FT |
404 | } |
405 | ||
fb05a379 | 406 | /* |
6442ca2a | 407 | * Bounce: copy the swiotlb buffer from or back to the original dma location |
fb05a379 | 408 | */ |
af51a9f1 AD |
409 | static void swiotlb_bounce(phys_addr_t orig_addr, phys_addr_t tlb_addr, |
410 | size_t size, enum dma_data_direction dir) | |
fb05a379 | 411 | { |
af51a9f1 AD |
412 | unsigned long pfn = PFN_DOWN(orig_addr); |
413 | unsigned char *vaddr = phys_to_virt(tlb_addr); | |
fb05a379 BB |
414 | |
415 | if (PageHighMem(pfn_to_page(pfn))) { | |
416 | /* The buffer does not have a mapping. Map it in and copy */ | |
af51a9f1 | 417 | unsigned int offset = orig_addr & ~PAGE_MASK; |
fb05a379 BB |
418 | char *buffer; |
419 | unsigned int sz = 0; | |
420 | unsigned long flags; | |
421 | ||
422 | while (size) { | |
67131ad0 | 423 | sz = min_t(size_t, PAGE_SIZE - offset, size); |
fb05a379 BB |
424 | |
425 | local_irq_save(flags); | |
c3eede8e | 426 | buffer = kmap_atomic(pfn_to_page(pfn)); |
fb05a379 | 427 | if (dir == DMA_TO_DEVICE) |
af51a9f1 | 428 | memcpy(vaddr, buffer + offset, sz); |
ef9b1893 | 429 | else |
af51a9f1 | 430 | memcpy(buffer + offset, vaddr, sz); |
c3eede8e | 431 | kunmap_atomic(buffer); |
ef9b1893 | 432 | local_irq_restore(flags); |
fb05a379 BB |
433 | |
434 | size -= sz; | |
435 | pfn++; | |
af51a9f1 | 436 | vaddr += sz; |
fb05a379 | 437 | offset = 0; |
ef9b1893 | 438 | } |
af51a9f1 AD |
439 | } else if (dir == DMA_TO_DEVICE) { |
440 | memcpy(vaddr, phys_to_virt(orig_addr), size); | |
ef9b1893 | 441 | } else { |
af51a9f1 | 442 | memcpy(phys_to_virt(orig_addr), vaddr, size); |
ef9b1893 | 443 | } |
1b548f66 JF |
444 | } |
445 | ||
e05ed4d1 AD |
446 | phys_addr_t swiotlb_tbl_map_single(struct device *hwdev, |
447 | dma_addr_t tbl_dma_addr, | |
3fc1ca00 LB |
448 | phys_addr_t orig_addr, |
449 | size_t mapping_size, | |
450 | size_t alloc_size, | |
0443fa00 AD |
451 | enum dma_data_direction dir, |
452 | unsigned long attrs) | |
1da177e4 LT |
453 | { |
454 | unsigned long flags; | |
e05ed4d1 | 455 | phys_addr_t tlb_addr; |
1da177e4 LT |
456 | unsigned int nslots, stride, index, wrap; |
457 | int i; | |
681cc5cd FT |
458 | unsigned long mask; |
459 | unsigned long offset_slots; | |
460 | unsigned long max_slots; | |
53b29c33 | 461 | unsigned long tmp_io_tlb_used; |
681cc5cd | 462 | |
ac2cbab2 YL |
463 | if (no_iotlb_memory) |
464 | panic("Can not allocate SWIOTLB buffer earlier and can't now provide you with the DMA bounce buffer"); | |
465 | ||
d7b417fa | 466 | if (mem_encrypt_active()) |
47e5d8f9 | 467 | pr_warn_once("Memory encryption is active and system is using DMA bounce buffers\n"); |
648babb7 | 468 | |
3fc1ca00 LB |
469 | if (mapping_size > alloc_size) { |
470 | dev_warn_once(hwdev, "Invalid sizes (mapping: %zd bytes, alloc: %zd bytes)", | |
471 | mapping_size, alloc_size); | |
472 | return (phys_addr_t)DMA_MAPPING_ERROR; | |
473 | } | |
474 | ||
681cc5cd | 475 | mask = dma_get_seg_boundary(hwdev); |
681cc5cd | 476 | |
eb605a57 FT |
477 | tbl_dma_addr &= mask; |
478 | ||
479 | offset_slots = ALIGN(tbl_dma_addr, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT; | |
a5ddde4a IC |
480 | |
481 | /* | |
3fc1ca00 LB |
482 | * Carefully handle integer overflow which can occur when mask == ~0UL. |
483 | */ | |
b15a3891 JB |
484 | max_slots = mask + 1 |
485 | ? ALIGN(mask + 1, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT | |
486 | : 1UL << (BITS_PER_LONG - IO_TLB_SHIFT); | |
1da177e4 LT |
487 | |
488 | /* | |
602d9858 NY |
489 | * For mappings greater than or equal to a page, we limit the stride |
490 | * (and hence alignment) to a page size. | |
1da177e4 | 491 | */ |
3fc1ca00 LB |
492 | nslots = ALIGN(alloc_size, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT; |
493 | if (alloc_size >= PAGE_SIZE) | |
1da177e4 LT |
494 | stride = (1 << (PAGE_SHIFT - IO_TLB_SHIFT)); |
495 | else | |
496 | stride = 1; | |
497 | ||
34814545 | 498 | BUG_ON(!nslots); |
1da177e4 LT |
499 | |
500 | /* | |
501 | * Find suitable number of IO TLB entries size that will fit this | |
502 | * request and allocate a buffer from that IO TLB pool. | |
503 | */ | |
504 | spin_lock_irqsave(&io_tlb_lock, flags); | |
60513ed0 DZ |
505 | |
506 | if (unlikely(nslots > io_tlb_nslabs - io_tlb_used)) | |
507 | goto not_found; | |
508 | ||
a7133a15 AM |
509 | index = ALIGN(io_tlb_index, stride); |
510 | if (index >= io_tlb_nslabs) | |
511 | index = 0; | |
512 | wrap = index; | |
513 | ||
514 | do { | |
a8522509 FT |
515 | while (iommu_is_span_boundary(index, nslots, offset_slots, |
516 | max_slots)) { | |
b15a3891 JB |
517 | index += stride; |
518 | if (index >= io_tlb_nslabs) | |
519 | index = 0; | |
a7133a15 AM |
520 | if (index == wrap) |
521 | goto not_found; | |
522 | } | |
523 | ||
524 | /* | |
525 | * If we find a slot that indicates we have 'nslots' number of | |
526 | * contiguous buffers, we allocate the buffers from that slot | |
527 | * and mark the entries as '0' indicating unavailable. | |
528 | */ | |
529 | if (io_tlb_list[index] >= nslots) { | |
530 | int count = 0; | |
531 | ||
532 | for (i = index; i < (int) (index + nslots); i++) | |
533 | io_tlb_list[i] = 0; | |
534 | for (i = index - 1; (OFFSET(i, IO_TLB_SEGSIZE) != IO_TLB_SEGSIZE - 1) && io_tlb_list[i]; i--) | |
535 | io_tlb_list[i] = ++count; | |
e05ed4d1 | 536 | tlb_addr = io_tlb_start + (index << IO_TLB_SHIFT); |
1da177e4 | 537 | |
a7133a15 AM |
538 | /* |
539 | * Update the indices to avoid searching in the next | |
540 | * round. | |
541 | */ | |
542 | io_tlb_index = ((index + nslots) < io_tlb_nslabs | |
543 | ? (index + nslots) : 0); | |
544 | ||
545 | goto found; | |
546 | } | |
547 | index += stride; | |
548 | if (index >= io_tlb_nslabs) | |
549 | index = 0; | |
550 | } while (index != wrap); | |
551 | ||
552 | not_found: | |
53b29c33 DZ |
553 | tmp_io_tlb_used = io_tlb_used; |
554 | ||
a7133a15 | 555 | spin_unlock_irqrestore(&io_tlb_lock, flags); |
d0bc0c2a | 556 | if (!(attrs & DMA_ATTR_NO_WARN) && printk_ratelimit()) |
53b29c33 | 557 | dev_warn(hwdev, "swiotlb buffer is full (sz: %zd bytes), total %lu (slots), used %lu (slots)\n", |
3fc1ca00 | 558 | alloc_size, io_tlb_nslabs, tmp_io_tlb_used); |
9c106119 | 559 | return (phys_addr_t)DMA_MAPPING_ERROR; |
a7133a15 | 560 | found: |
71602fe6 | 561 | io_tlb_used += nslots; |
1da177e4 LT |
562 | spin_unlock_irqrestore(&io_tlb_lock, flags); |
563 | ||
564 | /* | |
565 | * Save away the mapping from the original address to the DMA address. | |
566 | * This is needed when we sync the memory. Then we sync the buffer if | |
567 | * needed. | |
568 | */ | |
bc40ac66 | 569 | for (i = 0; i < nslots; i++) |
e05ed4d1 | 570 | io_tlb_orig_addr[index+i] = orig_addr + (i << IO_TLB_SHIFT); |
0443fa00 AD |
571 | if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC) && |
572 | (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL)) | |
3fc1ca00 | 573 | swiotlb_bounce(orig_addr, tlb_addr, mapping_size, DMA_TO_DEVICE); |
1da177e4 | 574 | |
e05ed4d1 | 575 | return tlb_addr; |
1da177e4 LT |
576 | } |
577 | ||
578 | /* | |
d0c8ba40 | 579 | * tlb_addr is the physical address of the bounce buffer to unmap. |
1da177e4 | 580 | */ |
61ca08c3 | 581 | void swiotlb_tbl_unmap_single(struct device *hwdev, phys_addr_t tlb_addr, |
3fc1ca00 LB |
582 | size_t mapping_size, size_t alloc_size, |
583 | enum dma_data_direction dir, unsigned long attrs) | |
1da177e4 LT |
584 | { |
585 | unsigned long flags; | |
3fc1ca00 | 586 | int i, count, nslots = ALIGN(alloc_size, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT; |
61ca08c3 AD |
587 | int index = (tlb_addr - io_tlb_start) >> IO_TLB_SHIFT; |
588 | phys_addr_t orig_addr = io_tlb_orig_addr[index]; | |
1da177e4 LT |
589 | |
590 | /* | |
591 | * First, sync the memory before unmapping the entry | |
592 | */ | |
8e0629c1 | 593 | if (orig_addr != INVALID_PHYS_ADDR && |
0443fa00 | 594 | !(attrs & DMA_ATTR_SKIP_CPU_SYNC) && |
8e0629c1 | 595 | ((dir == DMA_FROM_DEVICE) || (dir == DMA_BIDIRECTIONAL))) |
3fc1ca00 | 596 | swiotlb_bounce(orig_addr, tlb_addr, mapping_size, DMA_FROM_DEVICE); |
1da177e4 LT |
597 | |
598 | /* | |
599 | * Return the buffer to the free list by setting the corresponding | |
af901ca1 | 600 | * entries to indicate the number of contiguous entries available. |
1da177e4 LT |
601 | * While returning the entries to the free list, we merge the entries |
602 | * with slots below and above the pool being returned. | |
603 | */ | |
604 | spin_lock_irqsave(&io_tlb_lock, flags); | |
605 | { | |
606 | count = ((index + nslots) < ALIGN(index + 1, IO_TLB_SEGSIZE) ? | |
607 | io_tlb_list[index + nslots] : 0); | |
608 | /* | |
609 | * Step 1: return the slots to the free list, merging the | |
610 | * slots with superceeding slots | |
611 | */ | |
8e0629c1 | 612 | for (i = index + nslots - 1; i >= index; i--) { |
1da177e4 | 613 | io_tlb_list[i] = ++count; |
8e0629c1 JB |
614 | io_tlb_orig_addr[i] = INVALID_PHYS_ADDR; |
615 | } | |
1da177e4 LT |
616 | /* |
617 | * Step 2: merge the returned slots with the preceding slots, | |
618 | * if available (non zero) | |
619 | */ | |
620 | for (i = index - 1; (OFFSET(i, IO_TLB_SEGSIZE) != IO_TLB_SEGSIZE -1) && io_tlb_list[i]; i--) | |
621 | io_tlb_list[i] = ++count; | |
71602fe6 DZ |
622 | |
623 | io_tlb_used -= nslots; | |
1da177e4 LT |
624 | } |
625 | spin_unlock_irqrestore(&io_tlb_lock, flags); | |
626 | } | |
627 | ||
fbfda893 AD |
628 | void swiotlb_tbl_sync_single(struct device *hwdev, phys_addr_t tlb_addr, |
629 | size_t size, enum dma_data_direction dir, | |
630 | enum dma_sync_target target) | |
1da177e4 | 631 | { |
fbfda893 AD |
632 | int index = (tlb_addr - io_tlb_start) >> IO_TLB_SHIFT; |
633 | phys_addr_t orig_addr = io_tlb_orig_addr[index]; | |
bc40ac66 | 634 | |
8e0629c1 JB |
635 | if (orig_addr == INVALID_PHYS_ADDR) |
636 | return; | |
fbfda893 | 637 | orig_addr += (unsigned long)tlb_addr & ((1 << IO_TLB_SHIFT) - 1); |
df336d1c | 638 | |
de69e0f0 JL |
639 | switch (target) { |
640 | case SYNC_FOR_CPU: | |
641 | if (likely(dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)) | |
af51a9f1 | 642 | swiotlb_bounce(orig_addr, tlb_addr, |
fbfda893 | 643 | size, DMA_FROM_DEVICE); |
34814545 ES |
644 | else |
645 | BUG_ON(dir != DMA_TO_DEVICE); | |
de69e0f0 JL |
646 | break; |
647 | case SYNC_FOR_DEVICE: | |
648 | if (likely(dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL)) | |
af51a9f1 | 649 | swiotlb_bounce(orig_addr, tlb_addr, |
fbfda893 | 650 | size, DMA_TO_DEVICE); |
34814545 ES |
651 | else |
652 | BUG_ON(dir != DMA_FROM_DEVICE); | |
de69e0f0 JL |
653 | break; |
654 | default: | |
1da177e4 | 655 | BUG(); |
de69e0f0 | 656 | } |
1da177e4 LT |
657 | } |
658 | ||
55897af6 | 659 | /* |
4a47cbae | 660 | * Create a swiotlb mapping for the buffer at @paddr, and in case of DMAing |
55897af6 CH |
661 | * to the device copy the data into it as well. |
662 | */ | |
4a47cbae CH |
663 | dma_addr_t swiotlb_map(struct device *dev, phys_addr_t paddr, size_t size, |
664 | enum dma_data_direction dir, unsigned long attrs) | |
c4dae366 | 665 | { |
4a47cbae CH |
666 | phys_addr_t swiotlb_addr; |
667 | dma_addr_t dma_addr; | |
c4dae366 | 668 | |
4a47cbae CH |
669 | trace_swiotlb_bounced(dev, phys_to_dma(dev, paddr), size, |
670 | swiotlb_force); | |
c4dae366 | 671 | |
4a47cbae CH |
672 | swiotlb_addr = swiotlb_tbl_map_single(dev, |
673 | __phys_to_dma(dev, io_tlb_start), | |
674 | paddr, size, size, dir, attrs); | |
675 | if (swiotlb_addr == (phys_addr_t)DMA_MAPPING_ERROR) | |
676 | return DMA_MAPPING_ERROR; | |
c4dae366 CH |
677 | |
678 | /* Ensure that the address returned is DMA'ble */ | |
4a47cbae CH |
679 | dma_addr = __phys_to_dma(dev, swiotlb_addr); |
680 | if (unlikely(!dma_capable(dev, dma_addr, size, true))) { | |
681 | swiotlb_tbl_unmap_single(dev, swiotlb_addr, size, size, dir, | |
c4dae366 | 682 | attrs | DMA_ATTR_SKIP_CPU_SYNC); |
4a47cbae CH |
683 | dev_WARN_ONCE(dev, 1, |
684 | "swiotlb addr %pad+%zu overflow (mask %llx, bus limit %llx).\n", | |
685 | &dma_addr, size, *dev->dma_mask, dev->bus_dma_limit); | |
686 | return DMA_MAPPING_ERROR; | |
a4a4330d CH |
687 | } |
688 | ||
4a47cbae CH |
689 | if (!dev_is_dma_coherent(dev) && !(attrs & DMA_ATTR_SKIP_CPU_SYNC)) |
690 | arch_sync_dma_for_device(swiotlb_addr, size, dir); | |
691 | return dma_addr; | |
1da177e4 LT |
692 | } |
693 | ||
abe420bf JR |
694 | size_t swiotlb_max_mapping_size(struct device *dev) |
695 | { | |
696 | return ((size_t)1 << IO_TLB_SHIFT) * IO_TLB_SEGSIZE; | |
697 | } | |
492366f7 JR |
698 | |
699 | bool is_swiotlb_active(void) | |
700 | { | |
701 | /* | |
702 | * When SWIOTLB is initialized, even if io_tlb_start points to physical | |
703 | * address zero, io_tlb_end surely doesn't. | |
704 | */ | |
705 | return io_tlb_end != 0; | |
706 | } | |
45ba8d5d | 707 | |
71602fe6 DZ |
708 | #ifdef CONFIG_DEBUG_FS |
709 | ||
710 | static int __init swiotlb_create_debugfs(void) | |
711 | { | |
1be51474 | 712 | struct dentry *root; |
71602fe6 | 713 | |
1be51474 GKH |
714 | root = debugfs_create_dir("swiotlb", NULL); |
715 | debugfs_create_ulong("io_tlb_nslabs", 0400, root, &io_tlb_nslabs); | |
716 | debugfs_create_ulong("io_tlb_used", 0400, root, &io_tlb_used); | |
71602fe6 | 717 | return 0; |
71602fe6 DZ |
718 | } |
719 | ||
720 | late_initcall(swiotlb_create_debugfs); | |
721 | ||
722 | #endif |