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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Dynamic DMA mapping support. | |
3 | * | |
563aaf06 | 4 | * This implementation is a fallback for platforms that do not support |
1da177e4 LT |
5 | * I/O TLBs (aka DMA address translation hardware). |
6 | * Copyright (C) 2000 Asit Mallick <Asit.K.Mallick@intel.com> | |
7 | * Copyright (C) 2000 Goutham Rao <goutham.rao@intel.com> | |
8 | * Copyright (C) 2000, 2003 Hewlett-Packard Co | |
9 | * David Mosberger-Tang <davidm@hpl.hp.com> | |
10 | * | |
11 | * 03/05/07 davidm Switch from PCI-DMA to generic device DMA API. | |
12 | * 00/12/13 davidm Rename to swiotlb.c and add mark_clean() to avoid | |
13 | * unnecessary i-cache flushing. | |
569c8bf5 JL |
14 | * 04/07/.. ak Better overflow handling. Assorted fixes. |
15 | * 05/09/10 linville Add support for syncing ranges, support syncing for | |
16 | * DMA_BIDIRECTIONAL mappings, miscellaneous cleanup. | |
fb05a379 | 17 | * 08/12/11 beckyb Add highmem support |
1da177e4 LT |
18 | */ |
19 | ||
7d63fb3a KC |
20 | #define pr_fmt(fmt) "software IO TLB: " fmt |
21 | ||
1da177e4 | 22 | #include <linux/cache.h> |
ea8c64ac | 23 | #include <linux/dma-direct.h> |
1da177e4 | 24 | #include <linux/mm.h> |
8bc3bcc9 | 25 | #include <linux/export.h> |
1da177e4 LT |
26 | #include <linux/spinlock.h> |
27 | #include <linux/string.h> | |
0016fdee | 28 | #include <linux/swiotlb.h> |
fb05a379 | 29 | #include <linux/pfn.h> |
1da177e4 LT |
30 | #include <linux/types.h> |
31 | #include <linux/ctype.h> | |
ef9b1893 | 32 | #include <linux/highmem.h> |
5a0e3ad6 | 33 | #include <linux/gfp.h> |
84be456f | 34 | #include <linux/scatterlist.h> |
c7753208 | 35 | #include <linux/mem_encrypt.h> |
e7de6c7c | 36 | #include <linux/set_memory.h> |
71602fe6 DZ |
37 | #ifdef CONFIG_DEBUG_FS |
38 | #include <linux/debugfs.h> | |
39 | #endif | |
1da177e4 LT |
40 | |
41 | #include <asm/io.h> | |
1da177e4 LT |
42 | #include <asm/dma.h> |
43 | ||
44 | #include <linux/init.h> | |
57c8a661 | 45 | #include <linux/memblock.h> |
a8522509 | 46 | #include <linux/iommu-helper.h> |
1da177e4 | 47 | |
ce5be5a1 | 48 | #define CREATE_TRACE_POINTS |
2b2b614d ZK |
49 | #include <trace/events/swiotlb.h> |
50 | ||
1da177e4 LT |
51 | #define OFFSET(val,align) ((unsigned long) \ |
52 | ( (val) & ( (align) - 1))) | |
53 | ||
0b9afede AW |
54 | #define SLABS_PER_PAGE (1 << (PAGE_SHIFT - IO_TLB_SHIFT)) |
55 | ||
56 | /* | |
57 | * Minimum IO TLB size to bother booting with. Systems with mainly | |
58 | * 64bit capable cards will only lightly use the swiotlb. If we can't | |
59 | * allocate a contiguous 1MB, we're probably in trouble anyway. | |
60 | */ | |
61 | #define IO_TLB_MIN_SLABS ((1<<20) >> IO_TLB_SHIFT) | |
62 | ||
ae7871be | 63 | enum swiotlb_force swiotlb_force; |
1da177e4 LT |
64 | |
65 | /* | |
bfc5501f KRW |
66 | * Used to do a quick range check in swiotlb_tbl_unmap_single and |
67 | * swiotlb_tbl_sync_single_*, to see if the memory was in fact allocated by this | |
1da177e4 LT |
68 | * API. |
69 | */ | |
55897af6 | 70 | phys_addr_t io_tlb_start, io_tlb_end; |
1da177e4 LT |
71 | |
72 | /* | |
b595076a | 73 | * The number of IO TLB blocks (in groups of 64) between io_tlb_start and |
1da177e4 LT |
74 | * io_tlb_end. This is command line adjustable via setup_io_tlb_npages. |
75 | */ | |
76 | static unsigned long io_tlb_nslabs; | |
77 | ||
71602fe6 DZ |
78 | /* |
79 | * The number of used IO TLB block | |
80 | */ | |
81 | static unsigned long io_tlb_used; | |
82 | ||
1da177e4 LT |
83 | /* |
84 | * This is a free list describing the number of free entries available from | |
85 | * each index | |
86 | */ | |
87 | static unsigned int *io_tlb_list; | |
88 | static unsigned int io_tlb_index; | |
89 | ||
7453c549 KRW |
90 | /* |
91 | * Max segment that we can provide which (if pages are contingous) will | |
92 | * not be bounced (unless SWIOTLB_FORCE is set). | |
93 | */ | |
94 | unsigned int max_segment; | |
95 | ||
1da177e4 LT |
96 | /* |
97 | * We need to save away the original address corresponding to a mapped entry | |
98 | * for the sync operations. | |
99 | */ | |
8e0629c1 | 100 | #define INVALID_PHYS_ADDR (~(phys_addr_t)0) |
bc40ac66 | 101 | static phys_addr_t *io_tlb_orig_addr; |
1da177e4 LT |
102 | |
103 | /* | |
104 | * Protect the above data structures in the map and unmap calls | |
105 | */ | |
106 | static DEFINE_SPINLOCK(io_tlb_lock); | |
107 | ||
5740afdb FT |
108 | static int late_alloc; |
109 | ||
1da177e4 LT |
110 | static int __init |
111 | setup_io_tlb_npages(char *str) | |
112 | { | |
113 | if (isdigit(*str)) { | |
e8579e72 | 114 | io_tlb_nslabs = simple_strtoul(str, &str, 0); |
1da177e4 LT |
115 | /* avoid tail segment of size < IO_TLB_SEGSIZE */ |
116 | io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE); | |
117 | } | |
118 | if (*str == ',') | |
119 | ++str; | |
fff5d992 | 120 | if (!strcmp(str, "force")) { |
ae7871be | 121 | swiotlb_force = SWIOTLB_FORCE; |
fff5d992 GU |
122 | } else if (!strcmp(str, "noforce")) { |
123 | swiotlb_force = SWIOTLB_NO_FORCE; | |
124 | io_tlb_nslabs = 1; | |
125 | } | |
b18485e7 | 126 | |
c729de8f | 127 | return 0; |
1da177e4 | 128 | } |
c729de8f | 129 | early_param("swiotlb", setup_io_tlb_npages); |
1da177e4 | 130 | |
f21ffe9f | 131 | unsigned long swiotlb_nr_tbl(void) |
5f98ecdb FT |
132 | { |
133 | return io_tlb_nslabs; | |
134 | } | |
f21ffe9f | 135 | EXPORT_SYMBOL_GPL(swiotlb_nr_tbl); |
c729de8f | 136 | |
7453c549 KRW |
137 | unsigned int swiotlb_max_segment(void) |
138 | { | |
139 | return max_segment; | |
140 | } | |
141 | EXPORT_SYMBOL_GPL(swiotlb_max_segment); | |
142 | ||
143 | void swiotlb_set_max_segment(unsigned int val) | |
144 | { | |
145 | if (swiotlb_force == SWIOTLB_FORCE) | |
146 | max_segment = 1; | |
147 | else | |
148 | max_segment = rounddown(val, PAGE_SIZE); | |
149 | } | |
150 | ||
c729de8f YL |
151 | /* default to 64MB */ |
152 | #define IO_TLB_DEFAULT_SIZE (64UL<<20) | |
153 | unsigned long swiotlb_size_or_default(void) | |
154 | { | |
155 | unsigned long size; | |
156 | ||
157 | size = io_tlb_nslabs << IO_TLB_SHIFT; | |
158 | ||
159 | return size ? size : (IO_TLB_DEFAULT_SIZE); | |
160 | } | |
161 | ||
ac2cbab2 YL |
162 | static bool no_iotlb_memory; |
163 | ||
ad32e8cb | 164 | void swiotlb_print_info(void) |
2e5b2b86 | 165 | { |
ad32e8cb | 166 | unsigned long bytes = io_tlb_nslabs << IO_TLB_SHIFT; |
2e5b2b86 | 167 | |
ac2cbab2 | 168 | if (no_iotlb_memory) { |
7d63fb3a | 169 | pr_warn("No low mem\n"); |
ac2cbab2 YL |
170 | return; |
171 | } | |
172 | ||
7d63fb3a | 173 | pr_info("mapped [mem %#010llx-%#010llx] (%luMB)\n", |
ff7204a7 | 174 | (unsigned long long)io_tlb_start, |
c40dba06 | 175 | (unsigned long long)io_tlb_end, |
7d63fb3a | 176 | bytes >> 20); |
2e5b2b86 IC |
177 | } |
178 | ||
c7753208 TL |
179 | /* |
180 | * Early SWIOTLB allocation may be too early to allow an architecture to | |
181 | * perform the desired operations. This function allows the architecture to | |
182 | * call SWIOTLB when the operations are possible. It needs to be called | |
183 | * before the SWIOTLB memory is used. | |
184 | */ | |
185 | void __init swiotlb_update_mem_attributes(void) | |
186 | { | |
187 | void *vaddr; | |
188 | unsigned long bytes; | |
189 | ||
190 | if (no_iotlb_memory || late_alloc) | |
191 | return; | |
192 | ||
193 | vaddr = phys_to_virt(io_tlb_start); | |
194 | bytes = PAGE_ALIGN(io_tlb_nslabs << IO_TLB_SHIFT); | |
e7de6c7c | 195 | set_memory_decrypted((unsigned long)vaddr, bytes >> PAGE_SHIFT); |
c7753208 | 196 | memset(vaddr, 0, bytes); |
c7753208 TL |
197 | } |
198 | ||
ac2cbab2 | 199 | int __init swiotlb_init_with_tbl(char *tlb, unsigned long nslabs, int verbose) |
1da177e4 | 200 | { |
563aaf06 | 201 | unsigned long i, bytes; |
a0bf842e | 202 | size_t alloc_size; |
1da177e4 | 203 | |
abbceff7 | 204 | bytes = nslabs << IO_TLB_SHIFT; |
1da177e4 | 205 | |
abbceff7 | 206 | io_tlb_nslabs = nslabs; |
ff7204a7 AD |
207 | io_tlb_start = __pa(tlb); |
208 | io_tlb_end = io_tlb_start + bytes; | |
1da177e4 LT |
209 | |
210 | /* | |
211 | * Allocate and initialize the free list array. This array is used | |
212 | * to find contiguous free memory regions of size up to IO_TLB_SEGSIZE | |
213 | * between io_tlb_start and io_tlb_end. | |
214 | */ | |
a0bf842e MR |
215 | alloc_size = PAGE_ALIGN(io_tlb_nslabs * sizeof(int)); |
216 | io_tlb_list = memblock_alloc(alloc_size, PAGE_SIZE); | |
217 | if (!io_tlb_list) | |
218 | panic("%s: Failed to allocate %lu bytes align=0x%lx\n", | |
219 | __func__, alloc_size, PAGE_SIZE); | |
220 | ||
221 | alloc_size = PAGE_ALIGN(io_tlb_nslabs * sizeof(phys_addr_t)); | |
222 | io_tlb_orig_addr = memblock_alloc(alloc_size, PAGE_SIZE); | |
223 | if (!io_tlb_orig_addr) | |
224 | panic("%s: Failed to allocate %lu bytes align=0x%lx\n", | |
225 | __func__, alloc_size, PAGE_SIZE); | |
226 | ||
8e0629c1 JB |
227 | for (i = 0; i < io_tlb_nslabs; i++) { |
228 | io_tlb_list[i] = IO_TLB_SEGSIZE - OFFSET(i, IO_TLB_SEGSIZE); | |
229 | io_tlb_orig_addr[i] = INVALID_PHYS_ADDR; | |
230 | } | |
231 | io_tlb_index = 0; | |
1da177e4 | 232 | |
ad32e8cb FT |
233 | if (verbose) |
234 | swiotlb_print_info(); | |
ac2cbab2 | 235 | |
7453c549 | 236 | swiotlb_set_max_segment(io_tlb_nslabs << IO_TLB_SHIFT); |
ac2cbab2 | 237 | return 0; |
1da177e4 LT |
238 | } |
239 | ||
abbceff7 FT |
240 | /* |
241 | * Statically reserve bounce buffer space and initialize bounce buffer data | |
242 | * structures for the software IO TLB used to implement the DMA API. | |
243 | */ | |
ac2cbab2 YL |
244 | void __init |
245 | swiotlb_init(int verbose) | |
abbceff7 | 246 | { |
c729de8f | 247 | size_t default_size = IO_TLB_DEFAULT_SIZE; |
ff7204a7 | 248 | unsigned char *vstart; |
abbceff7 FT |
249 | unsigned long bytes; |
250 | ||
251 | if (!io_tlb_nslabs) { | |
252 | io_tlb_nslabs = (default_size >> IO_TLB_SHIFT); | |
253 | io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE); | |
254 | } | |
255 | ||
256 | bytes = io_tlb_nslabs << IO_TLB_SHIFT; | |
257 | ||
ac2cbab2 | 258 | /* Get IO TLB memory from the low pages */ |
eb31d559 | 259 | vstart = memblock_alloc_low_nopanic(PAGE_ALIGN(bytes), PAGE_SIZE); |
ac2cbab2 YL |
260 | if (vstart && !swiotlb_init_with_tbl(vstart, io_tlb_nslabs, verbose)) |
261 | return; | |
abbceff7 | 262 | |
ac2cbab2 | 263 | if (io_tlb_start) |
457ff1de SS |
264 | memblock_free_early(io_tlb_start, |
265 | PAGE_ALIGN(io_tlb_nslabs << IO_TLB_SHIFT)); | |
7d63fb3a | 266 | pr_warn("Cannot allocate buffer"); |
ac2cbab2 | 267 | no_iotlb_memory = true; |
1da177e4 LT |
268 | } |
269 | ||
0b9afede AW |
270 | /* |
271 | * Systems with larger DMA zones (those that don't support ISA) can | |
272 | * initialize the swiotlb later using the slab allocator if needed. | |
273 | * This should be just like above, but with some error catching. | |
274 | */ | |
275 | int | |
563aaf06 | 276 | swiotlb_late_init_with_default_size(size_t default_size) |
0b9afede | 277 | { |
74838b75 | 278 | unsigned long bytes, req_nslabs = io_tlb_nslabs; |
ff7204a7 | 279 | unsigned char *vstart = NULL; |
0b9afede | 280 | unsigned int order; |
74838b75 | 281 | int rc = 0; |
0b9afede AW |
282 | |
283 | if (!io_tlb_nslabs) { | |
284 | io_tlb_nslabs = (default_size >> IO_TLB_SHIFT); | |
285 | io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE); | |
286 | } | |
287 | ||
288 | /* | |
289 | * Get IO TLB memory from the low pages | |
290 | */ | |
563aaf06 | 291 | order = get_order(io_tlb_nslabs << IO_TLB_SHIFT); |
0b9afede | 292 | io_tlb_nslabs = SLABS_PER_PAGE << order; |
563aaf06 | 293 | bytes = io_tlb_nslabs << IO_TLB_SHIFT; |
0b9afede AW |
294 | |
295 | while ((SLABS_PER_PAGE << order) > IO_TLB_MIN_SLABS) { | |
ff7204a7 AD |
296 | vstart = (void *)__get_free_pages(GFP_DMA | __GFP_NOWARN, |
297 | order); | |
298 | if (vstart) | |
0b9afede AW |
299 | break; |
300 | order--; | |
301 | } | |
302 | ||
ff7204a7 | 303 | if (!vstart) { |
74838b75 KRW |
304 | io_tlb_nslabs = req_nslabs; |
305 | return -ENOMEM; | |
306 | } | |
563aaf06 | 307 | if (order != get_order(bytes)) { |
7d63fb3a KC |
308 | pr_warn("only able to allocate %ld MB\n", |
309 | (PAGE_SIZE << order) >> 20); | |
0b9afede AW |
310 | io_tlb_nslabs = SLABS_PER_PAGE << order; |
311 | } | |
ff7204a7 | 312 | rc = swiotlb_late_init_with_tbl(vstart, io_tlb_nslabs); |
74838b75 | 313 | if (rc) |
ff7204a7 | 314 | free_pages((unsigned long)vstart, order); |
7453c549 | 315 | |
74838b75 KRW |
316 | return rc; |
317 | } | |
318 | ||
319 | int | |
320 | swiotlb_late_init_with_tbl(char *tlb, unsigned long nslabs) | |
321 | { | |
322 | unsigned long i, bytes; | |
323 | ||
324 | bytes = nslabs << IO_TLB_SHIFT; | |
325 | ||
326 | io_tlb_nslabs = nslabs; | |
ff7204a7 AD |
327 | io_tlb_start = virt_to_phys(tlb); |
328 | io_tlb_end = io_tlb_start + bytes; | |
74838b75 | 329 | |
e7de6c7c | 330 | set_memory_decrypted((unsigned long)tlb, bytes >> PAGE_SHIFT); |
ff7204a7 | 331 | memset(tlb, 0, bytes); |
0b9afede AW |
332 | |
333 | /* | |
334 | * Allocate and initialize the free list array. This array is used | |
335 | * to find contiguous free memory regions of size up to IO_TLB_SEGSIZE | |
336 | * between io_tlb_start and io_tlb_end. | |
337 | */ | |
338 | io_tlb_list = (unsigned int *)__get_free_pages(GFP_KERNEL, | |
339 | get_order(io_tlb_nslabs * sizeof(int))); | |
340 | if (!io_tlb_list) | |
ee3f6ba8 | 341 | goto cleanup3; |
0b9afede | 342 | |
bc40ac66 BB |
343 | io_tlb_orig_addr = (phys_addr_t *) |
344 | __get_free_pages(GFP_KERNEL, | |
345 | get_order(io_tlb_nslabs * | |
346 | sizeof(phys_addr_t))); | |
0b9afede | 347 | if (!io_tlb_orig_addr) |
ee3f6ba8 | 348 | goto cleanup4; |
0b9afede | 349 | |
8e0629c1 JB |
350 | for (i = 0; i < io_tlb_nslabs; i++) { |
351 | io_tlb_list[i] = IO_TLB_SEGSIZE - OFFSET(i, IO_TLB_SEGSIZE); | |
352 | io_tlb_orig_addr[i] = INVALID_PHYS_ADDR; | |
353 | } | |
354 | io_tlb_index = 0; | |
0b9afede | 355 | |
ad32e8cb | 356 | swiotlb_print_info(); |
0b9afede | 357 | |
5740afdb FT |
358 | late_alloc = 1; |
359 | ||
7453c549 KRW |
360 | swiotlb_set_max_segment(io_tlb_nslabs << IO_TLB_SHIFT); |
361 | ||
0b9afede AW |
362 | return 0; |
363 | ||
364 | cleanup4: | |
25667d67 TL |
365 | free_pages((unsigned long)io_tlb_list, get_order(io_tlb_nslabs * |
366 | sizeof(int))); | |
0b9afede | 367 | io_tlb_list = NULL; |
ee3f6ba8 | 368 | cleanup3: |
c40dba06 | 369 | io_tlb_end = 0; |
ff7204a7 | 370 | io_tlb_start = 0; |
74838b75 | 371 | io_tlb_nslabs = 0; |
7453c549 | 372 | max_segment = 0; |
0b9afede AW |
373 | return -ENOMEM; |
374 | } | |
375 | ||
7f2c8bbd | 376 | void __init swiotlb_exit(void) |
5740afdb | 377 | { |
ee3f6ba8 | 378 | if (!io_tlb_orig_addr) |
5740afdb FT |
379 | return; |
380 | ||
381 | if (late_alloc) { | |
5740afdb FT |
382 | free_pages((unsigned long)io_tlb_orig_addr, |
383 | get_order(io_tlb_nslabs * sizeof(phys_addr_t))); | |
384 | free_pages((unsigned long)io_tlb_list, get_order(io_tlb_nslabs * | |
385 | sizeof(int))); | |
ff7204a7 | 386 | free_pages((unsigned long)phys_to_virt(io_tlb_start), |
5740afdb FT |
387 | get_order(io_tlb_nslabs << IO_TLB_SHIFT)); |
388 | } else { | |
457ff1de SS |
389 | memblock_free_late(__pa(io_tlb_orig_addr), |
390 | PAGE_ALIGN(io_tlb_nslabs * sizeof(phys_addr_t))); | |
391 | memblock_free_late(__pa(io_tlb_list), | |
392 | PAGE_ALIGN(io_tlb_nslabs * sizeof(int))); | |
393 | memblock_free_late(io_tlb_start, | |
394 | PAGE_ALIGN(io_tlb_nslabs << IO_TLB_SHIFT)); | |
5740afdb | 395 | } |
227a76b6 CH |
396 | io_tlb_start = 0; |
397 | io_tlb_end = 0; | |
f21ffe9f | 398 | io_tlb_nslabs = 0; |
7453c549 | 399 | max_segment = 0; |
5740afdb FT |
400 | } |
401 | ||
fb05a379 | 402 | /* |
6442ca2a | 403 | * Bounce: copy the swiotlb buffer from or back to the original dma location |
fb05a379 | 404 | */ |
af51a9f1 AD |
405 | static void swiotlb_bounce(phys_addr_t orig_addr, phys_addr_t tlb_addr, |
406 | size_t size, enum dma_data_direction dir) | |
fb05a379 | 407 | { |
af51a9f1 AD |
408 | unsigned long pfn = PFN_DOWN(orig_addr); |
409 | unsigned char *vaddr = phys_to_virt(tlb_addr); | |
fb05a379 BB |
410 | |
411 | if (PageHighMem(pfn_to_page(pfn))) { | |
412 | /* The buffer does not have a mapping. Map it in and copy */ | |
af51a9f1 | 413 | unsigned int offset = orig_addr & ~PAGE_MASK; |
fb05a379 BB |
414 | char *buffer; |
415 | unsigned int sz = 0; | |
416 | unsigned long flags; | |
417 | ||
418 | while (size) { | |
67131ad0 | 419 | sz = min_t(size_t, PAGE_SIZE - offset, size); |
fb05a379 BB |
420 | |
421 | local_irq_save(flags); | |
c3eede8e | 422 | buffer = kmap_atomic(pfn_to_page(pfn)); |
fb05a379 | 423 | if (dir == DMA_TO_DEVICE) |
af51a9f1 | 424 | memcpy(vaddr, buffer + offset, sz); |
ef9b1893 | 425 | else |
af51a9f1 | 426 | memcpy(buffer + offset, vaddr, sz); |
c3eede8e | 427 | kunmap_atomic(buffer); |
ef9b1893 | 428 | local_irq_restore(flags); |
fb05a379 BB |
429 | |
430 | size -= sz; | |
431 | pfn++; | |
af51a9f1 | 432 | vaddr += sz; |
fb05a379 | 433 | offset = 0; |
ef9b1893 | 434 | } |
af51a9f1 AD |
435 | } else if (dir == DMA_TO_DEVICE) { |
436 | memcpy(vaddr, phys_to_virt(orig_addr), size); | |
ef9b1893 | 437 | } else { |
af51a9f1 | 438 | memcpy(phys_to_virt(orig_addr), vaddr, size); |
ef9b1893 | 439 | } |
1b548f66 JF |
440 | } |
441 | ||
e05ed4d1 AD |
442 | phys_addr_t swiotlb_tbl_map_single(struct device *hwdev, |
443 | dma_addr_t tbl_dma_addr, | |
444 | phys_addr_t orig_addr, size_t size, | |
0443fa00 AD |
445 | enum dma_data_direction dir, |
446 | unsigned long attrs) | |
1da177e4 LT |
447 | { |
448 | unsigned long flags; | |
e05ed4d1 | 449 | phys_addr_t tlb_addr; |
1da177e4 LT |
450 | unsigned int nslots, stride, index, wrap; |
451 | int i; | |
681cc5cd FT |
452 | unsigned long mask; |
453 | unsigned long offset_slots; | |
454 | unsigned long max_slots; | |
455 | ||
ac2cbab2 YL |
456 | if (no_iotlb_memory) |
457 | panic("Can not allocate SWIOTLB buffer earlier and can't now provide you with the DMA bounce buffer"); | |
458 | ||
d7b417fa TL |
459 | if (mem_encrypt_active()) |
460 | pr_warn_once("%s is active and system is using DMA bounce buffers\n", | |
461 | sme_active() ? "SME" : "SEV"); | |
648babb7 | 462 | |
681cc5cd | 463 | mask = dma_get_seg_boundary(hwdev); |
681cc5cd | 464 | |
eb605a57 FT |
465 | tbl_dma_addr &= mask; |
466 | ||
467 | offset_slots = ALIGN(tbl_dma_addr, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT; | |
a5ddde4a IC |
468 | |
469 | /* | |
470 | * Carefully handle integer overflow which can occur when mask == ~0UL. | |
471 | */ | |
b15a3891 JB |
472 | max_slots = mask + 1 |
473 | ? ALIGN(mask + 1, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT | |
474 | : 1UL << (BITS_PER_LONG - IO_TLB_SHIFT); | |
1da177e4 LT |
475 | |
476 | /* | |
602d9858 NY |
477 | * For mappings greater than or equal to a page, we limit the stride |
478 | * (and hence alignment) to a page size. | |
1da177e4 LT |
479 | */ |
480 | nslots = ALIGN(size, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT; | |
602d9858 | 481 | if (size >= PAGE_SIZE) |
1da177e4 LT |
482 | stride = (1 << (PAGE_SHIFT - IO_TLB_SHIFT)); |
483 | else | |
484 | stride = 1; | |
485 | ||
34814545 | 486 | BUG_ON(!nslots); |
1da177e4 LT |
487 | |
488 | /* | |
489 | * Find suitable number of IO TLB entries size that will fit this | |
490 | * request and allocate a buffer from that IO TLB pool. | |
491 | */ | |
492 | spin_lock_irqsave(&io_tlb_lock, flags); | |
60513ed0 DZ |
493 | |
494 | if (unlikely(nslots > io_tlb_nslabs - io_tlb_used)) | |
495 | goto not_found; | |
496 | ||
a7133a15 AM |
497 | index = ALIGN(io_tlb_index, stride); |
498 | if (index >= io_tlb_nslabs) | |
499 | index = 0; | |
500 | wrap = index; | |
501 | ||
502 | do { | |
a8522509 FT |
503 | while (iommu_is_span_boundary(index, nslots, offset_slots, |
504 | max_slots)) { | |
b15a3891 JB |
505 | index += stride; |
506 | if (index >= io_tlb_nslabs) | |
507 | index = 0; | |
a7133a15 AM |
508 | if (index == wrap) |
509 | goto not_found; | |
510 | } | |
511 | ||
512 | /* | |
513 | * If we find a slot that indicates we have 'nslots' number of | |
514 | * contiguous buffers, we allocate the buffers from that slot | |
515 | * and mark the entries as '0' indicating unavailable. | |
516 | */ | |
517 | if (io_tlb_list[index] >= nslots) { | |
518 | int count = 0; | |
519 | ||
520 | for (i = index; i < (int) (index + nslots); i++) | |
521 | io_tlb_list[i] = 0; | |
522 | for (i = index - 1; (OFFSET(i, IO_TLB_SEGSIZE) != IO_TLB_SEGSIZE - 1) && io_tlb_list[i]; i--) | |
523 | io_tlb_list[i] = ++count; | |
e05ed4d1 | 524 | tlb_addr = io_tlb_start + (index << IO_TLB_SHIFT); |
1da177e4 | 525 | |
a7133a15 AM |
526 | /* |
527 | * Update the indices to avoid searching in the next | |
528 | * round. | |
529 | */ | |
530 | io_tlb_index = ((index + nslots) < io_tlb_nslabs | |
531 | ? (index + nslots) : 0); | |
532 | ||
533 | goto found; | |
534 | } | |
535 | index += stride; | |
536 | if (index >= io_tlb_nslabs) | |
537 | index = 0; | |
538 | } while (index != wrap); | |
539 | ||
540 | not_found: | |
541 | spin_unlock_irqrestore(&io_tlb_lock, flags); | |
d0bc0c2a | 542 | if (!(attrs & DMA_ATTR_NO_WARN) && printk_ratelimit()) |
0cb637bf | 543 | dev_warn(hwdev, "swiotlb buffer is full (sz: %zd bytes)\n", size); |
b907e205 | 544 | return DMA_MAPPING_ERROR; |
a7133a15 | 545 | found: |
71602fe6 | 546 | io_tlb_used += nslots; |
1da177e4 LT |
547 | spin_unlock_irqrestore(&io_tlb_lock, flags); |
548 | ||
549 | /* | |
550 | * Save away the mapping from the original address to the DMA address. | |
551 | * This is needed when we sync the memory. Then we sync the buffer if | |
552 | * needed. | |
553 | */ | |
bc40ac66 | 554 | for (i = 0; i < nslots; i++) |
e05ed4d1 | 555 | io_tlb_orig_addr[index+i] = orig_addr + (i << IO_TLB_SHIFT); |
0443fa00 AD |
556 | if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC) && |
557 | (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL)) | |
af51a9f1 | 558 | swiotlb_bounce(orig_addr, tlb_addr, size, DMA_TO_DEVICE); |
1da177e4 | 559 | |
e05ed4d1 | 560 | return tlb_addr; |
1da177e4 LT |
561 | } |
562 | ||
563 | /* | |
d0c8ba40 | 564 | * tlb_addr is the physical address of the bounce buffer to unmap. |
1da177e4 | 565 | */ |
61ca08c3 | 566 | void swiotlb_tbl_unmap_single(struct device *hwdev, phys_addr_t tlb_addr, |
0443fa00 AD |
567 | size_t size, enum dma_data_direction dir, |
568 | unsigned long attrs) | |
1da177e4 LT |
569 | { |
570 | unsigned long flags; | |
571 | int i, count, nslots = ALIGN(size, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT; | |
61ca08c3 AD |
572 | int index = (tlb_addr - io_tlb_start) >> IO_TLB_SHIFT; |
573 | phys_addr_t orig_addr = io_tlb_orig_addr[index]; | |
1da177e4 LT |
574 | |
575 | /* | |
576 | * First, sync the memory before unmapping the entry | |
577 | */ | |
8e0629c1 | 578 | if (orig_addr != INVALID_PHYS_ADDR && |
0443fa00 | 579 | !(attrs & DMA_ATTR_SKIP_CPU_SYNC) && |
8e0629c1 | 580 | ((dir == DMA_FROM_DEVICE) || (dir == DMA_BIDIRECTIONAL))) |
af51a9f1 | 581 | swiotlb_bounce(orig_addr, tlb_addr, size, DMA_FROM_DEVICE); |
1da177e4 LT |
582 | |
583 | /* | |
584 | * Return the buffer to the free list by setting the corresponding | |
af901ca1 | 585 | * entries to indicate the number of contiguous entries available. |
1da177e4 LT |
586 | * While returning the entries to the free list, we merge the entries |
587 | * with slots below and above the pool being returned. | |
588 | */ | |
589 | spin_lock_irqsave(&io_tlb_lock, flags); | |
590 | { | |
591 | count = ((index + nslots) < ALIGN(index + 1, IO_TLB_SEGSIZE) ? | |
592 | io_tlb_list[index + nslots] : 0); | |
593 | /* | |
594 | * Step 1: return the slots to the free list, merging the | |
595 | * slots with superceeding slots | |
596 | */ | |
8e0629c1 | 597 | for (i = index + nslots - 1; i >= index; i--) { |
1da177e4 | 598 | io_tlb_list[i] = ++count; |
8e0629c1 JB |
599 | io_tlb_orig_addr[i] = INVALID_PHYS_ADDR; |
600 | } | |
1da177e4 LT |
601 | /* |
602 | * Step 2: merge the returned slots with the preceding slots, | |
603 | * if available (non zero) | |
604 | */ | |
605 | for (i = index - 1; (OFFSET(i, IO_TLB_SEGSIZE) != IO_TLB_SEGSIZE -1) && io_tlb_list[i]; i--) | |
606 | io_tlb_list[i] = ++count; | |
71602fe6 DZ |
607 | |
608 | io_tlb_used -= nslots; | |
1da177e4 LT |
609 | } |
610 | spin_unlock_irqrestore(&io_tlb_lock, flags); | |
611 | } | |
612 | ||
fbfda893 AD |
613 | void swiotlb_tbl_sync_single(struct device *hwdev, phys_addr_t tlb_addr, |
614 | size_t size, enum dma_data_direction dir, | |
615 | enum dma_sync_target target) | |
1da177e4 | 616 | { |
fbfda893 AD |
617 | int index = (tlb_addr - io_tlb_start) >> IO_TLB_SHIFT; |
618 | phys_addr_t orig_addr = io_tlb_orig_addr[index]; | |
bc40ac66 | 619 | |
8e0629c1 JB |
620 | if (orig_addr == INVALID_PHYS_ADDR) |
621 | return; | |
fbfda893 | 622 | orig_addr += (unsigned long)tlb_addr & ((1 << IO_TLB_SHIFT) - 1); |
df336d1c | 623 | |
de69e0f0 JL |
624 | switch (target) { |
625 | case SYNC_FOR_CPU: | |
626 | if (likely(dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)) | |
af51a9f1 | 627 | swiotlb_bounce(orig_addr, tlb_addr, |
fbfda893 | 628 | size, DMA_FROM_DEVICE); |
34814545 ES |
629 | else |
630 | BUG_ON(dir != DMA_TO_DEVICE); | |
de69e0f0 JL |
631 | break; |
632 | case SYNC_FOR_DEVICE: | |
633 | if (likely(dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL)) | |
af51a9f1 | 634 | swiotlb_bounce(orig_addr, tlb_addr, |
fbfda893 | 635 | size, DMA_TO_DEVICE); |
34814545 ES |
636 | else |
637 | BUG_ON(dir != DMA_FROM_DEVICE); | |
de69e0f0 JL |
638 | break; |
639 | default: | |
1da177e4 | 640 | BUG(); |
de69e0f0 | 641 | } |
1da177e4 LT |
642 | } |
643 | ||
55897af6 CH |
644 | /* |
645 | * Create a swiotlb mapping for the buffer at @phys, and in case of DMAing | |
646 | * to the device copy the data into it as well. | |
647 | */ | |
648 | bool swiotlb_map(struct device *dev, phys_addr_t *phys, dma_addr_t *dma_addr, | |
c4dae366 CH |
649 | size_t size, enum dma_data_direction dir, unsigned long attrs) |
650 | { | |
55897af6 | 651 | trace_swiotlb_bounced(dev, *dma_addr, size, swiotlb_force); |
c4dae366 CH |
652 | |
653 | if (unlikely(swiotlb_force == SWIOTLB_NO_FORCE)) { | |
654 | dev_warn_ratelimited(dev, | |
655 | "Cannot do DMA to address %pa\n", phys); | |
55897af6 | 656 | return false; |
c4dae366 CH |
657 | } |
658 | ||
659 | /* Oh well, have to allocate and map a bounce buffer. */ | |
660 | *phys = swiotlb_tbl_map_single(dev, __phys_to_dma(dev, io_tlb_start), | |
661 | *phys, size, dir, attrs); | |
b907e205 | 662 | if (*phys == DMA_MAPPING_ERROR) |
55897af6 | 663 | return false; |
c4dae366 CH |
664 | |
665 | /* Ensure that the address returned is DMA'ble */ | |
55897af6 CH |
666 | *dma_addr = __phys_to_dma(dev, *phys); |
667 | if (unlikely(!dma_capable(dev, *dma_addr, size))) { | |
c4dae366 CH |
668 | swiotlb_tbl_unmap_single(dev, *phys, size, dir, |
669 | attrs | DMA_ATTR_SKIP_CPU_SYNC); | |
55897af6 | 670 | return false; |
a4a4330d CH |
671 | } |
672 | ||
55897af6 | 673 | return true; |
1da177e4 LT |
674 | } |
675 | ||
abe420bf JR |
676 | size_t swiotlb_max_mapping_size(struct device *dev) |
677 | { | |
678 | return ((size_t)1 << IO_TLB_SHIFT) * IO_TLB_SEGSIZE; | |
679 | } | |
492366f7 JR |
680 | |
681 | bool is_swiotlb_active(void) | |
682 | { | |
683 | /* | |
684 | * When SWIOTLB is initialized, even if io_tlb_start points to physical | |
685 | * address zero, io_tlb_end surely doesn't. | |
686 | */ | |
687 | return io_tlb_end != 0; | |
688 | } | |
45ba8d5d | 689 | |
71602fe6 DZ |
690 | #ifdef CONFIG_DEBUG_FS |
691 | ||
692 | static int __init swiotlb_create_debugfs(void) | |
693 | { | |
22cb45d7 | 694 | struct dentry *d_swiotlb_usage; |
71602fe6 DZ |
695 | struct dentry *ent; |
696 | ||
697 | d_swiotlb_usage = debugfs_create_dir("swiotlb", NULL); | |
698 | ||
699 | if (!d_swiotlb_usage) | |
700 | return -ENOMEM; | |
701 | ||
702 | ent = debugfs_create_ulong("io_tlb_nslabs", 0400, | |
703 | d_swiotlb_usage, &io_tlb_nslabs); | |
704 | if (!ent) | |
705 | goto fail; | |
706 | ||
707 | ent = debugfs_create_ulong("io_tlb_used", 0400, | |
708 | d_swiotlb_usage, &io_tlb_used); | |
709 | if (!ent) | |
710 | goto fail; | |
711 | ||
712 | return 0; | |
713 | ||
714 | fail: | |
715 | debugfs_remove_recursive(d_swiotlb_usage); | |
716 | return -ENOMEM; | |
717 | } | |
718 | ||
719 | late_initcall(swiotlb_create_debugfs); | |
720 | ||
721 | #endif |