]>
Commit | Line | Data |
---|---|---|
eadd0e44 PM |
1 | /* |
2 | * Copyright (C) 2012 - Virtual Open Systems and Columbia University | |
3 | * Author: Christoffer Dall <c.dall@virtualopensystems.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License, version 2, as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | |
17 | */ | |
18 | ||
19 | #ifndef __ARM_KVM_H__ | |
20 | #define __ARM_KVM_H__ | |
21 | ||
22 | #include <linux/types.h> | |
23 | #include <asm/ptrace.h> | |
24 | ||
25 | #define __KVM_HAVE_GUEST_DEBUG | |
26 | #define __KVM_HAVE_IRQ_LINE | |
27 | ||
28 | #define KVM_REG_SIZE(id) \ | |
29 | (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT)) | |
30 | ||
31 | /* Valid for svc_regs, abt_regs, und_regs, irq_regs in struct kvm_regs */ | |
32 | #define KVM_ARM_SVC_sp svc_regs[0] | |
33 | #define KVM_ARM_SVC_lr svc_regs[1] | |
34 | #define KVM_ARM_SVC_spsr svc_regs[2] | |
35 | #define KVM_ARM_ABT_sp abt_regs[0] | |
36 | #define KVM_ARM_ABT_lr abt_regs[1] | |
37 | #define KVM_ARM_ABT_spsr abt_regs[2] | |
38 | #define KVM_ARM_UND_sp und_regs[0] | |
39 | #define KVM_ARM_UND_lr und_regs[1] | |
40 | #define KVM_ARM_UND_spsr und_regs[2] | |
41 | #define KVM_ARM_IRQ_sp irq_regs[0] | |
42 | #define KVM_ARM_IRQ_lr irq_regs[1] | |
43 | #define KVM_ARM_IRQ_spsr irq_regs[2] | |
44 | ||
45 | /* Valid only for fiq_regs in struct kvm_regs */ | |
46 | #define KVM_ARM_FIQ_r8 fiq_regs[0] | |
47 | #define KVM_ARM_FIQ_r9 fiq_regs[1] | |
48 | #define KVM_ARM_FIQ_r10 fiq_regs[2] | |
49 | #define KVM_ARM_FIQ_fp fiq_regs[3] | |
50 | #define KVM_ARM_FIQ_ip fiq_regs[4] | |
51 | #define KVM_ARM_FIQ_sp fiq_regs[5] | |
52 | #define KVM_ARM_FIQ_lr fiq_regs[6] | |
53 | #define KVM_ARM_FIQ_spsr fiq_regs[7] | |
54 | ||
55 | struct kvm_regs { | |
56 | struct pt_regs usr_regs;/* R0_usr - R14_usr, PC, CPSR */ | |
57 | __u32 svc_regs[3]; /* SP_svc, LR_svc, SPSR_svc */ | |
58 | __u32 abt_regs[3]; /* SP_abt, LR_abt, SPSR_abt */ | |
59 | __u32 und_regs[3]; /* SP_und, LR_und, SPSR_und */ | |
60 | __u32 irq_regs[3]; /* SP_irq, LR_irq, SPSR_irq */ | |
61 | __u32 fiq_regs[8]; /* R8_fiq - R14_fiq, SPSR_fiq */ | |
62 | }; | |
63 | ||
64 | /* Supported Processor Types */ | |
65 | #define KVM_ARM_TARGET_CORTEX_A15 0 | |
66 | #define KVM_ARM_NUM_TARGETS 1 | |
67 | ||
68 | /* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */ | |
69 | #define KVM_ARM_DEVICE_TYPE_SHIFT 0 | |
70 | #define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT) | |
71 | #define KVM_ARM_DEVICE_ID_SHIFT 16 | |
72 | #define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT) | |
73 | ||
74 | /* Supported device IDs */ | |
75 | #define KVM_ARM_DEVICE_VGIC_V2 0 | |
76 | ||
77 | /* Supported VGIC address types */ | |
78 | #define KVM_VGIC_V2_ADDR_TYPE_DIST 0 | |
79 | #define KVM_VGIC_V2_ADDR_TYPE_CPU 1 | |
80 | ||
81 | #define KVM_VGIC_V2_DIST_SIZE 0x1000 | |
82 | #define KVM_VGIC_V2_CPU_SIZE 0x2000 | |
83 | ||
84 | #define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */ | |
85 | ||
86 | struct kvm_vcpu_init { | |
87 | __u32 target; | |
88 | __u32 features[7]; | |
89 | }; | |
90 | ||
91 | struct kvm_sregs { | |
92 | }; | |
93 | ||
94 | struct kvm_fpu { | |
95 | }; | |
96 | ||
97 | struct kvm_guest_debug_arch { | |
98 | }; | |
99 | ||
100 | struct kvm_debug_exit_arch { | |
101 | }; | |
102 | ||
103 | struct kvm_sync_regs { | |
104 | }; | |
105 | ||
106 | struct kvm_arch_memory_slot { | |
107 | }; | |
108 | ||
109 | /* If you need to interpret the index values, here is the key: */ | |
110 | #define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000 | |
111 | #define KVM_REG_ARM_COPROC_SHIFT 16 | |
112 | #define KVM_REG_ARM_32_OPC2_MASK 0x0000000000000007 | |
113 | #define KVM_REG_ARM_32_OPC2_SHIFT 0 | |
114 | #define KVM_REG_ARM_OPC1_MASK 0x0000000000000078 | |
115 | #define KVM_REG_ARM_OPC1_SHIFT 3 | |
116 | #define KVM_REG_ARM_CRM_MASK 0x0000000000000780 | |
117 | #define KVM_REG_ARM_CRM_SHIFT 7 | |
118 | #define KVM_REG_ARM_32_CRN_MASK 0x0000000000007800 | |
119 | #define KVM_REG_ARM_32_CRN_SHIFT 11 | |
120 | ||
121 | /* Normal registers are mapped as coprocessor 16. */ | |
122 | #define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT) | |
123 | #define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / 4) | |
124 | ||
125 | /* Some registers need more space to represent values. */ | |
126 | #define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT) | |
127 | #define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00 | |
128 | #define KVM_REG_ARM_DEMUX_ID_SHIFT 8 | |
129 | #define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT) | |
130 | #define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF | |
131 | #define KVM_REG_ARM_DEMUX_VAL_SHIFT 0 | |
132 | ||
133 | /* VFP registers: we could overload CP10 like ARM does, but that's ugly. */ | |
134 | #define KVM_REG_ARM_VFP (0x0012 << KVM_REG_ARM_COPROC_SHIFT) | |
135 | #define KVM_REG_ARM_VFP_MASK 0x000000000000FFFF | |
136 | #define KVM_REG_ARM_VFP_BASE_REG 0x0 | |
137 | #define KVM_REG_ARM_VFP_FPSID 0x1000 | |
138 | #define KVM_REG_ARM_VFP_FPSCR 0x1001 | |
139 | #define KVM_REG_ARM_VFP_MVFR1 0x1006 | |
140 | #define KVM_REG_ARM_VFP_MVFR0 0x1007 | |
141 | #define KVM_REG_ARM_VFP_FPEXC 0x1008 | |
142 | #define KVM_REG_ARM_VFP_FPINST 0x1009 | |
143 | #define KVM_REG_ARM_VFP_FPINST2 0x100A | |
144 | ||
145 | ||
146 | /* KVM_IRQ_LINE irq field index values */ | |
147 | #define KVM_ARM_IRQ_TYPE_SHIFT 24 | |
148 | #define KVM_ARM_IRQ_TYPE_MASK 0xff | |
149 | #define KVM_ARM_IRQ_VCPU_SHIFT 16 | |
150 | #define KVM_ARM_IRQ_VCPU_MASK 0xff | |
151 | #define KVM_ARM_IRQ_NUM_SHIFT 0 | |
152 | #define KVM_ARM_IRQ_NUM_MASK 0xffff | |
153 | ||
154 | /* irq_type field */ | |
155 | #define KVM_ARM_IRQ_TYPE_CPU 0 | |
156 | #define KVM_ARM_IRQ_TYPE_SPI 1 | |
157 | #define KVM_ARM_IRQ_TYPE_PPI 2 | |
158 | ||
159 | /* out-of-kernel GIC cpu interrupt injection irq_number field */ | |
160 | #define KVM_ARM_IRQ_CPU_IRQ 0 | |
161 | #define KVM_ARM_IRQ_CPU_FIQ 1 | |
162 | ||
163 | /* Highest supported SPI, from VGIC_NR_IRQS */ | |
164 | #define KVM_ARM_IRQ_GIC_MAX 127 | |
165 | ||
166 | /* PSCI interface */ | |
167 | #define KVM_PSCI_FN_BASE 0x95c1ba5e | |
168 | #define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n)) | |
169 | ||
170 | #define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0) | |
171 | #define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1) | |
172 | #define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2) | |
173 | #define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3) | |
174 | ||
175 | #define KVM_PSCI_RET_SUCCESS 0 | |
176 | #define KVM_PSCI_RET_NI ((unsigned long)-1) | |
177 | #define KVM_PSCI_RET_INVAL ((unsigned long)-2) | |
178 | #define KVM_PSCI_RET_DENIED ((unsigned long)-3) | |
179 | ||
180 | #endif /* __ARM_KVM_H__ */ |