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85e99cf8 | 1 | /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
e098b453 AK |
2 | /* |
3 | * This file is subject to the terms and conditions of the GNU General Public | |
4 | * License. See the file "COPYING" in the main directory of this archive | |
5 | * for more details. | |
6 | * | |
7 | * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. | |
8 | * Copyright (C) 2013 Cavium, Inc. | |
9 | * Authors: Sanjay Lal <sanjayl@kymasys.com> | |
10 | */ | |
11 | ||
12 | #ifndef __LINUX_KVM_MIPS_H | |
13 | #define __LINUX_KVM_MIPS_H | |
14 | ||
15 | #include <linux/types.h> | |
16 | ||
17 | /* | |
18 | * KVM MIPS specific structures and definitions. | |
19 | * | |
20 | * Some parts derived from the x86 version of this file. | |
21 | */ | |
22 | ||
85e99cf8 MT |
23 | #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 |
24 | ||
e098b453 AK |
25 | /* |
26 | * for KVM_GET_REGS and KVM_SET_REGS | |
27 | * | |
28 | * If Config[AT] is zero (32-bit CPU), the register contents are | |
29 | * stored in the lower 32-bits of the struct kvm_regs fields and sign | |
30 | * extended to 64-bits. | |
31 | */ | |
32 | struct kvm_regs { | |
33 | /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */ | |
34 | __u64 gpr[32]; | |
35 | __u64 hi; | |
36 | __u64 lo; | |
37 | __u64 pc; | |
38 | }; | |
39 | ||
40 | /* | |
41 | * for KVM_GET_FPU and KVM_SET_FPU | |
e098b453 AK |
42 | */ |
43 | struct kvm_fpu { | |
e098b453 AK |
44 | }; |
45 | ||
46 | ||
47 | /* | |
7a52ce8a | 48 | * For MIPS, we use KVM_SET_ONE_REG and KVM_GET_ONE_REG to access various |
e098b453 AK |
49 | * registers. The id field is broken down as follows: |
50 | * | |
c5daeae1 | 51 | * bits[63..52] - As per linux/kvm.h |
7a52ce8a CH |
52 | * bits[51..32] - Must be zero. |
53 | * bits[31..16] - Register set. | |
54 | * | |
55 | * Register set = 0: GP registers from kvm_regs (see definitions below). | |
56 | * | |
57 | * Register set = 1: CP0 registers. | |
85e99cf8 MT |
58 | * bits[15..8] - COP0 register set. |
59 | * | |
60 | * COP0 register set = 0: Main CP0 registers. | |
61 | * bits[7..3] - Register 'rd' index. | |
62 | * bits[2..0] - Register 'sel' index. | |
63 | * | |
64 | * COP0 register set = 1: MAARs. | |
65 | * bits[7..0] - MAAR index. | |
7a52ce8a CH |
66 | * |
67 | * Register set = 2: KVM specific registers (see definitions below). | |
68 | * | |
69 | * Register set = 3: FPU / MSA registers (see definitions below). | |
e098b453 AK |
70 | * |
71 | * Other sets registers may be added in the future. Each set would | |
c5daeae1 | 72 | * have its own identifier in bits[31..16]. |
e098b453 AK |
73 | */ |
74 | ||
7a52ce8a CH |
75 | #define KVM_REG_MIPS_GP (KVM_REG_MIPS | 0x0000000000000000ULL) |
76 | #define KVM_REG_MIPS_CP0 (KVM_REG_MIPS | 0x0000000000010000ULL) | |
77 | #define KVM_REG_MIPS_KVM (KVM_REG_MIPS | 0x0000000000020000ULL) | |
78 | #define KVM_REG_MIPS_FPU (KVM_REG_MIPS | 0x0000000000030000ULL) | |
79 | ||
80 | ||
81 | /* | |
82 | * KVM_REG_MIPS_GP - General purpose registers from kvm_regs. | |
83 | */ | |
84 | ||
85 | #define KVM_REG_MIPS_R0 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 0) | |
86 | #define KVM_REG_MIPS_R1 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 1) | |
87 | #define KVM_REG_MIPS_R2 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 2) | |
88 | #define KVM_REG_MIPS_R3 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 3) | |
89 | #define KVM_REG_MIPS_R4 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 4) | |
90 | #define KVM_REG_MIPS_R5 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 5) | |
91 | #define KVM_REG_MIPS_R6 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 6) | |
92 | #define KVM_REG_MIPS_R7 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 7) | |
93 | #define KVM_REG_MIPS_R8 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 8) | |
94 | #define KVM_REG_MIPS_R9 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 9) | |
95 | #define KVM_REG_MIPS_R10 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 10) | |
96 | #define KVM_REG_MIPS_R11 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 11) | |
97 | #define KVM_REG_MIPS_R12 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 12) | |
98 | #define KVM_REG_MIPS_R13 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 13) | |
99 | #define KVM_REG_MIPS_R14 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 14) | |
100 | #define KVM_REG_MIPS_R15 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 15) | |
101 | #define KVM_REG_MIPS_R16 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 16) | |
102 | #define KVM_REG_MIPS_R17 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 17) | |
103 | #define KVM_REG_MIPS_R18 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 18) | |
104 | #define KVM_REG_MIPS_R19 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 19) | |
105 | #define KVM_REG_MIPS_R20 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 20) | |
106 | #define KVM_REG_MIPS_R21 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 21) | |
107 | #define KVM_REG_MIPS_R22 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 22) | |
108 | #define KVM_REG_MIPS_R23 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 23) | |
109 | #define KVM_REG_MIPS_R24 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 24) | |
110 | #define KVM_REG_MIPS_R25 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 25) | |
111 | #define KVM_REG_MIPS_R26 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 26) | |
112 | #define KVM_REG_MIPS_R27 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 27) | |
113 | #define KVM_REG_MIPS_R28 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 28) | |
114 | #define KVM_REG_MIPS_R29 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 29) | |
115 | #define KVM_REG_MIPS_R30 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 30) | |
116 | #define KVM_REG_MIPS_R31 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 31) | |
117 | ||
118 | #define KVM_REG_MIPS_HI (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 32) | |
119 | #define KVM_REG_MIPS_LO (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 33) | |
120 | #define KVM_REG_MIPS_PC (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 34) | |
121 | ||
122 | ||
85e99cf8 MT |
123 | /* |
124 | * KVM_REG_MIPS_CP0 - Coprocessor 0 registers. | |
125 | */ | |
126 | ||
127 | #define KVM_REG_MIPS_MAAR (KVM_REG_MIPS_CP0 | (1 << 8)) | |
128 | #define KVM_REG_MIPS_CP0_MAAR(n) (KVM_REG_MIPS_MAAR | \ | |
129 | KVM_REG_SIZE_U64 | (n)) | |
130 | ||
131 | ||
7a52ce8a CH |
132 | /* |
133 | * KVM_REG_MIPS_KVM - KVM specific control registers. | |
134 | */ | |
b061808d AG |
135 | |
136 | /* | |
137 | * CP0_Count control | |
138 | * DC: Set 0: Master disable CP0_Count and set COUNT_RESUME to now | |
139 | * Set 1: Master re-enable CP0_Count with unchanged bias, handling timer | |
140 | * interrupts since COUNT_RESUME | |
141 | * This can be used to freeze the timer to get a consistent snapshot of | |
142 | * the CP0_Count and timer interrupt pending state, while also resuming | |
143 | * safely without losing time or guest timer interrupts. | |
144 | * Other: Reserved, do not change. | |
145 | */ | |
7a52ce8a | 146 | #define KVM_REG_MIPS_COUNT_CTL (KVM_REG_MIPS_KVM | KVM_REG_SIZE_U64 | 0) |
b061808d AG |
147 | #define KVM_REG_MIPS_COUNT_CTL_DC 0x00000001 |
148 | ||
149 | /* | |
150 | * CP0_Count resume monotonic nanoseconds | |
151 | * The monotonic nanosecond time of the last set of COUNT_CTL.DC (master | |
152 | * disable). Any reads and writes of Count related registers while | |
153 | * COUNT_CTL.DC=1 will appear to occur at this time. When COUNT_CTL.DC is | |
154 | * cleared again (master enable) any timer interrupts since this time will be | |
155 | * emulated. | |
156 | * Modifications to times in the future are rejected. | |
157 | */ | |
7a52ce8a | 158 | #define KVM_REG_MIPS_COUNT_RESUME (KVM_REG_MIPS_KVM | KVM_REG_SIZE_U64 | 1) |
b061808d AG |
159 | /* |
160 | * CP0_Count rate in Hz | |
161 | * Specifies the rate of the CP0_Count timer in Hz. Modifications occur without | |
162 | * discontinuities in CP0_Count. | |
163 | */ | |
7a52ce8a CH |
164 | #define KVM_REG_MIPS_COUNT_HZ (KVM_REG_MIPS_KVM | KVM_REG_SIZE_U64 | 2) |
165 | ||
166 | ||
167 | /* | |
168 | * KVM_REG_MIPS_FPU - Floating Point and MIPS SIMD Architecture (MSA) registers. | |
169 | * | |
170 | * bits[15..8] - Register subset (see definitions below). | |
171 | * bits[7..5] - Must be zero. | |
172 | * bits[4..0] - Register number within register subset. | |
173 | */ | |
174 | ||
175 | #define KVM_REG_MIPS_FPR (KVM_REG_MIPS_FPU | 0x0000000000000000ULL) | |
176 | #define KVM_REG_MIPS_FCR (KVM_REG_MIPS_FPU | 0x0000000000000100ULL) | |
177 | #define KVM_REG_MIPS_MSACR (KVM_REG_MIPS_FPU | 0x0000000000000200ULL) | |
178 | ||
179 | /* | |
180 | * KVM_REG_MIPS_FPR - Floating point / Vector registers. | |
181 | */ | |
182 | #define KVM_REG_MIPS_FPR_32(n) (KVM_REG_MIPS_FPR | KVM_REG_SIZE_U32 | (n)) | |
183 | #define KVM_REG_MIPS_FPR_64(n) (KVM_REG_MIPS_FPR | KVM_REG_SIZE_U64 | (n)) | |
184 | #define KVM_REG_MIPS_VEC_128(n) (KVM_REG_MIPS_FPR | KVM_REG_SIZE_U128 | (n)) | |
185 | ||
186 | /* | |
187 | * KVM_REG_MIPS_FCR - Floating point control registers. | |
188 | */ | |
189 | #define KVM_REG_MIPS_FCR_IR (KVM_REG_MIPS_FCR | KVM_REG_SIZE_U32 | 0) | |
190 | #define KVM_REG_MIPS_FCR_CSR (KVM_REG_MIPS_FCR | KVM_REG_SIZE_U32 | 31) | |
191 | ||
192 | /* | |
193 | * KVM_REG_MIPS_MSACR - MIPS SIMD Architecture (MSA) control registers. | |
194 | */ | |
195 | #define KVM_REG_MIPS_MSA_IR (KVM_REG_MIPS_MSACR | KVM_REG_SIZE_U32 | 0) | |
196 | #define KVM_REG_MIPS_MSA_CSR (KVM_REG_MIPS_MSACR | KVM_REG_SIZE_U32 | 1) | |
197 | ||
b061808d | 198 | |
e098b453 AK |
199 | /* |
200 | * KVM MIPS specific structures and definitions | |
201 | * | |
202 | */ | |
203 | struct kvm_debug_exit_arch { | |
204 | __u64 epc; | |
205 | }; | |
206 | ||
207 | /* for KVM_SET_GUEST_DEBUG */ | |
208 | struct kvm_guest_debug_arch { | |
209 | }; | |
210 | ||
211 | /* definition of registers in kvm_run */ | |
212 | struct kvm_sync_regs { | |
213 | }; | |
214 | ||
215 | /* dummy definition */ | |
216 | struct kvm_sregs { | |
217 | }; | |
218 | ||
219 | struct kvm_mips_interrupt { | |
220 | /* in */ | |
221 | __u32 cpu; | |
222 | __u32 irq; | |
223 | }; | |
224 | ||
225 | #endif /* __LINUX_KVM_MIPS_H */ |