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cd71c089 LV |
1 | /* |
2 | * qemu user cpu loop | |
3 | * | |
4 | * Copyright (c) 2003-2008 Fabrice Bellard | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
21 | #include "qemu.h" | |
3b249d26 | 22 | #include "user-internals.h" |
cd71c089 | 23 | #include "cpu_loop-common.h" |
2113aed6 | 24 | #include "signal-common.h" |
58908ef6 | 25 | #include "elf.h" |
502700d0 | 26 | #include "internal.h" |
81ddae7c | 27 | #include "fpu_helper.h" |
58908ef6 LV |
28 | |
29 | # ifdef TARGET_ABI_MIPSO32 | |
8d6d4c1b | 30 | # define MIPS_SYSCALL_NUMBER_UNUSED -1 |
8d6d4c1b | 31 | static const int8_t mips_syscall_args[] = { |
ac5d3c67 | 32 | #include "syscall-args-o32.c.inc" |
58908ef6 | 33 | }; |
58908ef6 LV |
34 | # endif /* O32 */ |
35 | ||
58908ef6 LV |
36 | /* Break codes */ |
37 | enum { | |
38 | BRK_OVERFLOW = 6, | |
39 | BRK_DIVZERO = 7 | |
40 | }; | |
41 | ||
bf19bdb8 | 42 | static void do_tr_or_bp(CPUMIPSState *env, unsigned int code, bool trap) |
58908ef6 | 43 | { |
bf19bdb8 | 44 | target_ulong pc = env->active_tc.PC; |
58908ef6 LV |
45 | |
46 | switch (code) { | |
47 | case BRK_OVERFLOW: | |
bf19bdb8 RH |
48 | force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTOVF, pc); |
49 | break; | |
58908ef6 | 50 | case BRK_DIVZERO: |
bf19bdb8 | 51 | force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, pc); |
58908ef6 LV |
52 | break; |
53 | default: | |
bf19bdb8 RH |
54 | if (trap) { |
55 | force_sig(TARGET_SIGTRAP); | |
56 | } else { | |
57 | force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, pc); | |
58 | } | |
58908ef6 LV |
59 | break; |
60 | } | |
58908ef6 LV |
61 | } |
62 | ||
63 | void cpu_loop(CPUMIPSState *env) | |
64 | { | |
5a7330b3 | 65 | CPUState *cs = env_cpu(env); |
73c0aa6a | 66 | int trapnr, si_code; |
6f3533dd | 67 | unsigned int code; |
58908ef6 LV |
68 | abi_long ret; |
69 | # ifdef TARGET_ABI_MIPSO32 | |
70 | unsigned int syscall_num; | |
71 | # endif | |
72 | ||
73 | for(;;) { | |
74 | cpu_exec_start(cs); | |
75 | trapnr = cpu_exec(cs); | |
76 | cpu_exec_end(cs); | |
77 | process_queued_cpu_work(cs); | |
78 | ||
79 | switch(trapnr) { | |
80 | case EXCP_SYSCALL: | |
81 | env->active_tc.PC += 4; | |
82 | # ifdef TARGET_ABI_MIPSO32 | |
83 | syscall_num = env->active_tc.gpr[2] - 4000; | |
84 | if (syscall_num >= sizeof(mips_syscall_args)) { | |
8d6d4c1b AM |
85 | /* syscall_num is larger that any defined for MIPS O32 */ |
86 | ret = -TARGET_ENOSYS; | |
87 | } else if (mips_syscall_args[syscall_num] == | |
88 | MIPS_SYSCALL_NUMBER_UNUSED) { | |
89 | /* syscall_num belongs to the range not defined for MIPS O32 */ | |
58908ef6 LV |
90 | ret = -TARGET_ENOSYS; |
91 | } else { | |
8d6d4c1b | 92 | /* syscall_num is valid */ |
58908ef6 LV |
93 | int nb_args; |
94 | abi_ulong sp_reg; | |
95 | abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0; | |
96 | ||
97 | nb_args = mips_syscall_args[syscall_num]; | |
98 | sp_reg = env->active_tc.gpr[29]; | |
99 | switch (nb_args) { | |
100 | /* these arguments are taken from the stack */ | |
101 | case 8: | |
102 | if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) { | |
103 | goto done_syscall; | |
104 | } | |
81966c18 | 105 | /* fall through */ |
58908ef6 LV |
106 | case 7: |
107 | if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) { | |
108 | goto done_syscall; | |
109 | } | |
81966c18 | 110 | /* fall through */ |
58908ef6 LV |
111 | case 6: |
112 | if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) { | |
113 | goto done_syscall; | |
114 | } | |
81966c18 | 115 | /* fall through */ |
58908ef6 LV |
116 | case 5: |
117 | if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) { | |
118 | goto done_syscall; | |
119 | } | |
81966c18 | 120 | /* fall through */ |
58908ef6 LV |
121 | default: |
122 | break; | |
123 | } | |
124 | ret = do_syscall(env, env->active_tc.gpr[2], | |
125 | env->active_tc.gpr[4], | |
126 | env->active_tc.gpr[5], | |
127 | env->active_tc.gpr[6], | |
128 | env->active_tc.gpr[7], | |
129 | arg5, arg6, arg7, arg8); | |
130 | } | |
131 | done_syscall: | |
132 | # else | |
133 | ret = do_syscall(env, env->active_tc.gpr[2], | |
134 | env->active_tc.gpr[4], env->active_tc.gpr[5], | |
135 | env->active_tc.gpr[6], env->active_tc.gpr[7], | |
136 | env->active_tc.gpr[8], env->active_tc.gpr[9], | |
137 | env->active_tc.gpr[10], env->active_tc.gpr[11]); | |
138 | # endif /* O32 */ | |
af254a27 | 139 | if (ret == -QEMU_ERESTARTSYS) { |
58908ef6 LV |
140 | env->active_tc.PC -= 4; |
141 | break; | |
142 | } | |
57a0c938 | 143 | if (ret == -QEMU_ESIGRETURN) { |
58908ef6 LV |
144 | /* Returning from a successful sigreturn syscall. |
145 | Avoid clobbering register state. */ | |
146 | break; | |
147 | } | |
148 | if ((abi_ulong)ret >= (abi_ulong)-1133) { | |
149 | env->active_tc.gpr[7] = 1; /* error flag */ | |
150 | ret = -ret; | |
151 | } else { | |
152 | env->active_tc.gpr[7] = 0; /* error flag */ | |
153 | } | |
154 | env->active_tc.gpr[2] = ret; | |
155 | break; | |
58908ef6 LV |
156 | case EXCP_CpU: |
157 | case EXCP_RI: | |
73c0aa6a RH |
158 | case EXCP_DSPDIS: |
159 | force_sig(TARGET_SIGILL); | |
58908ef6 LV |
160 | break; |
161 | case EXCP_INTERRUPT: | |
162 | /* just indicate that signals should be handled asap */ | |
163 | break; | |
164 | case EXCP_DEBUG: | |
73c0aa6a RH |
165 | force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, |
166 | env->active_tc.PC); | |
58908ef6 | 167 | break; |
64ce541c | 168 | case EXCP_FPE: |
73c0aa6a | 169 | si_code = TARGET_FPE_FLTUNK; |
64ce541c | 170 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) { |
73c0aa6a | 171 | si_code = TARGET_FPE_FLTINV; |
64ce541c | 172 | } else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_DIV0) { |
73c0aa6a | 173 | si_code = TARGET_FPE_FLTDIV; |
64ce541c | 174 | } else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_OVERFLOW) { |
73c0aa6a | 175 | si_code = TARGET_FPE_FLTOVF; |
64ce541c | 176 | } else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_UNDERFLOW) { |
73c0aa6a | 177 | si_code = TARGET_FPE_FLTUND; |
64ce541c | 178 | } else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INEXACT) { |
73c0aa6a | 179 | si_code = TARGET_FPE_FLTRES; |
64ce541c | 180 | } |
73c0aa6a | 181 | force_sig_fault(TARGET_SIGFPE, si_code, env->active_tc.PC); |
64ce541c | 182 | break; |
73c0aa6a | 183 | |
58908ef6 LV |
184 | /* The code below was inspired by the MIPS Linux kernel trap |
185 | * handling code in arch/mips/kernel/traps.c. | |
186 | */ | |
187 | case EXCP_BREAK: | |
6f3533dd RH |
188 | /* |
189 | * As described in the original Linux kernel code, the below | |
190 | * checks on 'code' are to work around an old assembly bug. | |
191 | */ | |
192 | code = env->error_code; | |
193 | if (code >= (1 << 10)) { | |
194 | code >>= 10; | |
58908ef6 | 195 | } |
6f3533dd | 196 | do_tr_or_bp(env, code, false); |
58908ef6 LV |
197 | break; |
198 | case EXCP_TRAP: | |
0a3336f6 | 199 | do_tr_or_bp(env, env->error_code, true); |
58908ef6 LV |
200 | break; |
201 | case EXCP_ATOMIC: | |
202 | cpu_exec_step_atomic(cs); | |
203 | break; | |
204 | default: | |
58908ef6 LV |
205 | EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); |
206 | abort(); | |
207 | } | |
208 | process_pending_signals(env); | |
209 | } | |
210 | } | |
cd71c089 LV |
211 | |
212 | void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) | |
213 | { | |
29a0af61 | 214 | CPUState *cpu = env_cpu(env); |
58908ef6 LV |
215 | TaskState *ts = cpu->opaque; |
216 | struct image_info *info = ts->info; | |
217 | int i; | |
218 | ||
0c1bbedc SM |
219 | struct mode_req { |
220 | bool single; | |
221 | bool soft; | |
222 | bool fr1; | |
223 | bool frdefault; | |
224 | bool fre; | |
225 | }; | |
226 | ||
227 | static const struct mode_req fpu_reqs[] = { | |
228 | [MIPS_ABI_FP_ANY] = { true, true, true, true, true }, | |
229 | [MIPS_ABI_FP_DOUBLE] = { false, false, false, true, true }, | |
230 | [MIPS_ABI_FP_SINGLE] = { true, false, false, false, false }, | |
231 | [MIPS_ABI_FP_SOFT] = { false, true, false, false, false }, | |
232 | [MIPS_ABI_FP_OLD_64] = { false, false, false, false, false }, | |
233 | [MIPS_ABI_FP_XX] = { false, false, true, true, true }, | |
234 | [MIPS_ABI_FP_64] = { false, false, true, false, false }, | |
235 | [MIPS_ABI_FP_64A] = { false, false, true, false, true } | |
236 | }; | |
237 | ||
238 | /* | |
239 | * Mode requirements when .MIPS.abiflags is not present in the ELF. | |
240 | * Not present means that everything is acceptable except FR1. | |
241 | */ | |
242 | static struct mode_req none_req = { true, true, false, true, true }; | |
243 | ||
244 | struct mode_req prog_req; | |
245 | struct mode_req interp_req; | |
246 | ||
58908ef6 LV |
247 | for(i = 0; i < 32; i++) { |
248 | env->active_tc.gpr[i] = regs->regs[i]; | |
249 | } | |
250 | env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1; | |
251 | if (regs->cp0_epc & 1) { | |
252 | env->hflags |= MIPS_HFLAG_M16; | |
253 | } | |
0c1bbedc SM |
254 | |
255 | #ifdef TARGET_ABI_MIPSO32 | |
256 | # define MAX_FP_ABI MIPS_ABI_FP_64A | |
257 | #else | |
258 | # define MAX_FP_ABI MIPS_ABI_FP_SOFT | |
259 | #endif | |
260 | if ((info->fp_abi > MAX_FP_ABI && info->fp_abi != MIPS_ABI_FP_UNKNOWN) | |
261 | || (info->interp_fp_abi > MAX_FP_ABI && | |
262 | info->interp_fp_abi != MIPS_ABI_FP_UNKNOWN)) { | |
263 | fprintf(stderr, "qemu: Unexpected FPU mode\n"); | |
264 | exit(1); | |
265 | } | |
266 | ||
267 | prog_req = (info->fp_abi == MIPS_ABI_FP_UNKNOWN) ? none_req | |
268 | : fpu_reqs[info->fp_abi]; | |
269 | interp_req = (info->interp_fp_abi == MIPS_ABI_FP_UNKNOWN) ? none_req | |
270 | : fpu_reqs[info->interp_fp_abi]; | |
271 | ||
272 | prog_req.single &= interp_req.single; | |
273 | prog_req.soft &= interp_req.soft; | |
274 | prog_req.fr1 &= interp_req.fr1; | |
275 | prog_req.frdefault &= interp_req.frdefault; | |
276 | prog_req.fre &= interp_req.fre; | |
277 | ||
7a47bae5 | 278 | bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS_R2 || |
2e211e0a | 279 | env->insn_flags & ISA_MIPS_R6; |
0c1bbedc SM |
280 | |
281 | if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) { | |
282 | env->CP0_Config5 |= (1 << CP0C5_FRE); | |
283 | if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { | |
284 | env->hflags |= MIPS_HFLAG_FRE; | |
285 | } | |
286 | } else if ((prog_req.fr1 && prog_req.frdefault) || | |
287 | (prog_req.single && !prog_req.frdefault)) { | |
288 | if ((env->active_fpu.fcr0 & (1 << FCR0_F64) | |
289 | && cpu_has_mips_r2_r6) || prog_req.fr1) { | |
290 | env->CP0_Status |= (1 << CP0St_FR); | |
291 | env->hflags |= MIPS_HFLAG_F64; | |
292 | } | |
293 | } else if (!prog_req.fre && !prog_req.frdefault && | |
294 | !prog_req.fr1 && !prog_req.single && !prog_req.soft) { | |
295 | fprintf(stderr, "qemu: Can't find a matching FPU mode\n"); | |
296 | exit(1); | |
297 | } | |
298 | ||
722ac96c AM |
299 | if (env->insn_flags & ISA_NANOMIPS32) { |
300 | return; | |
301 | } | |
58908ef6 LV |
302 | if (((info->elf_flags & EF_MIPS_NAN2008) != 0) != |
303 | ((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0)) { | |
304 | if ((env->active_fpu.fcr31_rw_bitmask & | |
305 | (1 << FCR31_NAN2008)) == 0) { | |
306 | fprintf(stderr, "ELF binary's NaN mode not supported by CPU\n"); | |
307 | exit(1); | |
308 | } | |
309 | if ((info->elf_flags & EF_MIPS_NAN2008) != 0) { | |
310 | env->active_fpu.fcr31 |= (1 << FCR31_NAN2008); | |
311 | } else { | |
312 | env->active_fpu.fcr31 &= ~(1 << FCR31_NAN2008); | |
313 | } | |
314 | restore_snan_bit_mode(env); | |
315 | } | |
cd71c089 | 316 | } |