[qemu.git] / softmmu_header.h

/*
 *  Software MMU support
 * 
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#if DATA_SIZE == 8
#define SUFFIX q
#define USUFFIX q
#define DATA_TYPE uint64_t
#elif DATA_SIZE == 4
#define SUFFIX l
#define USUFFIX l
#define DATA_TYPE uint32_t
#elif DATA_SIZE == 2
#define SUFFIX w
#define USUFFIX uw
#define DATA_TYPE uint16_t
#define DATA_STYPE int16_t
#elif DATA_SIZE == 1
#define SUFFIX b
#define USUFFIX ub
#define DATA_TYPE uint8_t
#define DATA_STYPE int8_t
#else
#error unsupported data size
#endif

#if ACCESS_TYPE == 0

#define CPU_MEM_INDEX 0
#define MMUSUFFIX _mmu

#elif ACCESS_TYPE == 1

#define CPU_MEM_INDEX 1
#define MMUSUFFIX _mmu

#elif ACCESS_TYPE == 2

#ifdef TARGET_I386
#define CPU_MEM_INDEX ((env->hflags & HF_CPL_MASK) == 3)
#elif defined (TARGET_PPC)
#define CPU_MEM_INDEX (msr_pr)
#elif defined (TARGET_MIPS)
#define CPU_MEM_INDEX ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM)
#elif defined (TARGET_SPARC)
#define CPU_MEM_INDEX ((env->psrs) == 0)
#elif defined (TARGET_ARM)
#define CPU_MEM_INDEX ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)
#elif defined (TARGET_SH4)
#define CPU_MEM_INDEX ((env->sr & SR_MD) == 0)
#else
#error unsupported CPU
#endif
#define MMUSUFFIX _mmu

#elif ACCESS_TYPE == 3

#ifdef TARGET_I386
#define CPU_MEM_INDEX ((env->hflags & HF_CPL_MASK) == 3)
#elif defined (TARGET_PPC)
#define CPU_MEM_INDEX (msr_pr)
#elif defined (TARGET_MIPS)
#define CPU_MEM_INDEX ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM)
#elif defined (TARGET_SPARC)
#define CPU_MEM_INDEX ((env->psrs) == 0)
#elif defined (TARGET_ARM)
#define CPU_MEM_INDEX ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)
#elif defined (TARGET_SH4)
#define CPU_MEM_INDEX ((env->sr & SR_MD) == 0)
#else
#error unsupported CPU
#endif
#define MMUSUFFIX _cmmu

#else
#error invalid ACCESS_TYPE
#endif

#if DATA_SIZE == 8
#define RES_TYPE uint64_t
#else
#define RES_TYPE int
#endif

#if ACCESS_TYPE == 3
#define ADDR_READ addr_code
#else
#define ADDR_READ addr_read
#endif

DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                         int is_user);
void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr, DATA_TYPE v, int is_user);

#if (DATA_SIZE <= 4) && (TARGET_LONG_BITS == 32) && defined(__i386__) && \
    (ACCESS_TYPE <= 1) && defined(ASM_SOFTMMU)

#define CPU_TLB_ENTRY_BITS 4

static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
{
    int res;

    asm volatile ("movl %1, %%edx\n"
                  "movl %1, %%eax\n"
                  "shrl %3, %%edx\n"
                  "andl %4, %%eax\n"
                  "andl %2, %%edx\n"
                  "leal %5(%%edx, %%ebp), %%edx\n"
                  "cmpl (%%edx), %%eax\n"
                  "movl %1, %%eax\n"
                  "je 1f\n"
                  "pushl %6\n"
                  "call %7\n"
                  "popl %%edx\n"
                  "movl %%eax, %0\n"
                  "jmp 2f\n"
                  "1:\n"
                  "addl 12(%%edx), %%eax\n"
#if DATA_SIZE == 1
                  "movzbl (%%eax), %0\n"
#elif DATA_SIZE == 2
                  "movzwl (%%eax), %0\n"
#elif DATA_SIZE == 4
                  "movl (%%eax), %0\n"
#else
#error unsupported size
#endif
                  "2:\n"
                  : "=r" (res)
                  : "r" (ptr), 
                  "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS), 
                  "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS), 
                  "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
                  "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MEM_INDEX][0].addr_read)),
                  "i" (CPU_MEM_INDEX),
                  "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
                  : "%eax", "%ecx", "%edx", "memory", "cc");
    return res;
}

#if DATA_SIZE <= 2
static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
{
    int res;

    asm volatile ("movl %1, %%edx\n"
                  "movl %1, %%eax\n"
                  "shrl %3, %%edx\n"
                  "andl %4, %%eax\n"
                  "andl %2, %%edx\n"
                  "leal %5(%%edx, %%ebp), %%edx\n"
                  "cmpl (%%edx), %%eax\n"
                  "movl %1, %%eax\n"
                  "je 1f\n"
                  "pushl %6\n"
                  "call %7\n"
                  "popl %%edx\n"
#if DATA_SIZE == 1
                  "movsbl %%al, %0\n"
#elif DATA_SIZE == 2
                  "movswl %%ax, %0\n"
#else
#error unsupported size
#endif
                  "jmp 2f\n"
                  "1:\n"
                  "addl 12(%%edx), %%eax\n"
#if DATA_SIZE == 1
                  "movsbl (%%eax), %0\n"
#elif DATA_SIZE == 2
                  "movswl (%%eax), %0\n"
#else
#error unsupported size
#endif
                  "2:\n"
                  : "=r" (res)
                  : "r" (ptr), 
                  "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS), 
                  "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS), 
                  "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
                  "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MEM_INDEX][0].addr_read)),
                  "i" (CPU_MEM_INDEX),
                  "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
                  : "%eax", "%ecx", "%edx", "memory", "cc");
    return res;
}
#endif

static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
{
    asm volatile ("movl %0, %%edx\n"
                  "movl %0, %%eax\n"
                  "shrl %3, %%edx\n"
                  "andl %4, %%eax\n"
                  "andl %2, %%edx\n"
                  "leal %5(%%edx, %%ebp), %%edx\n"
                  "cmpl (%%edx), %%eax\n"
                  "movl %0, %%eax\n"
                  "je 1f\n"
#if DATA_SIZE == 1
                  "movzbl %b1, %%edx\n"
#elif DATA_SIZE == 2
                  "movzwl %w1, %%edx\n"
#elif DATA_SIZE == 4
                  "movl %1, %%edx\n"
#else
#error unsupported size
#endif
                  "pushl %6\n"
                  "call %7\n"
                  "popl %%eax\n"
                  "jmp 2f\n"
                  "1:\n"
                  "addl 8(%%edx), %%eax\n"
#if DATA_SIZE == 1
                  "movb %b1, (%%eax)\n"
#elif DATA_SIZE == 2
                  "movw %w1, (%%eax)\n"
#elif DATA_SIZE == 4
                  "movl %1, (%%eax)\n"
#else
#error unsupported size
#endif
                  "2:\n"
                  : 
                  : "r" (ptr), 
/* NOTE: 'q' would be needed as constraint, but we could not use it
   with T1 ! */
                  "r" (v), 
                  "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS), 
                  "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS), 
                  "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
                  "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MEM_INDEX][0].addr_write)),
                  "i" (CPU_MEM_INDEX),
                  "m" (*(uint8_t *)&glue(glue(__st, SUFFIX), MMUSUFFIX))
                  : "%eax", "%ecx", "%edx", "memory", "cc");
}

#else

/* generic load/store macros */

static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
{
    int index;
    RES_TYPE res;
    target_ulong addr;
    unsigned long physaddr;
    int is_user;

    addr = ptr;
    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
    is_user = CPU_MEM_INDEX;
    if (__builtin_expect(env->tlb_table[is_user][index].ADDR_READ != 
                         (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
        res = glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, is_user);
    } else {
        physaddr = addr + env->tlb_table[is_user][index].addend;
        res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)physaddr);
    }
    return res;
}

#if DATA_SIZE <= 2
static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
{
    int res, index;
    target_ulong addr;
    unsigned long physaddr;
    int is_user;

    addr = ptr;
    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
    is_user = CPU_MEM_INDEX;
    if (__builtin_expect(env->tlb_table[is_user][index].ADDR_READ != 
                         (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
        res = (DATA_STYPE)glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, is_user);
    } else {
        physaddr = addr + env->tlb_table[is_user][index].addend;
        res = glue(glue(lds, SUFFIX), _raw)((uint8_t *)physaddr);
    }
    return res;
}
#endif

#if ACCESS_TYPE != 3

/* generic store macro */

static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
{
    int index;
    target_ulong addr;
    unsigned long physaddr;
    int is_user;

    addr = ptr;
    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
    is_user = CPU_MEM_INDEX;
    if (__builtin_expect(env->tlb_table[is_user][index].addr_write != 
                         (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
        glue(glue(__st, SUFFIX), MMUSUFFIX)(addr, v, is_user);
    } else {
        physaddr = addr + env->tlb_table[is_user][index].addend;
        glue(glue(st, SUFFIX), _raw)((uint8_t *)physaddr, v);
    }
}

#endif /* ACCESS_TYPE != 3 */

#endif /* !asm */

#if ACCESS_TYPE != 3

#if DATA_SIZE == 8
static inline float64 glue(ldfq, MEMSUFFIX)(target_ulong ptr)
{
    union {
        float64 d;
        uint64_t i;
    } u;
    u.i = glue(ldq, MEMSUFFIX)(ptr);
    return u.d;
}

static inline void glue(stfq, MEMSUFFIX)(target_ulong ptr, float64 v)
{
    union {
        float64 d;
        uint64_t i;
    } u;
    u.d = v;
    glue(stq, MEMSUFFIX)(ptr, u.i);
}
#endif /* DATA_SIZE == 8 */

#if DATA_SIZE == 4
static inline float32 glue(ldfl, MEMSUFFIX)(target_ulong ptr)
{
    union {
        float32 f;
        uint32_t i;
    } u;
    u.i = glue(ldl, MEMSUFFIX)(ptr);
    return u.f;
}

static inline void glue(stfl, MEMSUFFIX)(target_ulong ptr, float32 v)
{
    union {
        float32 f;
        uint32_t i;
    } u;
    u.f = v;
    glue(stl, MEMSUFFIX)(ptr, u.i);
}
#endif /* DATA_SIZE == 4 */

#endif /* ACCESS_TYPE != 3 */

#undef RES_TYPE
#undef DATA_TYPE
#undef DATA_STYPE
#undef SUFFIX
#undef USUFFIX
#undef DATA_SIZE
#undef CPU_MEM_INDEX
#undef MMUSUFFIX
#undef ADDR_READ
Commit	Line	Data
b92e5a22 FB	1	/*
	2	* Software MMU support
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20	#if DATA_SIZE == 8
	21	#define SUFFIX q
61382a50	22	#define USUFFIX q
b92e5a22 FB	23	#define DATA_TYPE uint64_t
	24	#elif DATA_SIZE == 4
	25	#define SUFFIX l
61382a50	26	#define USUFFIX l
b92e5a22 FB	27	#define DATA_TYPE uint32_t
	28	#elif DATA_SIZE == 2
	29	#define SUFFIX w
61382a50	30	#define USUFFIX uw
b92e5a22 FB	31	#define DATA_TYPE uint16_t
	32	#define DATA_STYPE int16_t
	33	#elif DATA_SIZE == 1
	34	#define SUFFIX b
61382a50	35	#define USUFFIX ub
b92e5a22 FB	36	#define DATA_TYPE uint8_t
	37	#define DATA_STYPE int8_t
	38	#else
	39	#error unsupported data size
	40	#endif
	41
61382a50 FB	42	#if ACCESS_TYPE == 0
	43
	44	#define CPU_MEM_INDEX 0
	45	#define MMUSUFFIX _mmu
	46
	47	#elif ACCESS_TYPE == 1
	48
	49	#define CPU_MEM_INDEX 1
	50	#define MMUSUFFIX _mmu
	51
	52	#elif ACCESS_TYPE == 2
	53
2d603d22	54	#ifdef TARGET_I386
61382a50	55	#define CPU_MEM_INDEX ((env->hflags & HF_CPL_MASK) == 3)
2d603d22 FB	56	#elif defined (TARGET_PPC)
2d603d22 FB	57	#define CPU_MEM_INDEX (msr_pr)
6af0bf9c FB	58	#elif defined (TARGET_MIPS)
6af0bf9c FB	59	#define CPU_MEM_INDEX ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM)
e95c8d51 FB	60	#elif defined (TARGET_SPARC)
e95c8d51 FB	61	#define CPU_MEM_INDEX ((env->psrs) == 0)
b5ff1b31 FB	62	#elif defined (TARGET_ARM)
b5ff1b31 FB	63	#define CPU_MEM_INDEX ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)
fdf9b3e8 FB	64	#elif defined (TARGET_SH4)
fdf9b3e8 FB	65	#define CPU_MEM_INDEX ((env->sr & SR_MD) == 0)
b5ff1b31 FB	66	#else
b5ff1b31 FB	67	#error unsupported CPU
2d603d22	68	#endif
61382a50 FB	69	#define MMUSUFFIX _mmu
	70
	71	#elif ACCESS_TYPE == 3
	72
2d603d22	73	#ifdef TARGET_I386
61382a50	74	#define CPU_MEM_INDEX ((env->hflags & HF_CPL_MASK) == 3)
2d603d22 FB	75	#elif defined (TARGET_PPC)
2d603d22 FB	76	#define CPU_MEM_INDEX (msr_pr)
6af0bf9c FB	77	#elif defined (TARGET_MIPS)
6af0bf9c FB	78	#define CPU_MEM_INDEX ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM)
e95c8d51 FB	79	#elif defined (TARGET_SPARC)
e95c8d51 FB	80	#define CPU_MEM_INDEX ((env->psrs) == 0)
b5ff1b31 FB	81	#elif defined (TARGET_ARM)
b5ff1b31 FB	82	#define CPU_MEM_INDEX ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)
fdf9b3e8 FB	83	#elif defined (TARGET_SH4)
fdf9b3e8 FB	84	#define CPU_MEM_INDEX ((env->sr & SR_MD) == 0)
b5ff1b31 FB	85	#else
b5ff1b31 FB	86	#error unsupported CPU
2d603d22	87	#endif
61382a50 FB	88	#define MMUSUFFIX _cmmu
61382a50 FB	89
b92e5a22	90	#else
61382a50	91	#error invalid ACCESS_TYPE
b92e5a22 FB	92	#endif
	93
	94	#if DATA_SIZE == 8
	95	#define RES_TYPE uint64_t
	96	#else
	97	#define RES_TYPE int
	98	#endif
	99
84b7b8e7 FB	100	#if ACCESS_TYPE == 3
	101	#define ADDR_READ addr_code
	102	#else
	103	#define ADDR_READ addr_read
	104	#endif
b92e5a22	105
c27004ec	106	DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
61382a50	107	int is_user);
c27004ec	108	void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr, DATA_TYPE v, int is_user);
b92e5a22	109
c27004ec FB	110	#if (DATA_SIZE <= 4) && (TARGET_LONG_BITS == 32) && defined(__i386__) && \
c27004ec FB	111	(ACCESS_TYPE <= 1) && defined(ASM_SOFTMMU)
e16c53fa	112
84b7b8e7 FB	113	#define CPU_TLB_ENTRY_BITS 4
84b7b8e7 FB	114
c27004ec	115	static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
e16c53fa FB	116	{
	117	int res;
	118
	119	asm volatile ("movl %1, %%edx\n"
	120	"movl %1, %%eax\n"
	121	"shrl %3, %%edx\n"
	122	"andl %4, %%eax\n"
	123	"andl %2, %%edx\n"
	124	"leal %5(%%edx, %%ebp), %%edx\n"
	125	"cmpl (%%edx), %%eax\n"
	126	"movl %1, %%eax\n"
	127	"je 1f\n"
	128	"pushl %6\n"
	129	"call %7\n"
	130	"popl %%edx\n"
	131	"movl %%eax, %0\n"
	132	"jmp 2f\n"
	133	"1:\n"
84b7b8e7	134	"addl 12(%%edx), %%eax\n"
e16c53fa FB	135	#if DATA_SIZE == 1
	136	"movzbl (%%eax), %0\n"
	137	#elif DATA_SIZE == 2
	138	"movzwl (%%eax), %0\n"
	139	#elif DATA_SIZE == 4
	140	"movl (%%eax), %0\n"
	141	#else
	142	#error unsupported size
	143	#endif
	144	"2:\n"
	145	: "=r" (res)
	146	: "r" (ptr),
84b7b8e7 FB	147	"i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
84b7b8e7 FB	148	"i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
e16c53fa	149	"i" (TARGET_PAGE_MASK \| (DATA_SIZE - 1)),
84b7b8e7	150	"m" ((uint32_t )offsetof(CPUState, tlb_table[CPU_MEM_INDEX][0].addr_read)),
e16c53fa FB	151	"i" (CPU_MEM_INDEX),
	152	"m" ((uint8_t )&glue(glue(__ld, SUFFIX), MMUSUFFIX))
	153	: "%eax", "%ecx", "%edx", "memory", "cc");
	154	return res;
	155	}
	156
	157	#if DATA_SIZE <= 2
c27004ec	158	static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
e16c53fa FB	159	{
	160	int res;
	161
	162	asm volatile ("movl %1, %%edx\n"
	163	"movl %1, %%eax\n"
	164	"shrl %3, %%edx\n"
	165	"andl %4, %%eax\n"
	166	"andl %2, %%edx\n"
	167	"leal %5(%%edx, %%ebp), %%edx\n"
	168	"cmpl (%%edx), %%eax\n"
	169	"movl %1, %%eax\n"
	170	"je 1f\n"
	171	"pushl %6\n"
	172	"call %7\n"
	173	"popl %%edx\n"
	174	#if DATA_SIZE == 1
	175	"movsbl %%al, %0\n"
	176	#elif DATA_SIZE == 2
	177	"movswl %%ax, %0\n"
	178	#else
	179	#error unsupported size
	180	#endif
	181	"jmp 2f\n"
	182	"1:\n"
84b7b8e7	183	"addl 12(%%edx), %%eax\n"
e16c53fa FB	184	#if DATA_SIZE == 1
	185	"movsbl (%%eax), %0\n"
	186	#elif DATA_SIZE == 2
	187	"movswl (%%eax), %0\n"
	188	#else
	189	#error unsupported size
	190	#endif
	191	"2:\n"
	192	: "=r" (res)
	193	: "r" (ptr),
84b7b8e7 FB	194	"i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
84b7b8e7 FB	195	"i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
e16c53fa	196	"i" (TARGET_PAGE_MASK \| (DATA_SIZE - 1)),
84b7b8e7	197	"m" ((uint32_t )offsetof(CPUState, tlb_table[CPU_MEM_INDEX][0].addr_read)),
e16c53fa FB	198	"i" (CPU_MEM_INDEX),
	199	"m" ((uint8_t )&glue(glue(__ld, SUFFIX), MMUSUFFIX))
	200	: "%eax", "%ecx", "%edx", "memory", "cc");
	201	return res;
	202	}
	203	#endif
	204
c27004ec	205	static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
e16c53fa FB	206	{
	207	asm volatile ("movl %0, %%edx\n"
	208	"movl %0, %%eax\n"
	209	"shrl %3, %%edx\n"
	210	"andl %4, %%eax\n"
	211	"andl %2, %%edx\n"
	212	"leal %5(%%edx, %%ebp), %%edx\n"
	213	"cmpl (%%edx), %%eax\n"
	214	"movl %0, %%eax\n"
	215	"je 1f\n"
	216	#if DATA_SIZE == 1
	217	"movzbl %b1, %%edx\n"
	218	#elif DATA_SIZE == 2
	219	"movzwl %w1, %%edx\n"
	220	#elif DATA_SIZE == 4
	221	"movl %1, %%edx\n"
	222	#else
	223	#error unsupported size
	224	#endif
	225	"pushl %6\n"
	226	"call %7\n"
	227	"popl %%eax\n"
	228	"jmp 2f\n"
	229	"1:\n"
84b7b8e7	230	"addl 8(%%edx), %%eax\n"
e16c53fa FB	231	#if DATA_SIZE == 1
	232	"movb %b1, (%%eax)\n"
	233	#elif DATA_SIZE == 2
	234	"movw %w1, (%%eax)\n"
	235	#elif DATA_SIZE == 4
	236	"movl %1, (%%eax)\n"
	237	#else
	238	#error unsupported size
	239	#endif
	240	"2:\n"
	241	:
	242	: "r" (ptr),
	243	/* NOTE: 'q' would be needed as constraint, but we could not use it
	244	with T1 ! */
	245	"r" (v),
84b7b8e7 FB	246	"i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
84b7b8e7 FB	247	"i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
e16c53fa	248	"i" (TARGET_PAGE_MASK \| (DATA_SIZE - 1)),
84b7b8e7	249	"m" ((uint32_t )offsetof(CPUState, tlb_table[CPU_MEM_INDEX][0].addr_write)),
e16c53fa FB	250	"i" (CPU_MEM_INDEX),
	251	"m" ((uint8_t )&glue(glue(__st, SUFFIX), MMUSUFFIX))
	252	: "%eax", "%ecx", "%edx", "memory", "cc");
	253	}
	254
	255	#else
	256
	257	/* generic load/store macros */
	258
c27004ec	259	static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
b92e5a22 FB	260	{
	261	int index;
	262	RES_TYPE res;
c27004ec FB	263	target_ulong addr;
c27004ec FB	264	unsigned long physaddr;
61382a50 FB	265	int is_user;
61382a50 FB	266
c27004ec	267	addr = ptr;
b92e5a22	268	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
61382a50	269	is_user = CPU_MEM_INDEX;
84b7b8e7	270	if (__builtin_expect(env->tlb_table[is_user][index].ADDR_READ !=
b92e5a22	271	(addr & (TARGET_PAGE_MASK \| (DATA_SIZE - 1))), 0)) {
61382a50	272	res = glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, is_user);
b92e5a22	273	} else {
84b7b8e7	274	physaddr = addr + env->tlb_table[is_user][index].addend;
61382a50	275	res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)physaddr);
b92e5a22 FB	276	}
	277	return res;
	278	}
	279
	280	#if DATA_SIZE <= 2
c27004ec	281	static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
b92e5a22 FB	282	{
b92e5a22 FB	283	int res, index;
c27004ec FB	284	target_ulong addr;
c27004ec FB	285	unsigned long physaddr;
61382a50 FB	286	int is_user;
61382a50 FB	287
c27004ec	288	addr = ptr;
b92e5a22	289	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
61382a50	290	is_user = CPU_MEM_INDEX;
84b7b8e7	291	if (__builtin_expect(env->tlb_table[is_user][index].ADDR_READ !=
b92e5a22	292	(addr & (TARGET_PAGE_MASK \| (DATA_SIZE - 1))), 0)) {
61382a50	293	res = (DATA_STYPE)glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, is_user);
b92e5a22	294	} else {
84b7b8e7	295	physaddr = addr + env->tlb_table[is_user][index].addend;
b92e5a22 FB	296	res = glue(glue(lds, SUFFIX), _raw)((uint8_t *)physaddr);
	297	}
	298	return res;
	299	}
	300	#endif
	301
84b7b8e7 FB	302	#if ACCESS_TYPE != 3
84b7b8e7 FB	303
e16c53fa FB	304	/* generic store macro */
e16c53fa FB	305
c27004ec	306	static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
b92e5a22 FB	307	{
b92e5a22 FB	308	int index;
c27004ec FB	309	target_ulong addr;
c27004ec FB	310	unsigned long physaddr;
61382a50 FB	311	int is_user;
61382a50 FB	312
c27004ec	313	addr = ptr;
b92e5a22	314	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
61382a50	315	is_user = CPU_MEM_INDEX;
84b7b8e7	316	if (__builtin_expect(env->tlb_table[is_user][index].addr_write !=
b92e5a22	317	(addr & (TARGET_PAGE_MASK \| (DATA_SIZE - 1))), 0)) {
61382a50	318	glue(glue(__st, SUFFIX), MMUSUFFIX)(addr, v, is_user);
b92e5a22	319	} else {
84b7b8e7	320	physaddr = addr + env->tlb_table[is_user][index].addend;
b92e5a22 FB	321	glue(glue(st, SUFFIX), _raw)((uint8_t *)physaddr, v);
	322	}
	323	}
	324
84b7b8e7 FB	325	#endif /* ACCESS_TYPE != 3 */
	326
	327	#endif /* !asm */
	328
	329	#if ACCESS_TYPE != 3
e16c53fa	330
2d603d22	331	#if DATA_SIZE == 8
3f87bf69	332	static inline float64 glue(ldfq, MEMSUFFIX)(target_ulong ptr)
2d603d22 FB	333	{
2d603d22 FB	334	union {
3f87bf69	335	float64 d;
2d603d22 FB	336	uint64_t i;
	337	} u;
	338	u.i = glue(ldq, MEMSUFFIX)(ptr);
	339	return u.d;
	340	}
	341
3f87bf69	342	static inline void glue(stfq, MEMSUFFIX)(target_ulong ptr, float64 v)
2d603d22 FB	343	{
2d603d22 FB	344	union {
3f87bf69	345	float64 d;
2d603d22 FB	346	uint64_t i;
	347	} u;
	348	u.d = v;
	349	glue(stq, MEMSUFFIX)(ptr, u.i);
	350	}
	351	#endif /* DATA_SIZE == 8 */
	352
	353	#if DATA_SIZE == 4
3f87bf69	354	static inline float32 glue(ldfl, MEMSUFFIX)(target_ulong ptr)
2d603d22 FB	355	{
2d603d22 FB	356	union {
3f87bf69	357	float32 f;
2d603d22 FB	358	uint32_t i;
	359	} u;
	360	u.i = glue(ldl, MEMSUFFIX)(ptr);
	361	return u.f;
	362	}
	363
3f87bf69	364	static inline void glue(stfl, MEMSUFFIX)(target_ulong ptr, float32 v)
2d603d22 FB	365	{
2d603d22 FB	366	union {
3f87bf69	367	float32 f;
2d603d22 FB	368	uint32_t i;
	369	} u;
	370	u.f = v;
	371	glue(stl, MEMSUFFIX)(ptr, u.i);
	372	}
	373	#endif /* DATA_SIZE == 4 */
	374
84b7b8e7 FB	375	#endif /* ACCESS_TYPE != 3 */
84b7b8e7 FB	376
b92e5a22 FB	377	#undef RES_TYPE
	378	#undef DATA_TYPE
	379	#undef DATA_STYPE
	380	#undef SUFFIX
61382a50	381	#undef USUFFIX
b92e5a22	382	#undef DATA_SIZE
61382a50 FB	383	#undef CPU_MEM_INDEX
61382a50 FB	384	#undef MMUSUFFIX
84b7b8e7	385	#undef ADDR_READ