]>
Commit | Line | Data |
---|---|---|
d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
cb5a6ffc RK |
2 | /* |
3 | * linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver | |
4 | * | |
5 | * Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved. | |
6 | * | |
cb5a6ffc RK |
7 | * Documentation: ARM DDI 0173B |
8 | */ | |
9 | #include <linux/module.h> | |
10 | #include <linux/delay.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/ioport.h> | |
13 | #include <linux/device.h> | |
14 | #include <linux/spinlock.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/err.h> | |
a62c80e5 | 17 | #include <linux/amba/bus.h> |
88cdca9c | 18 | #include <linux/io.h> |
cb5a6ffc | 19 | |
cb5a6ffc RK |
20 | #include <sound/core.h> |
21 | #include <sound/initval.h> | |
22 | #include <sound/ac97_codec.h> | |
23 | #include <sound/pcm.h> | |
24 | #include <sound/pcm_params.h> | |
25 | ||
26 | #include "aaci.h" | |
cb5a6ffc RK |
27 | |
28 | #define DRIVER_NAME "aaci-pl041" | |
29 | ||
250c7a61 RK |
30 | #define FRAME_PERIOD_US 21 |
31 | ||
cb5a6ffc RK |
32 | /* |
33 | * PM support is not complete. Turn it off. | |
34 | */ | |
35 | #undef CONFIG_PM | |
36 | ||
ceb9e476 | 37 | static void aaci_ac97_select_codec(struct aaci *aaci, struct snd_ac97 *ac97) |
cb5a6ffc RK |
38 | { |
39 | u32 v, maincr = aaci->maincr | MAINCR_SCRA(ac97->num); | |
40 | ||
41 | /* | |
42 | * Ensure that the slot 1/2 RX registers are empty. | |
43 | */ | |
44 | v = readl(aaci->base + AACI_SLFR); | |
45 | if (v & SLFR_2RXV) | |
46 | readl(aaci->base + AACI_SL2RX); | |
47 | if (v & SLFR_1RXV) | |
48 | readl(aaci->base + AACI_SL1RX); | |
49 | ||
7c289385 RK |
50 | if (maincr != readl(aaci->base + AACI_MAINCR)) { |
51 | writel(maincr, aaci->base + AACI_MAINCR); | |
52 | readl(aaci->base + AACI_MAINCR); | |
53 | udelay(1); | |
54 | } | |
cb5a6ffc RK |
55 | } |
56 | ||
57 | /* | |
58 | * P29: | |
59 | * The recommended use of programming the external codec through slot 1 | |
60 | * and slot 2 data is to use the channels during setup routines and the | |
61 | * slot register at any other time. The data written into slot 1, slot 2 | |
62 | * and slot 12 registers is transmitted only when their corresponding | |
63 | * SI1TxEn, SI2TxEn and SI12TxEn bits are set in the AACI_MAINCR | |
64 | * register. | |
65 | */ | |
14d178a1 KH |
66 | static void aaci_ac97_write(struct snd_ac97 *ac97, unsigned short reg, |
67 | unsigned short val) | |
cb5a6ffc RK |
68 | { |
69 | struct aaci *aaci = ac97->private_data; | |
250c7a61 | 70 | int timeout; |
cb5a6ffc RK |
71 | u32 v; |
72 | ||
73 | if (ac97->num >= 4) | |
74 | return; | |
75 | ||
12aa7579 | 76 | mutex_lock(&aaci->ac97_sem); |
cb5a6ffc RK |
77 | |
78 | aaci_ac97_select_codec(aaci, ac97); | |
79 | ||
80 | /* | |
81 | * P54: You must ensure that AACI_SL2TX is always written | |
82 | * to, if required, before data is written to AACI_SL1TX. | |
83 | */ | |
84 | writel(val << 4, aaci->base + AACI_SL2TX); | |
85 | writel(reg << 12, aaci->base + AACI_SL1TX); | |
86 | ||
250c7a61 RK |
87 | /* Initially, wait one frame period */ |
88 | udelay(FRAME_PERIOD_US); | |
89 | ||
90 | /* And then wait an additional eight frame periods for it to be sent */ | |
91 | timeout = FRAME_PERIOD_US * 8; | |
cb5a6ffc | 92 | do { |
250c7a61 | 93 | udelay(1); |
cb5a6ffc | 94 | v = readl(aaci->base + AACI_SLFR); |
f6f35bbe | 95 | } while ((v & (SLFR_1TXB|SLFR_2TXB)) && --timeout); |
14d178a1 | 96 | |
69058cd6 | 97 | if (v & (SLFR_1TXB|SLFR_2TXB)) |
14d178a1 KH |
98 | dev_err(&aaci->dev->dev, |
99 | "timeout waiting for write to complete\n"); | |
cb5a6ffc | 100 | |
12aa7579 | 101 | mutex_unlock(&aaci->ac97_sem); |
cb5a6ffc RK |
102 | } |
103 | ||
104 | /* | |
105 | * Read an AC'97 register. | |
106 | */ | |
ceb9e476 | 107 | static unsigned short aaci_ac97_read(struct snd_ac97 *ac97, unsigned short reg) |
cb5a6ffc RK |
108 | { |
109 | struct aaci *aaci = ac97->private_data; | |
250c7a61 | 110 | int timeout, retries = 10; |
cb5a6ffc RK |
111 | u32 v; |
112 | ||
113 | if (ac97->num >= 4) | |
114 | return ~0; | |
115 | ||
12aa7579 | 116 | mutex_lock(&aaci->ac97_sem); |
cb5a6ffc RK |
117 | |
118 | aaci_ac97_select_codec(aaci, ac97); | |
119 | ||
120 | /* | |
121 | * Write the register address to slot 1. | |
122 | */ | |
123 | writel((reg << 12) | (1 << 19), aaci->base + AACI_SL1TX); | |
124 | ||
250c7a61 RK |
125 | /* Initially, wait one frame period */ |
126 | udelay(FRAME_PERIOD_US); | |
127 | ||
128 | /* And then wait an additional eight frame periods for it to be sent */ | |
129 | timeout = FRAME_PERIOD_US * 8; | |
cb5a6ffc | 130 | do { |
250c7a61 | 131 | udelay(1); |
cb5a6ffc | 132 | v = readl(aaci->base + AACI_SLFR); |
f6f35bbe | 133 | } while ((v & SLFR_1TXB) && --timeout); |
14d178a1 | 134 | |
69058cd6 | 135 | if (v & SLFR_1TXB) { |
14d178a1 KH |
136 | dev_err(&aaci->dev->dev, "timeout on slot 1 TX busy\n"); |
137 | v = ~0; | |
138 | goto out; | |
139 | } | |
cb5a6ffc | 140 | |
250c7a61 RK |
141 | /* Now wait for the response frame */ |
142 | udelay(FRAME_PERIOD_US); | |
cb5a6ffc | 143 | |
250c7a61 RK |
144 | /* And then wait an additional eight frame periods for data */ |
145 | timeout = FRAME_PERIOD_US * 8; | |
cb5a6ffc | 146 | do { |
250c7a61 | 147 | udelay(1); |
cb5a6ffc RK |
148 | cond_resched(); |
149 | v = readl(aaci->base + AACI_SLFR) & (SLFR_1RXV|SLFR_2RXV); | |
f6f35bbe | 150 | } while ((v != (SLFR_1RXV|SLFR_2RXV)) && --timeout); |
cb5a6ffc | 151 | |
69058cd6 | 152 | if (v != (SLFR_1RXV|SLFR_2RXV)) { |
14d178a1 | 153 | dev_err(&aaci->dev->dev, "timeout on RX valid\n"); |
cb5a6ffc | 154 | v = ~0; |
14d178a1 | 155 | goto out; |
cb5a6ffc RK |
156 | } |
157 | ||
14d178a1 KH |
158 | do { |
159 | v = readl(aaci->base + AACI_SL1RX) >> 12; | |
160 | if (v == reg) { | |
161 | v = readl(aaci->base + AACI_SL2RX) >> 4; | |
162 | break; | |
163 | } else if (--retries) { | |
164 | dev_warn(&aaci->dev->dev, | |
165 | "ac97 read back fail. retry\n"); | |
166 | continue; | |
167 | } else { | |
168 | dev_warn(&aaci->dev->dev, | |
169 | "wrong ac97 register read back (%x != %x)\n", | |
170 | v, reg); | |
171 | v = ~0; | |
172 | } | |
173 | } while (retries); | |
174 | out: | |
12aa7579 | 175 | mutex_unlock(&aaci->ac97_sem); |
cb5a6ffc RK |
176 | return v; |
177 | } | |
178 | ||
d6a89fef RK |
179 | static inline void |
180 | aaci_chan_wait_ready(struct aaci_runtime *aacirun, unsigned long mask) | |
cb5a6ffc RK |
181 | { |
182 | u32 val; | |
183 | int timeout = 5000; | |
184 | ||
185 | do { | |
250c7a61 | 186 | udelay(1); |
cb5a6ffc | 187 | val = readl(aacirun->base + AACI_SR); |
d6a89fef | 188 | } while (val & mask && timeout--); |
cb5a6ffc RK |
189 | } |
190 | ||
191 | ||
192 | ||
193 | /* | |
194 | * Interrupt support. | |
195 | */ | |
62578cbf | 196 | static void aaci_fifo_irq(struct aaci *aaci, int channel, u32 mask) |
cb5a6ffc | 197 | { |
41762b8c KH |
198 | if (mask & ISR_ORINTR) { |
199 | dev_warn(&aaci->dev->dev, "RX overrun on chan %d\n", channel); | |
200 | writel(ICLR_RXOEC1 << channel, aaci->base + AACI_INTCLR); | |
201 | } | |
202 | ||
203 | if (mask & ISR_RXTOINTR) { | |
204 | dev_warn(&aaci->dev->dev, "RX timeout on chan %d\n", channel); | |
205 | writel(ICLR_RXTOFEC1 << channel, aaci->base + AACI_INTCLR); | |
206 | } | |
207 | ||
208 | if (mask & ISR_RXINTR) { | |
209 | struct aaci_runtime *aacirun = &aaci->capture; | |
ea51d0b1 | 210 | bool period_elapsed = false; |
41762b8c KH |
211 | void *ptr; |
212 | ||
213 | if (!aacirun->substream || !aacirun->start) { | |
898eb71c | 214 | dev_warn(&aaci->dev->dev, "RX interrupt???\n"); |
41762b8c KH |
215 | writel(0, aacirun->base + AACI_IE); |
216 | return; | |
217 | } | |
41762b8c | 218 | |
d6a89fef RK |
219 | spin_lock(&aacirun->lock); |
220 | ||
221 | ptr = aacirun->ptr; | |
41762b8c | 222 | do { |
5d350cba | 223 | unsigned int len = aacirun->fifo_bytes; |
41762b8c KH |
224 | u32 val; |
225 | ||
226 | if (aacirun->bytes <= 0) { | |
227 | aacirun->bytes += aacirun->period; | |
ea51d0b1 | 228 | period_elapsed = true; |
41762b8c KH |
229 | } |
230 | if (!(aacirun->cr & CR_EN)) | |
231 | break; | |
232 | ||
233 | val = readl(aacirun->base + AACI_SR); | |
234 | if (!(val & SR_RXHF)) | |
235 | break; | |
236 | if (!(val & SR_RXFF)) | |
237 | len >>= 1; | |
238 | ||
239 | aacirun->bytes -= len; | |
240 | ||
241 | /* reading 16 bytes at a time */ | |
242 | for( ; len > 0; len -= 16) { | |
243 | asm( | |
244 | "ldmia %1, {r0, r1, r2, r3}\n\t" | |
245 | "stmia %0!, {r0, r1, r2, r3}" | |
246 | : "+r" (ptr) | |
247 | : "r" (aacirun->fifo) | |
248 | : "r0", "r1", "r2", "r3", "cc"); | |
249 | ||
250 | if (ptr >= aacirun->end) | |
251 | ptr = aacirun->start; | |
252 | } | |
253 | } while(1); | |
d6a89fef | 254 | |
41762b8c | 255 | aacirun->ptr = ptr; |
d6a89fef RK |
256 | |
257 | spin_unlock(&aacirun->lock); | |
ea51d0b1 RK |
258 | |
259 | if (period_elapsed) | |
260 | snd_pcm_period_elapsed(aacirun->substream); | |
41762b8c KH |
261 | } |
262 | ||
cb5a6ffc | 263 | if (mask & ISR_URINTR) { |
62578cbf KH |
264 | dev_dbg(&aaci->dev->dev, "TX underrun on chan %d\n", channel); |
265 | writel(ICLR_TXUEC1 << channel, aaci->base + AACI_INTCLR); | |
cb5a6ffc RK |
266 | } |
267 | ||
268 | if (mask & ISR_TXINTR) { | |
269 | struct aaci_runtime *aacirun = &aaci->playback; | |
ea51d0b1 | 270 | bool period_elapsed = false; |
cb5a6ffc RK |
271 | void *ptr; |
272 | ||
273 | if (!aacirun->substream || !aacirun->start) { | |
898eb71c | 274 | dev_warn(&aaci->dev->dev, "TX interrupt???\n"); |
cb5a6ffc RK |
275 | writel(0, aacirun->base + AACI_IE); |
276 | return; | |
277 | } | |
278 | ||
d6a89fef RK |
279 | spin_lock(&aacirun->lock); |
280 | ||
cb5a6ffc RK |
281 | ptr = aacirun->ptr; |
282 | do { | |
5d350cba | 283 | unsigned int len = aacirun->fifo_bytes; |
cb5a6ffc RK |
284 | u32 val; |
285 | ||
286 | if (aacirun->bytes <= 0) { | |
287 | aacirun->bytes += aacirun->period; | |
ea51d0b1 | 288 | period_elapsed = true; |
cb5a6ffc | 289 | } |
41762b8c | 290 | if (!(aacirun->cr & CR_EN)) |
cb5a6ffc RK |
291 | break; |
292 | ||
293 | val = readl(aacirun->base + AACI_SR); | |
294 | if (!(val & SR_TXHE)) | |
295 | break; | |
296 | if (!(val & SR_TXFE)) | |
297 | len >>= 1; | |
298 | ||
299 | aacirun->bytes -= len; | |
300 | ||
301 | /* writing 16 bytes at a time */ | |
302 | for ( ; len > 0; len -= 16) { | |
303 | asm( | |
304 | "ldmia %0!, {r0, r1, r2, r3}\n\t" | |
305 | "stmia %1, {r0, r1, r2, r3}" | |
306 | : "+r" (ptr) | |
307 | : "r" (aacirun->fifo) | |
308 | : "r0", "r1", "r2", "r3", "cc"); | |
309 | ||
310 | if (ptr >= aacirun->end) | |
311 | ptr = aacirun->start; | |
312 | } | |
313 | } while (1); | |
314 | ||
315 | aacirun->ptr = ptr; | |
d6a89fef RK |
316 | |
317 | spin_unlock(&aacirun->lock); | |
ea51d0b1 RK |
318 | |
319 | if (period_elapsed) | |
320 | snd_pcm_period_elapsed(aacirun->substream); | |
cb5a6ffc RK |
321 | } |
322 | } | |
323 | ||
7d12e780 | 324 | static irqreturn_t aaci_irq(int irq, void *devid) |
cb5a6ffc RK |
325 | { |
326 | struct aaci *aaci = devid; | |
327 | u32 mask; | |
328 | int i; | |
329 | ||
cb5a6ffc RK |
330 | mask = readl(aaci->base + AACI_ALLINTS); |
331 | if (mask) { | |
332 | u32 m = mask; | |
333 | for (i = 0; i < 4; i++, m >>= 7) { | |
334 | if (m & 0x7f) { | |
62578cbf | 335 | aaci_fifo_irq(aaci, i, m); |
cb5a6ffc RK |
336 | } |
337 | } | |
338 | } | |
cb5a6ffc RK |
339 | |
340 | return mask ? IRQ_HANDLED : IRQ_NONE; | |
341 | } | |
342 | ||
343 | ||
344 | ||
345 | /* | |
346 | * ALSA support. | |
347 | */ | |
db566fb9 | 348 | static const struct snd_pcm_hardware aaci_hw_info = { |
cb5a6ffc RK |
349 | .info = SNDRV_PCM_INFO_MMAP | |
350 | SNDRV_PCM_INFO_MMAP_VALID | | |
351 | SNDRV_PCM_INFO_INTERLEAVED | | |
352 | SNDRV_PCM_INFO_BLOCK_TRANSFER | | |
353 | SNDRV_PCM_INFO_RESUME, | |
354 | ||
355 | /* | |
356 | * ALSA doesn't support 18-bit or 20-bit packed into 32-bit | |
357 | * words. It also doesn't support 12-bit at all. | |
358 | */ | |
359 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
360 | ||
6ca867c8 | 361 | /* rates are setup from the AC'97 codec */ |
cb5a6ffc | 362 | .channels_min = 2, |
e831d80b | 363 | .channels_max = 2, |
cb5a6ffc RK |
364 | .buffer_bytes_max = 64 * 1024, |
365 | .period_bytes_min = 256, | |
366 | .period_bytes_max = PAGE_SIZE, | |
367 | .periods_min = 4, | |
368 | .periods_max = PAGE_SIZE / 16, | |
369 | }; | |
370 | ||
e831d80b RK |
371 | /* |
372 | * We can support two and four channel audio. Unfortunately | |
373 | * six channel audio requires a non-standard channel ordering: | |
374 | * 2 -> FL(3), FR(4) | |
375 | * 4 -> FL(3), FR(4), SL(7), SR(8) | |
376 | * 6 -> FL(3), FR(4), SL(7), SR(8), C(6), LFE(9) (required) | |
377 | * FL(3), FR(4), C(6), SL(7), SR(8), LFE(9) (actual) | |
378 | * This requires an ALSA configuration file to correct. | |
379 | */ | |
380 | static int aaci_rule_channels(struct snd_pcm_hw_params *p, | |
381 | struct snd_pcm_hw_rule *rule) | |
382 | { | |
383 | static unsigned int channel_list[] = { 2, 4, 6 }; | |
384 | struct aaci *aaci = rule->private; | |
385 | unsigned int mask = 1 << 0, slots; | |
386 | ||
387 | /* pcms[0] is the our 5.1 PCM instance. */ | |
388 | slots = aaci->ac97_bus->pcms[0].r[0].slots; | |
389 | if (slots & (1 << AC97_SLOT_PCM_SLEFT)) { | |
390 | mask |= 1 << 1; | |
391 | if (slots & (1 << AC97_SLOT_LFE)) | |
392 | mask |= 1 << 2; | |
393 | } | |
394 | ||
395 | return snd_interval_list(hw_param_interval(p, rule->var), | |
396 | ARRAY_SIZE(channel_list), channel_list, mask); | |
397 | } | |
398 | ||
399 | static int aaci_pcm_open(struct snd_pcm_substream *substream) | |
cb5a6ffc | 400 | { |
ceb9e476 | 401 | struct snd_pcm_runtime *runtime = substream->runtime; |
e831d80b RK |
402 | struct aaci *aaci = substream->private_data; |
403 | struct aaci_runtime *aacirun; | |
b60fb519 | 404 | int ret = 0; |
cb5a6ffc | 405 | |
e831d80b RK |
406 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
407 | aacirun = &aaci->playback; | |
408 | } else { | |
409 | aacirun = &aaci->capture; | |
410 | } | |
411 | ||
cb5a6ffc RK |
412 | aacirun->substream = substream; |
413 | runtime->private_data = aacirun; | |
414 | runtime->hw = aaci_hw_info; | |
6ca867c8 RK |
415 | runtime->hw.rates = aacirun->pcm->rates; |
416 | snd_pcm_limit_hw_rates(runtime); | |
cb5a6ffc | 417 | |
e831d80b RK |
418 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
419 | runtime->hw.channels_max = 6; | |
420 | ||
421 | /* Add rule describing channel dependency. */ | |
422 | ret = snd_pcm_hw_rule_add(substream->runtime, 0, | |
423 | SNDRV_PCM_HW_PARAM_CHANNELS, | |
424 | aaci_rule_channels, aaci, | |
425 | SNDRV_PCM_HW_PARAM_CHANNELS, -1); | |
426 | if (ret) | |
427 | return ret; | |
428 | ||
429 | if (aacirun->pcm->r[1].slots) | |
430 | snd_ac97_pcm_double_rate_rules(runtime); | |
431 | } | |
a08d5658 | 432 | |
cb5a6ffc | 433 | /* |
5d350cba RK |
434 | * ALSA wants the byte-size of the FIFOs. As we only support |
435 | * 16-bit samples, this is twice the FIFO depth irrespective | |
436 | * of whether it's in compact mode or not. | |
cb5a6ffc | 437 | */ |
5d350cba | 438 | runtime->hw.fifo_size = aaci->fifo_depth * 2; |
cb5a6ffc | 439 | |
b60fb519 RK |
440 | mutex_lock(&aaci->irq_lock); |
441 | if (!aaci->users++) { | |
442 | ret = request_irq(aaci->dev->irq[0], aaci_irq, | |
88e24c3a | 443 | IRQF_SHARED, DRIVER_NAME, aaci); |
b60fb519 RK |
444 | if (ret != 0) |
445 | aaci->users--; | |
446 | } | |
447 | mutex_unlock(&aaci->irq_lock); | |
cb5a6ffc | 448 | |
cb5a6ffc RK |
449 | return ret; |
450 | } | |
451 | ||
452 | ||
453 | /* | |
454 | * Common ALSA stuff | |
455 | */ | |
ceb9e476 | 456 | static int aaci_pcm_close(struct snd_pcm_substream *substream) |
cb5a6ffc RK |
457 | { |
458 | struct aaci *aaci = substream->private_data; | |
459 | struct aaci_runtime *aacirun = substream->runtime->private_data; | |
460 | ||
41762b8c | 461 | WARN_ON(aacirun->cr & CR_EN); |
cb5a6ffc RK |
462 | |
463 | aacirun->substream = NULL; | |
b60fb519 RK |
464 | |
465 | mutex_lock(&aaci->irq_lock); | |
466 | if (!--aaci->users) | |
467 | free_irq(aaci->dev->irq[0], aaci); | |
468 | mutex_unlock(&aaci->irq_lock); | |
cb5a6ffc RK |
469 | |
470 | return 0; | |
471 | } | |
472 | ||
ceb9e476 | 473 | static int aaci_pcm_hw_free(struct snd_pcm_substream *substream) |
cb5a6ffc RK |
474 | { |
475 | struct aaci_runtime *aacirun = substream->runtime->private_data; | |
476 | ||
477 | /* | |
478 | * This must not be called with the device enabled. | |
479 | */ | |
41762b8c | 480 | WARN_ON(aacirun->cr & CR_EN); |
cb5a6ffc RK |
481 | |
482 | if (aacirun->pcm_open) | |
483 | snd_ac97_pcm_close(aacirun->pcm); | |
484 | aacirun->pcm_open = 0; | |
485 | ||
486 | /* | |
487 | * Clear out the DMA and any allocated buffers. | |
488 | */ | |
d6797322 | 489 | snd_pcm_lib_free_pages(substream); |
cb5a6ffc RK |
490 | |
491 | return 0; | |
492 | } | |
493 | ||
58e8a474 RK |
494 | /* Channel to slot mask */ |
495 | static const u32 channels_to_slotmask[] = { | |
496 | [2] = CR_SL3 | CR_SL4, | |
497 | [4] = CR_SL3 | CR_SL4 | CR_SL7 | CR_SL8, | |
498 | [6] = CR_SL3 | CR_SL4 | CR_SL7 | CR_SL8 | CR_SL6 | CR_SL9, | |
499 | }; | |
500 | ||
ceb9e476 | 501 | static int aaci_pcm_hw_params(struct snd_pcm_substream *substream, |
ceb9e476 | 502 | struct snd_pcm_hw_params *params) |
cb5a6ffc | 503 | { |
58e8a474 RK |
504 | struct aaci_runtime *aacirun = substream->runtime->private_data; |
505 | unsigned int channels = params_channels(params); | |
506 | unsigned int rate = params_rate(params); | |
507 | int dbl = rate > 48000; | |
cb5a6ffc RK |
508 | int err; |
509 | ||
510 | aaci_pcm_hw_free(substream); | |
4acd57c3 RK |
511 | if (aacirun->pcm_open) { |
512 | snd_ac97_pcm_close(aacirun->pcm); | |
513 | aacirun->pcm_open = 0; | |
514 | } | |
cb5a6ffc | 515 | |
58e8a474 RK |
516 | /* channels is already limited to 2, 4, or 6 by aaci_rule_channels */ |
517 | if (dbl && channels != 2) | |
518 | return -EINVAL; | |
519 | ||
d6797322 TI |
520 | err = snd_pcm_lib_malloc_pages(substream, |
521 | params_buffer_bytes(params)); | |
4e30b691 | 522 | if (err >= 0) { |
58e8a474 | 523 | struct aaci *aaci = substream->private_data; |
a08d5658 | 524 | |
58e8a474 | 525 | err = snd_ac97_pcm_open(aacirun->pcm, rate, channels, |
a08d5658 | 526 | aacirun->pcm->r[dbl].slots); |
cb5a6ffc | 527 | |
4e30b691 | 528 | aacirun->pcm_open = err == 0; |
d3aee799 | 529 | aacirun->cr = CR_FEN | CR_COMPACT | CR_SZ16; |
58e8a474 | 530 | aacirun->cr |= channels_to_slotmask[channels + dbl * 2]; |
d3aee799 | 531 | |
5d350cba RK |
532 | /* |
533 | * fifo_bytes is the number of bytes we transfer to/from | |
534 | * the FIFO, including padding. So that's x4. As we're | |
535 | * in compact mode, the FIFO is half the size. | |
536 | */ | |
537 | aacirun->fifo_bytes = aaci->fifo_depth * 4 / 2; | |
4e30b691 | 538 | } |
cb5a6ffc | 539 | |
cb5a6ffc RK |
540 | return err; |
541 | } | |
542 | ||
ceb9e476 | 543 | static int aaci_pcm_prepare(struct snd_pcm_substream *substream) |
cb5a6ffc | 544 | { |
ceb9e476 | 545 | struct snd_pcm_runtime *runtime = substream->runtime; |
cb5a6ffc RK |
546 | struct aaci_runtime *aacirun = runtime->private_data; |
547 | ||
c0dea82c | 548 | aacirun->period = snd_pcm_lib_period_bytes(substream); |
4e30b691 | 549 | aacirun->start = runtime->dma_area; |
88cdca9c | 550 | aacirun->end = aacirun->start + snd_pcm_lib_buffer_bytes(substream); |
cb5a6ffc | 551 | aacirun->ptr = aacirun->start; |
c0dea82c | 552 | aacirun->bytes = aacirun->period; |
cb5a6ffc RK |
553 | |
554 | return 0; | |
555 | } | |
556 | ||
ceb9e476 | 557 | static snd_pcm_uframes_t aaci_pcm_pointer(struct snd_pcm_substream *substream) |
cb5a6ffc | 558 | { |
ceb9e476 | 559 | struct snd_pcm_runtime *runtime = substream->runtime; |
cb5a6ffc RK |
560 | struct aaci_runtime *aacirun = runtime->private_data; |
561 | ssize_t bytes = aacirun->ptr - aacirun->start; | |
562 | ||
563 | return bytes_to_frames(runtime, bytes); | |
564 | } | |
565 | ||
cb5a6ffc RK |
566 | |
567 | /* | |
568 | * Playback specific ALSA stuff | |
569 | */ | |
cb5a6ffc RK |
570 | static void aaci_pcm_playback_stop(struct aaci_runtime *aacirun) |
571 | { | |
572 | u32 ie; | |
573 | ||
574 | ie = readl(aacirun->base + AACI_IE); | |
575 | ie &= ~(IE_URIE|IE_TXIE); | |
576 | writel(ie, aacirun->base + AACI_IE); | |
41762b8c | 577 | aacirun->cr &= ~CR_EN; |
d6a89fef | 578 | aaci_chan_wait_ready(aacirun, SR_TXB); |
cb5a6ffc RK |
579 | writel(aacirun->cr, aacirun->base + AACI_TXCR); |
580 | } | |
581 | ||
582 | static void aaci_pcm_playback_start(struct aaci_runtime *aacirun) | |
583 | { | |
584 | u32 ie; | |
585 | ||
d6a89fef | 586 | aaci_chan_wait_ready(aacirun, SR_TXB); |
41762b8c | 587 | aacirun->cr |= CR_EN; |
cb5a6ffc RK |
588 | |
589 | ie = readl(aacirun->base + AACI_IE); | |
590 | ie |= IE_URIE | IE_TXIE; | |
591 | writel(ie, aacirun->base + AACI_IE); | |
592 | writel(aacirun->cr, aacirun->base + AACI_TXCR); | |
593 | } | |
594 | ||
ceb9e476 | 595 | static int aaci_pcm_playback_trigger(struct snd_pcm_substream *substream, int cmd) |
cb5a6ffc | 596 | { |
cb5a6ffc RK |
597 | struct aaci_runtime *aacirun = substream->runtime->private_data; |
598 | unsigned long flags; | |
599 | int ret = 0; | |
600 | ||
d6a89fef RK |
601 | spin_lock_irqsave(&aacirun->lock, flags); |
602 | ||
cb5a6ffc RK |
603 | switch (cmd) { |
604 | case SNDRV_PCM_TRIGGER_START: | |
605 | aaci_pcm_playback_start(aacirun); | |
606 | break; | |
607 | ||
608 | case SNDRV_PCM_TRIGGER_RESUME: | |
609 | aaci_pcm_playback_start(aacirun); | |
610 | break; | |
611 | ||
612 | case SNDRV_PCM_TRIGGER_STOP: | |
613 | aaci_pcm_playback_stop(aacirun); | |
614 | break; | |
615 | ||
616 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
617 | aaci_pcm_playback_stop(aacirun); | |
618 | break; | |
619 | ||
620 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
621 | break; | |
622 | ||
623 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
624 | break; | |
625 | ||
626 | default: | |
627 | ret = -EINVAL; | |
628 | } | |
d6a89fef RK |
629 | |
630 | spin_unlock_irqrestore(&aacirun->lock, flags); | |
cb5a6ffc RK |
631 | |
632 | return ret; | |
633 | } | |
634 | ||
28f05480 | 635 | static const struct snd_pcm_ops aaci_playback_ops = { |
41762b8c | 636 | .open = aaci_pcm_open, |
cb5a6ffc RK |
637 | .close = aaci_pcm_close, |
638 | .ioctl = snd_pcm_lib_ioctl, | |
58e8a474 | 639 | .hw_params = aaci_pcm_hw_params, |
cb5a6ffc RK |
640 | .hw_free = aaci_pcm_hw_free, |
641 | .prepare = aaci_pcm_prepare, | |
642 | .trigger = aaci_pcm_playback_trigger, | |
643 | .pointer = aaci_pcm_pointer, | |
cb5a6ffc RK |
644 | }; |
645 | ||
41762b8c KH |
646 | static void aaci_pcm_capture_stop(struct aaci_runtime *aacirun) |
647 | { | |
648 | u32 ie; | |
649 | ||
d6a89fef | 650 | aaci_chan_wait_ready(aacirun, SR_RXB); |
41762b8c KH |
651 | |
652 | ie = readl(aacirun->base + AACI_IE); | |
653 | ie &= ~(IE_ORIE | IE_RXIE); | |
654 | writel(ie, aacirun->base+AACI_IE); | |
655 | ||
656 | aacirun->cr &= ~CR_EN; | |
cb5a6ffc | 657 | |
41762b8c KH |
658 | writel(aacirun->cr, aacirun->base + AACI_RXCR); |
659 | } | |
660 | ||
661 | static void aaci_pcm_capture_start(struct aaci_runtime *aacirun) | |
662 | { | |
663 | u32 ie; | |
664 | ||
d6a89fef | 665 | aaci_chan_wait_ready(aacirun, SR_RXB); |
41762b8c KH |
666 | |
667 | #ifdef DEBUG | |
668 | /* RX Timeout value: bits 28:17 in RXCR */ | |
669 | aacirun->cr |= 0xf << 17; | |
670 | #endif | |
671 | ||
672 | aacirun->cr |= CR_EN; | |
673 | writel(aacirun->cr, aacirun->base + AACI_RXCR); | |
674 | ||
675 | ie = readl(aacirun->base + AACI_IE); | |
676 | ie |= IE_ORIE |IE_RXIE; // overrun and rx interrupt -- half full | |
677 | writel(ie, aacirun->base + AACI_IE); | |
678 | } | |
679 | ||
8a371840 RK |
680 | static int aaci_pcm_capture_trigger(struct snd_pcm_substream *substream, int cmd) |
681 | { | |
41762b8c KH |
682 | struct aaci_runtime *aacirun = substream->runtime->private_data; |
683 | unsigned long flags; | |
684 | int ret = 0; | |
685 | ||
d6a89fef | 686 | spin_lock_irqsave(&aacirun->lock, flags); |
41762b8c KH |
687 | |
688 | switch (cmd) { | |
689 | case SNDRV_PCM_TRIGGER_START: | |
690 | aaci_pcm_capture_start(aacirun); | |
691 | break; | |
692 | ||
693 | case SNDRV_PCM_TRIGGER_RESUME: | |
694 | aaci_pcm_capture_start(aacirun); | |
695 | break; | |
696 | ||
697 | case SNDRV_PCM_TRIGGER_STOP: | |
698 | aaci_pcm_capture_stop(aacirun); | |
699 | break; | |
700 | ||
701 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
702 | aaci_pcm_capture_stop(aacirun); | |
703 | break; | |
704 | ||
705 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
706 | break; | |
707 | ||
708 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
709 | break; | |
710 | ||
711 | default: | |
712 | ret = -EINVAL; | |
713 | } | |
714 | ||
d6a89fef | 715 | spin_unlock_irqrestore(&aacirun->lock, flags); |
41762b8c KH |
716 | |
717 | return ret; | |
718 | } | |
719 | ||
8a371840 | 720 | static int aaci_pcm_capture_prepare(struct snd_pcm_substream *substream) |
41762b8c KH |
721 | { |
722 | struct snd_pcm_runtime *runtime = substream->runtime; | |
723 | struct aaci *aaci = substream->private_data; | |
724 | ||
725 | aaci_pcm_prepare(substream); | |
726 | ||
727 | /* allow changing of sample rate */ | |
728 | aaci_ac97_write(aaci->ac97, AC97_EXTENDED_STATUS, 0x0001); /* VRA */ | |
729 | aaci_ac97_write(aaci->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate); | |
730 | aaci_ac97_write(aaci->ac97, AC97_PCM_MIC_ADC_RATE, runtime->rate); | |
731 | ||
732 | /* Record select: Mic: 0, Aux: 3, Line: 4 */ | |
733 | aaci_ac97_write(aaci->ac97, AC97_REC_SEL, 0x0404); | |
734 | ||
735 | return 0; | |
736 | } | |
737 | ||
28f05480 | 738 | static const struct snd_pcm_ops aaci_capture_ops = { |
41762b8c KH |
739 | .open = aaci_pcm_open, |
740 | .close = aaci_pcm_close, | |
741 | .ioctl = snd_pcm_lib_ioctl, | |
58e8a474 | 742 | .hw_params = aaci_pcm_hw_params, |
41762b8c KH |
743 | .hw_free = aaci_pcm_hw_free, |
744 | .prepare = aaci_pcm_capture_prepare, | |
745 | .trigger = aaci_pcm_capture_trigger, | |
746 | .pointer = aaci_pcm_pointer, | |
41762b8c | 747 | }; |
cb5a6ffc RK |
748 | |
749 | /* | |
750 | * Power Management. | |
751 | */ | |
752 | #ifdef CONFIG_PM | |
b13a7149 | 753 | static int aaci_do_suspend(struct snd_card *card) |
cb5a6ffc RK |
754 | { |
755 | struct aaci *aaci = card->private_data; | |
792a6c51 | 756 | snd_power_change_state(card, SNDRV_CTL_POWER_D3cold); |
cb5a6ffc RK |
757 | return 0; |
758 | } | |
759 | ||
b13a7149 | 760 | static int aaci_do_resume(struct snd_card *card) |
cb5a6ffc | 761 | { |
792a6c51 | 762 | snd_power_change_state(card, SNDRV_CTL_POWER_D0); |
cb5a6ffc RK |
763 | return 0; |
764 | } | |
765 | ||
b13a7149 | 766 | static int aaci_suspend(struct device *dev) |
cb5a6ffc | 767 | { |
b13a7149 | 768 | struct snd_card *card = dev_get_drvdata(dev); |
cb5a6ffc RK |
769 | return card ? aaci_do_suspend(card) : 0; |
770 | } | |
771 | ||
b13a7149 | 772 | static int aaci_resume(struct device *dev) |
cb5a6ffc | 773 | { |
b13a7149 | 774 | struct snd_card *card = dev_get_drvdata(dev); |
cb5a6ffc RK |
775 | return card ? aaci_do_resume(card) : 0; |
776 | } | |
b13a7149 UH |
777 | |
778 | static SIMPLE_DEV_PM_OPS(aaci_dev_pm_ops, aaci_suspend, aaci_resume); | |
779 | #define AACI_DEV_PM_OPS (&aaci_dev_pm_ops) | |
cb5a6ffc | 780 | #else |
b13a7149 | 781 | #define AACI_DEV_PM_OPS NULL |
cb5a6ffc RK |
782 | #endif |
783 | ||
784 | ||
9b419cd4 | 785 | static const struct ac97_pcm ac97_defs[] = { |
41762b8c | 786 | [0] = { /* Front PCM */ |
cb5a6ffc RK |
787 | .exclusive = 1, |
788 | .r = { | |
789 | [0] = { | |
790 | .slots = (1 << AC97_SLOT_PCM_LEFT) | | |
791 | (1 << AC97_SLOT_PCM_RIGHT) | | |
792 | (1 << AC97_SLOT_PCM_CENTER) | | |
793 | (1 << AC97_SLOT_PCM_SLEFT) | | |
794 | (1 << AC97_SLOT_PCM_SRIGHT) | | |
795 | (1 << AC97_SLOT_LFE), | |
796 | }, | |
a08d5658 RK |
797 | [1] = { |
798 | .slots = (1 << AC97_SLOT_PCM_LEFT) | | |
799 | (1 << AC97_SLOT_PCM_RIGHT) | | |
800 | (1 << AC97_SLOT_PCM_LEFT_0) | | |
801 | (1 << AC97_SLOT_PCM_RIGHT_0), | |
802 | }, | |
cb5a6ffc RK |
803 | }, |
804 | }, | |
805 | [1] = { /* PCM in */ | |
806 | .stream = 1, | |
807 | .exclusive = 1, | |
808 | .r = { | |
809 | [0] = { | |
810 | .slots = (1 << AC97_SLOT_PCM_LEFT) | | |
811 | (1 << AC97_SLOT_PCM_RIGHT), | |
812 | }, | |
813 | }, | |
814 | }, | |
815 | [2] = { /* Mic in */ | |
816 | .stream = 1, | |
817 | .exclusive = 1, | |
818 | .r = { | |
819 | [0] = { | |
820 | .slots = (1 << AC97_SLOT_MIC), | |
821 | }, | |
822 | }, | |
823 | } | |
824 | }; | |
825 | ||
ceb9e476 | 826 | static struct snd_ac97_bus_ops aaci_bus_ops = { |
cb5a6ffc RK |
827 | .write = aaci_ac97_write, |
828 | .read = aaci_ac97_read, | |
829 | }; | |
830 | ||
6c9dc19c | 831 | static int aaci_probe_ac97(struct aaci *aaci) |
cb5a6ffc | 832 | { |
ceb9e476 TI |
833 | struct snd_ac97_template ac97_template; |
834 | struct snd_ac97_bus *ac97_bus; | |
835 | struct snd_ac97 *ac97; | |
cb5a6ffc RK |
836 | int ret; |
837 | ||
838 | /* | |
839 | * Assert AACIRESET for 2us | |
840 | */ | |
841 | writel(0, aaci->base + AACI_RESET); | |
842 | udelay(2); | |
843 | writel(RESET_NRST, aaci->base + AACI_RESET); | |
844 | ||
845 | /* | |
846 | * Give the AC'97 codec more than enough time | |
847 | * to wake up. (42us = ~2 frames at 48kHz.) | |
848 | */ | |
250c7a61 | 849 | udelay(FRAME_PERIOD_US * 2); |
cb5a6ffc RK |
850 | |
851 | ret = snd_ac97_bus(aaci->card, 0, &aaci_bus_ops, aaci, &ac97_bus); | |
852 | if (ret) | |
853 | goto out; | |
854 | ||
855 | ac97_bus->clock = 48000; | |
856 | aaci->ac97_bus = ac97_bus; | |
857 | ||
ceb9e476 | 858 | memset(&ac97_template, 0, sizeof(struct snd_ac97_template)); |
cb5a6ffc RK |
859 | ac97_template.private_data = aaci; |
860 | ac97_template.num = 0; | |
861 | ac97_template.scaps = AC97_SCAP_SKIP_MODEM; | |
862 | ||
863 | ret = snd_ac97_mixer(ac97_bus, &ac97_template, &ac97); | |
864 | if (ret) | |
865 | goto out; | |
41762b8c | 866 | aaci->ac97 = ac97; |
cb5a6ffc RK |
867 | |
868 | /* | |
869 | * Disable AC97 PC Beep input on audio codecs. | |
870 | */ | |
871 | if (ac97_is_audio(ac97)) | |
872 | snd_ac97_write_cache(ac97, AC97_PC_BEEP, 0x801e); | |
873 | ||
874 | ret = snd_ac97_pcm_assign(ac97_bus, ARRAY_SIZE(ac97_defs), ac97_defs); | |
875 | if (ret) | |
876 | goto out; | |
877 | ||
878 | aaci->playback.pcm = &ac97_bus->pcms[0]; | |
41762b8c | 879 | aaci->capture.pcm = &ac97_bus->pcms[1]; |
cb5a6ffc RK |
880 | |
881 | out: | |
882 | return ret; | |
883 | } | |
884 | ||
ceb9e476 | 885 | static void aaci_free_card(struct snd_card *card) |
cb5a6ffc RK |
886 | { |
887 | struct aaci *aaci = card->private_data; | |
ff6defa6 ME |
888 | |
889 | iounmap(aaci->base); | |
cb5a6ffc RK |
890 | } |
891 | ||
6c9dc19c | 892 | static struct aaci *aaci_init_card(struct amba_device *dev) |
cb5a6ffc RK |
893 | { |
894 | struct aaci *aaci; | |
ceb9e476 | 895 | struct snd_card *card; |
bd7dd77c | 896 | int err; |
cb5a6ffc | 897 | |
4a875580 TI |
898 | err = snd_card_new(&dev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1, |
899 | THIS_MODULE, sizeof(struct aaci), &card); | |
bd7dd77c | 900 | if (err < 0) |
631e8ad4 | 901 | return NULL; |
cb5a6ffc RK |
902 | |
903 | card->private_free = aaci_free_card; | |
cb5a6ffc RK |
904 | |
905 | strlcpy(card->driver, DRIVER_NAME, sizeof(card->driver)); | |
906 | strlcpy(card->shortname, "ARM AC'97 Interface", sizeof(card->shortname)); | |
907 | snprintf(card->longname, sizeof(card->longname), | |
f006d8fc RK |
908 | "%s PL%03x rev%u at 0x%08llx, irq %d", |
909 | card->shortname, amba_part(dev), amba_rev(dev), | |
910 | (unsigned long long)dev->res.start, dev->irq[0]); | |
cb5a6ffc RK |
911 | |
912 | aaci = card->private_data; | |
12aa7579 | 913 | mutex_init(&aaci->ac97_sem); |
b60fb519 | 914 | mutex_init(&aaci->irq_lock); |
cb5a6ffc RK |
915 | aaci->card = card; |
916 | aaci->dev = dev; | |
917 | ||
918 | /* Set MAINCR to allow slot 1 and 2 data IO */ | |
919 | aaci->maincr = MAINCR_IE | MAINCR_SL1RXEN | MAINCR_SL1TXEN | | |
920 | MAINCR_SL2RXEN | MAINCR_SL2TXEN; | |
921 | ||
922 | return aaci; | |
923 | } | |
924 | ||
6c9dc19c | 925 | static int aaci_init_pcm(struct aaci *aaci) |
cb5a6ffc | 926 | { |
ceb9e476 | 927 | struct snd_pcm *pcm; |
cb5a6ffc RK |
928 | int ret; |
929 | ||
41762b8c | 930 | ret = snd_pcm_new(aaci->card, "AACI AC'97", 0, 1, 1, &pcm); |
cb5a6ffc RK |
931 | if (ret == 0) { |
932 | aaci->pcm = pcm; | |
933 | pcm->private_data = aaci; | |
934 | pcm->info_flags = 0; | |
935 | ||
936 | strlcpy(pcm->name, DRIVER_NAME, sizeof(pcm->name)); | |
937 | ||
938 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &aaci_playback_ops); | |
41762b8c | 939 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &aaci_capture_ops); |
d6797322 | 940 | snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, |
bc70a9d7 TI |
941 | aaci->card->dev, |
942 | 0, 64 * 1024); | |
cb5a6ffc RK |
943 | } |
944 | ||
945 | return ret; | |
946 | } | |
947 | ||
6c9dc19c | 948 | static unsigned int aaci_size_fifo(struct aaci *aaci) |
cb5a6ffc | 949 | { |
41762b8c | 950 | struct aaci_runtime *aacirun = &aaci->playback; |
cb5a6ffc RK |
951 | int i; |
952 | ||
5d350cba RK |
953 | /* |
954 | * Enable the channel, but don't assign it to any slots, so | |
955 | * it won't empty onto the AC'97 link. | |
956 | */ | |
41762b8c | 957 | writel(CR_FEN | CR_SZ16 | CR_EN, aacirun->base + AACI_TXCR); |
cb5a6ffc | 958 | |
41762b8c KH |
959 | for (i = 0; !(readl(aacirun->base + AACI_SR) & SR_TXFF) && i < 4096; i++) |
960 | writel(0, aacirun->fifo); | |
cb5a6ffc | 961 | |
41762b8c | 962 | writel(0, aacirun->base + AACI_TXCR); |
cb5a6ffc RK |
963 | |
964 | /* | |
965 | * Re-initialise the AACI after the FIFO depth test, to | |
966 | * ensure that the FIFOs are empty. Unfortunately, merely | |
967 | * disabling the channel doesn't clear the FIFO. | |
968 | */ | |
969 | writel(aaci->maincr & ~MAINCR_IE, aaci->base + AACI_MAINCR); | |
7c289385 RK |
970 | readl(aaci->base + AACI_MAINCR); |
971 | udelay(1); | |
cb5a6ffc RK |
972 | writel(aaci->maincr, aaci->base + AACI_MAINCR); |
973 | ||
974 | /* | |
5d350cba | 975 | * If we hit 4096 entries, we failed. Go back to the specified |
cb5a6ffc RK |
976 | * fifo depth. |
977 | */ | |
978 | if (i == 4096) | |
979 | i = 8; | |
980 | ||
981 | return i; | |
982 | } | |
983 | ||
6c9dc19c BP |
984 | static int aaci_probe(struct amba_device *dev, |
985 | const struct amba_id *id) | |
cb5a6ffc RK |
986 | { |
987 | struct aaci *aaci; | |
988 | int ret, i; | |
989 | ||
990 | ret = amba_request_regions(dev, NULL); | |
991 | if (ret) | |
992 | return ret; | |
993 | ||
994 | aaci = aaci_init_card(dev); | |
631e8ad4 TI |
995 | if (!aaci) { |
996 | ret = -ENOMEM; | |
cb5a6ffc RK |
997 | goto out; |
998 | } | |
999 | ||
dc890c2d | 1000 | aaci->base = ioremap(dev->res.start, resource_size(&dev->res)); |
cb5a6ffc RK |
1001 | if (!aaci->base) { |
1002 | ret = -ENOMEM; | |
1003 | goto out; | |
1004 | } | |
1005 | ||
1006 | /* | |
1007 | * Playback uses AACI channel 0 | |
1008 | */ | |
d6a89fef | 1009 | spin_lock_init(&aaci->playback.lock); |
cb5a6ffc RK |
1010 | aaci->playback.base = aaci->base + AACI_CSCH1; |
1011 | aaci->playback.fifo = aaci->base + AACI_DR1; | |
1012 | ||
41762b8c KH |
1013 | /* |
1014 | * Capture uses AACI channel 0 | |
1015 | */ | |
d6a89fef | 1016 | spin_lock_init(&aaci->capture.lock); |
41762b8c KH |
1017 | aaci->capture.base = aaci->base + AACI_CSCH1; |
1018 | aaci->capture.fifo = aaci->base + AACI_DR1; | |
1019 | ||
cb5a6ffc | 1020 | for (i = 0; i < 4; i++) { |
e12ba644 | 1021 | void __iomem *base = aaci->base + i * 0x14; |
cb5a6ffc RK |
1022 | |
1023 | writel(0, base + AACI_IE); | |
1024 | writel(0, base + AACI_TXCR); | |
1025 | writel(0, base + AACI_RXCR); | |
1026 | } | |
1027 | ||
1028 | writel(0x1fff, aaci->base + AACI_INTCLR); | |
1029 | writel(aaci->maincr, aaci->base + AACI_MAINCR); | |
b68b58fd PJ |
1030 | /* |
1031 | * Fix: ac97 read back fail errors by reading | |
1032 | * from any arbitrary aaci register. | |
1033 | */ | |
1034 | readl(aaci->base + AACI_CSCH1); | |
f27f218c CM |
1035 | ret = aaci_probe_ac97(aaci); |
1036 | if (ret) | |
1037 | goto out; | |
1038 | ||
cb5a6ffc | 1039 | /* |
f27f218c | 1040 | * Size the FIFOs (must be multiple of 16). |
5d350cba | 1041 | * This is the number of entries in the FIFO. |
cb5a6ffc | 1042 | */ |
5d350cba RK |
1043 | aaci->fifo_depth = aaci_size_fifo(aaci); |
1044 | if (aaci->fifo_depth & 15) { | |
1045 | printk(KERN_WARNING "AACI: FIFO depth %d not supported\n", | |
1046 | aaci->fifo_depth); | |
f27f218c | 1047 | ret = -ENODEV; |
cb5a6ffc | 1048 | goto out; |
f27f218c | 1049 | } |
cb5a6ffc RK |
1050 | |
1051 | ret = aaci_init_pcm(aaci); | |
1052 | if (ret) | |
1053 | goto out; | |
1054 | ||
1055 | ret = snd_card_register(aaci->card); | |
1056 | if (ret == 0) { | |
5d350cba RK |
1057 | dev_info(&dev->dev, "%s\n", aaci->card->longname); |
1058 | dev_info(&dev->dev, "FIFO %u entries\n", aaci->fifo_depth); | |
cb5a6ffc RK |
1059 | amba_set_drvdata(dev, aaci->card); |
1060 | return ret; | |
1061 | } | |
1062 | ||
1063 | out: | |
1064 | if (aaci) | |
1065 | snd_card_free(aaci->card); | |
1066 | amba_release_regions(dev); | |
1067 | return ret; | |
1068 | } | |
1069 | ||
6c9dc19c | 1070 | static int aaci_remove(struct amba_device *dev) |
cb5a6ffc | 1071 | { |
ceb9e476 | 1072 | struct snd_card *card = amba_get_drvdata(dev); |
cb5a6ffc | 1073 | |
cb5a6ffc RK |
1074 | if (card) { |
1075 | struct aaci *aaci = card->private_data; | |
1076 | writel(0, aaci->base + AACI_MAINCR); | |
1077 | ||
1078 | snd_card_free(card); | |
1079 | amba_release_regions(dev); | |
1080 | } | |
1081 | ||
1082 | return 0; | |
1083 | } | |
1084 | ||
1085 | static struct amba_id aaci_ids[] = { | |
1086 | { | |
1087 | .id = 0x00041041, | |
1088 | .mask = 0x000fffff, | |
1089 | }, | |
1090 | { 0, 0 }, | |
1091 | }; | |
1092 | ||
9d5c6273 DM |
1093 | MODULE_DEVICE_TABLE(amba, aaci_ids); |
1094 | ||
cb5a6ffc RK |
1095 | static struct amba_driver aaci_driver = { |
1096 | .drv = { | |
1097 | .name = DRIVER_NAME, | |
b13a7149 | 1098 | .pm = AACI_DEV_PM_OPS, |
cb5a6ffc RK |
1099 | }, |
1100 | .probe = aaci_probe, | |
6c9dc19c | 1101 | .remove = aaci_remove, |
cb5a6ffc RK |
1102 | .id_table = aaci_ids, |
1103 | }; | |
1104 | ||
9e5ed094 | 1105 | module_amba_driver(aaci_driver); |
cb5a6ffc RK |
1106 | |
1107 | MODULE_LICENSE("GPL"); | |
1108 | MODULE_DESCRIPTION("ARM PrimeCell PL041 Advanced Audio CODEC Interface driver"); |