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ALSA: hda: constify attribute_group structures.
[mirror_ubuntu-bionic-kernel.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
27fe48d9 47#include <linux/io.h>
b8dfc462 48#include <linux/pm_runtime.h>
5d890f59
PLB		 49#include <linux/clocksource.h>
50#include <linux/time.h>
f4c482a4 51#include <linux/completion.h>
5d890f59 52
27fe48d9
TI		 53#ifdef CONFIG_X86
54/* for snoop control */
55#include <asm/pgtable.h>
7f80f513 56#include <asm/set_memory.h>
50279d9b 57#include <asm/cpufeature.h>
27fe48d9 58#endif
1da177e4
LT		 59#include <sound/core.h>
60#include <sound/initval.h>
98d8fc6c
ML		 61#include <sound/hdaudio.h>
62#include <sound/hda_i915.h>
9121947d 63#include <linux/vgaarb.h>
a82d51ed 64#include <linux/vga_switcheroo.h>
4918cdab 65#include <linux/firmware.h>
1da177e4 66#include "hda_codec.h"
05e84878 67#include "hda_controller.h"
347de1f8 68#include "hda_intel.h"
1da177e4 69
785d8c4b
LY		 70#define CREATE_TRACE_POINTS
71#include "hda_intel_trace.h"
72
b6050ef6
TI		 73/* position fix mode */
74enum {
75 POS_FIX_AUTO,
76 POS_FIX_LPIB,
77 POS_FIX_POSBUF,
78 POS_FIX_VIACOMBO,
79 POS_FIX_COMBO,
f87e7f25 80 POS_FIX_SKL,
b6050ef6
TI		 81};
82
9a34af4a
TI		 83/* Defines for ATI HD Audio support in SB450 south bridge */
84#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
85#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
86
87/* Defines for Nvidia HDA support */
88#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
89#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
90#define NVIDIA_HDA_ISTRM_COH 0x4d
91#define NVIDIA_HDA_OSTRM_COH 0x4c
92#define NVIDIA_HDA_ENABLE_COHBIT 0x01
93
94/* Defines for Intel SCH HDA snoop control */
6639484d
LY		 95#define INTEL_HDA_CGCTL 0x48
96#define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
9a34af4a
TI		 97#define INTEL_SCH_HDA_DEVC 0x78
98#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
99
100/* Define IN stream 0 FIFO size offset in VIA controller */
101#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
102/* Define VIA HD Audio Device ID*/
103#define VIA_HDAC_DEVICE_ID 0x3288
104
33124929
TI		 105/* max number of SDs */
106/* ICH, ATI and VIA have 4 playback and 4 capture */
107#define ICH6_NUM_CAPTURE 4
108#define ICH6_NUM_PLAYBACK 4
109
110/* ULI has 6 playback and 5 capture */
111#define ULI_NUM_CAPTURE 5
112#define ULI_NUM_PLAYBACK 6
113
114/* ATI HDMI may have up to 8 playbacks and 0 capture */
115#define ATIHDMI_NUM_CAPTURE 0
116#define ATIHDMI_NUM_PLAYBACK 8
117
118/* TERA has 4 playback and 3 capture */
119#define TERA_NUM_CAPTURE 3
120#define TERA_NUM_PLAYBACK 4
121
1da177e4 122
5aba4f8e
TI		 123static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
124static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 125static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 126static char *model[SNDRV_CARDS];
1dac6695 127static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 128static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 129static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 130static int probe_only[SNDRV_CARDS];
26a6cb6c 131static int jackpoll_ms[SNDRV_CARDS];
41438f13 132static int single_cmd = -1;
71623855 133static int enable_msi = -1;
4ea6fbc8
TI		 134#ifdef CONFIG_SND_HDA_PATCH_LOADER
135static char *patch[SNDRV_CARDS];
136#endif
2dca0bba 137#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 138static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 139 CONFIG_SND_HDA_INPUT_BEEP_MODE};
140#endif
1da177e4 141
5aba4f8e 142module_param_array(index, int, NULL, 0444);
1da177e4 143MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 144module_param_array(id, charp, NULL, 0444);
1da177e4 145MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 146module_param_array(enable, bool, NULL, 0444);
147MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
148module_param_array(model, charp, NULL, 0444);
1da177e4 149MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 150module_param_array(position_fix, int, NULL, 0444);
4cb36310 151MODULE_PARM_DESC(position_fix, "DMA pointer read method."
f87e7f25 152 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+).");
555e219f
TI		 153module_param_array(bdl_pos_adj, int, NULL, 0644);
154MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 155module_param_array(probe_mask, int, NULL, 0444);
606ad75f 156MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 157module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 158MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 159module_param_array(jackpoll_ms, int, NULL, 0444);
160MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
41438f13 161module_param(single_cmd, bint, 0444);
d01ce99f
TI		 162MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
163 "(for debugging only).");
ac9ef6cf 164module_param(enable_msi, bint, 0444);
134a11f0 165MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 166#ifdef CONFIG_SND_HDA_PATCH_LOADER
167module_param_array(patch, charp, NULL, 0444);
168MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
169#endif
2dca0bba 170#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 171module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 172MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 173 "(0=off, 1=on) (default=1).");
2dca0bba 174#endif
606ad75f 175
83012a7c 176#ifdef CONFIG_PM
65fcd41d 177static int param_set_xint(const char *val, const struct kernel_param *kp);
9c27847d 178static const struct kernel_param_ops param_ops_xint = {
65fcd41d
TI		 179 .set = param_set_xint,
180 .get = param_get_int,
181};
182#define param_check_xint param_check_int
183
fee2fba3 184static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 185module_param(power_save, xint, 0644);
fee2fba3
TI		 186MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
187 "(in second, 0 = disable).");
1da177e4 188
dee1b66c
TI		 189/* reset the HD-audio controller in power save mode.
190 * this may give more power-saving, but will take longer time to
191 * wake up.
192 */
8fc24426
TI		 193static bool power_save_controller = 1;
194module_param(power_save_controller, bool, 0644);
dee1b66c 195MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
e62a42ae 196#else
bb573928 197#define power_save 0
83012a7c 198#endif /* CONFIG_PM */
dee1b66c 199
7bfe059e
TI		 200static int align_buffer_size = -1;
201module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 202MODULE_PARM_DESC(align_buffer_size,
203 "Force buffer and period sizes to be multiple of 128 bytes.");
204
27fe48d9 205#ifdef CONFIG_X86
7c732015
TI		 206static int hda_snoop = -1;
207module_param_named(snoop, hda_snoop, bint, 0444);
27fe48d9 208MODULE_PARM_DESC(snoop, "Enable/disable snooping");
27fe48d9
TI		 209#else
210#define hda_snoop true
27fe48d9
TI		 211#endif
212
213
1da177e4
LT		 214MODULE_LICENSE("GPL");
215MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
216 "{Intel, ICH6M},"
2f1b3818 217 "{Intel, ICH7},"
f5d40b30 218 "{Intel, ESB2},"
d2981393 219 "{Intel, ICH8},"
f9cc8a8b 220 "{Intel, ICH9},"
c34f5a04 221 "{Intel, ICH10},"
b29c2360 222 "{Intel, PCH},"
d2f2fcd2 223 "{Intel, CPT},"
d2edeb7c 224 "{Intel, PPT},"
8bc039a1 225 "{Intel, LPT},"
144dad99 226 "{Intel, LPT_LP},"
4eeca499 227 "{Intel, WPT_LP},"
c8b00fd2 228 "{Intel, SPT},"
b4565913 229 "{Intel, SPT_LP},"
e926f2c8 230 "{Intel, HPT},"
cea310e8 231 "{Intel, PBG},"
4979bca9 232 "{Intel, SCH},"
fc20a562 233 "{ATI, SB450},"
89be83f8 234 "{ATI, SB600},"
778b6e1b 235 "{ATI, RS600},"
5b15c95f 236 "{ATI, RS690},"
e6db1119
WL		 237 "{ATI, RS780},"
238 "{ATI, R600},"
2797f724
HRK		 239 "{ATI, RV630},"
240 "{ATI, RV610},"
27da1834
WL		 241 "{ATI, RV670},"
242 "{ATI, RV635},"
243 "{ATI, RV620},"
244 "{ATI, RV770},"
fc20a562 245 "{VIA, VT8251},"
47672310 246 "{VIA, VT8237A},"
07e4ca50
TI		 247 "{SiS, SIS966},"
248 "{ULI, M5461}}");
1da177e4
LT		 249MODULE_DESCRIPTION("Intel HDA driver");
250
a82d51ed 251#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
f8f1becf 252#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
a82d51ed
TI		 253#define SUPPORT_VGA_SWITCHEROO
254#endif
255#endif
256
257
1da177e4 258/*
1da177e4 259 */
1da177e4 260
07e4ca50
TI		 261/* driver types */
262enum {
263 AZX_DRIVER_ICH,
32679f95 264 AZX_DRIVER_PCH,
4979bca9 265 AZX_DRIVER_SCH,
a4b4793f 266 AZX_DRIVER_SKL,
fab1285a 267 AZX_DRIVER_HDMI,
07e4ca50 268 AZX_DRIVER_ATI,
778b6e1b 269 AZX_DRIVER_ATIHDMI,
1815b34a 270 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 271 AZX_DRIVER_VIA,
272 AZX_DRIVER_SIS,
273 AZX_DRIVER_ULI,
da3fca21 274 AZX_DRIVER_NVIDIA,
f269002e 275 AZX_DRIVER_TERA,
14d34f16 276 AZX_DRIVER_CTX,
5ae763b1 277 AZX_DRIVER_CTHDA,
c563f473 278 AZX_DRIVER_CMEDIA,
c4da29ca 279 AZX_DRIVER_GENERIC,
2f5983f2 280 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 281};
282
37e661ee
TI		 283#define azx_get_snoop_type(chip) \
284 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
285#define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
286
b42b4afb
TI		 287/* quirks for old Intel chipsets */
288#define AZX_DCAPS_INTEL_ICH \
103884a3 289 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
b42b4afb 290
2ea3c6a2 291/* quirks for Intel PCH */
6603249d 292#define AZX_DCAPS_INTEL_PCH_BASE \
103884a3 293 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
bcb337d1 294 AZX_DCAPS_SNOOP_TYPE(SCH))
d7dab4db 295
55913110 296/* PCH up to IVB; no runtime PM */
6603249d 297#define AZX_DCAPS_INTEL_PCH_NOPM \
55913110 298 (AZX_DCAPS_INTEL_PCH_BASE)
6603249d 299
55913110 300/* PCH for HSW/BDW; with runtime PM */
d7dab4db 301#define AZX_DCAPS_INTEL_PCH \
6603249d 302 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
9477c58e 303
6603249d 304/* HSW HDMI */
33499a15 305#define AZX_DCAPS_INTEL_HASWELL \
103884a3 306 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
37e661ee
TI		 307 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
308 AZX_DCAPS_SNOOP_TYPE(SCH))
33499a15 309
54a0405d
LY		 310/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
311#define AZX_DCAPS_INTEL_BROADWELL \
103884a3 312 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
37e661ee
TI		 313 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
314 AZX_DCAPS_SNOOP_TYPE(SCH))
54a0405d 315
40cc2392
ML		 316#define AZX_DCAPS_INTEL_BAYTRAIL \
317 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
318
2d846c74
LY		 319#define AZX_DCAPS_INTEL_BRASWELL \
320 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
321
d6795827 322#define AZX_DCAPS_INTEL_SKYLAKE \
2d846c74
LY		 323 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
324 AZX_DCAPS_I915_POWERWELL)
d6795827 325
c87693da
LH		 326#define AZX_DCAPS_INTEL_BROXTON \
327 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
328 AZX_DCAPS_I915_POWERWELL)
329
9477c58e
TI		 330/* quirks for ATI SB / AMD Hudson */
331#define AZX_DCAPS_PRESET_ATI_SB \
37e661ee
TI		 332 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
333 AZX_DCAPS_SNOOP_TYPE(ATI))
9477c58e
TI		 334
335/* quirks for ATI/AMD HDMI */
336#define AZX_DCAPS_PRESET_ATI_HDMI \
db79afa1
BH		 337 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
338 AZX_DCAPS_NO_MSI64)
9477c58e 339
37e661ee
TI		 340/* quirks for ATI HDMI with snoop off */
341#define AZX_DCAPS_PRESET_ATI_HDMI_NS \
342 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
343
9477c58e
TI		 344/* quirks for Nvidia */
345#define AZX_DCAPS_PRESET_NVIDIA \
3ab7511e 346 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
37e661ee 347 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
9477c58e 348
5ae763b1 349#define AZX_DCAPS_PRESET_CTHDA \
37e661ee 350 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
cadd16ea 351 AZX_DCAPS_NO_64BIT |\
37e661ee 352 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
5ae763b1 353
a82d51ed 354/*
2b760d88 355 * vga_switcheroo support
a82d51ed
TI		 356 */
357#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 358#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
359#else
360#define use_vga_switcheroo(chip) 0
361#endif
362
03b135ce
LY		 363#define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
364 ((pci)->device == 0x0c0c) || \
365 ((pci)->device == 0x0d0c) || \
366 ((pci)->device == 0x160c))
367
7e31a015 368#define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
7c23b7c1 369
48c8b0eb 370static char *driver_short_names[] = {
07e4ca50 371 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 372 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 373 [AZX_DRIVER_SCH] = "HDA Intel MID",
a4b4793f 374 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
fab1285a 375 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 376 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 377 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 378 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 379 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
380 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 381 [AZX_DRIVER_ULI] = "HDA ULI M5461",
382 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 383 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 384 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 385 [AZX_DRIVER_CTHDA] = "HDA Creative",
c563f473 386 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
c4da29ca 387 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 388};
389
27fe48d9 390#ifdef CONFIG_X86
9ddf1aeb 391static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
27fe48d9 392{
9ddf1aeb
TI		 393 int pages;
394
27fe48d9
TI		 395 if (azx_snoop(chip))
396 return;
9ddf1aeb
TI		 397 if (!dmab || !dmab->area || !dmab->bytes)
398 return;
399
400#ifdef CONFIG_SND_DMA_SGBUF
401 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
402 struct snd_sg_buf *sgbuf = dmab->private_data;
3b70bdba
TI		 403 if (chip->driver_type == AZX_DRIVER_CMEDIA)
404 return; /* deal with only CORB/RIRB buffers */
27fe48d9 405 if (on)
9ddf1aeb 406 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
27fe48d9 407 else
9ddf1aeb
TI		 408 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
409 return;
27fe48d9 410 }
9ddf1aeb
TI		 411#endif
412
413 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
414 if (on)
415 set_memory_wc((unsigned long)dmab->area, pages);
416 else
417 set_memory_wb((unsigned long)dmab->area, pages);
27fe48d9
TI		 418}
419
420static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
421 bool on)
422{
9ddf1aeb 423 __mark_pages_wc(chip, buf, on);
27fe48d9
TI		 424}
425static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 426 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 427{
428 if (azx_dev->wc_marked != on) {
9ddf1aeb 429 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
27fe48d9
TI		 430 azx_dev->wc_marked = on;
431 }
432}
433#else
434/* NOP for other archs */
435static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
436 bool on)
437{
438}
439static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 440 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 441{
442}
443#endif
444
68e7fffc 445static int azx_acquire_irq(struct azx *chip, int do_disconnect);
111d3af5 446
cb53c626
TI		 447/*
448 * initialize the PCI registers
449 */
450/* update bits in a PCI register byte */
451static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
452 unsigned char mask, unsigned char val)
453{
454 unsigned char data;
455
456 pci_read_config_byte(pci, reg, &data);
457 data &= ~mask;
458 data |= (val & mask);
459 pci_write_config_byte(pci, reg, data);
460}
461
462static void azx_init_pci(struct azx *chip)
463{
37e661ee
TI		 464 int snoop_type = azx_get_snoop_type(chip);
465
cb53c626
TI		 466 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
467 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
468 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 469 * codecs.
470 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 471 */
46f2cc80 472 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
4e76a883 473 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
fb1d8ac2 474 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
9477c58e 475 }
cb53c626 476
9477c58e
TI		 477 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
478 * we need to enable snoop.
479 */
37e661ee 480 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
4e76a883
TI		 481 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
482 azx_snoop(chip));
cb53c626 483 update_pci_byte(chip->pci,
27fe48d9
TI		 484 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
485 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 486 }
487
488 /* For NVIDIA HDA, enable snoop */
37e661ee 489 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
4e76a883
TI		 490 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
491 azx_snoop(chip));
cb53c626
TI		 492 update_pci_byte(chip->pci,
493 NVIDIA_HDA_TRANSREG_ADDR,
494 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 495 update_pci_byte(chip->pci,
496 NVIDIA_HDA_ISTRM_COH,
497 0x01, NVIDIA_HDA_ENABLE_COHBIT);
498 update_pci_byte(chip->pci,
499 NVIDIA_HDA_OSTRM_COH,
500 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 501 }
502
503 /* Enable SCH/PCH snoop if needed */
37e661ee 504 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
27fe48d9 505 unsigned short snoop;
90a5ad52 506 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 507 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
508 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
509 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
510 if (!azx_snoop(chip))
511 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
512 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 513 pci_read_config_word(chip->pci,
514 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 515 }
4e76a883
TI		 516 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
517 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
518 "Disabled" : "Enabled");
da3fca21 519 }
1da177e4
LT		 520}
521
7c23b7c1
LH		 522/*
523 * In BXT-P A0, HD-Audio DMA requests is later than expected,
524 * and makes an audio stream sensitive to system latencies when
525 * 24/32 bits are playing.
526 * Adjusting threshold of DMA fifo to force the DMA request
527 * sooner to improve latency tolerance at the expense of power.
528 */
529static void bxt_reduce_dma_latency(struct azx *chip)
530{
531 u32 val;
532
70eafad8 533 val = azx_readl(chip, VS_EM4L);
7c23b7c1 534 val &= (0x3 << 20);
70eafad8 535 azx_writel(chip, VS_EM4L, val);
7c23b7c1
LH		 536}
537
1f9d3d98
LY		 538/*
539 * ML_LCAP bits:
540 * bit 0: 6 MHz Supported
541 * bit 1: 12 MHz Supported
542 * bit 2: 24 MHz Supported
543 * bit 3: 48 MHz Supported
544 * bit 4: 96 MHz Supported
545 * bit 5: 192 MHz Supported
546 */
547static int intel_get_lctl_scf(struct azx *chip)
548{
549 struct hdac_bus *bus = azx_bus(chip);
550 static int preferred_bits[] = { 2, 3, 1, 4, 5 };
551 u32 val, t;
552 int i;
553
554 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
555
556 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
557 t = preferred_bits[i];
558 if (val & (1 << t))
559 return t;
560 }
561
562 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
563 return 0;
564}
565
566static int intel_ml_lctl_set_power(struct azx *chip, int state)
567{
568 struct hdac_bus *bus = azx_bus(chip);
569 u32 val;
570 int timeout;
571
572 /*
573 * the codecs are sharing the first link setting by default
574 * If other links are enabled for stream, they need similar fix
575 */
576 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
577 val &= ~AZX_MLCTL_SPA;
578 val |= state << AZX_MLCTL_SPA_SHIFT;
579 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
580 /* wait for CPA */
581 timeout = 50;
582 while (timeout) {
583 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
584 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
585 return 0;
586 timeout--;
587 udelay(10);
588 }
589
590 return -1;
591}
592
593static void intel_init_lctl(struct azx *chip)
594{
595 struct hdac_bus *bus = azx_bus(chip);
596 u32 val;
597 int ret;
598
599 /* 0. check lctl register value is correct or not */
600 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
601 /* if SCF is already set, let's use it */
602 if ((val & ML_LCTL_SCF_MASK) != 0)
603 return;
604
605 /*
606 * Before operating on SPA, CPA must match SPA.
607 * Any deviation may result in undefined behavior.
608 */
609 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
610 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
611 return;
612
613 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
614 ret = intel_ml_lctl_set_power(chip, 0);
615 udelay(100);
616 if (ret)
617 goto set_spa;
618
619 /* 2. update SCF to select a properly audio clock*/
620 val &= ~ML_LCTL_SCF_MASK;
621 val |= intel_get_lctl_scf(chip);
622 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
623
624set_spa:
625 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
626 intel_ml_lctl_set_power(chip, 1);
627 udelay(100);
628}
629
0a673521
LH		 630static void hda_intel_init_chip(struct azx *chip, bool full_reset)
631{
98d8fc6c 632 struct hdac_bus *bus = azx_bus(chip);
7c23b7c1 633 struct pci_dev *pci = chip->pci;
6639484d 634 u32 val;
0a673521
LH		 635
636 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
98d8fc6c 637 snd_hdac_set_codec_wakeup(bus, true);
a4b4793f 638 if (chip->driver_type == AZX_DRIVER_SKL) {
6639484d
LY		 639 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
640 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
641 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
642 }
0a673521 643 azx_init_chip(chip, full_reset);
a4b4793f 644 if (chip->driver_type == AZX_DRIVER_SKL) {
6639484d
LY		 645 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
646 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
647 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
648 }
0a673521 649 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
98d8fc6c 650 snd_hdac_set_codec_wakeup(bus, false);
7c23b7c1
LH		 651
652 /* reduce dma latency to avoid noise */
7e31a015 653 if (IS_BXT(pci))
7c23b7c1 654 bxt_reduce_dma_latency(chip);
1f9d3d98
LY		 655
656 if (bus->mlcap != NULL)
657 intel_init_lctl(chip);
0a673521
LH		 658}
659
b6050ef6
TI		 660/* calculate runtime delay from LPIB */
661static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
662 unsigned int pos)
663{
7833c3f8 664 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6
TI		 665 int stream = substream->stream;
666 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
667 int delay;
668
669 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
670 delay = pos - lpib_pos;
671 else
672 delay = lpib_pos - pos;
673 if (delay < 0) {
7833c3f8 674 if (delay >= azx_dev->core.delay_negative_threshold)
b6050ef6
TI		 675 delay = 0;
676 else
7833c3f8 677 delay += azx_dev->core.bufsize;
b6050ef6
TI		 678 }
679
7833c3f8 680 if (delay >= azx_dev->core.period_bytes) {
b6050ef6
TI		 681 dev_info(chip->card->dev,
682 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
7833c3f8 683 delay, azx_dev->core.period_bytes);
b6050ef6
TI		 684 delay = 0;
685 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
686 chip->get_delay[stream] = NULL;
687 }
688
689 return bytes_to_frames(substream->runtime, delay);
690}
691
9ad593f6
TI		 692static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
693
7ca954a8
DR		 694/* called from IRQ */
695static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
696{
9a34af4a 697 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
7ca954a8
DR		 698 int ok;
699
700 ok = azx_position_ok(chip, azx_dev);
701 if (ok == 1) {
702 azx_dev->irq_pending = 0;
703 return ok;
2f35c630 704 } else if (ok == 0) {
7ca954a8
DR		 705 /* bogus IRQ, process it later */
706 azx_dev->irq_pending = 1;
2f35c630 707 schedule_work(&hda->irq_pending_work);
7ca954a8
DR		 708 }
709 return 0;
710}
711
17eccb27
ML		 712/* Enable/disable i915 display power for the link */
713static int azx_intel_link_power(struct azx *chip, bool enable)
714{
98d8fc6c 715 struct hdac_bus *bus = azx_bus(chip);
17eccb27 716
98d8fc6c 717 return snd_hdac_display_power(bus, enable);
17eccb27
ML		 718}
719
9ad593f6
TI		 720/*
721 * Check whether the current DMA position is acceptable for updating
722 * periods. Returns non-zero if it's OK.
723 *
724 * Many HD-audio controllers appear pretty inaccurate about
725 * the update-IRQ timing. The IRQ is issued before actually the
726 * data is processed. So, we need to process it afterwords in a
727 * workqueue.
728 */
729static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
730{
7833c3f8 731 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6 732 int stream = substream->stream;
e5463720 733 u32 wallclk;
9ad593f6
TI		 734 unsigned int pos;
735
7833c3f8
TI		 736 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
737 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
fa00e046 738 return -1; /* bogus (too early) interrupt */
fa00e046 739
b6050ef6
TI		 740 if (chip->get_position[stream])
741 pos = chip->get_position[stream](chip, azx_dev);
742 else { /* use the position buffer as default */
743 pos = azx_get_pos_posbuf(chip, azx_dev);
744 if (!pos || pos == (u32)-1) {
745 dev_info(chip->card->dev,
746 "Invalid position buffer, using LPIB read method instead.\n");
747 chip->get_position[stream] = azx_get_pos_lpib;
ccc98865
TI		 748 if (chip->get_position[0] == azx_get_pos_lpib &&
749 chip->get_position[1] == azx_get_pos_lpib)
750 azx_bus(chip)->use_posbuf = false;
b6050ef6
TI		 751 pos = azx_get_pos_lpib(chip, azx_dev);
752 chip->get_delay[stream] = NULL;
753 } else {
754 chip->get_position[stream] = azx_get_pos_posbuf;
755 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
756 chip->get_delay[stream] = azx_get_delay_from_lpib;
757 }
758 }
759
7833c3f8 760 if (pos >= azx_dev->core.bufsize)
b6050ef6 761 pos = 0;
9ad593f6 762
7833c3f8 763 if (WARN_ONCE(!azx_dev->core.period_bytes,
d6d8bf54 764 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 765 return -1; /* this shouldn't happen! */
7833c3f8
TI		 766 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
767 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
f48f606d 768 /* NG - it's below the first next period boundary */
4f0189be 769 return chip->bdl_pos_adj ? 0 : -1;
7833c3f8 770 azx_dev->core.start_wallclk += wallclk;
9ad593f6
TI		 771 return 1; /* OK, it's fine */
772}
773
774/*
775 * The work for pending PCM period updates.
776 */
777static void azx_irq_pending_work(struct work_struct *work)
778{
9a34af4a
TI		 779 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
780 struct azx *chip = &hda->chip;
7833c3f8
TI		 781 struct hdac_bus *bus = azx_bus(chip);
782 struct hdac_stream *s;
783 int pending, ok;
9ad593f6 784
9a34af4a 785 if (!hda->irq_pending_warned) {
4e76a883
TI		 786 dev_info(chip->card->dev,
787 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
788 chip->card->number);
9a34af4a 789 hda->irq_pending_warned = 1;
a6a950a8
TI		 790 }
791
9ad593f6
TI		 792 for (;;) {
793 pending = 0;
a41d1224 794 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 795 list_for_each_entry(s, &bus->stream_list, list) {
796 struct azx_dev *azx_dev = stream_to_azx_dev(s);
9ad593f6 797 if (!azx_dev->irq_pending ||
7833c3f8
TI		 798 !s->substream ||
799 !s->running)
9ad593f6 800 continue;
e5463720
JK		 801 ok = azx_position_ok(chip, azx_dev);
802 if (ok > 0) {
9ad593f6 803 azx_dev->irq_pending = 0;
a41d1224 804 spin_unlock(&bus->reg_lock);
7833c3f8 805 snd_pcm_period_elapsed(s->substream);
a41d1224 806 spin_lock(&bus->reg_lock);
e5463720
JK		 807 } else if (ok < 0) {
808 pending = 0; /* too early */
9ad593f6
TI		 809 } else
810 pending++;
811 }
a41d1224 812 spin_unlock_irq(&bus->reg_lock);
9ad593f6
TI		 813 if (!pending)
814 return;
08af495f 815 msleep(1);
9ad593f6
TI		 816 }
817}
818
819/* clear irq_pending flags and assure no on-going workq */
820static void azx_clear_irq_pending(struct azx *chip)
821{
7833c3f8
TI		 822 struct hdac_bus *bus = azx_bus(chip);
823 struct hdac_stream *s;
9ad593f6 824
a41d1224 825 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 826 list_for_each_entry(s, &bus->stream_list, list) {
827 struct azx_dev *azx_dev = stream_to_azx_dev(s);
828 azx_dev->irq_pending = 0;
829 }
a41d1224 830 spin_unlock_irq(&bus->reg_lock);
1da177e4
LT		 831}
832
68e7fffc
TI		 833static int azx_acquire_irq(struct azx *chip, int do_disconnect)
834{
a41d1224
TI		 835 struct hdac_bus *bus = azx_bus(chip);
836
437a5a46
TI		 837 if (request_irq(chip->pci->irq, azx_interrupt,
838 chip->msi ? 0 : IRQF_SHARED,
de65360b 839 chip->card->irq_descr, chip)) {
4e76a883
TI		 840 dev_err(chip->card->dev,
841 "unable to grab IRQ %d, disabling device\n",
842 chip->pci->irq);
68e7fffc
TI		 843 if (do_disconnect)
844 snd_card_disconnect(chip->card);
845 return -1;
846 }
a41d1224 847 bus->irq = chip->pci->irq;
69e13418 848 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 849 return 0;
850}
851
b6050ef6
TI		 852/* get the current DMA position with correction on VIA chips */
853static unsigned int azx_via_get_position(struct azx *chip,
854 struct azx_dev *azx_dev)
855{
856 unsigned int link_pos, mini_pos, bound_pos;
857 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
858 unsigned int fifo_size;
859
1604eeee 860 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
7833c3f8 861 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
b6050ef6
TI		 862 /* Playback, no problem using link position */
863 return link_pos;
864 }
865
866 /* Capture */
867 /* For new chipset,
868 * use mod to get the DMA position just like old chipset
869 */
7833c3f8
TI		 870 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
871 mod_dma_pos %= azx_dev->core.period_bytes;
b6050ef6
TI		 872
873 /* azx_dev->fifo_size can't get FIFO size of in stream.
874 * Get from base address + offset.
875 */
a41d1224
TI		 876 fifo_size = readw(azx_bus(chip)->remap_addr +
877 VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
b6050ef6
TI		 878
879 if (azx_dev->insufficient) {
880 /* Link position never gather than FIFO size */
881 if (link_pos <= fifo_size)
882 return 0;
883
884 azx_dev->insufficient = 0;
885 }
886
887 if (link_pos <= fifo_size)
7833c3f8 888 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
b6050ef6
TI		 889 else
890 mini_pos = link_pos - fifo_size;
891
892 /* Find nearest previous boudary */
7833c3f8
TI		 893 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
894 mod_link_pos = link_pos % azx_dev->core.period_bytes;
b6050ef6
TI		 895 if (mod_link_pos >= fifo_size)
896 bound_pos = link_pos - mod_link_pos;
897 else if (mod_dma_pos >= mod_mini_pos)
898 bound_pos = mini_pos - mod_mini_pos;
899 else {
7833c3f8
TI		 900 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
901 if (bound_pos >= azx_dev->core.bufsize)
b6050ef6
TI		 902 bound_pos = 0;
903 }
904
905 /* Calculate real DMA position we want */
906 return bound_pos + mod_dma_pos;
907}
908
f87e7f25
TI		 909static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
910 struct azx_dev *azx_dev)
911{
912 return _snd_hdac_chip_readl(azx_bus(chip),
913 AZX_REG_VS_SDXDPIB_XBASE +
914 (AZX_REG_VS_SDXDPIB_XINTERVAL *
915 azx_dev->core.index));
916}
917
918/* get the current DMA position with correction on SKL+ chips */
919static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
920{
921 /* DPIB register gives a more accurate position for playback */
922 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
923 return azx_skl_get_dpib_pos(chip, azx_dev);
924
925 /* For capture, we need to read posbuf, but it requires a delay
926 * for the possible boundary overlap; the read of DPIB fetches the
927 * actual posbuf
928 */
929 udelay(20);
930 azx_skl_get_dpib_pos(chip, azx_dev);
931 return azx_get_pos_posbuf(chip, azx_dev);
932}
933
83012a7c 934#ifdef CONFIG_PM
65fcd41d
TI		 935static DEFINE_MUTEX(card_list_lock);
936static LIST_HEAD(card_list);
937
938static void azx_add_card_list(struct azx *chip)
939{
9a34af4a 940 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 941 mutex_lock(&card_list_lock);
9a34af4a 942 list_add(&hda->list, &card_list);
65fcd41d
TI		 943 mutex_unlock(&card_list_lock);
944}
945
946static void azx_del_card_list(struct azx *chip)
947{
9a34af4a 948 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 949 mutex_lock(&card_list_lock);
9a34af4a 950 list_del_init(&hda->list);
65fcd41d
TI		 951 mutex_unlock(&card_list_lock);
952}
953
954/* trigger power-save check at writing parameter */
955static int param_set_xint(const char *val, const struct kernel_param *kp)
956{
9a34af4a 957 struct hda_intel *hda;
65fcd41d 958 struct azx *chip;
65fcd41d
TI		 959 int prev = power_save;
960 int ret = param_set_int(val, kp);
961
962 if (ret || prev == power_save)
963 return ret;
964
965 mutex_lock(&card_list_lock);
9a34af4a
TI		 966 list_for_each_entry(hda, &card_list, list) {
967 chip = &hda->chip;
a41d1224 968 if (!hda->probe_continued || chip->disabled)
65fcd41d 969 continue;
a41d1224 970 snd_hda_set_power_save(&chip->bus, power_save * 1000);
65fcd41d
TI		 971 }
972 mutex_unlock(&card_list_lock);
973 return 0;
974}
975#else
976#define azx_add_card_list(chip) /* NOP */
977#define azx_del_card_list(chip) /* NOP */
83012a7c 978#endif /* CONFIG_PM */
5c0b9bec 979
7ccbde57 980#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 981/*
982 * power management
983 */
68cb2b55 984static int azx_suspend(struct device *dev)
1da177e4 985{
68cb2b55 986 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 987 struct azx *chip;
988 struct hda_intel *hda;
a41d1224 989 struct hdac_bus *bus;
1da177e4 990
2d9772ef
TI		 991 if (!card)
992 return 0;
993
994 chip = card->private_data;
995 hda = container_of(chip, struct hda_intel, chip);
342e8449 996 if (chip->disabled || hda->init_failed || !chip->running)
c5c21523
TI		 997 return 0;
998
a41d1224 999 bus = azx_bus(chip);
421a1252 1000 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 1001 azx_clear_irq_pending(chip);
cb53c626 1002 azx_stop_chip(chip);
7295b264 1003 azx_enter_link_reset(chip);
a41d1224
TI		 1004 if (bus->irq >= 0) {
1005 free_irq(bus->irq, chip);
1006 bus->irq = -1;
30b35399 1007 }
a07187c9 1008
68e7fffc 1009 if (chip->msi)
43001c95 1010 pci_disable_msi(chip->pci);
795614dd
ML		 1011 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
1012 && hda->need_i915_power)
98d8fc6c 1013 snd_hdac_display_power(bus, false);
785d8c4b
LY		 1014
1015 trace_azx_suspend(chip);
1da177e4
LT		 1016 return 0;
1017}
1018
68cb2b55 1019static int azx_resume(struct device *dev)
1da177e4 1020{
68cb2b55
TI		 1021 struct pci_dev *pci = to_pci_dev(dev);
1022 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1023 struct azx *chip;
1024 struct hda_intel *hda;
a52ff34e 1025 struct hdac_bus *bus;
2d9772ef
TI		 1026
1027 if (!card)
1028 return 0;
1da177e4 1029
2d9772ef
TI		 1030 chip = card->private_data;
1031 hda = container_of(chip, struct hda_intel, chip);
a52ff34e 1032 bus = azx_bus(chip);
342e8449 1033 if (chip->disabled || hda->init_failed || !chip->running)
c5c21523
TI		 1034 return 0;
1035
a52ff34e
TI		 1036 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1037 snd_hdac_display_power(bus, true);
1038 if (hda->need_i915_power)
1039 snd_hdac_i915_set_bclk(bus);
a07187c9 1040 }
a52ff34e 1041
68e7fffc
TI		 1042 if (chip->msi)
1043 if (pci_enable_msi(pci) < 0)
1044 chip->msi = 0;
1045 if (azx_acquire_irq(chip, 1) < 0)
30b35399 1046 return -EIO;
cb53c626 1047 azx_init_pci(chip);
d804ad92 1048
0a673521 1049 hda_intel_init_chip(chip, true);
d804ad92 1050
a52ff34e
TI		 1051 /* power down again for link-controlled chips */
1052 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1053 !hda->need_i915_power)
1054 snd_hdac_display_power(bus, false);
1055
421a1252 1056 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
785d8c4b
LY		 1057
1058 trace_azx_resume(chip);
1da177e4
LT		 1059 return 0;
1060}
b8dfc462
ML		 1061#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
1062
3e6db33a
XZ		 1063#ifdef CONFIG_PM_SLEEP
1064/* put codec down to D3 at hibernation for Intel SKL+;
1065 * otherwise BIOS may still access the codec and screw up the driver
1066 */
3e6db33a
XZ		 1067static int azx_freeze_noirq(struct device *dev)
1068{
a4b4793f
TI		 1069 struct snd_card *card = dev_get_drvdata(dev);
1070 struct azx *chip = card->private_data;
3e6db33a
XZ		 1071 struct pci_dev *pci = to_pci_dev(dev);
1072
a4b4793f 1073 if (chip->driver_type == AZX_DRIVER_SKL)
3e6db33a
XZ		 1074 pci_set_power_state(pci, PCI_D3hot);
1075
1076 return 0;
1077}
1078
1079static int azx_thaw_noirq(struct device *dev)
1080{
a4b4793f
TI		 1081 struct snd_card *card = dev_get_drvdata(dev);
1082 struct azx *chip = card->private_data;
3e6db33a
XZ		 1083 struct pci_dev *pci = to_pci_dev(dev);
1084
a4b4793f 1085 if (chip->driver_type == AZX_DRIVER_SKL)
3e6db33a
XZ		 1086 pci_set_power_state(pci, PCI_D0);
1087
1088 return 0;
1089}
1090#endif /* CONFIG_PM_SLEEP */
1091
641d334b 1092#ifdef CONFIG_PM
b8dfc462
ML		 1093static int azx_runtime_suspend(struct device *dev)
1094{
1095 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1096 struct azx *chip;
1097 struct hda_intel *hda;
b8dfc462 1098
2d9772ef
TI		 1099 if (!card)
1100 return 0;
1101
1102 chip = card->private_data;
1103 hda = container_of(chip, struct hda_intel, chip);
1618e84a 1104 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1105 return 0;
1106
364aa716 1107 if (!azx_has_pm_runtime(chip))
246efa4a
DA		 1108 return 0;
1109
7d4f606c
WX		 1110 /* enable controller wake up event */
1111 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1112 STATESTS_INT_MASK);
1113
b8dfc462 1114 azx_stop_chip(chip);
873ce8ad 1115 azx_enter_link_reset(chip);
b8dfc462 1116 azx_clear_irq_pending(chip);
795614dd
ML		 1117 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
1118 && hda->need_i915_power)
98d8fc6c 1119 snd_hdac_display_power(azx_bus(chip), false);
e4d9e513 1120
785d8c4b 1121 trace_azx_runtime_suspend(chip);
b8dfc462
ML		 1122 return 0;
1123}
1124
1125static int azx_runtime_resume(struct device *dev)
1126{
1127 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1128 struct azx *chip;
1129 struct hda_intel *hda;
98d8fc6c 1130 struct hdac_bus *bus;
7d4f606c
WX		 1131 struct hda_codec *codec;
1132 int status;
b8dfc462 1133
2d9772ef
TI		 1134 if (!card)
1135 return 0;
1136
1137 chip = card->private_data;
1138 hda = container_of(chip, struct hda_intel, chip);
a52ff34e 1139 bus = azx_bus(chip);
1618e84a 1140 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1141 return 0;
1142
364aa716 1143 if (!azx_has_pm_runtime(chip))
246efa4a
DA		 1144 return 0;
1145
033ea349 1146 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
a52ff34e
TI		 1147 snd_hdac_display_power(bus, true);
1148 if (hda->need_i915_power)
bb03ed21 1149 snd_hdac_i915_set_bclk(bus);
a07187c9 1150 }
7d4f606c
WX		 1151
1152 /* Read STATESTS before controller reset */
1153 status = azx_readw(chip, STATESTS);
1154
b8dfc462 1155 azx_init_pci(chip);
0a673521 1156 hda_intel_init_chip(chip, true);
7d4f606c 1157
a41d1224
TI		 1158 if (status) {
1159 list_for_each_codec(codec, &chip->bus)
7d4f606c 1160 if (status & (1 << codec->addr))
2f35c630
TI		 1161 schedule_delayed_work(&codec->jackpoll_work,
1162 codec->jackpoll_interval);
7d4f606c
WX		 1163 }
1164
1165 /* disable controller Wake Up event*/
1166 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1167 ~STATESTS_INT_MASK);
1168
a52ff34e
TI		 1169 /* power down again for link-controlled chips */
1170 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1171 !hda->need_i915_power)
1172 snd_hdac_display_power(bus, false);
1173
785d8c4b 1174 trace_azx_runtime_resume(chip);
b8dfc462
ML		 1175 return 0;
1176}
6eb827d2
TI		 1177
1178static int azx_runtime_idle(struct device *dev)
1179{
1180 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1181 struct azx *chip;
1182 struct hda_intel *hda;
1183
1184 if (!card)
1185 return 0;
6eb827d2 1186
2d9772ef
TI		 1187 chip = card->private_data;
1188 hda = container_of(chip, struct hda_intel, chip);
1618e84a 1189 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1190 return 0;
1191
55ed9cd1 1192 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
342e8449 1193 azx_bus(chip)->codec_powered || !chip->running)
6eb827d2
TI		 1194 return -EBUSY;
1195
1196 return 0;
1197}
1198
b8dfc462
ML		 1199static const struct dev_pm_ops azx_pm = {
1200 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
3e6db33a
XZ		 1201#ifdef CONFIG_PM_SLEEP
1202 .freeze_noirq = azx_freeze_noirq,
1203 .thaw_noirq = azx_thaw_noirq,
1204#endif
6eb827d2 1205 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 1206};
1207
68cb2b55
TI		 1208#define AZX_PM_OPS &azx_pm
1209#else
68cb2b55 1210#define AZX_PM_OPS NULL
b8dfc462 1211#endif /* CONFIG_PM */
1da177e4
LT		 1212
1213
48c8b0eb 1214static int azx_probe_continue(struct azx *chip);
a82d51ed 1215
8393ec4a 1216#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 1217static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 1218
a82d51ed
TI		 1219static void azx_vs_set_state(struct pci_dev *pci,
1220 enum vga_switcheroo_state state)
1221{
1222 struct snd_card *card = pci_get_drvdata(pci);
1223 struct azx *chip = card->private_data;
9a34af4a 1224 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 1225 bool disabled;
1226
9a34af4a
TI		 1227 wait_for_completion(&hda->probe_wait);
1228 if (hda->init_failed)
a82d51ed
TI		 1229 return;
1230
1231 disabled = (state == VGA_SWITCHEROO_OFF);
1232 if (chip->disabled == disabled)
1233 return;
1234
a41d1224 1235 if (!hda->probe_continued) {
a82d51ed
TI		 1236 chip->disabled = disabled;
1237 if (!disabled) {
4e76a883
TI		 1238 dev_info(chip->card->dev,
1239 "Start delayed initialization\n");
5c90680e 1240 if (azx_probe_continue(chip) < 0) {
4e76a883 1241 dev_err(chip->card->dev, "initialization error\n");
9a34af4a 1242 hda->init_failed = true;
a82d51ed
TI		 1243 }
1244 }
1245 } else {
2b760d88 1246 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
4e76a883 1247 disabled ? "Disabling" : "Enabling");
a82d51ed 1248 if (disabled) {
8928756d
DR		 1249 pm_runtime_put_sync_suspend(card->dev);
1250 azx_suspend(card->dev);
2b760d88 1251 /* when we get suspended by vga_switcheroo we end up in D3cold,
246efa4a
DA		 1252 * however we have no ACPI handle, so pci/acpi can't put us there,
1253 * put ourselves there */
1254 pci->current_state = PCI_D3cold;
a82d51ed 1255 chip->disabled = true;
a41d1224 1256 if (snd_hda_lock_devices(&chip->bus))
4e76a883
TI		 1257 dev_warn(chip->card->dev,
1258 "Cannot lock devices!\n");
a82d51ed 1259 } else {
a41d1224 1260 snd_hda_unlock_devices(&chip->bus);
8928756d 1261 pm_runtime_get_noresume(card->dev);
a82d51ed 1262 chip->disabled = false;
8928756d 1263 azx_resume(card->dev);
a82d51ed
TI		 1264 }
1265 }
1266}
1267
1268static bool azx_vs_can_switch(struct pci_dev *pci)
1269{
1270 struct snd_card *card = pci_get_drvdata(pci);
1271 struct azx *chip = card->private_data;
9a34af4a 1272 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed 1273
9a34af4a
TI		 1274 wait_for_completion(&hda->probe_wait);
1275 if (hda->init_failed)
a82d51ed 1276 return false;
a41d1224 1277 if (chip->disabled || !hda->probe_continued)
a82d51ed 1278 return true;
a41d1224 1279 if (snd_hda_lock_devices(&chip->bus))
a82d51ed 1280 return false;
a41d1224 1281 snd_hda_unlock_devices(&chip->bus);
a82d51ed
TI		 1282 return true;
1283}
1284
e23e7a14 1285static void init_vga_switcheroo(struct azx *chip)
a82d51ed 1286{
9a34af4a 1287 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 1288 struct pci_dev *p = get_bound_vga(chip->pci);
1289 if (p) {
4e76a883 1290 dev_info(chip->card->dev,
2b760d88 1291 "Handle vga_switcheroo audio client\n");
9a34af4a 1292 hda->use_vga_switcheroo = 1;
a82d51ed
TI		 1293 pci_dev_put(p);
1294 }
1295}
1296
1297static const struct vga_switcheroo_client_ops azx_vs_ops = {
1298 .set_gpu_state = azx_vs_set_state,
1299 .can_switch = azx_vs_can_switch,
1300};
1301
e23e7a14 1302static int register_vga_switcheroo(struct azx *chip)
a82d51ed 1303{
9a34af4a 1304 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
128960a9
TI		 1305 int err;
1306
9a34af4a 1307 if (!hda->use_vga_switcheroo)
a82d51ed
TI		 1308 return 0;
1309 /* FIXME: currently only handling DIS controller
1310 * is there any machine with two switchable HDMI audio controllers?
1311 */
128960a9 1312 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
21b45676 1313 VGA_SWITCHEROO_DIS);
128960a9
TI		 1314 if (err < 0)
1315 return err;
9a34af4a 1316 hda->vga_switcheroo_registered = 1;
246efa4a
DA		 1317
1318 /* register as an optimus hdmi audio power domain */
8928756d 1319 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
9a34af4a 1320 &hda->hdmi_pm_domain);
128960a9 1321 return 0;
a82d51ed
TI		 1322}
1323#else
1324#define init_vga_switcheroo(chip) /* NOP */
1325#define register_vga_switcheroo(chip) 0
8393ec4a 1326#define check_hdmi_disabled(pci) false
a82d51ed
TI		 1327#endif /* SUPPORT_VGA_SWITCHER */
1328
1da177e4
LT		 1329/*
1330 * destructor
1331 */
a98f90fd 1332static int azx_free(struct azx *chip)
1da177e4 1333{
c67e2228 1334 struct pci_dev *pci = chip->pci;
a07187c9 1335 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a41d1224 1336 struct hdac_bus *bus = azx_bus(chip);
4ce107b9 1337
364aa716 1338 if (azx_has_pm_runtime(chip) && chip->running)
c67e2228
WX		 1339 pm_runtime_get_noresume(&pci->dev);
1340
65fcd41d
TI		 1341 azx_del_card_list(chip);
1342
9a34af4a
TI		 1343 hda->init_failed = 1; /* to be sure */
1344 complete_all(&hda->probe_wait);
f4c482a4 1345
9a34af4a 1346 if (use_vga_switcheroo(hda)) {
a41d1224
TI		 1347 if (chip->disabled && hda->probe_continued)
1348 snd_hda_unlock_devices(&chip->bus);
ab58d8cc 1349 if (hda->vga_switcheroo_registered) {
128960a9 1350 vga_switcheroo_unregister_client(chip->pci);
ab58d8cc
PW		 1351 vga_switcheroo_fini_domain_pm_ops(chip->card->dev);
1352 }
a82d51ed
TI		 1353 }
1354
a41d1224 1355 if (bus->chip_init) {
9ad593f6 1356 azx_clear_irq_pending(chip);
7833c3f8 1357 azx_stop_all_streams(chip);
cb53c626 1358 azx_stop_chip(chip);
1da177e4
LT		 1359 }
1360
a41d1224
TI		 1361 if (bus->irq >= 0)
1362 free_irq(bus->irq, (void*)chip);
68e7fffc 1363 if (chip->msi)
30b35399 1364 pci_disable_msi(chip->pci);
a41d1224 1365 iounmap(bus->remap_addr);
1da177e4 1366
67908994 1367 azx_free_stream_pages(chip);
a41d1224
TI		 1368 azx_free_streams(chip);
1369 snd_hdac_bus_exit(bus);
1370
a82d51ed
TI		 1371 if (chip->region_requested)
1372 pci_release_regions(chip->pci);
a41d1224 1373
1da177e4 1374 pci_disable_device(chip->pci);
4918cdab 1375#ifdef CONFIG_SND_HDA_PATCH_LOADER
f0acd28c 1376 release_firmware(chip->fw);
4918cdab 1377#endif
98d8fc6c 1378
99a2008d 1379 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
795614dd 1380 if (hda->need_i915_power)
98d8fc6c 1381 snd_hdac_display_power(bus, false);
99a2008d 1382 }
fcc88d91
TI		 1383 if (chip->driver_type == AZX_DRIVER_PCH ||
1384 (chip->driver_caps & AZX_DCAPS_I915_POWERWELL))
1385 snd_hdac_i915_exit(bus);
a07187c9 1386 kfree(hda);
1da177e4
LT		 1387
1388 return 0;
1389}
1390
a41d1224
TI		 1391static int azx_dev_disconnect(struct snd_device *device)
1392{
1393 struct azx *chip = device->device_data;
1394
1395 chip->bus.shutdown = 1;
1396 return 0;
1397}
1398
a98f90fd 1399static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 1400{
1401 return azx_free(device->device_data);
1402}
1403
8393ec4a 1404#ifdef SUPPORT_VGA_SWITCHEROO
9121947d 1405/*
2b760d88 1406 * Check of disabled HDMI controller by vga_switcheroo
9121947d 1407 */
e23e7a14 1408static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 1409{
1410 struct pci_dev *p;
1411
1412 /* check only discrete GPU */
1413 switch (pci->vendor) {
1414 case PCI_VENDOR_ID_ATI:
1415 case PCI_VENDOR_ID_AMD:
1416 case PCI_VENDOR_ID_NVIDIA:
1417 if (pci->devfn == 1) {
1418 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1419 pci->bus->number, 0);
1420 if (p) {
1421 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1422 return p;
1423 pci_dev_put(p);
1424 }
1425 }
1426 break;
1427 }
1428 return NULL;
1429}
1430
e23e7a14 1431static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 1432{
1433 bool vga_inactive = false;
1434 struct pci_dev *p = get_bound_vga(pci);
1435
1436 if (p) {
12b78a7f 1437 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 1438 vga_inactive = true;
1439 pci_dev_put(p);
1440 }
1441 return vga_inactive;
1442}
8393ec4a 1443#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 1444
3372a153
TI		 1445/*
1446 * white/black-listing for position_fix
1447 */
e23e7a14 1448static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 1449 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1450 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 1451 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 1452 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 1453 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 1454 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 1455 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 1456 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 1457 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 1458 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 1459 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 1460 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 1461 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 1462 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 1463 {}
1464};
1465
e23e7a14 1466static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 1467{
1468 const struct snd_pci_quirk *q;
1469
c673ba1c 1470 switch (fix) {
1dac6695 1471 case POS_FIX_AUTO:
c673ba1c
TI		 1472 case POS_FIX_LPIB:
1473 case POS_FIX_POSBUF:
4cb36310 1474 case POS_FIX_VIACOMBO:
a6f2fd55 1475 case POS_FIX_COMBO:
f87e7f25 1476 case POS_FIX_SKL:
c673ba1c
TI		 1477 return fix;
1478 }
1479
c673ba1c
TI		 1480 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1481 if (q) {
4e76a883
TI		 1482 dev_info(chip->card->dev,
1483 "position_fix set to %d for device %04x:%04x\n",
1484 q->value, q->subvendor, q->subdevice);
c673ba1c 1485 return q->value;
3372a153 1486 }
bdd9ef24
DH		 1487
1488 /* Check VIA/ATI HD Audio Controller exist */
26f05717 1489 if (chip->driver_type == AZX_DRIVER_VIA) {
4e76a883 1490 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
bdd9ef24 1491 return POS_FIX_VIACOMBO;
9477c58e
TI		 1492 }
1493 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
4e76a883 1494 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
50e3bbf9 1495 return POS_FIX_LPIB;
bdd9ef24 1496 }
a4b4793f 1497 if (chip->driver_type == AZX_DRIVER_SKL) {
f87e7f25
TI		 1498 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1499 return POS_FIX_SKL;
1500 }
c673ba1c 1501 return POS_FIX_AUTO;
3372a153
TI		 1502}
1503
b6050ef6
TI		 1504static void assign_position_fix(struct azx *chip, int fix)
1505{
1506 static azx_get_pos_callback_t callbacks[] = {
1507 [POS_FIX_AUTO] = NULL,
1508 [POS_FIX_LPIB] = azx_get_pos_lpib,
1509 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1510 [POS_FIX_VIACOMBO] = azx_via_get_position,
1511 [POS_FIX_COMBO] = azx_get_pos_lpib,
f87e7f25 1512 [POS_FIX_SKL] = azx_get_pos_skl,
b6050ef6
TI		 1513 };
1514
1515 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1516
1517 /* combo mode uses LPIB only for playback */
1518 if (fix == POS_FIX_COMBO)
1519 chip->get_position[1] = NULL;
1520
f87e7f25 1521 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
b6050ef6
TI		 1522 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1523 chip->get_delay[0] = chip->get_delay[1] =
1524 azx_get_delay_from_lpib;
1525 }
1526
1527}
1528
669ba27a
TI		 1529/*
1530 * black-lists for probe_mask
1531 */
e23e7a14 1532static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 1533 /* Thinkpad often breaks the controller communication when accessing
1534 * to the non-working (or non-existing) modem codec slot.
1535 */
1536 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1537 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1538 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 1539 /* broken BIOS */
1540 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 1541 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1542 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 1543 /* forced codec slots */
93574844 1544 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 1545 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 1546 /* WinFast VP200 H (Teradici) user reported broken communication */
1547 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 1548 {}
1549};
1550
f1eaaeec
TI		 1551#define AZX_FORCE_CODEC_MASK 0x100
1552
e23e7a14 1553static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 1554{
1555 const struct snd_pci_quirk *q;
1556
f1eaaeec
TI		 1557 chip->codec_probe_mask = probe_mask[dev];
1558 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 1559 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1560 if (q) {
4e76a883
TI		 1561 dev_info(chip->card->dev,
1562 "probe_mask set to 0x%x for device %04x:%04x\n",
1563 q->value, q->subvendor, q->subdevice);
f1eaaeec 1564 chip->codec_probe_mask = q->value;
669ba27a
TI		 1565 }
1566 }
f1eaaeec
TI		 1567
1568 /* check forced option */
1569 if (chip->codec_probe_mask != -1 &&
1570 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
a41d1224 1571 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
4e76a883 1572 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
a41d1224 1573 (int)azx_bus(chip)->codec_mask);
f1eaaeec 1574 }
669ba27a
TI		 1575}
1576
4d8e22e0 1577/*
71623855 1578 * white/black-list for enable_msi
4d8e22e0 1579 */
e23e7a14 1580static struct snd_pci_quirk msi_black_list[] = {
693e0cb0
DH		 1581 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1582 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1583 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1584 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 1585 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 1586 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 1587 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 1588 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 1589 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 1590 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 1591 {}
1592};
1593
e23e7a14 1594static void check_msi(struct azx *chip)
4d8e22e0
TI		 1595{
1596 const struct snd_pci_quirk *q;
1597
71623855
TI		 1598 if (enable_msi >= 0) {
1599 chip->msi = !!enable_msi;
4d8e22e0 1600 return;
71623855
TI		 1601 }
1602 chip->msi = 1; /* enable MSI as default */
1603 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0 1604 if (q) {
4e76a883
TI		 1605 dev_info(chip->card->dev,
1606 "msi for device %04x:%04x set to %d\n",
1607 q->subvendor, q->subdevice, q->value);
4d8e22e0 1608 chip->msi = q->value;
80c43ed7
TI		 1609 return;
1610 }
1611
1612 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e 1613 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
4e76a883 1614 dev_info(chip->card->dev, "Disabling MSI\n");
80c43ed7 1615 chip->msi = 0;
4d8e22e0
TI		 1616 }
1617}
1618
a1585d76 1619/* check the snoop mode availability */
e23e7a14 1620static void azx_check_snoop_available(struct azx *chip)
a1585d76 1621{
7c732015 1622 int snoop = hda_snoop;
a1585d76 1623
7c732015
TI		 1624 if (snoop >= 0) {
1625 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1626 snoop ? "snoop" : "non-snoop");
1627 chip->snoop = snoop;
1628 return;
1629 }
1630
1631 snoop = true;
37e661ee
TI		 1632 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1633 chip->driver_type == AZX_DRIVER_VIA) {
a1585d76
TI		 1634 /* force to non-snoop mode for a new VIA controller
1635 * when BIOS is set
1636 */
7c732015
TI		 1637 u8 val;
1638 pci_read_config_byte(chip->pci, 0x42, &val);
1639 if (!(val & 0x80) && chip->pci->revision == 0x30)
1640 snoop = false;
a1585d76
TI		 1641 }
1642
37e661ee
TI		 1643 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1644 snoop = false;
1645
7c732015
TI		 1646 chip->snoop = snoop;
1647 if (!snoop)
1648 dev_info(chip->card->dev, "Force to non-snoop mode\n");
a1585d76 1649}
669ba27a 1650
99a2008d
WX		 1651static void azx_probe_work(struct work_struct *work)
1652{
9a34af4a
TI		 1653 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1654 azx_probe_continue(&hda->chip);
99a2008d 1655}
99a2008d 1656
4f0189be
TI		 1657static int default_bdl_pos_adj(struct azx *chip)
1658{
2cf721db
TI		 1659 /* some exceptions: Atoms seem problematic with value 1 */
1660 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1661 switch (chip->pci->device) {
1662 case 0x0f04: /* Baytrail */
1663 case 0x2284: /* Braswell */
1664 return 32;
1665 }
1666 }
1667
4f0189be
TI		 1668 switch (chip->driver_type) {
1669 case AZX_DRIVER_ICH:
1670 case AZX_DRIVER_PCH:
1671 return 1;
1672 default:
1673 return 32;
1674 }
1675}
1676
1da177e4
LT		 1677/*
1678 * constructor
1679 */
a43ff5ba
TI		 1680static const struct hdac_io_ops pci_hda_io_ops;
1681static const struct hda_controller_ops pci_hda_ops;
1682
e23e7a14
BP		 1683static int azx_create(struct snd_card *card, struct pci_dev *pci,
1684 int dev, unsigned int driver_caps,
1685 struct azx **rchip)
1da177e4 1686{
a98f90fd 1687 static struct snd_device_ops ops = {
a41d1224 1688 .dev_disconnect = azx_dev_disconnect,
1da177e4
LT		 1689 .dev_free = azx_dev_free,
1690 };
a07187c9 1691 struct hda_intel *hda;
a82d51ed
TI		 1692 struct azx *chip;
1693 int err;
1da177e4
LT		 1694
1695 *rchip = NULL;
bcd72003 1696
927fc866
PM		 1697 err = pci_enable_device(pci);
1698 if (err < 0)
1da177e4
LT		 1699 return err;
1700
a07187c9
ML		 1701 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1702 if (!hda) {
1da177e4
LT		 1703 pci_disable_device(pci);
1704 return -ENOMEM;
1705 }
1706
a07187c9 1707 chip = &hda->chip;
62932df8 1708 mutex_init(&chip->open_mutex);
1da177e4
LT		 1709 chip->card = card;
1710 chip->pci = pci;
a43ff5ba 1711 chip->ops = &pci_hda_ops;
9477c58e
TI		 1712 chip->driver_caps = driver_caps;
1713 chip->driver_type = driver_caps & 0xff;
4d8e22e0 1714 check_msi(chip);
555e219f 1715 chip->dev_index = dev;
749ee287 1716 chip->jackpoll_ms = jackpoll_ms;
01b65bfb 1717 INIT_LIST_HEAD(&chip->pcm_list);
9a34af4a
TI		 1718 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1719 INIT_LIST_HEAD(&hda->list);
a82d51ed 1720 init_vga_switcheroo(chip);
9a34af4a 1721 init_completion(&hda->probe_wait);
1da177e4 1722
b6050ef6 1723 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
a6f2fd55 1724
5aba4f8e 1725 check_probe_mask(chip, dev);
3372a153 1726
41438f13
TI		 1727 if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1728 chip->fallback_to_single_cmd = 1;
1729 else /* explicitly set to single_cmd or not */
1730 chip->single_cmd = single_cmd;
1731
a1585d76 1732 azx_check_snoop_available(chip);
c74db86b 1733
4f0189be
TI		 1734 if (bdl_pos_adj[dev] < 0)
1735 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1736 else
1737 chip->bdl_pos_adj = bdl_pos_adj[dev];
5c0d7bc1 1738
a41d1224
TI		 1739 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1740 if (err < 0) {
1741 kfree(hda);
1742 pci_disable_device(pci);
1743 return err;
1744 }
1745
7d9a1808
TI		 1746 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1747 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1748 chip->bus.needs_damn_long_delay = 1;
1749 }
1750
a82d51ed
TI		 1751 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1752 if (err < 0) {
4e76a883 1753 dev_err(card->dev, "Error creating device [card]!\n");
a82d51ed
TI		 1754 azx_free(chip);
1755 return err;
1756 }
1757
99a2008d 1758 /* continue probing in work context as may trigger request module */
9a34af4a 1759 INIT_WORK(&hda->probe_work, azx_probe_work);
99a2008d 1760
a82d51ed 1761 *rchip = chip;
99a2008d 1762
a82d51ed
TI		 1763 return 0;
1764}
1765
48c8b0eb 1766static int azx_first_init(struct azx *chip)
a82d51ed
TI		 1767{
1768 int dev = chip->dev_index;
1769 struct pci_dev *pci = chip->pci;
1770 struct snd_card *card = chip->card;
a41d1224 1771 struct hdac_bus *bus = azx_bus(chip);
67908994 1772 int err;
a82d51ed 1773 unsigned short gcap;
413cbf46 1774 unsigned int dma_bits = 64;
a82d51ed 1775
07e4ca50
TI		 1776#if BITS_PER_LONG != 64
1777 /* Fix up base address on ULI M5461 */
1778 if (chip->driver_type == AZX_DRIVER_ULI) {
1779 u16 tmp3;
1780 pci_read_config_word(pci, 0x40, &tmp3);
1781 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1782 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1783 }
1784#endif
1785
927fc866 1786 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 1787 if (err < 0)
1da177e4 1788 return err;
a82d51ed 1789 chip->region_requested = 1;
1da177e4 1790
a41d1224
TI		 1791 bus->addr = pci_resource_start(pci, 0);
1792 bus->remap_addr = pci_ioremap_bar(pci, 0);
1793 if (bus->remap_addr == NULL) {
4e76a883 1794 dev_err(card->dev, "ioremap error\n");
a82d51ed 1795 return -ENXIO;
1da177e4
LT		 1796 }
1797
a4b4793f 1798 if (chip->driver_type == AZX_DRIVER_SKL)
50279d9b
GS		 1799 snd_hdac_bus_parse_capabilities(bus);
1800
1801 /*
1802 * Some Intel CPUs has always running timer (ART) feature and
1803 * controller may have Global time sync reporting capability, so
1804 * check both of these before declaring synchronized time reporting
1805 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1806 */
1807 chip->gts_present = false;
1808
1809#ifdef CONFIG_X86
1810 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1811 chip->gts_present = true;
1812#endif
1813
db79afa1
BH		 1814 if (chip->msi) {
1815 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1816 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1817 pci->no_64bit_msi = true;
1818 }
68e7fffc
TI		 1819 if (pci_enable_msi(pci) < 0)
1820 chip->msi = 0;
db79afa1 1821 }
7376d013 1822
a82d51ed
TI		 1823 if (azx_acquire_irq(chip, 0) < 0)
1824 return -EBUSY;
1da177e4
LT		 1825
1826 pci_set_master(pci);
a41d1224 1827 synchronize_irq(bus->irq);
1da177e4 1828
bcd72003 1829 gcap = azx_readw(chip, GCAP);
4e76a883 1830 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
bcd72003 1831
413cbf46
TI		 1832 /* AMD devices support 40 or 48bit DMA, take the safe one */
1833 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1834 dma_bits = 40;
1835
dc4c2e6b 1836 /* disable SB600 64bit support for safety */
9477c58e 1837 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b 1838 struct pci_dev *p_smbus;
413cbf46 1839 dma_bits = 40;
dc4c2e6b
AB		 1840 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1841 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1842 NULL);
1843 if (p_smbus) {
1844 if (p_smbus->revision < 0x30)
fb1d8ac2 1845 gcap &= ~AZX_GCAP_64OK;
dc4c2e6b
AB		 1846 pci_dev_put(p_smbus);
1847 }
1848 }
09240cf4 1849
3ab7511e
AB		 1850 /* NVidia hardware normally only supports up to 40 bits of DMA */
1851 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1852 dma_bits = 40;
1853
9477c58e
TI		 1854 /* disable 64bit DMA address on some devices */
1855 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
4e76a883 1856 dev_dbg(card->dev, "Disabling 64bit DMA\n");
fb1d8ac2 1857 gcap &= ~AZX_GCAP_64OK;
9477c58e 1858 }
396087ea 1859
2ae66c26 1860 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 1861 if (align_buffer_size >= 0)
1862 chip->align_buffer_size = !!align_buffer_size;
1863 else {
103884a3 1864 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
7bfe059e 1865 chip->align_buffer_size = 0;
7bfe059e
TI		 1866 else
1867 chip->align_buffer_size = 1;
1868 }
2ae66c26 1869
cf7aaca8 1870 /* allow 64bit DMA address if supported by H/W */
413cbf46
TI		 1871 if (!(gcap & AZX_GCAP_64OK))
1872 dma_bits = 32;
412b979c
QL		 1873 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1874 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
413cbf46 1875 } else {
412b979c
QL		 1876 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1877 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
09240cf4 1878 }
cf7aaca8 1879
8b6ed8e7
TI		 1880 /* read number of streams from GCAP register instead of using
1881 * hardcoded value
1882 */
1883 chip->capture_streams = (gcap >> 8) & 0x0f;
1884 chip->playback_streams = (gcap >> 12) & 0x0f;
1885 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 1886 /* gcap didn't give any info, switching to old method */
1887
1888 switch (chip->driver_type) {
1889 case AZX_DRIVER_ULI:
1890 chip->playback_streams = ULI_NUM_PLAYBACK;
1891 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 1892 break;
1893 case AZX_DRIVER_ATIHDMI:
1815b34a 1894 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 1895 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1896 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 1897 break;
c4da29ca 1898 case AZX_DRIVER_GENERIC:
bcd72003
TD		 1899 default:
1900 chip->playback_streams = ICH6_NUM_PLAYBACK;
1901 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 1902 break;
1903 }
07e4ca50 1904 }
8b6ed8e7
TI		 1905 chip->capture_index_offset = 0;
1906 chip->playback_index_offset = chip->capture_streams;
07e4ca50 1907 chip->num_streams = chip->playback_streams + chip->capture_streams;
07e4ca50 1908
df56c3db
JK		 1909 /* sanity check for the SDxCTL.STRM field overflow */
1910 if (chip->num_streams > 15 &&
1911 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1912 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1913 "forcing separate stream tags", chip->num_streams);
1914 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1915 }
1916
a41d1224
TI		 1917 /* initialize streams */
1918 err = azx_init_streams(chip);
81740861 1919 if (err < 0)
a82d51ed 1920 return err;
1da177e4 1921
a41d1224
TI		 1922 err = azx_alloc_stream_pages(chip);
1923 if (err < 0)
1924 return err;
1da177e4
LT		 1925
1926 /* initialize chip */
cb53c626 1927 azx_init_pci(chip);
e4d9e513 1928
bb03ed21
TI		 1929 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1930 snd_hdac_i915_set_bclk(bus);
e4d9e513 1931
0a673521 1932 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 1933
1934 /* codec detection */
a41d1224 1935 if (!azx_bus(chip)->codec_mask) {
4e76a883 1936 dev_err(card->dev, "no codecs found!\n");
a82d51ed 1937 return -ENODEV;
1da177e4
LT		 1938 }
1939
07e4ca50 1940 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 1941 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1942 sizeof(card->shortname));
1943 snprintf(card->longname, sizeof(card->longname),
1944 "%s at 0x%lx irq %i",
a41d1224 1945 card->shortname, bus->addr, bus->irq);
07e4ca50 1946
1da177e4 1947 return 0;
1da177e4
LT		 1948}
1949
97c6a3d1 1950#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 1951/* callback from request_firmware_nowait() */
1952static void azx_firmware_cb(const struct firmware *fw, void *context)
1953{
1954 struct snd_card *card = context;
1955 struct azx *chip = card->private_data;
1956 struct pci_dev *pci = chip->pci;
1957
1958 if (!fw) {
4e76a883 1959 dev_err(card->dev, "Cannot load firmware, aborting\n");
5cb543db
TI		 1960 goto error;
1961 }
1962
1963 chip->fw = fw;
1964 if (!chip->disabled) {
1965 /* continue probing */
1966 if (azx_probe_continue(chip))
1967 goto error;
1968 }
1969 return; /* OK */
1970
1971 error:
1972 snd_card_free(card);
1973 pci_set_drvdata(pci, NULL);
1974}
97c6a3d1 1975#endif
5cb543db 1976
40830813
DR		 1977/*
1978 * HDA controller ops.
1979 */
1980
1981/* PCI register access. */
db291e36 1982static void pci_azx_writel(u32 value, u32 __iomem *addr)
40830813
DR		 1983{
1984 writel(value, addr);
1985}
1986
db291e36 1987static u32 pci_azx_readl(u32 __iomem *addr)
40830813
DR		 1988{
1989 return readl(addr);
1990}
1991
db291e36 1992static void pci_azx_writew(u16 value, u16 __iomem *addr)
40830813
DR		 1993{
1994 writew(value, addr);
1995}
1996
db291e36 1997static u16 pci_azx_readw(u16 __iomem *addr)
40830813
DR		 1998{
1999 return readw(addr);
2000}
2001
db291e36 2002static void pci_azx_writeb(u8 value, u8 __iomem *addr)
40830813
DR		 2003{
2004 writeb(value, addr);
2005}
2006
db291e36 2007static u8 pci_azx_readb(u8 __iomem *addr)
40830813
DR		 2008{
2009 return readb(addr);
2010}
2011
f46ea609
DR		 2012static int disable_msi_reset_irq(struct azx *chip)
2013{
a41d1224 2014 struct hdac_bus *bus = azx_bus(chip);
f46ea609
DR		 2015 int err;
2016
a41d1224
TI		 2017 free_irq(bus->irq, chip);
2018 bus->irq = -1;
f46ea609
DR		 2019 pci_disable_msi(chip->pci);
2020 chip->msi = 0;
2021 err = azx_acquire_irq(chip, 1);
2022 if (err < 0)
2023 return err;
2024
2025 return 0;
2026}
2027
b419b35b 2028/* DMA page allocation helpers. */
a43ff5ba 2029static int dma_alloc_pages(struct hdac_bus *bus,
b419b35b
DR		 2030 int type,
2031 size_t size,
2032 struct snd_dma_buffer *buf)
2033{
a41d1224 2034 struct azx *chip = bus_to_azx(bus);
b419b35b
DR		 2035 int err;
2036
2037 err = snd_dma_alloc_pages(type,
a43ff5ba 2038 bus->dev,
b419b35b
DR		 2039 size, buf);
2040 if (err < 0)
2041 return err;
2042 mark_pages_wc(chip, buf, true);
2043 return 0;
2044}
2045
a43ff5ba 2046static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
b419b35b 2047{
a41d1224 2048 struct azx *chip = bus_to_azx(bus);
a43ff5ba 2049
b419b35b
DR		 2050 mark_pages_wc(chip, buf, false);
2051 snd_dma_free_pages(buf);
2052}
2053
2054static int substream_alloc_pages(struct azx *chip,
2055 struct snd_pcm_substream *substream,
2056 size_t size)
2057{
2058 struct azx_dev *azx_dev = get_azx_dev(substream);
2059 int ret;
2060
2061 mark_runtime_wc(chip, azx_dev, substream, false);
b419b35b
DR		 2062 ret = snd_pcm_lib_malloc_pages(substream, size);
2063 if (ret < 0)
2064 return ret;
2065 mark_runtime_wc(chip, azx_dev, substream, true);
2066 return 0;
2067}
2068
2069static int substream_free_pages(struct azx *chip,
2070 struct snd_pcm_substream *substream)
2071{
2072 struct azx_dev *azx_dev = get_azx_dev(substream);
2073 mark_runtime_wc(chip, azx_dev, substream, false);
2074 return snd_pcm_lib_free_pages(substream);
2075}
2076
8769b278
DR		 2077static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2078 struct vm_area_struct *area)
2079{
2080#ifdef CONFIG_X86
2081 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2082 struct azx *chip = apcm->chip;
3b70bdba 2083 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
8769b278
DR		 2084 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2085#endif
2086}
2087
a43ff5ba 2088static const struct hdac_io_ops pci_hda_io_ops = {
778bde6f
DR		 2089 .reg_writel = pci_azx_writel,
2090 .reg_readl = pci_azx_readl,
2091 .reg_writew = pci_azx_writew,
2092 .reg_readw = pci_azx_readw,
2093 .reg_writeb = pci_azx_writeb,
2094 .reg_readb = pci_azx_readb,
b419b35b
DR		 2095 .dma_alloc_pages = dma_alloc_pages,
2096 .dma_free_pages = dma_free_pages,
a43ff5ba
TI		 2097};
2098
2099static const struct hda_controller_ops pci_hda_ops = {
2100 .disable_msi_reset_irq = disable_msi_reset_irq,
b419b35b
DR		 2101 .substream_alloc_pages = substream_alloc_pages,
2102 .substream_free_pages = substream_free_pages,
8769b278 2103 .pcm_mmap_prepare = pcm_mmap_prepare,
7ca954a8 2104 .position_check = azx_position_check,
17eccb27 2105 .link_power = azx_intel_link_power,
40830813
DR		 2106};
2107
e23e7a14
BP		 2108static int azx_probe(struct pci_dev *pci,
2109 const struct pci_device_id *pci_id)
1da177e4 2110{
5aba4f8e 2111 static int dev;
a98f90fd 2112 struct snd_card *card;
9a34af4a 2113 struct hda_intel *hda;
a98f90fd 2114 struct azx *chip;
aad730d0 2115 bool schedule_probe;
927fc866 2116 int err;
1da177e4 2117
5aba4f8e
TI		 2118 if (dev >= SNDRV_CARDS)
2119 return -ENODEV;
2120 if (!enable[dev]) {
2121 dev++;
2122 return -ENOENT;
2123 }
2124
60c5772b
TI		 2125 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2126 0, &card);
e58de7ba 2127 if (err < 0) {
4e76a883 2128 dev_err(&pci->dev, "Error creating card!\n");
e58de7ba 2129 return err;
1da177e4
LT		 2130 }
2131
a43ff5ba 2132 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 2133 if (err < 0)
2134 goto out_free;
421a1252 2135 card->private_data = chip;
9a34af4a 2136 hda = container_of(chip, struct hda_intel, chip);
f4c482a4
TI		 2137
2138 pci_set_drvdata(pci, card);
2139
2140 err = register_vga_switcheroo(chip);
2141 if (err < 0) {
2b760d88 2142 dev_err(card->dev, "Error registering vga_switcheroo client\n");
f4c482a4
TI		 2143 goto out_free;
2144 }
2145
2146 if (check_hdmi_disabled(pci)) {
4e76a883
TI		 2147 dev_info(card->dev, "VGA controller is disabled\n");
2148 dev_info(card->dev, "Delaying initialization\n");
f4c482a4
TI		 2149 chip->disabled = true;
2150 }
2151
aad730d0 2152 schedule_probe = !chip->disabled;
1da177e4 2153
4918cdab
TI		 2154#ifdef CONFIG_SND_HDA_PATCH_LOADER
2155 if (patch[dev] && *patch[dev]) {
4e76a883
TI		 2156 dev_info(card->dev, "Applying patch firmware '%s'\n",
2157 patch[dev]);
5cb543db
TI		 2158 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2159 &pci->dev, GFP_KERNEL, card,
2160 azx_firmware_cb);
4918cdab
TI		 2161 if (err < 0)
2162 goto out_free;
aad730d0 2163 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 2164 }
2165#endif /* CONFIG_SND_HDA_PATCH_LOADER */
2166
aad730d0 2167#ifndef CONFIG_SND_HDA_I915
6ee8eeb4
TI		 2168 if (CONTROLLER_IN_GPU(pci))
2169 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
99a2008d 2170#endif
99a2008d 2171
aad730d0 2172 if (schedule_probe)
9a34af4a 2173 schedule_work(&hda->probe_work);
a82d51ed 2174
a82d51ed 2175 dev++;
88d071fc 2176 if (chip->disabled)
9a34af4a 2177 complete_all(&hda->probe_wait);
a82d51ed
TI		 2178 return 0;
2179
2180out_free:
2181 snd_card_free(card);
2182 return err;
2183}
2184
e62a42ae
DR		 2185/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2186static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2187 [AZX_DRIVER_NVIDIA] = 8,
2188 [AZX_DRIVER_TERA] = 1,
2189};
2190
48c8b0eb 2191static int azx_probe_continue(struct azx *chip)
a82d51ed 2192{
9a34af4a 2193 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
98d8fc6c 2194 struct hdac_bus *bus = azx_bus(chip);
c67e2228 2195 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 2196 int dev = chip->dev_index;
2197 int err;
2198
a41d1224 2199 hda->probe_continued = 1;
795614dd 2200
fcc88d91
TI		 2201 /* bind with i915 if needed */
2202 if (chip->driver_type == AZX_DRIVER_PCH ||
2203 (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)) {
98d8fc6c 2204 err = snd_hdac_i915_init(bus);
535115b5
TI		 2205 if (err < 0) {
2206 /* if the controller is bound only with HDMI/DP
2207 * (for HSW and BDW), we need to abort the probe;
2208 * for other chips, still continue probing as other
2209 * codecs can be on the same link.
2210 */
bed2e98e
TI		 2211 if (CONTROLLER_IN_GPU(pci)) {
2212 dev_err(chip->card->dev,
2213 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
535115b5 2214 goto out_free;
fcc88d91
TI		 2215 } else {
2216 /* don't bother any longer */
2217 chip->driver_caps &= ~AZX_DCAPS_I915_POWERWELL;
2218 }
535115b5 2219 }
fcc88d91
TI		 2220 }
2221
2222 /* Request display power well for the HDA controller or codec. For
2223 * Haswell/Broadwell, both the display HDA controller and codec need
2224 * this power. For other platforms, like Baytrail/Braswell, only the
2225 * display codec needs the power and it can be released after probe.
2226 */
2227 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
2228 /* HSW/BDW controllers need this power */
2229 if (CONTROLLER_IN_GPU(pci))
2230 hda->need_i915_power = 1;
795614dd 2231
98d8fc6c 2232 err = snd_hdac_display_power(bus, true);
74b0c2d7
TI		 2233 if (err < 0) {
2234 dev_err(chip->card->dev,
2235 "Cannot turn on display power on i915\n");
795614dd 2236 goto i915_power_fail;
74b0c2d7 2237 }
99a2008d
WX		 2238 }
2239
5c90680e
TI		 2240 err = azx_first_init(chip);
2241 if (err < 0)
2242 goto out_free;
2243
2dca0bba
JK		 2244#ifdef CONFIG_SND_HDA_INPUT_BEEP
2245 chip->beep_mode = beep_mode[dev];
2246#endif
2247
1da177e4 2248 /* create codec instances */
96d2bd6e 2249 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
41dda0fd
WF		 2250 if (err < 0)
2251 goto out_free;
96d2bd6e 2252
4ea6fbc8 2253#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab 2254 if (chip->fw) {
a41d1224 2255 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
4918cdab 2256 chip->fw->data);
4ea6fbc8
TI		 2257 if (err < 0)
2258 goto out_free;
e39ae856 2259#ifndef CONFIG_PM
4918cdab
TI		 2260 release_firmware(chip->fw); /* no longer needed */
2261 chip->fw = NULL;
e39ae856 2262#endif
4ea6fbc8
TI		 2263 }
2264#endif
10e77dda 2265 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 2266 err = azx_codec_configure(chip);
2267 if (err < 0)
2268 goto out_free;
2269 }
1da177e4 2270
a82d51ed 2271 err = snd_card_register(chip->card);
41dda0fd
WF		 2272 if (err < 0)
2273 goto out_free;
1da177e4 2274
cb53c626 2275 chip->running = 1;
65fcd41d 2276 azx_add_card_list(chip);
a41d1224 2277 snd_hda_set_power_save(&chip->bus, power_save * 1000);
364aa716 2278 if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
30ff5957 2279 pm_runtime_put_autosuspend(&pci->dev);
1da177e4 2280
41dda0fd 2281out_free:
795614dd
ML		 2282 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
2283 && !hda->need_i915_power)
98d8fc6c 2284 snd_hdac_display_power(bus, false);
795614dd
ML		 2285
2286i915_power_fail:
88d071fc 2287 if (err < 0)
9a34af4a
TI		 2288 hda->init_failed = 1;
2289 complete_all(&hda->probe_wait);
41dda0fd 2290 return err;
1da177e4
LT		 2291}
2292
e23e7a14 2293static void azx_remove(struct pci_dev *pci)
1da177e4 2294{
9121947d 2295 struct snd_card *card = pci_get_drvdata(pci);
991f86d7
TI		 2296 struct azx *chip;
2297 struct hda_intel *hda;
2298
2299 if (card) {
0b8c8219 2300 /* cancel the pending probing work */
991f86d7
TI		 2301 chip = card->private_data;
2302 hda = container_of(chip, struct hda_intel, chip);
ab949d51
TI		 2303 /* FIXME: below is an ugly workaround.
2304 * Both device_release_driver() and driver_probe_device()
2305 * take *both* the device's and its parent's lock before
2306 * calling the remove() and probe() callbacks. The codec
2307 * probe takes the locks of both the codec itself and its
2308 * parent, i.e. the PCI controller dev. Meanwhile, when
2309 * the PCI controller is unbound, it takes its lock, too
2310 * ==> ouch, a deadlock!
2311 * As a workaround, we unlock temporarily here the controller
2312 * device during cancel_work_sync() call.
2313 */
2314 device_unlock(&pci->dev);
0b8c8219 2315 cancel_work_sync(&hda->probe_work);
ab949d51 2316 device_lock(&pci->dev);
b8dfc462 2317
9121947d 2318 snd_card_free(card);
991f86d7 2319 }
1da177e4
LT		 2320}
2321
b2a0bafa
TI		 2322static void azx_shutdown(struct pci_dev *pci)
2323{
2324 struct snd_card *card = pci_get_drvdata(pci);
2325 struct azx *chip;
2326
2327 if (!card)
2328 return;
2329 chip = card->private_data;
2330 if (chip && chip->running)
2331 azx_stop_chip(chip);
2332}
2333
1da177e4 2334/* PCI IDs */
6f51f6cf 2335static const struct pci_device_id azx_ids[] = {
d2f2fcd2 2336 /* CPT */
9477c58e 2337 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 2338 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 2339 /* PBG */
9477c58e 2340 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 2341 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 2342 /* Panther Point */
9477c58e 2343 { PCI_DEVICE(0x8086, 0x1e20),
de5d0ad5 2344 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
8bc039a1
SH		 2345 /* Lynx Point */
2346 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 2347 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
77f07800
TI		 2348 /* 9 Series */
2349 { PCI_DEVICE(0x8086, 0x8ca0),
2350 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 2351 /* Wellsburg */
2352 { PCI_DEVICE(0x8086, 0x8d20),
2353 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2354 { PCI_DEVICE(0x8086, 0x8d21),
2355 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
5cf92c8b
AY		 2356 /* Lewisburg */
2357 { PCI_DEVICE(0x8086, 0xa1f0),
e7480b34 2358 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
5cf92c8b 2359 { PCI_DEVICE(0x8086, 0xa270),
e7480b34 2360 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
144dad99
JR		 2361 /* Lynx Point-LP */
2362 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 2363 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 2364 /* Lynx Point-LP */
2365 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 2366 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4eeca499
JR		 2367 /* Wildcat Point-LP */
2368 { PCI_DEVICE(0x8086, 0x9ca0),
2369 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
c8b00fd2
JR		 2370 /* Sunrise Point */
2371 { PCI_DEVICE(0x8086, 0xa170),
a4b4793f 2372 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
b4565913
DR		 2373 /* Sunrise Point-LP */
2374 { PCI_DEVICE(0x8086, 0x9d70),
a4b4793f 2375 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
35639a0e
VK		 2376 /* Kabylake */
2377 { PCI_DEVICE(0x8086, 0xa171),
a4b4793f 2378 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
35639a0e
VK		 2379 /* Kabylake-LP */
2380 { PCI_DEVICE(0x8086, 0x9d71),
a4b4793f 2381 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
6858107e
VK		 2382 /* Kabylake-H */
2383 { PCI_DEVICE(0x8086, 0xa2f0),
a4b4793f 2384 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
e79b0006
MD		 2385 /* Coffelake */
2386 { PCI_DEVICE(0x8086, 0xa348),
a4b4793f 2387 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
c87693da
LH		 2388 /* Broxton-P(Apollolake) */
2389 { PCI_DEVICE(0x8086, 0x5a98),
a4b4793f 2390 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
9859a971
LH		 2391 /* Broxton-T */
2392 { PCI_DEVICE(0x8086, 0x1a98),
a4b4793f 2393 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
44b46d73
VK		 2394 /* Gemini-Lake */
2395 { PCI_DEVICE(0x8086, 0x3198),
a4b4793f 2396 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
e926f2c8 2397 /* Haswell */
4a7c516b 2398 { PCI_DEVICE(0x8086, 0x0a0c),
fab1285a 2399 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
e926f2c8 2400 { PCI_DEVICE(0x8086, 0x0c0c),
fab1285a 2401 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
d279fae8 2402 { PCI_DEVICE(0x8086, 0x0d0c),
fab1285a 2403 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
862d7618
ML		 2404 /* Broadwell */
2405 { PCI_DEVICE(0x8086, 0x160c),
54a0405d 2406 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
99df18b3
PLB		 2407 /* 5 Series/3400 */
2408 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 2409 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 2410 /* Poulsbo */
9477c58e 2411 { PCI_DEVICE(0x8086, 0x811b),
6603249d 2412 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
f748abcc 2413 /* Oaktrail */
09904b95 2414 { PCI_DEVICE(0x8086, 0x080a),
6603249d 2415 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
e44007e0
CCE		 2416 /* BayTrail */
2417 { PCI_DEVICE(0x8086, 0x0f04),
40cc2392 2418 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
f31b2ffc
LY		 2419 /* Braswell */
2420 { PCI_DEVICE(0x8086, 0x2284),
2d846c74 2421 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
b42b4afb 2422 /* ICH6 */
8b0bd226 2423 { PCI_DEVICE(0x8086, 0x2668),
b42b4afb
TI		 2424 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2425 /* ICH7 */
8b0bd226 2426 { PCI_DEVICE(0x8086, 0x27d8),
b42b4afb
TI		 2427 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2428 /* ESB2 */
8b0bd226 2429 { PCI_DEVICE(0x8086, 0x269a),
b42b4afb
TI		 2430 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2431 /* ICH8 */
8b0bd226 2432 { PCI_DEVICE(0x8086, 0x284b),
b42b4afb
TI		 2433 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2434 /* ICH9 */
8b0bd226 2435 { PCI_DEVICE(0x8086, 0x293e),
b42b4afb
TI		 2436 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2437 /* ICH9 */
8b0bd226 2438 { PCI_DEVICE(0x8086, 0x293f),
b42b4afb
TI		 2439 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2440 /* ICH10 */
8b0bd226 2441 { PCI_DEVICE(0x8086, 0x3a3e),
b42b4afb
TI		 2442 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2443 /* ICH10 */
8b0bd226 2444 { PCI_DEVICE(0x8086, 0x3a6e),
b42b4afb 2445 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
b6864535
TI		 2446 /* Generic Intel */
2447 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2448 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2449 .class_mask = 0xffffff,
103884a3 2450 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
9477c58e
TI		 2451 /* ATI SB 450/600/700/800/900 */
2452 { PCI_DEVICE(0x1002, 0x437b),
2453 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2454 { PCI_DEVICE(0x1002, 0x4383),
2455 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2456 /* AMD Hudson */
2457 { PCI_DEVICE(0x1022, 0x780d),
2458 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 2459 /* ATI HDMI */
fd48331f
MSB		 2460 { PCI_DEVICE(0x1002, 0x0002),
2461 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
650474fb
AD		 2462 { PCI_DEVICE(0x1002, 0x1308),
2463 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2464 { PCI_DEVICE(0x1002, 0x157a),
2465 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
d716fb03
AB		 2466 { PCI_DEVICE(0x1002, 0x15b3),
2467 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2468 { PCI_DEVICE(0x1002, 0x793b),
2469 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2470 { PCI_DEVICE(0x1002, 0x7919),
2471 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2472 { PCI_DEVICE(0x1002, 0x960f),
2473 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2474 { PCI_DEVICE(0x1002, 0x970f),
2475 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
650474fb
AD		 2476 { PCI_DEVICE(0x1002, 0x9840),
2477 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2478 { PCI_DEVICE(0x1002, 0xaa00),
2479 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2480 { PCI_DEVICE(0x1002, 0xaa08),
2481 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2482 { PCI_DEVICE(0x1002, 0xaa10),
2483 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2484 { PCI_DEVICE(0x1002, 0xaa18),
2485 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2486 { PCI_DEVICE(0x1002, 0xaa20),
2487 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2488 { PCI_DEVICE(0x1002, 0xaa28),
2489 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2490 { PCI_DEVICE(0x1002, 0xaa30),
2491 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2492 { PCI_DEVICE(0x1002, 0xaa38),
2493 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2494 { PCI_DEVICE(0x1002, 0xaa40),
2495 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2496 { PCI_DEVICE(0x1002, 0xaa48),
2497 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
bbaa0d66
CL		 2498 { PCI_DEVICE(0x1002, 0xaa50),
2499 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2500 { PCI_DEVICE(0x1002, 0xaa58),
2501 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2502 { PCI_DEVICE(0x1002, 0xaa60),
2503 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2504 { PCI_DEVICE(0x1002, 0xaa68),
2505 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2506 { PCI_DEVICE(0x1002, 0xaa80),
2507 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2508 { PCI_DEVICE(0x1002, 0xaa88),
2509 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2510 { PCI_DEVICE(0x1002, 0xaa90),
2511 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2512 { PCI_DEVICE(0x1002, 0xaa98),
2513 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a 2514 { PCI_DEVICE(0x1002, 0x9902),
37e661ee 2515 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2516 { PCI_DEVICE(0x1002, 0xaaa0),
37e661ee 2517 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2518 { PCI_DEVICE(0x1002, 0xaaa8),
37e661ee 2519 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2520 { PCI_DEVICE(0x1002, 0xaab0),
37e661ee 2521 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2522 { PCI_DEVICE(0x1002, 0xaac0),
2523 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
0fa372b6
TI		 2524 { PCI_DEVICE(0x1002, 0xaac8),
2525 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2526 { PCI_DEVICE(0x1002, 0xaad8),
2527 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2528 { PCI_DEVICE(0x1002, 0xaae8),
2529 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
8eb22214
MSB		 2530 { PCI_DEVICE(0x1002, 0xaae0),
2531 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2532 { PCI_DEVICE(0x1002, 0xaaf0),
2533 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
87218e9c 2534 /* VIA VT8251/VT8237A */
26f05717 2535 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
754fdff8
AL		 2536 /* VIA GFX VT7122/VX900 */
2537 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2538 /* VIA GFX VT6122/VX11 */
2539 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 2540 /* SIS966 */
2541 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2542 /* ULI M5461 */
2543 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2544 /* NVIDIA MCP */
0c2fd1bf
TI		 2545 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2546 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2547 .class_mask = 0xffffff,
9477c58e 2548 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 2549 /* Teradici */
9477c58e
TI		 2550 { PCI_DEVICE(0x6549, 0x1200),
2551 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 2552 { PCI_DEVICE(0x6549, 0x2200),
2553 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 2554 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 2555 /* CTHDA chips */
2556 { PCI_DEVICE(0x1102, 0x0010),
2557 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2558 { PCI_DEVICE(0x1102, 0x0012),
2559 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
8eeaa2f9 2560#if !IS_ENABLED(CONFIG_SND_CTXFI)
313f6e2d
TI		 2561 /* the following entry conflicts with snd-ctxfi driver,
2562 * as ctxfi driver mutates from HD-audio to native mode with
2563 * a special command sequence.
2564 */
4e01f54b
TI		 2565 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2566 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2567 .class_mask = 0xffffff,
9477c58e 2568 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2569 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 2570#else
2571 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 2572 { PCI_DEVICE(0x1102, 0x0009),
2573 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2574 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 2575#endif
c563f473
TI		 2576 /* CM8888 */
2577 { PCI_DEVICE(0x13f6, 0x5011),
2578 .driver_data = AZX_DRIVER_CMEDIA |
37e661ee 2579 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
e35d4b11
OS		 2580 /* Vortex86MX */
2581 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 2582 /* VMware HDAudio */
2583 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 2584 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 2585 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2586 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2587 .class_mask = 0xffffff,
9477c58e 2588 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 2589 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2590 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2591 .class_mask = 0xffffff,
9477c58e 2592 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 2593 { 0, }
2594};
2595MODULE_DEVICE_TABLE(pci, azx_ids);
2596
2597/* pci_driver definition */
e9f66d9b 2598static struct pci_driver azx_driver = {
3733e424 2599 .name = KBUILD_MODNAME,
1da177e4
LT		 2600 .id_table = azx_ids,
2601 .probe = azx_probe,
e23e7a14 2602 .remove = azx_remove,
b2a0bafa 2603 .shutdown = azx_shutdown,
68cb2b55
TI		 2604 .driver = {
2605 .pm = AZX_PM_OPS,
2606 },
1da177e4
LT		 2607};
2608
e9f66d9b 2609module_pci_driver(azx_driver);
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