[mirror_ubuntu-artful-kernel.git] / sound / pci / hda / hda_priv.h

/*
 *  Common defines for the alsa driver code base for HD Audio.
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License as published by the Free
 *  Software Foundation; either version 2 of the License, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 *  more details.
 */

#ifndef __SOUND_HDA_PRIV_H
#define __SOUND_HDA_PRIV_H

#include <linux/clocksource.h>
#include <sound/core.h>
#include <sound/pcm.h>

/*
 * registers
 */
#define ICH6_REG_GCAP			0x00
#define   ICH6_GCAP_64OK	(1 << 0)   /* 64bit address support */
#define   ICH6_GCAP_NSDO	(3 << 1)   /* # of serial data out signals */
#define   ICH6_GCAP_BSS		(31 << 3)  /* # of bidirectional streams */
#define   ICH6_GCAP_ISS		(15 << 8)  /* # of input streams */
#define   ICH6_GCAP_OSS		(15 << 12) /* # of output streams */
#define ICH6_REG_VMIN			0x02
#define ICH6_REG_VMAJ			0x03
#define ICH6_REG_OUTPAY			0x04
#define ICH6_REG_INPAY			0x06
#define ICH6_REG_GCTL			0x08
#define   ICH6_GCTL_RESET	(1 << 0)   /* controller reset */
#define   ICH6_GCTL_FCNTRL	(1 << 1)   /* flush control */
#define   ICH6_GCTL_UNSOL	(1 << 8)   /* accept unsol. response enable */
#define ICH6_REG_WAKEEN			0x0c
#define ICH6_REG_STATESTS		0x0e
#define ICH6_REG_GSTS			0x10
#define   ICH6_GSTS_FSTS	(1 << 1)   /* flush status */
#define ICH6_REG_INTCTL			0x20
#define ICH6_REG_INTSTS			0x24
#define ICH6_REG_WALLCLK		0x30	/* 24Mhz source */
#define ICH6_REG_OLD_SSYNC		0x34	/* SSYNC for old ICH */
#define ICH6_REG_SSYNC			0x38
#define ICH6_REG_CORBLBASE		0x40
#define ICH6_REG_CORBUBASE		0x44
#define ICH6_REG_CORBWP			0x48
#define ICH6_REG_CORBRP			0x4a
#define   ICH6_CORBRP_RST	(1 << 15)  /* read pointer reset */
#define ICH6_REG_CORBCTL		0x4c
#define   ICH6_CORBCTL_RUN	(1 << 1)   /* enable DMA */
#define   ICH6_CORBCTL_CMEIE	(1 << 0)   /* enable memory error irq */
#define ICH6_REG_CORBSTS		0x4d
#define   ICH6_CORBSTS_CMEI	(1 << 0)   /* memory error indication */
#define ICH6_REG_CORBSIZE		0x4e

#define ICH6_REG_RIRBLBASE		0x50
#define ICH6_REG_RIRBUBASE		0x54
#define ICH6_REG_RIRBWP			0x58
#define   ICH6_RIRBWP_RST	(1 << 15)  /* write pointer reset */
#define ICH6_REG_RINTCNT		0x5a
#define ICH6_REG_RIRBCTL		0x5c
#define   ICH6_RBCTL_IRQ_EN	(1 << 0)   /* enable IRQ */
#define   ICH6_RBCTL_DMA_EN	(1 << 1)   /* enable DMA */
#define   ICH6_RBCTL_OVERRUN_EN	(1 << 2)   /* enable overrun irq */
#define ICH6_REG_RIRBSTS		0x5d
#define   ICH6_RBSTS_IRQ	(1 << 0)   /* response irq */
#define   ICH6_RBSTS_OVERRUN	(1 << 2)   /* overrun irq */
#define ICH6_REG_RIRBSIZE		0x5e

#define ICH6_REG_IC			0x60
#define ICH6_REG_IR			0x64
#define ICH6_REG_IRS			0x68
#define   ICH6_IRS_VALID	(1<<1)
#define   ICH6_IRS_BUSY		(1<<0)

#define ICH6_REG_DPLBASE		0x70
#define ICH6_REG_DPUBASE		0x74
#define   ICH6_DPLBASE_ENABLE	0x1	/* Enable position buffer */

/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };

/* stream register offsets from stream base */
#define ICH6_REG_SD_CTL			0x00
#define ICH6_REG_SD_STS			0x03
#define ICH6_REG_SD_LPIB		0x04
#define ICH6_REG_SD_CBL			0x08
#define ICH6_REG_SD_LVI			0x0c
#define ICH6_REG_SD_FIFOW		0x0e
#define ICH6_REG_SD_FIFOSIZE		0x10
#define ICH6_REG_SD_FORMAT		0x12
#define ICH6_REG_SD_BDLPL		0x18
#define ICH6_REG_SD_BDLPU		0x1c

/* PCI space */
#define ICH6_PCIREG_TCSEL	0x44

/*
 * other constants
 */

/* max number of fragments - we may use more if allocating more pages for BDL */
#define BDL_SIZE		4096
#define AZX_MAX_BDL_ENTRIES	(BDL_SIZE / 16)
#define AZX_MAX_FRAG		32
/* max buffer size - no h/w limit, you can increase as you like */
#define AZX_MAX_BUF_SIZE	(1024*1024*1024)

/* RIRB int mask: overrun[2], response[0] */
#define RIRB_INT_RESPONSE	0x01
#define RIRB_INT_OVERRUN	0x04
#define RIRB_INT_MASK		0x05

/* STATESTS int mask: S3,SD2,SD1,SD0 */
#define AZX_MAX_CODECS		8
#define AZX_DEFAULT_CODECS	4
#define STATESTS_INT_MASK	((1 << AZX_MAX_CODECS) - 1)

/* SD_CTL bits */
#define SD_CTL_STREAM_RESET	0x01	/* stream reset bit */
#define SD_CTL_DMA_START	0x02	/* stream DMA start bit */
#define SD_CTL_STRIPE		(3 << 16)	/* stripe control */
#define SD_CTL_TRAFFIC_PRIO	(1 << 18)	/* traffic priority */
#define SD_CTL_DIR		(1 << 19)	/* bi-directional stream */
#define SD_CTL_STREAM_TAG_MASK	(0xf << 20)
#define SD_CTL_STREAM_TAG_SHIFT	20

/* SD_CTL and SD_STS */
#define SD_INT_DESC_ERR		0x10	/* descriptor error interrupt */
#define SD_INT_FIFO_ERR		0x08	/* FIFO error interrupt */
#define SD_INT_COMPLETE		0x04	/* completion interrupt */
#define SD_INT_MASK		(SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
				 SD_INT_COMPLETE)

/* SD_STS */
#define SD_STS_FIFO_READY	0x20	/* FIFO ready */

/* INTCTL and INTSTS */
#define ICH6_INT_ALL_STREAM	0xff	   /* all stream interrupts */
#define ICH6_INT_CTRL_EN	0x40000000 /* controller interrupt enable bit */
#define ICH6_INT_GLOBAL_EN	0x80000000 /* global interrupt enable bit */

/* below are so far hardcoded - should read registers in future */
#define ICH6_MAX_CORB_ENTRIES	256
#define ICH6_MAX_RIRB_ENTRIES	256

/* driver quirks (capabilities) */
/* bits 0-7 are used for indicating driver type */
#define AZX_DCAPS_NO_TCSEL	(1 << 8)	/* No Intel TCSEL bit */
#define AZX_DCAPS_NO_MSI	(1 << 9)	/* No MSI support */
#define AZX_DCAPS_ATI_SNOOP	(1 << 10)	/* ATI snoop enable */
#define AZX_DCAPS_NVIDIA_SNOOP	(1 << 11)	/* Nvidia snoop enable */
#define AZX_DCAPS_SCH_SNOOP	(1 << 12)	/* SCH/PCH snoop enable */
#define AZX_DCAPS_RIRB_DELAY	(1 << 13)	/* Long delay in read loop */
#define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14)	/* Put a delay before read */
#define AZX_DCAPS_CTX_WORKAROUND (1 << 15)	/* X-Fi workaround */
#define AZX_DCAPS_POSFIX_LPIB	(1 << 16)	/* Use LPIB as default */
#define AZX_DCAPS_POSFIX_VIA	(1 << 17)	/* Use VIACOMBO as default */
#define AZX_DCAPS_NO_64BIT	(1 << 18)	/* No 64bit address */
#define AZX_DCAPS_SYNC_WRITE	(1 << 19)	/* sync each cmd write */
#define AZX_DCAPS_OLD_SSYNC	(1 << 20)	/* Old SSYNC reg for ICH */
#define AZX_DCAPS_BUFSIZE	(1 << 21)	/* no buffer size alignment */
#define AZX_DCAPS_ALIGN_BUFSIZE	(1 << 22)	/* buffer size alignment */
#define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23)	/* BDLE in 4k boundary */
#define AZX_DCAPS_COUNT_LPIB_DELAY  (1 << 25)	/* Take LPIB as delay */
#define AZX_DCAPS_PM_RUNTIME	(1 << 26)	/* runtime PM support */
#define AZX_DCAPS_I915_POWERWELL (1 << 27)	/* HSW i915 powerwell support */
#define AZX_DCAPS_CORBRP_SELF_CLEAR (1 << 28)	/* CORBRP clears itself after reset */

/* HD Audio class code */
#define PCI_CLASS_MULTIMEDIA_HD_AUDIO	0x0403

struct azx_dev {
	struct snd_dma_buffer bdl; /* BDL buffer */
	u32 *posbuf;		/* position buffer pointer */

	unsigned int bufsize;	/* size of the play buffer in bytes */
	unsigned int period_bytes; /* size of the period in bytes */
	unsigned int frags;	/* number for period in the play buffer */
	unsigned int fifo_size;	/* FIFO size */
	unsigned long start_wallclk;	/* start + minimum wallclk */
	unsigned long period_wallclk;	/* wallclk for period */

	void __iomem *sd_addr;	/* stream descriptor pointer */

	u32 sd_int_sta_mask;	/* stream int status mask */

	/* pcm support */
	struct snd_pcm_substream *substream;	/* assigned substream,
						 * set in PCM open
						 */
	unsigned int format_val;	/* format value to be set in the
					 * controller and the codec
					 */
	unsigned char stream_tag;	/* assigned stream */
	unsigned char index;		/* stream index */
	int assigned_key;		/* last device# key assigned to */

	unsigned int opened:1;
	unsigned int running:1;
	unsigned int irq_pending:1;
	unsigned int prepared:1;
	unsigned int locked:1;
	/*
	 * For VIA:
	 *  A flag to ensure DMA position is 0
	 *  when link position is not greater than FIFO size
	 */
	unsigned int insufficient:1;
	unsigned int wc_marked:1;
	unsigned int no_period_wakeup:1;

	struct timecounter  azx_tc;
	struct cyclecounter azx_cc;

	int delay_negative_threshold;

#ifdef CONFIG_SND_HDA_DSP_LOADER
	/* Allows dsp load to have sole access to the playback stream. */
	struct mutex dsp_mutex;
#endif
};

/* CORB/RIRB */
struct azx_rb {
	u32 *buf;		/* CORB/RIRB buffer
				 * Each CORB entry is 4byte, RIRB is 8byte
				 */
	dma_addr_t addr;	/* physical address of CORB/RIRB buffer */
	/* for RIRB */
	unsigned short rp, wp;	/* read/write pointers */
	int cmds[AZX_MAX_CODECS];	/* number of pending requests */
	u32 res[AZX_MAX_CODECS];	/* last read value */
};

struct azx;

/* Functions to read/write to hda registers. */
struct hda_controller_ops {
	/* Register Access */
	void (*reg_writel)(u32 value, u32 __iomem *addr);
	u32 (*reg_readl)(u32 __iomem *addr);
	void (*reg_writew)(u16 value, u16 __iomem *addr);
	u16 (*reg_readw)(u16 __iomem *addr);
	void (*reg_writeb)(u8 value, u8 __iomem *addr);
	u8 (*reg_readb)(u8 __iomem *addr);
	/* Disable msi if supported, PCI only */
	int (*disable_msi_reset_irq)(struct azx *);
	/* Allocation ops */
	int (*dma_alloc_pages)(struct azx *chip,
			       int type,
			       size_t size,
			       struct snd_dma_buffer *buf);
	void (*dma_free_pages)(struct azx *chip, struct snd_dma_buffer *buf);
	int (*substream_alloc_pages)(struct azx *chip,
				     struct snd_pcm_substream *substream,
				     size_t size);
	int (*substream_free_pages)(struct azx *chip,
				    struct snd_pcm_substream *substream);
	void (*pcm_mmap_prepare)(struct snd_pcm_substream *substream,
				 struct vm_area_struct *area);
	/* Check if current position is acceptable */
	int (*position_check)(struct azx *chip, struct azx_dev *azx_dev);
};

struct azx_pcm {
	struct azx *chip;
	struct snd_pcm *pcm;
	struct hda_codec *codec;
	struct hda_pcm_stream *hinfo[2];
	struct list_head list;
};

typedef unsigned int (*azx_get_pos_callback_t)(struct azx *, struct azx_dev *);
typedef int (*azx_get_delay_callback_t)(struct azx *, struct azx_dev *, unsigned int pos);

struct azx {
	struct snd_card *card;
	struct pci_dev *pci;
	int dev_index;

	/* chip type specific */
	int driver_type;
	unsigned int driver_caps;
	int playback_streams;
	int playback_index_offset;
	int capture_streams;
	int capture_index_offset;
	int num_streams;
	const int *jackpoll_ms; /* per-card jack poll interval */

	/* Register interaction. */
	const struct hda_controller_ops *ops;

	/* position adjustment callbacks */
	azx_get_pos_callback_t get_position[2];
	azx_get_delay_callback_t get_delay[2];

	/* pci resources */
	unsigned long addr;
	void __iomem *remap_addr;
	int irq;

	/* locks */
	spinlock_t reg_lock;
	struct mutex open_mutex; /* Prevents concurrent open/close operations */

	/* streams (x num_streams) */
	struct azx_dev *azx_dev;

	/* PCM */
	struct list_head pcm_list; /* azx_pcm list */

	/* HD codec */
	unsigned short codec_mask;
	int  codec_probe_mask; /* copied from probe_mask option */
	struct hda_bus *bus;
	unsigned int beep_mode;

	/* CORB/RIRB */
	struct azx_rb corb;
	struct azx_rb rirb;

	/* CORB/RIRB and position buffers */
	struct snd_dma_buffer rb;
	struct snd_dma_buffer posbuf;

#ifdef CONFIG_SND_HDA_PATCH_LOADER
	const struct firmware *fw;
#endif

	/* flags */
	const int *bdl_pos_adj;
	int poll_count;
	unsigned int running:1;
	unsigned int initialized:1;
	unsigned int single_cmd:1;
	unsigned int polling_mode:1;
	unsigned int msi:1;
	unsigned int probing:1; /* codec probing phase */
	unsigned int snoop:1;
	unsigned int align_buffer_size:1;
	unsigned int region_requested:1;
	unsigned int disabled:1; /* disabled by VGA-switcher */

	/* for debugging */
	unsigned int last_cmd[AZX_MAX_CODECS];

	/* reboot notifier (for mysterious hangup problem at power-down) */
	struct notifier_block reboot_notifier;

#ifdef CONFIG_SND_HDA_DSP_LOADER
	struct azx_dev saved_azx_dev;
#endif
};

#ifdef CONFIG_X86
#define azx_snoop(chip)		((chip)->snoop)
#else
#define azx_snoop(chip)		true
#endif

/*
 * macros for easy use
 */

#define azx_writel(chip, reg, value) \
	((chip)->ops->reg_writel(value, (chip)->remap_addr + ICH6_REG_##reg))
#define azx_readl(chip, reg) \
	((chip)->ops->reg_readl((chip)->remap_addr + ICH6_REG_##reg))
#define azx_writew(chip, reg, value) \
	((chip)->ops->reg_writew(value, (chip)->remap_addr + ICH6_REG_##reg))
#define azx_readw(chip, reg) \
	((chip)->ops->reg_readw((chip)->remap_addr + ICH6_REG_##reg))
#define azx_writeb(chip, reg, value) \
	((chip)->ops->reg_writeb(value, (chip)->remap_addr + ICH6_REG_##reg))
#define azx_readb(chip, reg) \
	((chip)->ops->reg_readb((chip)->remap_addr + ICH6_REG_##reg))

#define azx_sd_writel(chip, dev, reg, value) \
	((chip)->ops->reg_writel(value, (dev)->sd_addr + ICH6_REG_##reg))
#define azx_sd_readl(chip, dev, reg) \
	((chip)->ops->reg_readl((dev)->sd_addr + ICH6_REG_##reg))
#define azx_sd_writew(chip, dev, reg, value) \
	((chip)->ops->reg_writew(value, (dev)->sd_addr + ICH6_REG_##reg))
#define azx_sd_readw(chip, dev, reg) \
	((chip)->ops->reg_readw((dev)->sd_addr + ICH6_REG_##reg))
#define azx_sd_writeb(chip, dev, reg, value) \
	((chip)->ops->reg_writeb(value, (dev)->sd_addr + ICH6_REG_##reg))
#define azx_sd_readb(chip, dev, reg) \
	((chip)->ops->reg_readb((dev)->sd_addr + ICH6_REG_##reg))

#endif /* __SOUND_HDA_PRIV_H */
Commit	Line	Data
2538a4f5 DR	1	/*
	2	* Common defines for the alsa driver code base for HD Audio.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms of the GNU General Public License as published by the Free
	6	* Software Foundation; either version 2 of the License, or (at your option)
	7	* any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*/
	14
	15	#ifndef __SOUND_HDA_PRIV_H
	16	#define __SOUND_HDA_PRIV_H
	17
	18	#include <linux/clocksource.h>
	19	#include <sound/core.h>
	20	#include <sound/pcm.h>
	21
	22	/*
	23	* registers
	24	*/
	25	#define ICH6_REG_GCAP 0x00
	26	#define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
	27	#define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
	28	#define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
	29	#define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
	30	#define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
	31	#define ICH6_REG_VMIN 0x02
	32	#define ICH6_REG_VMAJ 0x03
	33	#define ICH6_REG_OUTPAY 0x04
	34	#define ICH6_REG_INPAY 0x06
	35	#define ICH6_REG_GCTL 0x08
	36	#define ICH6_GCTL_RESET (1 << 0) /* controller reset */
	37	#define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
	38	#define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
	39	#define ICH6_REG_WAKEEN 0x0c
	40	#define ICH6_REG_STATESTS 0x0e
	41	#define ICH6_REG_GSTS 0x10
	42	#define ICH6_GSTS_FSTS (1 << 1) /* flush status */
	43	#define ICH6_REG_INTCTL 0x20
	44	#define ICH6_REG_INTSTS 0x24
	45	#define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
	46	#define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
	47	#define ICH6_REG_SSYNC 0x38
	48	#define ICH6_REG_CORBLBASE 0x40
	49	#define ICH6_REG_CORBUBASE 0x44
	50	#define ICH6_REG_CORBWP 0x48
	51	#define ICH6_REG_CORBRP 0x4a
	52	#define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
	53	#define ICH6_REG_CORBCTL 0x4c
	54	#define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
	55	#define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
	56	#define ICH6_REG_CORBSTS 0x4d
	57	#define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
	58	#define ICH6_REG_CORBSIZE 0x4e
	59
	60	#define ICH6_REG_RIRBLBASE 0x50
	61	#define ICH6_REG_RIRBUBASE 0x54
	62	#define ICH6_REG_RIRBWP 0x58
	63	#define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
	64	#define ICH6_REG_RINTCNT 0x5a
65	#define ICH6_REG_RIRBCTL 0x5c
66	#define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
67	#define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
68	#define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
69	#define ICH6_REG_RIRBSTS 0x5d
70	#define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
71	#define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
72	#define ICH6_REG_RIRBSIZE 0x5e
73
74	#define ICH6_REG_IC 0x60
75	#define ICH6_REG_IR 0x64
76	#define ICH6_REG_IRS 0x68
77	#define ICH6_IRS_VALID (1<<1)
78	#define ICH6_IRS_BUSY (1<<0)
79
80	#define ICH6_REG_DPLBASE 0x70
81	#define ICH6_REG_DPUBASE 0x74
82	#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
83
84	/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
85	enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
86
87	/* stream register offsets from stream base */
88	#define ICH6_REG_SD_CTL 0x00
89	#define ICH6_REG_SD_STS 0x03
90	#define ICH6_REG_SD_LPIB 0x04
91	#define ICH6_REG_SD_CBL 0x08
92	#define ICH6_REG_SD_LVI 0x0c
93	#define ICH6_REG_SD_FIFOW 0x0e
94	#define ICH6_REG_SD_FIFOSIZE 0x10
95	#define ICH6_REG_SD_FORMAT 0x12
96	#define ICH6_REG_SD_BDLPL 0x18
97	#define ICH6_REG_SD_BDLPU 0x1c
98
99	/* PCI space */
100	#define ICH6_PCIREG_TCSEL 0x44
101
102	/*
103	* other constants
104	*/
105
2538a4f5 DR	106	/* max number of fragments - we may use more if allocating more pages for BDL */
	107	#define BDL_SIZE 4096
	108	#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
	109	#define AZX_MAX_FRAG 32
	110	/* max buffer size - no h/w limit, you can increase as you like */
	111	#define AZX_MAX_BUF_SIZE (102410241024)
	112
	113	/* RIRB int mask: overrun[2], response[0] */
	114	#define RIRB_INT_RESPONSE 0x01
	115	#define RIRB_INT_OVERRUN 0x04
	116	#define RIRB_INT_MASK 0x05
	117
	118	/* STATESTS int mask: S3,SD2,SD1,SD0 */
	119	#define AZX_MAX_CODECS 8
	120	#define AZX_DEFAULT_CODECS 4
	121	#define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
	122
	123	/* SD_CTL bits */
	124	#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
	125	#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
	126	#define SD_CTL_STRIPE (3 << 16) /* stripe control */
	127	#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
	128	#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
	129	#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
	130	#define SD_CTL_STREAM_TAG_SHIFT 20
	131
	132	/* SD_CTL and SD_STS */
	133	#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
	134	#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
	135	#define SD_INT_COMPLETE 0x04 /* completion interrupt */
	136	#define SD_INT_MASK (SD_INT_DESC_ERR\|SD_INT_FIFO_ERR\|\
	137	SD_INT_COMPLETE)
	138
	139	/* SD_STS */
	140	#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
	141
	142	/* INTCTL and INTSTS */
	143	#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
	144	#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
	145	#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
	146
	147	/* below are so far hardcoded - should read registers in future */
	148	#define ICH6_MAX_CORB_ENTRIES 256
	149	#define ICH6_MAX_RIRB_ENTRIES 256
	150
	151	/* driver quirks (capabilities) */
	152	/* bits 0-7 are used for indicating driver type */
	153	#define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
	154	#define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
	155	#define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
	156	#define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
	157	#define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
	158	#define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
	159	#define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
	160	#define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
	161	#define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
	162	#define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
	163	#define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
	164	#define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
	165	#define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
	166	#define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
	167	#define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */
	168	#define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
	169	#define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */
170	#define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */
171	#define AZX_DCAPS_I915_POWERWELL (1 << 27) /* HSW i915 powerwell support */
6ba736dd	172	#define AZX_DCAPS_CORBRP_SELF_CLEAR (1 << 28) /* CORBRP clears itself after reset */
2538a4f5	173
2538a4f5 DR	174	/* HD Audio class code */
	175	#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
	176
	177	struct azx_dev {
	178	struct snd_dma_buffer bdl; /* BDL buffer */
	179	u32 posbuf; / position buffer pointer */
	180
	181	unsigned int bufsize; /* size of the play buffer in bytes */
	182	unsigned int period_bytes; /* size of the period in bytes */
	183	unsigned int frags; /* number for period in the play buffer */
	184	unsigned int fifo_size; /* FIFO size */
	185	unsigned long start_wallclk; /* start + minimum wallclk */
	186	unsigned long period_wallclk; /* wallclk for period */
	187
	188	void __iomem sd_addr; / stream descriptor pointer */
	189
	190	u32 sd_int_sta_mask; /* stream int status mask */
	191
	192	/* pcm support */
	193	struct snd_pcm_substream substream; / assigned substream,
	194	* set in PCM open
	195	*/
	196	unsigned int format_val; /* format value to be set in the
	197	* controller and the codec
	198	*/
	199	unsigned char stream_tag; /* assigned stream */
	200	unsigned char index; /* stream index */
	201	int assigned_key; /* last device# key assigned to */
	202
	203	unsigned int opened:1;
	204	unsigned int running:1;
	205	unsigned int irq_pending:1;
	206	unsigned int prepared:1;
	207	unsigned int locked:1;
	208	/*
	209	* For VIA:
	210	* A flag to ensure DMA position is 0
	211	* when link position is not greater than FIFO size
	212	*/
	213	unsigned int insufficient:1;
	214	unsigned int wc_marked:1;
	215	unsigned int no_period_wakeup:1;
	216
	217	struct timecounter azx_tc;
	218	struct cyclecounter azx_cc;
	219
	220	int delay_negative_threshold;
	221
	222	#ifdef CONFIG_SND_HDA_DSP_LOADER
	223	/* Allows dsp load to have sole access to the playback stream. */
	224	struct mutex dsp_mutex;
	225	#endif
	226	};
	227
	228	/* CORB/RIRB */
	229	struct azx_rb {
	230	u32 buf; / CORB/RIRB buffer
	231	* Each CORB entry is 4byte, RIRB is 8byte
	232	*/
	233	dma_addr_t addr; /* physical address of CORB/RIRB buffer */
	234	/* for RIRB */
	235	unsigned short rp, wp; /* read/write pointers */
	236	int cmds[AZX_MAX_CODECS]; /* number of pending requests */
	237	u32 res[AZX_MAX_CODECS]; /* last read value */
238	};
239
f46ea609 DR	240	struct azx;
f46ea609 DR	241
40830813 DR	242	/* Functions to read/write to hda registers. */
	243	struct hda_controller_ops {
	244	/* Register Access */
db291e36 DR	245	void (reg_writel)(u32 value, u32 __iomem addr);
	246	u32 (reg_readl)(u32 __iomem addr);
	247	void (reg_writew)(u16 value, u16 __iomem addr);
	248	u16 (reg_readw)(u16 __iomem addr);
	249	void (reg_writeb)(u8 value, u8 __iomem addr);
	250	u8 (reg_readb)(u8 __iomem addr);
f46ea609 DR	251	/* Disable msi if supported, PCI only */
f46ea609 DR	252	int (disable_msi_reset_irq)(struct azx );
b419b35b DR	253	/* Allocation ops */
	254	int (dma_alloc_pages)(struct azx chip,
	255	int type,
	256	size_t size,
	257	struct snd_dma_buffer *buf);
	258	void (dma_free_pages)(struct azx chip, struct snd_dma_buffer *buf);
	259	int (substream_alloc_pages)(struct azx chip,
	260	struct snd_pcm_substream *substream,
	261	size_t size);
	262	int (substream_free_pages)(struct azx chip,
	263	struct snd_pcm_substream *substream);
8769b278 DR	264	void (pcm_mmap_prepare)(struct snd_pcm_substream substream,
8769b278 DR	265	struct vm_area_struct *area);
7ca954a8 DR	266	/* Check if current position is acceptable */
7ca954a8 DR	267	int (position_check)(struct azx chip, struct azx_dev *azx_dev);
40830813 DR	268	};
40830813 DR	269
2538a4f5 DR	270	struct azx_pcm {
	271	struct azx *chip;
	272	struct snd_pcm *pcm;
	273	struct hda_codec *codec;
	274	struct hda_pcm_stream *hinfo[2];
	275	struct list_head list;
	276	};
	277
b6050ef6 TI	278	typedef unsigned int (azx_get_pos_callback_t)(struct azx , struct azx_dev *);
	279	typedef int (azx_get_delay_callback_t)(struct azx , struct azx_dev *, unsigned int pos);
	280
2538a4f5 DR	281	struct azx {
	282	struct snd_card *card;
	283	struct pci_dev *pci;
	284	int dev_index;
	285
	286	/* chip type specific */
	287	int driver_type;
	288	unsigned int driver_caps;
	289	int playback_streams;
	290	int playback_index_offset;
	291	int capture_streams;
	292	int capture_index_offset;
	293	int num_streams;
749ee287	294	const int jackpoll_ms; / per-card jack poll interval */
2538a4f5	295
40830813 DR	296	/* Register interaction. */
	297	const struct hda_controller_ops *ops;
	298
b6050ef6 TI	299	/* position adjustment callbacks */
	300	azx_get_pos_callback_t get_position[2];
	301	azx_get_delay_callback_t get_delay[2];
	302
2538a4f5 DR	303	/* pci resources */
	304	unsigned long addr;
	305	void __iomem *remap_addr;
	306	int irq;
	307
	308	/* locks */
	309	spinlock_t reg_lock;
	310	struct mutex open_mutex; /* Prevents concurrent open/close operations */
2538a4f5 DR	311
	312	/* streams (x num_streams) */
	313	struct azx_dev *azx_dev;
	314
	315	/* PCM */
	316	struct list_head pcm_list; /* azx_pcm list */
	317
	318	/* HD codec */
	319	unsigned short codec_mask;
	320	int codec_probe_mask; /* copied from probe_mask option */
	321	struct hda_bus *bus;
	322	unsigned int beep_mode;
	323
	324	/* CORB/RIRB */
	325	struct azx_rb corb;
	326	struct azx_rb rirb;
	327
	328	/* CORB/RIRB and position buffers */
	329	struct snd_dma_buffer rb;
	330	struct snd_dma_buffer posbuf;
	331
	332	#ifdef CONFIG_SND_HDA_PATCH_LOADER
	333	const struct firmware *fw;
	334	#endif
	335
	336	/* flags */
9cdc0115	337	const int *bdl_pos_adj;
2538a4f5 DR	338	int poll_count;
	339	unsigned int running:1;
	340	unsigned int initialized:1;
	341	unsigned int single_cmd:1;
	342	unsigned int polling_mode:1;
	343	unsigned int msi:1;
2538a4f5 DR	344	unsigned int probing:1; /* codec probing phase */
	345	unsigned int snoop:1;
	346	unsigned int align_buffer_size:1;
	347	unsigned int region_requested:1;
2538a4f5 DR	348	unsigned int disabled:1; /* disabled by VGA-switcher */
	349
	350	/* for debugging */
	351	unsigned int last_cmd[AZX_MAX_CODECS];
	352
2538a4f5 DR	353	/* reboot notifier (for mysterious hangup problem at power-down) */
	354	struct notifier_block reboot_notifier;
	355
2538a4f5 DR	356	#ifdef CONFIG_SND_HDA_DSP_LOADER
	357	struct azx_dev saved_azx_dev;
	358	#endif
2538a4f5 DR	359	};
2538a4f5 DR	360
2538a4f5 DR	361	#ifdef CONFIG_X86
	362	#define azx_snoop(chip) ((chip)->snoop)
	363	#else
	364	#define azx_snoop(chip) true
	365	#endif
	366
40830813 DR	367	/*
	368	* macros for easy use
	369	*/
	370
	371	#define azx_writel(chip, reg, value) \
778bde6f	372	((chip)->ops->reg_writel(value, (chip)->remap_addr + ICH6_REG_##reg))
40830813	373	#define azx_readl(chip, reg) \
778bde6f	374	((chip)->ops->reg_readl((chip)->remap_addr + ICH6_REG_##reg))
40830813	375	#define azx_writew(chip, reg, value) \
778bde6f	376	((chip)->ops->reg_writew(value, (chip)->remap_addr + ICH6_REG_##reg))
40830813	377	#define azx_readw(chip, reg) \
778bde6f	378	((chip)->ops->reg_readw((chip)->remap_addr + ICH6_REG_##reg))
40830813	379	#define azx_writeb(chip, reg, value) \
778bde6f	380	((chip)->ops->reg_writeb(value, (chip)->remap_addr + ICH6_REG_##reg))
40830813	381	#define azx_readb(chip, reg) \
778bde6f	382	((chip)->ops->reg_readb((chip)->remap_addr + ICH6_REG_##reg))
40830813 DR	383
40830813 DR	384	#define azx_sd_writel(chip, dev, reg, value) \
778bde6f	385	((chip)->ops->reg_writel(value, (dev)->sd_addr + ICH6_REG_##reg))
40830813	386	#define azx_sd_readl(chip, dev, reg) \
778bde6f	387	((chip)->ops->reg_readl((dev)->sd_addr + ICH6_REG_##reg))
40830813	388	#define azx_sd_writew(chip, dev, reg, value) \
778bde6f	389	((chip)->ops->reg_writew(value, (dev)->sd_addr + ICH6_REG_##reg))
40830813	390	#define azx_sd_readw(chip, dev, reg) \
778bde6f	391	((chip)->ops->reg_readw((dev)->sd_addr + ICH6_REG_##reg))
40830813	392	#define azx_sd_writeb(chip, dev, reg, value) \
778bde6f	393	((chip)->ops->reg_writeb(value, (dev)->sd_addr + ICH6_REG_##reg))
40830813	394	#define azx_sd_readb(chip, dev, reg) \
778bde6f	395	((chip)->ops->reg_readb((dev)->sd_addr + ICH6_REG_##reg))
40830813	396
2538a4f5	397	#endif /* __SOUND_HDA_PRIV_H */