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sound: fix drivers needing module.h not moduleparam.h
[mirror_ubuntu-artful-kernel.git] / sound / pci / hda / patch_hdmi.c
CommitLineData
079d88cc
WF		 1/*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
84eb01be
TI		 6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
079d88cc
WF		 9 *
10 * Authors:
11 * Wu Fengguang <wfg@linux.intel.com>
12 *
13 * Maintained by:
14 * Wu Fengguang <wfg@linux.intel.com>
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the Free
18 * Software Foundation; either version 2 of the License, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful, but
22 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
23 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
24 * for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software Foundation,
28 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
84eb01be
TI		 31#include <linux/init.h>
32#include <linux/delay.h>
33#include <linux/slab.h>
65a77217 34#include <linux/module.h>
84eb01be 35#include <sound/core.h>
07acecc1 36#include <sound/jack.h>
84eb01be
TI		 37#include "hda_codec.h"
38#include "hda_local.h"
39
0ebaa24c
TI		 40static bool static_hdmi_pcm;
41module_param(static_hdmi_pcm, bool, 0644);
42MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
43
84eb01be
TI		 44/*
45 * The HDMI/DisplayPort configuration can be highly dynamic. A graphics device
384a48d7 46 * could support N independent pipes, each of them can be connected to one or
84eb01be
TI		 47 * more ports (DVI, HDMI or DisplayPort).
48 *
49 * The HDA correspondence of pipes/ports are converter/pin nodes.
50 */
73926656
SW		 51#define MAX_HDMI_CVTS 4
52#define MAX_HDMI_PINS 4
079d88cc 53
384a48d7
SW		 54struct hdmi_spec_per_cvt {
55 hda_nid_t cvt_nid;
56 int assigned;
57 unsigned int channels_min;
58 unsigned int channels_max;
59 u32 rates;
60 u64 formats;
61 unsigned int maxbps;
62};
079d88cc 63
384a48d7
SW		 64struct hdmi_spec_per_pin {
65 hda_nid_t pin_nid;
66 int num_mux_nids;
67 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
68 struct hdmi_eld sink_eld;
69};
079d88cc 70
384a48d7
SW		 71struct hdmi_spec {
72 int num_cvts;
73 struct hdmi_spec_per_cvt cvts[MAX_HDMI_CVTS];
079d88cc 74
384a48d7
SW		 75 int num_pins;
76 struct hdmi_spec_per_pin pins[MAX_HDMI_PINS];
77 struct hda_pcm pcm_rec[MAX_HDMI_PINS];
079d88cc
WF		 78
79 /*
384a48d7 80 * Non-generic ATI/NVIDIA specific
079d88cc
WF		 81 */
82 struct hda_multi_out multiout;
fb79e1e0 83 const struct hda_pcm_stream *pcm_playback;
079d88cc
WF		 84};
85
86
87struct hdmi_audio_infoframe {
88 u8 type; /* 0x84 */
89 u8 ver; /* 0x01 */
90 u8 len; /* 0x0a */
91
53d7d69d
WF		 92 u8 checksum;
93
079d88cc
WF		 94 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
95 u8 SS01_SF24;
96 u8 CXT04;
97 u8 CA;
98 u8 LFEPBL01_LSV36_DM_INH7;
53d7d69d
WF		 99};
100
101struct dp_audio_infoframe {
102 u8 type; /* 0x84 */
103 u8 len; /* 0x1b */
104 u8 ver; /* 0x11 << 2 */
105
106 u8 CC02_CT47; /* match with HDMI infoframe from this on */
107 u8 SS01_SF24;
108 u8 CXT04;
109 u8 CA;
110 u8 LFEPBL01_LSV36_DM_INH7;
079d88cc
WF		 111};
112
2b203dbb
TI		 113union audio_infoframe {
114 struct hdmi_audio_infoframe hdmi;
115 struct dp_audio_infoframe dp;
116 u8 bytes[0];
117};
118
079d88cc
WF		 119/*
120 * CEA speaker placement:
121 *
122 * FLH FCH FRH
123 * FLW FL FLC FC FRC FR FRW
124 *
125 * LFE
126 * TC
127 *
128 * RL RLC RC RRC RR
129 *
130 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
131 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
132 */
133enum cea_speaker_placement {
134 FL = (1 << 0), /* Front Left */
135 FC = (1 << 1), /* Front Center */
136 FR = (1 << 2), /* Front Right */
137 FLC = (1 << 3), /* Front Left Center */
138 FRC = (1 << 4), /* Front Right Center */
139 RL = (1 << 5), /* Rear Left */
140 RC = (1 << 6), /* Rear Center */
141 RR = (1 << 7), /* Rear Right */
142 RLC = (1 << 8), /* Rear Left Center */
143 RRC = (1 << 9), /* Rear Right Center */
144 LFE = (1 << 10), /* Low Frequency Effect */
145 FLW = (1 << 11), /* Front Left Wide */
146 FRW = (1 << 12), /* Front Right Wide */
147 FLH = (1 << 13), /* Front Left High */
148 FCH = (1 << 14), /* Front Center High */
149 FRH = (1 << 15), /* Front Right High */
150 TC = (1 << 16), /* Top Center */
151};
152
153/*
154 * ELD SA bits in the CEA Speaker Allocation data block
155 */
156static int eld_speaker_allocation_bits[] = {
157 [0] = FL | FR,
158 [1] = LFE,
159 [2] = FC,
160 [3] = RL | RR,
161 [4] = RC,
162 [5] = FLC | FRC,
163 [6] = RLC | RRC,
164 /* the following are not defined in ELD yet */
165 [7] = FLW | FRW,
166 [8] = FLH | FRH,
167 [9] = TC,
168 [10] = FCH,
169};
170
171struct cea_channel_speaker_allocation {
172 int ca_index;
173 int speakers[8];
174
175 /* derived values, just for convenience */
176 int channels;
177 int spk_mask;
178};
179
180/*
181 * ALSA sequence is:
182 *
183 * surround40 surround41 surround50 surround51 surround71
184 * ch0 front left = = = =
185 * ch1 front right = = = =
186 * ch2 rear left = = = =
187 * ch3 rear right = = = =
188 * ch4 LFE center center center
189 * ch5 LFE LFE
190 * ch6 side left
191 * ch7 side right
192 *
193 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
194 */
195static int hdmi_channel_mapping[0x32][8] = {
196 /* stereo */
197 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
198 /* 2.1 */
199 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
200 /* Dolby Surround */
201 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
202 /* surround40 */
203 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
204 /* 4ch */
205 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
206 /* surround41 */
9396d317 207 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
079d88cc
WF		 208 /* surround50 */
209 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
210 /* surround51 */
211 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
212 /* 7.1 */
213 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
214};
215
216/*
217 * This is an ordered list!
218 *
219 * The preceding ones have better chances to be selected by
53d7d69d 220 * hdmi_channel_allocation().
079d88cc
WF		 221 */
222static struct cea_channel_speaker_allocation channel_allocations[] = {
223/* channel: 7 6 5 4 3 2 1 0 */
224{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
225 /* 2.1 */
226{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
227 /* Dolby Surround */
228{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
229 /* surround40 */
230{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
231 /* surround41 */
232{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
233 /* surround50 */
234{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
235 /* surround51 */
236{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
237 /* 6.1 */
238{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
239 /* surround71 */
240{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
241
242{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
243{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
244{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
245{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
246{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
247{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
248{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
249{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
250{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
251{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
252{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
253{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
254{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
255{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
256{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
257{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
258{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
259{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
260{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
261{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
262{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
263{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
264{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
265{ .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
266{ .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
267{ .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
268{ .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
269{ .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
270{ .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
271{ .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
272{ .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
273{ .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
274{ .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
275{ .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
276{ .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
277{ .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
278{ .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
279{ .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
280{ .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
281{ .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
282{ .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
283};
284
285
286/*
287 * HDMI routines
288 */
289
384a48d7 290static int pin_nid_to_pin_index(struct hdmi_spec *spec, hda_nid_t pin_nid)
079d88cc 291{
384a48d7 292 int pin_idx;
079d88cc 293
384a48d7
SW		 294 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
295 if (spec->pins[pin_idx].pin_nid == pin_nid)
296 return pin_idx;
079d88cc 297
384a48d7
SW		 298 snd_printk(KERN_WARNING "HDMI: pin nid %d not registered\n", pin_nid);
299 return -EINVAL;
300}
301
302static int hinfo_to_pin_index(struct hdmi_spec *spec,
303 struct hda_pcm_stream *hinfo)
304{
305 int pin_idx;
306
307 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
308 if (&spec->pcm_rec[pin_idx].stream[0] == hinfo)
309 return pin_idx;
310
311 snd_printk(KERN_WARNING "HDMI: hinfo %p not registered\n", hinfo);
312 return -EINVAL;
313}
314
315static int cvt_nid_to_cvt_index(struct hdmi_spec *spec, hda_nid_t cvt_nid)
316{
317 int cvt_idx;
318
319 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
320 if (spec->cvts[cvt_idx].cvt_nid == cvt_nid)
321 return cvt_idx;
322
323 snd_printk(KERN_WARNING "HDMI: cvt nid %d not registered\n", cvt_nid);
079d88cc
WF		 324 return -EINVAL;
325}
326
14bc52b8
PLB		 327static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
328 struct snd_ctl_elem_info *uinfo)
329{
330 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
331 struct hdmi_spec *spec;
332 int pin_idx;
333
334 spec = codec->spec;
335 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
336
337 pin_idx = kcontrol->private_value;
338 uinfo->count = spec->pins[pin_idx].sink_eld.eld_size;
339
340 return 0;
341}
342
343static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
344 struct snd_ctl_elem_value *ucontrol)
345{
346 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
347 struct hdmi_spec *spec;
348 int pin_idx;
349
350 spec = codec->spec;
351 pin_idx = kcontrol->private_value;
352
353 memcpy(ucontrol->value.bytes.data,
354 spec->pins[pin_idx].sink_eld.eld_buffer, ELD_MAX_SIZE);
355
356 return 0;
357}
358
359static struct snd_kcontrol_new eld_bytes_ctl = {
360 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
361 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
362 .name = "ELD",
363 .info = hdmi_eld_ctl_info,
364 .get = hdmi_eld_ctl_get,
365};
366
367static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
368 int device)
369{
370 struct snd_kcontrol *kctl;
371 struct hdmi_spec *spec = codec->spec;
372 int err;
373
374 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
375 if (!kctl)
376 return -ENOMEM;
377 kctl->private_value = pin_idx;
378 kctl->id.device = device;
379
380 err = snd_hda_ctl_add(codec, spec->pins[pin_idx].pin_nid, kctl);
381 if (err < 0)
382 return err;
383
384 return 0;
385}
386
079d88cc
WF		 387#ifdef BE_PARANOID
388static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
389 int *packet_index, int *byte_index)
390{
391 int val;
392
393 val = snd_hda_codec_read(codec, pin_nid, 0,
394 AC_VERB_GET_HDMI_DIP_INDEX, 0);
395
396 *packet_index = val >> 5;
397 *byte_index = val & 0x1f;
398}
399#endif
400
401static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
402 int packet_index, int byte_index)
403{
404 int val;
405
406 val = (packet_index << 5) | (byte_index & 0x1f);
407
408 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
409}
410
411static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
412 unsigned char val)
413{
414 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
415}
416
384a48d7 417static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc
WF		 418{
419 /* Unmute */
420 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
421 snd_hda_codec_write(codec, pin_nid, 0,
422 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
384a48d7 423 /* Disable pin out until stream is active*/
079d88cc 424 snd_hda_codec_write(codec, pin_nid, 0,
384a48d7 425 AC_VERB_SET_PIN_WIDGET_CONTROL, 0);
079d88cc
WF		 426}
427
384a48d7 428static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc 429{
384a48d7 430 return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
079d88cc
WF		 431 AC_VERB_GET_CVT_CHAN_COUNT, 0);
432}
433
434static void hdmi_set_channel_count(struct hda_codec *codec,
384a48d7 435 hda_nid_t cvt_nid, int chs)
079d88cc 436{
384a48d7
SW		 437 if (chs != hdmi_get_channel_count(codec, cvt_nid))
438 snd_hda_codec_write(codec, cvt_nid, 0,
079d88cc
WF		 439 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
440}
441
442
443/*
444 * Channel mapping routines
445 */
446
447/*
448 * Compute derived values in channel_allocations[].
449 */
450static void init_channel_allocations(void)
451{
452 int i, j;
453 struct cea_channel_speaker_allocation *p;
454
455 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
456 p = channel_allocations + i;
457 p->channels = 0;
458 p->spk_mask = 0;
459 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
460 if (p->speakers[j]) {
461 p->channels++;
462 p->spk_mask |= p->speakers[j];
463 }
464 }
465}
466
467/*
468 * The transformation takes two steps:
469 *
470 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
471 * spk_mask => (channel_allocations[]) => ai->CA
472 *
473 * TODO: it could select the wrong CA from multiple candidates.
474*/
384a48d7 475static int hdmi_channel_allocation(struct hdmi_eld *eld, int channels)
079d88cc 476{
079d88cc 477 int i;
53d7d69d 478 int ca = 0;
079d88cc 479 int spk_mask = 0;
079d88cc
WF		 480 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
481
482 /*
483 * CA defaults to 0 for basic stereo audio
484 */
485 if (channels <= 2)
486 return 0;
487
079d88cc
WF		 488 /*
489 * expand ELD's speaker allocation mask
490 *
491 * ELD tells the speaker mask in a compact(paired) form,
492 * expand ELD's notions to match the ones used by Audio InfoFrame.
493 */
494 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
495 if (eld->spk_alloc & (1 << i))
496 spk_mask |= eld_speaker_allocation_bits[i];
497 }
498
499 /* search for the first working match in the CA table */
500 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
501 if (channels == channel_allocations[i].channels &&
502 (spk_mask & channel_allocations[i].spk_mask) ==
503 channel_allocations[i].spk_mask) {
53d7d69d 504 ca = channel_allocations[i].ca_index;
079d88cc
WF		 505 break;
506 }
507 }
508
509 snd_print_channel_allocation(eld->spk_alloc, buf, sizeof(buf));
2abbf439 510 snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n",
53d7d69d 511 ca, channels, buf);
079d88cc 512
53d7d69d 513 return ca;
079d88cc
WF		 514}
515
516static void hdmi_debug_channel_mapping(struct hda_codec *codec,
517 hda_nid_t pin_nid)
518{
519#ifdef CONFIG_SND_DEBUG_VERBOSE
520 int i;
521 int slot;
522
523 for (i = 0; i < 8; i++) {
524 slot = snd_hda_codec_read(codec, pin_nid, 0,
525 AC_VERB_GET_HDMI_CHAN_SLOT, i);
526 printk(KERN_DEBUG "HDMI: ASP channel %d => slot %d\n",
527 slot >> 4, slot & 0xf);
528 }
529#endif
530}
531
532
533static void hdmi_setup_channel_mapping(struct hda_codec *codec,
534 hda_nid_t pin_nid,
53d7d69d 535 int ca)
079d88cc
WF		 536{
537 int i;
079d88cc
WF		 538 int err;
539
540 if (hdmi_channel_mapping[ca][1] == 0) {
541 for (i = 0; i < channel_allocations[ca].channels; i++)
542 hdmi_channel_mapping[ca][i] = i | (i << 4);
543 for (; i < 8; i++)
544 hdmi_channel_mapping[ca][i] = 0xf | (i << 4);
545 }
546
547 for (i = 0; i < 8; i++) {
548 err = snd_hda_codec_write(codec, pin_nid, 0,
549 AC_VERB_SET_HDMI_CHAN_SLOT,
550 hdmi_channel_mapping[ca][i]);
551 if (err) {
2abbf439
WF		 552 snd_printdd(KERN_NOTICE
553 "HDMI: channel mapping failed\n");
079d88cc
WF		 554 break;
555 }
556 }
557
558 hdmi_debug_channel_mapping(codec, pin_nid);
559}
560
561
562/*
563 * Audio InfoFrame routines
564 */
565
566/*
567 * Enable Audio InfoFrame Transmission
568 */
569static void hdmi_start_infoframe_trans(struct hda_codec *codec,
570 hda_nid_t pin_nid)
571{
572 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
573 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
574 AC_DIPXMIT_BEST);
575}
576
577/*
578 * Disable Audio InfoFrame Transmission
579 */
580static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
581 hda_nid_t pin_nid)
582{
583 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
584 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
585 AC_DIPXMIT_DISABLE);
586}
587
588static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
589{
590#ifdef CONFIG_SND_DEBUG_VERBOSE
591 int i;
592 int size;
593
594 size = snd_hdmi_get_eld_size(codec, pin_nid);
595 printk(KERN_DEBUG "HDMI: ELD buf size is %d\n", size);
596
597 for (i = 0; i < 8; i++) {
598 size = snd_hda_codec_read(codec, pin_nid, 0,
599 AC_VERB_GET_HDMI_DIP_SIZE, i);
600 printk(KERN_DEBUG "HDMI: DIP GP[%d] buf size is %d\n", i, size);
601 }
602#endif
603}
604
605static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
606{
607#ifdef BE_PARANOID
608 int i, j;
609 int size;
610 int pi, bi;
611 for (i = 0; i < 8; i++) {
612 size = snd_hda_codec_read(codec, pin_nid, 0,
613 AC_VERB_GET_HDMI_DIP_SIZE, i);
614 if (size == 0)
615 continue;
616
617 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
618 for (j = 1; j < 1000; j++) {
619 hdmi_write_dip_byte(codec, pin_nid, 0x0);
620 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
621 if (pi != i)
622 snd_printd(KERN_INFO "dip index %d: %d != %d\n",
623 bi, pi, i);
624 if (bi == 0) /* byte index wrapped around */
625 break;
626 }
627 snd_printd(KERN_INFO
628 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
629 i, size, j);
630 }
631#endif
632}
633
53d7d69d 634static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
079d88cc 635{
53d7d69d 636 u8 *bytes = (u8 *)hdmi_ai;
079d88cc
WF		 637 u8 sum = 0;
638 int i;
639
53d7d69d 640 hdmi_ai->checksum = 0;
079d88cc 641
53d7d69d 642 for (i = 0; i < sizeof(*hdmi_ai); i++)
079d88cc
WF		 643 sum += bytes[i];
644
53d7d69d 645 hdmi_ai->checksum = -sum;
079d88cc
WF		 646}
647
648static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
649 hda_nid_t pin_nid,
53d7d69d 650 u8 *dip, int size)
079d88cc 651{
079d88cc
WF		 652 int i;
653
654 hdmi_debug_dip_size(codec, pin_nid);
655 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
656
079d88cc 657 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d
WF		 658 for (i = 0; i < size; i++)
659 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
079d88cc
WF		 660}
661
662static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
53d7d69d 663 u8 *dip, int size)
079d88cc 664{
079d88cc
WF		 665 u8 val;
666 int i;
667
668 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
669 != AC_DIPXMIT_BEST)
670 return false;
671
672 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d 673 for (i = 0; i < size; i++) {
079d88cc
WF		 674 val = snd_hda_codec_read(codec, pin_nid, 0,
675 AC_VERB_GET_HDMI_DIP_DATA, 0);
53d7d69d 676 if (val != dip[i])
079d88cc
WF		 677 return false;
678 }
679
680 return true;
681}
682
384a48d7 683static void hdmi_setup_audio_infoframe(struct hda_codec *codec, int pin_idx,
079d88cc
WF		 684 struct snd_pcm_substream *substream)
685{
686 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 687 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
688 hda_nid_t pin_nid = per_pin->pin_nid;
53d7d69d 689 int channels = substream->runtime->channels;
384a48d7 690 struct hdmi_eld *eld;
53d7d69d 691 int ca;
2b203dbb 692 union audio_infoframe ai;
079d88cc 693
384a48d7
SW		 694 eld = &spec->pins[pin_idx].sink_eld;
695 if (!eld->monitor_present)
696 return;
079d88cc 697
384a48d7
SW		 698 ca = hdmi_channel_allocation(eld, channels);
699
700 memset(&ai, 0, sizeof(ai));
701 if (eld->conn_type == 0) { /* HDMI */
702 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
703
704 hdmi_ai->type = 0x84;
705 hdmi_ai->ver = 0x01;
706 hdmi_ai->len = 0x0a;
707 hdmi_ai->CC02_CT47 = channels - 1;
708 hdmi_ai->CA = ca;
709 hdmi_checksum_audio_infoframe(hdmi_ai);
710 } else if (eld->conn_type == 1) { /* DisplayPort */
711 struct dp_audio_infoframe *dp_ai = &ai.dp;
712
713 dp_ai->type = 0x84;
714 dp_ai->len = 0x1b;
715 dp_ai->ver = 0x11 << 2;
716 dp_ai->CC02_CT47 = channels - 1;
717 dp_ai->CA = ca;
718 } else {
719 snd_printd("HDMI: unknown connection type at pin %d\n",
720 pin_nid);
721 return;
722 }
53d7d69d 723
384a48d7
SW		 724 /*
725 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
726 * sizeof(*dp_ai) to avoid partial match/update problems when
727 * the user switches between HDMI/DP monitors.
728 */
729 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
730 sizeof(ai))) {
731 snd_printdd("hdmi_setup_audio_infoframe: "
732 "pin=%d channels=%d\n",
733 pin_nid,
734 channels);
735 hdmi_setup_channel_mapping(codec, pin_nid, ca);
736 hdmi_stop_infoframe_trans(codec, pin_nid);
737 hdmi_fill_audio_infoframe(codec, pin_nid,
738 ai.bytes, sizeof(ai));
739 hdmi_start_infoframe_trans(codec, pin_nid);
079d88cc
WF		 740 }
741}
742
743
744/*
745 * Unsolicited events
746 */
747
38faddb1
TI		 748static void hdmi_present_sense(struct hda_codec *codec, hda_nid_t pin_nid,
749 struct hdmi_eld *eld);
750
079d88cc
WF		 751static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
752{
753 struct hdmi_spec *spec = codec->spec;
5d44f927
SW		 754 int pin_nid = res >> AC_UNSOL_RES_TAG_SHIFT;
755 int pd = !!(res & AC_UNSOL_RES_PD);
079d88cc 756 int eldv = !!(res & AC_UNSOL_RES_ELDV);
384a48d7
SW		 757 int pin_idx;
758 struct hdmi_eld *eld;
079d88cc
WF		 759
760 printk(KERN_INFO
384a48d7
SW		 761 "HDMI hot plug event: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
762 codec->addr, pin_nid, pd, eldv);
079d88cc 763
384a48d7
SW		 764 pin_idx = pin_nid_to_pin_index(spec, pin_nid);
765 if (pin_idx < 0)
079d88cc 766 return;
384a48d7 767 eld = &spec->pins[pin_idx].sink_eld;
079d88cc 768
384a48d7
SW		 769 hdmi_present_sense(codec, pin_nid, eld);
770
771 /*
772 * HDMI sink's ELD info cannot always be retrieved for now, e.g.
773 * in console or for audio devices. Assume the highest speakers
774 * configuration, to _not_ prohibit multi-channel audio playback.
775 */
776 if (!eld->spk_alloc)
777 eld->spk_alloc = 0xffff;
079d88cc
WF		 778}
779
780static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
781{
782 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
783 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
784 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
785 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
786
787 printk(KERN_INFO
384a48d7
SW		 788 "HDMI CP event: CODEC=%d PIN=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
789 codec->addr,
079d88cc
WF		 790 tag,
791 subtag,
792 cp_state,
793 cp_ready);
794
795 /* TODO */
796 if (cp_state)
797 ;
798 if (cp_ready)
799 ;
800}
801
802
803static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
804{
805 struct hdmi_spec *spec = codec->spec;
806 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
807 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
808
384a48d7 809 if (pin_nid_to_pin_index(spec, tag) < 0) {
079d88cc
WF		 810 snd_printd(KERN_INFO "Unexpected HDMI event tag 0x%x\n", tag);
811 return;
812 }
813
814 if (subtag == 0)
815 hdmi_intrinsic_event(codec, res);
816 else
817 hdmi_non_intrinsic_event(codec, res);
818}
819
820/*
821 * Callbacks
822 */
823
92f10b3f
TI		 824/* HBR should be Non-PCM, 8 channels */
825#define is_hbr_format(format) \
826 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
827
384a48d7
SW		 828static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
829 hda_nid_t pin_nid, u32 stream_tag, int format)
079d88cc 830{
ea87d1c4
AH		 831 int pinctl;
832 int new_pinctl = 0;
ea87d1c4 833
384a48d7
SW		 834 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
835 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
ea87d1c4
AH		 836 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
837
838 new_pinctl = pinctl & ~AC_PINCTL_EPT;
92f10b3f 839 if (is_hbr_format(format))
ea87d1c4
AH		 840 new_pinctl |= AC_PINCTL_EPT_HBR;
841 else
842 new_pinctl |= AC_PINCTL_EPT_NATIVE;
843
844 snd_printdd("hdmi_setup_stream: "
845 "NID=0x%x, %spinctl=0x%x\n",
384a48d7 846 pin_nid,
ea87d1c4
AH		 847 pinctl == new_pinctl ? "" : "new-",
848 new_pinctl);
849
850 if (pinctl != new_pinctl)
384a48d7 851 snd_hda_codec_write(codec, pin_nid, 0,
ea87d1c4
AH		 852 AC_VERB_SET_PIN_WIDGET_CONTROL,
853 new_pinctl);
ea87d1c4 854
384a48d7 855 }
92f10b3f 856 if (is_hbr_format(format) && !new_pinctl) {
ea87d1c4
AH		 857 snd_printdd("hdmi_setup_stream: HBR is not supported\n");
858 return -EINVAL;
859 }
079d88cc 860
384a48d7 861 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
ea87d1c4 862 return 0;
079d88cc
WF		 863}
864
bbbe3390
TI		 865/*
866 * HDA PCM callbacks
867 */
868static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
869 struct hda_codec *codec,
870 struct snd_pcm_substream *substream)
871{
872 struct hdmi_spec *spec = codec->spec;
639cef0e 873 struct snd_pcm_runtime *runtime = substream->runtime;
384a48d7
SW		 874 int pin_idx, cvt_idx, mux_idx = 0;
875 struct hdmi_spec_per_pin *per_pin;
876 struct hdmi_eld *eld;
877 struct hdmi_spec_per_cvt *per_cvt = NULL;
878 int pinctl;
bbbe3390 879
384a48d7
SW		 880 /* Validate hinfo */
881 pin_idx = hinfo_to_pin_index(spec, hinfo);
882 if (snd_BUG_ON(pin_idx < 0))
bbbe3390 883 return -EINVAL;
384a48d7
SW		 884 per_pin = &spec->pins[pin_idx];
885 eld = &per_pin->sink_eld;
886
887 /* Dynamically assign converter to stream */
888 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
889 per_cvt = &spec->cvts[cvt_idx];
bbbe3390 890
384a48d7
SW		 891 /* Must not already be assigned */
892 if (per_cvt->assigned)
893 continue;
894 /* Must be in pin's mux's list of converters */
895 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
896 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
897 break;
898 /* Not in mux list */
899 if (mux_idx == per_pin->num_mux_nids)
900 continue;
901 break;
902 }
903 /* No free converters */
904 if (cvt_idx == spec->num_cvts)
905 return -ENODEV;
906
907 /* Claim converter */
908 per_cvt->assigned = 1;
909 hinfo->nid = per_cvt->cvt_nid;
910
911 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
912 AC_VERB_SET_CONNECT_SEL,
913 mux_idx);
914 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
915 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
916 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
917 AC_VERB_SET_PIN_WIDGET_CONTROL,
918 pinctl | PIN_OUT);
919 snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
bbbe3390 920
2def8172 921 /* Initially set the converter's capabilities */
384a48d7
SW		 922 hinfo->channels_min = per_cvt->channels_min;
923 hinfo->channels_max = per_cvt->channels_max;
924 hinfo->rates = per_cvt->rates;
925 hinfo->formats = per_cvt->formats;
926 hinfo->maxbps = per_cvt->maxbps;
2def8172 927
384a48d7 928 /* Restrict capabilities by ELD if this isn't disabled */
c3d52105 929 if (!static_hdmi_pcm && eld->eld_valid) {
2def8172 930 snd_hdmi_eld_update_pcm_info(eld, hinfo);
bbbe3390
TI		 931 if (hinfo->channels_min > hinfo->channels_max ||
932 !hinfo->rates || !hinfo->formats)
933 return -ENODEV;
bbbe3390 934 }
2def8172
SW		 935
936 /* Store the updated parameters */
639cef0e
TI		 937 runtime->hw.channels_min = hinfo->channels_min;
938 runtime->hw.channels_max = hinfo->channels_max;
939 runtime->hw.formats = hinfo->formats;
940 runtime->hw.rates = hinfo->rates;
4fe2ca14
TI		 941
942 snd_pcm_hw_constraint_step(substream->runtime, 0,
943 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
bbbe3390
TI		 944 return 0;
945}
946
079d88cc
WF		 947/*
948 * HDA/HDMI auto parsing
949 */
384a48d7 950static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
079d88cc
WF		 951{
952 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 953 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
954 hda_nid_t pin_nid = per_pin->pin_nid;
079d88cc
WF		 955
956 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
957 snd_printk(KERN_WARNING
958 "HDMI: pin %d wcaps %#x "
959 "does not support connection list\n",
960 pin_nid, get_wcaps(codec, pin_nid));
961 return -EINVAL;
962 }
963
384a48d7
SW		 964 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
965 per_pin->mux_nids,
966 HDA_MAX_CONNECTIONS);
079d88cc
WF		 967
968 return 0;
969}
970
971static void hdmi_present_sense(struct hda_codec *codec, hda_nid_t pin_nid,
972 struct hdmi_eld *eld)
973{
5d44f927
SW		 974 /*
975 * Always execute a GetPinSense verb here, even when called from
976 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
977 * response's PD bit is not the real PD value, but indicates that
978 * the real PD value changed. An older version of the HD-audio
979 * specification worked this way. Hence, we just ignore the data in
980 * the unsolicited response to avoid custom WARs.
981 */
079d88cc
WF		 982 int present = snd_hda_pin_sense(codec, pin_nid);
983
5d44f927
SW		 984 memset(eld, 0, sizeof(*eld));
985
079d88cc 986 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
5d44f927
SW		 987 if (eld->monitor_present)
988 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
989 else
990 eld->eld_valid = 0;
079d88cc 991
5d44f927 992 printk(KERN_INFO
384a48d7
SW		 993 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
994 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
5d44f927
SW		 995
996 if (eld->eld_valid)
997 if (!snd_hdmi_get_eld(eld, codec, pin_nid))
998 snd_hdmi_show_eld(eld);
999
1000 snd_hda_input_jack_report(codec, pin_nid);
079d88cc
WF		 1001}
1002
1003static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1004{
1005 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1006 unsigned int caps, config;
1007 int pin_idx;
1008 struct hdmi_spec_per_pin *per_pin;
1009 struct hdmi_eld *eld;
07acecc1 1010 int err;
079d88cc 1011
384a48d7
SW		 1012 caps = snd_hda_param_read(codec, pin_nid, AC_PAR_PIN_CAP);
1013 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1014 return 0;
1015
1016 config = snd_hda_codec_read(codec, pin_nid, 0,
1017 AC_VERB_GET_CONFIG_DEFAULT, 0);
1018 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1019 return 0;
1020
1021 if (snd_BUG_ON(spec->num_pins >= MAX_HDMI_PINS))
3eaead57 1022 return -E2BIG;
384a48d7
SW		 1023
1024 pin_idx = spec->num_pins;
1025 per_pin = &spec->pins[pin_idx];
1026 eld = &per_pin->sink_eld;
1027
1028 per_pin->pin_nid = pin_nid;
079d88cc 1029
384a48d7
SW		 1030 err = hdmi_read_pin_conn(codec, pin_idx);
1031 if (err < 0)
1032 return err;
079d88cc 1033
079d88cc
WF		 1034 spec->num_pins++;
1035
384a48d7 1036 return 0;
079d88cc
WF		 1037}
1038
384a48d7 1039static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc
WF		 1040{
1041 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1042 int cvt_idx;
1043 struct hdmi_spec_per_cvt *per_cvt;
1044 unsigned int chans;
1045 int err;
079d88cc 1046
116dcde6
DH		 1047 if (snd_BUG_ON(spec->num_cvts >= MAX_HDMI_CVTS))
1048 return -E2BIG;
1049
384a48d7
SW		 1050 chans = get_wcaps(codec, cvt_nid);
1051 chans = get_wcaps_channels(chans);
1052
1053 cvt_idx = spec->num_cvts;
1054 per_cvt = &spec->cvts[cvt_idx];
1055
1056 per_cvt->cvt_nid = cvt_nid;
1057 per_cvt->channels_min = 2;
1058 if (chans <= 16)
1059 per_cvt->channels_max = chans;
1060
1061 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1062 &per_cvt->rates,
1063 &per_cvt->formats,
1064 &per_cvt->maxbps);
1065 if (err < 0)
1066 return err;
1067
079d88cc
WF		 1068 spec->num_cvts++;
1069
1070 return 0;
1071}
1072
1073static int hdmi_parse_codec(struct hda_codec *codec)
1074{
1075 hda_nid_t nid;
1076 int i, nodes;
1077
1078 nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid);
1079 if (!nid || nodes < 0) {
1080 snd_printk(KERN_WARNING "HDMI: failed to get afg sub nodes\n");
1081 return -EINVAL;
1082 }
1083
1084 for (i = 0; i < nodes; i++, nid++) {
1085 unsigned int caps;
1086 unsigned int type;
1087
1088 caps = snd_hda_param_read(codec, nid, AC_PAR_AUDIO_WIDGET_CAP);
1089 type = get_wcaps_type(caps);
1090
1091 if (!(caps & AC_WCAP_DIGITAL))
1092 continue;
1093
1094 switch (type) {
1095 case AC_WID_AUD_OUT:
384a48d7 1096 hdmi_add_cvt(codec, nid);
079d88cc
WF		 1097 break;
1098 case AC_WID_PIN:
3eaead57 1099 hdmi_add_pin(codec, nid);
079d88cc
WF		 1100 break;
1101 }
1102 }
1103
1104 /*
1105 * G45/IbexPeak don't support EPSS: the unsolicited pin hot plug event
1106 * can be lost and presence sense verb will become inaccurate if the
1107 * HDA link is powered off at hot plug or hw initialization time.
1108 */
1109#ifdef CONFIG_SND_HDA_POWER_SAVE
1110 if (!(snd_hda_param_read(codec, codec->afg, AC_PAR_POWER_STATE) &
1111 AC_PWRST_EPSS))
1112 codec->bus->power_keep_link_on = 1;
1113#endif
1114
1115 return 0;
1116}
1117
84eb01be
TI		 1118/*
1119 */
384a48d7 1120static char *generic_hdmi_pcm_names[MAX_HDMI_PINS] = {
84eb01be
TI		 1121 "HDMI 0",
1122 "HDMI 1",
1123 "HDMI 2",
73926656 1124 "HDMI 3",
84eb01be
TI		 1125};
1126
1127/*
1128 * HDMI callbacks
1129 */
1130
1131static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1132 struct hda_codec *codec,
1133 unsigned int stream_tag,
1134 unsigned int format,
1135 struct snd_pcm_substream *substream)
1136{
384a48d7
SW		 1137 hda_nid_t cvt_nid = hinfo->nid;
1138 struct hdmi_spec *spec = codec->spec;
1139 int pin_idx = hinfo_to_pin_index(spec, hinfo);
1140 hda_nid_t pin_nid = spec->pins[pin_idx].pin_nid;
1141
1142 hdmi_set_channel_count(codec, cvt_nid, substream->runtime->channels);
84eb01be 1143
384a48d7 1144 hdmi_setup_audio_infoframe(codec, pin_idx, substream);
84eb01be 1145
384a48d7 1146 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
84eb01be
TI		 1147}
1148
384a48d7
SW		 1149static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1150 struct hda_codec *codec,
1151 struct snd_pcm_substream *substream)
1152{
1153 struct hdmi_spec *spec = codec->spec;
1154 int cvt_idx, pin_idx;
1155 struct hdmi_spec_per_cvt *per_cvt;
1156 struct hdmi_spec_per_pin *per_pin;
1157 int pinctl;
1158
1159 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1160
1161 if (hinfo->nid) {
1162 cvt_idx = cvt_nid_to_cvt_index(spec, hinfo->nid);
1163 if (snd_BUG_ON(cvt_idx < 0))
1164 return -EINVAL;
1165 per_cvt = &spec->cvts[cvt_idx];
1166
1167 snd_BUG_ON(!per_cvt->assigned);
1168 per_cvt->assigned = 0;
1169 hinfo->nid = 0;
1170
1171 pin_idx = hinfo_to_pin_index(spec, hinfo);
1172 if (snd_BUG_ON(pin_idx < 0))
1173 return -EINVAL;
1174 per_pin = &spec->pins[pin_idx];
1175
1176 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1177 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1178 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1179 AC_VERB_SET_PIN_WIDGET_CONTROL,
1180 pinctl & ~PIN_OUT);
1181 snd_hda_spdif_ctls_unassign(codec, pin_idx);
1182 }
1183
1184 return 0;
1185}
1186
1187static const struct hda_pcm_ops generic_ops = {
1188 .open = hdmi_pcm_open,
1189 .prepare = generic_hdmi_playback_pcm_prepare,
1190 .cleanup = generic_hdmi_playback_pcm_cleanup,
84eb01be
TI		 1191};
1192
1193static int generic_hdmi_build_pcms(struct hda_codec *codec)
1194{
1195 struct hdmi_spec *spec = codec->spec;
384a48d7 1196 int pin_idx;
84eb01be 1197
384a48d7
SW		 1198 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1199 struct hda_pcm *info;
84eb01be
TI		 1200 struct hda_pcm_stream *pstr;
1201
384a48d7
SW		 1202 info = &spec->pcm_rec[pin_idx];
1203 info->name = generic_hdmi_pcm_names[pin_idx];
84eb01be 1204 info->pcm_type = HDA_PCM_TYPE_HDMI;
384a48d7 1205
84eb01be 1206 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
384a48d7
SW		 1207 pstr->substreams = 1;
1208 pstr->ops = generic_ops;
1209 /* other pstr fields are set in open */
84eb01be
TI		 1210 }
1211
384a48d7
SW		 1212 codec->num_pcms = spec->num_pins;
1213 codec->pcm_info = spec->pcm_rec;
1214
84eb01be
TI		 1215 return 0;
1216}
1217
0b6c49b5
DH		 1218static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
1219{
1220 int err;
1221 char hdmi_str[32];
1222 struct hdmi_spec *spec = codec->spec;
1223 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
1224 int pcmdev = spec->pcm_rec[pin_idx].device;
1225
1226 snprintf(hdmi_str, sizeof(hdmi_str), "HDMI/DP,pcm=%d", pcmdev);
1227
1228 err = snd_hda_input_jack_add(codec, per_pin->pin_nid,
1229 SND_JACK_VIDEOOUT, pcmdev > 0 ? hdmi_str : NULL);
1230 if (err < 0)
1231 return err;
1232
1233 hdmi_present_sense(codec, per_pin->pin_nid, &per_pin->sink_eld);
1234 return 0;
1235}
1236
84eb01be
TI		 1237static int generic_hdmi_build_controls(struct hda_codec *codec)
1238{
1239 struct hdmi_spec *spec = codec->spec;
1240 int err;
384a48d7 1241 int pin_idx;
84eb01be 1242
384a48d7
SW		 1243 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1244 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
0b6c49b5
DH		 1245
1246 err = generic_hdmi_build_jack(codec, pin_idx);
1247 if (err < 0)
1248 return err;
1249
384a48d7
SW		 1250 err = snd_hda_create_spdif_out_ctls(codec,
1251 per_pin->pin_nid,
1252 per_pin->mux_nids[0]);
84eb01be
TI		 1253 if (err < 0)
1254 return err;
384a48d7 1255 snd_hda_spdif_ctls_unassign(codec, pin_idx);
14bc52b8
PLB		 1256
1257 /* add control for ELD Bytes */
1258 err = hdmi_create_eld_ctl(codec,
1259 pin_idx,
1260 spec->pcm_rec[pin_idx].device);
1261
1262 if (err < 0)
1263 return err;
84eb01be
TI		 1264 }
1265
1266 return 0;
1267}
1268
1269static int generic_hdmi_init(struct hda_codec *codec)
1270{
1271 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1272 int pin_idx;
1273
1274 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1275 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
1276 hda_nid_t pin_nid = per_pin->pin_nid;
1277 struct hdmi_eld *eld = &per_pin->sink_eld;
84eb01be 1278
384a48d7
SW		 1279 hdmi_init_pin(codec, pin_nid);
1280 snd_hda_codec_write(codec, pin_nid, 0,
84eb01be 1281 AC_VERB_SET_UNSOLICITED_ENABLE,
384a48d7
SW		 1282 AC_USRSP_EN | pin_nid);
1283
1284 snd_hda_eld_proc_new(codec, eld, pin_idx);
84eb01be
TI		 1285 }
1286 return 0;
1287}
1288
1289static void generic_hdmi_free(struct hda_codec *codec)
1290{
1291 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1292 int pin_idx;
1293
1294 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1295 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
1296 struct hdmi_eld *eld = &per_pin->sink_eld;
84eb01be 1297
384a48d7
SW		 1298 snd_hda_eld_proc_free(codec, eld);
1299 }
07acecc1 1300 snd_hda_input_jack_free(codec);
84eb01be
TI		 1301
1302 kfree(spec);
1303}
1304
fb79e1e0 1305static const struct hda_codec_ops generic_hdmi_patch_ops = {
84eb01be
TI		 1306 .init = generic_hdmi_init,
1307 .free = generic_hdmi_free,
1308 .build_pcms = generic_hdmi_build_pcms,
1309 .build_controls = generic_hdmi_build_controls,
1310 .unsol_event = hdmi_unsol_event,
1311};
1312
1313static int patch_generic_hdmi(struct hda_codec *codec)
1314{
1315 struct hdmi_spec *spec;
84eb01be
TI		 1316
1317 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1318 if (spec == NULL)
1319 return -ENOMEM;
1320
1321 codec->spec = spec;
1322 if (hdmi_parse_codec(codec) < 0) {
1323 codec->spec = NULL;
1324 kfree(spec);
1325 return -EINVAL;
1326 }
1327 codec->patch_ops = generic_hdmi_patch_ops;
1328
84eb01be
TI		 1329 init_channel_allocations();
1330
1331 return 0;
1332}
1333
3aaf8980
SW		 1334/*
1335 * Shared non-generic implementations
1336 */
1337
1338static int simple_playback_build_pcms(struct hda_codec *codec)
1339{
1340 struct hdmi_spec *spec = codec->spec;
1341 struct hda_pcm *info = spec->pcm_rec;
1342 int i;
1343
1344 codec->num_pcms = spec->num_cvts;
1345 codec->pcm_info = info;
1346
1347 for (i = 0; i < codec->num_pcms; i++, info++) {
1348 unsigned int chans;
1349 struct hda_pcm_stream *pstr;
1350
384a48d7 1351 chans = get_wcaps(codec, spec->cvts[i].cvt_nid);
3aaf8980
SW		 1352 chans = get_wcaps_channels(chans);
1353
1354 info->name = generic_hdmi_pcm_names[i];
1355 info->pcm_type = HDA_PCM_TYPE_HDMI;
1356 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
1357 snd_BUG_ON(!spec->pcm_playback);
1358 *pstr = *spec->pcm_playback;
384a48d7 1359 pstr->nid = spec->cvts[i].cvt_nid;
3aaf8980
SW		 1360 if (pstr->channels_max <= 2 && chans && chans <= 16)
1361 pstr->channels_max = chans;
1362 }
1363
1364 return 0;
1365}
1366
1367static int simple_playback_build_controls(struct hda_codec *codec)
1368{
1369 struct hdmi_spec *spec = codec->spec;
1370 int err;
1371 int i;
1372
1373 for (i = 0; i < codec->num_pcms; i++) {
1374 err = snd_hda_create_spdif_out_ctls(codec,
384a48d7
SW		 1375 spec->cvts[i].cvt_nid,
1376 spec->cvts[i].cvt_nid);
3aaf8980
SW		 1377 if (err < 0)
1378 return err;
1379 }
1380
1381 return 0;
1382}
1383
1384static void simple_playback_free(struct hda_codec *codec)
1385{
1386 struct hdmi_spec *spec = codec->spec;
1387
1388 kfree(spec);
1389}
1390
84eb01be
TI		 1391/*
1392 * Nvidia specific implementations
1393 */
1394
1395#define Nv_VERB_SET_Channel_Allocation 0xF79
1396#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
1397#define Nv_VERB_SET_Audio_Protection_On 0xF98
1398#define Nv_VERB_SET_Audio_Protection_Off 0xF99
1399
1400#define nvhdmi_master_con_nid_7x 0x04
1401#define nvhdmi_master_pin_nid_7x 0x05
1402
fb79e1e0 1403static const hda_nid_t nvhdmi_con_nids_7x[4] = {
84eb01be
TI		 1404 /*front, rear, clfe, rear_surr */
1405 0x6, 0x8, 0xa, 0xc,
1406};
1407
fb79e1e0 1408static const struct hda_verb nvhdmi_basic_init_7x[] = {
84eb01be
TI		 1409 /* set audio protect on */
1410 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
1411 /* enable digital output on pin widget */
1412 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1413 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1414 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1415 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1416 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1417 {} /* terminator */
1418};
1419
1420#ifdef LIMITED_RATE_FMT_SUPPORT
1421/* support only the safe format and rate */
1422#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
1423#define SUPPORTED_MAXBPS 16
1424#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
1425#else
1426/* support all rates and formats */
1427#define SUPPORTED_RATES \
1428 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
1429 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
1430 SNDRV_PCM_RATE_192000)
1431#define SUPPORTED_MAXBPS 24
1432#define SUPPORTED_FORMATS \
1433 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
1434#endif
1435
1436static int nvhdmi_7x_init(struct hda_codec *codec)
1437{
1438 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x);
1439 return 0;
1440}
1441
393004b2
ND		 1442static unsigned int channels_2_6_8[] = {
1443 2, 6, 8
1444};
1445
1446static unsigned int channels_2_8[] = {
1447 2, 8
1448};
1449
1450static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
1451 .count = ARRAY_SIZE(channels_2_6_8),
1452 .list = channels_2_6_8,
1453 .mask = 0,
1454};
1455
1456static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
1457 .count = ARRAY_SIZE(channels_2_8),
1458 .list = channels_2_8,
1459 .mask = 0,
1460};
1461
84eb01be
TI		 1462static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
1463 struct hda_codec *codec,
1464 struct snd_pcm_substream *substream)
1465{
1466 struct hdmi_spec *spec = codec->spec;
393004b2
ND		 1467 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
1468
1469 switch (codec->preset->id) {
1470 case 0x10de0002:
1471 case 0x10de0003:
1472 case 0x10de0005:
1473 case 0x10de0006:
1474 hw_constraints_channels = &hw_constraints_2_8_channels;
1475 break;
1476 case 0x10de0007:
1477 hw_constraints_channels = &hw_constraints_2_6_8_channels;
1478 break;
1479 default:
1480 break;
1481 }
1482
1483 if (hw_constraints_channels != NULL) {
1484 snd_pcm_hw_constraint_list(substream->runtime, 0,
1485 SNDRV_PCM_HW_PARAM_CHANNELS,
1486 hw_constraints_channels);
ad09fc9d
TI		 1487 } else {
1488 snd_pcm_hw_constraint_step(substream->runtime, 0,
1489 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
393004b2
ND		 1490 }
1491
84eb01be
TI		 1492 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
1493}
1494
1495static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
1496 struct hda_codec *codec,
1497 struct snd_pcm_substream *substream)
1498{
1499 struct hdmi_spec *spec = codec->spec;
1500 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
1501}
1502
1503static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1504 struct hda_codec *codec,
1505 unsigned int stream_tag,
1506 unsigned int format,
1507 struct snd_pcm_substream *substream)
1508{
1509 struct hdmi_spec *spec = codec->spec;
1510 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
1511 stream_tag, format, substream);
1512}
1513
1f348522
AP		 1514static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
1515 int channels)
1516{
1517 unsigned int chanmask;
1518 int chan = channels ? (channels - 1) : 1;
1519
1520 switch (channels) {
1521 default:
1522 case 0:
1523 case 2:
1524 chanmask = 0x00;
1525 break;
1526 case 4:
1527 chanmask = 0x08;
1528 break;
1529 case 6:
1530 chanmask = 0x0b;
1531 break;
1532 case 8:
1533 chanmask = 0x13;
1534 break;
1535 }
1536
1537 /* Set the audio infoframe channel allocation and checksum fields. The
1538 * channel count is computed implicitly by the hardware. */
1539 snd_hda_codec_write(codec, 0x1, 0,
1540 Nv_VERB_SET_Channel_Allocation, chanmask);
1541
1542 snd_hda_codec_write(codec, 0x1, 0,
1543 Nv_VERB_SET_Info_Frame_Checksum,
1544 (0x71 - chan - chanmask));
1545}
1546
84eb01be
TI		 1547static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
1548 struct hda_codec *codec,
1549 struct snd_pcm_substream *substream)
1550{
1551 struct hdmi_spec *spec = codec->spec;
1552 int i;
1553
1554 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
1555 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
1556 for (i = 0; i < 4; i++) {
1557 /* set the stream id */
1558 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
1559 AC_VERB_SET_CHANNEL_STREAMID, 0);
1560 /* set the stream format */
1561 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
1562 AC_VERB_SET_STREAM_FORMAT, 0);
1563 }
1564
1f348522
AP		 1565 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
1566 * streams are disabled. */
1567 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
1568
84eb01be
TI		 1569 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
1570}
1571
1572static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
1573 struct hda_codec *codec,
1574 unsigned int stream_tag,
1575 unsigned int format,
1576 struct snd_pcm_substream *substream)
1577{
1578 int chs;
1f348522 1579 unsigned int dataDCC1, dataDCC2, channel_id;
84eb01be 1580 int i;
7c935976
SW		 1581 struct hdmi_spec *spec = codec->spec;
1582 struct hda_spdif_out *spdif =
384a48d7 1583 snd_hda_spdif_out_of_nid(codec, spec->cvts[0].cvt_nid);
84eb01be
TI		 1584
1585 mutex_lock(&codec->spdif_mutex);
1586
1587 chs = substream->runtime->channels;
84eb01be 1588
84eb01be
TI		 1589 dataDCC1 = AC_DIG1_ENABLE | AC_DIG1_COPYRIGHT;
1590 dataDCC2 = 0x2;
1591
84eb01be 1592 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
7c935976 1593 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 1594 snd_hda_codec_write(codec,
1595 nvhdmi_master_con_nid_7x,
1596 0,
1597 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 1598 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 1599
1600 /* set the stream id */
1601 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
1602 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
1603
1604 /* set the stream format */
1605 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
1606 AC_VERB_SET_STREAM_FORMAT, format);
1607
1608 /* turn on again (if needed) */
1609 /* enable and set the channel status audio/data flag */
7c935976 1610 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 1611 snd_hda_codec_write(codec,
1612 nvhdmi_master_con_nid_7x,
1613 0,
1614 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 1615 spdif->ctls & 0xff);
84eb01be
TI		 1616 snd_hda_codec_write(codec,
1617 nvhdmi_master_con_nid_7x,
1618 0,
1619 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
1620 }
1621
1622 for (i = 0; i < 4; i++) {
1623 if (chs == 2)
1624 channel_id = 0;
1625 else
1626 channel_id = i * 2;
1627
1628 /* turn off SPDIF once;
1629 *otherwise the IEC958 bits won't be updated
1630 */
1631 if (codec->spdif_status_reset &&
7c935976 1632 (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 1633 snd_hda_codec_write(codec,
1634 nvhdmi_con_nids_7x[i],
1635 0,
1636 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 1637 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 1638 /* set the stream id */
1639 snd_hda_codec_write(codec,
1640 nvhdmi_con_nids_7x[i],
1641 0,
1642 AC_VERB_SET_CHANNEL_STREAMID,
1643 (stream_tag << 4) | channel_id);
1644 /* set the stream format */
1645 snd_hda_codec_write(codec,
1646 nvhdmi_con_nids_7x[i],
1647 0,
1648 AC_VERB_SET_STREAM_FORMAT,
1649 format);
1650 /* turn on again (if needed) */
1651 /* enable and set the channel status audio/data flag */
1652 if (codec->spdif_status_reset &&
7c935976 1653 (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 1654 snd_hda_codec_write(codec,
1655 nvhdmi_con_nids_7x[i],
1656 0,
1657 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 1658 spdif->ctls & 0xff);
84eb01be
TI		 1659 snd_hda_codec_write(codec,
1660 nvhdmi_con_nids_7x[i],
1661 0,
1662 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
1663 }
1664 }
1665
1f348522 1666 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
84eb01be
TI		 1667
1668 mutex_unlock(&codec->spdif_mutex);
1669 return 0;
1670}
1671
fb79e1e0 1672static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
84eb01be
TI		 1673 .substreams = 1,
1674 .channels_min = 2,
1675 .channels_max = 8,
1676 .nid = nvhdmi_master_con_nid_7x,
1677 .rates = SUPPORTED_RATES,
1678 .maxbps = SUPPORTED_MAXBPS,
1679 .formats = SUPPORTED_FORMATS,
1680 .ops = {
1681 .open = simple_playback_pcm_open,
1682 .close = nvhdmi_8ch_7x_pcm_close,
1683 .prepare = nvhdmi_8ch_7x_pcm_prepare
1684 },
1685};
1686
fb79e1e0 1687static const struct hda_pcm_stream nvhdmi_pcm_playback_2ch = {
84eb01be
TI		 1688 .substreams = 1,
1689 .channels_min = 2,
1690 .channels_max = 2,
1691 .nid = nvhdmi_master_con_nid_7x,
1692 .rates = SUPPORTED_RATES,
1693 .maxbps = SUPPORTED_MAXBPS,
1694 .formats = SUPPORTED_FORMATS,
1695 .ops = {
1696 .open = simple_playback_pcm_open,
1697 .close = simple_playback_pcm_close,
1698 .prepare = simple_playback_pcm_prepare
1699 },
1700};
1701
fb79e1e0 1702static const struct hda_codec_ops nvhdmi_patch_ops_8ch_7x = {
3aaf8980
SW		 1703 .build_controls = simple_playback_build_controls,
1704 .build_pcms = simple_playback_build_pcms,
84eb01be 1705 .init = nvhdmi_7x_init,
3aaf8980 1706 .free = simple_playback_free,
84eb01be
TI		 1707};
1708
fb79e1e0 1709static const struct hda_codec_ops nvhdmi_patch_ops_2ch = {
3aaf8980
SW		 1710 .build_controls = simple_playback_build_controls,
1711 .build_pcms = simple_playback_build_pcms,
84eb01be 1712 .init = nvhdmi_7x_init,
3aaf8980 1713 .free = simple_playback_free,
84eb01be
TI		 1714};
1715
84eb01be
TI		 1716static int patch_nvhdmi_2ch(struct hda_codec *codec)
1717{
1718 struct hdmi_spec *spec;
1719
1720 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1721 if (spec == NULL)
1722 return -ENOMEM;
1723
1724 codec->spec = spec;
1725
1726 spec->multiout.num_dacs = 0; /* no analog */
1727 spec->multiout.max_channels = 2;
1728 spec->multiout.dig_out_nid = nvhdmi_master_con_nid_7x;
84eb01be 1729 spec->num_cvts = 1;
384a48d7 1730 spec->cvts[0].cvt_nid = nvhdmi_master_con_nid_7x;
84eb01be
TI		 1731 spec->pcm_playback = &nvhdmi_pcm_playback_2ch;
1732
1733 codec->patch_ops = nvhdmi_patch_ops_2ch;
1734
1735 return 0;
1736}
1737
1738static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
1739{
1740 struct hdmi_spec *spec;
1741 int err = patch_nvhdmi_2ch(codec);
1742
1743 if (err < 0)
1744 return err;
1745 spec = codec->spec;
1746 spec->multiout.max_channels = 8;
1747 spec->pcm_playback = &nvhdmi_pcm_playback_8ch_7x;
1748 codec->patch_ops = nvhdmi_patch_ops_8ch_7x;
1f348522
AP		 1749
1750 /* Initialize the audio infoframe channel mask and checksum to something
1751 * valid */
1752 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
1753
84eb01be
TI		 1754 return 0;
1755}
1756
1757/*
1758 * ATI-specific implementations
1759 *
1760 * FIXME: we may omit the whole this and use the generic code once after
1761 * it's confirmed to work.
1762 */
1763
1764#define ATIHDMI_CVT_NID 0x02 /* audio converter */
1765#define ATIHDMI_PIN_NID 0x03 /* HDMI output pin */
1766
1767static int atihdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1768 struct hda_codec *codec,
1769 unsigned int stream_tag,
1770 unsigned int format,
1771 struct snd_pcm_substream *substream)
1772{
1773 struct hdmi_spec *spec = codec->spec;
1774 int chans = substream->runtime->channels;
1775 int i, err;
1776
1777 err = simple_playback_pcm_prepare(hinfo, codec, stream_tag, format,
1778 substream);
1779 if (err < 0)
1780 return err;
384a48d7
SW		 1781 snd_hda_codec_write(codec, spec->cvts[0].cvt_nid, 0,
1782 AC_VERB_SET_CVT_CHAN_COUNT, chans - 1);
84eb01be
TI		 1783 /* FIXME: XXX */
1784 for (i = 0; i < chans; i++) {
384a48d7 1785 snd_hda_codec_write(codec, spec->cvts[0].cvt_nid, 0,
84eb01be
TI		 1786 AC_VERB_SET_HDMI_CHAN_SLOT,
1787 (i << 4) | i);
1788 }
1789 return 0;
1790}
1791
fb79e1e0 1792static const struct hda_pcm_stream atihdmi_pcm_digital_playback = {
84eb01be
TI		 1793 .substreams = 1,
1794 .channels_min = 2,
1795 .channels_max = 2,
1796 .nid = ATIHDMI_CVT_NID,
1797 .ops = {
1798 .open = simple_playback_pcm_open,
1799 .close = simple_playback_pcm_close,
1800 .prepare = atihdmi_playback_pcm_prepare
1801 },
1802};
1803
fb79e1e0 1804static const struct hda_verb atihdmi_basic_init[] = {
84eb01be
TI		 1805 /* enable digital output on pin widget */
1806 { 0x03, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT },
1807 {} /* terminator */
1808};
1809
1810static int atihdmi_init(struct hda_codec *codec)
1811{
1812 struct hdmi_spec *spec = codec->spec;
1813
1814 snd_hda_sequence_write(codec, atihdmi_basic_init);
1815 /* SI codec requires to unmute the pin */
384a48d7
SW		 1816 if (get_wcaps(codec, spec->pins[0].pin_nid) & AC_WCAP_OUT_AMP)
1817 snd_hda_codec_write(codec, spec->pins[0].pin_nid, 0,
84eb01be
TI		 1818 AC_VERB_SET_AMP_GAIN_MUTE,
1819 AMP_OUT_UNMUTE);
1820 return 0;
1821}
1822
fb79e1e0 1823static const struct hda_codec_ops atihdmi_patch_ops = {
3aaf8980
SW		 1824 .build_controls = simple_playback_build_controls,
1825 .build_pcms = simple_playback_build_pcms,
84eb01be 1826 .init = atihdmi_init,
3aaf8980 1827 .free = simple_playback_free,
84eb01be
TI		 1828};
1829
1830
1831static int patch_atihdmi(struct hda_codec *codec)
1832{
1833 struct hdmi_spec *spec;
1834
1835 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1836 if (spec == NULL)
1837 return -ENOMEM;
1838
1839 codec->spec = spec;
1840
1841 spec->multiout.num_dacs = 0; /* no analog */
1842 spec->multiout.max_channels = 2;
1843 spec->multiout.dig_out_nid = ATIHDMI_CVT_NID;
1844 spec->num_cvts = 1;
384a48d7
SW		 1845 spec->cvts[0].cvt_nid = ATIHDMI_CVT_NID;
1846 spec->pins[0].pin_nid = ATIHDMI_PIN_NID;
84eb01be
TI		 1847 spec->pcm_playback = &atihdmi_pcm_digital_playback;
1848
1849 codec->patch_ops = atihdmi_patch_ops;
1850
1851 return 0;
1852}
1853
1854
1855/*
1856 * patch entries
1857 */
fb79e1e0 1858static const struct hda_codec_preset snd_hda_preset_hdmi[] = {
84eb01be
TI		 1859{ .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
1860{ .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
1861{ .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
36e9c135 1862{ .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 1863{ .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
1864{ .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
1865{ .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
1866{ .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
1867{ .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
1868{ .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
1869{ .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
1870{ .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
5d44f927
SW		 1871{ .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_generic_hdmi },
1872{ .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_generic_hdmi },
1873{ .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_generic_hdmi },
1874{ .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_generic_hdmi },
1875{ .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_generic_hdmi },
1876{ .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_generic_hdmi },
1877{ .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_generic_hdmi },
1878{ .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_generic_hdmi },
1879{ .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_generic_hdmi },
1880{ .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_generic_hdmi },
1881{ .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_generic_hdmi },
c8900a0f 1882/* 17 is known to be absent */
5d44f927
SW		 1883{ .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_generic_hdmi },
1884{ .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_generic_hdmi },
1885{ .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_generic_hdmi },
1886{ .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_generic_hdmi },
1887{ .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_generic_hdmi },
1888{ .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_generic_hdmi },
1889{ .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_generic_hdmi },
1890{ .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_generic_hdmi },
1891{ .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_generic_hdmi },
1892{ .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_generic_hdmi },
84eb01be
TI		 1893{ .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
1894{ .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
1895{ .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
1896{ .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
1897{ .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
1898{ .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
1899{ .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
1900{ .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
591e610d 1901{ .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 1902{ .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
1903{} /* terminator */
1904};
1905
1906MODULE_ALIAS("snd-hda-codec-id:1002793c");
1907MODULE_ALIAS("snd-hda-codec-id:10027919");
1908MODULE_ALIAS("snd-hda-codec-id:1002791a");
1909MODULE_ALIAS("snd-hda-codec-id:1002aa01");
1910MODULE_ALIAS("snd-hda-codec-id:10951390");
1911MODULE_ALIAS("snd-hda-codec-id:10951392");
1912MODULE_ALIAS("snd-hda-codec-id:10de0002");
1913MODULE_ALIAS("snd-hda-codec-id:10de0003");
1914MODULE_ALIAS("snd-hda-codec-id:10de0005");
1915MODULE_ALIAS("snd-hda-codec-id:10de0006");
1916MODULE_ALIAS("snd-hda-codec-id:10de0007");
1917MODULE_ALIAS("snd-hda-codec-id:10de000a");
1918MODULE_ALIAS("snd-hda-codec-id:10de000b");
1919MODULE_ALIAS("snd-hda-codec-id:10de000c");
1920MODULE_ALIAS("snd-hda-codec-id:10de000d");
1921MODULE_ALIAS("snd-hda-codec-id:10de0010");
1922MODULE_ALIAS("snd-hda-codec-id:10de0011");
1923MODULE_ALIAS("snd-hda-codec-id:10de0012");
1924MODULE_ALIAS("snd-hda-codec-id:10de0013");
1925MODULE_ALIAS("snd-hda-codec-id:10de0014");
c8900a0f
RS		 1926MODULE_ALIAS("snd-hda-codec-id:10de0015");
1927MODULE_ALIAS("snd-hda-codec-id:10de0016");
84eb01be
TI		 1928MODULE_ALIAS("snd-hda-codec-id:10de0018");
1929MODULE_ALIAS("snd-hda-codec-id:10de0019");
1930MODULE_ALIAS("snd-hda-codec-id:10de001a");
1931MODULE_ALIAS("snd-hda-codec-id:10de001b");
1932MODULE_ALIAS("snd-hda-codec-id:10de001c");
1933MODULE_ALIAS("snd-hda-codec-id:10de0040");
1934MODULE_ALIAS("snd-hda-codec-id:10de0041");
1935MODULE_ALIAS("snd-hda-codec-id:10de0042");
1936MODULE_ALIAS("snd-hda-codec-id:10de0043");
1937MODULE_ALIAS("snd-hda-codec-id:10de0044");
1938MODULE_ALIAS("snd-hda-codec-id:10de0067");
1939MODULE_ALIAS("snd-hda-codec-id:10de8001");
1940MODULE_ALIAS("snd-hda-codec-id:17e80047");
1941MODULE_ALIAS("snd-hda-codec-id:80860054");
1942MODULE_ALIAS("snd-hda-codec-id:80862801");
1943MODULE_ALIAS("snd-hda-codec-id:80862802");
1944MODULE_ALIAS("snd-hda-codec-id:80862803");
1945MODULE_ALIAS("snd-hda-codec-id:80862804");
1946MODULE_ALIAS("snd-hda-codec-id:80862805");
591e610d 1947MODULE_ALIAS("snd-hda-codec-id:80862806");
84eb01be
TI		 1948MODULE_ALIAS("snd-hda-codec-id:808629fb");
1949
1950MODULE_LICENSE("GPL");
1951MODULE_DESCRIPTION("HDMI HD-audio codec");
1952MODULE_ALIAS("snd-hda-codec-intelhdmi");
1953MODULE_ALIAS("snd-hda-codec-nvhdmi");
1954MODULE_ALIAS("snd-hda-codec-atihdmi");
1955
1956static struct hda_codec_preset_list intel_list = {
1957 .preset = snd_hda_preset_hdmi,
1958 .owner = THIS_MODULE,
1959};
1960
1961static int __init patch_hdmi_init(void)
1962{
1963 return snd_hda_add_codec_preset(&intel_list);
1964}
1965
1966static void __exit patch_hdmi_exit(void)
1967{
1968 snd_hda_delete_codec_preset(&intel_list);
1969}
1970
1971module_init(patch_hdmi_init)
1972module_exit(patch_hdmi_exit)
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