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4101866c LPC |
1 | /* |
2 | * Common code for ADAU1X61 and ADAU1X81 codecs | |
3 | * | |
4 | * Copyright 2011-2014 Analog Devices Inc. | |
5 | * Author: Lars-Peter Clausen <lars@metafoo.de> | |
6 | * | |
7 | * Licensed under the GPL-2 or later. | |
8 | */ | |
9 | ||
10 | #include <linux/module.h> | |
11 | #include <linux/init.h> | |
5d76de61 | 12 | #include <linux/clk.h> |
4101866c LPC |
13 | #include <linux/delay.h> |
14 | #include <linux/slab.h> | |
15 | #include <sound/core.h> | |
16 | #include <sound/pcm.h> | |
17 | #include <sound/pcm_params.h> | |
18 | #include <sound/soc.h> | |
19 | #include <sound/tlv.h> | |
20 | #include <linux/gcd.h> | |
21 | #include <linux/i2c.h> | |
22 | #include <linux/spi/spi.h> | |
23 | #include <linux/regmap.h> | |
24 | ||
25 | #include "sigmadsp.h" | |
26 | #include "adau17x1.h" | |
0eadaa9c | 27 | #include "adau-utils.h" |
4101866c LPC |
28 | |
29 | static const char * const adau17x1_capture_mixer_boost_text[] = { | |
30 | "Normal operation", "Boost Level 1", "Boost Level 2", "Boost Level 3", | |
31 | }; | |
32 | ||
33 | static SOC_ENUM_SINGLE_DECL(adau17x1_capture_boost_enum, | |
34 | ADAU17X1_REC_POWER_MGMT, 5, adau17x1_capture_mixer_boost_text); | |
35 | ||
36 | static const char * const adau17x1_mic_bias_mode_text[] = { | |
37 | "Normal operation", "High performance", | |
38 | }; | |
39 | ||
40 | static SOC_ENUM_SINGLE_DECL(adau17x1_mic_bias_mode_enum, | |
41 | ADAU17X1_MICBIAS, 3, adau17x1_mic_bias_mode_text); | |
42 | ||
43 | static const DECLARE_TLV_DB_MINMAX(adau17x1_digital_tlv, -9563, 0); | |
44 | ||
45 | static const struct snd_kcontrol_new adau17x1_controls[] = { | |
46 | SOC_DOUBLE_R_TLV("Digital Capture Volume", | |
47 | ADAU17X1_LEFT_INPUT_DIGITAL_VOL, | |
48 | ADAU17X1_RIGHT_INPUT_DIGITAL_VOL, | |
49 | 0, 0xff, 1, adau17x1_digital_tlv), | |
50 | SOC_DOUBLE_R_TLV("Digital Playback Volume", ADAU17X1_DAC_CONTROL1, | |
51 | ADAU17X1_DAC_CONTROL2, 0, 0xff, 1, adau17x1_digital_tlv), | |
52 | ||
53 | SOC_SINGLE("ADC High Pass Filter Switch", ADAU17X1_ADC_CONTROL, | |
54 | 5, 1, 0), | |
55 | SOC_SINGLE("Playback De-emphasis Switch", ADAU17X1_DAC_CONTROL0, | |
56 | 2, 1, 0), | |
57 | ||
58 | SOC_ENUM("Capture Boost", adau17x1_capture_boost_enum), | |
59 | ||
60 | SOC_ENUM("Mic Bias Mode", adau17x1_mic_bias_mode_enum), | |
61 | }; | |
62 | ||
63 | static int adau17x1_pll_event(struct snd_soc_dapm_widget *w, | |
64 | struct snd_kcontrol *kcontrol, int event) | |
65 | { | |
d69db7f7 LPC |
66 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
67 | struct adau *adau = snd_soc_codec_get_drvdata(codec); | |
4101866c LPC |
68 | |
69 | if (SND_SOC_DAPM_EVENT_ON(event)) { | |
70 | adau->pll_regs[5] = 1; | |
71 | } else { | |
72 | adau->pll_regs[5] = 0; | |
73 | /* Bypass the PLL when disabled, otherwise registers will become | |
74 | * inaccessible. */ | |
75 | regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL, | |
76 | ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL, 0); | |
77 | } | |
78 | ||
79 | /* The PLL register is 6 bytes long and can only be written at once. */ | |
1d007348 | 80 | regmap_raw_write(adau->regmap, ADAU17X1_PLL_CONTROL, |
4101866c LPC |
81 | adau->pll_regs, ARRAY_SIZE(adau->pll_regs)); |
82 | ||
83 | if (SND_SOC_DAPM_EVENT_ON(event)) { | |
84 | mdelay(5); | |
85 | regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL, | |
86 | ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL, | |
87 | ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL); | |
88 | } | |
89 | ||
90 | return 0; | |
91 | } | |
92 | ||
1e6f4fc0 RW |
93 | static int adau17x1_adc_fixup(struct snd_soc_dapm_widget *w, |
94 | struct snd_kcontrol *kcontrol, int event) | |
95 | { | |
96 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); | |
97 | struct adau *adau = snd_soc_codec_get_drvdata(codec); | |
98 | ||
99 | /* | |
100 | * If we are capturing, toggle the ADOSR bit in Converter Control 0 to | |
101 | * avoid losing SNR (workaround from ADI). This must be done after | |
102 | * the ADC(s) have been enabled. According to the data sheet, it is | |
103 | * normally illegal to set this bit when the sampling rate is 96 kHz, | |
104 | * but according to ADI it is acceptable for this workaround. | |
105 | */ | |
106 | regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0, | |
107 | ADAU17X1_CONVERTER0_ADOSR, ADAU17X1_CONVERTER0_ADOSR); | |
108 | regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0, | |
109 | ADAU17X1_CONVERTER0_ADOSR, 0); | |
110 | ||
111 | return 0; | |
112 | } | |
113 | ||
4101866c LPC |
114 | static const char * const adau17x1_mono_stereo_text[] = { |
115 | "Stereo", | |
116 | "Mono Left Channel (L+R)", | |
117 | "Mono Right Channel (L+R)", | |
118 | "Mono (L+R)", | |
119 | }; | |
120 | ||
121 | static SOC_ENUM_SINGLE_DECL(adau17x1_dac_mode_enum, | |
122 | ADAU17X1_DAC_CONTROL0, 6, adau17x1_mono_stereo_text); | |
123 | ||
124 | static const struct snd_kcontrol_new adau17x1_dac_mode_mux = | |
125 | SOC_DAPM_ENUM("DAC Mono-Stereo-Mode", adau17x1_dac_mode_enum); | |
126 | ||
127 | static const struct snd_soc_dapm_widget adau17x1_dapm_widgets[] = { | |
128 | SND_SOC_DAPM_SUPPLY_S("PLL", 3, SND_SOC_NOPM, 0, 0, adau17x1_pll_event, | |
129 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), | |
130 | ||
131 | SND_SOC_DAPM_SUPPLY("AIFCLK", SND_SOC_NOPM, 0, 0, NULL, 0), | |
132 | ||
133 | SND_SOC_DAPM_SUPPLY("MICBIAS", ADAU17X1_MICBIAS, 0, 0, NULL, 0), | |
134 | ||
135 | SND_SOC_DAPM_SUPPLY("Left Playback Enable", ADAU17X1_PLAY_POWER_MGMT, | |
136 | 0, 0, NULL, 0), | |
137 | SND_SOC_DAPM_SUPPLY("Right Playback Enable", ADAU17X1_PLAY_POWER_MGMT, | |
138 | 1, 0, NULL, 0), | |
139 | ||
140 | SND_SOC_DAPM_MUX("Left DAC Mode Mux", SND_SOC_NOPM, 0, 0, | |
141 | &adau17x1_dac_mode_mux), | |
142 | SND_SOC_DAPM_MUX("Right DAC Mode Mux", SND_SOC_NOPM, 0, 0, | |
143 | &adau17x1_dac_mode_mux), | |
144 | ||
1e6f4fc0 RW |
145 | SND_SOC_DAPM_ADC_E("Left Decimator", NULL, ADAU17X1_ADC_CONTROL, 0, 0, |
146 | adau17x1_adc_fixup, SND_SOC_DAPM_POST_PMU), | |
4101866c LPC |
147 | SND_SOC_DAPM_ADC("Right Decimator", NULL, ADAU17X1_ADC_CONTROL, 1, 0), |
148 | SND_SOC_DAPM_DAC("Left DAC", NULL, ADAU17X1_DAC_CONTROL0, 0, 0), | |
149 | SND_SOC_DAPM_DAC("Right DAC", NULL, ADAU17X1_DAC_CONTROL0, 1, 0), | |
150 | }; | |
151 | ||
152 | static const struct snd_soc_dapm_route adau17x1_dapm_routes[] = { | |
153 | { "Left Decimator", NULL, "SYSCLK" }, | |
154 | { "Right Decimator", NULL, "SYSCLK" }, | |
155 | { "Left DAC", NULL, "SYSCLK" }, | |
156 | { "Right DAC", NULL, "SYSCLK" }, | |
157 | { "Capture", NULL, "SYSCLK" }, | |
158 | { "Playback", NULL, "SYSCLK" }, | |
159 | ||
160 | { "Left DAC", NULL, "Left DAC Mode Mux" }, | |
161 | { "Right DAC", NULL, "Right DAC Mode Mux" }, | |
162 | ||
163 | { "Capture", NULL, "AIFCLK" }, | |
164 | { "Playback", NULL, "AIFCLK" }, | |
165 | }; | |
166 | ||
167 | static const struct snd_soc_dapm_route adau17x1_dapm_pll_route = { | |
168 | "SYSCLK", NULL, "PLL", | |
169 | }; | |
170 | ||
171 | /* | |
172 | * The MUX register for the Capture and Playback MUXs selects either DSP as | |
173 | * source/destination or one of the TDM slots. The TDM slot is selected via | |
174 | * snd_soc_dai_set_tdm_slot(), so we only expose whether to go to the DSP or | |
175 | * directly to the DAI interface with this control. | |
176 | */ | |
177 | static int adau17x1_dsp_mux_enum_put(struct snd_kcontrol *kcontrol, | |
178 | struct snd_ctl_elem_value *ucontrol) | |
179 | { | |
180 | struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol); | |
33c7b140 | 181 | struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); |
4101866c LPC |
182 | struct adau *adau = snd_soc_codec_get_drvdata(codec); |
183 | struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; | |
e411b0b5 | 184 | struct snd_soc_dapm_update update = { 0 }; |
4101866c LPC |
185 | unsigned int stream = e->shift_l; |
186 | unsigned int val, change; | |
187 | int reg; | |
188 | ||
189 | if (ucontrol->value.enumerated.item[0] >= e->items) | |
190 | return -EINVAL; | |
191 | ||
192 | switch (ucontrol->value.enumerated.item[0]) { | |
193 | case 0: | |
194 | val = 0; | |
195 | adau->dsp_bypass[stream] = false; | |
196 | break; | |
197 | default: | |
198 | val = (adau->tdm_slot[stream] * 2) + 1; | |
199 | adau->dsp_bypass[stream] = true; | |
200 | break; | |
201 | } | |
202 | ||
203 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) | |
204 | reg = ADAU17X1_SERIAL_INPUT_ROUTE; | |
205 | else | |
206 | reg = ADAU17X1_SERIAL_OUTPUT_ROUTE; | |
207 | ||
208 | change = snd_soc_test_bits(codec, reg, 0xff, val); | |
209 | if (change) { | |
210 | update.kcontrol = kcontrol; | |
211 | update.mask = 0xff; | |
212 | update.reg = reg; | |
213 | update.val = val; | |
214 | ||
33c7b140 | 215 | snd_soc_dapm_mux_update_power(dapm, kcontrol, |
4101866c LPC |
216 | ucontrol->value.enumerated.item[0], e, &update); |
217 | } | |
218 | ||
219 | return change; | |
220 | } | |
221 | ||
222 | static int adau17x1_dsp_mux_enum_get(struct snd_kcontrol *kcontrol, | |
223 | struct snd_ctl_elem_value *ucontrol) | |
224 | { | |
225 | struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol); | |
226 | struct adau *adau = snd_soc_codec_get_drvdata(codec); | |
227 | struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; | |
228 | unsigned int stream = e->shift_l; | |
229 | unsigned int reg, val; | |
230 | int ret; | |
231 | ||
232 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) | |
233 | reg = ADAU17X1_SERIAL_INPUT_ROUTE; | |
234 | else | |
235 | reg = ADAU17X1_SERIAL_OUTPUT_ROUTE; | |
236 | ||
237 | ret = regmap_read(adau->regmap, reg, &val); | |
238 | if (ret) | |
239 | return ret; | |
240 | ||
241 | if (val != 0) | |
242 | val = 1; | |
243 | ucontrol->value.enumerated.item[0] = val; | |
244 | ||
245 | return 0; | |
246 | } | |
247 | ||
248 | #define DECLARE_ADAU17X1_DSP_MUX_CTRL(_name, _label, _stream, _text) \ | |
249 | const struct snd_kcontrol_new _name = \ | |
250 | SOC_DAPM_ENUM_EXT(_label, (const struct soc_enum)\ | |
251 | SOC_ENUM_SINGLE(SND_SOC_NOPM, _stream, \ | |
252 | ARRAY_SIZE(_text), _text), \ | |
253 | adau17x1_dsp_mux_enum_get, adau17x1_dsp_mux_enum_put) | |
254 | ||
255 | static const char * const adau17x1_dac_mux_text[] = { | |
256 | "DSP", | |
257 | "AIFIN", | |
258 | }; | |
259 | ||
260 | static const char * const adau17x1_capture_mux_text[] = { | |
261 | "DSP", | |
262 | "Decimator", | |
263 | }; | |
264 | ||
265 | static DECLARE_ADAU17X1_DSP_MUX_CTRL(adau17x1_dac_mux, "DAC Playback Mux", | |
266 | SNDRV_PCM_STREAM_PLAYBACK, adau17x1_dac_mux_text); | |
267 | ||
268 | static DECLARE_ADAU17X1_DSP_MUX_CTRL(adau17x1_capture_mux, "Capture Mux", | |
269 | SNDRV_PCM_STREAM_CAPTURE, adau17x1_capture_mux_text); | |
270 | ||
271 | static const struct snd_soc_dapm_widget adau17x1_dsp_dapm_widgets[] = { | |
272 | SND_SOC_DAPM_PGA("DSP", ADAU17X1_DSP_RUN, 0, 0, NULL, 0), | |
273 | SND_SOC_DAPM_SIGGEN("DSP Siggen"), | |
274 | ||
275 | SND_SOC_DAPM_MUX("DAC Playback Mux", SND_SOC_NOPM, 0, 0, | |
276 | &adau17x1_dac_mux), | |
277 | SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, | |
278 | &adau17x1_capture_mux), | |
279 | }; | |
280 | ||
281 | static const struct snd_soc_dapm_route adau17x1_dsp_dapm_routes[] = { | |
282 | { "DAC Playback Mux", "DSP", "DSP" }, | |
283 | { "DAC Playback Mux", "AIFIN", "Playback" }, | |
284 | ||
285 | { "Left DAC Mode Mux", "Stereo", "DAC Playback Mux" }, | |
286 | { "Left DAC Mode Mux", "Mono (L+R)", "DAC Playback Mux" }, | |
287 | { "Left DAC Mode Mux", "Mono Left Channel (L+R)", "DAC Playback Mux" }, | |
288 | { "Right DAC Mode Mux", "Stereo", "DAC Playback Mux" }, | |
289 | { "Right DAC Mode Mux", "Mono (L+R)", "DAC Playback Mux" }, | |
290 | { "Right DAC Mode Mux", "Mono Right Channel (L+R)", "DAC Playback Mux" }, | |
291 | ||
292 | { "Capture Mux", "DSP", "DSP" }, | |
293 | { "Capture Mux", "Decimator", "Left Decimator" }, | |
294 | { "Capture Mux", "Decimator", "Right Decimator" }, | |
295 | ||
296 | { "Capture", NULL, "Capture Mux" }, | |
297 | ||
298 | { "DSP", NULL, "DSP Siggen" }, | |
299 | ||
300 | { "DSP", NULL, "Left Decimator" }, | |
301 | { "DSP", NULL, "Right Decimator" }, | |
302 | }; | |
303 | ||
304 | static const struct snd_soc_dapm_route adau17x1_no_dsp_dapm_routes[] = { | |
305 | { "Left DAC Mode Mux", "Stereo", "Playback" }, | |
306 | { "Left DAC Mode Mux", "Mono (L+R)", "Playback" }, | |
307 | { "Left DAC Mode Mux", "Mono Left Channel (L+R)", "Playback" }, | |
308 | { "Right DAC Mode Mux", "Stereo", "Playback" }, | |
309 | { "Right DAC Mode Mux", "Mono (L+R)", "Playback" }, | |
310 | { "Right DAC Mode Mux", "Mono Right Channel (L+R)", "Playback" }, | |
311 | { "Capture", NULL, "Left Decimator" }, | |
312 | { "Capture", NULL, "Right Decimator" }, | |
313 | }; | |
314 | ||
315 | bool adau17x1_has_dsp(struct adau *adau) | |
316 | { | |
317 | switch (adau->type) { | |
318 | case ADAU1761: | |
319 | case ADAU1381: | |
320 | case ADAU1781: | |
321 | return true; | |
322 | default: | |
323 | return false; | |
324 | } | |
325 | } | |
326 | EXPORT_SYMBOL_GPL(adau17x1_has_dsp); | |
327 | ||
5d76de61 LPC |
328 | static int adau17x1_set_dai_pll(struct snd_soc_dai *dai, int pll_id, |
329 | int source, unsigned int freq_in, unsigned int freq_out) | |
330 | { | |
331 | struct snd_soc_codec *codec = dai->codec; | |
332 | struct adau *adau = snd_soc_codec_get_drvdata(codec); | |
333 | int ret; | |
334 | ||
335 | if (freq_in < 8000000 || freq_in > 27000000) | |
336 | return -EINVAL; | |
337 | ||
338 | ret = adau_calc_pll_cfg(freq_in, freq_out, adau->pll_regs); | |
339 | if (ret < 0) | |
340 | return ret; | |
341 | ||
342 | /* The PLL register is 6 bytes long and can only be written at once. */ | |
343 | ret = regmap_raw_write(adau->regmap, ADAU17X1_PLL_CONTROL, | |
344 | adau->pll_regs, ARRAY_SIZE(adau->pll_regs)); | |
345 | if (ret) | |
346 | return ret; | |
347 | ||
348 | adau->pll_freq = freq_out; | |
349 | ||
350 | return 0; | |
351 | } | |
352 | ||
353 | static int adau17x1_set_dai_sysclk(struct snd_soc_dai *dai, | |
354 | int clk_id, unsigned int freq, int dir) | |
355 | { | |
356 | struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(dai->codec); | |
357 | struct adau *adau = snd_soc_codec_get_drvdata(dai->codec); | |
358 | bool is_pll; | |
359 | bool was_pll; | |
360 | ||
361 | switch (clk_id) { | |
362 | case ADAU17X1_CLK_SRC_MCLK: | |
363 | is_pll = false; | |
364 | break; | |
365 | case ADAU17X1_CLK_SRC_PLL_AUTO: | |
366 | if (!adau->mclk) | |
367 | return -EINVAL; | |
368 | /* Fall-through */ | |
369 | case ADAU17X1_CLK_SRC_PLL: | |
370 | is_pll = true; | |
371 | break; | |
372 | default: | |
373 | return -EINVAL; | |
374 | } | |
375 | ||
376 | switch (adau->clk_src) { | |
377 | case ADAU17X1_CLK_SRC_MCLK: | |
378 | was_pll = false; | |
379 | break; | |
380 | case ADAU17X1_CLK_SRC_PLL: | |
381 | case ADAU17X1_CLK_SRC_PLL_AUTO: | |
382 | was_pll = true; | |
383 | break; | |
384 | default: | |
385 | return -EINVAL; | |
386 | } | |
387 | ||
388 | adau->sysclk = freq; | |
389 | ||
390 | if (is_pll != was_pll) { | |
391 | if (is_pll) { | |
392 | snd_soc_dapm_add_routes(dapm, | |
393 | &adau17x1_dapm_pll_route, 1); | |
394 | } else { | |
395 | snd_soc_dapm_del_routes(dapm, | |
396 | &adau17x1_dapm_pll_route, 1); | |
397 | } | |
398 | } | |
399 | ||
400 | adau->clk_src = clk_id; | |
401 | ||
402 | return 0; | |
403 | } | |
404 | ||
405 | static int adau17x1_auto_pll(struct snd_soc_dai *dai, | |
406 | struct snd_pcm_hw_params *params) | |
407 | { | |
408 | struct adau *adau = snd_soc_dai_get_drvdata(dai); | |
409 | unsigned int pll_rate; | |
410 | ||
411 | switch (params_rate(params)) { | |
412 | case 48000: | |
413 | case 8000: | |
414 | case 12000: | |
415 | case 16000: | |
416 | case 24000: | |
417 | case 32000: | |
418 | case 96000: | |
419 | pll_rate = 48000 * 1024; | |
420 | break; | |
421 | case 44100: | |
422 | case 7350: | |
423 | case 11025: | |
424 | case 14700: | |
425 | case 22050: | |
426 | case 29400: | |
427 | case 88200: | |
428 | pll_rate = 44100 * 1024; | |
429 | break; | |
430 | default: | |
431 | return -EINVAL; | |
432 | } | |
433 | ||
434 | return adau17x1_set_dai_pll(dai, ADAU17X1_PLL, ADAU17X1_PLL_SRC_MCLK, | |
435 | clk_get_rate(adau->mclk), pll_rate); | |
436 | } | |
437 | ||
4101866c LPC |
438 | static int adau17x1_hw_params(struct snd_pcm_substream *substream, |
439 | struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) | |
440 | { | |
441 | struct snd_soc_codec *codec = dai->codec; | |
442 | struct adau *adau = snd_soc_codec_get_drvdata(codec); | |
443 | unsigned int val, div, dsp_div; | |
444 | unsigned int freq; | |
d48b088e | 445 | int ret; |
4101866c | 446 | |
5d76de61 LPC |
447 | switch (adau->clk_src) { |
448 | case ADAU17X1_CLK_SRC_PLL_AUTO: | |
449 | ret = adau17x1_auto_pll(dai, params); | |
450 | if (ret) | |
451 | return ret; | |
452 | /* Fall-through */ | |
453 | case ADAU17X1_CLK_SRC_PLL: | |
4101866c | 454 | freq = adau->pll_freq; |
5d76de61 LPC |
455 | break; |
456 | default: | |
4101866c | 457 | freq = adau->sysclk; |
5d76de61 LPC |
458 | break; |
459 | } | |
4101866c LPC |
460 | |
461 | if (freq % params_rate(params) != 0) | |
462 | return -EINVAL; | |
463 | ||
464 | switch (freq / params_rate(params)) { | |
465 | case 1024: /* fs */ | |
466 | div = 0; | |
467 | dsp_div = 1; | |
468 | break; | |
469 | case 6144: /* fs / 6 */ | |
470 | div = 1; | |
471 | dsp_div = 6; | |
472 | break; | |
473 | case 4096: /* fs / 4 */ | |
474 | div = 2; | |
475 | dsp_div = 5; | |
476 | break; | |
477 | case 3072: /* fs / 3 */ | |
478 | div = 3; | |
479 | dsp_div = 4; | |
480 | break; | |
481 | case 2048: /* fs / 2 */ | |
482 | div = 4; | |
483 | dsp_div = 3; | |
484 | break; | |
485 | case 1536: /* fs / 1.5 */ | |
486 | div = 5; | |
487 | dsp_div = 2; | |
488 | break; | |
489 | case 512: /* fs / 0.5 */ | |
490 | div = 6; | |
491 | dsp_div = 0; | |
492 | break; | |
493 | default: | |
494 | return -EINVAL; | |
495 | } | |
496 | ||
497 | regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0, | |
498 | ADAU17X1_CONVERTER0_CONVSR_MASK, div); | |
499 | if (adau17x1_has_dsp(adau)) { | |
500 | regmap_write(adau->regmap, ADAU17X1_SERIAL_SAMPLING_RATE, div); | |
501 | regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, dsp_div); | |
502 | } | |
503 | ||
d48b088e LPC |
504 | if (adau->sigmadsp) { |
505 | ret = adau17x1_setup_firmware(adau, params_rate(params)); | |
506 | if (ret < 0) | |
507 | return ret; | |
508 | } | |
509 | ||
4101866c LPC |
510 | if (adau->dai_fmt != SND_SOC_DAIFMT_RIGHT_J) |
511 | return 0; | |
512 | ||
d2a9b1c1 MB |
513 | switch (params_width(params)) { |
514 | case 16: | |
4101866c LPC |
515 | val = ADAU17X1_SERIAL_PORT1_DELAY16; |
516 | break; | |
d2a9b1c1 | 517 | case 24: |
4101866c LPC |
518 | val = ADAU17X1_SERIAL_PORT1_DELAY8; |
519 | break; | |
d2a9b1c1 | 520 | case 32: |
4101866c LPC |
521 | val = ADAU17X1_SERIAL_PORT1_DELAY0; |
522 | break; | |
523 | default: | |
524 | return -EINVAL; | |
525 | } | |
526 | ||
527 | return regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT1, | |
528 | ADAU17X1_SERIAL_PORT1_DELAY_MASK, val); | |
529 | } | |
530 | ||
4101866c LPC |
531 | static int adau17x1_set_dai_fmt(struct snd_soc_dai *dai, |
532 | unsigned int fmt) | |
533 | { | |
534 | struct adau *adau = snd_soc_codec_get_drvdata(dai->codec); | |
535 | unsigned int ctrl0, ctrl1; | |
536 | int lrclk_pol; | |
537 | ||
538 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
539 | case SND_SOC_DAIFMT_CBM_CFM: | |
540 | ctrl0 = ADAU17X1_SERIAL_PORT0_MASTER; | |
541 | adau->master = true; | |
542 | break; | |
543 | case SND_SOC_DAIFMT_CBS_CFS: | |
544 | ctrl0 = 0; | |
545 | adau->master = false; | |
546 | break; | |
547 | default: | |
548 | return -EINVAL; | |
549 | } | |
550 | ||
551 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
552 | case SND_SOC_DAIFMT_I2S: | |
553 | lrclk_pol = 0; | |
554 | ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY1; | |
555 | break; | |
556 | case SND_SOC_DAIFMT_LEFT_J: | |
557 | case SND_SOC_DAIFMT_RIGHT_J: | |
558 | lrclk_pol = 1; | |
559 | ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY0; | |
560 | break; | |
561 | case SND_SOC_DAIFMT_DSP_A: | |
562 | lrclk_pol = 1; | |
563 | ctrl0 |= ADAU17X1_SERIAL_PORT0_PULSE_MODE; | |
564 | ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY1; | |
565 | break; | |
566 | case SND_SOC_DAIFMT_DSP_B: | |
567 | lrclk_pol = 1; | |
568 | ctrl0 |= ADAU17X1_SERIAL_PORT0_PULSE_MODE; | |
569 | ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY0; | |
570 | break; | |
571 | default: | |
572 | return -EINVAL; | |
573 | } | |
574 | ||
575 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
576 | case SND_SOC_DAIFMT_NB_NF: | |
577 | break; | |
578 | case SND_SOC_DAIFMT_IB_NF: | |
579 | ctrl0 |= ADAU17X1_SERIAL_PORT0_BCLK_POL; | |
580 | break; | |
581 | case SND_SOC_DAIFMT_NB_IF: | |
582 | lrclk_pol = !lrclk_pol; | |
583 | break; | |
584 | case SND_SOC_DAIFMT_IB_IF: | |
585 | ctrl0 |= ADAU17X1_SERIAL_PORT0_BCLK_POL; | |
586 | lrclk_pol = !lrclk_pol; | |
587 | break; | |
588 | default: | |
589 | return -EINVAL; | |
590 | } | |
591 | ||
592 | if (lrclk_pol) | |
593 | ctrl0 |= ADAU17X1_SERIAL_PORT0_LRCLK_POL; | |
594 | ||
595 | regmap_write(adau->regmap, ADAU17X1_SERIAL_PORT0, ctrl0); | |
596 | regmap_write(adau->regmap, ADAU17X1_SERIAL_PORT1, ctrl1); | |
597 | ||
598 | adau->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK; | |
599 | ||
600 | return 0; | |
601 | } | |
602 | ||
603 | static int adau17x1_set_dai_tdm_slot(struct snd_soc_dai *dai, | |
604 | unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) | |
605 | { | |
606 | struct adau *adau = snd_soc_codec_get_drvdata(dai->codec); | |
607 | unsigned int ser_ctrl0, ser_ctrl1; | |
608 | unsigned int conv_ctrl0, conv_ctrl1; | |
609 | ||
610 | /* I2S mode */ | |
611 | if (slots == 0) { | |
612 | slots = 2; | |
613 | rx_mask = 3; | |
614 | tx_mask = 3; | |
615 | slot_width = 32; | |
616 | } | |
617 | ||
618 | switch (slots) { | |
619 | case 2: | |
620 | ser_ctrl0 = ADAU17X1_SERIAL_PORT0_STEREO; | |
621 | break; | |
622 | case 4: | |
623 | ser_ctrl0 = ADAU17X1_SERIAL_PORT0_TDM4; | |
624 | break; | |
625 | case 8: | |
626 | if (adau->type == ADAU1361) | |
627 | return -EINVAL; | |
628 | ||
629 | ser_ctrl0 = ADAU17X1_SERIAL_PORT0_TDM8; | |
630 | break; | |
631 | default: | |
632 | return -EINVAL; | |
633 | } | |
634 | ||
635 | switch (slot_width * slots) { | |
636 | case 32: | |
637 | if (adau->type == ADAU1761) | |
638 | return -EINVAL; | |
639 | ||
640 | ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK32; | |
641 | break; | |
642 | case 64: | |
643 | ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK64; | |
644 | break; | |
645 | case 48: | |
646 | ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK48; | |
647 | break; | |
648 | case 128: | |
649 | ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK128; | |
650 | break; | |
651 | case 256: | |
652 | if (adau->type == ADAU1361) | |
653 | return -EINVAL; | |
654 | ||
655 | ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK256; | |
656 | break; | |
657 | default: | |
658 | return -EINVAL; | |
659 | } | |
660 | ||
661 | switch (rx_mask) { | |
662 | case 0x03: | |
663 | conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(1); | |
664 | adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 0; | |
665 | break; | |
666 | case 0x0c: | |
667 | conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(2); | |
668 | adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 1; | |
669 | break; | |
670 | case 0x30: | |
671 | conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(3); | |
672 | adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 2; | |
673 | break; | |
674 | case 0xc0: | |
675 | conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(4); | |
676 | adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 3; | |
677 | break; | |
678 | default: | |
679 | return -EINVAL; | |
680 | } | |
681 | ||
682 | switch (tx_mask) { | |
683 | case 0x03: | |
684 | conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(1); | |
685 | adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 0; | |
686 | break; | |
687 | case 0x0c: | |
688 | conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(2); | |
689 | adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 1; | |
690 | break; | |
691 | case 0x30: | |
692 | conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(3); | |
693 | adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 2; | |
694 | break; | |
695 | case 0xc0: | |
696 | conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(4); | |
697 | adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 3; | |
698 | break; | |
699 | default: | |
700 | return -EINVAL; | |
701 | } | |
702 | ||
703 | regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0, | |
704 | ADAU17X1_CONVERTER0_DAC_PAIR_MASK, conv_ctrl0); | |
705 | regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER1, | |
706 | ADAU17X1_CONVERTER1_ADC_PAIR_MASK, conv_ctrl1); | |
707 | regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT0, | |
708 | ADAU17X1_SERIAL_PORT0_TDM_MASK, ser_ctrl0); | |
709 | regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT1, | |
710 | ADAU17X1_SERIAL_PORT1_BCLK_MASK, ser_ctrl1); | |
711 | ||
712 | if (!adau17x1_has_dsp(adau)) | |
713 | return 0; | |
714 | ||
715 | if (adau->dsp_bypass[SNDRV_PCM_STREAM_PLAYBACK]) { | |
716 | regmap_write(adau->regmap, ADAU17X1_SERIAL_INPUT_ROUTE, | |
717 | (adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] * 2) + 1); | |
718 | } | |
719 | ||
720 | if (adau->dsp_bypass[SNDRV_PCM_STREAM_CAPTURE]) { | |
721 | regmap_write(adau->regmap, ADAU17X1_SERIAL_OUTPUT_ROUTE, | |
722 | (adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] * 2) + 1); | |
723 | } | |
724 | ||
725 | return 0; | |
726 | } | |
727 | ||
d48b088e LPC |
728 | static int adau17x1_startup(struct snd_pcm_substream *substream, |
729 | struct snd_soc_dai *dai) | |
730 | { | |
731 | struct adau *adau = snd_soc_codec_get_drvdata(dai->codec); | |
732 | ||
733 | if (adau->sigmadsp) | |
734 | return sigmadsp_restrict_params(adau->sigmadsp, substream); | |
735 | ||
736 | return 0; | |
737 | } | |
738 | ||
4101866c LPC |
739 | const struct snd_soc_dai_ops adau17x1_dai_ops = { |
740 | .hw_params = adau17x1_hw_params, | |
741 | .set_sysclk = adau17x1_set_dai_sysclk, | |
742 | .set_fmt = adau17x1_set_dai_fmt, | |
743 | .set_pll = adau17x1_set_dai_pll, | |
744 | .set_tdm_slot = adau17x1_set_dai_tdm_slot, | |
d48b088e | 745 | .startup = adau17x1_startup, |
4101866c LPC |
746 | }; |
747 | EXPORT_SYMBOL_GPL(adau17x1_dai_ops); | |
748 | ||
749 | int adau17x1_set_micbias_voltage(struct snd_soc_codec *codec, | |
750 | enum adau17x1_micbias_voltage micbias) | |
751 | { | |
752 | struct adau *adau = snd_soc_codec_get_drvdata(codec); | |
753 | ||
754 | switch (micbias) { | |
755 | case ADAU17X1_MICBIAS_0_90_AVDD: | |
756 | case ADAU17X1_MICBIAS_0_65_AVDD: | |
757 | break; | |
758 | default: | |
759 | return -EINVAL; | |
760 | } | |
761 | ||
762 | return regmap_write(adau->regmap, ADAU17X1_MICBIAS, micbias << 2); | |
763 | } | |
764 | EXPORT_SYMBOL_GPL(adau17x1_set_micbias_voltage); | |
765 | ||
dee9cec4 LPC |
766 | bool adau17x1_precious_register(struct device *dev, unsigned int reg) |
767 | { | |
768 | /* SigmaDSP parameter memory */ | |
769 | if (reg < 0x400) | |
770 | return true; | |
771 | ||
772 | return false; | |
773 | } | |
774 | EXPORT_SYMBOL_GPL(adau17x1_precious_register); | |
775 | ||
4101866c LPC |
776 | bool adau17x1_readable_register(struct device *dev, unsigned int reg) |
777 | { | |
dee9cec4 LPC |
778 | /* SigmaDSP parameter memory */ |
779 | if (reg < 0x400) | |
780 | return true; | |
781 | ||
4101866c LPC |
782 | switch (reg) { |
783 | case ADAU17X1_CLOCK_CONTROL: | |
784 | case ADAU17X1_PLL_CONTROL: | |
785 | case ADAU17X1_REC_POWER_MGMT: | |
786 | case ADAU17X1_MICBIAS: | |
787 | case ADAU17X1_SERIAL_PORT0: | |
788 | case ADAU17X1_SERIAL_PORT1: | |
789 | case ADAU17X1_CONVERTER0: | |
790 | case ADAU17X1_CONVERTER1: | |
791 | case ADAU17X1_LEFT_INPUT_DIGITAL_VOL: | |
792 | case ADAU17X1_RIGHT_INPUT_DIGITAL_VOL: | |
793 | case ADAU17X1_ADC_CONTROL: | |
794 | case ADAU17X1_PLAY_POWER_MGMT: | |
795 | case ADAU17X1_DAC_CONTROL0: | |
796 | case ADAU17X1_DAC_CONTROL1: | |
797 | case ADAU17X1_DAC_CONTROL2: | |
798 | case ADAU17X1_SERIAL_PORT_PAD: | |
799 | case ADAU17X1_CONTROL_PORT_PAD0: | |
800 | case ADAU17X1_CONTROL_PORT_PAD1: | |
801 | case ADAU17X1_DSP_SAMPLING_RATE: | |
802 | case ADAU17X1_SERIAL_INPUT_ROUTE: | |
803 | case ADAU17X1_SERIAL_OUTPUT_ROUTE: | |
804 | case ADAU17X1_DSP_ENABLE: | |
805 | case ADAU17X1_DSP_RUN: | |
806 | case ADAU17X1_SERIAL_SAMPLING_RATE: | |
807 | return true; | |
808 | default: | |
809 | break; | |
810 | } | |
811 | return false; | |
812 | } | |
813 | EXPORT_SYMBOL_GPL(adau17x1_readable_register); | |
814 | ||
815 | bool adau17x1_volatile_register(struct device *dev, unsigned int reg) | |
816 | { | |
817 | /* SigmaDSP parameter and program memory */ | |
818 | if (reg < 0x4000) | |
819 | return true; | |
820 | ||
821 | switch (reg) { | |
822 | /* The PLL register is 6 bytes long */ | |
823 | case ADAU17X1_PLL_CONTROL: | |
824 | case ADAU17X1_PLL_CONTROL + 1: | |
825 | case ADAU17X1_PLL_CONTROL + 2: | |
826 | case ADAU17X1_PLL_CONTROL + 3: | |
827 | case ADAU17X1_PLL_CONTROL + 4: | |
828 | case ADAU17X1_PLL_CONTROL + 5: | |
829 | return true; | |
830 | default: | |
831 | break; | |
832 | } | |
833 | ||
834 | return false; | |
835 | } | |
836 | EXPORT_SYMBOL_GPL(adau17x1_volatile_register); | |
837 | ||
d48b088e | 838 | int adau17x1_setup_firmware(struct adau *adau, unsigned int rate) |
4101866c LPC |
839 | { |
840 | int ret; | |
841 | int dspsr; | |
842 | ||
843 | ret = regmap_read(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, &dspsr); | |
844 | if (ret) | |
845 | return ret; | |
846 | ||
847 | regmap_write(adau->regmap, ADAU17X1_DSP_ENABLE, 1); | |
848 | regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, 0xf); | |
849 | ||
d48b088e | 850 | ret = sigmadsp_setup(adau->sigmadsp, rate); |
4101866c LPC |
851 | if (ret) { |
852 | regmap_write(adau->regmap, ADAU17X1_DSP_ENABLE, 0); | |
853 | return ret; | |
854 | } | |
855 | regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, dspsr); | |
856 | ||
857 | return 0; | |
858 | } | |
d48b088e | 859 | EXPORT_SYMBOL_GPL(adau17x1_setup_firmware); |
4101866c LPC |
860 | |
861 | int adau17x1_add_widgets(struct snd_soc_codec *codec) | |
862 | { | |
33c7b140 | 863 | struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); |
4101866c LPC |
864 | struct adau *adau = snd_soc_codec_get_drvdata(codec); |
865 | int ret; | |
866 | ||
867 | ret = snd_soc_add_codec_controls(codec, adau17x1_controls, | |
868 | ARRAY_SIZE(adau17x1_controls)); | |
869 | if (ret) | |
870 | return ret; | |
33c7b140 | 871 | ret = snd_soc_dapm_new_controls(dapm, adau17x1_dapm_widgets, |
4101866c LPC |
872 | ARRAY_SIZE(adau17x1_dapm_widgets)); |
873 | if (ret) | |
874 | return ret; | |
875 | ||
876 | if (adau17x1_has_dsp(adau)) { | |
33c7b140 | 877 | ret = snd_soc_dapm_new_controls(dapm, adau17x1_dsp_dapm_widgets, |
4101866c | 878 | ARRAY_SIZE(adau17x1_dsp_dapm_widgets)); |
d48b088e LPC |
879 | if (ret) |
880 | return ret; | |
881 | ||
882 | if (!adau->sigmadsp) | |
883 | return 0; | |
884 | ||
885 | ret = sigmadsp_attach(adau->sigmadsp, &codec->component); | |
886 | if (ret) { | |
887 | dev_err(codec->dev, "Failed to attach firmware: %d\n", | |
888 | ret); | |
889 | return ret; | |
890 | } | |
4101866c | 891 | } |
d48b088e LPC |
892 | |
893 | return 0; | |
4101866c LPC |
894 | } |
895 | EXPORT_SYMBOL_GPL(adau17x1_add_widgets); | |
896 | ||
897 | int adau17x1_add_routes(struct snd_soc_codec *codec) | |
898 | { | |
33c7b140 | 899 | struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); |
4101866c LPC |
900 | struct adau *adau = snd_soc_codec_get_drvdata(codec); |
901 | int ret; | |
902 | ||
33c7b140 | 903 | ret = snd_soc_dapm_add_routes(dapm, adau17x1_dapm_routes, |
4101866c LPC |
904 | ARRAY_SIZE(adau17x1_dapm_routes)); |
905 | if (ret) | |
906 | return ret; | |
907 | ||
908 | if (adau17x1_has_dsp(adau)) { | |
33c7b140 | 909 | ret = snd_soc_dapm_add_routes(dapm, adau17x1_dsp_dapm_routes, |
4101866c LPC |
910 | ARRAY_SIZE(adau17x1_dsp_dapm_routes)); |
911 | } else { | |
33c7b140 | 912 | ret = snd_soc_dapm_add_routes(dapm, adau17x1_no_dsp_dapm_routes, |
4101866c LPC |
913 | ARRAY_SIZE(adau17x1_no_dsp_dapm_routes)); |
914 | } | |
5d76de61 LPC |
915 | |
916 | if (adau->clk_src != ADAU17X1_CLK_SRC_MCLK) | |
917 | snd_soc_dapm_add_routes(dapm, &adau17x1_dapm_pll_route, 1); | |
918 | ||
4101866c LPC |
919 | return ret; |
920 | } | |
921 | EXPORT_SYMBOL_GPL(adau17x1_add_routes); | |
922 | ||
4101866c LPC |
923 | int adau17x1_resume(struct snd_soc_codec *codec) |
924 | { | |
925 | struct adau *adau = snd_soc_codec_get_drvdata(codec); | |
926 | ||
927 | if (adau->switch_mode) | |
928 | adau->switch_mode(codec->dev); | |
929 | ||
4101866c LPC |
930 | regcache_sync(adau->regmap); |
931 | ||
932 | return 0; | |
933 | } | |
934 | EXPORT_SYMBOL_GPL(adau17x1_resume); | |
935 | ||
936 | int adau17x1_probe(struct device *dev, struct regmap *regmap, | |
d48b088e LPC |
937 | enum adau17x1_type type, void (*switch_mode)(struct device *dev), |
938 | const char *firmware_name) | |
4101866c LPC |
939 | { |
940 | struct adau *adau; | |
5d76de61 | 941 | int ret; |
4101866c LPC |
942 | |
943 | if (IS_ERR(regmap)) | |
944 | return PTR_ERR(regmap); | |
945 | ||
946 | adau = devm_kzalloc(dev, sizeof(*adau), GFP_KERNEL); | |
947 | if (!adau) | |
948 | return -ENOMEM; | |
949 | ||
5d76de61 LPC |
950 | adau->mclk = devm_clk_get(dev, "mclk"); |
951 | if (IS_ERR(adau->mclk)) { | |
952 | if (PTR_ERR(adau->mclk) != -ENOENT) | |
953 | return PTR_ERR(adau->mclk); | |
954 | /* Clock is optional (for the driver) */ | |
955 | adau->mclk = NULL; | |
956 | } else if (adau->mclk) { | |
957 | adau->clk_src = ADAU17X1_CLK_SRC_PLL_AUTO; | |
958 | ||
959 | /* | |
960 | * Any valid PLL output rate will work at this point, use one | |
961 | * that is likely to be chosen later as well. The register will | |
962 | * be written when the PLL is powered up for the first time. | |
963 | */ | |
964 | ret = adau_calc_pll_cfg(clk_get_rate(adau->mclk), 48000 * 1024, | |
965 | adau->pll_regs); | |
966 | if (ret < 0) | |
967 | return ret; | |
968 | ||
969 | ret = clk_prepare_enable(adau->mclk); | |
970 | if (ret) | |
971 | return ret; | |
972 | } | |
973 | ||
4101866c LPC |
974 | adau->regmap = regmap; |
975 | adau->switch_mode = switch_mode; | |
976 | adau->type = type; | |
977 | ||
978 | dev_set_drvdata(dev, adau); | |
979 | ||
d48b088e LPC |
980 | if (firmware_name) { |
981 | adau->sigmadsp = devm_sigmadsp_init_regmap(dev, regmap, NULL, | |
982 | firmware_name); | |
983 | if (IS_ERR(adau->sigmadsp)) { | |
984 | dev_warn(dev, "Could not find firmware file: %ld\n", | |
985 | PTR_ERR(adau->sigmadsp)); | |
986 | adau->sigmadsp = NULL; | |
987 | } | |
988 | } | |
989 | ||
4101866c LPC |
990 | if (switch_mode) |
991 | switch_mode(dev); | |
992 | ||
993 | return 0; | |
994 | } | |
995 | EXPORT_SYMBOL_GPL(adau17x1_probe); | |
996 | ||
5d76de61 LPC |
997 | void adau17x1_remove(struct device *dev) |
998 | { | |
999 | struct adau *adau = dev_get_drvdata(dev); | |
1000 | ||
1001 | snd_soc_unregister_codec(dev); | |
1002 | if (adau->mclk) | |
1003 | clk_disable_unprepare(adau->mclk); | |
1004 | } | |
1005 | EXPORT_SYMBOL_GPL(adau17x1_remove); | |
1006 | ||
4101866c LPC |
1007 | MODULE_DESCRIPTION("ASoC ADAU1X61/ADAU1X81 common code"); |
1008 | MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); | |
1009 | MODULE_LICENSE("GPL"); |