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07cf7cba BL |
1 | /* |
2 | * rt286.c -- RT286 ALSA SoC audio codec driver | |
3 | * | |
4 | * Copyright 2013 Realtek Semiconductor Corp. | |
5 | * Author: Bard Liao <bardliao@realtek.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/module.h> | |
13 | #include <linux/moduleparam.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/pm.h> | |
17 | #include <linux/i2c.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/spi/spi.h> | |
20 | #include <linux/acpi.h> | |
21 | #include <sound/core.h> | |
22 | #include <sound/pcm.h> | |
23 | #include <sound/pcm_params.h> | |
24 | #include <sound/soc.h> | |
25 | #include <sound/soc-dapm.h> | |
26 | #include <sound/initval.h> | |
27 | #include <sound/tlv.h> | |
28 | #include <sound/jack.h> | |
29 | #include <linux/workqueue.h> | |
30 | #include <sound/rt286.h> | |
31 | #include <sound/hda_verbs.h> | |
32 | ||
33 | #include "rt286.h" | |
34 | ||
35 | #define RT286_VENDOR_ID 0x10ec0286 | |
36 | ||
37 | struct rt286_priv { | |
38 | struct regmap *regmap; | |
39 | struct snd_soc_codec *codec; | |
40 | struct rt286_platform_data pdata; | |
41 | struct i2c_client *i2c; | |
42 | struct snd_soc_jack *jack; | |
43 | struct delayed_work jack_detect_work; | |
44 | int sys_clk; | |
45 | struct reg_default *index_cache; | |
46 | }; | |
47 | ||
48 | static struct reg_default rt286_index_def[] = { | |
49 | { 0x01, 0xaaaa }, | |
50 | { 0x02, 0x8aaa }, | |
51 | { 0x03, 0x0002 }, | |
52 | { 0x04, 0xaf01 }, | |
53 | { 0x08, 0x000d }, | |
54 | { 0x09, 0xd810 }, | |
55 | { 0x0a, 0x0060 }, | |
56 | { 0x0b, 0x0000 }, | |
bc6c4e45 | 57 | { 0x0d, 0x2800 }, |
07cf7cba BL |
58 | { 0x0f, 0x0000 }, |
59 | { 0x19, 0x0a17 }, | |
60 | { 0x20, 0x0020 }, | |
61 | { 0x33, 0x0208 }, | |
62 | { 0x49, 0x0004 }, | |
63 | { 0x4f, 0x50e9 }, | |
64 | { 0x50, 0x2c00 }, | |
65 | { 0x63, 0x2902 }, | |
bc6c4e45 BL |
66 | { 0x67, 0x1111 }, |
67 | { 0x68, 0x1016 }, | |
68 | { 0x69, 0x273f }, | |
07cf7cba BL |
69 | }; |
70 | #define INDEX_CACHE_SIZE ARRAY_SIZE(rt286_index_def) | |
71 | ||
72 | static const struct reg_default rt286_reg[] = { | |
73 | { 0x00170500, 0x00000400 }, | |
74 | { 0x00220000, 0x00000031 }, | |
75 | { 0x00239000, 0x0000007f }, | |
76 | { 0x0023a000, 0x0000007f }, | |
77 | { 0x00270500, 0x00000400 }, | |
78 | { 0x00370500, 0x00000400 }, | |
79 | { 0x00870500, 0x00000400 }, | |
80 | { 0x00920000, 0x00000031 }, | |
81 | { 0x00935000, 0x000000c3 }, | |
82 | { 0x00936000, 0x000000c3 }, | |
83 | { 0x00970500, 0x00000400 }, | |
84 | { 0x00b37000, 0x00000097 }, | |
85 | { 0x00b37200, 0x00000097 }, | |
86 | { 0x00b37300, 0x00000097 }, | |
87 | { 0x00c37000, 0x00000000 }, | |
88 | { 0x00c37100, 0x00000080 }, | |
89 | { 0x01270500, 0x00000400 }, | |
90 | { 0x01370500, 0x00000400 }, | |
91 | { 0x01371f00, 0x411111f0 }, | |
92 | { 0x01439000, 0x00000080 }, | |
93 | { 0x0143a000, 0x00000080 }, | |
94 | { 0x01470700, 0x00000000 }, | |
95 | { 0x01470500, 0x00000400 }, | |
96 | { 0x01470c00, 0x00000000 }, | |
97 | { 0x01470100, 0x00000000 }, | |
98 | { 0x01837000, 0x00000000 }, | |
99 | { 0x01870500, 0x00000400 }, | |
100 | { 0x02050000, 0x00000000 }, | |
101 | { 0x02139000, 0x00000080 }, | |
102 | { 0x0213a000, 0x00000080 }, | |
103 | { 0x02170100, 0x00000000 }, | |
104 | { 0x02170500, 0x00000400 }, | |
105 | { 0x02170700, 0x00000000 }, | |
106 | { 0x02270100, 0x00000000 }, | |
107 | { 0x02370100, 0x00000000 }, | |
108 | { 0x02040000, 0x00004002 }, | |
109 | { 0x01870700, 0x00000020 }, | |
110 | { 0x00830000, 0x000000c3 }, | |
111 | { 0x00930000, 0x000000c3 }, | |
112 | { 0x01270700, 0x00000000 }, | |
113 | }; | |
114 | ||
115 | static bool rt286_volatile_register(struct device *dev, unsigned int reg) | |
116 | { | |
117 | switch (reg) { | |
118 | case 0 ... 0xff: | |
119 | case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID): | |
120 | case RT286_GET_HP_SENSE: | |
121 | case RT286_GET_MIC1_SENSE: | |
122 | case RT286_PROC_COEF: | |
123 | return true; | |
124 | default: | |
125 | return false; | |
126 | } | |
127 | ||
128 | ||
129 | } | |
130 | ||
131 | static bool rt286_readable_register(struct device *dev, unsigned int reg) | |
132 | { | |
133 | switch (reg) { | |
134 | case 0 ... 0xff: | |
135 | case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID): | |
136 | case RT286_GET_HP_SENSE: | |
137 | case RT286_GET_MIC1_SENSE: | |
138 | case RT286_SET_AUDIO_POWER: | |
139 | case RT286_SET_HPO_POWER: | |
140 | case RT286_SET_SPK_POWER: | |
141 | case RT286_SET_DMIC1_POWER: | |
142 | case RT286_SPK_MUX: | |
143 | case RT286_HPO_MUX: | |
144 | case RT286_ADC0_MUX: | |
145 | case RT286_ADC1_MUX: | |
146 | case RT286_SET_MIC1: | |
147 | case RT286_SET_PIN_HPO: | |
148 | case RT286_SET_PIN_SPK: | |
149 | case RT286_SET_PIN_DMIC1: | |
150 | case RT286_SPK_EAPD: | |
151 | case RT286_SET_AMP_GAIN_HPO: | |
152 | case RT286_SET_DMIC2_DEFAULT: | |
153 | case RT286_DACL_GAIN: | |
154 | case RT286_DACR_GAIN: | |
155 | case RT286_ADCL_GAIN: | |
156 | case RT286_ADCR_GAIN: | |
157 | case RT286_MIC_GAIN: | |
158 | case RT286_SPOL_GAIN: | |
159 | case RT286_SPOR_GAIN: | |
160 | case RT286_HPOL_GAIN: | |
161 | case RT286_HPOR_GAIN: | |
162 | case RT286_F_DAC_SWITCH: | |
163 | case RT286_F_RECMIX_SWITCH: | |
164 | case RT286_REC_MIC_SWITCH: | |
165 | case RT286_REC_I2S_SWITCH: | |
166 | case RT286_REC_LINE_SWITCH: | |
167 | case RT286_REC_BEEP_SWITCH: | |
168 | case RT286_DAC_FORMAT: | |
169 | case RT286_ADC_FORMAT: | |
170 | case RT286_COEF_INDEX: | |
171 | case RT286_PROC_COEF: | |
172 | case RT286_SET_AMP_GAIN_ADC_IN1: | |
173 | case RT286_SET_AMP_GAIN_ADC_IN2: | |
174 | case RT286_SET_POWER(RT286_DAC_OUT1): | |
175 | case RT286_SET_POWER(RT286_DAC_OUT2): | |
176 | case RT286_SET_POWER(RT286_ADC_IN1): | |
177 | case RT286_SET_POWER(RT286_ADC_IN2): | |
178 | case RT286_SET_POWER(RT286_DMIC2): | |
179 | case RT286_SET_POWER(RT286_MIC1): | |
180 | return true; | |
181 | default: | |
182 | return false; | |
183 | } | |
184 | } | |
185 | ||
186 | static int rt286_hw_write(void *context, unsigned int reg, unsigned int value) | |
187 | { | |
188 | struct i2c_client *client = context; | |
189 | struct rt286_priv *rt286 = i2c_get_clientdata(client); | |
190 | u8 data[4]; | |
191 | int ret, i; | |
192 | ||
193 | /*handle index registers*/ | |
194 | if (reg <= 0xff) { | |
195 | rt286_hw_write(client, RT286_COEF_INDEX, reg); | |
196 | reg = RT286_PROC_COEF; | |
197 | for (i = 0; i < INDEX_CACHE_SIZE; i++) { | |
198 | if (reg == rt286->index_cache[i].reg) { | |
199 | rt286->index_cache[i].def = value; | |
200 | break; | |
201 | } | |
202 | ||
203 | } | |
204 | } | |
205 | ||
206 | data[0] = (reg >> 24) & 0xff; | |
207 | data[1] = (reg >> 16) & 0xff; | |
208 | /* | |
209 | * 4 bit VID: reg should be 0 | |
210 | * 12 bit VID: value should be 0 | |
211 | * So we use an OR operator to handle it rather than use if condition. | |
212 | */ | |
213 | data[2] = ((reg >> 8) & 0xff) | ((value >> 8) & 0xff); | |
214 | data[3] = value & 0xff; | |
215 | ||
216 | ret = i2c_master_send(client, data, 4); | |
217 | ||
218 | if (ret == 4) | |
219 | return 0; | |
220 | else | |
221 | pr_err("ret=%d\n", ret); | |
222 | if (ret < 0) | |
223 | return ret; | |
224 | else | |
225 | return -EIO; | |
226 | } | |
227 | ||
228 | static int rt286_hw_read(void *context, unsigned int reg, unsigned int *value) | |
229 | { | |
230 | struct i2c_client *client = context; | |
231 | struct i2c_msg xfer[2]; | |
232 | int ret; | |
233 | __be32 be_reg; | |
234 | unsigned int index, vid, buf = 0x0; | |
235 | ||
236 | /*handle index registers*/ | |
237 | if (reg <= 0xff) { | |
238 | rt286_hw_write(client, RT286_COEF_INDEX, reg); | |
239 | reg = RT286_PROC_COEF; | |
240 | } | |
241 | ||
242 | reg = reg | 0x80000; | |
243 | vid = (reg >> 8) & 0xfff; | |
244 | ||
245 | if (AC_VERB_GET_AMP_GAIN_MUTE == (vid & 0xf00)) { | |
246 | index = (reg >> 8) & 0xf; | |
247 | reg = (reg & ~0xf0f) | index; | |
248 | } | |
249 | be_reg = cpu_to_be32(reg); | |
250 | ||
251 | /* Write register */ | |
252 | xfer[0].addr = client->addr; | |
253 | xfer[0].flags = 0; | |
254 | xfer[0].len = 4; | |
255 | xfer[0].buf = (u8 *)&be_reg; | |
256 | ||
257 | /* Read data */ | |
258 | xfer[1].addr = client->addr; | |
259 | xfer[1].flags = I2C_M_RD; | |
260 | xfer[1].len = 4; | |
261 | xfer[1].buf = (u8 *)&buf; | |
262 | ||
263 | ret = i2c_transfer(client->adapter, xfer, 2); | |
264 | if (ret < 0) | |
265 | return ret; | |
266 | else if (ret != 2) | |
267 | return -EIO; | |
268 | ||
269 | *value = be32_to_cpu(buf); | |
270 | ||
271 | return 0; | |
272 | } | |
273 | ||
274 | static void rt286_index_sync(struct snd_soc_codec *codec) | |
275 | { | |
276 | struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); | |
277 | int i; | |
278 | ||
279 | for (i = 0; i < INDEX_CACHE_SIZE; i++) { | |
280 | snd_soc_write(codec, rt286->index_cache[i].reg, | |
281 | rt286->index_cache[i].def); | |
282 | } | |
283 | } | |
284 | ||
285 | static int rt286_support_power_controls[] = { | |
286 | RT286_DAC_OUT1, | |
287 | RT286_DAC_OUT2, | |
288 | RT286_ADC_IN1, | |
289 | RT286_ADC_IN2, | |
290 | RT286_MIC1, | |
291 | RT286_DMIC1, | |
292 | RT286_DMIC2, | |
293 | RT286_SPK_OUT, | |
294 | RT286_HP_OUT, | |
295 | }; | |
296 | #define RT286_POWER_REG_LEN ARRAY_SIZE(rt286_support_power_controls) | |
297 | ||
298 | static int rt286_jack_detect(struct snd_soc_codec *codec, bool *hp, bool *mic) | |
299 | { | |
300 | struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); | |
301 | unsigned int val, buf; | |
302 | int i; | |
303 | ||
304 | *hp = false; | |
305 | *mic = false; | |
306 | ||
307 | if (rt286->pdata.cbj_en) { | |
308 | buf = snd_soc_read(codec, RT286_GET_HP_SENSE); | |
309 | *hp = buf & 0x80000000; | |
310 | if (*hp) { | |
311 | /* power on HV,VERF */ | |
312 | snd_soc_update_bits(codec, | |
313 | RT286_POWER_CTRL1, 0x1001, 0x0); | |
314 | /* power LDO1 */ | |
315 | snd_soc_update_bits(codec, | |
316 | RT286_POWER_CTRL2, 0x4, 0x4); | |
317 | snd_soc_write(codec, RT286_SET_MIC1, 0x24); | |
318 | val = snd_soc_read(codec, RT286_CBJ_CTRL2); | |
319 | ||
320 | msleep(200); | |
321 | i = 40; | |
322 | while (((val & 0x0800) == 0) && (i > 0)) { | |
323 | val = snd_soc_read(codec, | |
324 | RT286_CBJ_CTRL2); | |
325 | i--; | |
326 | msleep(20); | |
327 | } | |
328 | ||
329 | if (0x0400 == (val & 0x0700)) { | |
330 | *mic = false; | |
331 | ||
332 | snd_soc_write(codec, | |
333 | RT286_SET_MIC1, 0x20); | |
334 | /* power off HV,VERF */ | |
335 | snd_soc_update_bits(codec, | |
336 | RT286_POWER_CTRL1, 0x1001, 0x1001); | |
337 | snd_soc_update_bits(codec, | |
338 | RT286_A_BIAS_CTRL3, 0xc000, 0x0000); | |
339 | snd_soc_update_bits(codec, | |
340 | RT286_CBJ_CTRL1, 0x0030, 0x0000); | |
341 | snd_soc_update_bits(codec, | |
342 | RT286_A_BIAS_CTRL2, 0xc000, 0x0000); | |
343 | } else if ((0x0200 == (val & 0x0700)) || | |
344 | (0x0100 == (val & 0x0700))) { | |
345 | *mic = true; | |
346 | snd_soc_update_bits(codec, | |
347 | RT286_A_BIAS_CTRL3, 0xc000, 0x8000); | |
348 | snd_soc_update_bits(codec, | |
349 | RT286_CBJ_CTRL1, 0x0030, 0x0020); | |
350 | snd_soc_update_bits(codec, | |
351 | RT286_A_BIAS_CTRL2, 0xc000, 0x8000); | |
352 | } else { | |
353 | *mic = false; | |
354 | } | |
355 | ||
356 | snd_soc_update_bits(codec, | |
357 | RT286_MISC_CTRL1, | |
358 | 0x0060, 0x0000); | |
359 | } else { | |
360 | snd_soc_update_bits(codec, | |
361 | RT286_MISC_CTRL1, | |
362 | 0x0060, 0x0020); | |
363 | snd_soc_update_bits(codec, | |
364 | RT286_A_BIAS_CTRL3, | |
365 | 0xc000, 0x8000); | |
366 | snd_soc_update_bits(codec, | |
367 | RT286_CBJ_CTRL1, | |
368 | 0x0030, 0x0020); | |
369 | snd_soc_update_bits(codec, | |
370 | RT286_A_BIAS_CTRL2, | |
371 | 0xc000, 0x8000); | |
372 | ||
373 | *mic = false; | |
374 | } | |
375 | } else { | |
376 | buf = snd_soc_read(codec, RT286_GET_HP_SENSE); | |
377 | *hp = buf & 0x80000000; | |
378 | buf = snd_soc_read(codec, RT286_GET_MIC1_SENSE); | |
379 | *mic = buf & 0x80000000; | |
380 | } | |
381 | ||
382 | return 0; | |
383 | } | |
384 | ||
385 | static void rt286_jack_detect_work(struct work_struct *work) | |
386 | { | |
387 | struct rt286_priv *rt286 = | |
388 | container_of(work, struct rt286_priv, jack_detect_work.work); | |
389 | int status = 0; | |
390 | bool hp = false; | |
391 | bool mic = false; | |
392 | ||
393 | rt286_jack_detect(rt286->codec, &hp, &mic); | |
394 | ||
395 | if (hp == true) | |
396 | status |= SND_JACK_HEADPHONE; | |
397 | ||
398 | if (mic == true) | |
399 | status |= SND_JACK_MICROPHONE; | |
400 | ||
401 | snd_soc_jack_report(rt286->jack, status, | |
402 | SND_JACK_MICROPHONE | SND_JACK_HEADPHONE); | |
403 | } | |
404 | ||
405 | int rt286_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack) | |
406 | { | |
407 | struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); | |
408 | ||
409 | rt286->jack = jack; | |
410 | ||
411 | /* Send an initial empty report */ | |
412 | snd_soc_jack_report(rt286->jack, 0, | |
413 | SND_JACK_MICROPHONE | SND_JACK_HEADPHONE); | |
414 | ||
415 | return 0; | |
416 | } | |
417 | EXPORT_SYMBOL_GPL(rt286_mic_detect); | |
418 | ||
419 | static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0); | |
420 | static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0); | |
421 | ||
422 | static const struct snd_kcontrol_new rt286_snd_controls[] = { | |
423 | SOC_DOUBLE_R_TLV("DAC0 Playback Volume", RT286_DACL_GAIN, | |
424 | RT286_DACR_GAIN, 0, 0x7f, 0, out_vol_tlv), | |
425 | SOC_DOUBLE_R_TLV("ADC0 Capture Volume", RT286_ADCL_GAIN, | |
426 | RT286_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv), | |
427 | SOC_SINGLE_TLV("AMIC Volume", RT286_MIC_GAIN, | |
428 | 0, 0x3, 0, mic_vol_tlv), | |
429 | SOC_DOUBLE_R("Speaker Playback Switch", RT286_SPOL_GAIN, | |
430 | RT286_SPOR_GAIN, RT286_MUTE_SFT, 1, 1), | |
431 | }; | |
432 | ||
433 | /* Digital Mixer */ | |
434 | static const struct snd_kcontrol_new rt286_front_mix[] = { | |
435 | SOC_DAPM_SINGLE("DAC Switch", RT286_F_DAC_SWITCH, | |
436 | RT286_MUTE_SFT, 1, 1), | |
437 | SOC_DAPM_SINGLE("RECMIX Switch", RT286_F_RECMIX_SWITCH, | |
438 | RT286_MUTE_SFT, 1, 1), | |
439 | }; | |
440 | ||
441 | /* Analog Input Mixer */ | |
442 | static const struct snd_kcontrol_new rt286_rec_mix[] = { | |
443 | SOC_DAPM_SINGLE("Mic1 Switch", RT286_REC_MIC_SWITCH, | |
444 | RT286_MUTE_SFT, 1, 1), | |
445 | SOC_DAPM_SINGLE("I2S Switch", RT286_REC_I2S_SWITCH, | |
446 | RT286_MUTE_SFT, 1, 1), | |
447 | SOC_DAPM_SINGLE("Line1 Switch", RT286_REC_LINE_SWITCH, | |
448 | RT286_MUTE_SFT, 1, 1), | |
449 | SOC_DAPM_SINGLE("Beep Switch", RT286_REC_BEEP_SWITCH, | |
450 | RT286_MUTE_SFT, 1, 1), | |
451 | }; | |
452 | ||
453 | static const struct snd_kcontrol_new spo_enable_control = | |
454 | SOC_DAPM_SINGLE("Switch", RT286_SET_PIN_SPK, | |
455 | RT286_SET_PIN_SFT, 1, 0); | |
456 | ||
457 | static const struct snd_kcontrol_new hpol_enable_control = | |
458 | SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOL_GAIN, | |
459 | RT286_MUTE_SFT, 1, 1); | |
460 | ||
461 | static const struct snd_kcontrol_new hpor_enable_control = | |
462 | SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOR_GAIN, | |
463 | RT286_MUTE_SFT, 1, 1); | |
464 | ||
465 | /* ADC0 source */ | |
466 | static const char * const rt286_adc_src[] = { | |
467 | "Mic", "RECMIX", "Dmic" | |
468 | }; | |
469 | ||
470 | static const int rt286_adc_values[] = { | |
471 | 0, 4, 5, | |
472 | }; | |
473 | ||
474 | static SOC_VALUE_ENUM_SINGLE_DECL( | |
475 | rt286_adc0_enum, RT286_ADC0_MUX, RT286_ADC_SEL_SFT, | |
476 | RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values); | |
477 | ||
478 | static const struct snd_kcontrol_new rt286_adc0_mux = | |
479 | SOC_DAPM_ENUM("ADC 0 source", rt286_adc0_enum); | |
480 | ||
481 | static SOC_VALUE_ENUM_SINGLE_DECL( | |
482 | rt286_adc1_enum, RT286_ADC1_MUX, RT286_ADC_SEL_SFT, | |
483 | RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values); | |
484 | ||
485 | static const struct snd_kcontrol_new rt286_adc1_mux = | |
486 | SOC_DAPM_ENUM("ADC 1 source", rt286_adc1_enum); | |
487 | ||
488 | static const char * const rt286_dac_src[] = { | |
489 | "Front", "Surround" | |
490 | }; | |
491 | /* HP-OUT source */ | |
492 | static SOC_ENUM_SINGLE_DECL(rt286_hpo_enum, RT286_HPO_MUX, | |
493 | 0, rt286_dac_src); | |
494 | ||
495 | static const struct snd_kcontrol_new rt286_hpo_mux = | |
496 | SOC_DAPM_ENUM("HPO source", rt286_hpo_enum); | |
497 | ||
498 | /* SPK-OUT source */ | |
499 | static SOC_ENUM_SINGLE_DECL(rt286_spo_enum, RT286_SPK_MUX, | |
500 | 0, rt286_dac_src); | |
501 | ||
502 | static const struct snd_kcontrol_new rt286_spo_mux = | |
503 | SOC_DAPM_ENUM("SPO source", rt286_spo_enum); | |
504 | ||
505 | static int rt286_spk_event(struct snd_soc_dapm_widget *w, | |
506 | struct snd_kcontrol *kcontrol, int event) | |
507 | { | |
508 | struct snd_soc_codec *codec = w->codec; | |
509 | ||
510 | switch (event) { | |
511 | case SND_SOC_DAPM_POST_PMU: | |
512 | snd_soc_write(codec, | |
513 | RT286_SPK_EAPD, RT286_SET_EAPD_HIGH); | |
514 | break; | |
515 | case SND_SOC_DAPM_PRE_PMD: | |
516 | snd_soc_write(codec, | |
517 | RT286_SPK_EAPD, RT286_SET_EAPD_LOW); | |
518 | break; | |
519 | ||
520 | default: | |
521 | return 0; | |
522 | } | |
523 | ||
524 | return 0; | |
525 | } | |
526 | ||
527 | static int rt286_set_dmic1_event(struct snd_soc_dapm_widget *w, | |
528 | struct snd_kcontrol *kcontrol, int event) | |
529 | { | |
530 | struct snd_soc_codec *codec = w->codec; | |
531 | ||
532 | switch (event) { | |
533 | case SND_SOC_DAPM_POST_PMU: | |
534 | snd_soc_write(codec, RT286_SET_PIN_DMIC1, 0x20); | |
535 | break; | |
536 | case SND_SOC_DAPM_PRE_PMD: | |
537 | snd_soc_write(codec, RT286_SET_PIN_DMIC1, 0); | |
538 | break; | |
539 | default: | |
540 | return 0; | |
541 | } | |
542 | ||
543 | return 0; | |
544 | } | |
545 | ||
546 | static int rt286_adc_event(struct snd_soc_dapm_widget *w, | |
547 | struct snd_kcontrol *kcontrol, int event) | |
548 | { | |
549 | struct snd_soc_codec *codec = w->codec; | |
550 | unsigned int nid; | |
551 | ||
552 | nid = (w->reg >> 20) & 0xff; | |
553 | ||
554 | switch (event) { | |
555 | case SND_SOC_DAPM_POST_PMU: | |
556 | snd_soc_update_bits(codec, | |
557 | VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, nid, 0), | |
558 | 0x7080, 0x7000); | |
559 | break; | |
560 | case SND_SOC_DAPM_PRE_PMD: | |
561 | snd_soc_update_bits(codec, | |
562 | VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, nid, 0), | |
563 | 0x7080, 0x7080); | |
564 | break; | |
565 | default: | |
566 | return 0; | |
567 | } | |
568 | ||
569 | return 0; | |
570 | } | |
571 | ||
572 | static const struct snd_soc_dapm_widget rt286_dapm_widgets[] = { | |
573 | /* Input Lines */ | |
574 | SND_SOC_DAPM_INPUT("DMIC1 Pin"), | |
575 | SND_SOC_DAPM_INPUT("DMIC2 Pin"), | |
576 | SND_SOC_DAPM_INPUT("MIC1"), | |
577 | SND_SOC_DAPM_INPUT("LINE1"), | |
578 | SND_SOC_DAPM_INPUT("Beep"), | |
579 | ||
580 | /* DMIC */ | |
581 | SND_SOC_DAPM_PGA_E("DMIC1", RT286_SET_POWER(RT286_DMIC1), 0, 1, | |
582 | NULL, 0, rt286_set_dmic1_event, | |
583 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), | |
584 | SND_SOC_DAPM_PGA("DMIC2", RT286_SET_POWER(RT286_DMIC2), 0, 1, | |
585 | NULL, 0), | |
586 | SND_SOC_DAPM_SUPPLY("DMIC Receiver", SND_SOC_NOPM, | |
587 | 0, 0, NULL, 0), | |
588 | ||
589 | /* REC Mixer */ | |
590 | SND_SOC_DAPM_MIXER("RECMIX", SND_SOC_NOPM, 0, 0, | |
591 | rt286_rec_mix, ARRAY_SIZE(rt286_rec_mix)), | |
592 | ||
593 | /* ADCs */ | |
594 | SND_SOC_DAPM_ADC("ADC 0", NULL, SND_SOC_NOPM, 0, 0), | |
595 | SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0), | |
596 | ||
597 | /* ADC Mux */ | |
598 | SND_SOC_DAPM_MUX_E("ADC 0 Mux", RT286_SET_POWER(RT286_ADC_IN1), 0, 1, | |
599 | &rt286_adc0_mux, rt286_adc_event, SND_SOC_DAPM_PRE_PMD | | |
600 | SND_SOC_DAPM_POST_PMU), | |
601 | SND_SOC_DAPM_MUX_E("ADC 1 Mux", RT286_SET_POWER(RT286_ADC_IN2), 0, 1, | |
602 | &rt286_adc1_mux, rt286_adc_event, SND_SOC_DAPM_PRE_PMD | | |
603 | SND_SOC_DAPM_POST_PMU), | |
604 | ||
605 | /* Audio Interface */ | |
606 | SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), | |
607 | SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), | |
608 | SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), | |
609 | SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), | |
610 | ||
611 | /* Output Side */ | |
612 | /* DACs */ | |
613 | SND_SOC_DAPM_DAC("DAC 0", NULL, SND_SOC_NOPM, 0, 0), | |
614 | SND_SOC_DAPM_DAC("DAC 1", NULL, SND_SOC_NOPM, 0, 0), | |
615 | ||
616 | /* Output Mux */ | |
617 | SND_SOC_DAPM_MUX("SPK Mux", SND_SOC_NOPM, 0, 0, &rt286_spo_mux), | |
618 | SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt286_hpo_mux), | |
619 | ||
620 | SND_SOC_DAPM_SUPPLY("HP Power", RT286_SET_PIN_HPO, | |
621 | RT286_SET_PIN_SFT, 0, NULL, 0), | |
622 | ||
623 | /* Output Mixer */ | |
624 | SND_SOC_DAPM_MIXER("Front", RT286_SET_POWER(RT286_DAC_OUT1), 0, 1, | |
625 | rt286_front_mix, ARRAY_SIZE(rt286_front_mix)), | |
626 | SND_SOC_DAPM_PGA("Surround", RT286_SET_POWER(RT286_DAC_OUT2), 0, 1, | |
627 | NULL, 0), | |
628 | ||
629 | /* Output Pga */ | |
630 | SND_SOC_DAPM_SWITCH_E("SPO", SND_SOC_NOPM, 0, 0, | |
631 | &spo_enable_control, rt286_spk_event, | |
632 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), | |
633 | SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0, | |
634 | &hpol_enable_control), | |
635 | SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0, | |
636 | &hpor_enable_control), | |
637 | ||
638 | /* Output Lines */ | |
639 | SND_SOC_DAPM_OUTPUT("SPOL"), | |
640 | SND_SOC_DAPM_OUTPUT("SPOR"), | |
641 | SND_SOC_DAPM_OUTPUT("HPO Pin"), | |
642 | SND_SOC_DAPM_OUTPUT("SPDIF"), | |
643 | }; | |
644 | ||
645 | static const struct snd_soc_dapm_route rt286_dapm_routes[] = { | |
646 | {"DMIC1", NULL, "DMIC1 Pin"}, | |
647 | {"DMIC2", NULL, "DMIC2 Pin"}, | |
648 | {"DMIC1", NULL, "DMIC Receiver"}, | |
649 | {"DMIC2", NULL, "DMIC Receiver"}, | |
650 | ||
651 | {"RECMIX", "Beep Switch", "Beep"}, | |
652 | {"RECMIX", "Line1 Switch", "LINE1"}, | |
653 | {"RECMIX", "Mic1 Switch", "MIC1"}, | |
654 | ||
655 | {"ADC 0 Mux", "Dmic", "DMIC1"}, | |
656 | {"ADC 0 Mux", "RECMIX", "RECMIX"}, | |
657 | {"ADC 0 Mux", "Mic", "MIC1"}, | |
658 | {"ADC 1 Mux", "Dmic", "DMIC2"}, | |
659 | {"ADC 1 Mux", "RECMIX", "RECMIX"}, | |
660 | {"ADC 1 Mux", "Mic", "MIC1"}, | |
661 | ||
662 | {"ADC 0", NULL, "ADC 0 Mux"}, | |
663 | {"ADC 1", NULL, "ADC 1 Mux"}, | |
664 | ||
665 | {"AIF1TX", NULL, "ADC 0"}, | |
666 | {"AIF2TX", NULL, "ADC 1"}, | |
667 | ||
668 | {"DAC 0", NULL, "AIF1RX"}, | |
669 | {"DAC 1", NULL, "AIF2RX"}, | |
670 | ||
671 | {"Front", "DAC Switch", "DAC 0"}, | |
672 | {"Front", "RECMIX Switch", "RECMIX"}, | |
673 | ||
674 | {"Surround", NULL, "DAC 1"}, | |
675 | ||
676 | {"SPK Mux", "Front", "Front"}, | |
677 | {"SPK Mux", "Surround", "Surround"}, | |
678 | ||
679 | {"HPO Mux", "Front", "Front"}, | |
680 | {"HPO Mux", "Surround", "Surround"}, | |
681 | ||
682 | {"SPO", "Switch", "SPK Mux"}, | |
683 | {"HPO L", "Switch", "HPO Mux"}, | |
684 | {"HPO R", "Switch", "HPO Mux"}, | |
685 | {"HPO L", NULL, "HP Power"}, | |
686 | {"HPO R", NULL, "HP Power"}, | |
687 | ||
688 | {"SPOL", NULL, "SPO"}, | |
689 | {"SPOR", NULL, "SPO"}, | |
690 | {"HPO Pin", NULL, "HPO L"}, | |
691 | {"HPO Pin", NULL, "HPO R"}, | |
692 | }; | |
693 | ||
694 | static int rt286_hw_params(struct snd_pcm_substream *substream, | |
695 | struct snd_pcm_hw_params *params, | |
696 | struct snd_soc_dai *dai) | |
697 | { | |
698 | struct snd_soc_codec *codec = dai->codec; | |
699 | struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); | |
700 | unsigned int val = 0; | |
701 | int d_len_code; | |
702 | ||
703 | switch (params_rate(params)) { | |
704 | /* bit 14 0:48K 1:44.1K */ | |
705 | case 44100: | |
706 | val |= 0x4000; | |
707 | break; | |
708 | case 48000: | |
709 | break; | |
710 | default: | |
711 | dev_err(codec->dev, "Unsupported sample rate %d\n", | |
712 | params_rate(params)); | |
713 | return -EINVAL; | |
714 | } | |
715 | switch (rt286->sys_clk) { | |
716 | case 12288000: | |
717 | case 24576000: | |
718 | if (params_rate(params) != 48000) { | |
719 | dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n", | |
720 | params_rate(params), rt286->sys_clk); | |
721 | return -EINVAL; | |
722 | } | |
723 | break; | |
724 | case 11289600: | |
725 | case 22579200: | |
726 | if (params_rate(params) != 44100) { | |
727 | dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n", | |
728 | params_rate(params), rt286->sys_clk); | |
729 | return -EINVAL; | |
730 | } | |
731 | break; | |
732 | } | |
733 | ||
734 | if (params_channels(params) <= 16) { | |
735 | /* bit 3:0 Number of Channel */ | |
736 | val |= (params_channels(params) - 1); | |
737 | } else { | |
738 | dev_err(codec->dev, "Unsupported channels %d\n", | |
739 | params_channels(params)); | |
740 | return -EINVAL; | |
741 | } | |
742 | ||
743 | d_len_code = 0; | |
744 | switch (params_width(params)) { | |
745 | /* bit 6:4 Bits per Sample */ | |
746 | case 16: | |
747 | d_len_code = 0; | |
748 | val |= (0x1 << 4); | |
749 | break; | |
750 | case 32: | |
751 | d_len_code = 2; | |
752 | val |= (0x4 << 4); | |
753 | break; | |
754 | case 20: | |
755 | d_len_code = 1; | |
756 | val |= (0x2 << 4); | |
757 | break; | |
758 | case 24: | |
759 | d_len_code = 2; | |
760 | val |= (0x3 << 4); | |
761 | break; | |
762 | case 8: | |
763 | d_len_code = 3; | |
764 | break; | |
765 | default: | |
766 | return -EINVAL; | |
767 | } | |
768 | ||
769 | snd_soc_update_bits(codec, | |
770 | RT286_I2S_CTRL1, 0x0018, d_len_code << 3); | |
771 | dev_dbg(codec->dev, "format val = 0x%x\n", val); | |
772 | ||
773 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
774 | snd_soc_update_bits(codec, RT286_DAC_FORMAT, 0x407f, val); | |
775 | else | |
776 | snd_soc_update_bits(codec, RT286_ADC_FORMAT, 0x407f, val); | |
777 | ||
778 | return 0; | |
779 | } | |
780 | ||
781 | static int rt286_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) | |
782 | { | |
783 | struct snd_soc_codec *codec = dai->codec; | |
784 | ||
785 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
786 | case SND_SOC_DAIFMT_CBM_CFM: | |
787 | snd_soc_update_bits(codec, | |
788 | RT286_I2S_CTRL1, 0x800, 0x800); | |
789 | break; | |
790 | case SND_SOC_DAIFMT_CBS_CFS: | |
791 | snd_soc_update_bits(codec, | |
792 | RT286_I2S_CTRL1, 0x800, 0x0); | |
793 | break; | |
794 | default: | |
795 | return -EINVAL; | |
796 | } | |
797 | ||
798 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
799 | case SND_SOC_DAIFMT_I2S: | |
800 | snd_soc_update_bits(codec, | |
801 | RT286_I2S_CTRL1, 0x300, 0x0); | |
802 | break; | |
803 | case SND_SOC_DAIFMT_LEFT_J: | |
804 | snd_soc_update_bits(codec, | |
805 | RT286_I2S_CTRL1, 0x300, 0x1 << 8); | |
806 | break; | |
807 | case SND_SOC_DAIFMT_DSP_A: | |
808 | snd_soc_update_bits(codec, | |
809 | RT286_I2S_CTRL1, 0x300, 0x2 << 8); | |
810 | break; | |
811 | case SND_SOC_DAIFMT_DSP_B: | |
812 | snd_soc_update_bits(codec, | |
813 | RT286_I2S_CTRL1, 0x300, 0x3 << 8); | |
814 | break; | |
815 | default: | |
816 | return -EINVAL; | |
817 | } | |
818 | /* bit 15 Stream Type 0:PCM 1:Non-PCM */ | |
819 | snd_soc_update_bits(codec, RT286_DAC_FORMAT, 0x8000, 0); | |
820 | snd_soc_update_bits(codec, RT286_ADC_FORMAT, 0x8000, 0); | |
821 | ||
822 | return 0; | |
823 | } | |
824 | ||
825 | static int rt286_set_dai_sysclk(struct snd_soc_dai *dai, | |
826 | int clk_id, unsigned int freq, int dir) | |
827 | { | |
828 | struct snd_soc_codec *codec = dai->codec; | |
829 | struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); | |
830 | ||
831 | dev_dbg(codec->dev, "%s freq=%d\n", __func__, freq); | |
832 | ||
833 | if (RT286_SCLK_S_MCLK == clk_id) { | |
834 | snd_soc_update_bits(codec, | |
835 | RT286_I2S_CTRL2, 0x0100, 0x0); | |
836 | snd_soc_update_bits(codec, | |
837 | RT286_PLL_CTRL1, 0x20, 0x20); | |
838 | } else { | |
839 | snd_soc_update_bits(codec, | |
840 | RT286_I2S_CTRL2, 0x0100, 0x0100); | |
841 | snd_soc_update_bits(codec, | |
842 | RT286_PLL_CTRL, 0x4, 0x4); | |
843 | snd_soc_update_bits(codec, | |
844 | RT286_PLL_CTRL1, 0x20, 0x0); | |
845 | } | |
846 | ||
847 | switch (freq) { | |
848 | case 19200000: | |
849 | if (RT286_SCLK_S_MCLK == clk_id) { | |
850 | dev_err(codec->dev, "Should not use MCLK\n"); | |
851 | return -EINVAL; | |
852 | } | |
853 | snd_soc_update_bits(codec, | |
854 | RT286_I2S_CTRL2, 0x40, 0x40); | |
855 | break; | |
856 | case 24000000: | |
857 | if (RT286_SCLK_S_MCLK == clk_id) { | |
858 | dev_err(codec->dev, "Should not use MCLK\n"); | |
859 | return -EINVAL; | |
860 | } | |
861 | snd_soc_update_bits(codec, | |
862 | RT286_I2S_CTRL2, 0x40, 0x0); | |
863 | break; | |
864 | case 12288000: | |
865 | case 11289600: | |
866 | snd_soc_update_bits(codec, | |
867 | RT286_I2S_CTRL2, 0x8, 0x0); | |
868 | snd_soc_update_bits(codec, | |
869 | RT286_CLK_DIV, 0xfc1e, 0x0004); | |
870 | break; | |
871 | case 24576000: | |
872 | case 22579200: | |
873 | snd_soc_update_bits(codec, | |
874 | RT286_I2S_CTRL2, 0x8, 0x8); | |
875 | snd_soc_update_bits(codec, | |
876 | RT286_CLK_DIV, 0xfc1e, 0x5406); | |
877 | break; | |
878 | default: | |
879 | dev_err(codec->dev, "Unsupported system clock\n"); | |
880 | return -EINVAL; | |
881 | } | |
882 | ||
883 | rt286->sys_clk = freq; | |
884 | ||
885 | return 0; | |
886 | } | |
887 | ||
888 | static int rt286_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) | |
889 | { | |
890 | struct snd_soc_codec *codec = dai->codec; | |
891 | ||
892 | dev_dbg(codec->dev, "%s ratio=%d\n", __func__, ratio); | |
893 | if (50 == ratio) | |
894 | snd_soc_update_bits(codec, | |
895 | RT286_I2S_CTRL1, 0x1000, 0x1000); | |
896 | else | |
897 | snd_soc_update_bits(codec, | |
898 | RT286_I2S_CTRL1, 0x1000, 0x0); | |
899 | ||
900 | ||
901 | return 0; | |
902 | } | |
903 | ||
904 | static int rt286_set_bias_level(struct snd_soc_codec *codec, | |
905 | enum snd_soc_bias_level level) | |
906 | { | |
907 | switch (level) { | |
908 | case SND_SOC_BIAS_PREPARE: | |
bc6c4e45 | 909 | if (SND_SOC_BIAS_STANDBY == codec->dapm.bias_level) { |
07cf7cba BL |
910 | snd_soc_write(codec, |
911 | RT286_SET_AUDIO_POWER, AC_PWRST_D0); | |
bc6c4e45 BL |
912 | snd_soc_update_bits(codec, |
913 | RT286_DC_GAIN, 0x200, 0x200); | |
914 | } | |
915 | break; | |
916 | ||
917 | case SND_SOC_BIAS_ON: | |
918 | mdelay(10); | |
07cf7cba BL |
919 | break; |
920 | ||
921 | case SND_SOC_BIAS_STANDBY: | |
922 | snd_soc_write(codec, | |
923 | RT286_SET_AUDIO_POWER, AC_PWRST_D3); | |
bc6c4e45 BL |
924 | snd_soc_update_bits(codec, |
925 | RT286_DC_GAIN, 0x200, 0x0); | |
07cf7cba BL |
926 | break; |
927 | ||
928 | default: | |
929 | break; | |
930 | } | |
931 | codec->dapm.bias_level = level; | |
932 | ||
933 | return 0; | |
934 | } | |
935 | ||
936 | static irqreturn_t rt286_irq(int irq, void *data) | |
937 | { | |
938 | struct rt286_priv *rt286 = data; | |
939 | bool hp = false; | |
940 | bool mic = false; | |
941 | int status = 0; | |
942 | ||
943 | rt286_jack_detect(rt286->codec, &hp, &mic); | |
944 | ||
945 | /* Clear IRQ */ | |
946 | snd_soc_update_bits(rt286->codec, | |
947 | RT286_IRQ_CTRL, 0x1, 0x1); | |
948 | ||
949 | if (hp == true) | |
950 | status |= SND_JACK_HEADPHONE; | |
951 | ||
952 | if (mic == true) | |
953 | status |= SND_JACK_MICROPHONE; | |
954 | ||
955 | snd_soc_jack_report(rt286->jack, status, | |
956 | SND_JACK_MICROPHONE | SND_JACK_HEADPHONE); | |
957 | ||
958 | pm_wakeup_event(&rt286->i2c->dev, 300); | |
959 | ||
960 | return IRQ_HANDLED; | |
961 | } | |
962 | ||
963 | static int rt286_probe(struct snd_soc_codec *codec) | |
964 | { | |
965 | struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); | |
07cf7cba BL |
966 | |
967 | codec->dapm.bias_level = SND_SOC_BIAS_OFF; | |
968 | rt286->codec = codec; | |
969 | ||
07cf7cba BL |
970 | return 0; |
971 | } | |
972 | ||
973 | static int rt286_remove(struct snd_soc_codec *codec) | |
974 | { | |
975 | struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); | |
976 | ||
977 | cancel_delayed_work_sync(&rt286->jack_detect_work); | |
978 | ||
979 | return 0; | |
980 | } | |
981 | ||
982 | #ifdef CONFIG_PM | |
983 | static int rt286_suspend(struct snd_soc_codec *codec) | |
984 | { | |
985 | struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); | |
986 | ||
987 | regcache_cache_only(rt286->regmap, true); | |
988 | regcache_mark_dirty(rt286->regmap); | |
989 | ||
990 | return 0; | |
991 | } | |
992 | ||
993 | static int rt286_resume(struct snd_soc_codec *codec) | |
994 | { | |
995 | struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec); | |
996 | ||
997 | regcache_cache_only(rt286->regmap, false); | |
998 | rt286_index_sync(codec); | |
999 | regcache_sync(rt286->regmap); | |
1000 | ||
1001 | return 0; | |
1002 | } | |
1003 | #else | |
1004 | #define rt286_suspend NULL | |
1005 | #define rt286_resume NULL | |
1006 | #endif | |
1007 | ||
1008 | #define RT286_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) | |
1009 | #define RT286_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ | |
1010 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) | |
1011 | ||
1012 | static const struct snd_soc_dai_ops rt286_aif_dai_ops = { | |
1013 | .hw_params = rt286_hw_params, | |
1014 | .set_fmt = rt286_set_dai_fmt, | |
1015 | .set_sysclk = rt286_set_dai_sysclk, | |
1016 | .set_bclk_ratio = rt286_set_bclk_ratio, | |
1017 | }; | |
1018 | ||
1019 | static struct snd_soc_dai_driver rt286_dai[] = { | |
1020 | { | |
1021 | .name = "rt286-aif1", | |
1022 | .id = RT286_AIF1, | |
1023 | .playback = { | |
1024 | .stream_name = "AIF1 Playback", | |
1025 | .channels_min = 1, | |
1026 | .channels_max = 2, | |
1027 | .rates = RT286_STEREO_RATES, | |
1028 | .formats = RT286_FORMATS, | |
1029 | }, | |
1030 | .capture = { | |
1031 | .stream_name = "AIF1 Capture", | |
1032 | .channels_min = 1, | |
1033 | .channels_max = 2, | |
1034 | .rates = RT286_STEREO_RATES, | |
1035 | .formats = RT286_FORMATS, | |
1036 | }, | |
1037 | .ops = &rt286_aif_dai_ops, | |
1038 | .symmetric_rates = 1, | |
1039 | }, | |
1040 | { | |
1041 | .name = "rt286-aif2", | |
1042 | .id = RT286_AIF2, | |
1043 | .playback = { | |
1044 | .stream_name = "AIF2 Playback", | |
1045 | .channels_min = 1, | |
1046 | .channels_max = 2, | |
1047 | .rates = RT286_STEREO_RATES, | |
1048 | .formats = RT286_FORMATS, | |
1049 | }, | |
1050 | .capture = { | |
1051 | .stream_name = "AIF2 Capture", | |
1052 | .channels_min = 1, | |
1053 | .channels_max = 2, | |
1054 | .rates = RT286_STEREO_RATES, | |
1055 | .formats = RT286_FORMATS, | |
1056 | }, | |
1057 | .ops = &rt286_aif_dai_ops, | |
1058 | .symmetric_rates = 1, | |
1059 | }, | |
1060 | ||
1061 | }; | |
1062 | ||
1063 | static struct snd_soc_codec_driver soc_codec_dev_rt286 = { | |
1064 | .probe = rt286_probe, | |
1065 | .remove = rt286_remove, | |
1066 | .suspend = rt286_suspend, | |
1067 | .resume = rt286_resume, | |
1068 | .set_bias_level = rt286_set_bias_level, | |
1069 | .idle_bias_off = true, | |
1070 | .controls = rt286_snd_controls, | |
1071 | .num_controls = ARRAY_SIZE(rt286_snd_controls), | |
1072 | .dapm_widgets = rt286_dapm_widgets, | |
1073 | .num_dapm_widgets = ARRAY_SIZE(rt286_dapm_widgets), | |
1074 | .dapm_routes = rt286_dapm_routes, | |
1075 | .num_dapm_routes = ARRAY_SIZE(rt286_dapm_routes), | |
1076 | }; | |
1077 | ||
1078 | static const struct regmap_config rt286_regmap = { | |
1079 | .reg_bits = 32, | |
1080 | .val_bits = 32, | |
1081 | .max_register = 0x02370100, | |
1082 | .volatile_reg = rt286_volatile_register, | |
1083 | .readable_reg = rt286_readable_register, | |
1084 | .reg_write = rt286_hw_write, | |
1085 | .reg_read = rt286_hw_read, | |
1086 | .cache_type = REGCACHE_RBTREE, | |
1087 | .reg_defaults = rt286_reg, | |
1088 | .num_reg_defaults = ARRAY_SIZE(rt286_reg), | |
1089 | }; | |
1090 | ||
1091 | static const struct i2c_device_id rt286_i2c_id[] = { | |
1092 | {"rt286", 0}, | |
1093 | {} | |
1094 | }; | |
1095 | MODULE_DEVICE_TABLE(i2c, rt286_i2c_id); | |
1096 | ||
1097 | static const struct acpi_device_id rt286_acpi_match[] = { | |
1098 | { "INT343A", 0 }, | |
1099 | {}, | |
1100 | }; | |
1101 | MODULE_DEVICE_TABLE(acpi, rt286_acpi_match); | |
1102 | ||
1103 | static int rt286_i2c_probe(struct i2c_client *i2c, | |
1104 | const struct i2c_device_id *id) | |
1105 | { | |
1106 | struct rt286_platform_data *pdata = dev_get_platdata(&i2c->dev); | |
1107 | struct rt286_priv *rt286; | |
61a414c4 | 1108 | int i, ret; |
07cf7cba BL |
1109 | |
1110 | rt286 = devm_kzalloc(&i2c->dev, sizeof(*rt286), | |
1111 | GFP_KERNEL); | |
1112 | if (NULL == rt286) | |
1113 | return -ENOMEM; | |
1114 | ||
1115 | rt286->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt286_regmap); | |
1116 | if (IS_ERR(rt286->regmap)) { | |
1117 | ret = PTR_ERR(rt286->regmap); | |
1118 | dev_err(&i2c->dev, "Failed to allocate register map: %d\n", | |
1119 | ret); | |
1120 | return ret; | |
1121 | } | |
1122 | ||
4b21768a BL |
1123 | regmap_read(rt286->regmap, |
1124 | RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &ret); | |
1125 | if (ret != RT286_VENDOR_ID) { | |
1126 | dev_err(&i2c->dev, | |
1127 | "Device with ID register %x is not rt286\n", ret); | |
1128 | return -ENODEV; | |
1129 | } | |
1130 | ||
07cf7cba BL |
1131 | rt286->index_cache = rt286_index_def; |
1132 | rt286->i2c = i2c; | |
1133 | i2c_set_clientdata(i2c, rt286); | |
1134 | ||
1135 | if (pdata) | |
1136 | rt286->pdata = *pdata; | |
1137 | ||
61a414c4 BL |
1138 | regmap_write(rt286->regmap, RT286_SET_AUDIO_POWER, AC_PWRST_D3); |
1139 | ||
1140 | for (i = 0; i < RT286_POWER_REG_LEN; i++) | |
1141 | regmap_write(rt286->regmap, | |
1142 | RT286_SET_POWER(rt286_support_power_controls[i]), | |
1143 | AC_PWRST_D1); | |
1144 | ||
1145 | if (!rt286->pdata.cbj_en) { | |
1146 | regmap_write(rt286->regmap, RT286_CBJ_CTRL2, 0x0000); | |
1147 | regmap_write(rt286->regmap, RT286_MIC1_DET_CTRL, 0x0816); | |
1148 | regmap_write(rt286->regmap, RT286_MISC_CTRL1, 0x0000); | |
1149 | regmap_update_bits(rt286->regmap, | |
1150 | RT286_CBJ_CTRL1, 0xf000, 0xb000); | |
1151 | } else { | |
1152 | regmap_update_bits(rt286->regmap, | |
1153 | RT286_CBJ_CTRL1, 0xf000, 0x5000); | |
1154 | } | |
1155 | ||
1156 | mdelay(10); | |
1157 | ||
1158 | if (!rt286->pdata.gpio2_en) | |
1159 | regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0x4000); | |
1160 | else | |
1161 | regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0); | |
1162 | ||
1163 | mdelay(10); | |
1164 | ||
1165 | /*Power down LDO2*/ | |
1166 | regmap_update_bits(rt286->regmap, RT286_POWER_CTRL2, 0x8, 0x0); | |
1167 | ||
bc6c4e45 BL |
1168 | /*Set depop parameter*/ |
1169 | regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL2, 0x403a, 0x401a); | |
1170 | regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL3, 0xf777, 0x4737); | |
1171 | regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL4, 0x00ff, 0x003f); | |
1172 | ||
61a414c4 BL |
1173 | if (rt286->i2c->irq) { |
1174 | regmap_update_bits(rt286->regmap, | |
1175 | RT286_IRQ_CTRL, 0x2, 0x2); | |
1176 | ||
1177 | INIT_DELAYED_WORK(&rt286->jack_detect_work, | |
1178 | rt286_jack_detect_work); | |
1179 | schedule_delayed_work(&rt286->jack_detect_work, | |
1180 | msecs_to_jiffies(1250)); | |
1181 | ||
1182 | ret = request_threaded_irq(rt286->i2c->irq, NULL, rt286_irq, | |
1183 | IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt286", rt286); | |
1184 | if (ret != 0) { | |
1185 | dev_err(&i2c->dev, | |
1186 | "Failed to reguest IRQ: %d\n", ret); | |
1187 | return ret; | |
1188 | } | |
1189 | } | |
1190 | ||
07cf7cba BL |
1191 | ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt286, |
1192 | rt286_dai, ARRAY_SIZE(rt286_dai)); | |
1193 | ||
1194 | return ret; | |
1195 | } | |
1196 | ||
1197 | static int rt286_i2c_remove(struct i2c_client *i2c) | |
1198 | { | |
1199 | struct rt286_priv *rt286 = i2c_get_clientdata(i2c); | |
1200 | ||
1201 | if (i2c->irq) | |
1202 | free_irq(i2c->irq, rt286); | |
1203 | snd_soc_unregister_codec(&i2c->dev); | |
1204 | ||
1205 | return 0; | |
1206 | } | |
1207 | ||
1208 | ||
23c4fd5c | 1209 | static struct i2c_driver rt286_i2c_driver = { |
07cf7cba BL |
1210 | .driver = { |
1211 | .name = "rt286", | |
1212 | .owner = THIS_MODULE, | |
1213 | .acpi_match_table = ACPI_PTR(rt286_acpi_match), | |
1214 | }, | |
1215 | .probe = rt286_i2c_probe, | |
1216 | .remove = rt286_i2c_remove, | |
1217 | .id_table = rt286_i2c_id, | |
1218 | }; | |
1219 | ||
1220 | module_i2c_driver(rt286_i2c_driver); | |
1221 | ||
1222 | MODULE_DESCRIPTION("ASoC RT286 driver"); | |
1223 | MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); | |
1224 | MODULE_LICENSE("GPL"); |