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ASoC: rt5663: Optimize the Jack Type detection
[mirror_ubuntu-bionic-kernel.git] / sound / soc / codecs / rt5663.c
CommitLineData
df7c5216 1/*
73444723 2 * rt5663.c -- RT5663 ALSA SoC audio codec driver
df7c5216
BL		 3 *
4 * Copyright 2016 Realtek Semiconductor Corp.
5 * Author: Jack Yu <jack.yu@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/init.h>
14#include <linux/delay.h>
15#include <linux/pm.h>
16#include <linux/i2c.h>
17#include <linux/platform_device.h>
18#include <linux/spi/spi.h>
19#include <linux/acpi.h>
20#include <linux/workqueue.h>
21#include <sound/core.h>
22#include <sound/pcm.h>
23#include <sound/pcm_params.h>
24#include <sound/jack.h>
25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h>
28#include <sound/tlv.h>
29
30#include "rt5663.h"
31#include "rl6231.h"
32
73444723
BL		 33#define RT5663_DEVICE_ID_2 0x6451
34#define RT5663_DEVICE_ID_1 0x6406
df7c5216
BL		 35
36enum {
73444723
BL		 37 CODEC_VER_1,
38 CODEC_VER_0,
df7c5216
BL		 39};
40
41struct rt5663_priv {
42 struct snd_soc_codec *codec;
43 struct regmap *regmap;
44 struct delayed_work jack_detect_work;
45 struct snd_soc_jack *hs_jack;
46 struct timer_list btn_check_timer;
47
73444723 48 int codec_ver;
df7c5216
BL		 49 int sysclk;
50 int sysclk_src;
51 int lrck;
52
53 int pll_src;
54 int pll_in;
55 int pll_out;
56
57 int jack_type;
58};
59
73444723 60static const struct reg_default rt5663_v2_reg[] = {
df7c5216
BL		 61 { 0x0000, 0x0000 },
62 { 0x0001, 0xc8c8 },
63 { 0x0002, 0x8080 },
64 { 0x0003, 0x8000 },
65 { 0x0004, 0xc80a },
66 { 0x0005, 0x0000 },
67 { 0x0006, 0x0000 },
68 { 0x0007, 0x0000 },
69 { 0x000a, 0x0000 },
70 { 0x000b, 0x0000 },
71 { 0x000c, 0x0000 },
72 { 0x000d, 0x0000 },
73 { 0x000f, 0x0808 },
74 { 0x0010, 0x4000 },
75 { 0x0011, 0x0000 },
76 { 0x0012, 0x1404 },
77 { 0x0013, 0x1000 },
78 { 0x0014, 0xa00a },
79 { 0x0015, 0x0404 },
80 { 0x0016, 0x0404 },
81 { 0x0017, 0x0011 },
82 { 0x0018, 0xafaf },
83 { 0x0019, 0xafaf },
84 { 0x001a, 0xafaf },
85 { 0x001b, 0x0011 },
86 { 0x001c, 0x2f2f },
87 { 0x001d, 0x2f2f },
88 { 0x001e, 0x2f2f },
89 { 0x001f, 0x0000 },
90 { 0x0020, 0x0000 },
91 { 0x0021, 0x0000 },
92 { 0x0022, 0x5757 },
93 { 0x0023, 0x0039 },
94 { 0x0024, 0x000b },
95 { 0x0026, 0xc0c0 },
96 { 0x0027, 0xc0c0 },
97 { 0x0028, 0xc0c0 },
98 { 0x0029, 0x8080 },
99 { 0x002a, 0xaaaa },
100 { 0x002b, 0xaaaa },
101 { 0x002c, 0xaba8 },
102 { 0x002d, 0x0000 },
103 { 0x002e, 0x0000 },
104 { 0x002f, 0x0000 },
105 { 0x0030, 0x0000 },
106 { 0x0031, 0x5000 },
107 { 0x0032, 0x0000 },
108 { 0x0033, 0x0000 },
109 { 0x0034, 0x0000 },
110 { 0x0035, 0x0000 },
111 { 0x003a, 0x0000 },
112 { 0x003b, 0x0000 },
113 { 0x003c, 0x00ff },
114 { 0x003d, 0x0000 },
115 { 0x003e, 0x00ff },
116 { 0x003f, 0x0000 },
117 { 0x0040, 0x0000 },
118 { 0x0041, 0x00ff },
119 { 0x0042, 0x0000 },
120 { 0x0043, 0x00ff },
121 { 0x0044, 0x0c0c },
122 { 0x0049, 0xc00b },
123 { 0x004a, 0x0000 },
124 { 0x004b, 0x031f },
125 { 0x004d, 0x0000 },
126 { 0x004e, 0x001f },
127 { 0x004f, 0x0000 },
128 { 0x0050, 0x001f },
129 { 0x0052, 0xf000 },
130 { 0x0061, 0x0000 },
131 { 0x0062, 0x0000 },
132 { 0x0063, 0x003e },
133 { 0x0064, 0x0000 },
134 { 0x0065, 0x0000 },
135 { 0x0066, 0x003f },
136 { 0x0067, 0x0000 },
137 { 0x006b, 0x0000 },
138 { 0x006d, 0xff00 },
139 { 0x006e, 0x2808 },
140 { 0x006f, 0x000a },
141 { 0x0070, 0x8000 },
142 { 0x0071, 0x8000 },
143 { 0x0072, 0x8000 },
144 { 0x0073, 0x7000 },
145 { 0x0074, 0x7770 },
146 { 0x0075, 0x0002 },
147 { 0x0076, 0x0001 },
148 { 0x0078, 0x00f0 },
149 { 0x0079, 0x0000 },
150 { 0x007a, 0x0000 },
151 { 0x007b, 0x0000 },
152 { 0x007c, 0x0000 },
153 { 0x007d, 0x0123 },
154 { 0x007e, 0x4500 },
155 { 0x007f, 0x8003 },
156 { 0x0080, 0x0000 },
157 { 0x0081, 0x0000 },
158 { 0x0082, 0x0000 },
159 { 0x0083, 0x0000 },
160 { 0x0084, 0x0000 },
161 { 0x0085, 0x0000 },
162 { 0x0086, 0x0008 },
163 { 0x0087, 0x0000 },
164 { 0x0088, 0x0000 },
165 { 0x0089, 0x0000 },
166 { 0x008a, 0x0000 },
167 { 0x008b, 0x0000 },
168 { 0x008c, 0x0003 },
169 { 0x008e, 0x0060 },
170 { 0x008f, 0x1000 },
171 { 0x0091, 0x0c26 },
172 { 0x0092, 0x0073 },
173 { 0x0093, 0x0000 },
174 { 0x0094, 0x0080 },
175 { 0x0098, 0x0000 },
176 { 0x0099, 0x0000 },
177 { 0x009a, 0x0007 },
178 { 0x009f, 0x0000 },
179 { 0x00a0, 0x0000 },
180 { 0x00a1, 0x0002 },
181 { 0x00a2, 0x0001 },
182 { 0x00a3, 0x0002 },
183 { 0x00a4, 0x0001 },
184 { 0x00ae, 0x2040 },
185 { 0x00af, 0x0000 },
186 { 0x00b6, 0x0000 },
187 { 0x00b7, 0x0000 },
188 { 0x00b8, 0x0000 },
189 { 0x00b9, 0x0000 },
190 { 0x00ba, 0x0002 },
191 { 0x00bb, 0x0000 },
192 { 0x00be, 0x0000 },
193 { 0x00c0, 0x0000 },
194 { 0x00c1, 0x0aaa },
195 { 0x00c2, 0xaa80 },
196 { 0x00c3, 0x0003 },
197 { 0x00c4, 0x0000 },
198 { 0x00d0, 0x0000 },
199 { 0x00d1, 0x2244 },
200 { 0x00d2, 0x0000 },
201 { 0x00d3, 0x3300 },
202 { 0x00d4, 0x2200 },
203 { 0x00d9, 0x0809 },
204 { 0x00da, 0x0000 },
205 { 0x00db, 0x0008 },
206 { 0x00dc, 0x00c0 },
207 { 0x00dd, 0x6724 },
208 { 0x00de, 0x3131 },
209 { 0x00df, 0x0008 },
210 { 0x00e0, 0x4000 },
211 { 0x00e1, 0x3131 },
212 { 0x00e2, 0x600c },
213 { 0x00ea, 0xb320 },
214 { 0x00eb, 0x0000 },
215 { 0x00ec, 0xb300 },
216 { 0x00ed, 0x0000 },
217 { 0x00ee, 0xb320 },
218 { 0x00ef, 0x0000 },
219 { 0x00f0, 0x0201 },
220 { 0x00f1, 0x0ddd },
221 { 0x00f2, 0x0ddd },
222 { 0x00f6, 0x0000 },
223 { 0x00f7, 0x0000 },
224 { 0x00f8, 0x0000 },
225 { 0x00fa, 0x0000 },
226 { 0x00fb, 0x0000 },
227 { 0x00fc, 0x0000 },
228 { 0x00fd, 0x0000 },
229 { 0x00fe, 0x10ec },
230 { 0x00ff, 0x6451 },
231 { 0x0100, 0xaaaa },
232 { 0x0101, 0x000a },
233 { 0x010a, 0xaaaa },
234 { 0x010b, 0xa0a0 },
235 { 0x010c, 0xaeae },
236 { 0x010d, 0xaaaa },
237 { 0x010e, 0xaaaa },
238 { 0x010f, 0xaaaa },
239 { 0x0110, 0xe002 },
240 { 0x0111, 0xa602 },
241 { 0x0112, 0xaaaa },
242 { 0x0113, 0x2000 },
243 { 0x0117, 0x0f00 },
244 { 0x0125, 0x0420 },
245 { 0x0132, 0x0000 },
246 { 0x0133, 0x0000 },
247 { 0x0136, 0x5555 },
248 { 0x0137, 0x5540 },
249 { 0x0138, 0x3700 },
250 { 0x0139, 0x79a1 },
251 { 0x013a, 0x2020 },
252 { 0x013b, 0x2020 },
253 { 0x013c, 0x2005 },
254 { 0x013f, 0x0000 },
255 { 0x0145, 0x0002 },
256 { 0x0146, 0x0000 },
257 { 0x0147, 0x0000 },
258 { 0x0148, 0x0000 },
259 { 0x0160, 0x4ec0 },
260 { 0x0161, 0x0080 },
261 { 0x0162, 0x0200 },
262 { 0x0163, 0x0800 },
263 { 0x0164, 0x0000 },
264 { 0x0165, 0x0000 },
265 { 0x0166, 0x0000 },
266 { 0x0167, 0x000f },
267 { 0x0168, 0x000f },
268 { 0x0170, 0x4e80 },
269 { 0x0171, 0x0080 },
270 { 0x0172, 0x0200 },
271 { 0x0173, 0x0800 },
272 { 0x0174, 0x00ff },
273 { 0x0175, 0x0000 },
274 { 0x0190, 0x4131 },
275 { 0x0191, 0x4131 },
276 { 0x0192, 0x4131 },
277 { 0x0193, 0x4131 },
278 { 0x0194, 0x0000 },
279 { 0x0195, 0x0000 },
280 { 0x0196, 0x0000 },
281 { 0x0197, 0x0000 },
282 { 0x0198, 0x0000 },
283 { 0x0199, 0x0000 },
284 { 0x01a0, 0x1e64 },
285 { 0x01a1, 0x06a3 },
286 { 0x01a2, 0x0000 },
287 { 0x01a3, 0x0000 },
288 { 0x01a4, 0x0000 },
289 { 0x01a5, 0x0000 },
290 { 0x01a6, 0x0000 },
291 { 0x01a7, 0x0000 },
292 { 0x01a8, 0x0000 },
293 { 0x01a9, 0x0000 },
294 { 0x01aa, 0x0000 },
295 { 0x01ab, 0x0000 },
296 { 0x01b5, 0x0000 },
297 { 0x01b6, 0x01c3 },
298 { 0x01b7, 0x02a0 },
299 { 0x01b8, 0x03e9 },
300 { 0x01b9, 0x1389 },
301 { 0x01ba, 0xc351 },
302 { 0x01bb, 0x0009 },
303 { 0x01bc, 0x0018 },
304 { 0x01bd, 0x002a },
305 { 0x01be, 0x004c },
306 { 0x01bf, 0x0097 },
307 { 0x01c0, 0x433d },
308 { 0x01c1, 0x0000 },
309 { 0x01c2, 0x0000 },
310 { 0x01c3, 0x0000 },
311 { 0x01c4, 0x0000 },
312 { 0x01c5, 0x0000 },
313 { 0x01c6, 0x0000 },
314 { 0x01c7, 0x0000 },
315 { 0x01c8, 0x40af },
316 { 0x01c9, 0x0702 },
317 { 0x01ca, 0x0000 },
318 { 0x01cb, 0x0000 },
319 { 0x01cc, 0x5757 },
320 { 0x01cd, 0x5757 },
321 { 0x01ce, 0x5757 },
322 { 0x01cf, 0x5757 },
323 { 0x01d0, 0x5757 },
324 { 0x01d1, 0x5757 },
325 { 0x01d2, 0x5757 },
326 { 0x01d3, 0x5757 },
327 { 0x01d4, 0x5757 },
328 { 0x01d5, 0x5757 },
329 { 0x01d6, 0x003c },
330 { 0x01da, 0x0000 },
331 { 0x01db, 0x0000 },
332 { 0x01dc, 0x0000 },
333 { 0x01de, 0x7c00 },
334 { 0x01df, 0x0320 },
335 { 0x01e0, 0x06a1 },
336 { 0x01e1, 0x0000 },
337 { 0x01e2, 0x0000 },
338 { 0x01e3, 0x0000 },
339 { 0x01e4, 0x0000 },
340 { 0x01e5, 0x0000 },
341 { 0x01e6, 0x0001 },
342 { 0x01e7, 0x0000 },
343 { 0x01e8, 0x0000 },
344 { 0x01ea, 0x0000 },
345 { 0x01eb, 0x0000 },
346 { 0x01ec, 0x0000 },
347 { 0x01ed, 0x0000 },
348 { 0x01ee, 0x0000 },
349 { 0x01ef, 0x0000 },
350 { 0x01f0, 0x0000 },
351 { 0x01f1, 0x0000 },
352 { 0x01f2, 0x0000 },
353 { 0x01f3, 0x0000 },
354 { 0x01f4, 0x0000 },
355 { 0x0200, 0x0000 },
356 { 0x0201, 0x0000 },
357 { 0x0202, 0x0000 },
358 { 0x0203, 0x0000 },
359 { 0x0204, 0x0000 },
360 { 0x0205, 0x0000 },
361 { 0x0206, 0x0000 },
362 { 0x0207, 0x0000 },
363 { 0x0208, 0x0000 },
364 { 0x0210, 0x60b1 },
365 { 0x0211, 0xa000 },
366 { 0x0212, 0x024c },
367 { 0x0213, 0xf7ff },
368 { 0x0214, 0x024c },
369 { 0x0215, 0x0102 },
370 { 0x0216, 0x00a3 },
371 { 0x0217, 0x0048 },
372 { 0x0218, 0x92c0 },
373 { 0x0219, 0x0000 },
374 { 0x021a, 0x00c8 },
375 { 0x021b, 0x0020 },
376 { 0x02fa, 0x0000 },
377 { 0x02fb, 0x0000 },
378 { 0x02fc, 0x0000 },
379 { 0x02ff, 0x0110 },
380 { 0x0300, 0x001f },
381 { 0x0301, 0x032c },
382 { 0x0302, 0x5f21 },
383 { 0x0303, 0x4000 },
384 { 0x0304, 0x4000 },
385 { 0x0305, 0x06d5 },
386 { 0x0306, 0x8000 },
387 { 0x0307, 0x0700 },
388 { 0x0310, 0x4560 },
389 { 0x0311, 0xa4a8 },
390 { 0x0312, 0x7418 },
391 { 0x0313, 0x0000 },
392 { 0x0314, 0x0006 },
393 { 0x0315, 0xffff },
394 { 0x0316, 0xc400 },
395 { 0x0317, 0x0000 },
396 { 0x0330, 0x00a6 },
397 { 0x0331, 0x04c3 },
398 { 0x0332, 0x27c8 },
399 { 0x0333, 0xbf50 },
400 { 0x0334, 0x0045 },
401 { 0x0335, 0x0007 },
402 { 0x0336, 0x7418 },
403 { 0x0337, 0x0501 },
404 { 0x0338, 0x0000 },
405 { 0x0339, 0x0010 },
406 { 0x033a, 0x1010 },
407 { 0x03c0, 0x7e00 },
408 { 0x03c1, 0x8000 },
409 { 0x03c2, 0x8000 },
410 { 0x03c3, 0x8000 },
411 { 0x03c4, 0x8000 },
412 { 0x03c5, 0x8000 },
413 { 0x03c6, 0x8000 },
414 { 0x03c7, 0x8000 },
415 { 0x03c8, 0x8000 },
416 { 0x03c9, 0x8000 },
417 { 0x03ca, 0x8000 },
418 { 0x03cb, 0x8000 },
419 { 0x03cc, 0x8000 },
420 { 0x03d0, 0x0000 },
421 { 0x03d1, 0x0000 },
422 { 0x03d2, 0x0000 },
423 { 0x03d3, 0x0000 },
424 { 0x03d4, 0x2000 },
425 { 0x03d5, 0x2000 },
426 { 0x03d6, 0x0000 },
427 { 0x03d7, 0x0000 },
428 { 0x03d8, 0x2000 },
429 { 0x03d9, 0x2000 },
430 { 0x03da, 0x2000 },
431 { 0x03db, 0x2000 },
432 { 0x03dc, 0x0000 },
433 { 0x03dd, 0x0000 },
434 { 0x03de, 0x0000 },
435 { 0x03df, 0x2000 },
436 { 0x03e0, 0x0000 },
437 { 0x03e1, 0x0000 },
438 { 0x03e2, 0x0000 },
439 { 0x03e3, 0x0000 },
440 { 0x03e4, 0x0000 },
441 { 0x03e5, 0x0000 },
442 { 0x03e6, 0x0000 },
443 { 0x03e7, 0x0000 },
444 { 0x03e8, 0x0000 },
445 { 0x03e9, 0x0000 },
446 { 0x03ea, 0x0000 },
447 { 0x03eb, 0x0000 },
448 { 0x03ec, 0x0000 },
449 { 0x03ed, 0x0000 },
450 { 0x03ee, 0x0000 },
451 { 0x03ef, 0x0000 },
452 { 0x03f0, 0x0800 },
453 { 0x03f1, 0x0800 },
454 { 0x03f2, 0x0800 },
455 { 0x03f3, 0x0800 },
456 { 0x03fe, 0x0000 },
457 { 0x03ff, 0x0000 },
458 { 0x07f0, 0x0000 },
459 { 0x07fa, 0x0000 },
460};
461
462static const struct reg_default rt5663_reg[] = {
463 { 0x0000, 0x0000 },
464 { 0x0002, 0x0008 },
465 { 0x0005, 0x1000 },
466 { 0x0006, 0x1000 },
467 { 0x000a, 0x0000 },
468 { 0x0010, 0x000f },
469 { 0x0015, 0x42c1 },
470 { 0x0016, 0x0000 },
471 { 0x0018, 0x000b },
472 { 0x0019, 0xafaf },
473 { 0x001c, 0x2f2f },
474 { 0x001f, 0x0000 },
475 { 0x0022, 0x5757 },
476 { 0x0023, 0x0039 },
477 { 0x0026, 0xc0c0 },
478 { 0x0029, 0x8080 },
479 { 0x002a, 0xa0a0 },
480 { 0x002c, 0x000c },
481 { 0x002d, 0x0000 },
482 { 0x0040, 0x0808 },
483 { 0x0061, 0x0000 },
484 { 0x0062, 0x0000 },
485 { 0x0063, 0x003e },
486 { 0x0064, 0x0000 },
487 { 0x0065, 0x0000 },
488 { 0x0066, 0x0000 },
489 { 0x006b, 0x0000 },
490 { 0x006e, 0x0000 },
491 { 0x006f, 0x0000 },
492 { 0x0070, 0x8020 },
493 { 0x0073, 0x1000 },
494 { 0x0074, 0xe400 },
495 { 0x0075, 0x0002 },
496 { 0x0076, 0x0001 },
497 { 0x0077, 0x00f0 },
498 { 0x0078, 0x0000 },
499 { 0x0079, 0x0000 },
500 { 0x007a, 0x0123 },
501 { 0x007b, 0x8003 },
502 { 0x0080, 0x0000 },
503 { 0x0081, 0x0000 },
504 { 0x0082, 0x0000 },
505 { 0x0083, 0x0000 },
506 { 0x0084, 0x0000 },
507 { 0x0086, 0x0008 },
508 { 0x0087, 0x0000 },
509 { 0x008a, 0x0000 },
510 { 0x008b, 0x0000 },
511 { 0x008c, 0x0003 },
512 { 0x008e, 0x0004 },
513 { 0x008f, 0x1000 },
514 { 0x0090, 0x0646 },
515 { 0x0091, 0x0e3e },
516 { 0x0092, 0x1071 },
517 { 0x0093, 0x0000 },
518 { 0x0094, 0x0080 },
519 { 0x0097, 0x0000 },
520 { 0x0098, 0x0000 },
521 { 0x009a, 0x0000 },
522 { 0x009f, 0x0000 },
523 { 0x00ae, 0x2000 },
524 { 0x00af, 0x0000 },
525 { 0x00b6, 0x0000 },
526 { 0x00b7, 0x0000 },
527 { 0x00b8, 0x0000 },
528 { 0x00ba, 0x0000 },
529 { 0x00bb, 0x0000 },
530 { 0x00be, 0x0000 },
531 { 0x00bf, 0x0000 },
532 { 0x00c0, 0x0000 },
533 { 0x00c1, 0x0000 },
534 { 0x00c5, 0x0000 },
535 { 0x00cb, 0xa02f },
536 { 0x00cc, 0x0000 },
537 { 0x00cd, 0x0e02 },
538 { 0x00d9, 0x08f9 },
539 { 0x00db, 0x0008 },
540 { 0x00dc, 0x00c0 },
541 { 0x00dd, 0x6724 },
542 { 0x00de, 0x3131 },
543 { 0x00df, 0x0008 },
544 { 0x00e0, 0x4000 },
545 { 0x00e1, 0x3131 },
546 { 0x00e2, 0x0043 },
547 { 0x00e4, 0x400b },
548 { 0x00e5, 0x8031 },
549 { 0x00e6, 0x3080 },
550 { 0x00e7, 0x4100 },
551 { 0x00e8, 0x1400 },
552 { 0x00e9, 0xe00a },
553 { 0x00ea, 0x0404 },
554 { 0x00eb, 0x0404 },
555 { 0x00ec, 0xb320 },
556 { 0x00ed, 0x0000 },
557 { 0x00f4, 0x0000 },
558 { 0x00f6, 0x0000 },
559 { 0x00f8, 0x0000 },
560 { 0x00fa, 0x8000 },
561 { 0x00fd, 0x0001 },
562 { 0x00fe, 0x10ec },
563 { 0x00ff, 0x6406 },
564 { 0x0100, 0xa0a0 },
565 { 0x0108, 0x4444 },
566 { 0x0109, 0x4444 },
567 { 0x010a, 0xaaaa },
568 { 0x010b, 0x00a0 },
569 { 0x010c, 0x8aaa },
570 { 0x010d, 0xaaaa },
571 { 0x010e, 0x2aaa },
572 { 0x010f, 0x002a },
573 { 0x0110, 0xa0a4 },
574 { 0x0111, 0x4602 },
575 { 0x0112, 0x0101 },
576 { 0x0113, 0x2000 },
577 { 0x0114, 0x0000 },
578 { 0x0116, 0x0000 },
579 { 0x0117, 0x0f00 },
580 { 0x0118, 0x0006 },
581 { 0x0125, 0x2224 },
582 { 0x0126, 0x5550 },
583 { 0x0127, 0x0400 },
584 { 0x0128, 0x7711 },
585 { 0x0132, 0x0004 },
586 { 0x0137, 0x5441 },
587 { 0x0139, 0x79a1 },
588 { 0x013a, 0x30c0 },
589 { 0x013b, 0x2000 },
590 { 0x013c, 0x2005 },
591 { 0x013d, 0x30c0 },
592 { 0x013e, 0x0000 },
593 { 0x0140, 0x3700 },
594 { 0x0141, 0x1f00 },
595 { 0x0144, 0x0000 },
596 { 0x0145, 0x0002 },
597 { 0x0146, 0x0000 },
598 { 0x0160, 0x0e80 },
599 { 0x0161, 0x0020 },
600 { 0x0162, 0x0080 },
601 { 0x0163, 0x0800 },
602 { 0x0164, 0x0000 },
603 { 0x0165, 0x0000 },
604 { 0x0166, 0x0000 },
605 { 0x0167, 0x1417 },
606 { 0x0168, 0x0017 },
607 { 0x0169, 0x0017 },
608 { 0x0180, 0x2000 },
609 { 0x0181, 0x0000 },
610 { 0x0182, 0x0000 },
611 { 0x0183, 0x2000 },
612 { 0x0184, 0x0000 },
613 { 0x0185, 0x0000 },
614 { 0x01b0, 0x4b30 },
615 { 0x01b1, 0x0000 },
616 { 0x01b2, 0xd870 },
617 { 0x01b3, 0x0000 },
618 { 0x01b4, 0x0030 },
619 { 0x01b5, 0x5757 },
620 { 0x01b6, 0x5757 },
621 { 0x01b7, 0x5757 },
622 { 0x01b8, 0x5757 },
623 { 0x01c0, 0x433d },
624 { 0x01c1, 0x0540 },
625 { 0x01c2, 0x0000 },
626 { 0x01c3, 0x0000 },
627 { 0x01c4, 0x0000 },
628 { 0x01c5, 0x0009 },
629 { 0x01c6, 0x0018 },
630 { 0x01c7, 0x002a },
631 { 0x01c8, 0x004c },
632 { 0x01c9, 0x0097 },
633 { 0x01ca, 0x01c3 },
634 { 0x01cb, 0x03e9 },
635 { 0x01cc, 0x1389 },
636 { 0x01cd, 0xc351 },
637 { 0x01ce, 0x0000 },
638 { 0x01cf, 0x0000 },
639 { 0x01d0, 0x0000 },
640 { 0x01d1, 0x0000 },
641 { 0x01d2, 0x0000 },
642 { 0x01d3, 0x003c },
643 { 0x01d4, 0x5757 },
644 { 0x01d5, 0x5757 },
645 { 0x01d6, 0x5757 },
646 { 0x01d7, 0x5757 },
647 { 0x01d8, 0x5757 },
648 { 0x01d9, 0x5757 },
649 { 0x01da, 0x0000 },
650 { 0x01db, 0x0000 },
651 { 0x01dd, 0x0009 },
652 { 0x01de, 0x7f00 },
653 { 0x01df, 0x00c8 },
654 { 0x01e0, 0x0691 },
655 { 0x01e1, 0x0000 },
656 { 0x01e2, 0x0000 },
657 { 0x01e3, 0x0000 },
658 { 0x01e4, 0x0000 },
659 { 0x01e5, 0x0040 },
660 { 0x01e6, 0x0000 },
661 { 0x01e7, 0x0000 },
662 { 0x01e8, 0x0000 },
663 { 0x01ea, 0x0000 },
664 { 0x01eb, 0x0000 },
665 { 0x01ec, 0x0000 },
666 { 0x01ed, 0x0000 },
667 { 0x01ee, 0x0000 },
668 { 0x01ef, 0x0000 },
669 { 0x01f0, 0x0000 },
670 { 0x01f1, 0x0000 },
671 { 0x01f2, 0x0000 },
672 { 0x0200, 0x0000 },
673 { 0x0201, 0x2244 },
674 { 0x0202, 0xaaaa },
675 { 0x0250, 0x8010 },
676 { 0x0251, 0x0000 },
677 { 0x0252, 0x028a },
678 { 0x02fa, 0x0000 },
679 { 0x02fb, 0x0000 },
680 { 0x02fc, 0x0000 },
681 { 0x0300, 0x0000 },
682 { 0x03d0, 0x0000 },
683 { 0x03d1, 0x0000 },
684 { 0x03d2, 0x0000 },
685 { 0x03d3, 0x0000 },
686 { 0x03d4, 0x2000 },
687 { 0x03d5, 0x2000 },
688 { 0x03d6, 0x0000 },
689 { 0x03d7, 0x0000 },
690 { 0x03d8, 0x2000 },
691 { 0x03d9, 0x2000 },
692 { 0x03da, 0x2000 },
693 { 0x03db, 0x2000 },
694 { 0x03dc, 0x0000 },
695 { 0x03dd, 0x0000 },
696 { 0x03de, 0x0000 },
697 { 0x03df, 0x2000 },
698 { 0x03e0, 0x0000 },
699 { 0x03e1, 0x0000 },
700 { 0x03e2, 0x0000 },
701 { 0x03e3, 0x0000 },
702 { 0x03e4, 0x0000 },
703 { 0x03e5, 0x0000 },
704 { 0x03e6, 0x0000 },
705 { 0x03e7, 0x0000 },
706 { 0x03e8, 0x0000 },
707 { 0x03e9, 0x0000 },
708 { 0x03ea, 0x0000 },
709 { 0x03eb, 0x0000 },
710 { 0x03ec, 0x0000 },
711 { 0x03ed, 0x0000 },
712 { 0x03ee, 0x0000 },
713 { 0x03ef, 0x0000 },
714 { 0x03f0, 0x0800 },
715 { 0x03f1, 0x0800 },
716 { 0x03f2, 0x0800 },
717 { 0x03f3, 0x0800 },
718};
719
720static bool rt5663_volatile_register(struct device *dev, unsigned int reg)
721{
722 switch (reg) {
723 case RT5663_RESET:
724 case RT5663_SIL_DET_CTL:
725 case RT5663_HP_IMP_GAIN_2:
726 case RT5663_AD_DA_MIXER:
727 case RT5663_FRAC_DIV_2:
728 case RT5663_MICBIAS_1:
729 case RT5663_ASRC_11_2:
730 case RT5663_ADC_EQ_1:
731 case RT5663_INT_ST_1:
732 case RT5663_INT_ST_2:
73444723 733 case RT5663_GPIO_STA1:
df7c5216
BL		 734 case RT5663_SIN_GEN_1:
735 case RT5663_IL_CMD_1:
736 case RT5663_IL_CMD_5:
737 case RT5663_IL_CMD_PWRSAV1:
738 case RT5663_EM_JACK_TYPE_1:
739 case RT5663_EM_JACK_TYPE_2:
740 case RT5663_EM_JACK_TYPE_3:
741 case RT5663_JD_CTRL2:
742 case RT5663_VENDOR_ID:
743 case RT5663_VENDOR_ID_1:
744 case RT5663_VENDOR_ID_2:
745 case RT5663_PLL_INT_REG:
746 case RT5663_SOFT_RAMP:
747 case RT5663_STO_DRE_1:
748 case RT5663_STO_DRE_5:
749 case RT5663_STO_DRE_6:
750 case RT5663_STO_DRE_7:
751 case RT5663_MIC_DECRO_1:
752 case RT5663_MIC_DECRO_4:
753 case RT5663_HP_IMP_SEN_1:
754 case RT5663_HP_IMP_SEN_3:
755 case RT5663_HP_IMP_SEN_4:
756 case RT5663_HP_IMP_SEN_5:
757 case RT5663_HP_CALIB_1_1:
758 case RT5663_HP_CALIB_9:
759 case RT5663_HP_CALIB_ST1:
760 case RT5663_HP_CALIB_ST2:
761 case RT5663_HP_CALIB_ST3:
762 case RT5663_HP_CALIB_ST4:
763 case RT5663_HP_CALIB_ST5:
764 case RT5663_HP_CALIB_ST6:
765 case RT5663_HP_CALIB_ST7:
766 case RT5663_HP_CALIB_ST8:
767 case RT5663_HP_CALIB_ST9:
768 case RT5663_ANA_JD:
769 return true;
770 default:
771 return false;
772 }
773}
774
775static bool rt5663_readable_register(struct device *dev, unsigned int reg)
776{
777 switch (reg) {
778 case RT5663_RESET:
779 case RT5663_HP_OUT_EN:
780 case RT5663_HP_LCH_DRE:
781 case RT5663_HP_RCH_DRE:
782 case RT5663_CALIB_BST:
783 case RT5663_RECMIX:
784 case RT5663_SIL_DET_CTL:
785 case RT5663_PWR_SAV_SILDET:
786 case RT5663_SIDETONE_CTL:
787 case RT5663_STO1_DAC_DIG_VOL:
788 case RT5663_STO1_ADC_DIG_VOL:
789 case RT5663_STO1_BOOST:
790 case RT5663_HP_IMP_GAIN_1:
791 case RT5663_HP_IMP_GAIN_2:
792 case RT5663_STO1_ADC_MIXER:
793 case RT5663_AD_DA_MIXER:
794 case RT5663_STO_DAC_MIXER:
795 case RT5663_DIG_SIDE_MIXER:
796 case RT5663_BYPASS_STO_DAC:
797 case RT5663_CALIB_REC_MIX:
798 case RT5663_PWR_DIG_1:
799 case RT5663_PWR_DIG_2:
800 case RT5663_PWR_ANLG_1:
801 case RT5663_PWR_ANLG_2:
802 case RT5663_PWR_ANLG_3:
803 case RT5663_PWR_MIXER:
804 case RT5663_SIG_CLK_DET:
805 case RT5663_PRE_DIV_GATING_1:
806 case RT5663_PRE_DIV_GATING_2:
807 case RT5663_I2S1_SDP:
808 case RT5663_ADDA_CLK_1:
809 case RT5663_ADDA_RST:
810 case RT5663_FRAC_DIV_1:
811 case RT5663_FRAC_DIV_2:
812 case RT5663_TDM_1:
813 case RT5663_TDM_2:
814 case RT5663_TDM_3:
815 case RT5663_TDM_4:
816 case RT5663_TDM_5:
817 case RT5663_GLB_CLK:
818 case RT5663_PLL_1:
819 case RT5663_PLL_2:
820 case RT5663_ASRC_1:
821 case RT5663_ASRC_2:
822 case RT5663_ASRC_4:
823 case RT5663_DUMMY_REG:
824 case RT5663_ASRC_8:
825 case RT5663_ASRC_9:
826 case RT5663_ASRC_11:
827 case RT5663_DEPOP_1:
828 case RT5663_DEPOP_2:
829 case RT5663_DEPOP_3:
830 case RT5663_HP_CHARGE_PUMP_1:
831 case RT5663_HP_CHARGE_PUMP_2:
832 case RT5663_MICBIAS_1:
833 case RT5663_RC_CLK:
834 case RT5663_ASRC_11_2:
835 case RT5663_DUMMY_REG_2:
836 case RT5663_REC_PATH_GAIN:
837 case RT5663_AUTO_1MRC_CLK:
838 case RT5663_ADC_EQ_1:
839 case RT5663_ADC_EQ_2:
840 case RT5663_IRQ_1:
841 case RT5663_IRQ_2:
842 case RT5663_IRQ_3:
843 case RT5663_IRQ_4:
844 case RT5663_IRQ_5:
845 case RT5663_INT_ST_1:
846 case RT5663_INT_ST_2:
847 case RT5663_GPIO_1:
848 case RT5663_GPIO_2:
73444723 849 case RT5663_GPIO_STA1:
df7c5216
BL		 850 case RT5663_SIN_GEN_1:
851 case RT5663_SIN_GEN_2:
852 case RT5663_SIN_GEN_3:
853 case RT5663_SOF_VOL_ZC1:
854 case RT5663_IL_CMD_1:
855 case RT5663_IL_CMD_2:
856 case RT5663_IL_CMD_3:
857 case RT5663_IL_CMD_4:
858 case RT5663_IL_CMD_5:
859 case RT5663_IL_CMD_6:
860 case RT5663_IL_CMD_7:
861 case RT5663_IL_CMD_8:
862 case RT5663_IL_CMD_PWRSAV1:
863 case RT5663_IL_CMD_PWRSAV2:
864 case RT5663_EM_JACK_TYPE_1:
865 case RT5663_EM_JACK_TYPE_2:
866 case RT5663_EM_JACK_TYPE_3:
867 case RT5663_EM_JACK_TYPE_4:
868 case RT5663_EM_JACK_TYPE_5:
869 case RT5663_EM_JACK_TYPE_6:
870 case RT5663_STO1_HPF_ADJ1:
871 case RT5663_STO1_HPF_ADJ2:
872 case RT5663_FAST_OFF_MICBIAS:
873 case RT5663_JD_CTRL1:
874 case RT5663_JD_CTRL2:
875 case RT5663_DIG_MISC:
876 case RT5663_VENDOR_ID:
877 case RT5663_VENDOR_ID_1:
878 case RT5663_VENDOR_ID_2:
879 case RT5663_DIG_VOL_ZCD:
880 case RT5663_ANA_BIAS_CUR_1:
881 case RT5663_ANA_BIAS_CUR_2:
882 case RT5663_ANA_BIAS_CUR_3:
883 case RT5663_ANA_BIAS_CUR_4:
884 case RT5663_ANA_BIAS_CUR_5:
885 case RT5663_ANA_BIAS_CUR_6:
886 case RT5663_BIAS_CUR_5:
887 case RT5663_BIAS_CUR_6:
888 case RT5663_BIAS_CUR_7:
889 case RT5663_BIAS_CUR_8:
890 case RT5663_DACREF_LDO:
891 case RT5663_DUMMY_REG_3:
892 case RT5663_BIAS_CUR_9:
893 case RT5663_DUMMY_REG_4:
894 case RT5663_VREFADJ_OP:
895 case RT5663_VREF_RECMIX:
896 case RT5663_CHARGE_PUMP_1:
897 case RT5663_CHARGE_PUMP_1_2:
898 case RT5663_CHARGE_PUMP_1_3:
899 case RT5663_CHARGE_PUMP_2:
900 case RT5663_DIG_IN_PIN1:
901 case RT5663_PAD_DRV_CTL:
902 case RT5663_PLL_INT_REG:
903 case RT5663_CHOP_DAC_L:
904 case RT5663_CHOP_ADC:
905 case RT5663_CALIB_ADC:
906 case RT5663_CHOP_DAC_R:
907 case RT5663_DUMMY_CTL_DACLR:
908 case RT5663_DUMMY_REG_5:
909 case RT5663_SOFT_RAMP:
910 case RT5663_TEST_MODE_1:
911 case RT5663_TEST_MODE_2:
912 case RT5663_TEST_MODE_3:
913 case RT5663_STO_DRE_1:
914 case RT5663_STO_DRE_2:
915 case RT5663_STO_DRE_3:
916 case RT5663_STO_DRE_4:
917 case RT5663_STO_DRE_5:
918 case RT5663_STO_DRE_6:
919 case RT5663_STO_DRE_7:
920 case RT5663_STO_DRE_8:
921 case RT5663_STO_DRE_9:
922 case RT5663_STO_DRE_10:
923 case RT5663_MIC_DECRO_1:
924 case RT5663_MIC_DECRO_2:
925 case RT5663_MIC_DECRO_3:
926 case RT5663_MIC_DECRO_4:
927 case RT5663_MIC_DECRO_5:
928 case RT5663_MIC_DECRO_6:
929 case RT5663_HP_DECRO_1:
930 case RT5663_HP_DECRO_2:
931 case RT5663_HP_DECRO_3:
932 case RT5663_HP_DECRO_4:
933 case RT5663_HP_DECOUP:
934 case RT5663_HP_IMP_SEN_MAP8:
935 case RT5663_HP_IMP_SEN_MAP9:
936 case RT5663_HP_IMP_SEN_MAP10:
937 case RT5663_HP_IMP_SEN_MAP11:
938 case RT5663_HP_IMP_SEN_1:
939 case RT5663_HP_IMP_SEN_2:
940 case RT5663_HP_IMP_SEN_3:
941 case RT5663_HP_IMP_SEN_4:
942 case RT5663_HP_IMP_SEN_5:
943 case RT5663_HP_IMP_SEN_6:
944 case RT5663_HP_IMP_SEN_7:
945 case RT5663_HP_IMP_SEN_8:
946 case RT5663_HP_IMP_SEN_9:
947 case RT5663_HP_IMP_SEN_10:
948 case RT5663_HP_IMP_SEN_11:
949 case RT5663_HP_IMP_SEN_12:
950 case RT5663_HP_IMP_SEN_13:
951 case RT5663_HP_IMP_SEN_14:
952 case RT5663_HP_IMP_SEN_15:
953 case RT5663_HP_IMP_SEN_16:
954 case RT5663_HP_IMP_SEN_17:
955 case RT5663_HP_IMP_SEN_18:
956 case RT5663_HP_IMP_SEN_19:
957 case RT5663_HP_IMPSEN_DIG5:
958 case RT5663_HP_IMPSEN_MAP1:
959 case RT5663_HP_IMPSEN_MAP2:
960 case RT5663_HP_IMPSEN_MAP3:
961 case RT5663_HP_IMPSEN_MAP4:
962 case RT5663_HP_IMPSEN_MAP5:
963 case RT5663_HP_IMPSEN_MAP7:
964 case RT5663_HP_LOGIC_1:
965 case RT5663_HP_LOGIC_2:
966 case RT5663_HP_CALIB_1:
967 case RT5663_HP_CALIB_1_1:
968 case RT5663_HP_CALIB_2:
969 case RT5663_HP_CALIB_3:
970 case RT5663_HP_CALIB_4:
971 case RT5663_HP_CALIB_5:
972 case RT5663_HP_CALIB_5_1:
973 case RT5663_HP_CALIB_6:
974 case RT5663_HP_CALIB_7:
975 case RT5663_HP_CALIB_9:
976 case RT5663_HP_CALIB_10:
977 case RT5663_HP_CALIB_11:
978 case RT5663_HP_CALIB_ST1:
979 case RT5663_HP_CALIB_ST2:
980 case RT5663_HP_CALIB_ST3:
981 case RT5663_HP_CALIB_ST4:
982 case RT5663_HP_CALIB_ST5:
983 case RT5663_HP_CALIB_ST6:
984 case RT5663_HP_CALIB_ST7:
985 case RT5663_HP_CALIB_ST8:
986 case RT5663_HP_CALIB_ST9:
987 case RT5663_HP_AMP_DET:
988 case RT5663_DUMMY_REG_6:
989 case RT5663_HP_BIAS:
990 case RT5663_CBJ_1:
991 case RT5663_CBJ_2:
992 case RT5663_CBJ_3:
993 case RT5663_DUMMY_1:
994 case RT5663_DUMMY_2:
995 case RT5663_DUMMY_3:
996 case RT5663_ANA_JD:
997 case RT5663_ADC_LCH_LPF1_A1:
998 case RT5663_ADC_RCH_LPF1_A1:
999 case RT5663_ADC_LCH_LPF1_H0:
1000 case RT5663_ADC_RCH_LPF1_H0:
1001 case RT5663_ADC_LCH_BPF1_A1:
1002 case RT5663_ADC_RCH_BPF1_A1:
1003 case RT5663_ADC_LCH_BPF1_A2:
1004 case RT5663_ADC_RCH_BPF1_A2:
1005 case RT5663_ADC_LCH_BPF1_H0:
1006 case RT5663_ADC_RCH_BPF1_H0:
1007 case RT5663_ADC_LCH_BPF2_A1:
1008 case RT5663_ADC_RCH_BPF2_A1:
1009 case RT5663_ADC_LCH_BPF2_A2:
1010 case RT5663_ADC_RCH_BPF2_A2:
1011 case RT5663_ADC_LCH_BPF2_H0:
1012 case RT5663_ADC_RCH_BPF2_H0:
1013 case RT5663_ADC_LCH_BPF3_A1:
1014 case RT5663_ADC_RCH_BPF3_A1:
1015 case RT5663_ADC_LCH_BPF3_A2:
1016 case RT5663_ADC_RCH_BPF3_A2:
1017 case RT5663_ADC_LCH_BPF3_H0:
1018 case RT5663_ADC_RCH_BPF3_H0:
1019 case RT5663_ADC_LCH_BPF4_A1:
1020 case RT5663_ADC_RCH_BPF4_A1:
1021 case RT5663_ADC_LCH_BPF4_A2:
1022 case RT5663_ADC_RCH_BPF4_A2:
1023 case RT5663_ADC_LCH_BPF4_H0:
1024 case RT5663_ADC_RCH_BPF4_H0:
1025 case RT5663_ADC_LCH_HPF1_A1:
1026 case RT5663_ADC_RCH_HPF1_A1:
1027 case RT5663_ADC_LCH_HPF1_H0:
1028 case RT5663_ADC_RCH_HPF1_H0:
1029 case RT5663_ADC_EQ_PRE_VOL_L:
1030 case RT5663_ADC_EQ_PRE_VOL_R:
1031 case RT5663_ADC_EQ_POST_VOL_L:
1032 case RT5663_ADC_EQ_POST_VOL_R:
1033 return true;
1034 default:
1035 return false;
1036 }
1037}
1038
73444723 1039static bool rt5663_v2_volatile_register(struct device *dev, unsigned int reg)
df7c5216
BL		 1040{
1041 switch (reg) {
1042 case RT5663_RESET:
73444723
BL		 1043 case RT5663_CBJ_TYPE_2:
1044 case RT5663_PDM_OUT_CTL:
1045 case RT5663_PDM_I2C_DATA_CTL1:
1046 case RT5663_PDM_I2C_DATA_CTL4:
1047 case RT5663_ALC_BK_GAIN:
df7c5216
BL		 1048 case RT5663_PLL_2:
1049 case RT5663_MICBIAS_1:
1050 case RT5663_ADC_EQ_1:
1051 case RT5663_INT_ST_1:
73444723 1052 case RT5663_GPIO_STA2:
df7c5216
BL		 1053 case RT5663_IL_CMD_1:
1054 case RT5663_IL_CMD_5:
73444723 1055 case RT5663_A_JD_CTRL:
df7c5216
BL		 1056 case RT5663_JD_CTRL2:
1057 case RT5663_VENDOR_ID:
1058 case RT5663_VENDOR_ID_1:
1059 case RT5663_VENDOR_ID_2:
1060 case RT5663_STO_DRE_1:
1061 case RT5663_STO_DRE_5:
1062 case RT5663_STO_DRE_6:
1063 case RT5663_STO_DRE_7:
73444723
BL		 1064 case RT5663_MONO_DYNA_6:
1065 case RT5663_STO1_SIL_DET:
1066 case RT5663_MONOL_SIL_DET:
1067 case RT5663_MONOR_SIL_DET:
1068 case RT5663_STO2_DAC_SIL:
1069 case RT5663_MONO_AMP_CAL_ST1:
1070 case RT5663_MONO_AMP_CAL_ST2:
1071 case RT5663_MONO_AMP_CAL_ST3:
1072 case RT5663_MONO_AMP_CAL_ST4:
df7c5216
BL		 1073 case RT5663_HP_IMP_SEN_2:
1074 case RT5663_HP_IMP_SEN_3:
1075 case RT5663_HP_IMP_SEN_4:
1076 case RT5663_HP_IMP_SEN_10:
1077 case RT5663_HP_CALIB_1:
1078 case RT5663_HP_CALIB_10:
1079 case RT5663_HP_CALIB_ST1:
1080 case RT5663_HP_CALIB_ST4:
1081 case RT5663_HP_CALIB_ST5:
1082 case RT5663_HP_CALIB_ST6:
1083 case RT5663_HP_CALIB_ST7:
1084 case RT5663_HP_CALIB_ST8:
1085 case RT5663_HP_CALIB_ST9:
73444723
BL		 1086 case RT5663_HP_CALIB_ST10:
1087 case RT5663_HP_CALIB_ST11:
df7c5216
BL		 1088 return true;
1089 default:
1090 return false;
1091 }
1092}
1093
73444723 1094static bool rt5663_v2_readable_register(struct device *dev, unsigned int reg)
df7c5216
BL		 1095{
1096 switch (reg) {
73444723
BL		 1097 case RT5663_LOUT_CTRL:
1098 case RT5663_HP_AMP_2:
1099 case RT5663_MONO_OUT:
1100 case RT5663_MONO_GAIN:
1101 case RT5663_AEC_BST:
1102 case RT5663_IN1_IN2:
1103 case RT5663_IN3_IN4:
1104 case RT5663_INL1_INR1:
1105 case RT5663_CBJ_TYPE_2:
1106 case RT5663_CBJ_TYPE_3:
1107 case RT5663_CBJ_TYPE_4:
1108 case RT5663_CBJ_TYPE_5:
1109 case RT5663_CBJ_TYPE_8:
1110 case RT5663_DAC3_DIG_VOL:
1111 case RT5663_DAC3_CTRL:
1112 case RT5663_MONO_ADC_DIG_VOL:
1113 case RT5663_STO2_ADC_DIG_VOL:
1114 case RT5663_MONO_ADC_BST_GAIN:
1115 case RT5663_STO2_ADC_BST_GAIN:
1116 case RT5663_SIDETONE_CTRL:
1117 case RT5663_MONO1_ADC_MIXER:
1118 case RT5663_STO2_ADC_MIXER:
1119 case RT5663_MONO_DAC_MIXER:
1120 case RT5663_DAC2_SRC_CTRL:
1121 case RT5663_IF_3_4_DATA_CTL:
1122 case RT5663_IF_5_DATA_CTL:
1123 case RT5663_PDM_OUT_CTL:
1124 case RT5663_PDM_I2C_DATA_CTL1:
1125 case RT5663_PDM_I2C_DATA_CTL2:
1126 case RT5663_PDM_I2C_DATA_CTL3:
1127 case RT5663_PDM_I2C_DATA_CTL4:
1128 case RT5663_RECMIX1_NEW:
1129 case RT5663_RECMIX1L_0:
1130 case RT5663_RECMIX1L:
1131 case RT5663_RECMIX1R_0:
1132 case RT5663_RECMIX1R:
1133 case RT5663_RECMIX2_NEW:
1134 case RT5663_RECMIX2_L_2:
1135 case RT5663_RECMIX2_R:
1136 case RT5663_RECMIX2_R_2:
1137 case RT5663_CALIB_REC_LR:
1138 case RT5663_ALC_BK_GAIN:
1139 case RT5663_MONOMIX_GAIN:
1140 case RT5663_MONOMIX_IN_GAIN:
1141 case RT5663_OUT_MIXL_GAIN:
1142 case RT5663_OUT_LMIX_IN_GAIN:
1143 case RT5663_OUT_RMIX_IN_GAIN:
1144 case RT5663_OUT_RMIX_IN_GAIN1:
1145 case RT5663_LOUT_MIXER_CTRL:
1146 case RT5663_PWR_VOL:
1147 case RT5663_ADCDAC_RST:
1148 case RT5663_I2S34_SDP:
1149 case RT5663_I2S5_SDP:
1150 case RT5663_TDM_6:
1151 case RT5663_TDM_7:
1152 case RT5663_TDM_8:
1153 case RT5663_TDM_9:
1154 case RT5663_ASRC_3:
1155 case RT5663_ASRC_6:
1156 case RT5663_ASRC_7:
1157 case RT5663_PLL_TRK_13:
1158 case RT5663_I2S_M_CLK_CTL:
1159 case RT5663_FDIV_I2S34_M_CLK:
1160 case RT5663_FDIV_I2S34_M_CLK2:
1161 case RT5663_FDIV_I2S5_M_CLK:
1162 case RT5663_FDIV_I2S5_M_CLK2:
1163 case RT5663_V2_IRQ_4:
1164 case RT5663_GPIO_3:
1165 case RT5663_GPIO_4:
1166 case RT5663_GPIO_STA2:
1167 case RT5663_HP_AMP_DET1:
1168 case RT5663_HP_AMP_DET2:
1169 case RT5663_HP_AMP_DET3:
1170 case RT5663_MID_BD_HP_AMP:
1171 case RT5663_LOW_BD_HP_AMP:
1172 case RT5663_SOF_VOL_ZC2:
1173 case RT5663_ADC_STO2_ADJ1:
1174 case RT5663_ADC_STO2_ADJ2:
1175 case RT5663_A_JD_CTRL:
1176 case RT5663_JD1_TRES_CTRL:
1177 case RT5663_JD2_TRES_CTRL:
1178 case RT5663_V2_JD_CTRL2:
1179 case RT5663_DUM_REG_2:
1180 case RT5663_DUM_REG_3:
df7c5216
BL		 1181 case RT5663_VENDOR_ID:
1182 case RT5663_VENDOR_ID_1:
1183 case RT5663_VENDOR_ID_2:
73444723
BL		 1184 case RT5663_DACADC_DIG_VOL2:
1185 case RT5663_DIG_IN_PIN2:
1186 case RT5663_PAD_DRV_CTL1:
1187 case RT5663_SOF_RAM_DEPOP:
1188 case RT5663_VOL_TEST:
1189 case RT5663_TEST_MODE_4:
1190 case RT5663_TEST_MODE_5:
df7c5216 1191 case RT5663_STO_DRE_9:
73444723
BL		 1192 case RT5663_MONO_DYNA_1:
1193 case RT5663_MONO_DYNA_2:
1194 case RT5663_MONO_DYNA_3:
1195 case RT5663_MONO_DYNA_4:
1196 case RT5663_MONO_DYNA_5:
1197 case RT5663_MONO_DYNA_6:
1198 case RT5663_STO1_SIL_DET:
1199 case RT5663_MONOL_SIL_DET:
1200 case RT5663_MONOR_SIL_DET:
1201 case RT5663_STO2_DAC_SIL:
1202 case RT5663_PWR_SAV_CTL1:
1203 case RT5663_PWR_SAV_CTL2:
1204 case RT5663_PWR_SAV_CTL3:
1205 case RT5663_PWR_SAV_CTL4:
1206 case RT5663_PWR_SAV_CTL5:
1207 case RT5663_PWR_SAV_CTL6:
1208 case RT5663_MONO_AMP_CAL1:
1209 case RT5663_MONO_AMP_CAL2:
1210 case RT5663_MONO_AMP_CAL3:
1211 case RT5663_MONO_AMP_CAL4:
1212 case RT5663_MONO_AMP_CAL5:
1213 case RT5663_MONO_AMP_CAL6:
1214 case RT5663_MONO_AMP_CAL7:
1215 case RT5663_MONO_AMP_CAL_ST1:
1216 case RT5663_MONO_AMP_CAL_ST2:
1217 case RT5663_MONO_AMP_CAL_ST3:
1218 case RT5663_MONO_AMP_CAL_ST4:
1219 case RT5663_MONO_AMP_CAL_ST5:
1220 case RT5663_V2_HP_IMP_SEN_13:
1221 case RT5663_V2_HP_IMP_SEN_14:
1222 case RT5663_V2_HP_IMP_SEN_6:
1223 case RT5663_V2_HP_IMP_SEN_7:
1224 case RT5663_V2_HP_IMP_SEN_8:
1225 case RT5663_V2_HP_IMP_SEN_9:
1226 case RT5663_V2_HP_IMP_SEN_10:
1227 case RT5663_HP_LOGIC_3:
1228 case RT5663_HP_CALIB_ST10:
1229 case RT5663_HP_CALIB_ST11:
1230 case RT5663_PRO_REG_TBL_4:
1231 case RT5663_PRO_REG_TBL_5:
1232 case RT5663_PRO_REG_TBL_6:
1233 case RT5663_PRO_REG_TBL_7:
1234 case RT5663_PRO_REG_TBL_8:
1235 case RT5663_PRO_REG_TBL_9:
1236 case RT5663_SAR_ADC_INL_1:
1237 case RT5663_SAR_ADC_INL_2:
1238 case RT5663_SAR_ADC_INL_3:
1239 case RT5663_SAR_ADC_INL_4:
1240 case RT5663_SAR_ADC_INL_5:
1241 case RT5663_SAR_ADC_INL_6:
1242 case RT5663_SAR_ADC_INL_7:
1243 case RT5663_SAR_ADC_INL_8:
1244 case RT5663_SAR_ADC_INL_9:
1245 case RT5663_SAR_ADC_INL_10:
1246 case RT5663_SAR_ADC_INL_11:
1247 case RT5663_SAR_ADC_INL_12:
1248 case RT5663_DRC_CTRL_1:
1249 case RT5663_DRC1_CTRL_2:
1250 case RT5663_DRC1_CTRL_3:
1251 case RT5663_DRC1_CTRL_4:
1252 case RT5663_DRC1_CTRL_5:
1253 case RT5663_DRC1_CTRL_6:
1254 case RT5663_DRC1_HD_CTRL_1:
1255 case RT5663_DRC1_HD_CTRL_2:
1256 case RT5663_DRC1_PRI_REG_1:
1257 case RT5663_DRC1_PRI_REG_2:
1258 case RT5663_DRC1_PRI_REG_3:
1259 case RT5663_DRC1_PRI_REG_4:
1260 case RT5663_DRC1_PRI_REG_5:
1261 case RT5663_DRC1_PRI_REG_6:
1262 case RT5663_DRC1_PRI_REG_7:
1263 case RT5663_DRC1_PRI_REG_8:
1264 case RT5663_ALC_PGA_CTL_1:
1265 case RT5663_ALC_PGA_CTL_2:
1266 case RT5663_ALC_PGA_CTL_3:
1267 case RT5663_ALC_PGA_CTL_4:
1268 case RT5663_ALC_PGA_CTL_5:
1269 case RT5663_ALC_PGA_CTL_6:
1270 case RT5663_ALC_PGA_CTL_7:
1271 case RT5663_ALC_PGA_CTL_8:
1272 case RT5663_ALC_PGA_REG_1:
1273 case RT5663_ALC_PGA_REG_2:
1274 case RT5663_ALC_PGA_REG_3:
1275 case RT5663_ADC_EQ_RECOV_1:
1276 case RT5663_ADC_EQ_RECOV_2:
1277 case RT5663_ADC_EQ_RECOV_3:
1278 case RT5663_ADC_EQ_RECOV_4:
1279 case RT5663_ADC_EQ_RECOV_5:
1280 case RT5663_ADC_EQ_RECOV_6:
1281 case RT5663_ADC_EQ_RECOV_7:
1282 case RT5663_ADC_EQ_RECOV_8:
1283 case RT5663_ADC_EQ_RECOV_9:
1284 case RT5663_ADC_EQ_RECOV_10:
1285 case RT5663_ADC_EQ_RECOV_11:
1286 case RT5663_ADC_EQ_RECOV_12:
1287 case RT5663_ADC_EQ_RECOV_13:
1288 case RT5663_VID_HIDDEN:
1289 case RT5663_VID_CUSTOMER:
1290 case RT5663_SCAN_MODE:
1291 case RT5663_I2C_BYPA:
df7c5216
BL		 1292 return true;
1293 case RT5663_TDM_1:
1294 case RT5663_DEPOP_3:
1295 case RT5663_ASRC_11_2:
1296 case RT5663_INT_ST_2:
73444723 1297 case RT5663_GPIO_STA1:
df7c5216
BL		 1298 case RT5663_SIN_GEN_1:
1299 case RT5663_SIN_GEN_2:
1300 case RT5663_SIN_GEN_3:
1301 case RT5663_IL_CMD_PWRSAV1:
1302 case RT5663_IL_CMD_PWRSAV2:
1303 case RT5663_EM_JACK_TYPE_1:
1304 case RT5663_EM_JACK_TYPE_2:
1305 case RT5663_EM_JACK_TYPE_3:
1306 case RT5663_EM_JACK_TYPE_4:
1307 case RT5663_FAST_OFF_MICBIAS:
1308 case RT5663_ANA_BIAS_CUR_1:
1309 case RT5663_ANA_BIAS_CUR_2:
1310 case RT5663_BIAS_CUR_9:
1311 case RT5663_DUMMY_REG_4:
1312 case RT5663_VREF_RECMIX:
1313 case RT5663_CHARGE_PUMP_1_2:
1314 case RT5663_CHARGE_PUMP_1_3:
1315 case RT5663_CHARGE_PUMP_2:
1316 case RT5663_CHOP_DAC_R:
1317 case RT5663_DUMMY_CTL_DACLR:
1318 case RT5663_DUMMY_REG_5:
1319 case RT5663_SOFT_RAMP:
1320 case RT5663_TEST_MODE_1:
1321 case RT5663_STO_DRE_10:
1322 case RT5663_MIC_DECRO_1:
1323 case RT5663_MIC_DECRO_2:
1324 case RT5663_MIC_DECRO_3:
1325 case RT5663_MIC_DECRO_4:
1326 case RT5663_MIC_DECRO_5:
1327 case RT5663_MIC_DECRO_6:
1328 case RT5663_HP_DECRO_1:
1329 case RT5663_HP_DECRO_2:
1330 case RT5663_HP_DECRO_3:
1331 case RT5663_HP_DECRO_4:
1332 case RT5663_HP_DECOUP:
1333 case RT5663_HP_IMPSEN_MAP4:
1334 case RT5663_HP_IMPSEN_MAP5:
1335 case RT5663_HP_IMPSEN_MAP7:
1336 case RT5663_HP_CALIB_1:
1337 case RT5663_CBJ_1:
1338 case RT5663_CBJ_2:
1339 case RT5663_CBJ_3:
1340 return false;
1341 default:
1342 return rt5663_readable_register(dev, reg);
1343 }
1344}
1345
1346static const DECLARE_TLV_DB_SCALE(rt5663_hp_vol_tlv, -2400, 150, 0);
73444723 1347static const DECLARE_TLV_DB_SCALE(rt5663_v2_hp_vol_tlv, -2250, 150, 0);
df7c5216
BL		 1348static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
1349static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
1350
1351/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
1352static const DECLARE_TLV_DB_RANGE(in_bst_tlv,
1353 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
1354 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
1355 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
1356 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
1357 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
1358 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
1359 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
1360);
1361
1362/* Interface data select */
1363static const char * const rt5663_if1_adc_data_select[] = {
1364 "L/R", "R/L", "L/L", "R/R"
1365};
1366
66d7c262 1367static SOC_ENUM_SINGLE_DECL(rt5663_if1_adc_enum, RT5663_TDM_2,
df7c5216
BL		 1368 RT5663_DATA_SWAP_ADCDAT1_SHIFT, rt5663_if1_adc_data_select);
1369
1370static void rt5663_enable_push_button_irq(struct snd_soc_codec *codec,
1371 bool enable)
1372{
1373 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1374
1375 if (enable) {
1376 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
73444723 1377 RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_EN);
df7c5216
BL		 1378 /* reset in-line command */
1379 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
73444723
BL		 1380 RT5663_RESET_4BTN_INL_MASK,
1381 RT5663_RESET_4BTN_INL_RESET);
df7c5216 1382 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
73444723
BL		 1383 RT5663_RESET_4BTN_INL_MASK,
1384 RT5663_RESET_4BTN_INL_NOR);
1385 switch (rt5663->codec_ver) {
1386 case CODEC_VER_1:
df7c5216 1387 snd_soc_update_bits(codec, RT5663_IRQ_3,
73444723
BL		 1388 RT5663_V2_EN_IRQ_INLINE_MASK,
1389 RT5663_V2_EN_IRQ_INLINE_NOR);
df7c5216 1390 break;
73444723 1391 case CODEC_VER_0:
df7c5216
BL		 1392 snd_soc_update_bits(codec, RT5663_IRQ_2,
1393 RT5663_EN_IRQ_INLINE_MASK,
1394 RT5663_EN_IRQ_INLINE_NOR);
1395 break;
1396 default:
73444723 1397 dev_err(codec->dev, "Unknown CODEC Version\n");
df7c5216
BL		 1398 }
1399 } else {
73444723
BL		 1400 switch (rt5663->codec_ver) {
1401 case CODEC_VER_1:
df7c5216 1402 snd_soc_update_bits(codec, RT5663_IRQ_3,
73444723
BL		 1403 RT5663_V2_EN_IRQ_INLINE_MASK,
1404 RT5663_V2_EN_IRQ_INLINE_BYP);
df7c5216 1405 break;
73444723 1406 case CODEC_VER_0:
df7c5216
BL		 1407 snd_soc_update_bits(codec, RT5663_IRQ_2,
1408 RT5663_EN_IRQ_INLINE_MASK,
1409 RT5663_EN_IRQ_INLINE_BYP);
1410 break;
1411 default:
73444723 1412 dev_err(codec->dev, "Unknown CODEC Version\n");
df7c5216
BL		 1413 }
1414 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
73444723 1415 RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_DIS);
df7c5216
BL		 1416 /* reset in-line command */
1417 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
73444723
BL		 1418 RT5663_RESET_4BTN_INL_MASK,
1419 RT5663_RESET_4BTN_INL_RESET);
df7c5216 1420 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
73444723
BL		 1421 RT5663_RESET_4BTN_INL_MASK,
1422 RT5663_RESET_4BTN_INL_NOR);
df7c5216
BL		 1423 }
1424}
1425
1426/**
73444723 1427 * rt5663_v2_jack_detect - Detect headset.
df7c5216
BL		 1428 * @codec: SoC audio codec device.
1429 * @jack_insert: Jack insert or not.
1430 *
1431 * Detect whether is headset or not when jack inserted.
1432 *
1433 * Returns detect status.
1434 */
1435
73444723 1436static int rt5663_v2_jack_detect(struct snd_soc_codec *codec, int jack_insert)
df7c5216
BL		 1437{
1438 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
73444723 1439 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
df7c5216
BL		 1440 int val, i = 0, sleep_time[5] = {300, 150, 100, 50, 30};
1441
1442 dev_dbg(codec->dev, "%s jack_insert:%d\n", __func__, jack_insert);
1443 if (jack_insert) {
73444723
BL		 1444 snd_soc_write(codec, RT5663_CBJ_TYPE_2, 0x8040);
1445 snd_soc_write(codec, RT5663_CBJ_TYPE_3, 0x1484);
df7c5216
BL		 1446
1447 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
1448 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS2");
1449 snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power");
1450 snd_soc_dapm_force_enable_pin(dapm, "CBJ Power");
1451 snd_soc_dapm_sync(dapm);
1452 snd_soc_update_bits(codec, RT5663_RC_CLK,
73444723 1453 RT5663_DIG_1M_CLK_MASK, RT5663_DIG_1M_CLK_EN);
df7c5216
BL		 1454 snd_soc_update_bits(codec, RT5663_RECMIX, 0x8, 0x8);
1455
1456 while (i < 5) {
1457 msleep(sleep_time[i]);
73444723 1458 val = snd_soc_read(codec, RT5663_CBJ_TYPE_2) & 0x0003;
df7c5216
BL		 1459 if (val == 0x1 || val == 0x2 || val == 0x3)
1460 break;
1461 dev_dbg(codec->dev, "%s: MX-0011 val=%x sleep %d\n",
1462 __func__, val, sleep_time[i]);
1463 i++;
1464 }
1465 dev_dbg(codec->dev, "%s val = %d\n", __func__, val);
1466 switch (val) {
1467 case 1:
1468 case 2:
73444723 1469 rt5663->jack_type = SND_JACK_HEADSET;
df7c5216
BL		 1470 rt5663_enable_push_button_irq(codec, true);
1471 break;
1472 default:
1473 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1474 snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
1475 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1476 snd_soc_dapm_disable_pin(dapm, "CBJ Power");
1477 snd_soc_dapm_sync(dapm);
73444723 1478 rt5663->jack_type = SND_JACK_HEADPHONE;
df7c5216
BL		 1479 break;
1480 }
1481 } else {
1482 snd_soc_update_bits(codec, RT5663_RECMIX, 0x8, 0x0);
1483
73444723 1484 if (rt5663->jack_type == SND_JACK_HEADSET) {
df7c5216
BL		 1485 rt5663_enable_push_button_irq(codec, false);
1486 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1487 snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
1488 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1489 snd_soc_dapm_disable_pin(dapm, "CBJ Power");
1490 snd_soc_dapm_sync(dapm);
1491 }
73444723 1492 rt5663->jack_type = 0;
df7c5216
BL		 1493 }
1494
73444723
BL		 1495 dev_dbg(codec->dev, "jack_type = %d\n", rt5663->jack_type);
1496 return rt5663->jack_type;
df7c5216
BL		 1497}
1498
1499/**
1500 * rt5663_jack_detect - Detect headset.
1501 * @codec: SoC audio codec device.
1502 * @jack_insert: Jack insert or not.
1503 *
1504 * Detect whether is headset or not when jack inserted.
1505 *
1506 * Returns detect status.
1507 */
1508static int rt5663_jack_detect(struct snd_soc_codec *codec, int jack_insert)
1509{
1510 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
8f244127 1511 int val, i = 0;
df7c5216
BL		 1512
1513 dev_dbg(codec->dev, "%s jack_insert:%d\n", __func__, jack_insert);
1514
1515 if (jack_insert) {
1516 snd_soc_update_bits(codec, RT5663_DIG_MISC,
73444723 1517 RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN);
df7c5216 1518 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
73444723
BL		 1519 RT5663_SI_HP_MASK | RT5663_OSW_HP_L_MASK |
1520 RT5663_OSW_HP_R_MASK, RT5663_SI_HP_EN |
1521 RT5663_OSW_HP_L_DIS | RT5663_OSW_HP_R_DIS);
df7c5216
BL		 1522 snd_soc_update_bits(codec, RT5663_DUMMY_1,
1523 RT5663_EMB_CLK_MASK | RT5663_HPA_CPL_BIAS_MASK |
1524 RT5663_HPA_CPR_BIAS_MASK, RT5663_EMB_CLK_EN |
1525 RT5663_HPA_CPL_BIAS_1 | RT5663_HPA_CPR_BIAS_1);
1526 snd_soc_update_bits(codec, RT5663_CBJ_1,
1527 RT5663_INBUF_CBJ_BST1_MASK | RT5663_CBJ_SENSE_BST1_MASK,
1528 RT5663_INBUF_CBJ_BST1_ON | RT5663_CBJ_SENSE_BST1_L);
1529 snd_soc_update_bits(codec, RT5663_IL_CMD_2,
1530 RT5663_PWR_MIC_DET_MASK, RT5663_PWR_MIC_DET_ON);
1531 /* BST1 power on for JD */
1532 snd_soc_update_bits(codec, RT5663_PWR_ANLG_2,
73444723 1533 RT5663_PWR_BST1_MASK, RT5663_PWR_BST1_ON);
df7c5216
BL		 1534 snd_soc_update_bits(codec, RT5663_EM_JACK_TYPE_1,
1535 RT5663_CBJ_DET_MASK | RT5663_EXT_JD_MASK |
1536 RT5663_POL_EXT_JD_MASK, RT5663_CBJ_DET_EN |
1537 RT5663_EXT_JD_EN | RT5663_POL_EXT_JD_EN);
1538 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
73444723
BL		 1539 RT5663_PWR_MB_MASK | RT5663_LDO1_DVO_MASK |
1540 RT5663_AMP_HP_MASK, RT5663_PWR_MB |
1541 RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X);
df7c5216 1542 snd_soc_update_bits(codec, RT5663_AUTO_1MRC_CLK,
73444723 1543 RT5663_IRQ_POW_SAV_MASK, RT5663_IRQ_POW_SAV_EN);
df7c5216
BL		 1544 snd_soc_update_bits(codec, RT5663_IRQ_1,
1545 RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN);
8f244127 1546
1547 while (true) {
1548 regmap_read(rt5663->regmap, RT5663_INT_ST_2, &val);
1549 if (!(val & 0x80))
1550 usleep_range(10000, 10005);
1551 else
1552 break;
1553
1554 if (i > 200)
df7c5216 1555 break;
8f244127 1556 i++;
df7c5216 1557 }
8f244127 1558
1559 val = snd_soc_read(codec, RT5663_EM_JACK_TYPE_2) & 0x0003;
df7c5216 1560 dev_dbg(codec->dev, "%s val = %d\n", __func__, val);
8f244127 1561
df7c5216
BL		 1562 switch (val) {
1563 case 1:
1564 case 2:
1565 rt5663->jack_type = SND_JACK_HEADSET;
1566 rt5663_enable_push_button_irq(codec, true);
1567 break;
1568 default:
1569 rt5663->jack_type = SND_JACK_HEADPHONE;
1570 break;
1571 }
1572 } else {
1573 if (rt5663->jack_type == SND_JACK_HEADSET)
1574 rt5663_enable_push_button_irq(codec, false);
1575 rt5663->jack_type = 0;
1576 }
1577
1578 dev_dbg(codec->dev, "jack_type = %d\n", rt5663->jack_type);
1579 return rt5663->jack_type;
1580}
1581
66d7c262 1582static int rt5663_button_detect(struct snd_soc_codec *codec)
df7c5216
BL		 1583{
1584 int btn_type, val;
1585
1586 val = snd_soc_read(codec, RT5663_IL_CMD_5);
1587 dev_dbg(codec->dev, "%s: val=0x%x\n", __func__, val);
1588 btn_type = val & 0xfff0;
1589 snd_soc_write(codec, RT5663_IL_CMD_5, val);
1590
1591 return btn_type;
1592}
1593
1594static irqreturn_t rt5663_irq(int irq, void *data)
1595{
1596 struct rt5663_priv *rt5663 = data;
1597
1598 dev_dbg(rt5663->codec->dev, "%s IRQ queue work\n", __func__);
1599
1600 queue_delayed_work(system_wq, &rt5663->jack_detect_work,
1601 msecs_to_jiffies(250));
1602
1603 return IRQ_HANDLED;
1604}
1605
1606int rt5663_set_jack_detect(struct snd_soc_codec *codec,
1607 struct snd_soc_jack *hs_jack)
1608{
1609 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1610
1611 rt5663->hs_jack = hs_jack;
1612
1613 rt5663_irq(0, rt5663);
1614
1615 return 0;
1616}
1617EXPORT_SYMBOL_GPL(rt5663_set_jack_detect);
1618
1619static bool rt5663_check_jd_status(struct snd_soc_codec *codec)
1620{
1621 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1622 int val = snd_soc_read(codec, RT5663_INT_ST_1);
1623
1624 dev_dbg(codec->dev, "%s val=%x\n", __func__, val);
1625
1626 /* JD1 */
73444723
BL		 1627 switch (rt5663->codec_ver) {
1628 case CODEC_VER_1:
df7c5216 1629 return !(val & 0x2000);
73444723 1630 case CODEC_VER_0:
df7c5216
BL		 1631 return !(val & 0x1000);
1632 default:
73444723 1633 dev_err(codec->dev, "Unknown CODEC Version\n");
df7c5216
BL		 1634 }
1635
1636 return false;
1637}
1638
1639static void rt5663_jack_detect_work(struct work_struct *work)
1640{
1641 struct rt5663_priv *rt5663 =
1642 container_of(work, struct rt5663_priv, jack_detect_work.work);
1643 struct snd_soc_codec *codec = rt5663->codec;
1644 int btn_type, report = 0;
1645
1646 if (!codec)
1647 return;
1648
1649 if (rt5663_check_jd_status(codec)) {
1650 /* jack in */
1651 if (rt5663->jack_type == 0) {
1652 /* jack was out, report jack type */
73444723
BL		 1653 switch (rt5663->codec_ver) {
1654 case CODEC_VER_1:
1655 report = rt5663_v2_jack_detect(
1656 rt5663->codec, 1);
df7c5216 1657 break;
73444723 1658 case CODEC_VER_0:
df7c5216
BL		 1659 report = rt5663_jack_detect(rt5663->codec, 1);
1660 break;
1661 default:
73444723 1662 dev_err(codec->dev, "Unknown CODEC Version\n");
df7c5216
BL		 1663 }
1664 } else {
1665 /* jack is already in, report button event */
1666 report = SND_JACK_HEADSET;
1667 btn_type = rt5663_button_detect(rt5663->codec);
1668 /**
1669 * rt5663 can report three kinds of button behavior,
1670 * one click, double click and hold. However,
1671 * currently we will report button pressed/released
1672 * event. So all the three button behaviors are
1673 * treated as button pressed.
1674 */
1675 switch (btn_type) {
1676 case 0x8000:
1677 case 0x4000:
1678 case 0x2000:
1679 report |= SND_JACK_BTN_0;
1680 break;
1681 case 0x1000:
1682 case 0x0800:
1683 case 0x0400:
1684 report |= SND_JACK_BTN_1;
1685 break;
1686 case 0x0200:
1687 case 0x0100:
1688 case 0x0080:
1689 report |= SND_JACK_BTN_2;
1690 break;
1691 case 0x0040:
1692 case 0x0020:
1693 case 0x0010:
1694 report |= SND_JACK_BTN_3;
1695 break;
1696 case 0x0000: /* unpressed */
1697 break;
1698 default:
1699 btn_type = 0;
1700 dev_err(rt5663->codec->dev,
1701 "Unexpected button code 0x%04x\n",
1702 btn_type);
1703 break;
1704 }
1705 /* button release or spurious interrput*/
1706 if (btn_type == 0)
1707 report = rt5663->jack_type;
1708 }
1709 } else {
1710 /* jack out */
73444723
BL		 1711 switch (rt5663->codec_ver) {
1712 case CODEC_VER_1:
1713 report = rt5663_v2_jack_detect(rt5663->codec, 0);
df7c5216 1714 break;
73444723 1715 case CODEC_VER_0:
df7c5216
BL		 1716 report = rt5663_jack_detect(rt5663->codec, 0);
1717 break;
1718 default:
73444723 1719 dev_err(codec->dev, "Unknown CODEC Version\n");
df7c5216
BL		 1720 }
1721 }
1722 dev_dbg(codec->dev, "%s jack report: 0x%04x\n", __func__, report);
1723 snd_soc_jack_report(rt5663->hs_jack, report, SND_JACK_HEADSET |
1724 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1725 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1726}
1727
1728static const struct snd_kcontrol_new rt5663_snd_controls[] = {
1729 /* DAC Digital Volume */
1730 SOC_DOUBLE_TLV("DAC Playback Volume", RT5663_STO1_DAC_DIG_VOL,
73444723 1731 RT5663_DAC_L1_VOL_SHIFT + 1, RT5663_DAC_R1_VOL_SHIFT + 1,
df7c5216
BL		 1732 87, 0, dac_vol_tlv),
1733 /* ADC Digital Volume Control */
1734 SOC_DOUBLE("ADC Capture Switch", RT5663_STO1_ADC_DIG_VOL,
73444723 1735 RT5663_ADC_L_MUTE_SHIFT, RT5663_ADC_R_MUTE_SHIFT, 1, 1),
df7c5216 1736 SOC_DOUBLE_TLV("ADC Capture Volume", RT5663_STO1_ADC_DIG_VOL,
73444723 1737 RT5663_ADC_L_VOL_SHIFT + 1, RT5663_ADC_R_VOL_SHIFT + 1,
df7c5216
BL		 1738 63, 0, adc_vol_tlv),
1739};
1740
73444723 1741static const struct snd_kcontrol_new rt5663_v2_specific_controls[] = {
df7c5216
BL		 1742 /* Headphone Output Volume */
1743 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_HP_LCH_DRE,
73444723
BL		 1744 RT5663_HP_RCH_DRE, RT5663_GAIN_HP_SHIFT, 15, 1,
1745 rt5663_v2_hp_vol_tlv),
df7c5216 1746 /* Mic Boost Volume */
73444723
BL		 1747 SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_AEC_BST,
1748 RT5663_GAIN_CBJ_SHIFT, 8, 0, in_bst_tlv),
df7c5216
BL		 1749};
1750
1751static const struct snd_kcontrol_new rt5663_specific_controls[] = {
1752 /* Headphone Output Volume */
1753 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_STO_DRE_9,
1754 RT5663_STO_DRE_10, RT5663_DRE_GAIN_HP_SHIFT, 23, 1,
1755 rt5663_hp_vol_tlv),
1756 /* Mic Boost Volume*/
1757 SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_CBJ_2,
1758 RT5663_GAIN_BST1_SHIFT, 8, 0, in_bst_tlv),
1759 /* Data Swap for Slot0/1 in ADCDAT1 */
1760 SOC_ENUM("IF1 ADC Data Swap", rt5663_if1_adc_enum),
1761};
1762
1763static int rt5663_is_sys_clk_from_pll(struct snd_soc_dapm_widget *w,
1764 struct snd_soc_dapm_widget *sink)
1765{
1766 unsigned int val;
1767 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1768
1769 val = snd_soc_read(codec, RT5663_GLB_CLK);
1770 val &= RT5663_SCLK_SRC_MASK;
1771 if (val == RT5663_SCLK_SRC_PLL1)
1772 return 1;
1773 else
1774 return 0;
1775}
1776
1777static int rt5663_is_using_asrc(struct snd_soc_dapm_widget *w,
1778 struct snd_soc_dapm_widget *sink)
1779{
1780 unsigned int reg, shift, val;
1781 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1782 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1783
73444723 1784 if (rt5663->codec_ver == CODEC_VER_1) {
df7c5216 1785 switch (w->shift) {
73444723
BL		 1786 case RT5663_ADC_STO1_ASRC_SHIFT:
1787 reg = RT5663_ASRC_3;
1788 shift = RT5663_V2_AD_STO1_TRACK_SHIFT;
df7c5216 1789 break;
73444723 1790 case RT5663_DAC_STO1_ASRC_SHIFT:
df7c5216 1791 reg = RT5663_ASRC_2;
73444723 1792 shift = RT5663_DA_STO1_TRACK_SHIFT;
df7c5216
BL		 1793 break;
1794 default:
1795 return 0;
1796 }
1797 } else {
1798 switch (w->shift) {
1799 case RT5663_ADC_STO1_ASRC_SHIFT:
1800 reg = RT5663_ASRC_2;
1801 shift = RT5663_AD_STO1_TRACK_SHIFT;
1802 break;
1803 case RT5663_DAC_STO1_ASRC_SHIFT:
1804 reg = RT5663_ASRC_2;
1805 shift = RT5663_DA_STO1_TRACK_SHIFT;
1806 break;
1807 default:
1808 return 0;
1809 }
1810 }
1811
1812 val = (snd_soc_read(codec, reg) >> shift) & 0x7;
1813
1814 if (val)
1815 return 1;
1816
1817 return 0;
1818}
1819
1820static int rt5663_i2s_use_asrc(struct snd_soc_dapm_widget *source,
1821 struct snd_soc_dapm_widget *sink)
1822{
1823 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
1824 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1825 int da_asrc_en, ad_asrc_en;
1826
1827 da_asrc_en = (snd_soc_read(codec, RT5663_ASRC_2) &
1828 RT5663_DA_STO1_TRACK_MASK) ? 1 : 0;
73444723
BL		 1829 switch (rt5663->codec_ver) {
1830 case CODEC_VER_1:
1831 ad_asrc_en = (snd_soc_read(codec, RT5663_ASRC_3) &
1832 RT5663_V2_AD_STO1_TRACK_MASK) ? 1 : 0;
df7c5216 1833 break;
73444723 1834 case CODEC_VER_0:
df7c5216
BL		 1835 ad_asrc_en = (snd_soc_read(codec, RT5663_ASRC_2) &
1836 RT5663_AD_STO1_TRACK_MASK) ? 1 : 0;
1837 break;
1838 default:
73444723 1839 dev_err(codec->dev, "Unknown CODEC Version\n");
56efaed5 1840 return 1;
df7c5216
BL		 1841 }
1842
1843 if (da_asrc_en || ad_asrc_en)
1844 if (rt5663->sysclk > rt5663->lrck * 384)
1845 return 1;
1846
1847 dev_err(codec->dev, "sysclk < 384 x fs, disable i2s asrc\n");
1848
1849 return 0;
1850}
1851
1852/**
1853 * rt5663_sel_asrc_clk_src - select ASRC clock source for a set of filters
1854 * @codec: SoC audio codec device.
1855 * @filter_mask: mask of filters.
1856 * @clk_src: clock source
1857 *
73444723 1858 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5663 can
df7c5216
BL		 1859 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1860 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1861 * ASRC function will track i2s clock and generate a corresponding system clock
1862 * for codec. This function provides an API to select the clock source for a
1863 * set of filters specified by the mask. And the codec driver will turn on ASRC
1864 * for these filters if ASRC is selected as their clock source.
1865 */
1866int rt5663_sel_asrc_clk_src(struct snd_soc_codec *codec,
1867 unsigned int filter_mask, unsigned int clk_src)
1868{
73444723 1869 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
df7c5216
BL		 1870 unsigned int asrc2_mask = 0;
1871 unsigned int asrc2_value = 0;
1872 unsigned int asrc3_mask = 0;
1873 unsigned int asrc3_value = 0;
1874
1875 switch (clk_src) {
1876 case RT5663_CLK_SEL_SYS:
1877 case RT5663_CLK_SEL_I2S1_ASRC:
1878 break;
1879
1880 default:
1881 return -EINVAL;
1882 }
1883
1884 if (filter_mask & RT5663_DA_STEREO_FILTER) {
73444723
BL		 1885 asrc2_mask |= RT5663_DA_STO1_TRACK_MASK;
1886 asrc2_value |= clk_src << RT5663_DA_STO1_TRACK_SHIFT;
df7c5216
BL		 1887 }
1888
1889 if (filter_mask & RT5663_AD_STEREO_FILTER) {
73444723
BL		 1890 switch (rt5663->codec_ver) {
1891 case CODEC_VER_1:
1892 asrc3_mask |= RT5663_V2_AD_STO1_TRACK_MASK;
1893 asrc3_value |= clk_src << RT5663_V2_AD_STO1_TRACK_SHIFT;
df7c5216 1894 break;
73444723 1895 case CODEC_VER_0:
df7c5216
BL		 1896 asrc2_mask |= RT5663_AD_STO1_TRACK_MASK;
1897 asrc2_value |= clk_src << RT5663_AD_STO1_TRACK_SHIFT;
1898 break;
1899 default:
73444723 1900 dev_err(codec->dev, "Unknown CODEC Version\n");
df7c5216
BL		 1901 }
1902 }
1903
1904 if (asrc2_mask)
1905 snd_soc_update_bits(codec, RT5663_ASRC_2, asrc2_mask,
1906 asrc2_value);
1907
1908 if (asrc3_mask)
73444723 1909 snd_soc_update_bits(codec, RT5663_ASRC_3, asrc3_mask,
df7c5216
BL		 1910 asrc3_value);
1911
1912 return 0;
1913}
1914EXPORT_SYMBOL_GPL(rt5663_sel_asrc_clk_src);
1915
1916/* Analog Mixer */
73444723
BL		 1917static const struct snd_kcontrol_new rt5663_recmix1l[] = {
1918 SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1L,
1919 RT5663_RECMIX1L_BST2_SHIFT, 1, 1),
1920 SOC_DAPM_SINGLE("BST1 CBJ Switch", RT5663_RECMIX1L,
1921 RT5663_RECMIX1L_BST1_CBJ_SHIFT, 1, 1),
df7c5216
BL		 1922};
1923
73444723
BL		 1924static const struct snd_kcontrol_new rt5663_recmix1r[] = {
1925 SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1R,
1926 RT5663_RECMIX1R_BST2_SHIFT, 1, 1),
df7c5216
BL		 1927};
1928
1929/* Digital Mixer */
1930static const struct snd_kcontrol_new rt5663_sto1_adc_l_mix[] = {
1931 SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER,
73444723 1932 RT5663_M_STO1_ADC_L1_SHIFT, 1, 1),
df7c5216 1933 SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER,
73444723 1934 RT5663_M_STO1_ADC_L2_SHIFT, 1, 1),
df7c5216
BL		 1935};
1936
73444723 1937static const struct snd_kcontrol_new rt5663_sto1_adc_r_mix[] = {
df7c5216 1938 SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER,
73444723 1939 RT5663_M_STO1_ADC_R1_SHIFT, 1, 1),
df7c5216 1940 SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER,
73444723 1941 RT5663_M_STO1_ADC_R2_SHIFT, 1, 1),
df7c5216
BL		 1942};
1943
1944static const struct snd_kcontrol_new rt5663_adda_l_mix[] = {
1945 SOC_DAPM_SINGLE("ADC L Switch", RT5663_AD_DA_MIXER,
73444723 1946 RT5663_M_ADCMIX_L_SHIFT, 1, 1),
df7c5216 1947 SOC_DAPM_SINGLE("DAC L Switch", RT5663_AD_DA_MIXER,
73444723 1948 RT5663_M_DAC1_L_SHIFT, 1, 1),
df7c5216
BL		 1949};
1950
1951static const struct snd_kcontrol_new rt5663_adda_r_mix[] = {
1952 SOC_DAPM_SINGLE("ADC R Switch", RT5663_AD_DA_MIXER,
73444723 1953 RT5663_M_ADCMIX_R_SHIFT, 1, 1),
df7c5216 1954 SOC_DAPM_SINGLE("DAC R Switch", RT5663_AD_DA_MIXER,
73444723 1955 RT5663_M_DAC1_R_SHIFT, 1, 1),
df7c5216
BL		 1956};
1957
1958static const struct snd_kcontrol_new rt5663_sto1_dac_l_mix[] = {
1959 SOC_DAPM_SINGLE("DAC L Switch", RT5663_STO_DAC_MIXER,
73444723 1960 RT5663_M_DAC_L1_STO_L_SHIFT, 1, 1),
df7c5216 1961 SOC_DAPM_SINGLE("DAC R Switch", RT5663_STO_DAC_MIXER,
73444723 1962 RT5663_M_DAC_R1_STO_L_SHIFT, 1, 1),
df7c5216
BL		 1963};
1964
1965static const struct snd_kcontrol_new rt5663_sto1_dac_r_mix[] = {
1966 SOC_DAPM_SINGLE("DAC L Switch", RT5663_STO_DAC_MIXER,
73444723 1967 RT5663_M_DAC_L1_STO_R_SHIFT, 1, 1),
df7c5216 1968 SOC_DAPM_SINGLE("DAC R Switch", RT5663_STO_DAC_MIXER,
73444723 1969 RT5663_M_DAC_R1_STO_R_SHIFT, 1, 1),
df7c5216
BL		 1970};
1971
1972/* Out Switch */
73444723
BL		 1973static const struct snd_kcontrol_new rt5663_hpo_switch =
1974 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5663_HP_AMP_2,
1975 RT5663_EN_DAC_HPO_SHIFT, 1, 0);
df7c5216
BL		 1976
1977/* Stereo ADC source */
73444723 1978static const char * const rt5663_sto1_adc_src[] = {
df7c5216
BL		 1979 "ADC L", "ADC R"
1980};
1981
73444723
BL		 1982static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcl_enum, RT5663_STO1_ADC_MIXER,
1983 RT5663_STO1_ADC_L_SRC_SHIFT, rt5663_sto1_adc_src);
df7c5216 1984
73444723
BL		 1985static const struct snd_kcontrol_new rt5663_sto1_adcl_mux =
1986 SOC_DAPM_ENUM("STO1 ADC L Mux", rt5663_sto1_adcl_enum);
df7c5216 1987
73444723
BL		 1988static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcr_enum, RT5663_STO1_ADC_MIXER,
1989 RT5663_STO1_ADC_R_SRC_SHIFT, rt5663_sto1_adc_src);
df7c5216 1990
73444723
BL		 1991static const struct snd_kcontrol_new rt5663_sto1_adcr_mux =
1992 SOC_DAPM_ENUM("STO1 ADC R Mux", rt5663_sto1_adcr_enum);
df7c5216
BL		 1993
1994/* RT5663: Analog DACL1 input source */
1995static const char * const rt5663_alg_dacl_src[] = {
1996 "DAC L", "STO DAC MIXL"
1997};
1998
1999static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacl_enum, RT5663_BYPASS_STO_DAC,
2000 RT5663_DACL1_SRC_SHIFT, rt5663_alg_dacl_src);
2001
2002static const struct snd_kcontrol_new rt5663_alg_dacl_mux =
2003 SOC_DAPM_ENUM("DAC L Mux", rt5663_alg_dacl_enum);
2004
2005/* RT5663: Analog DACR1 input source */
2006static const char * const rt5663_alg_dacr_src[] = {
2007 "DAC R", "STO DAC MIXR"
2008};
2009
2010static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacr_enum, RT5663_BYPASS_STO_DAC,
2011 RT5663_DACR1_SRC_SHIFT, rt5663_alg_dacr_src);
2012
2013static const struct snd_kcontrol_new rt5663_alg_dacr_mux =
2014 SOC_DAPM_ENUM("DAC R Mux", rt5663_alg_dacr_enum);
2015
2016static int rt5663_hp_event(struct snd_soc_dapm_widget *w,
2017 struct snd_kcontrol *kcontrol, int event)
2018{
2019 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2020 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2021
2022 switch (event) {
2023 case SND_SOC_DAPM_POST_PMU:
73444723 2024 if (rt5663->codec_ver == CODEC_VER_1) {
df7c5216 2025 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
73444723 2026 RT5663_SEL_PM_HP_SHIFT, RT5663_SEL_PM_HP_HIGH);
df7c5216 2027 snd_soc_update_bits(codec, RT5663_HP_LOGIC_2,
73444723
BL		 2028 RT5663_HP_SIG_SRC1_MASK,
2029 RT5663_HP_SIG_SRC1_SILENCE);
df7c5216
BL		 2030 } else {
2031 snd_soc_write(codec, RT5663_DEPOP_2, 0x3003);
2032 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x000b,
2033 0x000b);
2034 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0030,
2035 0x0030);
2036 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
73444723 2037 RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_DIS);
df7c5216
BL		 2038 snd_soc_write(codec, RT5663_HP_CHARGE_PUMP_2, 0x1371);
2039 snd_soc_write(codec, RT5663_HP_BIAS, 0xabba);
2040 snd_soc_write(codec, RT5663_CHARGE_PUMP_1, 0x2224);
2041 snd_soc_write(codec, RT5663_ANA_BIAS_CUR_1, 0x7766);
2042 snd_soc_write(codec, RT5663_HP_BIAS, 0xafaa);
2043 snd_soc_write(codec, RT5663_CHARGE_PUMP_2, 0x7777);
2044 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x3000,
2045 0x3000);
2046 }
2047 break;
2048
2049 case SND_SOC_DAPM_PRE_PMD:
73444723 2050 if (rt5663->codec_ver == CODEC_VER_1) {
df7c5216 2051 snd_soc_update_bits(codec, RT5663_HP_LOGIC_2,
73444723
BL		 2052 RT5663_HP_SIG_SRC1_MASK,
2053 RT5663_HP_SIG_SRC1_REG);
df7c5216
BL		 2054 } else {
2055 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x3000, 0x0);
2056 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
73444723 2057 RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_EN);
df7c5216
BL		 2058 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0030, 0x0);
2059 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x000b,
2060 0x000b);
2061 }
2062 break;
2063
2064 default:
2065 return 0;
2066 }
2067
2068 return 0;
2069}
2070
73444723 2071static int rt5663_bst2_power(struct snd_soc_dapm_widget *w,
df7c5216
BL		 2072 struct snd_kcontrol *kcontrol, int event)
2073{
2074 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2075
2076 switch (event) {
2077 case SND_SOC_DAPM_POST_PMU:
2078 snd_soc_update_bits(codec, RT5663_PWR_ANLG_2,
73444723
BL		 2079 RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK,
2080 RT5663_PWR_BST2 | RT5663_PWR_BST2_OP);
df7c5216
BL		 2081 break;
2082
2083 case SND_SOC_DAPM_PRE_PMD:
2084 snd_soc_update_bits(codec, RT5663_PWR_ANLG_2,
73444723 2085 RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK, 0);
df7c5216
BL		 2086 break;
2087
2088 default:
2089 return 0;
2090 }
2091
2092 return 0;
2093}
2094
2095static int rt5663_pre_div_power(struct snd_soc_dapm_widget *w,
2096 struct snd_kcontrol *kcontrol, int event)
2097{
2098 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2099
2100 switch (event) {
2101 case SND_SOC_DAPM_POST_PMU:
2102 snd_soc_write(codec, RT5663_PRE_DIV_GATING_1, 0xff00);
2103 snd_soc_write(codec, RT5663_PRE_DIV_GATING_2, 0xfffc);
2104 break;
2105
2106 case SND_SOC_DAPM_PRE_PMD:
2107 snd_soc_write(codec, RT5663_PRE_DIV_GATING_1, 0x0000);
2108 snd_soc_write(codec, RT5663_PRE_DIV_GATING_2, 0x0000);
2109 break;
2110
2111 default:
2112 return 0;
2113 }
2114
2115 return 0;
2116}
2117
2118static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
73444723 2119 SND_SOC_DAPM_SUPPLY("PLL", RT5663_PWR_ANLG_3, RT5663_PWR_PLL_SHIFT, 0,
df7c5216
BL		 2120 NULL, 0),
2121
2122 /* micbias */
2123 SND_SOC_DAPM_MICBIAS("MICBIAS1", RT5663_PWR_ANLG_2,
73444723 2124 RT5663_PWR_MB1_SHIFT, 0),
df7c5216 2125 SND_SOC_DAPM_MICBIAS("MICBIAS2", RT5663_PWR_ANLG_2,
73444723 2126 RT5663_PWR_MB2_SHIFT, 0),
df7c5216
BL		 2127
2128 /* Input Lines */
2129 SND_SOC_DAPM_INPUT("IN1P"),
2130 SND_SOC_DAPM_INPUT("IN1N"),
2131
2132 /* REC Mixer Power */
2133 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5663_PWR_ANLG_2,
73444723 2134 RT5663_PWR_RECMIX1_SHIFT, 0, NULL, 0),
df7c5216
BL		 2135
2136 /* ADCs */
2137 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
2138 SND_SOC_DAPM_SUPPLY("ADC L Power", RT5663_PWR_DIG_1,
73444723 2139 RT5663_PWR_ADC_L1_SHIFT, 0, NULL, 0),
df7c5216 2140 SND_SOC_DAPM_SUPPLY("ADC Clock", RT5663_CHOP_ADC,
73444723 2141 RT5663_CKGEN_ADCC_SHIFT, 0, NULL, 0),
df7c5216
BL		 2142
2143 /* ADC Mixer */
2144 SND_SOC_DAPM_MIXER("STO1 ADC MIXL", SND_SOC_NOPM,
2145 0, 0, rt5663_sto1_adc_l_mix,
2146 ARRAY_SIZE(rt5663_sto1_adc_l_mix)),
2147
2148 /* ADC Filter Power */
2149 SND_SOC_DAPM_SUPPLY("STO1 ADC Filter", RT5663_PWR_DIG_2,
73444723 2150 RT5663_PWR_ADC_S1F_SHIFT, 0, NULL, 0),
df7c5216
BL		 2151
2152 /* Digital Interface */
73444723 2153 SND_SOC_DAPM_SUPPLY("I2S", RT5663_PWR_DIG_1, RT5663_PWR_I2S1_SHIFT, 0,
df7c5216
BL		 2154 NULL, 0),
2155 SND_SOC_DAPM_PGA("IF DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2156 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2157 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2158 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2159 SND_SOC_DAPM_PGA("IF ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2160
2161 /* Audio Interface */
2162 SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0),
2163 SND_SOC_DAPM_AIF_OUT("AIFTX", "AIF Capture", 0, SND_SOC_NOPM, 0, 0),
2164
2165 /* DAC mixer before sound effect */
2166 SND_SOC_DAPM_MIXER("ADDA MIXL", SND_SOC_NOPM, 0, 0, rt5663_adda_l_mix,
2167 ARRAY_SIZE(rt5663_adda_l_mix)),
2168 SND_SOC_DAPM_MIXER("ADDA MIXR", SND_SOC_NOPM, 0, 0, rt5663_adda_r_mix,
2169 ARRAY_SIZE(rt5663_adda_r_mix)),
2170 SND_SOC_DAPM_PGA("DAC L1", SND_SOC_NOPM, 0, 0, NULL, 0),
2171 SND_SOC_DAPM_PGA("DAC R1", SND_SOC_NOPM, 0, 0, NULL, 0),
2172
2173 /* DAC Mixer */
2174 SND_SOC_DAPM_SUPPLY("STO1 DAC Filter", RT5663_PWR_DIG_2,
73444723 2175 RT5663_PWR_DAC_S1F_SHIFT, 0, NULL, 0),
df7c5216
BL		 2176 SND_SOC_DAPM_MIXER("STO1 DAC MIXL", SND_SOC_NOPM, 0, 0,
2177 rt5663_sto1_dac_l_mix, ARRAY_SIZE(rt5663_sto1_dac_l_mix)),
2178 SND_SOC_DAPM_MIXER("STO1 DAC MIXR", SND_SOC_NOPM, 0, 0,
2179 rt5663_sto1_dac_r_mix, ARRAY_SIZE(rt5663_sto1_dac_r_mix)),
2180
2181 /* DACs */
2182 SND_SOC_DAPM_SUPPLY("STO1 DAC L Power", RT5663_PWR_DIG_1,
73444723 2183 RT5663_PWR_DAC_L1_SHIFT, 0, NULL, 0),
df7c5216 2184 SND_SOC_DAPM_SUPPLY("STO1 DAC R Power", RT5663_PWR_DIG_1,
73444723 2185 RT5663_PWR_DAC_R1_SHIFT, 0, NULL, 0),
df7c5216
BL		 2186 SND_SOC_DAPM_DAC("DAC L", NULL, SND_SOC_NOPM, 0, 0),
2187 SND_SOC_DAPM_DAC("DAC R", NULL, SND_SOC_NOPM, 0, 0),
2188
2189 /* Headphone*/
2190 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5663_hp_event,
2191 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2192
2193 /* Output Lines */
2194 SND_SOC_DAPM_OUTPUT("HPOL"),
2195 SND_SOC_DAPM_OUTPUT("HPOR"),
2196};
2197
73444723 2198static const struct snd_soc_dapm_widget rt5663_v2_specific_dapm_widgets[] = {
df7c5216 2199 SND_SOC_DAPM_SUPPLY("LDO2", RT5663_PWR_ANLG_3,
73444723
BL		 2200 RT5663_PWR_LDO2_SHIFT, 0, NULL, 0),
2201 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5663_PWR_VOL,
2202 RT5663_V2_PWR_MIC_DET_SHIFT, 0, NULL, 0),
df7c5216 2203 SND_SOC_DAPM_SUPPLY("LDO DAC", RT5663_PWR_DIG_1,
73444723 2204 RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
df7c5216
BL		 2205
2206 /* ASRC */
2207 SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1,
73444723 2208 RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0),
df7c5216 2209 SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1,
73444723 2210 RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0),
df7c5216 2211 SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1,
73444723 2212 RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0),
df7c5216
BL		 2213
2214 /* Input Lines */
2215 SND_SOC_DAPM_INPUT("IN2P"),
2216 SND_SOC_DAPM_INPUT("IN2N"),
2217
2218 /* Boost */
2219 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 0, 0, NULL, 0),
2220 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5663_PWR_ANLG_3,
73444723 2221 RT5663_PWR_CBJ_SHIFT, 0, NULL, 0),
df7c5216
BL		 2222 SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM, 0, 0, NULL, 0),
2223 SND_SOC_DAPM_SUPPLY("BST2 Power", SND_SOC_NOPM, 0, 0,
73444723 2224 rt5663_bst2_power, SND_SOC_DAPM_PRE_PMD |
df7c5216
BL		 2225 SND_SOC_DAPM_POST_PMU),
2226
2227 /* REC Mixer */
73444723
BL		 2228 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5663_recmix1l,
2229 ARRAY_SIZE(rt5663_recmix1l)),
2230 SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5663_recmix1r,
2231 ARRAY_SIZE(rt5663_recmix1r)),
df7c5216 2232 SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5663_PWR_ANLG_2,
73444723 2233 RT5663_PWR_RECMIX2_SHIFT, 0, NULL, 0),
df7c5216
BL		 2234
2235 /* ADC */
2236 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
2237 SND_SOC_DAPM_SUPPLY("ADC R Power", RT5663_PWR_DIG_1,
73444723 2238 RT5663_PWR_ADC_R1_SHIFT, 0, NULL, 0),
df7c5216
BL		 2239
2240 /* ADC Mux */
2241 SND_SOC_DAPM_PGA("STO1 ADC L1", RT5663_STO1_ADC_MIXER,
73444723 2242 RT5663_STO1_ADC_L1_SRC_SHIFT, 0, NULL, 0),
df7c5216 2243 SND_SOC_DAPM_PGA("STO1 ADC R1", RT5663_STO1_ADC_MIXER,
73444723 2244 RT5663_STO1_ADC_R1_SRC_SHIFT, 0, NULL, 0),
df7c5216 2245 SND_SOC_DAPM_PGA("STO1 ADC L2", RT5663_STO1_ADC_MIXER,
73444723 2246 RT5663_STO1_ADC_L2_SRC_SHIFT, 1, NULL, 0),
df7c5216 2247 SND_SOC_DAPM_PGA("STO1 ADC R2", RT5663_STO1_ADC_MIXER,
73444723 2248 RT5663_STO1_ADC_R2_SRC_SHIFT, 1, NULL, 0),
df7c5216
BL		 2249
2250 SND_SOC_DAPM_MUX("STO1 ADC L Mux", SND_SOC_NOPM, 0, 0,
73444723 2251 &rt5663_sto1_adcl_mux),
df7c5216 2252 SND_SOC_DAPM_MUX("STO1 ADC R Mux", SND_SOC_NOPM, 0, 0,
73444723 2253 &rt5663_sto1_adcr_mux),
df7c5216
BL		 2254
2255 /* ADC Mix */
2256 SND_SOC_DAPM_MIXER("STO1 ADC MIXR", SND_SOC_NOPM, 0, 0,
73444723 2257 rt5663_sto1_adc_r_mix, ARRAY_SIZE(rt5663_sto1_adc_r_mix)),
df7c5216
BL		 2258
2259 /* Analog DAC Clock */
2260 SND_SOC_DAPM_SUPPLY("DAC Clock", RT5663_CHOP_DAC_L,
73444723 2261 RT5663_CKGEN_DAC1_SHIFT, 0, NULL, 0),
df7c5216
BL		 2262
2263 /* Headphone out */
2264 SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0,
73444723 2265 &rt5663_hpo_switch),
df7c5216
BL		 2266};
2267
2268static const struct snd_soc_dapm_widget rt5663_specific_dapm_widgets[] = {
2269 /* System Clock Pre Divider Gating */
2270 SND_SOC_DAPM_SUPPLY("Pre Div Power", SND_SOC_NOPM, 0, 0,
2271 rt5663_pre_div_power, SND_SOC_DAPM_POST_PMU |
2272 SND_SOC_DAPM_PRE_PMD),
2273
2274 /* LDO */
2275 SND_SOC_DAPM_SUPPLY("LDO ADC", RT5663_PWR_DIG_1,
73444723 2276 RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
df7c5216
BL		 2277
2278 /* ASRC */
2279 SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1,
2280 RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0),
2281 SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1,
2282 RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0),
2283 SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1,
2284 RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0),
2285
2286 /* Boost */
2287 SND_SOC_DAPM_PGA("BST1", SND_SOC_NOPM, 0, 0, NULL, 0),
2288
2289 /* STO ADC */
2290 SND_SOC_DAPM_PGA("STO1 ADC L1", SND_SOC_NOPM, 0, 0, NULL, 0),
2291 SND_SOC_DAPM_PGA("STO1 ADC L2", SND_SOC_NOPM, 0, 0, NULL, 0),
2292
2293 /* Analog DAC source */
2294 SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0, &rt5663_alg_dacl_mux),
2295 SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0, &rt5663_alg_dacr_mux),
2296};
2297
2298static const struct snd_soc_dapm_route rt5663_dapm_routes[] = {
2299 /* PLL */
2300 { "I2S", NULL, "PLL", rt5663_is_sys_clk_from_pll },
2301
2302 /* ASRC */
2303 { "STO1 ADC Filter", NULL, "ADC ASRC", rt5663_is_using_asrc },
2304 { "STO1 DAC Filter", NULL, "DAC ASRC", rt5663_is_using_asrc },
2305 { "I2S", NULL, "I2S ASRC", rt5663_i2s_use_asrc },
2306
2307 { "ADC L", NULL, "ADC L Power" },
2308 { "ADC L", NULL, "ADC Clock" },
2309
2310 { "STO1 ADC L2", NULL, "STO1 DAC MIXL" },
2311
2312 { "STO1 ADC MIXL", "ADC1 Switch", "STO1 ADC L1" },
2313 { "STO1 ADC MIXL", "ADC2 Switch", "STO1 ADC L2" },
2314 { "STO1 ADC MIXL", NULL, "STO1 ADC Filter" },
2315
2316 { "IF1 ADC1", NULL, "STO1 ADC MIXL" },
2317 { "IF ADC", NULL, "IF1 ADC1" },
2318 { "AIFTX", NULL, "IF ADC" },
2319 { "AIFTX", NULL, "I2S" },
2320
2321 { "AIFRX", NULL, "I2S" },
2322 { "IF DAC", NULL, "AIFRX" },
2323 { "IF1 DAC1 L", NULL, "IF DAC" },
2324 { "IF1 DAC1 R", NULL, "IF DAC" },
2325
2326 { "ADDA MIXL", "ADC L Switch", "STO1 ADC MIXL" },
2327 { "ADDA MIXL", "DAC L Switch", "IF1 DAC1 L" },
2328 { "ADDA MIXL", NULL, "STO1 DAC Filter" },
2329 { "ADDA MIXL", NULL, "STO1 DAC L Power" },
2330 { "ADDA MIXR", "DAC R Switch", "IF1 DAC1 R" },
2331 { "ADDA MIXR", NULL, "STO1 DAC Filter" },
2332 { "ADDA MIXR", NULL, "STO1 DAC R Power" },
2333
2334 { "DAC L1", NULL, "ADDA MIXL" },
2335 { "DAC R1", NULL, "ADDA MIXR" },
2336
2337 { "STO1 DAC MIXL", "DAC L Switch", "DAC L1" },
2338 { "STO1 DAC MIXL", "DAC R Switch", "DAC R1" },
2339 { "STO1 DAC MIXL", NULL, "STO1 DAC L Power" },
2340 { "STO1 DAC MIXL", NULL, "STO1 DAC Filter" },
2341 { "STO1 DAC MIXR", "DAC R Switch", "DAC R1" },
2342 { "STO1 DAC MIXR", "DAC L Switch", "DAC L1" },
2343 { "STO1 DAC MIXR", NULL, "STO1 DAC R Power" },
2344 { "STO1 DAC MIXR", NULL, "STO1 DAC Filter" },
2345
2346 { "HP Amp", NULL, "DAC L" },
2347 { "HP Amp", NULL, "DAC R" },
2348};
2349
73444723 2350static const struct snd_soc_dapm_route rt5663_v2_specific_dapm_routes[] = {
df7c5216
BL		 2351 { "MICBIAS1", NULL, "LDO2" },
2352 { "MICBIAS2", NULL, "LDO2" },
2353
2354 { "BST1 CBJ", NULL, "IN1P" },
2355 { "BST1 CBJ", NULL, "IN1N" },
2356 { "BST1 CBJ", NULL, "CBJ Power" },
2357
2358 { "BST2", NULL, "IN2P" },
2359 { "BST2", NULL, "IN2N" },
2360 { "BST2", NULL, "BST2 Power" },
2361
2362 { "RECMIX1L", "BST2 Switch", "BST2" },
2363 { "RECMIX1L", "BST1 CBJ Switch", "BST1 CBJ" },
2364 { "RECMIX1L", NULL, "RECMIX1L Power" },
2365 { "RECMIX1R", "BST2 Switch", "BST2" },
2366 { "RECMIX1R", NULL, "RECMIX1R Power" },
2367
2368 { "ADC L", NULL, "RECMIX1L" },
2369 { "ADC R", NULL, "RECMIX1R" },
2370 { "ADC R", NULL, "ADC R Power" },
2371 { "ADC R", NULL, "ADC Clock" },
2372
2373 { "STO1 ADC L Mux", "ADC L", "ADC L" },
2374 { "STO1 ADC L Mux", "ADC R", "ADC R" },
2375 { "STO1 ADC L1", NULL, "STO1 ADC L Mux" },
2376
2377 { "STO1 ADC R Mux", "ADC L", "ADC L" },
2378 { "STO1 ADC R Mux", "ADC R", "ADC R" },
2379 { "STO1 ADC R1", NULL, "STO1 ADC R Mux" },
2380 { "STO1 ADC R2", NULL, "STO1 DAC MIXR" },
2381
2382 { "STO1 ADC MIXR", "ADC1 Switch", "STO1 ADC R1" },
2383 { "STO1 ADC MIXR", "ADC2 Switch", "STO1 ADC R2" },
2384 { "STO1 ADC MIXR", NULL, "STO1 ADC Filter" },
2385
2386 { "IF1 ADC1", NULL, "STO1 ADC MIXR" },
2387
2388 { "ADDA MIXR", "ADC R Switch", "STO1 ADC MIXR" },
2389
2390 { "DAC L", NULL, "STO1 DAC MIXL" },
2391 { "DAC L", NULL, "LDO DAC" },
2392 { "DAC L", NULL, "DAC Clock" },
2393 { "DAC R", NULL, "STO1 DAC MIXR" },
2394 { "DAC R", NULL, "LDO DAC" },
2395 { "DAC R", NULL, "DAC Clock" },
2396
2397 { "HPO Playback", "Switch", "HP Amp" },
2398 { "HPOL", NULL, "HPO Playback" },
2399 { "HPOR", NULL, "HPO Playback" },
2400};
2401
2402static const struct snd_soc_dapm_route rt5663_specific_dapm_routes[] = {
2403 { "I2S", NULL, "Pre Div Power" },
2404
2405 { "BST1", NULL, "IN1P" },
2406 { "BST1", NULL, "IN1N" },
2407 { "BST1", NULL, "RECMIX1L Power" },
2408
2409 { "ADC L", NULL, "BST1" },
2410
2411 { "STO1 ADC L1", NULL, "ADC L" },
2412
2413 { "DAC L Mux", "DAC L", "DAC L1" },
2414 { "DAC L Mux", "STO DAC MIXL", "STO1 DAC MIXL" },
2415 { "DAC R Mux", "DAC R", "DAC R1"},
2416 { "DAC R Mux", "STO DAC MIXR", "STO1 DAC MIXR" },
2417
2418 { "DAC L", NULL, "DAC L Mux" },
2419 { "DAC R", NULL, "DAC R Mux" },
2420
2421 { "HPOL", NULL, "HP Amp" },
2422 { "HPOR", NULL, "HP Amp" },
2423};
2424
2425static int rt5663_hw_params(struct snd_pcm_substream *substream,
2426 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2427{
2428 struct snd_soc_codec *codec = dai->codec;
2429 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2430 unsigned int val_len = 0;
2431 int pre_div;
2432
2433 rt5663->lrck = params_rate(params);
2434
2435 dev_dbg(dai->dev, "bclk is %dHz and sysclk is %dHz\n",
2436 rt5663->lrck, rt5663->sysclk);
2437
2438 pre_div = rl6231_get_clk_info(rt5663->sysclk, rt5663->lrck);
2439 if (pre_div < 0) {
2440 dev_err(codec->dev, "Unsupported clock setting %d for DAI %d\n",
2441 rt5663->lrck, dai->id);
2442 return -EINVAL;
2443 }
2444
2445 dev_dbg(dai->dev, "pre_div is %d for iis %d\n", pre_div, dai->id);
2446
2447 switch (params_width(params)) {
2448 case 8:
73444723 2449 val_len = RT5663_I2S_DL_8;
df7c5216
BL		 2450 break;
2451 case 16:
73444723 2452 val_len = RT5663_I2S_DL_16;
df7c5216
BL		 2453 break;
2454 case 20:
73444723 2455 val_len = RT5663_I2S_DL_20;
df7c5216
BL		 2456 break;
2457 case 24:
73444723 2458 val_len = RT5663_I2S_DL_24;
df7c5216
BL		 2459 break;
2460 default:
2461 return -EINVAL;
2462 }
2463
2464 snd_soc_update_bits(codec, RT5663_I2S1_SDP,
73444723 2465 RT5663_I2S_DL_MASK, val_len);
df7c5216
BL		 2466
2467 snd_soc_update_bits(codec, RT5663_ADDA_CLK_1,
73444723 2468 RT5663_I2S_PD1_MASK, pre_div << RT5663_I2S_PD1_SHIFT);
df7c5216
BL		 2469
2470 return 0;
2471}
2472
2473static int rt5663_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2474{
2475 struct snd_soc_codec *codec = dai->codec;
2476 unsigned int reg_val = 0;
2477
2478 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2479 case SND_SOC_DAIFMT_CBM_CFM:
2480 break;
2481 case SND_SOC_DAIFMT_CBS_CFS:
73444723 2482 reg_val |= RT5663_I2S_MS_S;
df7c5216
BL		 2483 break;
2484 default:
2485 return -EINVAL;
2486 }
2487
2488 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2489 case SND_SOC_DAIFMT_NB_NF:
2490 break;
2491 case SND_SOC_DAIFMT_IB_NF:
73444723 2492 reg_val |= RT5663_I2S_BP_INV;
df7c5216
BL		 2493 break;
2494 default:
2495 return -EINVAL;
2496 }
2497
2498 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2499 case SND_SOC_DAIFMT_I2S:
2500 break;
2501 case SND_SOC_DAIFMT_LEFT_J:
73444723 2502 reg_val |= RT5663_I2S_DF_LEFT;
df7c5216
BL		 2503 break;
2504 case SND_SOC_DAIFMT_DSP_A:
73444723 2505 reg_val |= RT5663_I2S_DF_PCM_A;
df7c5216
BL		 2506 break;
2507 case SND_SOC_DAIFMT_DSP_B:
73444723 2508 reg_val |= RT5663_I2S_DF_PCM_B;
df7c5216
BL		 2509 break;
2510 default:
2511 return -EINVAL;
2512 }
2513
73444723
BL		 2514 snd_soc_update_bits(codec, RT5663_I2S1_SDP, RT5663_I2S_MS_MASK |
2515 RT5663_I2S_BP_MASK | RT5663_I2S_DF_MASK, reg_val);
df7c5216
BL		 2516
2517 return 0;
2518}
2519
2520static int rt5663_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
2521 unsigned int freq, int dir)
2522{
2523 struct snd_soc_codec *codec = dai->codec;
2524 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2525 unsigned int reg_val = 0;
2526
2527 if (freq == rt5663->sysclk && clk_id == rt5663->sysclk_src)
2528 return 0;
2529
2530 switch (clk_id) {
2531 case RT5663_SCLK_S_MCLK:
2532 reg_val |= RT5663_SCLK_SRC_MCLK;
2533 break;
2534 case RT5663_SCLK_S_PLL1:
2535 reg_val |= RT5663_SCLK_SRC_PLL1;
2536 break;
2537 case RT5663_SCLK_S_RCCLK:
2538 reg_val |= RT5663_SCLK_SRC_RCCLK;
2539 break;
2540 default:
2541 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
2542 return -EINVAL;
2543 }
73444723 2544 snd_soc_update_bits(codec, RT5663_GLB_CLK, RT5663_SCLK_SRC_MASK,
df7c5216
BL		 2545 reg_val);
2546 rt5663->sysclk = freq;
2547 rt5663->sysclk_src = clk_id;
2548
2549 dev_dbg(codec->dev, "Sysclk is %dHz and clock id is %d\n",
2550 freq, clk_id);
2551
2552 return 0;
2553}
2554
2555static int rt5663_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2556 unsigned int freq_in, unsigned int freq_out)
2557{
2558 struct snd_soc_codec *codec = dai->codec;
2559 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2560 struct rl6231_pll_code pll_code;
2561 int ret;
2562 int mask, shift, val;
2563
2564 if (source == rt5663->pll_src && freq_in == rt5663->pll_in &&
2565 freq_out == rt5663->pll_out)
2566 return 0;
2567
2568 if (!freq_in || !freq_out) {
2569 dev_dbg(codec->dev, "PLL disabled\n");
2570
2571 rt5663->pll_in = 0;
2572 rt5663->pll_out = 0;
2573 snd_soc_update_bits(codec, RT5663_GLB_CLK,
2574 RT5663_SCLK_SRC_MASK, RT5663_SCLK_SRC_MCLK);
2575 return 0;
2576 }
2577
73444723
BL		 2578 switch (rt5663->codec_ver) {
2579 case CODEC_VER_1:
2580 mask = RT5663_V2_PLL1_SRC_MASK;
2581 shift = RT5663_V2_PLL1_SRC_SHIFT;
df7c5216 2582 break;
73444723 2583 case CODEC_VER_0:
df7c5216
BL		 2584 mask = RT5663_PLL1_SRC_MASK;
2585 shift = RT5663_PLL1_SRC_SHIFT;
2586 break;
2587 default:
73444723 2588 dev_err(codec->dev, "Unknown CODEC Version\n");
56efaed5 2589 return -EINVAL;
df7c5216
BL		 2590 }
2591
2592 switch (source) {
2593 case RT5663_PLL1_S_MCLK:
2594 val = 0x0;
2595 break;
2596 case RT5663_PLL1_S_BCLK1:
2597 val = 0x1;
2598 break;
2599 default:
2600 dev_err(codec->dev, "Unknown PLL source %d\n", source);
2601 return -EINVAL;
2602 }
2603 snd_soc_update_bits(codec, RT5663_GLB_CLK, mask, (val << shift));
2604
2605 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2606 if (ret < 0) {
2607 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
2608 return ret;
2609 }
2610
2611 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n", pll_code.m_bp,
2612 (pll_code.m_bp ? 0 : pll_code.m_code), pll_code.n_code,
2613 pll_code.k_code);
2614
2615 snd_soc_write(codec, RT5663_PLL_1,
73444723 2616 pll_code.n_code << RT5663_PLL_N_SHIFT | pll_code.k_code);
df7c5216 2617 snd_soc_write(codec, RT5663_PLL_2,
73444723
BL		 2618 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5663_PLL_M_SHIFT |
2619 pll_code.m_bp << RT5663_PLL_M_BP_SHIFT);
df7c5216
BL		 2620
2621 rt5663->pll_in = freq_in;
2622 rt5663->pll_out = freq_out;
2623 rt5663->pll_src = source;
2624
2625 return 0;
2626}
2627
2628static int rt5663_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2629 unsigned int rx_mask, int slots, int slot_width)
2630{
2631 struct snd_soc_codec *codec = dai->codec;
2632 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2633 unsigned int val = 0, reg;
2634
2635 if (rx_mask || tx_mask)
73444723 2636 val |= RT5663_TDM_MODE_TDM;
df7c5216
BL		 2637
2638 switch (slots) {
2639 case 4:
73444723
BL		 2640 val |= RT5663_TDM_IN_CH_4;
2641 val |= RT5663_TDM_OUT_CH_4;
df7c5216
BL		 2642 break;
2643 case 6:
73444723
BL		 2644 val |= RT5663_TDM_IN_CH_6;
2645 val |= RT5663_TDM_OUT_CH_6;
df7c5216
BL		 2646 break;
2647 case 8:
73444723
BL		 2648 val |= RT5663_TDM_IN_CH_8;
2649 val |= RT5663_TDM_OUT_CH_8;
df7c5216
BL		 2650 break;
2651 case 2:
2652 break;
2653 default:
2654 return -EINVAL;
2655 }
2656
2657 switch (slot_width) {
2658 case 20:
73444723
BL		 2659 val |= RT5663_TDM_IN_LEN_20;
2660 val |= RT5663_TDM_OUT_LEN_20;
df7c5216
BL		 2661 break;
2662 case 24:
73444723
BL		 2663 val |= RT5663_TDM_IN_LEN_24;
2664 val |= RT5663_TDM_OUT_LEN_24;
df7c5216
BL		 2665 break;
2666 case 32:
73444723
BL		 2667 val |= RT5663_TDM_IN_LEN_32;
2668 val |= RT5663_TDM_OUT_LEN_32;
df7c5216
BL		 2669 break;
2670 case 16:
2671 break;
2672 default:
2673 return -EINVAL;
2674 }
2675
73444723
BL		 2676 switch (rt5663->codec_ver) {
2677 case CODEC_VER_1:
df7c5216
BL		 2678 reg = RT5663_TDM_2;
2679 break;
73444723 2680 case CODEC_VER_0:
df7c5216
BL		 2681 reg = RT5663_TDM_1;
2682 break;
2683 default:
73444723 2684 dev_err(codec->dev, "Unknown CODEC Version\n");
56efaed5 2685 return -EINVAL;
df7c5216
BL		 2686 }
2687
73444723
BL		 2688 snd_soc_update_bits(codec, reg, RT5663_TDM_MODE_MASK |
2689 RT5663_TDM_IN_CH_MASK | RT5663_TDM_OUT_CH_MASK |
2690 RT5663_TDM_IN_LEN_MASK | RT5663_TDM_OUT_LEN_MASK, val);
df7c5216
BL		 2691
2692 return 0;
2693}
2694
2695static int rt5663_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2696{
2697 struct snd_soc_codec *codec = dai->codec;
2698 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2699 unsigned int reg;
2700
2701 dev_dbg(codec->dev, "%s ratio = %d\n", __func__, ratio);
2702
73444723
BL		 2703 if (rt5663->codec_ver == CODEC_VER_1)
2704 reg = RT5663_TDM_9;
df7c5216
BL		 2705 else
2706 reg = RT5663_TDM_5;
2707
2708 switch (ratio) {
2709 case 32:
2710 snd_soc_update_bits(codec, reg,
2711 RT5663_TDM_LENGTN_MASK,
2712 RT5663_TDM_LENGTN_16);
2713 break;
2714 case 40:
2715 snd_soc_update_bits(codec, reg,
2716 RT5663_TDM_LENGTN_MASK,
2717 RT5663_TDM_LENGTN_20);
2718 break;
2719 case 48:
2720 snd_soc_update_bits(codec, reg,
2721 RT5663_TDM_LENGTN_MASK,
2722 RT5663_TDM_LENGTN_24);
2723 break;
2724 case 64:
2725 snd_soc_update_bits(codec, reg,
2726 RT5663_TDM_LENGTN_MASK,
2727 RT5663_TDM_LENGTN_32);
2728 break;
2729 default:
2730 dev_err(codec->dev, "Invalid ratio!\n");
2731 return -EINVAL;
2732 }
2733
2734 return 0;
2735}
2736
2737static int rt5663_set_bias_level(struct snd_soc_codec *codec,
2738 enum snd_soc_bias_level level)
2739{
2740 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2741
2742 switch (level) {
2743 case SND_SOC_BIAS_ON:
2744 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
73444723
BL		 2745 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
2746 RT5663_PWR_FV1 | RT5663_PWR_FV2);
df7c5216
BL		 2747 break;
2748
2749 case SND_SOC_BIAS_PREPARE:
73444723 2750 if (rt5663->codec_ver == CODEC_VER_1) {
df7c5216 2751 snd_soc_update_bits(codec, RT5663_DIG_MISC,
73444723
BL		 2752 RT5663_DIG_GATE_CTRL_MASK,
2753 RT5663_DIG_GATE_CTRL_EN);
df7c5216 2754 snd_soc_update_bits(codec, RT5663_SIG_CLK_DET,
73444723
BL		 2755 RT5663_EN_ANA_CLK_DET_MASK |
2756 RT5663_PWR_CLK_DET_MASK,
2757 RT5663_EN_ANA_CLK_DET_AUTO |
2758 RT5663_PWR_CLK_DET_EN);
df7c5216
BL		 2759 }
2760 break;
2761
2762 case SND_SOC_BIAS_STANDBY:
73444723 2763 if (rt5663->codec_ver == CODEC_VER_1)
df7c5216 2764 snd_soc_update_bits(codec, RT5663_DIG_MISC,
73444723
BL		 2765 RT5663_DIG_GATE_CTRL_MASK,
2766 RT5663_DIG_GATE_CTRL_DIS);
df7c5216 2767 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
73444723
BL		 2768 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
2769 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK |
2770 RT5663_PWR_MB_MASK, RT5663_PWR_VREF1 |
2771 RT5663_PWR_VREF2 | RT5663_PWR_MB);
df7c5216 2772 usleep_range(10000, 10005);
73444723 2773 if (rt5663->codec_ver == CODEC_VER_1) {
df7c5216 2774 snd_soc_update_bits(codec, RT5663_SIG_CLK_DET,
73444723
BL		 2775 RT5663_EN_ANA_CLK_DET_MASK |
2776 RT5663_PWR_CLK_DET_MASK,
2777 RT5663_EN_ANA_CLK_DET_DIS |
2778 RT5663_PWR_CLK_DET_DIS);
df7c5216
BL		 2779 }
2780 break;
2781
2782 case SND_SOC_BIAS_OFF:
2783 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
73444723
BL		 2784 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
2785 RT5663_PWR_FV1 | RT5663_PWR_FV2, 0x0);
df7c5216
BL		 2786 break;
2787
2788 default:
2789 break;
2790 }
2791
2792 return 0;
2793}
2794
2795static int rt5663_probe(struct snd_soc_codec *codec)
2796{
2797 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
2798 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2799
2800 rt5663->codec = codec;
2801
73444723
BL		 2802 switch (rt5663->codec_ver) {
2803 case CODEC_VER_1:
df7c5216 2804 snd_soc_dapm_new_controls(dapm,
73444723
BL		 2805 rt5663_v2_specific_dapm_widgets,
2806 ARRAY_SIZE(rt5663_v2_specific_dapm_widgets));
df7c5216 2807 snd_soc_dapm_add_routes(dapm,
73444723
BL		 2808 rt5663_v2_specific_dapm_routes,
2809 ARRAY_SIZE(rt5663_v2_specific_dapm_routes));
2810 snd_soc_add_codec_controls(codec, rt5663_v2_specific_controls,
2811 ARRAY_SIZE(rt5663_v2_specific_controls));
df7c5216 2812 break;
73444723 2813 case CODEC_VER_0:
df7c5216
BL		 2814 snd_soc_dapm_new_controls(dapm,
2815 rt5663_specific_dapm_widgets,
2816 ARRAY_SIZE(rt5663_specific_dapm_widgets));
2817 snd_soc_dapm_add_routes(dapm,
2818 rt5663_specific_dapm_routes,
2819 ARRAY_SIZE(rt5663_specific_dapm_routes));
2820 snd_soc_add_codec_controls(codec, rt5663_specific_controls,
2821 ARRAY_SIZE(rt5663_specific_controls));
2822 break;
2823 }
2824
2825 return 0;
2826}
2827
2828static int rt5663_remove(struct snd_soc_codec *codec)
2829{
2830 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2831
2832 regmap_write(rt5663->regmap, RT5663_RESET, 0);
2833
2834 return 0;
2835}
2836
2837#ifdef CONFIG_PM
2838static int rt5663_suspend(struct snd_soc_codec *codec)
2839{
2840 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2841
2842 regcache_cache_only(rt5663->regmap, true);
2843 regcache_mark_dirty(rt5663->regmap);
2844
2845 return 0;
2846}
2847
2848static int rt5663_resume(struct snd_soc_codec *codec)
2849{
2850 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2851
2852 regcache_cache_only(rt5663->regmap, false);
2853 regcache_sync(rt5663->regmap);
2854
17616ce6
OC		 2855 rt5663_irq(0, rt5663);
2856
df7c5216
BL		 2857 return 0;
2858}
2859#else
2860#define rt5663_suspend NULL
2861#define rt5663_resume NULL
2862#endif
2863
2864#define RT5663_STEREO_RATES SNDRV_PCM_RATE_8000_192000
2865#define RT5663_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
2866 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
2867
66d7c262 2868static struct snd_soc_dai_ops rt5663_aif_dai_ops = {
df7c5216
BL		 2869 .hw_params = rt5663_hw_params,
2870 .set_fmt = rt5663_set_dai_fmt,
2871 .set_sysclk = rt5663_set_dai_sysclk,
2872 .set_pll = rt5663_set_dai_pll,
2873 .set_tdm_slot = rt5663_set_tdm_slot,
2874 .set_bclk_ratio = rt5663_set_bclk_ratio,
2875};
2876
66d7c262 2877static struct snd_soc_dai_driver rt5663_dai[] = {
df7c5216
BL		 2878 {
2879 .name = "rt5663-aif",
2880 .id = RT5663_AIF,
2881 .playback = {
2882 .stream_name = "AIF Playback",
2883 .channels_min = 1,
2884 .channels_max = 2,
2885 .rates = RT5663_STEREO_RATES,
2886 .formats = RT5663_FORMATS,
2887 },
2888 .capture = {
2889 .stream_name = "AIF Capture",
2890 .channels_min = 1,
2891 .channels_max = 2,
2892 .rates = RT5663_STEREO_RATES,
2893 .formats = RT5663_FORMATS,
2894 },
2895 .ops = &rt5663_aif_dai_ops,
2896 },
2897};
2898
2899static struct snd_soc_codec_driver soc_codec_dev_rt5663 = {
2900 .probe = rt5663_probe,
2901 .remove = rt5663_remove,
2902 .suspend = rt5663_suspend,
2903 .resume = rt5663_resume,
2904 .set_bias_level = rt5663_set_bias_level,
2905 .idle_bias_off = true,
2906 .component_driver = {
2907 .controls = rt5663_snd_controls,
2908 .num_controls = ARRAY_SIZE(rt5663_snd_controls),
2909 .dapm_widgets = rt5663_dapm_widgets,
2910 .num_dapm_widgets = ARRAY_SIZE(rt5663_dapm_widgets),
2911 .dapm_routes = rt5663_dapm_routes,
2912 .num_dapm_routes = ARRAY_SIZE(rt5663_dapm_routes),
2913 }
2914};
2915
73444723 2916static const struct regmap_config rt5663_v2_regmap = {
df7c5216
BL		 2917 .reg_bits = 16,
2918 .val_bits = 16,
2919 .use_single_rw = true,
2920 .max_register = 0x07fa,
73444723
BL		 2921 .volatile_reg = rt5663_v2_volatile_register,
2922 .readable_reg = rt5663_v2_readable_register,
df7c5216 2923 .cache_type = REGCACHE_RBTREE,
73444723
BL		 2924 .reg_defaults = rt5663_v2_reg,
2925 .num_reg_defaults = ARRAY_SIZE(rt5663_v2_reg),
df7c5216
BL		 2926};
2927
2928static const struct regmap_config rt5663_regmap = {
2929 .reg_bits = 16,
2930 .val_bits = 16,
2931 .use_single_rw = true,
2932 .max_register = 0x03f3,
2933 .volatile_reg = rt5663_volatile_register,
2934 .readable_reg = rt5663_readable_register,
2935 .cache_type = REGCACHE_RBTREE,
2936 .reg_defaults = rt5663_reg,
2937 .num_reg_defaults = ARRAY_SIZE(rt5663_reg),
2938};
2939
2940static const struct regmap_config temp_regmap = {
2941 .name = "nocache",
2942 .reg_bits = 16,
2943 .val_bits = 16,
2944 .use_single_rw = true,
2945 .max_register = 0x03f3,
2946 .cache_type = REGCACHE_NONE,
2947};
2948
2949static const struct i2c_device_id rt5663_i2c_id[] = {
df7c5216
BL		 2950 { "rt5663", 0 },
2951 {}
2952};
2953MODULE_DEVICE_TABLE(i2c, rt5663_i2c_id);
2954
2955#if defined(CONFIG_OF)
2956static const struct of_device_id rt5663_of_match[] = {
df7c5216
BL		 2957 { .compatible = "realtek,rt5663", },
2958 {},
2959};
2960MODULE_DEVICE_TABLE(of, rt5663_of_match);
2961#endif
2962
2963#ifdef CONFIG_ACPI
2964static struct acpi_device_id rt5663_acpi_match[] = {
df7c5216
BL		 2965 { "10EC5663", 0},
2966 {},
2967};
2968MODULE_DEVICE_TABLE(acpi, rt5663_acpi_match);
2969#endif
2970
73444723 2971static void rt5663_v2_calibrate(struct rt5663_priv *rt5663)
df7c5216 2972{
73444723
BL		 2973 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402);
2974 regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x0100);
2975 regmap_write(rt5663->regmap, RT5663_RECMIX, 0x4040);
2976 regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x0001);
2977 regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0380);
2978 regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000);
2979 regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1000);
2980 regmap_write(rt5663->regmap, RT5663_CHOP_DAC_L, 0x3030);
2981 regmap_write(rt5663->regmap, RT5663_CALIB_ADC, 0x3c05);
2982 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23e);
df7c5216 2983 msleep(40);
73444723
BL		 2984 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23e);
2985 regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x0321);
2986 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0xfc00);
df7c5216
BL		 2987 msleep(500);
2988}
2989
73444723 2990static void rt5663_calibrate(struct rt5663_priv *rt5663)
df7c5216
BL		 2991{
2992 int value, count;
2993
7d8e00c7 2994 regmap_write(rt5663->regmap, RT5663_RESET, 0x0000);
2995 msleep(20);
2996 regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_4, 0x00a1);
2997 regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0380);
73444723 2998 regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000);
7d8e00c7 2999 regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1000);
73444723 3000 regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032);
7d8e00c7 3001 regmap_write(rt5663->regmap, RT5663_HP_IMP_SEN_19, 0x000c);
3002 regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x0324);
3003 regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x8001);
3004 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23b);
3005 msleep(30);
3006 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23b);
3007 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x8000);
3008 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x0008);
73444723
BL		 3009 regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_1, 0xffff);
3010 regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_2, 0xffff);
7d8e00c7 3011 regmap_write(rt5663->regmap, RT5663_CBJ_1, 0x8c10);
3012 regmap_write(rt5663->regmap, RT5663_IL_CMD_2, 0x00c1);
3013 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_1, 0xb880);
3014 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_2, 0x4110);
3015 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_2, 0x4118);
3016
3017 count = 0;
3018 while (true) {
3019 regmap_read(rt5663->regmap, RT5663_INT_ST_2, &value);
3020 if (!(value & 0x80))
3021 usleep_range(10000, 10005);
3022 else
3023 break;
3024
3025 if (count > 200)
3026 break;
3027 }
3028
3029 regmap_write(rt5663->regmap, RT5663_HP_IMP_SEN_19, 0x0000);
73444723 3030 regmap_write(rt5663->regmap, RT5663_DEPOP_2, 0x3003);
7d8e00c7 3031 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x0038);
73444723 3032 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x003b);
7d8e00c7 3033 regmap_write(rt5663->regmap, RT5663_PWR_DIG_2, 0x8400);
3034 regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x8df8);
3035 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x8003);
3036 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x018c);
73444723 3037 regmap_write(rt5663->regmap, RT5663_HP_CHARGE_PUMP_1, 0x1e32);
73444723 3038 regmap_write(rt5663->regmap, RT5663_DACREF_LDO, 0x3b0b);
7d8e00c7 3039 regmap_write(rt5663->regmap, RT5663_STO_DAC_MIXER, 0x0000);
73444723 3040 regmap_write(rt5663->regmap, RT5663_BYPASS_STO_DAC, 0x000c);
7d8e00c7 3041 regmap_write(rt5663->regmap, RT5663_HP_BIAS, 0xafaa);
73444723
BL		 3042 regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_1, 0x2224);
3043 regmap_write(rt5663->regmap, RT5663_HP_OUT_EN, 0x8088);
3044 regmap_write(rt5663->regmap, RT5663_STO_DRE_9, 0x0017);
3045 regmap_write(rt5663->regmap, RT5663_STO_DRE_10, 0x0017);
3046 regmap_write(rt5663->regmap, RT5663_STO1_ADC_MIXER, 0x4040);
7d8e00c7 3047 regmap_write(rt5663->regmap, RT5663_CHOP_ADC, 0x3000);
73444723
BL		 3048 regmap_write(rt5663->regmap, RT5663_RECMIX, 0x0005);
3049 regmap_write(rt5663->regmap, RT5663_ADDA_RST, 0xc000);
3050 regmap_write(rt5663->regmap, RT5663_STO1_HPF_ADJ1, 0x3320);
3051 regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x00c9);
3052 regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x004c);
7d8e00c7 3053 regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_1, 0x1111);
3054 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0x4402);
3055 regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_2, 0x3311);
73444723 3056 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0x0069);
7d8e00c7 3057 regmap_write(rt5663->regmap, RT5663_HP_CALIB_3, 0x06ce);
3058 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x6800);
3059 regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_2, 0x1100);
3060 regmap_write(rt5663->regmap, RT5663_HP_CALIB_7, 0x0057);
3061 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xe800);
3062
df7c5216
BL		 3063 count = 0;
3064 while (true) {
73444723 3065 regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value);
df7c5216
BL		 3066 if (value & 0x8000)
3067 usleep_range(10000, 10005);
3068 else
3069 break;
3070
3071 if (count > 200)
3072 return;
3073 count++;
3074 }
7d8e00c7 3075
3076 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x6200);
3077 regmap_write(rt5663->regmap, RT5663_HP_CALIB_7, 0x0059);
3078 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xe200);
3079
3080 count = 0;
3081 while (true) {
3082 regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value);
3083 if (value & 0x8000)
3084 usleep_range(10000, 10005);
3085 else
3086 break;
3087
3088 if (count > 200)
3089 return;
3090 count++;
3091 }
3092
3093 regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_1, 0xb8e0);
3094 usleep_range(10000, 10005);
3095 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0x003b);
3096 usleep_range(10000, 10005);
3097 regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x0000);
3098 usleep_range(10000, 10005);
3099 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x000b);
3100 usleep_range(10000, 10005);
3101 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x0008);
3102 usleep_range(10000, 10005);
3103 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x0000);
3104 usleep_range(10000, 10005);
df7c5216
BL		 3105}
3106
3107static int rt5663_i2c_probe(struct i2c_client *i2c,
3108 const struct i2c_device_id *id)
3109{
3110 struct rt5663_priv *rt5663;
3111 int ret;
3112 unsigned int val;
3113 struct regmap *regmap;
3114
3115 rt5663 = devm_kzalloc(&i2c->dev, sizeof(struct rt5663_priv),
3116 GFP_KERNEL);
3117
3118 if (rt5663 == NULL)
3119 return -ENOMEM;
3120
3121 i2c_set_clientdata(i2c, rt5663);
3122
3123 regmap = devm_regmap_init_i2c(i2c, &temp_regmap);
3124 if (IS_ERR(regmap)) {
3125 ret = PTR_ERR(regmap);
3126 dev_err(&i2c->dev, "Failed to allocate temp register map: %d\n",
3127 ret);
3128 return ret;
3129 }
3130 regmap_read(regmap, RT5663_VENDOR_ID_2, &val);
3131 switch (val) {
73444723
BL		 3132 case RT5663_DEVICE_ID_2:
3133 rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_v2_regmap);
3134 rt5663->codec_ver = CODEC_VER_1;
df7c5216 3135 break;
73444723 3136 case RT5663_DEVICE_ID_1:
df7c5216 3137 rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_regmap);
73444723 3138 rt5663->codec_ver = CODEC_VER_0;
df7c5216
BL		 3139 break;
3140 default:
3141 dev_err(&i2c->dev,
73444723 3142 "Device with ID register %#x is not rt5663\n",
df7c5216
BL		 3143 val);
3144 return -ENODEV;
3145 }
3146
3147 if (IS_ERR(rt5663->regmap)) {
3148 ret = PTR_ERR(rt5663->regmap);
3149 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
3150 ret);
3151 return ret;
3152 }
3153
3154 /* reset and calibrate */
3155 regmap_write(rt5663->regmap, RT5663_RESET, 0);
3156 regcache_cache_bypass(rt5663->regmap, true);
73444723
BL		 3157 switch (rt5663->codec_ver) {
3158 case CODEC_VER_1:
3159 rt5663_v2_calibrate(rt5663);
df7c5216 3160 break;
73444723 3161 case CODEC_VER_0:
df7c5216
BL		 3162 rt5663_calibrate(rt5663);
3163 break;
3164 default:
3165 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3166 }
3167 regcache_cache_bypass(rt5663->regmap, false);
3168 regmap_write(rt5663->regmap, RT5663_RESET, 0);
3169 dev_dbg(&i2c->dev, "calibrate done\n");
3170
3171 /* GPIO1 as IRQ */
73444723
BL		 3172 regmap_update_bits(rt5663->regmap, RT5663_GPIO_1, RT5663_GP1_PIN_MASK,
3173 RT5663_GP1_PIN_IRQ);
df7c5216
BL		 3174 /* 4btn inline command debounce */
3175 regmap_update_bits(rt5663->regmap, RT5663_IL_CMD_5,
73444723 3176 RT5663_4BTN_CLK_DEB_MASK, RT5663_4BTN_CLK_DEB_65MS);
df7c5216 3177
73444723
BL		 3178 switch (rt5663->codec_ver) {
3179 case CODEC_VER_1:
df7c5216
BL		 3180 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402);
3181 /* JD1 */
3182 regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK,
73444723
BL		 3183 RT5663_IRQ_POW_SAV_MASK | RT5663_IRQ_POW_SAV_JD1_MASK,
3184 RT5663_IRQ_POW_SAV_EN | RT5663_IRQ_POW_SAV_JD1_EN);
df7c5216 3185 regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_2,
73444723 3186 RT5663_PWR_JD1_MASK, RT5663_PWR_JD1);
df7c5216 3187 regmap_update_bits(rt5663->regmap, RT5663_IRQ_1,
73444723 3188 RT5663_EN_CB_JD_MASK, RT5663_EN_CB_JD_EN);
df7c5216
BL		 3189
3190 regmap_update_bits(rt5663->regmap, RT5663_HP_LOGIC_2,
73444723 3191 RT5663_HP_SIG_SRC1_MASK, RT5663_HP_SIG_SRC1_REG);
df7c5216 3192 regmap_update_bits(rt5663->regmap, RT5663_RECMIX,
73444723
BL		 3193 RT5663_VREF_BIAS_MASK | RT5663_CBJ_DET_MASK |
3194 RT5663_DET_TYPE_MASK, RT5663_VREF_BIAS_REG |
3195 RT5663_CBJ_DET_EN | RT5663_DET_TYPE_QFN);
df7c5216
BL		 3196 /* Set GPIO4 and GPIO8 as input for combo jack */
3197 regmap_update_bits(rt5663->regmap, RT5663_GPIO_2,
73444723
BL		 3198 RT5663_GP4_PIN_CONF_MASK, RT5663_GP4_PIN_CONF_INPUT);
3199 regmap_update_bits(rt5663->regmap, RT5663_GPIO_3,
3200 RT5663_GP8_PIN_CONF_MASK, RT5663_GP8_PIN_CONF_INPUT);
df7c5216 3201 regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_1,
73444723
BL		 3202 RT5663_LDO1_DVO_MASK | RT5663_AMP_HP_MASK,
3203 RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X);
df7c5216 3204 break;
73444723 3205 case CODEC_VER_0:
7e7e76bd 3206 regmap_update_bits(rt5663->regmap, RT5663_DIG_MISC,
73444723 3207 RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN);
7e7e76bd 3208 regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK,
af2728e4 3209 RT5663_IRQ_MANUAL_MASK, RT5663_IRQ_MANUAL_EN);
7e7e76bd
JY		 3210 regmap_update_bits(rt5663->regmap, RT5663_IRQ_1,
3211 RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN);
3212 regmap_update_bits(rt5663->regmap, RT5663_GPIO_1,
3213 RT5663_GPIO1_TYPE_MASK, RT5663_GPIO1_TYPE_EN);
df7c5216
BL		 3214 regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032);
3215 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa2be);
3216 msleep(20);
3217 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf2be);
3218 regmap_update_bits(rt5663->regmap, RT5663_GPIO_2,
7e7e76bd
JY		 3219 RT5663_GP1_PIN_CONF_MASK | RT5663_SEL_GPIO1_MASK,
3220 RT5663_GP1_PIN_CONF_OUTPUT | RT5663_SEL_GPIO1_EN);
df7c5216
BL		 3221 /* DACREF LDO control */
3222 regmap_update_bits(rt5663->regmap, RT5663_DACREF_LDO, 0x3e0e,
3223 0x3a0a);
3224 regmap_update_bits(rt5663->regmap, RT5663_RECMIX,
3225 RT5663_RECMIX1_BST1_MASK, RT5663_RECMIX1_BST1_ON);
3226 regmap_update_bits(rt5663->regmap, RT5663_TDM_2,
3227 RT5663_DATA_SWAP_ADCDAT1_MASK,
3228 RT5663_DATA_SWAP_ADCDAT1_LL);
3229 break;
3230 default:
3231 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3232 }
3233
3234 INIT_DELAYED_WORK(&rt5663->jack_detect_work, rt5663_jack_detect_work);
3235
3236 if (i2c->irq) {
3237 ret = request_irq(i2c->irq, rt5663_irq,
3238 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
3239 | IRQF_ONESHOT, "rt5663", rt5663);
3240 if (ret)
3241 dev_err(&i2c->dev, "%s Failed to reguest IRQ: %d\n",
3242 __func__, ret);
3243 }
3244
3245 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5663,
3246 rt5663_dai, ARRAY_SIZE(rt5663_dai));
3247
3248 if (ret) {
3249 if (i2c->irq)
3250 free_irq(i2c->irq, rt5663);
3251 }
3252
3253 return ret;
3254}
3255
3256static int rt5663_i2c_remove(struct i2c_client *i2c)
3257{
3258 struct rt5663_priv *rt5663 = i2c_get_clientdata(i2c);
3259
3260 if (i2c->irq)
3261 free_irq(i2c->irq, rt5663);
3262
3263 snd_soc_unregister_codec(&i2c->dev);
3264
3265 return 0;
3266}
3267
66d7c262 3268static void rt5663_i2c_shutdown(struct i2c_client *client)
df7c5216
BL		 3269{
3270 struct rt5663_priv *rt5663 = i2c_get_clientdata(client);
3271
3272 regmap_write(rt5663->regmap, RT5663_RESET, 0);
3273}
3274
66d7c262 3275static struct i2c_driver rt5663_i2c_driver = {
df7c5216
BL		 3276 .driver = {
3277 .name = "rt5663",
df7c5216
BL		 3278 .acpi_match_table = ACPI_PTR(rt5663_acpi_match),
3279 .of_match_table = of_match_ptr(rt5663_of_match),
3280 },
3281 .probe = rt5663_i2c_probe,
3282 .remove = rt5663_i2c_remove,
3283 .shutdown = rt5663_i2c_shutdown,
3284 .id_table = rt5663_i2c_id,
3285};
3286module_i2c_driver(rt5663_i2c_driver);
3287
3288MODULE_DESCRIPTION("ASoC RT5663 driver");
3289MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
3290MODULE_LICENSE("GPL v2");
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