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UBUNTU: Ubuntu-4.15.0-96.97
[mirror_ubuntu-bionic-kernel.git] / sound / soc / codecs / rt5670.c
CommitLineData
5e8351de
BL		 1/*
2 * rt5670.c -- RT5670 ALSA SoC audio codec driver
3 *
4 * Copyright 2014 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
64e89e5f 17#include <linux/pm_runtime.h>
5e8351de
BL		 18#include <linux/i2c.h>
19#include <linux/platform_device.h>
0605815e 20#include <linux/acpi.h>
5e8351de 21#include <linux/spi/spi.h>
223c055a 22#include <linux/dmi.h>
5e8351de
BL		 23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/jack.h>
27#include <sound/soc.h>
28#include <sound/soc-dapm.h>
29#include <sound/initval.h>
30#include <sound/tlv.h>
31#include <sound/rt5670.h>
32
33#include "rl6231.h"
34#include "rt5670.h"
35#include "rt5670-dsp.h"
36
8e1b1785
PLB		 37#define RT5670_DEV_GPIO BIT(0)
38#define RT5670_IN2_DIFF BIT(1)
39#define RT5670_DMIC_EN BIT(2)
40#define RT5670_DMIC1_IN2P BIT(3)
41#define RT5670_DMIC1_GPIO6 BIT(4)
42#define RT5670_DMIC1_GPIO7 BIT(5)
43#define RT5670_DMIC2_INR BIT(6)
44#define RT5670_DMIC2_GPIO8 BIT(7)
45#define RT5670_DMIC3_GPIO5 BIT(8)
46#define RT5670_JD_MODE1 BIT(9)
47#define RT5670_JD_MODE2 BIT(10)
48#define RT5670_JD_MODE3 BIT(11)
49
50static unsigned long rt5670_quirk;
51static unsigned int quirk_override;
52module_param_named(quirk, quirk_override, uint, 0444);
53MODULE_PARM_DESC(quirk, "Board-specific quirk override");
54
5e8351de
BL		 55#define RT5670_DEVICE_ID 0x6271
56
57#define RT5670_PR_RANGE_BASE (0xff + 1)
58#define RT5670_PR_SPACING 0x100
59
60#define RT5670_PR_BASE (RT5670_PR_RANGE_BASE + (0 * RT5670_PR_SPACING))
61
62static const struct regmap_range_cfg rt5670_ranges[] = {
63 { .name = "PR", .range_min = RT5670_PR_BASE,
64 .range_max = RT5670_PR_BASE + 0xf8,
65 .selector_reg = RT5670_PRIV_INDEX,
66 .selector_mask = 0xff,
67 .selector_shift = 0x0,
68 .window_start = RT5670_PRIV_DATA,
69 .window_len = 0x1, },
70};
71
8019ff6c 72static const struct reg_sequence init_list[] = {
5e8351de
BL		 73 { RT5670_PR_BASE + 0x14, 0x9a8a },
74 { RT5670_PR_BASE + 0x38, 0x3ba1 },
75 { RT5670_PR_BASE + 0x3d, 0x3640 },
874352a7 76 { 0x8a, 0x0123 },
5e8351de 77};
5e8351de
BL		 78
79static const struct reg_default rt5670_reg[] = {
80 { 0x00, 0x0000 },
81 { 0x02, 0x8888 },
82 { 0x03, 0x8888 },
83 { 0x0a, 0x0001 },
84 { 0x0b, 0x0827 },
85 { 0x0c, 0x0000 },
86 { 0x0d, 0x0008 },
87 { 0x0e, 0x0000 },
88 { 0x0f, 0x0808 },
89 { 0x19, 0xafaf },
90 { 0x1a, 0xafaf },
91 { 0x1b, 0x0011 },
92 { 0x1c, 0x2f2f },
93 { 0x1d, 0x2f2f },
94 { 0x1e, 0x0000 },
95 { 0x1f, 0x2f2f },
96 { 0x20, 0x0000 },
97 { 0x26, 0x7860 },
98 { 0x27, 0x7860 },
99 { 0x28, 0x7871 },
100 { 0x29, 0x8080 },
101 { 0x2a, 0x5656 },
102 { 0x2b, 0x5454 },
103 { 0x2c, 0xaaa0 },
104 { 0x2d, 0x0000 },
105 { 0x2e, 0x2f2f },
106 { 0x2f, 0x1002 },
107 { 0x30, 0x0000 },
108 { 0x31, 0x5f00 },
109 { 0x32, 0x0000 },
110 { 0x33, 0x0000 },
111 { 0x34, 0x0000 },
112 { 0x35, 0x0000 },
113 { 0x36, 0x0000 },
114 { 0x37, 0x0000 },
115 { 0x38, 0x0000 },
116 { 0x3b, 0x0000 },
117 { 0x3c, 0x007f },
118 { 0x3d, 0x0000 },
119 { 0x3e, 0x007f },
120 { 0x45, 0xe00f },
121 { 0x4c, 0x5380 },
122 { 0x4f, 0x0073 },
123 { 0x52, 0x00d3 },
ac87f221 124 { 0x53, 0xf000 },
5e8351de
BL		 125 { 0x61, 0x0000 },
126 { 0x62, 0x0001 },
127 { 0x63, 0x00c3 },
128 { 0x64, 0x0000 },
ac87f221 129 { 0x65, 0x0001 },
5e8351de
BL		 130 { 0x66, 0x0000 },
131 { 0x6f, 0x8000 },
132 { 0x70, 0x8000 },
133 { 0x71, 0x8000 },
134 { 0x72, 0x8000 },
ac87f221 135 { 0x73, 0x7770 },
5e8351de
BL		 136 { 0x74, 0x0e00 },
137 { 0x75, 0x1505 },
138 { 0x76, 0x0015 },
139 { 0x77, 0x0c00 },
140 { 0x78, 0x4000 },
141 { 0x79, 0x0123 },
142 { 0x7f, 0x1100 },
143 { 0x80, 0x0000 },
144 { 0x81, 0x0000 },
145 { 0x82, 0x0000 },
146 { 0x83, 0x0000 },
147 { 0x84, 0x0000 },
148 { 0x85, 0x0000 },
ac87f221 149 { 0x86, 0x0004 },
5e8351de
BL		 150 { 0x87, 0x0000 },
151 { 0x88, 0x0000 },
152 { 0x89, 0x0000 },
874352a7 153 { 0x8a, 0x0123 },
5e8351de 154 { 0x8b, 0x0000 },
ac87f221 155 { 0x8c, 0x0003 },
5e8351de
BL		 156 { 0x8d, 0x0000 },
157 { 0x8e, 0x0004 },
158 { 0x8f, 0x1100 },
159 { 0x90, 0x0646 },
160 { 0x91, 0x0c06 },
161 { 0x93, 0x0000 },
ac87f221
BL		 162 { 0x94, 0x1270 },
163 { 0x95, 0x1000 },
5e8351de
BL		 164 { 0x97, 0x0000 },
165 { 0x98, 0x0000 },
166 { 0x99, 0x0000 },
167 { 0x9a, 0x2184 },
168 { 0x9b, 0x010a },
169 { 0x9c, 0x0aea },
170 { 0x9d, 0x000c },
171 { 0x9e, 0x0400 },
172 { 0xae, 0x7000 },
173 { 0xaf, 0x0000 },
ac87f221 174 { 0xb0, 0x7000 },
5e8351de
BL		 175 { 0xb1, 0x0000 },
176 { 0xb2, 0x0000 },
177 { 0xb3, 0x001f },
ac87f221 178 { 0xb4, 0x220c },
5e8351de
BL		 179 { 0xb5, 0x1f00 },
180 { 0xb6, 0x0000 },
181 { 0xb7, 0x0000 },
182 { 0xbb, 0x0000 },
183 { 0xbc, 0x0000 },
184 { 0xbd, 0x0000 },
185 { 0xbe, 0x0000 },
186 { 0xbf, 0x0000 },
187 { 0xc0, 0x0000 },
188 { 0xc1, 0x0000 },
189 { 0xc2, 0x0000 },
190 { 0xcd, 0x0000 },
191 { 0xce, 0x0000 },
192 { 0xcf, 0x1813 },
193 { 0xd0, 0x0690 },
194 { 0xd1, 0x1c17 },
ac87f221 195 { 0xd3, 0xa220 },
5e8351de
BL		 196 { 0xd4, 0x0000 },
197 { 0xd6, 0x0400 },
198 { 0xd9, 0x0809 },
199 { 0xda, 0x0000 },
200 { 0xdb, 0x0001 },
201 { 0xdc, 0x0049 },
ac87f221 202 { 0xdd, 0x0024 },
5e8351de
BL		 203 { 0xe6, 0x8000 },
204 { 0xe7, 0x0000 },
ac87f221 205 { 0xec, 0xa200 },
5e8351de 206 { 0xed, 0x0000 },
ac87f221 207 { 0xee, 0xa200 },
5e8351de
BL		 208 { 0xef, 0x0000 },
209 { 0xf8, 0x0000 },
210 { 0xf9, 0x0000 },
211 { 0xfa, 0x8010 },
212 { 0xfb, 0x0033 },
ac87f221 213 { 0xfc, 0x0100 },
5e8351de
BL		 214};
215
216static bool rt5670_volatile_register(struct device *dev, unsigned int reg)
217{
218 int i;
219
220 for (i = 0; i < ARRAY_SIZE(rt5670_ranges); i++) {
221 if ((reg >= rt5670_ranges[i].window_start &&
222 reg <= rt5670_ranges[i].window_start +
223 rt5670_ranges[i].window_len) ||
224 (reg >= rt5670_ranges[i].range_min &&
225 reg <= rt5670_ranges[i].range_max)) {
226 return true;
227 }
228 }
229
230 switch (reg) {
231 case RT5670_RESET:
232 case RT5670_PDM_DATA_CTRL1:
233 case RT5670_PDM1_DATA_CTRL4:
234 case RT5670_PDM2_DATA_CTRL4:
235 case RT5670_PRIV_DATA:
236 case RT5670_ASRC_5:
237 case RT5670_CJ_CTRL1:
238 case RT5670_CJ_CTRL2:
239 case RT5670_CJ_CTRL3:
240 case RT5670_A_JD_CTRL1:
241 case RT5670_A_JD_CTRL2:
242 case RT5670_VAD_CTRL5:
243 case RT5670_ADC_EQ_CTRL1:
244 case RT5670_EQ_CTRL1:
245 case RT5670_ALC_CTRL_1:
5e8351de
BL		 246 case RT5670_IRQ_CTRL2:
247 case RT5670_INT_IRQ_ST:
248 case RT5670_IL_CMD:
249 case RT5670_DSP_CTRL1:
250 case RT5670_DSP_CTRL2:
251 case RT5670_DSP_CTRL3:
252 case RT5670_DSP_CTRL4:
253 case RT5670_DSP_CTRL5:
254 case RT5670_VENDOR_ID:
255 case RT5670_VENDOR_ID1:
256 case RT5670_VENDOR_ID2:
257 return true;
258 default:
259 return false;
260 }
261}
262
263static bool rt5670_readable_register(struct device *dev, unsigned int reg)
264{
265 int i;
266
267 for (i = 0; i < ARRAY_SIZE(rt5670_ranges); i++) {
268 if ((reg >= rt5670_ranges[i].window_start &&
269 reg <= rt5670_ranges[i].window_start +
270 rt5670_ranges[i].window_len) ||
271 (reg >= rt5670_ranges[i].range_min &&
272 reg <= rt5670_ranges[i].range_max)) {
273 return true;
274 }
275 }
276
277 switch (reg) {
278 case RT5670_RESET:
279 case RT5670_HP_VOL:
280 case RT5670_LOUT1:
281 case RT5670_CJ_CTRL1:
282 case RT5670_CJ_CTRL2:
283 case RT5670_CJ_CTRL3:
284 case RT5670_IN2:
285 case RT5670_INL1_INR1_VOL:
286 case RT5670_DAC1_DIG_VOL:
287 case RT5670_DAC2_DIG_VOL:
288 case RT5670_DAC_CTRL:
289 case RT5670_STO1_ADC_DIG_VOL:
290 case RT5670_MONO_ADC_DIG_VOL:
291 case RT5670_STO2_ADC_DIG_VOL:
292 case RT5670_ADC_BST_VOL1:
293 case RT5670_ADC_BST_VOL2:
294 case RT5670_STO2_ADC_MIXER:
295 case RT5670_STO1_ADC_MIXER:
296 case RT5670_MONO_ADC_MIXER:
297 case RT5670_AD_DA_MIXER:
298 case RT5670_STO_DAC_MIXER:
299 case RT5670_DD_MIXER:
300 case RT5670_DIG_MIXER:
301 case RT5670_DSP_PATH1:
302 case RT5670_DSP_PATH2:
303 case RT5670_DIG_INF1_DATA:
304 case RT5670_DIG_INF2_DATA:
305 case RT5670_PDM_OUT_CTRL:
306 case RT5670_PDM_DATA_CTRL1:
307 case RT5670_PDM1_DATA_CTRL2:
308 case RT5670_PDM1_DATA_CTRL3:
309 case RT5670_PDM1_DATA_CTRL4:
310 case RT5670_PDM2_DATA_CTRL2:
311 case RT5670_PDM2_DATA_CTRL3:
312 case RT5670_PDM2_DATA_CTRL4:
313 case RT5670_REC_L1_MIXER:
314 case RT5670_REC_L2_MIXER:
315 case RT5670_REC_R1_MIXER:
316 case RT5670_REC_R2_MIXER:
317 case RT5670_HPO_MIXER:
318 case RT5670_MONO_MIXER:
319 case RT5670_OUT_L1_MIXER:
320 case RT5670_OUT_R1_MIXER:
321 case RT5670_LOUT_MIXER:
322 case RT5670_PWR_DIG1:
323 case RT5670_PWR_DIG2:
324 case RT5670_PWR_ANLG1:
325 case RT5670_PWR_ANLG2:
326 case RT5670_PWR_MIXER:
327 case RT5670_PWR_VOL:
328 case RT5670_PRIV_INDEX:
329 case RT5670_PRIV_DATA:
330 case RT5670_I2S4_SDP:
331 case RT5670_I2S1_SDP:
332 case RT5670_I2S2_SDP:
333 case RT5670_I2S3_SDP:
334 case RT5670_ADDA_CLK1:
335 case RT5670_ADDA_CLK2:
336 case RT5670_DMIC_CTRL1:
337 case RT5670_DMIC_CTRL2:
338 case RT5670_TDM_CTRL_1:
339 case RT5670_TDM_CTRL_2:
340 case RT5670_TDM_CTRL_3:
341 case RT5670_DSP_CLK:
342 case RT5670_GLB_CLK:
343 case RT5670_PLL_CTRL1:
344 case RT5670_PLL_CTRL2:
345 case RT5670_ASRC_1:
346 case RT5670_ASRC_2:
347 case RT5670_ASRC_3:
348 case RT5670_ASRC_4:
349 case RT5670_ASRC_5:
350 case RT5670_ASRC_7:
351 case RT5670_ASRC_8:
352 case RT5670_ASRC_9:
353 case RT5670_ASRC_10:
354 case RT5670_ASRC_11:
355 case RT5670_ASRC_12:
356 case RT5670_ASRC_13:
357 case RT5670_ASRC_14:
358 case RT5670_DEPOP_M1:
359 case RT5670_DEPOP_M2:
360 case RT5670_DEPOP_M3:
361 case RT5670_CHARGE_PUMP:
362 case RT5670_MICBIAS:
363 case RT5670_A_JD_CTRL1:
364 case RT5670_A_JD_CTRL2:
365 case RT5670_VAD_CTRL1:
366 case RT5670_VAD_CTRL2:
367 case RT5670_VAD_CTRL3:
368 case RT5670_VAD_CTRL4:
369 case RT5670_VAD_CTRL5:
370 case RT5670_ADC_EQ_CTRL1:
371 case RT5670_ADC_EQ_CTRL2:
372 case RT5670_EQ_CTRL1:
373 case RT5670_EQ_CTRL2:
374 case RT5670_ALC_DRC_CTRL1:
375 case RT5670_ALC_DRC_CTRL2:
376 case RT5670_ALC_CTRL_1:
377 case RT5670_ALC_CTRL_2:
378 case RT5670_ALC_CTRL_3:
379 case RT5670_JD_CTRL:
380 case RT5670_IRQ_CTRL1:
381 case RT5670_IRQ_CTRL2:
382 case RT5670_INT_IRQ_ST:
383 case RT5670_GPIO_CTRL1:
384 case RT5670_GPIO_CTRL2:
385 case RT5670_GPIO_CTRL3:
386 case RT5670_SCRABBLE_FUN:
387 case RT5670_SCRABBLE_CTRL:
388 case RT5670_BASE_BACK:
389 case RT5670_MP3_PLUS1:
390 case RT5670_MP3_PLUS2:
391 case RT5670_ADJ_HPF1:
392 case RT5670_ADJ_HPF2:
393 case RT5670_HP_CALIB_AMP_DET:
394 case RT5670_SV_ZCD1:
395 case RT5670_SV_ZCD2:
396 case RT5670_IL_CMD:
397 case RT5670_IL_CMD2:
398 case RT5670_IL_CMD3:
399 case RT5670_DRC_HL_CTRL1:
400 case RT5670_DRC_HL_CTRL2:
401 case RT5670_ADC_MONO_HP_CTRL1:
402 case RT5670_ADC_MONO_HP_CTRL2:
403 case RT5670_ADC_STO2_HP_CTRL1:
404 case RT5670_ADC_STO2_HP_CTRL2:
405 case RT5670_JD_CTRL3:
406 case RT5670_JD_CTRL4:
407 case RT5670_DIG_MISC:
408 case RT5670_DSP_CTRL1:
409 case RT5670_DSP_CTRL2:
410 case RT5670_DSP_CTRL3:
411 case RT5670_DSP_CTRL4:
412 case RT5670_DSP_CTRL5:
413 case RT5670_GEN_CTRL2:
414 case RT5670_GEN_CTRL3:
415 case RT5670_VENDOR_ID:
416 case RT5670_VENDOR_ID1:
417 case RT5670_VENDOR_ID2:
418 return true;
419 default:
420 return false;
421 }
422}
423
d3ef7054
BL		 424/**
425 * rt5670_headset_detect - Detect headset.
426 * @codec: SoC audio codec device.
427 * @jack_insert: Jack insert or not.
428 *
429 * Detect whether is headset or not when jack inserted.
430 *
431 * Returns detect status.
432 */
433
434static int rt5670_headset_detect(struct snd_soc_codec *codec, int jack_insert)
435{
436 int val;
6d8135ff 437 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
d3ef7054
BL		 438 struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
439
440 if (jack_insert) {
6d8135ff
LPC		 441 snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power");
442 snd_soc_dapm_sync(dapm);
d3ef7054
BL		 443 snd_soc_update_bits(codec, RT5670_GEN_CTRL3, 0x4, 0x0);
444 snd_soc_update_bits(codec, RT5670_CJ_CTRL2,
445 RT5670_CBJ_DET_MODE | RT5670_CBJ_MN_JD,
446 RT5670_CBJ_MN_JD);
447 snd_soc_write(codec, RT5670_GPIO_CTRL2, 0x0004);
448 snd_soc_update_bits(codec, RT5670_GPIO_CTRL1,
449 RT5670_GP1_PIN_MASK, RT5670_GP1_PIN_IRQ);
450 snd_soc_update_bits(codec, RT5670_CJ_CTRL1,
451 RT5670_CBJ_BST1_EN, RT5670_CBJ_BST1_EN);
452 snd_soc_write(codec, RT5670_JD_CTRL3, 0x00f0);
453 snd_soc_update_bits(codec, RT5670_CJ_CTRL2,
454 RT5670_CBJ_MN_JD, RT5670_CBJ_MN_JD);
455 snd_soc_update_bits(codec, RT5670_CJ_CTRL2,
456 RT5670_CBJ_MN_JD, 0);
457 msleep(300);
458 val = snd_soc_read(codec, RT5670_CJ_CTRL3) & 0x7;
459 if (val == 0x1 || val == 0x2) {
460 rt5670->jack_type = SND_JACK_HEADSET;
461 /* for push button */
462 snd_soc_update_bits(codec, RT5670_INT_IRQ_ST, 0x8, 0x8);
463 snd_soc_update_bits(codec, RT5670_IL_CMD, 0x40, 0x40);
464 snd_soc_read(codec, RT5670_IL_CMD);
465 } else {
466 snd_soc_update_bits(codec, RT5670_GEN_CTRL3, 0x4, 0x4);
467 rt5670->jack_type = SND_JACK_HEADPHONE;
6d8135ff
LPC		 468 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
469 snd_soc_dapm_sync(dapm);
d3ef7054
BL		 470 }
471 } else {
472 snd_soc_update_bits(codec, RT5670_INT_IRQ_ST, 0x8, 0x0);
473 snd_soc_update_bits(codec, RT5670_GEN_CTRL3, 0x4, 0x4);
474 rt5670->jack_type = 0;
6d8135ff
LPC		 475 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
476 snd_soc_dapm_sync(dapm);
d3ef7054
BL		 477 }
478
479 return rt5670->jack_type;
480}
481
cc3c340d
BL		 482void rt5670_jack_suspend(struct snd_soc_codec *codec)
483{
484 struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
485
486 rt5670->jack_type_saved = rt5670->jack_type;
487 rt5670_headset_detect(codec, 0);
488}
489EXPORT_SYMBOL_GPL(rt5670_jack_suspend);
490
491void rt5670_jack_resume(struct snd_soc_codec *codec)
492{
493 struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
494
495 if (rt5670->jack_type_saved)
496 rt5670_headset_detect(codec, 1);
497}
498EXPORT_SYMBOL_GPL(rt5670_jack_resume);
499
d3ef7054
BL		 500static int rt5670_button_detect(struct snd_soc_codec *codec)
501{
502 int btn_type, val;
503
504 val = snd_soc_read(codec, RT5670_IL_CMD);
505 btn_type = val & 0xff80;
506 snd_soc_write(codec, RT5670_IL_CMD, val);
507 if (btn_type != 0) {
508 msleep(20);
509 val = snd_soc_read(codec, RT5670_IL_CMD);
510 snd_soc_write(codec, RT5670_IL_CMD, val);
511 }
512
513 return btn_type;
514}
515
516static int rt5670_irq_detection(void *data)
517{
518 struct rt5670_priv *rt5670 = (struct rt5670_priv *)data;
519 struct snd_soc_jack_gpio *gpio = &rt5670->hp_gpio;
520 struct snd_soc_jack *jack = rt5670->jack;
521 int val, btn_type, report = jack->status;
522
523 if (rt5670->pdata.jd_mode == 1) /* 2 port */
524 val = snd_soc_read(rt5670->codec, RT5670_A_JD_CTRL1) & 0x0070;
525 else
526 val = snd_soc_read(rt5670->codec, RT5670_A_JD_CTRL1) & 0x0020;
527
528 switch (val) {
529 /* jack in */
530 case 0x30: /* 2 port */
531 case 0x0: /* 1 port or 2 port */
532 if (rt5670->jack_type == 0) {
533 report = rt5670_headset_detect(rt5670->codec, 1);
534 /* for push button and jack out */
535 gpio->debounce_time = 25;
536 break;
537 }
538 btn_type = 0;
539 if (snd_soc_read(rt5670->codec, RT5670_INT_IRQ_ST) & 0x4) {
540 /* button pressed */
541 report = SND_JACK_HEADSET;
542 btn_type = rt5670_button_detect(rt5670->codec);
543 switch (btn_type) {
544 case 0x2000: /* up */
545 report |= SND_JACK_BTN_1;
546 break;
547 case 0x0400: /* center */
548 report |= SND_JACK_BTN_0;
549 break;
550 case 0x0080: /* down */
551 report |= SND_JACK_BTN_2;
552 break;
553 default:
554 dev_err(rt5670->codec->dev,
555 "Unexpected button code 0x%04x\n",
556 btn_type);
557 break;
558 }
559 }
560 if (btn_type == 0)/* button release */
561 report = rt5670->jack_type;
562
563 break;
564 /* jack out */
565 case 0x70: /* 2 port */
566 case 0x10: /* 2 port */
567 case 0x20: /* 1 port */
568 report = 0;
569 snd_soc_update_bits(rt5670->codec, RT5670_INT_IRQ_ST, 0x1, 0x0);
570 rt5670_headset_detect(rt5670->codec, 0);
571 gpio->debounce_time = 150; /* for jack in */
572 break;
573 default:
574 break;
575 }
576
577 return report;
578}
579
580int rt5670_set_jack_detect(struct snd_soc_codec *codec,
581 struct snd_soc_jack *jack)
582{
583 struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
584 int ret;
585
586 rt5670->jack = jack;
587 rt5670->hp_gpio.gpiod_dev = codec->dev;
804e73ad 588 rt5670->hp_gpio.name = "headset";
d3ef7054
BL		 589 rt5670->hp_gpio.report = SND_JACK_HEADSET |
590 SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2;
591 rt5670->hp_gpio.debounce_time = 150;
592 rt5670->hp_gpio.wake = true;
593 rt5670->hp_gpio.data = (struct rt5670_priv *)rt5670;
594 rt5670->hp_gpio.jack_status_check = rt5670_irq_detection;
595
596 ret = snd_soc_jack_add_gpios(rt5670->jack, 1,
597 &rt5670->hp_gpio);
598 if (ret) {
599 dev_err(codec->dev, "Adding jack GPIO failed\n");
600 return ret;
601 }
602
603 return 0;
604}
605EXPORT_SYMBOL_GPL(rt5670_set_jack_detect);
606
5e8351de
BL		 607static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
608static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
609static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
610static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
611static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
612
613/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
dea6d32e 614static const DECLARE_TLV_DB_RANGE(bst_tlv,
5e8351de
BL		 615 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
616 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
617 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
618 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
619 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
620 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
dea6d32e
LPC		 621 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
622);
5e8351de
BL		 623
624/* Interface data select */
625static const char * const rt5670_data_select[] = {
626 "Normal", "Swap", "left copy to right", "right copy to left"
627};
628
01957572 629static SOC_ENUM_SINGLE_DECL(rt5670_if2_dac_enum, RT5670_DIG_INF1_DATA,
5e8351de
BL		 630 RT5670_IF2_DAC_SEL_SFT, rt5670_data_select);
631
01957572 632static SOC_ENUM_SINGLE_DECL(rt5670_if2_adc_enum, RT5670_DIG_INF1_DATA,
5e8351de
BL		 633 RT5670_IF2_ADC_SEL_SFT, rt5670_data_select);
634
635static const struct snd_kcontrol_new rt5670_snd_controls[] = {
636 /* Headphone Output Volume */
637 SOC_DOUBLE("HP Playback Switch", RT5670_HP_VOL,
638 RT5670_L_MUTE_SFT, RT5670_R_MUTE_SFT, 1, 1),
639 SOC_DOUBLE_TLV("HP Playback Volume", RT5670_HP_VOL,
640 RT5670_L_VOL_SFT, RT5670_R_VOL_SFT,
e1f42a2f 641 39, 1, out_vol_tlv),
5e8351de
BL		 642 /* OUTPUT Control */
643 SOC_DOUBLE("OUT Channel Switch", RT5670_LOUT1,
644 RT5670_VOL_L_SFT, RT5670_VOL_R_SFT, 1, 1),
645 SOC_DOUBLE_TLV("OUT Playback Volume", RT5670_LOUT1,
646 RT5670_L_VOL_SFT, RT5670_R_VOL_SFT, 39, 1, out_vol_tlv),
647 /* DAC Digital Volume */
648 SOC_DOUBLE("DAC2 Playback Switch", RT5670_DAC_CTRL,
649 RT5670_M_DAC_L2_VOL_SFT, RT5670_M_DAC_R2_VOL_SFT, 1, 1),
650 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5670_DAC1_DIG_VOL,
651 RT5670_L_VOL_SFT, RT5670_R_VOL_SFT,
652 175, 0, dac_vol_tlv),
653 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5670_DAC2_DIG_VOL,
654 RT5670_L_VOL_SFT, RT5670_R_VOL_SFT,
655 175, 0, dac_vol_tlv),
656 /* IN1/IN2 Control */
657 SOC_SINGLE_TLV("IN1 Boost Volume", RT5670_CJ_CTRL1,
658 RT5670_BST_SFT1, 8, 0, bst_tlv),
659 SOC_SINGLE_TLV("IN2 Boost Volume", RT5670_IN2,
660 RT5670_BST_SFT1, 8, 0, bst_tlv),
661 /* INL/INR Volume Control */
662 SOC_DOUBLE_TLV("IN Capture Volume", RT5670_INL1_INR1_VOL,
663 RT5670_INL_VOL_SFT, RT5670_INR_VOL_SFT,
664 31, 1, in_vol_tlv),
665 /* ADC Digital Volume Control */
666 SOC_DOUBLE("ADC Capture Switch", RT5670_STO1_ADC_DIG_VOL,
667 RT5670_L_MUTE_SFT, RT5670_R_MUTE_SFT, 1, 1),
668 SOC_DOUBLE_TLV("ADC Capture Volume", RT5670_STO1_ADC_DIG_VOL,
669 RT5670_L_VOL_SFT, RT5670_R_VOL_SFT,
670 127, 0, adc_vol_tlv),
671
672 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5670_MONO_ADC_DIG_VOL,
673 RT5670_L_VOL_SFT, RT5670_R_VOL_SFT,
674 127, 0, adc_vol_tlv),
675
676 /* ADC Boost Volume Control */
677 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5670_ADC_BST_VOL1,
678 RT5670_STO1_ADC_L_BST_SFT, RT5670_STO1_ADC_R_BST_SFT,
679 3, 0, adc_bst_tlv),
680
681 SOC_DOUBLE_TLV("STO2 ADC Boost Gain Volume", RT5670_ADC_BST_VOL1,
682 RT5670_STO2_ADC_L_BST_SFT, RT5670_STO2_ADC_R_BST_SFT,
683 3, 0, adc_bst_tlv),
684
685 SOC_ENUM("ADC IF2 Data Switch", rt5670_if2_adc_enum),
686 SOC_ENUM("DAC IF2 Data Switch", rt5670_if2_dac_enum),
687};
688
689/**
690 * set_dmic_clk - Set parameter of dmic.
691 *
692 * @w: DAPM widget.
693 * @kcontrol: The kcontrol of this widget.
694 * @event: Event id.
695 *
696 * Choose dmic clock between 1MHz and 3MHz.
697 * It is better for clock to approximate 3MHz.
698 */
699static int set_dmic_clk(struct snd_soc_dapm_widget *w,
700 struct snd_kcontrol *kcontrol, int event)
701{
8eee1468 702 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
5e8351de 703 struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
00a6d6e5 704 int idx, rate;
5e8351de 705
00a6d6e5
OC		 706 rate = rt5670->sysclk / rl6231_get_pre_div(rt5670->regmap,
707 RT5670_ADDA_CLK1, RT5670_I2S_PD1_SFT);
708 idx = rl6231_calc_dmic_clk(rate);
5e8351de
BL		 709 if (idx < 0)
710 dev_err(codec->dev, "Failed to set DMIC clock\n");
711 else
712 snd_soc_update_bits(codec, RT5670_DMIC_CTRL1,
713 RT5670_DMIC_CLK_MASK, idx << RT5670_DMIC_CLK_SFT);
714 return idx;
715}
716
717static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
718 struct snd_soc_dapm_widget *sink)
719{
66454b3e 720 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
485372dc 721 struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
5e8351de 722
485372dc 723 if (rt5670->sysclk_src == RT5670_SCLK_S_PLL1)
5e8351de
BL		 724 return 1;
725 else
726 return 0;
727}
728
729static int is_using_asrc(struct snd_soc_dapm_widget *source,
730 struct snd_soc_dapm_widget *sink)
731{
8eee1468 732 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
5e8351de
BL		 733 unsigned int reg, shift, val;
734
735 switch (source->shift) {
736 case 0:
737 reg = RT5670_ASRC_3;
738 shift = 0;
739 break;
740 case 1:
741 reg = RT5670_ASRC_3;
742 shift = 4;
743 break;
744 case 2:
745 reg = RT5670_ASRC_5;
746 shift = 12;
747 break;
748 case 3:
749 reg = RT5670_ASRC_2;
750 shift = 0;
751 break;
752 case 8:
753 reg = RT5670_ASRC_2;
754 shift = 4;
755 break;
756 case 9:
757 reg = RT5670_ASRC_2;
758 shift = 8;
759 break;
760 case 10:
761 reg = RT5670_ASRC_2;
762 shift = 12;
763 break;
764 default:
765 return 0;
766 }
767
8eee1468 768 val = (snd_soc_read(codec, reg) >> shift) & 0xf;
5e8351de
BL		 769 switch (val) {
770 case 1:
771 case 2:
772 case 3:
773 case 4:
774 return 1;
775 default:
776 return 0;
777 }
778
779}
780
e50334d4
BL		 781static int can_use_asrc(struct snd_soc_dapm_widget *source,
782 struct snd_soc_dapm_widget *sink)
783{
784 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
785 struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
786
787 if (rt5670->sysclk > rt5670->lrck[RT5670_AIF1] * 384)
788 return 1;
789
790 return 0;
791}
792
ea232b3f
ML		 793
794/**
795 * rt5670_sel_asrc_clk_src - select ASRC clock source for a set of filters
796 * @codec: SoC audio codec device.
797 * @filter_mask: mask of filters.
798 * @clk_src: clock source
799 *
800 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5670 can
801 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
802 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
803 * ASRC function will track i2s clock and generate a corresponding system clock
804 * for codec. This function provides an API to select the clock source for a
805 * set of filters specified by the mask. And the codec driver will turn on ASRC
806 * for these filters if ASRC is selected as their clock source.
807 */
808int rt5670_sel_asrc_clk_src(struct snd_soc_codec *codec,
809 unsigned int filter_mask, unsigned int clk_src)
810{
811 unsigned int asrc2_mask = 0, asrc2_value = 0;
812 unsigned int asrc3_mask = 0, asrc3_value = 0;
813
814 if (clk_src > RT5670_CLK_SEL_SYS3)
815 return -EINVAL;
816
817 if (filter_mask & RT5670_DA_STEREO_FILTER) {
818 asrc2_mask |= RT5670_DA_STO_CLK_SEL_MASK;
819 asrc2_value = (asrc2_value & ~RT5670_DA_STO_CLK_SEL_MASK)
820 | (clk_src << RT5670_DA_STO_CLK_SEL_SFT);
821 }
822
823 if (filter_mask & RT5670_DA_MONO_L_FILTER) {
824 asrc2_mask |= RT5670_DA_MONOL_CLK_SEL_MASK;
825 asrc2_value = (asrc2_value & ~RT5670_DA_MONOL_CLK_SEL_MASK)
826 | (clk_src << RT5670_DA_MONOL_CLK_SEL_SFT);
827 }
828
829 if (filter_mask & RT5670_DA_MONO_R_FILTER) {
830 asrc2_mask |= RT5670_DA_MONOR_CLK_SEL_MASK;
831 asrc2_value = (asrc2_value & ~RT5670_DA_MONOR_CLK_SEL_MASK)
832 | (clk_src << RT5670_DA_MONOR_CLK_SEL_SFT);
833 }
834
835 if (filter_mask & RT5670_AD_STEREO_FILTER) {
836 asrc2_mask |= RT5670_AD_STO1_CLK_SEL_MASK;
837 asrc2_value = (asrc2_value & ~RT5670_AD_STO1_CLK_SEL_MASK)
838 | (clk_src << RT5670_AD_STO1_CLK_SEL_SFT);
839 }
840
841 if (filter_mask & RT5670_AD_MONO_L_FILTER) {
842 asrc3_mask |= RT5670_AD_MONOL_CLK_SEL_MASK;
843 asrc3_value = (asrc3_value & ~RT5670_AD_MONOL_CLK_SEL_MASK)
844 | (clk_src << RT5670_AD_MONOL_CLK_SEL_SFT);
845 }
846
847 if (filter_mask & RT5670_AD_MONO_R_FILTER) {
848 asrc3_mask |= RT5670_AD_MONOR_CLK_SEL_MASK;
849 asrc3_value = (asrc3_value & ~RT5670_AD_MONOR_CLK_SEL_MASK)
850 | (clk_src << RT5670_AD_MONOR_CLK_SEL_SFT);
851 }
852
853 if (filter_mask & RT5670_UP_RATE_FILTER) {
854 asrc3_mask |= RT5670_UP_CLK_SEL_MASK;
855 asrc3_value = (asrc3_value & ~RT5670_UP_CLK_SEL_MASK)
856 | (clk_src << RT5670_UP_CLK_SEL_SFT);
857 }
858
859 if (filter_mask & RT5670_DOWN_RATE_FILTER) {
860 asrc3_mask |= RT5670_DOWN_CLK_SEL_MASK;
861 asrc3_value = (asrc3_value & ~RT5670_DOWN_CLK_SEL_MASK)
862 | (clk_src << RT5670_DOWN_CLK_SEL_SFT);
863 }
864
865 if (asrc2_mask)
866 snd_soc_update_bits(codec, RT5670_ASRC_2,
867 asrc2_mask, asrc2_value);
868
869 if (asrc3_mask)
870 snd_soc_update_bits(codec, RT5670_ASRC_3,
871 asrc3_mask, asrc3_value);
872 return 0;
873}
874EXPORT_SYMBOL_GPL(rt5670_sel_asrc_clk_src);
875
5e8351de
BL		 876/* Digital Mixer */
877static const struct snd_kcontrol_new rt5670_sto1_adc_l_mix[] = {
878 SOC_DAPM_SINGLE("ADC1 Switch", RT5670_STO1_ADC_MIXER,
879 RT5670_M_ADC_L1_SFT, 1, 1),
880 SOC_DAPM_SINGLE("ADC2 Switch", RT5670_STO1_ADC_MIXER,
881 RT5670_M_ADC_L2_SFT, 1, 1),
882};
883
884static const struct snd_kcontrol_new rt5670_sto1_adc_r_mix[] = {
885 SOC_DAPM_SINGLE("ADC1 Switch", RT5670_STO1_ADC_MIXER,
886 RT5670_M_ADC_R1_SFT, 1, 1),
887 SOC_DAPM_SINGLE("ADC2 Switch", RT5670_STO1_ADC_MIXER,
888 RT5670_M_ADC_R2_SFT, 1, 1),
889};
890
891static const struct snd_kcontrol_new rt5670_sto2_adc_l_mix[] = {
892 SOC_DAPM_SINGLE("ADC1 Switch", RT5670_STO2_ADC_MIXER,
893 RT5670_M_ADC_L1_SFT, 1, 1),
894 SOC_DAPM_SINGLE("ADC2 Switch", RT5670_STO2_ADC_MIXER,
895 RT5670_M_ADC_L2_SFT, 1, 1),
896};
897
898static const struct snd_kcontrol_new rt5670_sto2_adc_r_mix[] = {
899 SOC_DAPM_SINGLE("ADC1 Switch", RT5670_STO2_ADC_MIXER,
900 RT5670_M_ADC_R1_SFT, 1, 1),
901 SOC_DAPM_SINGLE("ADC2 Switch", RT5670_STO2_ADC_MIXER,
902 RT5670_M_ADC_R2_SFT, 1, 1),
903};
904
905static const struct snd_kcontrol_new rt5670_mono_adc_l_mix[] = {
906 SOC_DAPM_SINGLE("ADC1 Switch", RT5670_MONO_ADC_MIXER,
907 RT5670_M_MONO_ADC_L1_SFT, 1, 1),
908 SOC_DAPM_SINGLE("ADC2 Switch", RT5670_MONO_ADC_MIXER,
909 RT5670_M_MONO_ADC_L2_SFT, 1, 1),
910};
911
912static const struct snd_kcontrol_new rt5670_mono_adc_r_mix[] = {
913 SOC_DAPM_SINGLE("ADC1 Switch", RT5670_MONO_ADC_MIXER,
914 RT5670_M_MONO_ADC_R1_SFT, 1, 1),
915 SOC_DAPM_SINGLE("ADC2 Switch", RT5670_MONO_ADC_MIXER,
916 RT5670_M_MONO_ADC_R2_SFT, 1, 1),
917};
918
919static const struct snd_kcontrol_new rt5670_dac_l_mix[] = {
920 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5670_AD_DA_MIXER,
921 RT5670_M_ADCMIX_L_SFT, 1, 1),
922 SOC_DAPM_SINGLE("DAC1 Switch", RT5670_AD_DA_MIXER,
923 RT5670_M_DAC1_L_SFT, 1, 1),
924};
925
926static const struct snd_kcontrol_new rt5670_dac_r_mix[] = {
927 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5670_AD_DA_MIXER,
928 RT5670_M_ADCMIX_R_SFT, 1, 1),
929 SOC_DAPM_SINGLE("DAC1 Switch", RT5670_AD_DA_MIXER,
930 RT5670_M_DAC1_R_SFT, 1, 1),
931};
932
933static const struct snd_kcontrol_new rt5670_sto_dac_l_mix[] = {
934 SOC_DAPM_SINGLE("DAC L1 Switch", RT5670_STO_DAC_MIXER,
935 RT5670_M_DAC_L1_SFT, 1, 1),
936 SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_STO_DAC_MIXER,
937 RT5670_M_DAC_L2_SFT, 1, 1),
938 SOC_DAPM_SINGLE("DAC R1 Switch", RT5670_STO_DAC_MIXER,
939 RT5670_M_DAC_R1_STO_L_SFT, 1, 1),
940};
941
942static const struct snd_kcontrol_new rt5670_sto_dac_r_mix[] = {
943 SOC_DAPM_SINGLE("DAC R1 Switch", RT5670_STO_DAC_MIXER,
944 RT5670_M_DAC_R1_SFT, 1, 1),
945 SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_STO_DAC_MIXER,
946 RT5670_M_DAC_R2_SFT, 1, 1),
947 SOC_DAPM_SINGLE("DAC L1 Switch", RT5670_STO_DAC_MIXER,
948 RT5670_M_DAC_L1_STO_R_SFT, 1, 1),
949};
950
951static const struct snd_kcontrol_new rt5670_mono_dac_l_mix[] = {
952 SOC_DAPM_SINGLE("DAC L1 Switch", RT5670_DD_MIXER,
953 RT5670_M_DAC_L1_MONO_L_SFT, 1, 1),
954 SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_DD_MIXER,
955 RT5670_M_DAC_L2_MONO_L_SFT, 1, 1),
956 SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_DD_MIXER,
957 RT5670_M_DAC_R2_MONO_L_SFT, 1, 1),
958};
959
960static const struct snd_kcontrol_new rt5670_mono_dac_r_mix[] = {
961 SOC_DAPM_SINGLE("DAC R1 Switch", RT5670_DD_MIXER,
962 RT5670_M_DAC_R1_MONO_R_SFT, 1, 1),
963 SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_DD_MIXER,
964 RT5670_M_DAC_R2_MONO_R_SFT, 1, 1),
965 SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_DD_MIXER,
966 RT5670_M_DAC_L2_MONO_R_SFT, 1, 1),
967};
968
969static const struct snd_kcontrol_new rt5670_dig_l_mix[] = {
970 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5670_DIG_MIXER,
971 RT5670_M_STO_L_DAC_L_SFT, 1, 1),
972 SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_DIG_MIXER,
973 RT5670_M_DAC_L2_DAC_L_SFT, 1, 1),
974 SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_DIG_MIXER,
975 RT5670_M_DAC_R2_DAC_L_SFT, 1, 1),
976};
977
978static const struct snd_kcontrol_new rt5670_dig_r_mix[] = {
979 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5670_DIG_MIXER,
980 RT5670_M_STO_R_DAC_R_SFT, 1, 1),
981 SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_DIG_MIXER,
982 RT5670_M_DAC_R2_DAC_R_SFT, 1, 1),
983 SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_DIG_MIXER,
984 RT5670_M_DAC_L2_DAC_R_SFT, 1, 1),
985};
986
987/* Analog Input Mixer */
988static const struct snd_kcontrol_new rt5670_rec_l_mix[] = {
989 SOC_DAPM_SINGLE("INL Switch", RT5670_REC_L2_MIXER,
990 RT5670_M_IN_L_RM_L_SFT, 1, 1),
991 SOC_DAPM_SINGLE("BST2 Switch", RT5670_REC_L2_MIXER,
992 RT5670_M_BST2_RM_L_SFT, 1, 1),
993 SOC_DAPM_SINGLE("BST1 Switch", RT5670_REC_L2_MIXER,
994 RT5670_M_BST1_RM_L_SFT, 1, 1),
995};
996
997static const struct snd_kcontrol_new rt5670_rec_r_mix[] = {
998 SOC_DAPM_SINGLE("INR Switch", RT5670_REC_R2_MIXER,
999 RT5670_M_IN_R_RM_R_SFT, 1, 1),
1000 SOC_DAPM_SINGLE("BST2 Switch", RT5670_REC_R2_MIXER,
1001 RT5670_M_BST2_RM_R_SFT, 1, 1),
1002 SOC_DAPM_SINGLE("BST1 Switch", RT5670_REC_R2_MIXER,
1003 RT5670_M_BST1_RM_R_SFT, 1, 1),
1004};
1005
1006static const struct snd_kcontrol_new rt5670_out_l_mix[] = {
1007 SOC_DAPM_SINGLE("BST1 Switch", RT5670_OUT_L1_MIXER,
1008 RT5670_M_BST1_OM_L_SFT, 1, 1),
1009 SOC_DAPM_SINGLE("INL Switch", RT5670_OUT_L1_MIXER,
1010 RT5670_M_IN_L_OM_L_SFT, 1, 1),
1011 SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_OUT_L1_MIXER,
1012 RT5670_M_DAC_L2_OM_L_SFT, 1, 1),
1013 SOC_DAPM_SINGLE("DAC L1 Switch", RT5670_OUT_L1_MIXER,
1014 RT5670_M_DAC_L1_OM_L_SFT, 1, 1),
1015};
1016
1017static const struct snd_kcontrol_new rt5670_out_r_mix[] = {
1018 SOC_DAPM_SINGLE("BST2 Switch", RT5670_OUT_R1_MIXER,
1019 RT5670_M_BST2_OM_R_SFT, 1, 1),
1020 SOC_DAPM_SINGLE("INR Switch", RT5670_OUT_R1_MIXER,
1021 RT5670_M_IN_R_OM_R_SFT, 1, 1),
1022 SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_OUT_R1_MIXER,
1023 RT5670_M_DAC_R2_OM_R_SFT, 1, 1),
1024 SOC_DAPM_SINGLE("DAC R1 Switch", RT5670_OUT_R1_MIXER,
1025 RT5670_M_DAC_R1_OM_R_SFT, 1, 1),
1026};
1027
1028static const struct snd_kcontrol_new rt5670_hpo_mix[] = {
1029 SOC_DAPM_SINGLE("DAC1 Switch", RT5670_HPO_MIXER,
1030 RT5670_M_DAC1_HM_SFT, 1, 1),
1031 SOC_DAPM_SINGLE("HPVOL Switch", RT5670_HPO_MIXER,
1032 RT5670_M_HPVOL_HM_SFT, 1, 1),
1033};
1034
1035static const struct snd_kcontrol_new rt5670_hpvoll_mix[] = {
1036 SOC_DAPM_SINGLE("DAC1 Switch", RT5670_HPO_MIXER,
1037 RT5670_M_DACL1_HML_SFT, 1, 1),
1038 SOC_DAPM_SINGLE("INL Switch", RT5670_HPO_MIXER,
1039 RT5670_M_INL1_HML_SFT, 1, 1),
1040};
1041
1042static const struct snd_kcontrol_new rt5670_hpvolr_mix[] = {
1043 SOC_DAPM_SINGLE("DAC1 Switch", RT5670_HPO_MIXER,
1044 RT5670_M_DACR1_HMR_SFT, 1, 1),
1045 SOC_DAPM_SINGLE("INR Switch", RT5670_HPO_MIXER,
1046 RT5670_M_INR1_HMR_SFT, 1, 1),
1047};
1048
1049static const struct snd_kcontrol_new rt5670_lout_mix[] = {
1050 SOC_DAPM_SINGLE("DAC L1 Switch", RT5670_LOUT_MIXER,
1051 RT5670_M_DAC_L1_LM_SFT, 1, 1),
1052 SOC_DAPM_SINGLE("DAC R1 Switch", RT5670_LOUT_MIXER,
1053 RT5670_M_DAC_R1_LM_SFT, 1, 1),
1054 SOC_DAPM_SINGLE("OUTMIX L Switch", RT5670_LOUT_MIXER,
1055 RT5670_M_OV_L_LM_SFT, 1, 1),
1056 SOC_DAPM_SINGLE("OUTMIX R Switch", RT5670_LOUT_MIXER,
1057 RT5670_M_OV_R_LM_SFT, 1, 1),
1058};
1059
1060static const struct snd_kcontrol_new rt5670_hpl_mix[] = {
1061 SOC_DAPM_SINGLE("DAC L1 Switch", RT5670_HPO_MIXER,
1062 RT5670_M_DACL1_HML_SFT, 1, 1),
1063 SOC_DAPM_SINGLE("INL1 Switch", RT5670_HPO_MIXER,
1064 RT5670_M_INL1_HML_SFT, 1, 1),
1065};
1066
1067static const struct snd_kcontrol_new rt5670_hpr_mix[] = {
1068 SOC_DAPM_SINGLE("DAC R1 Switch", RT5670_HPO_MIXER,
1069 RT5670_M_DACR1_HMR_SFT, 1, 1),
1070 SOC_DAPM_SINGLE("INR1 Switch", RT5670_HPO_MIXER,
1071 RT5670_M_INR1_HMR_SFT, 1, 1),
1072};
1073
1074static const struct snd_kcontrol_new lout_l_enable_control =
1075 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5670_LOUT1,
1076 RT5670_L_MUTE_SFT, 1, 1);
1077
1078static const struct snd_kcontrol_new lout_r_enable_control =
1079 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5670_LOUT1,
1080 RT5670_R_MUTE_SFT, 1, 1);
1081
1082/* DAC1 L/R source */ /* MX-29 [9:8] [11:10] */
1083static const char * const rt5670_dac1_src[] = {
1084 "IF1 DAC", "IF2 DAC"
1085};
1086
01957572 1087static SOC_ENUM_SINGLE_DECL(rt5670_dac1l_enum, RT5670_AD_DA_MIXER,
5e8351de
BL		 1088 RT5670_DAC1_L_SEL_SFT, rt5670_dac1_src);
1089
1090static const struct snd_kcontrol_new rt5670_dac1l_mux =
1091 SOC_DAPM_ENUM("DAC1 L source", rt5670_dac1l_enum);
1092
01957572 1093static SOC_ENUM_SINGLE_DECL(rt5670_dac1r_enum, RT5670_AD_DA_MIXER,
5e8351de
BL		 1094 RT5670_DAC1_R_SEL_SFT, rt5670_dac1_src);
1095
1096static const struct snd_kcontrol_new rt5670_dac1r_mux =
1097 SOC_DAPM_ENUM("DAC1 R source", rt5670_dac1r_enum);
1098
1099/*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */
1100/* TODO Use SOC_VALUE_ENUM_SINGLE_DECL */
1101static const char * const rt5670_dac12_src[] = {
1102 "IF1 DAC", "IF2 DAC", "IF3 DAC", "TxDC DAC",
1103 "Bass", "VAD_ADC", "IF4 DAC"
1104};
1105
01957572 1106static SOC_ENUM_SINGLE_DECL(rt5670_dac2l_enum, RT5670_DAC_CTRL,
5e8351de
BL		 1107 RT5670_DAC2_L_SEL_SFT, rt5670_dac12_src);
1108
1109static const struct snd_kcontrol_new rt5670_dac_l2_mux =
1110 SOC_DAPM_ENUM("DAC2 L source", rt5670_dac2l_enum);
1111
1112static const char * const rt5670_dacr2_src[] = {
1113 "IF1 DAC", "IF2 DAC", "IF3 DAC", "TxDC DAC", "TxDP ADC", "IF4 DAC"
1114};
1115
01957572 1116static SOC_ENUM_SINGLE_DECL(rt5670_dac2r_enum, RT5670_DAC_CTRL,
5e8351de
BL		 1117 RT5670_DAC2_R_SEL_SFT, rt5670_dacr2_src);
1118
1119static const struct snd_kcontrol_new rt5670_dac_r2_mux =
1120 SOC_DAPM_ENUM("DAC2 R source", rt5670_dac2r_enum);
1121
1122/*RxDP source*/ /* MX-2D [15:13] */
1123static const char * const rt5670_rxdp_src[] = {
1124 "IF2 DAC", "IF1 DAC", "STO1 ADC Mixer", "STO2 ADC Mixer",
1125 "Mono ADC Mixer L", "Mono ADC Mixer R", "DAC1"
1126};
1127
01957572 1128static SOC_ENUM_SINGLE_DECL(rt5670_rxdp_enum, RT5670_DSP_PATH1,
5e8351de
BL		 1129 RT5670_RXDP_SEL_SFT, rt5670_rxdp_src);
1130
1131static const struct snd_kcontrol_new rt5670_rxdp_mux =
1132 SOC_DAPM_ENUM("DAC2 L source", rt5670_rxdp_enum);
1133
1134/* MX-2D [1] [0] */
1135static const char * const rt5670_dsp_bypass_src[] = {
1136 "DSP", "Bypass"
1137};
1138
01957572 1139static SOC_ENUM_SINGLE_DECL(rt5670_dsp_ul_enum, RT5670_DSP_PATH1,
5e8351de
BL		 1140 RT5670_DSP_UL_SFT, rt5670_dsp_bypass_src);
1141
1142static const struct snd_kcontrol_new rt5670_dsp_ul_mux =
1143 SOC_DAPM_ENUM("DSP UL source", rt5670_dsp_ul_enum);
1144
01957572 1145static SOC_ENUM_SINGLE_DECL(rt5670_dsp_dl_enum, RT5670_DSP_PATH1,
5e8351de
BL		 1146 RT5670_DSP_DL_SFT, rt5670_dsp_bypass_src);
1147
1148static const struct snd_kcontrol_new rt5670_dsp_dl_mux =
1149 SOC_DAPM_ENUM("DSP DL source", rt5670_dsp_dl_enum);
1150
1151/* Stereo2 ADC source */
1152/* MX-26 [15] */
1153static const char * const rt5670_stereo2_adc_lr_src[] = {
1154 "L", "LR"
1155};
1156
01957572 1157static SOC_ENUM_SINGLE_DECL(rt5670_stereo2_adc_lr_enum, RT5670_STO2_ADC_MIXER,
5e8351de
BL		 1158 RT5670_STO2_ADC_SRC_SFT, rt5670_stereo2_adc_lr_src);
1159
1160static const struct snd_kcontrol_new rt5670_sto2_adc_lr_mux =
1161 SOC_DAPM_ENUM("Stereo2 ADC LR source", rt5670_stereo2_adc_lr_enum);
1162
1163/* Stereo1 ADC source */
1164/* MX-27 MX-26 [12] */
1165static const char * const rt5670_stereo_adc1_src[] = {
1166 "DAC MIX", "ADC"
1167};
1168
01957572 1169static SOC_ENUM_SINGLE_DECL(rt5670_stereo1_adc1_enum, RT5670_STO1_ADC_MIXER,
5e8351de
BL		 1170 RT5670_ADC_1_SRC_SFT, rt5670_stereo_adc1_src);
1171
ea746a29
BL		 1172static const struct snd_kcontrol_new rt5670_sto_adc_1_mux =
1173 SOC_DAPM_ENUM("Stereo1 ADC 1 Mux", rt5670_stereo1_adc1_enum);
5e8351de 1174
01957572 1175static SOC_ENUM_SINGLE_DECL(rt5670_stereo2_adc1_enum, RT5670_STO2_ADC_MIXER,
5e8351de
BL		 1176 RT5670_ADC_1_SRC_SFT, rt5670_stereo_adc1_src);
1177
ea746a29
BL		 1178static const struct snd_kcontrol_new rt5670_sto2_adc_1_mux =
1179 SOC_DAPM_ENUM("Stereo2 ADC 1 Mux", rt5670_stereo2_adc1_enum);
5e8351de 1180
5e8351de
BL		 1181
1182/* MX-27 MX-26 [11] */
1183static const char * const rt5670_stereo_adc2_src[] = {
1184 "DAC MIX", "DMIC"
1185};
1186
01957572 1187static SOC_ENUM_SINGLE_DECL(rt5670_stereo1_adc2_enum, RT5670_STO1_ADC_MIXER,
5e8351de
BL		 1188 RT5670_ADC_2_SRC_SFT, rt5670_stereo_adc2_src);
1189
ea746a29
BL		 1190static const struct snd_kcontrol_new rt5670_sto_adc_2_mux =
1191 SOC_DAPM_ENUM("Stereo1 ADC 2 Mux", rt5670_stereo1_adc2_enum);
5e8351de 1192
01957572 1193static SOC_ENUM_SINGLE_DECL(rt5670_stereo2_adc2_enum, RT5670_STO2_ADC_MIXER,
5e8351de
BL		 1194 RT5670_ADC_2_SRC_SFT, rt5670_stereo_adc2_src);
1195
ea746a29
BL		 1196static const struct snd_kcontrol_new rt5670_sto2_adc_2_mux =
1197 SOC_DAPM_ENUM("Stereo2 ADC 2 Mux", rt5670_stereo2_adc2_enum);
5e8351de 1198
5e8351de
BL		 1199
1200/* MX-27 MX26 [10] */
1201static const char * const rt5670_stereo_adc_src[] = {
1202 "ADC1L ADC2R", "ADC3"
1203};
1204
01957572 1205static SOC_ENUM_SINGLE_DECL(rt5670_stereo1_adc_enum, RT5670_STO1_ADC_MIXER,
5e8351de
BL		 1206 RT5670_ADC_SRC_SFT, rt5670_stereo_adc_src);
1207
1208static const struct snd_kcontrol_new rt5670_sto_adc_mux =
1209 SOC_DAPM_ENUM("Stereo1 ADC source", rt5670_stereo1_adc_enum);
1210
01957572 1211static SOC_ENUM_SINGLE_DECL(rt5670_stereo2_adc_enum, RT5670_STO2_ADC_MIXER,
5e8351de
BL		 1212 RT5670_ADC_SRC_SFT, rt5670_stereo_adc_src);
1213
1214static const struct snd_kcontrol_new rt5670_sto2_adc_mux =
1215 SOC_DAPM_ENUM("Stereo2 ADC source", rt5670_stereo2_adc_enum);
1216
1217/* MX-27 MX-26 [9:8] */
1218static const char * const rt5670_stereo_dmic_src[] = {
1219 "DMIC1", "DMIC2", "DMIC3"
1220};
1221
01957572 1222static SOC_ENUM_SINGLE_DECL(rt5670_stereo1_dmic_enum, RT5670_STO1_ADC_MIXER,
5e8351de
BL		 1223 RT5670_DMIC_SRC_SFT, rt5670_stereo_dmic_src);
1224
1225static const struct snd_kcontrol_new rt5670_sto1_dmic_mux =
1226 SOC_DAPM_ENUM("Stereo1 DMIC source", rt5670_stereo1_dmic_enum);
1227
01957572 1228static SOC_ENUM_SINGLE_DECL(rt5670_stereo2_dmic_enum, RT5670_STO2_ADC_MIXER,
5e8351de
BL		 1229 RT5670_DMIC_SRC_SFT, rt5670_stereo_dmic_src);
1230
1231static const struct snd_kcontrol_new rt5670_sto2_dmic_mux =
1232 SOC_DAPM_ENUM("Stereo2 DMIC source", rt5670_stereo2_dmic_enum);
1233
1234/* MX-27 [0] */
1235static const char * const rt5670_stereo_dmic3_src[] = {
1236 "DMIC3", "PDM ADC"
1237};
1238
01957572 1239static SOC_ENUM_SINGLE_DECL(rt5670_stereo_dmic3_enum, RT5670_STO1_ADC_MIXER,
5e8351de
BL		 1240 RT5670_DMIC3_SRC_SFT, rt5670_stereo_dmic3_src);
1241
1242static const struct snd_kcontrol_new rt5670_sto_dmic3_mux =
1243 SOC_DAPM_ENUM("Stereo DMIC3 source", rt5670_stereo_dmic3_enum);
1244
1245/* Mono ADC source */
1246/* MX-28 [12] */
1247static const char * const rt5670_mono_adc_l1_src[] = {
1248 "Mono DAC MIXL", "ADC1"
1249};
1250
01957572 1251static SOC_ENUM_SINGLE_DECL(rt5670_mono_adc_l1_enum, RT5670_MONO_ADC_MIXER,
5e8351de
BL		 1252 RT5670_MONO_ADC_L1_SRC_SFT, rt5670_mono_adc_l1_src);
1253
1254static const struct snd_kcontrol_new rt5670_mono_adc_l1_mux =
1255 SOC_DAPM_ENUM("Mono ADC1 left source", rt5670_mono_adc_l1_enum);
1256/* MX-28 [11] */
1257static const char * const rt5670_mono_adc_l2_src[] = {
1258 "Mono DAC MIXL", "DMIC"
1259};
1260
01957572 1261static SOC_ENUM_SINGLE_DECL(rt5670_mono_adc_l2_enum, RT5670_MONO_ADC_MIXER,
5e8351de
BL		 1262 RT5670_MONO_ADC_L2_SRC_SFT, rt5670_mono_adc_l2_src);
1263
1264static const struct snd_kcontrol_new rt5670_mono_adc_l2_mux =
1265 SOC_DAPM_ENUM("Mono ADC2 left source", rt5670_mono_adc_l2_enum);
1266
1267/* MX-28 [9:8] */
1268static const char * const rt5670_mono_dmic_src[] = {
1269 "DMIC1", "DMIC2", "DMIC3"
1270};
1271
01957572 1272static SOC_ENUM_SINGLE_DECL(rt5670_mono_dmic_l_enum, RT5670_MONO_ADC_MIXER,
5e8351de
BL		 1273 RT5670_MONO_DMIC_L_SRC_SFT, rt5670_mono_dmic_src);
1274
1275static const struct snd_kcontrol_new rt5670_mono_dmic_l_mux =
1276 SOC_DAPM_ENUM("Mono DMIC left source", rt5670_mono_dmic_l_enum);
1277/* MX-28 [1:0] */
01957572 1278static SOC_ENUM_SINGLE_DECL(rt5670_mono_dmic_r_enum, RT5670_MONO_ADC_MIXER,
5e8351de
BL		 1279 RT5670_MONO_DMIC_R_SRC_SFT, rt5670_mono_dmic_src);
1280
1281static const struct snd_kcontrol_new rt5670_mono_dmic_r_mux =
1282 SOC_DAPM_ENUM("Mono DMIC Right source", rt5670_mono_dmic_r_enum);
1283/* MX-28 [4] */
1284static const char * const rt5670_mono_adc_r1_src[] = {
1285 "Mono DAC MIXR", "ADC2"
1286};
1287
01957572 1288static SOC_ENUM_SINGLE_DECL(rt5670_mono_adc_r1_enum, RT5670_MONO_ADC_MIXER,
5e8351de
BL		 1289 RT5670_MONO_ADC_R1_SRC_SFT, rt5670_mono_adc_r1_src);
1290
1291static const struct snd_kcontrol_new rt5670_mono_adc_r1_mux =
1292 SOC_DAPM_ENUM("Mono ADC1 right source", rt5670_mono_adc_r1_enum);
1293/* MX-28 [3] */
1294static const char * const rt5670_mono_adc_r2_src[] = {
1295 "Mono DAC MIXR", "DMIC"
1296};
1297
01957572 1298static SOC_ENUM_SINGLE_DECL(rt5670_mono_adc_r2_enum, RT5670_MONO_ADC_MIXER,
5e8351de
BL		 1299 RT5670_MONO_ADC_R2_SRC_SFT, rt5670_mono_adc_r2_src);
1300
1301static const struct snd_kcontrol_new rt5670_mono_adc_r2_mux =
1302 SOC_DAPM_ENUM("Mono ADC2 right source", rt5670_mono_adc_r2_enum);
1303
1304/* MX-2D [3:2] */
1305static const char * const rt5670_txdp_slot_src[] = {
1306 "Slot 0-1", "Slot 2-3", "Slot 4-5", "Slot 6-7"
1307};
1308
01957572 1309static SOC_ENUM_SINGLE_DECL(rt5670_txdp_slot_enum, RT5670_DSP_PATH1,
5e8351de
BL		 1310 RT5670_TXDP_SLOT_SEL_SFT, rt5670_txdp_slot_src);
1311
1312static const struct snd_kcontrol_new rt5670_txdp_slot_mux =
1313 SOC_DAPM_ENUM("TxDP Slot source", rt5670_txdp_slot_enum);
1314
1315/* MX-2F [15] */
1316static const char * const rt5670_if1_adc2_in_src[] = {
1317 "IF_ADC2", "VAD_ADC"
1318};
1319
01957572 1320static SOC_ENUM_SINGLE_DECL(rt5670_if1_adc2_in_enum, RT5670_DIG_INF1_DATA,
5e8351de
BL		 1321 RT5670_IF1_ADC2_IN_SFT, rt5670_if1_adc2_in_src);
1322
1323static const struct snd_kcontrol_new rt5670_if1_adc2_in_mux =
1324 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5670_if1_adc2_in_enum);
1325
1326/* MX-2F [14:12] */
1327static const char * const rt5670_if2_adc_in_src[] = {
1328 "IF_ADC1", "IF_ADC2", "IF_ADC3", "TxDC_DAC", "TxDP_ADC", "VAD_ADC"
1329};
1330
01957572 1331static SOC_ENUM_SINGLE_DECL(rt5670_if2_adc_in_enum, RT5670_DIG_INF1_DATA,
5e8351de
BL		 1332 RT5670_IF2_ADC_IN_SFT, rt5670_if2_adc_in_src);
1333
1334static const struct snd_kcontrol_new rt5670_if2_adc_in_mux =
1335 SOC_DAPM_ENUM("IF2 ADC IN source", rt5670_if2_adc_in_enum);
1336
1337/* MX-30 [5:4] */
1338static const char * const rt5670_if4_adc_in_src[] = {
1339 "IF_ADC1", "IF_ADC2", "IF_ADC3"
1340};
1341
01957572 1342static SOC_ENUM_SINGLE_DECL(rt5670_if4_adc_in_enum, RT5670_DIG_INF2_DATA,
5e8351de
BL		 1343 RT5670_IF4_ADC_IN_SFT, rt5670_if4_adc_in_src);
1344
1345static const struct snd_kcontrol_new rt5670_if4_adc_in_mux =
1346 SOC_DAPM_ENUM("IF4 ADC IN source", rt5670_if4_adc_in_enum);
1347
1348/* MX-31 [15] [13] [11] [9] */
1349static const char * const rt5670_pdm_src[] = {
1350 "Mono DAC", "Stereo DAC"
1351};
1352
01957572 1353static SOC_ENUM_SINGLE_DECL(rt5670_pdm1_l_enum, RT5670_PDM_OUT_CTRL,
5e8351de
BL		 1354 RT5670_PDM1_L_SFT, rt5670_pdm_src);
1355
1356static const struct snd_kcontrol_new rt5670_pdm1_l_mux =
1357 SOC_DAPM_ENUM("PDM1 L source", rt5670_pdm1_l_enum);
1358
01957572 1359static SOC_ENUM_SINGLE_DECL(rt5670_pdm1_r_enum, RT5670_PDM_OUT_CTRL,
5e8351de
BL		 1360 RT5670_PDM1_R_SFT, rt5670_pdm_src);
1361
1362static const struct snd_kcontrol_new rt5670_pdm1_r_mux =
1363 SOC_DAPM_ENUM("PDM1 R source", rt5670_pdm1_r_enum);
1364
01957572 1365static SOC_ENUM_SINGLE_DECL(rt5670_pdm2_l_enum, RT5670_PDM_OUT_CTRL,
5e8351de
BL		 1366 RT5670_PDM2_L_SFT, rt5670_pdm_src);
1367
1368static const struct snd_kcontrol_new rt5670_pdm2_l_mux =
1369 SOC_DAPM_ENUM("PDM2 L source", rt5670_pdm2_l_enum);
1370
01957572 1371static SOC_ENUM_SINGLE_DECL(rt5670_pdm2_r_enum, RT5670_PDM_OUT_CTRL,
5e8351de
BL		 1372 RT5670_PDM2_R_SFT, rt5670_pdm_src);
1373
1374static const struct snd_kcontrol_new rt5670_pdm2_r_mux =
1375 SOC_DAPM_ENUM("PDM2 R source", rt5670_pdm2_r_enum);
1376
1377/* MX-FA [12] */
1378static const char * const rt5670_if1_adc1_in1_src[] = {
1379 "IF_ADC1", "IF1_ADC3"
1380};
1381
01957572 1382static SOC_ENUM_SINGLE_DECL(rt5670_if1_adc1_in1_enum, RT5670_DIG_MISC,
5e8351de
BL		 1383 RT5670_IF1_ADC1_IN1_SFT, rt5670_if1_adc1_in1_src);
1384
1385static const struct snd_kcontrol_new rt5670_if1_adc1_in1_mux =
1386 SOC_DAPM_ENUM("IF1 ADC1 IN1 source", rt5670_if1_adc1_in1_enum);
1387
1388/* MX-FA [11] */
1389static const char * const rt5670_if1_adc1_in2_src[] = {
1390 "IF1_ADC1_IN1", "IF1_ADC4"
1391};
1392
01957572 1393static SOC_ENUM_SINGLE_DECL(rt5670_if1_adc1_in2_enum, RT5670_DIG_MISC,
5e8351de
BL		 1394 RT5670_IF1_ADC1_IN2_SFT, rt5670_if1_adc1_in2_src);
1395
1396static const struct snd_kcontrol_new rt5670_if1_adc1_in2_mux =
1397 SOC_DAPM_ENUM("IF1 ADC1 IN2 source", rt5670_if1_adc1_in2_enum);
1398
1399/* MX-FA [10] */
1400static const char * const rt5670_if1_adc2_in1_src[] = {
1401 "IF1_ADC2_IN", "IF1_ADC4"
1402};
1403
01957572 1404static SOC_ENUM_SINGLE_DECL(rt5670_if1_adc2_in1_enum, RT5670_DIG_MISC,
5e8351de
BL		 1405 RT5670_IF1_ADC2_IN1_SFT, rt5670_if1_adc2_in1_src);
1406
1407static const struct snd_kcontrol_new rt5670_if1_adc2_in1_mux =
1408 SOC_DAPM_ENUM("IF1 ADC2 IN1 source", rt5670_if1_adc2_in1_enum);
1409
1410/* MX-9D [9:8] */
1411static const char * const rt5670_vad_adc_src[] = {
1412 "Sto1 ADC L", "Mono ADC L", "Mono ADC R", "Sto2 ADC L"
1413};
1414
01957572 1415static SOC_ENUM_SINGLE_DECL(rt5670_vad_adc_enum, RT5670_VAD_CTRL4,
5e8351de
BL		 1416 RT5670_VAD_SEL_SFT, rt5670_vad_adc_src);
1417
1418static const struct snd_kcontrol_new rt5670_vad_adc_mux =
1419 SOC_DAPM_ENUM("VAD ADC source", rt5670_vad_adc_enum);
1420
1421static int rt5670_hp_power_event(struct snd_soc_dapm_widget *w,
1422 struct snd_kcontrol *kcontrol, int event)
1423{
8eee1468 1424 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
5e8351de
BL		 1425 struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
1426
1427 switch (event) {
1428 case SND_SOC_DAPM_POST_PMU:
1429 regmap_update_bits(rt5670->regmap, RT5670_CHARGE_PUMP,
1430 RT5670_PM_HP_MASK, RT5670_PM_HP_HV);
1431 regmap_update_bits(rt5670->regmap, RT5670_GEN_CTRL2,
1432 0x0400, 0x0400);
1433 /* headphone amp power on */
1434 regmap_update_bits(rt5670->regmap, RT5670_PWR_ANLG1,
1435 RT5670_PWR_HA | RT5670_PWR_FV1 |
1436 RT5670_PWR_FV2, RT5670_PWR_HA |
1437 RT5670_PWR_FV1 | RT5670_PWR_FV2);
1438 /* depop parameters */
1439 regmap_write(rt5670->regmap, RT5670_DEPOP_M2, 0x3100);
1440 regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x8009);
1441 regmap_write(rt5670->regmap, RT5670_PR_BASE +
1442 RT5670_HP_DCC_INT1, 0x9f00);
1443 mdelay(20);
1444 regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x8019);
1445 break;
1446 case SND_SOC_DAPM_PRE_PMD:
1447 regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x0004);
1448 msleep(30);
1449 break;
1450 default:
1451 return 0;
1452 }
1453
1454 return 0;
1455}
1456
1457static int rt5670_hp_event(struct snd_soc_dapm_widget *w,
1458 struct snd_kcontrol *kcontrol, int event)
1459{
8eee1468 1460 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
5e8351de
BL		 1461 struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
1462
1463 switch (event) {
1464 case SND_SOC_DAPM_POST_PMU:
1465 /* headphone unmute sequence */
1466 regmap_write(rt5670->regmap, RT5670_PR_BASE +
1467 RT5670_MAMP_INT_REG2, 0xb400);
1468 regmap_write(rt5670->regmap, RT5670_DEPOP_M3, 0x0772);
1469 regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x805d);
1470 regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x831d);
1471 regmap_update_bits(rt5670->regmap, RT5670_GEN_CTRL2,
1472 0x0300, 0x0300);
1473 regmap_update_bits(rt5670->regmap, RT5670_HP_VOL,
1474 RT5670_L_MUTE | RT5670_R_MUTE, 0);
1475 msleep(80);
1476 regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x8019);
1477 break;
1478
1479 case SND_SOC_DAPM_PRE_PMD:
1480 /* headphone mute sequence */
1481 regmap_write(rt5670->regmap, RT5670_PR_BASE +
1482 RT5670_MAMP_INT_REG2, 0xb400);
1483 regmap_write(rt5670->regmap, RT5670_DEPOP_M3, 0x0772);
1484 regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x803d);
1485 mdelay(10);
1486 regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x831d);
1487 mdelay(10);
1488 regmap_update_bits(rt5670->regmap, RT5670_HP_VOL,
1489 RT5670_L_MUTE | RT5670_R_MUTE,
1490 RT5670_L_MUTE | RT5670_R_MUTE);
1491 msleep(20);
1492 regmap_update_bits(rt5670->regmap,
1493 RT5670_GEN_CTRL2, 0x0300, 0x0);
1494 regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x8019);
1495 regmap_write(rt5670->regmap, RT5670_DEPOP_M3, 0x0707);
1496 regmap_write(rt5670->regmap, RT5670_PR_BASE +
1497 RT5670_MAMP_INT_REG2, 0xfc00);
1498 break;
1499
1500 default:
1501 return 0;
1502 }
1503
1504 return 0;
1505}
1506
1507static int rt5670_bst1_event(struct snd_soc_dapm_widget *w,
1508 struct snd_kcontrol *kcontrol, int event)
1509{
8eee1468 1510 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
5e8351de
BL		 1511
1512 switch (event) {
1513 case SND_SOC_DAPM_POST_PMU:
1514 snd_soc_update_bits(codec, RT5670_PWR_ANLG2,
1515 RT5670_PWR_BST1_P, RT5670_PWR_BST1_P);
1516 break;
1517
1518 case SND_SOC_DAPM_PRE_PMD:
1519 snd_soc_update_bits(codec, RT5670_PWR_ANLG2,
1520 RT5670_PWR_BST1_P, 0);
1521 break;
1522
1523 default:
1524 return 0;
1525 }
1526
1527 return 0;
1528}
1529
1530static int rt5670_bst2_event(struct snd_soc_dapm_widget *w,
1531 struct snd_kcontrol *kcontrol, int event)
1532{
8eee1468 1533 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
5e8351de
BL		 1534
1535 switch (event) {
1536 case SND_SOC_DAPM_POST_PMU:
1537 snd_soc_update_bits(codec, RT5670_PWR_ANLG2,
1538 RT5670_PWR_BST2_P, RT5670_PWR_BST2_P);
1539 break;
1540
1541 case SND_SOC_DAPM_PRE_PMD:
1542 snd_soc_update_bits(codec, RT5670_PWR_ANLG2,
1543 RT5670_PWR_BST2_P, 0);
1544 break;
1545
1546 default:
1547 return 0;
1548 }
1549
1550 return 0;
1551}
1552
1553static const struct snd_soc_dapm_widget rt5670_dapm_widgets[] = {
1554 SND_SOC_DAPM_SUPPLY("PLL1", RT5670_PWR_ANLG2,
1555 RT5670_PWR_PLL_BIT, 0, NULL, 0),
1556 SND_SOC_DAPM_SUPPLY("I2S DSP", RT5670_PWR_DIG2,
1557 RT5670_PWR_I2S_DSP_BIT, 0, NULL, 0),
1558 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5670_PWR_VOL,
1559 RT5670_PWR_MIC_DET_BIT, 0, NULL, 0),
1560
1561 /* ASRC */
1562 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5670_ASRC_1,
1563 11, 0, NULL, 0),
1564 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5670_ASRC_1,
1565 12, 0, NULL, 0),
1566 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5670_ASRC_1,
1567 10, 0, NULL, 0),
1568 SND_SOC_DAPM_SUPPLY_S("DAC MONO L ASRC", 1, RT5670_ASRC_1,
1569 9, 0, NULL, 0),
1570 SND_SOC_DAPM_SUPPLY_S("DAC MONO R ASRC", 1, RT5670_ASRC_1,
1571 8, 0, NULL, 0),
ff4541c3
BL		 1572 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5670_ASRC_1,
1573 7, 0, NULL, 0),
1574 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5670_ASRC_1,
1575 6, 0, NULL, 0),
1576 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5670_ASRC_1,
1577 5, 0, NULL, 0),
1578 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5670_ASRC_1,
1579 4, 0, NULL, 0),
5e8351de
BL		 1580 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5670_ASRC_1,
1581 3, 0, NULL, 0),
1582 SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5670_ASRC_1,
1583 2, 0, NULL, 0),
1584 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5670_ASRC_1,
1585 1, 0, NULL, 0),
1586 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5670_ASRC_1,
1587 0, 0, NULL, 0),
1588
1589 /* Input Side */
1590 /* micbias */
1591 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5670_PWR_ANLG2,
1592 RT5670_PWR_MB1_BIT, 0, NULL, 0),
1593
1594 /* Input Lines */
1595 SND_SOC_DAPM_INPUT("DMIC L1"),
1596 SND_SOC_DAPM_INPUT("DMIC R1"),
1597 SND_SOC_DAPM_INPUT("DMIC L2"),
1598 SND_SOC_DAPM_INPUT("DMIC R2"),
1599 SND_SOC_DAPM_INPUT("DMIC L3"),
1600 SND_SOC_DAPM_INPUT("DMIC R3"),
1601
1602 SND_SOC_DAPM_INPUT("IN1P"),
1603 SND_SOC_DAPM_INPUT("IN1N"),
1604 SND_SOC_DAPM_INPUT("IN2P"),
1605 SND_SOC_DAPM_INPUT("IN2N"),
1606
1607 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1608 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1609 SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1610
1611 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1612 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1613 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5670_DMIC_CTRL1,
1614 RT5670_DMIC_1_EN_SFT, 0, NULL, 0),
1615 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5670_DMIC_CTRL1,
1616 RT5670_DMIC_2_EN_SFT, 0, NULL, 0),
1617 SND_SOC_DAPM_SUPPLY("DMIC3 Power", RT5670_DMIC_CTRL1,
1618 RT5670_DMIC_3_EN_SFT, 0, NULL, 0),
1619 /* Boost */
1620 SND_SOC_DAPM_PGA_E("BST1", RT5670_PWR_ANLG2, RT5670_PWR_BST1_BIT,
1621 0, NULL, 0, rt5670_bst1_event,
1622 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1623 SND_SOC_DAPM_PGA_E("BST2", RT5670_PWR_ANLG2, RT5670_PWR_BST2_BIT,
1624 0, NULL, 0, rt5670_bst2_event,
1625 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1626 /* Input Volume */
1627 SND_SOC_DAPM_PGA("INL VOL", RT5670_PWR_VOL,
1628 RT5670_PWR_IN_L_BIT, 0, NULL, 0),
1629 SND_SOC_DAPM_PGA("INR VOL", RT5670_PWR_VOL,
1630 RT5670_PWR_IN_R_BIT, 0, NULL, 0),
1631
1632 /* REC Mixer */
1633 SND_SOC_DAPM_MIXER("RECMIXL", RT5670_PWR_MIXER, RT5670_PWR_RM_L_BIT, 0,
1634 rt5670_rec_l_mix, ARRAY_SIZE(rt5670_rec_l_mix)),
1635 SND_SOC_DAPM_MIXER("RECMIXR", RT5670_PWR_MIXER, RT5670_PWR_RM_R_BIT, 0,
1636 rt5670_rec_r_mix, ARRAY_SIZE(rt5670_rec_r_mix)),
1637 /* ADCs */
1638 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0),
1639 SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM, 0, 0),
1640
1641 SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
1642
1643 SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5670_PWR_DIG1,
1644 RT5670_PWR_ADC_L_BIT, 0, NULL, 0),
1645 SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5670_PWR_DIG1,
1646 RT5670_PWR_ADC_R_BIT, 0, NULL, 0),
1647 SND_SOC_DAPM_SUPPLY("ADC clock", RT5670_PR_BASE +
1648 RT5670_CHOP_DAC_ADC, 12, 0, NULL, 0),
1649 /* ADC Mux */
1650 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
1651 &rt5670_sto1_dmic_mux),
1652 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
ea746a29 1653 &rt5670_sto_adc_2_mux),
5e8351de 1654 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
ea746a29 1655 &rt5670_sto_adc_2_mux),
5e8351de 1656 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
ea746a29 1657 &rt5670_sto_adc_1_mux),
5e8351de 1658 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
ea746a29 1659 &rt5670_sto_adc_1_mux),
5e8351de
BL		 1660 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
1661 &rt5670_sto2_dmic_mux),
1662 SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
ea746a29 1663 &rt5670_sto2_adc_2_mux),
5e8351de 1664 SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
ea746a29 1665 &rt5670_sto2_adc_2_mux),
5e8351de 1666 SND_SOC_DAPM_MUX("Stereo2 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
ea746a29 1667 &rt5670_sto2_adc_1_mux),
5e8351de 1668 SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
ea746a29 1669 &rt5670_sto2_adc_1_mux),
5e8351de
BL		 1670 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
1671 &rt5670_sto2_adc_lr_mux),
1672 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
1673 &rt5670_mono_dmic_l_mux),
1674 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
1675 &rt5670_mono_dmic_r_mux),
1676 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1677 &rt5670_mono_adc_l2_mux),
1678 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1679 &rt5670_mono_adc_l1_mux),
1680 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1681 &rt5670_mono_adc_r1_mux),
1682 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1683 &rt5670_mono_adc_r2_mux),
1684 /* ADC Mixer */
1685 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5670_PWR_DIG2,
1686 RT5670_PWR_ADC_S1F_BIT, 0, NULL, 0),
1687 SND_SOC_DAPM_SUPPLY("ADC Stereo2 Filter", RT5670_PWR_DIG2,
1688 RT5670_PWR_ADC_S2F_BIT, 0, NULL, 0),
1689 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", RT5670_STO1_ADC_DIG_VOL,
1690 RT5670_L_MUTE_SFT, 1, rt5670_sto1_adc_l_mix,
1691 ARRAY_SIZE(rt5670_sto1_adc_l_mix)),
1692 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", RT5670_STO1_ADC_DIG_VOL,
1693 RT5670_R_MUTE_SFT, 1, rt5670_sto1_adc_r_mix,
1694 ARRAY_SIZE(rt5670_sto1_adc_r_mix)),
1695 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
1696 rt5670_sto2_adc_l_mix,
1697 ARRAY_SIZE(rt5670_sto2_adc_l_mix)),
1698 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
1699 rt5670_sto2_adc_r_mix,
1700 ARRAY_SIZE(rt5670_sto2_adc_r_mix)),
1701 SND_SOC_DAPM_SUPPLY("ADC Mono Left Filter", RT5670_PWR_DIG2,
1702 RT5670_PWR_ADC_MF_L_BIT, 0, NULL, 0),
1703 SND_SOC_DAPM_MIXER("Mono ADC MIXL", RT5670_MONO_ADC_DIG_VOL,
1704 RT5670_L_MUTE_SFT, 1, rt5670_mono_adc_l_mix,
1705 ARRAY_SIZE(rt5670_mono_adc_l_mix)),
1706 SND_SOC_DAPM_SUPPLY("ADC Mono Right Filter", RT5670_PWR_DIG2,
1707 RT5670_PWR_ADC_MF_R_BIT, 0, NULL, 0),
1708 SND_SOC_DAPM_MIXER("Mono ADC MIXR", RT5670_MONO_ADC_DIG_VOL,
1709 RT5670_R_MUTE_SFT, 1, rt5670_mono_adc_r_mix,
1710 ARRAY_SIZE(rt5670_mono_adc_r_mix)),
1711
1712 /* ADC PGA */
1713 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1714 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1715 SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1716 SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1717 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1718 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1719 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1720 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1721 SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1722 SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1723 SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1724 SND_SOC_DAPM_PGA("IF_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1725 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1726 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1727 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
5e8351de
BL		 1728
1729 /* DSP */
1730 SND_SOC_DAPM_PGA("TxDP_ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1731 SND_SOC_DAPM_PGA("TxDP_ADC_L", SND_SOC_NOPM, 0, 0, NULL, 0),
1732 SND_SOC_DAPM_PGA("TxDP_ADC_R", SND_SOC_NOPM, 0, 0, NULL, 0),
1733 SND_SOC_DAPM_PGA("TxDC_DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1734
1735 SND_SOC_DAPM_MUX("TDM Data Mux", SND_SOC_NOPM, 0, 0,
1736 &rt5670_txdp_slot_mux),
1737
1738 SND_SOC_DAPM_MUX("DSP UL Mux", SND_SOC_NOPM, 0, 0,
1739 &rt5670_dsp_ul_mux),
1740 SND_SOC_DAPM_MUX("DSP DL Mux", SND_SOC_NOPM, 0, 0,
1741 &rt5670_dsp_dl_mux),
1742
1743 SND_SOC_DAPM_MUX("RxDP Mux", SND_SOC_NOPM, 0, 0,
1744 &rt5670_rxdp_mux),
1745
1746 /* IF2 Mux */
1747 SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM, 0, 0,
1748 &rt5670_if2_adc_in_mux),
1749
1750 /* Digital Interface */
1751 SND_SOC_DAPM_SUPPLY("I2S1", RT5670_PWR_DIG1,
1752 RT5670_PWR_I2S1_BIT, 0, NULL, 0),
1753 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1754 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1755 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1756 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1757 SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1758 SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1759 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1760 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1761 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1762 SND_SOC_DAPM_SUPPLY("I2S2", RT5670_PWR_DIG1,
1763 RT5670_PWR_I2S2_BIT, 0, NULL, 0),
1764 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1765 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1766 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1767 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1768 SND_SOC_DAPM_PGA("IF2 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1769 SND_SOC_DAPM_PGA("IF2 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1770
1771 /* Digital Interface Select */
1772 SND_SOC_DAPM_MUX("IF1 ADC1 IN1 Mux", SND_SOC_NOPM, 0, 0,
1773 &rt5670_if1_adc1_in1_mux),
1774 SND_SOC_DAPM_MUX("IF1 ADC1 IN2 Mux", SND_SOC_NOPM, 0, 0,
1775 &rt5670_if1_adc1_in2_mux),
1776 SND_SOC_DAPM_MUX("IF1 ADC2 IN Mux", SND_SOC_NOPM, 0, 0,
1777 &rt5670_if1_adc2_in_mux),
1778 SND_SOC_DAPM_MUX("IF1 ADC2 IN1 Mux", SND_SOC_NOPM, 0, 0,
1779 &rt5670_if1_adc2_in1_mux),
1780 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
1781 &rt5670_vad_adc_mux),
1782
1783 /* Audio Interface */
1784 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1785 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1786 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1787 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
1788 RT5670_GPIO_CTRL1, RT5670_I2S2_PIN_SFT, 1),
1789
1790 /* Audio DSP */
1791 SND_SOC_DAPM_PGA("Audio DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
1792
1793 /* Output Side */
1794 /* DAC mixer before sound effect */
1795 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1796 rt5670_dac_l_mix, ARRAY_SIZE(rt5670_dac_l_mix)),
1797 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1798 rt5670_dac_r_mix, ARRAY_SIZE(rt5670_dac_r_mix)),
1799 SND_SOC_DAPM_PGA("DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1800
1801 /* DAC2 channel Mux */
1802 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0,
1803 &rt5670_dac_l2_mux),
1804 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0,
1805 &rt5670_dac_r2_mux),
1806 SND_SOC_DAPM_PGA("DAC L2 Volume", RT5670_PWR_DIG1,
1807 RT5670_PWR_DAC_L2_BIT, 0, NULL, 0),
1808 SND_SOC_DAPM_PGA("DAC R2 Volume", RT5670_PWR_DIG1,
1809 RT5670_PWR_DAC_R2_BIT, 0, NULL, 0),
1810
1811 SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5670_dac1l_mux),
1812 SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5670_dac1r_mux),
1813
1814 /* DAC Mixer */
1815 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5670_PWR_DIG2,
1816 RT5670_PWR_DAC_S1F_BIT, 0, NULL, 0),
1817 SND_SOC_DAPM_SUPPLY("DAC Mono Left Filter", RT5670_PWR_DIG2,
1818 RT5670_PWR_DAC_MF_L_BIT, 0, NULL, 0),
1819 SND_SOC_DAPM_SUPPLY("DAC Mono Right Filter", RT5670_PWR_DIG2,
1820 RT5670_PWR_DAC_MF_R_BIT, 0, NULL, 0),
1821 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
1822 rt5670_sto_dac_l_mix,
1823 ARRAY_SIZE(rt5670_sto_dac_l_mix)),
1824 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
1825 rt5670_sto_dac_r_mix,
1826 ARRAY_SIZE(rt5670_sto_dac_r_mix)),
1827 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
1828 rt5670_mono_dac_l_mix,
1829 ARRAY_SIZE(rt5670_mono_dac_l_mix)),
1830 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
1831 rt5670_mono_dac_r_mix,
1832 ARRAY_SIZE(rt5670_mono_dac_r_mix)),
1833 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
1834 rt5670_dig_l_mix,
1835 ARRAY_SIZE(rt5670_dig_l_mix)),
1836 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
1837 rt5670_dig_r_mix,
1838 ARRAY_SIZE(rt5670_dig_r_mix)),
1839
1840 /* DACs */
1841 SND_SOC_DAPM_SUPPLY("DAC L1 Power", RT5670_PWR_DIG1,
1842 RT5670_PWR_DAC_L1_BIT, 0, NULL, 0),
1843 SND_SOC_DAPM_SUPPLY("DAC R1 Power", RT5670_PWR_DIG1,
1844 RT5670_PWR_DAC_R1_BIT, 0, NULL, 0),
1845 SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
1846 SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
1847 SND_SOC_DAPM_DAC("DAC L2", NULL, RT5670_PWR_DIG1,
1848 RT5670_PWR_DAC_L2_BIT, 0),
1849
1850 SND_SOC_DAPM_DAC("DAC R2", NULL, RT5670_PWR_DIG1,
1851 RT5670_PWR_DAC_R2_BIT, 0),
1852 /* OUT Mixer */
1853
1854 SND_SOC_DAPM_MIXER("OUT MIXL", RT5670_PWR_MIXER, RT5670_PWR_OM_L_BIT,
1855 0, rt5670_out_l_mix, ARRAY_SIZE(rt5670_out_l_mix)),
1856 SND_SOC_DAPM_MIXER("OUT MIXR", RT5670_PWR_MIXER, RT5670_PWR_OM_R_BIT,
1857 0, rt5670_out_r_mix, ARRAY_SIZE(rt5670_out_r_mix)),
1858 /* Ouput Volume */
1859 SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5670_PWR_VOL,
1860 RT5670_PWR_HV_L_BIT, 0,
1861 rt5670_hpvoll_mix, ARRAY_SIZE(rt5670_hpvoll_mix)),
1862 SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5670_PWR_VOL,
1863 RT5670_PWR_HV_R_BIT, 0,
1864 rt5670_hpvolr_mix, ARRAY_SIZE(rt5670_hpvolr_mix)),
1865 SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0),
1866 SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0),
1867 SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0),
1868
1869 /* HPO/LOUT/Mono Mixer */
1870 SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0,
1871 rt5670_hpo_mix, ARRAY_SIZE(rt5670_hpo_mix)),
1872 SND_SOC_DAPM_MIXER("LOUT MIX", RT5670_PWR_ANLG1, RT5670_PWR_LM_BIT,
1873 0, rt5670_lout_mix, ARRAY_SIZE(rt5670_lout_mix)),
1874 SND_SOC_DAPM_SUPPLY_S("Improve HP Amp Drv", 1, SND_SOC_NOPM, 0, 0,
1875 rt5670_hp_power_event, SND_SOC_DAPM_POST_PMU |
1876 SND_SOC_DAPM_PRE_PMD),
1877 SND_SOC_DAPM_SUPPLY("HP L Amp", RT5670_PWR_ANLG1,
1878 RT5670_PWR_HP_L_BIT, 0, NULL, 0),
1879 SND_SOC_DAPM_SUPPLY("HP R Amp", RT5670_PWR_ANLG1,
1880 RT5670_PWR_HP_R_BIT, 0, NULL, 0),
1881 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0,
1882 rt5670_hp_event, SND_SOC_DAPM_PRE_PMD |
1883 SND_SOC_DAPM_POST_PMU),
1884 SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0,
1885 &lout_l_enable_control),
1886 SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0,
1887 &lout_r_enable_control),
1888 SND_SOC_DAPM_PGA("LOUT Amp", SND_SOC_NOPM, 0, 0, NULL, 0),
1889
1890 /* PDM */
1891 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5670_PWR_DIG2,
1892 RT5670_PWR_PDM1_BIT, 0, NULL, 0),
5e8351de
BL		 1893
1894 SND_SOC_DAPM_MUX("PDM1 L Mux", RT5670_PDM_OUT_CTRL,
1895 RT5670_M_PDM1_L_SFT, 1, &rt5670_pdm1_l_mux),
1896 SND_SOC_DAPM_MUX("PDM1 R Mux", RT5670_PDM_OUT_CTRL,
1897 RT5670_M_PDM1_R_SFT, 1, &rt5670_pdm1_r_mux),
5e8351de
BL		 1898
1899 /* Output Lines */
1900 SND_SOC_DAPM_OUTPUT("HPOL"),
1901 SND_SOC_DAPM_OUTPUT("HPOR"),
1902 SND_SOC_DAPM_OUTPUT("LOUTL"),
1903 SND_SOC_DAPM_OUTPUT("LOUTR"),
0cf18632
BL		 1904};
1905
1906static const struct snd_soc_dapm_widget rt5670_specific_dapm_widgets[] = {
1907 SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5670_PWR_DIG2,
1908 RT5670_PWR_PDM2_BIT, 0, NULL, 0),
1909 SND_SOC_DAPM_MUX("PDM2 L Mux", RT5670_PDM_OUT_CTRL,
1910 RT5670_M_PDM2_L_SFT, 1, &rt5670_pdm2_l_mux),
1911 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5670_PDM_OUT_CTRL,
1912 RT5670_M_PDM2_R_SFT, 1, &rt5670_pdm2_r_mux),
5e8351de
BL		 1913 SND_SOC_DAPM_OUTPUT("PDM1L"),
1914 SND_SOC_DAPM_OUTPUT("PDM1R"),
1915 SND_SOC_DAPM_OUTPUT("PDM2L"),
1916 SND_SOC_DAPM_OUTPUT("PDM2R"),
1917};
1918
0cf18632
BL		 1919static const struct snd_soc_dapm_widget rt5672_specific_dapm_widgets[] = {
1920 SND_SOC_DAPM_PGA("SPO Amp", SND_SOC_NOPM, 0, 0, NULL, 0),
1921 SND_SOC_DAPM_OUTPUT("SPOLP"),
1922 SND_SOC_DAPM_OUTPUT("SPOLN"),
1923 SND_SOC_DAPM_OUTPUT("SPORP"),
1924 SND_SOC_DAPM_OUTPUT("SPORN"),
1925};
1926
5e8351de
BL		 1927static const struct snd_soc_dapm_route rt5670_dapm_routes[] = {
1928 { "ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc },
1929 { "ADC Stereo2 Filter", NULL, "ADC STO2 ASRC", is_using_asrc },
1930 { "ADC Mono Left Filter", NULL, "ADC MONO L ASRC", is_using_asrc },
1931 { "ADC Mono Right Filter", NULL, "ADC MONO R ASRC", is_using_asrc },
1932 { "DAC Mono Left Filter", NULL, "DAC MONO L ASRC", is_using_asrc },
1933 { "DAC Mono Right Filter", NULL, "DAC MONO R ASRC", is_using_asrc },
1934 { "DAC Stereo1 Filter", NULL, "DAC STO ASRC", is_using_asrc },
ff4541c3
BL		 1935 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC", can_use_asrc },
1936 { "Stereo2 DMIC Mux", NULL, "DMIC STO2 ASRC", can_use_asrc },
1937 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC", can_use_asrc },
1938 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC", can_use_asrc },
5e8351de 1939
e50334d4
BL		 1940 { "I2S1", NULL, "I2S1 ASRC", can_use_asrc},
1941 { "I2S2", NULL, "I2S2 ASRC", can_use_asrc},
5e8351de
BL		 1942
1943 { "DMIC1", NULL, "DMIC L1" },
1944 { "DMIC1", NULL, "DMIC R1" },
1945 { "DMIC2", NULL, "DMIC L2" },
1946 { "DMIC2", NULL, "DMIC R2" },
1947 { "DMIC3", NULL, "DMIC L3" },
1948 { "DMIC3", NULL, "DMIC R3" },
1949
1950 { "BST1", NULL, "IN1P" },
1951 { "BST1", NULL, "IN1N" },
1952 { "BST1", NULL, "Mic Det Power" },
1953 { "BST2", NULL, "IN2P" },
1954 { "BST2", NULL, "IN2N" },
1955
1956 { "INL VOL", NULL, "IN2P" },
1957 { "INR VOL", NULL, "IN2N" },
1958
1959 { "RECMIXL", "INL Switch", "INL VOL" },
1960 { "RECMIXL", "BST2 Switch", "BST2" },
1961 { "RECMIXL", "BST1 Switch", "BST1" },
1962
1963 { "RECMIXR", "INR Switch", "INR VOL" },
1964 { "RECMIXR", "BST2 Switch", "BST2" },
1965 { "RECMIXR", "BST1 Switch", "BST1" },
1966
1967 { "ADC 1", NULL, "RECMIXL" },
1968 { "ADC 1", NULL, "ADC 1 power" },
1969 { "ADC 1", NULL, "ADC clock" },
1970 { "ADC 2", NULL, "RECMIXR" },
1971 { "ADC 2", NULL, "ADC 2 power" },
1972 { "ADC 2", NULL, "ADC clock" },
1973
1974 { "DMIC L1", NULL, "DMIC CLK" },
1975 { "DMIC L1", NULL, "DMIC1 Power" },
1976 { "DMIC R1", NULL, "DMIC CLK" },
1977 { "DMIC R1", NULL, "DMIC1 Power" },
1978 { "DMIC L2", NULL, "DMIC CLK" },
1979 { "DMIC L2", NULL, "DMIC2 Power" },
1980 { "DMIC R2", NULL, "DMIC CLK" },
1981 { "DMIC R2", NULL, "DMIC2 Power" },
1982 { "DMIC L3", NULL, "DMIC CLK" },
1983 { "DMIC L3", NULL, "DMIC3 Power" },
1984 { "DMIC R3", NULL, "DMIC CLK" },
1985 { "DMIC R3", NULL, "DMIC3 Power" },
1986
1987 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
1988 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
1989 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
1990
1991 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
1992 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
1993 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
1994
1995 { "Mono DMIC L Mux", "DMIC1", "DMIC L1" },
1996 { "Mono DMIC L Mux", "DMIC2", "DMIC L2" },
1997 { "Mono DMIC L Mux", "DMIC3", "DMIC L3" },
1998
1999 { "Mono DMIC R Mux", "DMIC1", "DMIC R1" },
2000 { "Mono DMIC R Mux", "DMIC2", "DMIC R2" },
2001 { "Mono DMIC R Mux", "DMIC3", "DMIC R3" },
2002
2003 { "ADC 1_2", NULL, "ADC 1" },
2004 { "ADC 1_2", NULL, "ADC 2" },
2005
2006 { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2007 { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
2008 { "Stereo1 ADC L1 Mux", "ADC", "ADC 1_2" },
2009 { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
2010
2011 { "Stereo1 ADC R1 Mux", "ADC", "ADC 1_2" },
2012 { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
2013 { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2014 { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
2015
2016 { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
2017 { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
2018 { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
2019 { "Mono ADC L1 Mux", "ADC1", "ADC 1" },
2020
2021 { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
2022 { "Mono ADC R1 Mux", "ADC2", "ADC 2" },
2023 { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
2024 { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
2025
2026 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" },
2027 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },
2028 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },
2029 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },
2030
2031 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
2032 { "Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter" },
5e8351de
BL		 2033
2034 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
2035 { "Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter" },
2036 { "ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll },
2037
2038 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" },
2039 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
2040 { "Mono ADC MIXL", NULL, "ADC Mono Left Filter" },
2041 { "ADC Mono Left Filter", NULL, "PLL1", is_sys_clk_from_pll },
2042
2043 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
2044 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
2045 { "Mono ADC MIXR", NULL, "ADC Mono Right Filter" },
2046 { "ADC Mono Right Filter", NULL, "PLL1", is_sys_clk_from_pll },
2047
2048 { "Stereo2 ADC L2 Mux", "DMIC", "Stereo2 DMIC Mux" },
2049 { "Stereo2 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
2050 { "Stereo2 ADC L1 Mux", "ADC", "ADC 1_2" },
2051 { "Stereo2 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
2052
2053 { "Stereo2 ADC R1 Mux", "ADC", "ADC 1_2" },
2054 { "Stereo2 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
2055 { "Stereo2 ADC R2 Mux", "DMIC", "Stereo2 DMIC Mux" },
2056 { "Stereo2 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
2057
2058 { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC L1 Mux" },
2059 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux" },
2060 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux" },
2061 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC R2 Mux" },
2062
2063 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
2064 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
2065
2066 { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
2067 { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
2068
2069 { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
2070 { "Stereo2 ADC MIXL", NULL, "ADC Stereo2 Filter" },
5e8351de
BL		 2071
2072 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
2073 { "Stereo2 ADC MIXR", NULL, "ADC Stereo2 Filter" },
2074 { "ADC Stereo2 Filter", NULL, "PLL1", is_sys_clk_from_pll },
2075
2076 { "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" },
2077 { "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" },
2078 { "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" },
2079 { "VAD ADC Mux", "Sto2 ADC L", "Sto2 ADC MIXL" },
2080
2081 { "VAD_ADC", NULL, "VAD ADC Mux" },
2082
2083 { "IF_ADC1", NULL, "Stereo1 ADC MIXL" },
2084 { "IF_ADC1", NULL, "Stereo1 ADC MIXR" },
2085 { "IF_ADC2", NULL, "Mono ADC MIXL" },
2086 { "IF_ADC2", NULL, "Mono ADC MIXR" },
2087 { "IF_ADC3", NULL, "Stereo2 ADC MIXL" },
2088 { "IF_ADC3", NULL, "Stereo2 ADC MIXR" },
2089
2090 { "IF1 ADC1 IN1 Mux", "IF_ADC1", "IF_ADC1" },
2091 { "IF1 ADC1 IN1 Mux", "IF1_ADC3", "IF1_ADC3" },
2092
2093 { "IF1 ADC1 IN2 Mux", "IF1_ADC1_IN1", "IF1 ADC1 IN1 Mux" },
8e2d163b 2094 { "IF1 ADC1 IN2 Mux", "IF1_ADC4", "TxDP_ADC" },
5e8351de
BL		 2095
2096 { "IF1 ADC2 IN Mux", "IF_ADC2", "IF_ADC2" },
2097 { "IF1 ADC2 IN Mux", "VAD_ADC", "VAD_ADC" },
2098
2099 { "IF1 ADC2 IN1 Mux", "IF1_ADC2_IN", "IF1 ADC2 IN Mux" },
8e2d163b 2100 { "IF1 ADC2 IN1 Mux", "IF1_ADC4", "TxDP_ADC" },
5e8351de
BL		 2101
2102 { "IF1_ADC1" , NULL, "IF1 ADC1 IN2 Mux" },
2103 { "IF1_ADC2" , NULL, "IF1 ADC2 IN1 Mux" },
2104
2105 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
2106 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
2107 { "Stereo2 ADC MIX", NULL, "Sto2 ADC MIXL" },
2108 { "Stereo2 ADC MIX", NULL, "Sto2 ADC MIXR" },
2109 { "Mono ADC MIX", NULL, "Mono ADC MIXL" },
2110 { "Mono ADC MIX", NULL, "Mono ADC MIXR" },
2111
2112 { "RxDP Mux", "IF2 DAC", "IF2 DAC" },
2113 { "RxDP Mux", "IF1 DAC", "IF1 DAC2" },
2114 { "RxDP Mux", "STO1 ADC Mixer", "Stereo1 ADC MIX" },
2115 { "RxDP Mux", "STO2 ADC Mixer", "Stereo2 ADC MIX" },
2116 { "RxDP Mux", "Mono ADC Mixer L", "Mono ADC MIXL" },
2117 { "RxDP Mux", "Mono ADC Mixer R", "Mono ADC MIXR" },
2118 { "RxDP Mux", "DAC1", "DAC MIX" },
2119
2120 { "TDM Data Mux", "Slot 0-1", "Stereo1 ADC MIX" },
2121 { "TDM Data Mux", "Slot 2-3", "Mono ADC MIX" },
2122 { "TDM Data Mux", "Slot 4-5", "Stereo2 ADC MIX" },
2123 { "TDM Data Mux", "Slot 6-7", "IF2 DAC" },
2124
2125 { "DSP UL Mux", "Bypass", "TDM Data Mux" },
2126 { "DSP UL Mux", NULL, "I2S DSP" },
2127 { "DSP DL Mux", "Bypass", "RxDP Mux" },
2128 { "DSP DL Mux", NULL, "I2S DSP" },
2129
2130 { "TxDP_ADC_L", NULL, "DSP UL Mux" },
2131 { "TxDP_ADC_R", NULL, "DSP UL Mux" },
2132 { "TxDC_DAC", NULL, "DSP DL Mux" },
2133
2134 { "TxDP_ADC", NULL, "TxDP_ADC_L" },
2135 { "TxDP_ADC", NULL, "TxDP_ADC_R" },
2136
2137 { "IF1 ADC", NULL, "I2S1" },
2138 { "IF1 ADC", NULL, "IF1_ADC1" },
2139 { "IF1 ADC", NULL, "IF1_ADC2" },
2140 { "IF1 ADC", NULL, "IF_ADC3" },
2141 { "IF1 ADC", NULL, "TxDP_ADC" },
2142
2143 { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },
2144 { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },
2145 { "IF2 ADC Mux", "IF_ADC3", "IF_ADC3" },
2146 { "IF2 ADC Mux", "TxDC_DAC", "TxDC_DAC" },
2147 { "IF2 ADC Mux", "TxDP_ADC", "TxDP_ADC" },
2148 { "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" },
2149
2150 { "IF2 ADC L", NULL, "IF2 ADC Mux" },
2151 { "IF2 ADC R", NULL, "IF2 ADC Mux" },
2152
2153 { "IF2 ADC", NULL, "I2S2" },
2154 { "IF2 ADC", NULL, "IF2 ADC L" },
2155 { "IF2 ADC", NULL, "IF2 ADC R" },
2156
2157 { "AIF1TX", NULL, "IF1 ADC" },
2158 { "AIF2TX", NULL, "IF2 ADC" },
2159
2160 { "IF1 DAC1", NULL, "AIF1RX" },
2161 { "IF1 DAC2", NULL, "AIF1RX" },
2162 { "IF2 DAC", NULL, "AIF2RX" },
2163
2164 { "IF1 DAC1", NULL, "I2S1" },
2165 { "IF1 DAC2", NULL, "I2S1" },
2166 { "IF2 DAC", NULL, "I2S2" },
2167
2168 { "IF1 DAC2 L", NULL, "IF1 DAC2" },
2169 { "IF1 DAC2 R", NULL, "IF1 DAC2" },
2170 { "IF1 DAC1 L", NULL, "IF1 DAC1" },
2171 { "IF1 DAC1 R", NULL, "IF1 DAC1" },
2172 { "IF2 DAC L", NULL, "IF2 DAC" },
2173 { "IF2 DAC R", NULL, "IF2 DAC" },
2174
2175 { "DAC1 L Mux", "IF1 DAC", "IF1 DAC1 L" },
2176 { "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" },
2177
2178 { "DAC1 R Mux", "IF1 DAC", "IF1 DAC1 R" },
2179 { "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" },
2180
2181 { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" },
2182 { "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" },
2183 { "DAC1 MIXL", NULL, "DAC Stereo1 Filter" },
2184 { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" },
2185 { "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" },
2186 { "DAC1 MIXR", NULL, "DAC Stereo1 Filter" },
2187
96927ac9
BL		 2188 { "DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll },
2189 { "DAC Mono Left Filter", NULL, "PLL1", is_sys_clk_from_pll },
2190 { "DAC Mono Right Filter", NULL, "PLL1", is_sys_clk_from_pll },
2191
5e8351de
BL		 2192 { "DAC MIX", NULL, "DAC1 MIXL" },
2193 { "DAC MIX", NULL, "DAC1 MIXR" },
2194
2195 { "Audio DSP", NULL, "DAC1 MIXL" },
2196 { "Audio DSP", NULL, "DAC1 MIXR" },
2197
2198 { "DAC L2 Mux", "IF1 DAC", "IF1 DAC2 L" },
2199 { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
2200 { "DAC L2 Mux", "TxDC DAC", "TxDC_DAC" },
2201 { "DAC L2 Mux", "VAD_ADC", "VAD_ADC" },
2202 { "DAC L2 Volume", NULL, "DAC L2 Mux" },
2203 { "DAC L2 Volume", NULL, "DAC Mono Left Filter" },
2204
2205 { "DAC R2 Mux", "IF1 DAC", "IF1 DAC2 R" },
2206 { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
2207 { "DAC R2 Mux", "TxDC DAC", "TxDC_DAC" },
2208 { "DAC R2 Mux", "TxDP ADC", "TxDP_ADC" },
2209 { "DAC R2 Volume", NULL, "DAC R2 Mux" },
2210 { "DAC R2 Volume", NULL, "DAC Mono Right Filter" },
2211
2212 { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
2213 { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
2214 { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2215 { "Stereo DAC MIXL", NULL, "DAC Stereo1 Filter" },
2216 { "Stereo DAC MIXL", NULL, "DAC L1 Power" },
2217 { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
2218 { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
2219 { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2220 { "Stereo DAC MIXR", NULL, "DAC Stereo1 Filter" },
2221 { "Stereo DAC MIXR", NULL, "DAC R1 Power" },
2222
2223 { "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
2224 { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2225 { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
2226 { "Mono DAC MIXL", NULL, "DAC Mono Left Filter" },
2227 { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
2228 { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2229 { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
2230 { "Mono DAC MIXR", NULL, "DAC Mono Right Filter" },
2231
2232 { "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
2233 { "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2234 { "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
2235 { "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
2236 { "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2237 { "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
2238
2239 { "DAC L1", NULL, "DAC L1 Power" },
2240 { "DAC L1", NULL, "Stereo DAC MIXL" },
5e8351de
BL		 2241 { "DAC R1", NULL, "DAC R1 Power" },
2242 { "DAC R1", NULL, "Stereo DAC MIXR" },
5e8351de 2243 { "DAC L2", NULL, "Mono DAC MIXL" },
5e8351de 2244 { "DAC R2", NULL, "Mono DAC MIXR" },
5e8351de
BL		 2245
2246 { "OUT MIXL", "BST1 Switch", "BST1" },
2247 { "OUT MIXL", "INL Switch", "INL VOL" },
2248 { "OUT MIXL", "DAC L2 Switch", "DAC L2" },
2249 { "OUT MIXL", "DAC L1 Switch", "DAC L1" },
2250
2251 { "OUT MIXR", "BST2 Switch", "BST2" },
2252 { "OUT MIXR", "INR Switch", "INR VOL" },
2253 { "OUT MIXR", "DAC R2 Switch", "DAC R2" },
2254 { "OUT MIXR", "DAC R1 Switch", "DAC R1" },
2255
2256 { "HPOVOL MIXL", "DAC1 Switch", "DAC L1" },
2257 { "HPOVOL MIXL", "INL Switch", "INL VOL" },
2258 { "HPOVOL MIXR", "DAC1 Switch", "DAC R1" },
2259 { "HPOVOL MIXR", "INR Switch", "INR VOL" },
2260
2261 { "DAC 2", NULL, "DAC L2" },
2262 { "DAC 2", NULL, "DAC R2" },
2263 { "DAC 1", NULL, "DAC L1" },
2264 { "DAC 1", NULL, "DAC R1" },
2265 { "HPOVOL", NULL, "HPOVOL MIXL" },
2266 { "HPOVOL", NULL, "HPOVOL MIXR" },
2267 { "HPO MIX", "DAC1 Switch", "DAC 1" },
2268 { "HPO MIX", "HPVOL Switch", "HPOVOL" },
2269
2270 { "LOUT MIX", "DAC L1 Switch", "DAC L1" },
2271 { "LOUT MIX", "DAC R1 Switch", "DAC R1" },
2272 { "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" },
2273 { "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" },
2274
2275 { "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" },
2276 { "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" },
2277 { "PDM1 L Mux", NULL, "PDM1 Power" },
2278 { "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" },
2279 { "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" },
2280 { "PDM1 R Mux", NULL, "PDM1 Power" },
5e8351de
BL		 2281
2282 { "HP Amp", NULL, "HPO MIX" },
2283 { "HP Amp", NULL, "Mic Det Power" },
2284 { "HPOL", NULL, "HP Amp" },
2285 { "HPOL", NULL, "HP L Amp" },
2286 { "HPOL", NULL, "Improve HP Amp Drv" },
2287 { "HPOR", NULL, "HP Amp" },
2288 { "HPOR", NULL, "HP R Amp" },
2289 { "HPOR", NULL, "Improve HP Amp Drv" },
2290
2291 { "LOUT Amp", NULL, "LOUT MIX" },
2292 { "LOUT L Playback", "Switch", "LOUT Amp" },
2293 { "LOUT R Playback", "Switch", "LOUT Amp" },
2294 { "LOUTL", NULL, "LOUT L Playback" },
2295 { "LOUTR", NULL, "LOUT R Playback" },
2296 { "LOUTL", NULL, "Improve HP Amp Drv" },
2297 { "LOUTR", NULL, "Improve HP Amp Drv" },
0cf18632 2298};
5e8351de 2299
0cf18632
BL		 2300static const struct snd_soc_dapm_route rt5670_specific_dapm_routes[] = {
2301 { "PDM2 L Mux", "Stereo DAC", "Stereo DAC MIXL" },
2302 { "PDM2 L Mux", "Mono DAC", "Mono DAC MIXL" },
2303 { "PDM2 L Mux", NULL, "PDM2 Power" },
2304 { "PDM2 R Mux", "Stereo DAC", "Stereo DAC MIXR" },
2305 { "PDM2 R Mux", "Mono DAC", "Mono DAC MIXR" },
2306 { "PDM2 R Mux", NULL, "PDM2 Power" },
5e8351de
BL		 2307 { "PDM1L", NULL, "PDM1 L Mux" },
2308 { "PDM1R", NULL, "PDM1 R Mux" },
2309 { "PDM2L", NULL, "PDM2 L Mux" },
2310 { "PDM2R", NULL, "PDM2 R Mux" },
2311};
2312
0cf18632
BL		 2313static const struct snd_soc_dapm_route rt5672_specific_dapm_routes[] = {
2314 { "SPO Amp", NULL, "PDM1 L Mux" },
2315 { "SPO Amp", NULL, "PDM1 R Mux" },
2316 { "SPOLP", NULL, "SPO Amp" },
2317 { "SPOLN", NULL, "SPO Amp" },
2318 { "SPORP", NULL, "SPO Amp" },
2319 { "SPORN", NULL, "SPO Amp" },
2320};
2321
5e8351de
BL		 2322static int rt5670_hw_params(struct snd_pcm_substream *substream,
2323 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2324{
2325 struct snd_soc_codec *codec = dai->codec;
2326 struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
2327 unsigned int val_len = 0, val_clk, mask_clk;
2328 int pre_div, bclk_ms, frame_size;
2329
2330 rt5670->lrck[dai->id] = params_rate(params);
2331 pre_div = rl6231_get_clk_info(rt5670->sysclk, rt5670->lrck[dai->id]);
2332 if (pre_div < 0) {
2333 dev_err(codec->dev, "Unsupported clock setting %d for DAI %d\n",
2334 rt5670->lrck[dai->id], dai->id);
2335 return -EINVAL;
2336 }
2337 frame_size = snd_soc_params_to_frame_size(params);
2338 if (frame_size < 0) {
2339 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
2340 return -EINVAL;
2341 }
2342 bclk_ms = frame_size > 32;
2343 rt5670->bclk[dai->id] = rt5670->lrck[dai->id] * (32 << bclk_ms);
2344
2345 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
2346 rt5670->bclk[dai->id], rt5670->lrck[dai->id]);
2347 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
2348 bclk_ms, pre_div, dai->id);
2349
2350 switch (params_width(params)) {
2351 case 16:
2352 break;
2353 case 20:
2354 val_len |= RT5670_I2S_DL_20;
2355 break;
2356 case 24:
2357 val_len |= RT5670_I2S_DL_24;
2358 break;
2359 case 8:
2360 val_len |= RT5670_I2S_DL_8;
2361 break;
2362 default:
2363 return -EINVAL;
2364 }
2365
2366 switch (dai->id) {
2367 case RT5670_AIF1:
2368 mask_clk = RT5670_I2S_BCLK_MS1_MASK | RT5670_I2S_PD1_MASK;
2369 val_clk = bclk_ms << RT5670_I2S_BCLK_MS1_SFT |
2370 pre_div << RT5670_I2S_PD1_SFT;
2371 snd_soc_update_bits(codec, RT5670_I2S1_SDP,
2372 RT5670_I2S_DL_MASK, val_len);
2373 snd_soc_update_bits(codec, RT5670_ADDA_CLK1, mask_clk, val_clk);
2374 break;
2375 case RT5670_AIF2:
2376 mask_clk = RT5670_I2S_BCLK_MS2_MASK | RT5670_I2S_PD2_MASK;
2377 val_clk = bclk_ms << RT5670_I2S_BCLK_MS2_SFT |
2378 pre_div << RT5670_I2S_PD2_SFT;
2379 snd_soc_update_bits(codec, RT5670_I2S2_SDP,
2380 RT5670_I2S_DL_MASK, val_len);
2381 snd_soc_update_bits(codec, RT5670_ADDA_CLK1, mask_clk, val_clk);
2382 break;
2383 default:
2384 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2385 return -EINVAL;
2386 }
2387
2388 return 0;
2389}
2390
2391static int rt5670_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2392{
2393 struct snd_soc_codec *codec = dai->codec;
2394 struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
2395 unsigned int reg_val = 0;
2396
2397 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2398 case SND_SOC_DAIFMT_CBM_CFM:
2399 rt5670->master[dai->id] = 1;
2400 break;
2401 case SND_SOC_DAIFMT_CBS_CFS:
2402 reg_val |= RT5670_I2S_MS_S;
2403 rt5670->master[dai->id] = 0;
2404 break;
2405 default:
2406 return -EINVAL;
2407 }
2408
2409 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2410 case SND_SOC_DAIFMT_NB_NF:
2411 break;
2412 case SND_SOC_DAIFMT_IB_NF:
2413 reg_val |= RT5670_I2S_BP_INV;
2414 break;
2415 default:
2416 return -EINVAL;
2417 }
2418
2419 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2420 case SND_SOC_DAIFMT_I2S:
2421 break;
2422 case SND_SOC_DAIFMT_LEFT_J:
2423 reg_val |= RT5670_I2S_DF_LEFT;
2424 break;
2425 case SND_SOC_DAIFMT_DSP_A:
2426 reg_val |= RT5670_I2S_DF_PCM_A;
2427 break;
2428 case SND_SOC_DAIFMT_DSP_B:
2429 reg_val |= RT5670_I2S_DF_PCM_B;
2430 break;
2431 default:
2432 return -EINVAL;
2433 }
2434
2435 switch (dai->id) {
2436 case RT5670_AIF1:
2437 snd_soc_update_bits(codec, RT5670_I2S1_SDP,
2438 RT5670_I2S_MS_MASK | RT5670_I2S_BP_MASK |
2439 RT5670_I2S_DF_MASK, reg_val);
2440 break;
2441 case RT5670_AIF2:
2442 snd_soc_update_bits(codec, RT5670_I2S2_SDP,
2443 RT5670_I2S_MS_MASK | RT5670_I2S_BP_MASK |
2444 RT5670_I2S_DF_MASK, reg_val);
2445 break;
2446 default:
2447 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2448 return -EINVAL;
2449 }
2450 return 0;
2451}
2452
c243d963 2453static int rt5670_set_codec_sysclk(struct snd_soc_codec *codec, int clk_id,
6c28ce3c 2454 int source, unsigned int freq, int dir)
5e8351de 2455{
5e8351de
BL		 2456 struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
2457 unsigned int reg_val = 0;
2458
5e8351de
BL		 2459 switch (clk_id) {
2460 case RT5670_SCLK_S_MCLK:
2461 reg_val |= RT5670_SCLK_SRC_MCLK;
2462 break;
2463 case RT5670_SCLK_S_PLL1:
2464 reg_val |= RT5670_SCLK_SRC_PLL1;
2465 break;
2466 case RT5670_SCLK_S_RCCLK:
2467 reg_val |= RT5670_SCLK_SRC_RCCLK;
2468 break;
2469 default:
2470 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
2471 return -EINVAL;
2472 }
2473 snd_soc_update_bits(codec, RT5670_GLB_CLK,
2474 RT5670_SCLK_SRC_MASK, reg_val);
2475 rt5670->sysclk = freq;
485372dc
BL		 2476 if (clk_id != RT5670_SCLK_S_RCCLK)
2477 rt5670->sysclk_src = clk_id;
5e8351de 2478
6c28ce3c 2479 dev_dbg(codec->dev, "Sysclk : %dHz clock id : %d\n", freq, clk_id);
5e8351de
BL		 2480
2481 return 0;
2482}
2483
2484static int rt5670_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2485 unsigned int freq_in, unsigned int freq_out)
2486{
2487 struct snd_soc_codec *codec = dai->codec;
2488 struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
2489 struct rl6231_pll_code pll_code;
2490 int ret;
2491
2492 if (source == rt5670->pll_src && freq_in == rt5670->pll_in &&
2493 freq_out == rt5670->pll_out)
2494 return 0;
2495
2496 if (!freq_in || !freq_out) {
2497 dev_dbg(codec->dev, "PLL disabled\n");
2498
2499 rt5670->pll_in = 0;
2500 rt5670->pll_out = 0;
2501 snd_soc_update_bits(codec, RT5670_GLB_CLK,
2502 RT5670_SCLK_SRC_MASK, RT5670_SCLK_SRC_MCLK);
2503 return 0;
2504 }
2505
2506 switch (source) {
2507 case RT5670_PLL1_S_MCLK:
2508 snd_soc_update_bits(codec, RT5670_GLB_CLK,
2509 RT5670_PLL1_SRC_MASK, RT5670_PLL1_SRC_MCLK);
2510 break;
2511 case RT5670_PLL1_S_BCLK1:
2512 case RT5670_PLL1_S_BCLK2:
2513 case RT5670_PLL1_S_BCLK3:
2514 case RT5670_PLL1_S_BCLK4:
2515 switch (dai->id) {
2516 case RT5670_AIF1:
2517 snd_soc_update_bits(codec, RT5670_GLB_CLK,
2518 RT5670_PLL1_SRC_MASK, RT5670_PLL1_SRC_BCLK1);
2519 break;
2520 case RT5670_AIF2:
2521 snd_soc_update_bits(codec, RT5670_GLB_CLK,
2522 RT5670_PLL1_SRC_MASK, RT5670_PLL1_SRC_BCLK2);
2523 break;
2524 default:
2525 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2526 return -EINVAL;
2527 }
2528 break;
2529 default:
2530 dev_err(codec->dev, "Unknown PLL source %d\n", source);
2531 return -EINVAL;
2532 }
2533
2534 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2535 if (ret < 0) {
2536 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
2537 return ret;
2538 }
2539
2540 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
2541 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2542 pll_code.n_code, pll_code.k_code);
2543
2544 snd_soc_write(codec, RT5670_PLL_CTRL1,
2545 pll_code.n_code << RT5670_PLL_N_SFT | pll_code.k_code);
2546 snd_soc_write(codec, RT5670_PLL_CTRL2,
2547 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5670_PLL_M_SFT |
2548 pll_code.m_bp << RT5670_PLL_M_BP_SFT);
2549
2550 rt5670->pll_in = freq_in;
2551 rt5670->pll_out = freq_out;
2552 rt5670->pll_src = source;
2553
2554 return 0;
2555}
2556
2557static int rt5670_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2558 unsigned int rx_mask, int slots, int slot_width)
2559{
2560 struct snd_soc_codec *codec = dai->codec;
2561 unsigned int val = 0;
2562
2563 if (rx_mask || tx_mask)
2564 val |= (1 << 14);
2565
2566 switch (slots) {
2567 case 4:
2568 val |= (1 << 12);
2569 break;
2570 case 6:
2571 val |= (2 << 12);
2572 break;
2573 case 8:
2574 val |= (3 << 12);
2575 break;
2576 case 2:
2577 break;
2578 default:
2579 return -EINVAL;
2580 }
2581
2582 switch (slot_width) {
2583 case 20:
2584 val |= (1 << 10);
2585 break;
2586 case 24:
2587 val |= (2 << 10);
2588 break;
2589 case 32:
2590 val |= (3 << 10);
2591 break;
2592 case 16:
2593 break;
2594 default:
2595 return -EINVAL;
2596 }
2597
2598 snd_soc_update_bits(codec, RT5670_TDM_CTRL_1, 0x7c00, val);
2599
2600 return 0;
2601}
2602
d0817657
BL		 2603static int rt5670_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2604{
2605 struct snd_soc_codec *codec = dai->codec;
2606
2607 dev_dbg(codec->dev, "%s ratio=%d\n", __func__, ratio);
2608 if (dai->id != RT5670_AIF1)
2609 return 0;
2610
2611 if ((ratio % 50) == 0)
2612 snd_soc_update_bits(codec, RT5670_GEN_CTRL3,
2613 RT5670_TDM_DATA_MODE_SEL, RT5670_TDM_DATA_MODE_50FS);
2614 else
2615 snd_soc_update_bits(codec, RT5670_GEN_CTRL3,
2616 RT5670_TDM_DATA_MODE_SEL, RT5670_TDM_DATA_MODE_NOR);
2617
2618 return 0;
2619}
2620
5e8351de
BL		 2621static int rt5670_set_bias_level(struct snd_soc_codec *codec,
2622 enum snd_soc_bias_level level)
2623{
044b724a
BL		 2624 struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
2625
5e8351de
BL		 2626 switch (level) {
2627 case SND_SOC_BIAS_PREPARE:
6d8135ff 2628 if (SND_SOC_BIAS_STANDBY == snd_soc_codec_get_bias_level(codec)) {
5e8351de
BL		 2629 snd_soc_update_bits(codec, RT5670_PWR_ANLG1,
2630 RT5670_PWR_VREF1 | RT5670_PWR_MB |
2631 RT5670_PWR_BG | RT5670_PWR_VREF2,
2632 RT5670_PWR_VREF1 | RT5670_PWR_MB |
2633 RT5670_PWR_BG | RT5670_PWR_VREF2);
2634 mdelay(10);
2635 snd_soc_update_bits(codec, RT5670_PWR_ANLG1,
2636 RT5670_PWR_FV1 | RT5670_PWR_FV2,
2637 RT5670_PWR_FV1 | RT5670_PWR_FV2);
2638 snd_soc_update_bits(codec, RT5670_CHARGE_PUMP,
2639 RT5670_OSW_L_MASK | RT5670_OSW_R_MASK,
2640 RT5670_OSW_L_DIS | RT5670_OSW_R_DIS);
2641 snd_soc_update_bits(codec, RT5670_DIG_MISC, 0x1, 0x1);
2642 snd_soc_update_bits(codec, RT5670_PWR_ANLG1,
c8c6f0d8 2643 RT5670_LDO_SEL_MASK, 0x5);
5e8351de
BL		 2644 }
2645 break;
2646 case SND_SOC_BIAS_STANDBY:
044b724a
BL		 2647 snd_soc_update_bits(codec, RT5670_PWR_ANLG1,
2648 RT5670_PWR_VREF1 | RT5670_PWR_VREF2 |
2649 RT5670_PWR_FV1 | RT5670_PWR_FV2, 0);
5e8351de 2650 snd_soc_update_bits(codec, RT5670_PWR_ANLG1,
c8c6f0d8 2651 RT5670_LDO_SEL_MASK, 0x3);
5e8351de 2652 break;
044b724a
BL		 2653 case SND_SOC_BIAS_OFF:
2654 if (rt5670->pdata.jd_mode)
2655 snd_soc_update_bits(codec, RT5670_PWR_ANLG1,
2656 RT5670_PWR_VREF1 | RT5670_PWR_MB |
2657 RT5670_PWR_BG | RT5670_PWR_VREF2 |
2658 RT5670_PWR_FV1 | RT5670_PWR_FV2,
2659 RT5670_PWR_MB | RT5670_PWR_BG);
2660 else
2661 snd_soc_update_bits(codec, RT5670_PWR_ANLG1,
2662 RT5670_PWR_VREF1 | RT5670_PWR_MB |
2663 RT5670_PWR_BG | RT5670_PWR_VREF2 |
2664 RT5670_PWR_FV1 | RT5670_PWR_FV2, 0);
2665
2666 snd_soc_update_bits(codec, RT5670_DIG_MISC, 0x1, 0x0);
2667 break;
5e8351de
BL		 2668
2669 default:
2670 break;
2671 }
5e8351de
BL		 2672
2673 return 0;
2674}
2675
2676static int rt5670_probe(struct snd_soc_codec *codec)
2677{
6d8135ff 2678 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
5e8351de
BL		 2679 struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
2680
0cf18632
BL		 2681 switch (snd_soc_read(codec, RT5670_RESET) & RT5670_ID_MASK) {
2682 case RT5670_ID_5670:
2683 case RT5670_ID_5671:
6d8135ff 2684 snd_soc_dapm_new_controls(dapm,
0cf18632
BL		 2685 rt5670_specific_dapm_widgets,
2686 ARRAY_SIZE(rt5670_specific_dapm_widgets));
6d8135ff 2687 snd_soc_dapm_add_routes(dapm,
0cf18632
BL		 2688 rt5670_specific_dapm_routes,
2689 ARRAY_SIZE(rt5670_specific_dapm_routes));
2690 break;
2691 case RT5670_ID_5672:
6d8135ff 2692 snd_soc_dapm_new_controls(dapm,
0cf18632
BL		 2693 rt5672_specific_dapm_widgets,
2694 ARRAY_SIZE(rt5672_specific_dapm_widgets));
6d8135ff 2695 snd_soc_dapm_add_routes(dapm,
0cf18632
BL		 2696 rt5672_specific_dapm_routes,
2697 ARRAY_SIZE(rt5672_specific_dapm_routes));
2698 break;
2699 default:
2700 dev_err(codec->dev,
2701 "The driver is for RT5670 RT5671 or RT5672 only\n");
2702 return -ENODEV;
2703 }
5e8351de
BL		 2704 rt5670->codec = codec;
2705
2706 return 0;
2707}
2708
2709static int rt5670_remove(struct snd_soc_codec *codec)
2710{
2711 struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
2712
2713 regmap_write(rt5670->regmap, RT5670_RESET, 0);
d3ef7054 2714 snd_soc_jack_free_gpios(rt5670->jack, 1, &rt5670->hp_gpio);
5e8351de
BL		 2715 return 0;
2716}
2717
2718#ifdef CONFIG_PM
2719static int rt5670_suspend(struct snd_soc_codec *codec)
2720{
2721 struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
2722
2723 regcache_cache_only(rt5670->regmap, true);
2724 regcache_mark_dirty(rt5670->regmap);
2725 return 0;
2726}
2727
2728static int rt5670_resume(struct snd_soc_codec *codec)
2729{
2730 struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
2731
2732 regcache_cache_only(rt5670->regmap, false);
2733 regcache_sync(rt5670->regmap);
2734
2735 return 0;
2736}
2737#else
2738#define rt5670_suspend NULL
2739#define rt5670_resume NULL
2740#endif
2741
2742#define RT5670_STEREO_RATES SNDRV_PCM_RATE_8000_96000
2743#define RT5670_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
2744 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
2745
64793047 2746static const struct snd_soc_dai_ops rt5670_aif_dai_ops = {
5e8351de
BL		 2747 .hw_params = rt5670_hw_params,
2748 .set_fmt = rt5670_set_dai_fmt,
5e8351de
BL		 2749 .set_tdm_slot = rt5670_set_tdm_slot,
2750 .set_pll = rt5670_set_dai_pll,
d0817657 2751 .set_bclk_ratio = rt5670_set_bclk_ratio,
5e8351de
BL		 2752};
2753
ff62b958 2754static struct snd_soc_dai_driver rt5670_dai[] = {
5e8351de
BL		 2755 {
2756 .name = "rt5670-aif1",
2757 .id = RT5670_AIF1,
2758 .playback = {
2759 .stream_name = "AIF1 Playback",
2760 .channels_min = 1,
2761 .channels_max = 2,
2762 .rates = RT5670_STEREO_RATES,
2763 .formats = RT5670_FORMATS,
2764 },
2765 .capture = {
2766 .stream_name = "AIF1 Capture",
2767 .channels_min = 1,
2768 .channels_max = 2,
2769 .rates = RT5670_STEREO_RATES,
2770 .formats = RT5670_FORMATS,
2771 },
2772 .ops = &rt5670_aif_dai_ops,
8215313c 2773 .symmetric_rates = 1,
5e8351de
BL		 2774 },
2775 {
2776 .name = "rt5670-aif2",
2777 .id = RT5670_AIF2,
2778 .playback = {
2779 .stream_name = "AIF2 Playback",
2780 .channels_min = 1,
2781 .channels_max = 2,
2782 .rates = RT5670_STEREO_RATES,
2783 .formats = RT5670_FORMATS,
2784 },
2785 .capture = {
2786 .stream_name = "AIF2 Capture",
2787 .channels_min = 1,
2788 .channels_max = 2,
2789 .rates = RT5670_STEREO_RATES,
2790 .formats = RT5670_FORMATS,
2791 },
2792 .ops = &rt5670_aif_dai_ops,
8215313c 2793 .symmetric_rates = 1,
5e8351de
BL		 2794 },
2795};
2796
a180ba45 2797static const struct snd_soc_codec_driver soc_codec_dev_rt5670 = {
5e8351de
BL		 2798 .probe = rt5670_probe,
2799 .remove = rt5670_remove,
2800 .suspend = rt5670_suspend,
2801 .resume = rt5670_resume,
2802 .set_bias_level = rt5670_set_bias_level,
2803 .idle_bias_off = true,
6c28ce3c 2804 .set_sysclk = rt5670_set_codec_sysclk,
462fe794
KM		 2805 .component_driver = {
2806 .controls = rt5670_snd_controls,
2807 .num_controls = ARRAY_SIZE(rt5670_snd_controls),
2808 .dapm_widgets = rt5670_dapm_widgets,
2809 .num_dapm_widgets = ARRAY_SIZE(rt5670_dapm_widgets),
2810 .dapm_routes = rt5670_dapm_routes,
2811 .num_dapm_routes = ARRAY_SIZE(rt5670_dapm_routes),
2812 },
5e8351de
BL		 2813};
2814
2815static const struct regmap_config rt5670_regmap = {
2816 .reg_bits = 8,
2817 .val_bits = 16,
92b133f2 2818 .use_single_rw = true,
5e8351de
BL		 2819 .max_register = RT5670_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5670_ranges) *
2820 RT5670_PR_SPACING),
2821 .volatile_reg = rt5670_volatile_register,
2822 .readable_reg = rt5670_readable_register,
2823 .cache_type = REGCACHE_RBTREE,
2824 .reg_defaults = rt5670_reg,
2825 .num_reg_defaults = ARRAY_SIZE(rt5670_reg),
2826 .ranges = rt5670_ranges,
2827 .num_ranges = ARRAY_SIZE(rt5670_ranges),
2828};
2829
2830static const struct i2c_device_id rt5670_i2c_id[] = {
2831 { "rt5670", 0 },
0cf18632
BL		 2832 { "rt5671", 0 },
2833 { "rt5672", 0 },
5e8351de
BL		 2834 { }
2835};
2836MODULE_DEVICE_TABLE(i2c, rt5670_i2c_id);
2837
0605815e 2838#ifdef CONFIG_ACPI
4e0ce6a4 2839static const struct acpi_device_id rt5670_acpi_match[] = {
0605815e 2840 { "10EC5670", 0},
d2528006 2841 { "10EC5672", 0},
93ffeaa8 2842 { "10EC5640", 0}, /* quirk */
0605815e
ML		 2843 { },
2844};
2845MODULE_DEVICE_TABLE(acpi, rt5670_acpi_match);
2846#endif
2847
8e1b1785
PLB		 2848static int rt5670_quirk_cb(const struct dmi_system_id *id)
2849{
2850 rt5670_quirk = (unsigned long)id->driver_data;
2851 return 1;
2852}
2853
2854static const struct dmi_system_id dmi_platform_intel_quirks[] = {
223c055a 2855 {
8e1b1785 2856 .callback = rt5670_quirk_cb,
223c055a
BL		 2857 .ident = "Intel Braswell",
2858 .matches = {
2859 DMI_MATCH(DMI_SYS_VENDOR, "Intel Corporation"),
2860 DMI_MATCH(DMI_BOARD_NAME, "Braswell CRB"),
2861 },
8e1b1785
PLB		 2862 .driver_data = (unsigned long *)(RT5670_DMIC_EN |
2863 RT5670_DMIC1_IN2P |
2864 RT5670_DEV_GPIO |
2865 RT5670_JD_MODE1),
223c055a 2866 },
b4ff47d2 2867 {
8e1b1785 2868 .callback = rt5670_quirk_cb,
b4ff47d2
TI		 2869 .ident = "Dell Wyse 3040",
2870 .matches = {
2871 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
2872 DMI_MATCH(DMI_PRODUCT_NAME, "Wyse 3040"),
2873 },
8e1b1785
PLB		 2874 .driver_data = (unsigned long *)(RT5670_DMIC_EN |
2875 RT5670_DMIC1_IN2P |
2876 RT5670_DEV_GPIO |
2877 RT5670_JD_MODE1),
b4ff47d2 2878 },
67e03ff3 2879 {
8e1b1785 2880 .callback = rt5670_quirk_cb,
67e03ff3
NF		 2881 .ident = "Lenovo Thinkpad Tablet 10",
2882 .matches = {
2883 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
2884 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad 10"),
2885 },
8e1b1785
PLB		 2886 .driver_data = (unsigned long *)(RT5670_DMIC_EN |
2887 RT5670_DMIC1_IN2P |
2888 RT5670_DEV_GPIO |
2889 RT5670_JD_MODE1),
67e03ff3
NF		 2890 },
2891 {
8e1b1785 2892 .callback = rt5670_quirk_cb,
67e03ff3
NF		 2893 .ident = "Lenovo Thinkpad Tablet 10",
2894 .matches = {
2895 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
2896 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad Tablet B"),
2897 },
8e1b1785
PLB		 2898 .driver_data = (unsigned long *)(RT5670_DMIC_EN |
2899 RT5670_DMIC1_IN2P |
2900 RT5670_DEV_GPIO |
2901 RT5670_JD_MODE1),
67e03ff3
NF		 2902 },
2903 {
8e1b1785 2904 .callback = rt5670_quirk_cb,
67e03ff3
NF		 2905 .ident = "Lenovo Thinkpad Tablet 10",
2906 .matches = {
2907 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
2908 DMI_MATCH(DMI_PRODUCT_VERSION, "Lenovo Miix 2 10"),
2909 },
8e1b1785
PLB		 2910 .driver_data = (unsigned long *)(RT5670_DMIC_EN |
2911 RT5670_DMIC1_IN2P |
2912 RT5670_DEV_GPIO |
2913 RT5670_JD_MODE2),
67e03ff3 2914 },
c26d8389 2915 {
8e1b1785 2916 .callback = rt5670_quirk_cb,
c26d8389
PLB		 2917 .ident = "Dell Venue 8 Pro 5855",
2918 .matches = {
2919 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
2920 DMI_MATCH(DMI_PRODUCT_NAME, "Venue 8 Pro 5855"),
2921 },
8e1b1785
PLB		 2922 .driver_data = (unsigned long *)(RT5670_DMIC_EN |
2923 RT5670_DMIC2_INR |
2924 RT5670_DEV_GPIO |
2925 RT5670_JD_MODE3),
c26d8389
PLB		 2926 },
2927 {}
2928};
2929
5e8351de
BL		 2930static int rt5670_i2c_probe(struct i2c_client *i2c,
2931 const struct i2c_device_id *id)
2932{
2933 struct rt5670_platform_data *pdata = dev_get_platdata(&i2c->dev);
2934 struct rt5670_priv *rt5670;
2935 int ret;
2936 unsigned int val;
2937
2938 rt5670 = devm_kzalloc(&i2c->dev,
2939 sizeof(struct rt5670_priv),
2940 GFP_KERNEL);
2941 if (NULL == rt5670)
2942 return -ENOMEM;
2943
2944 i2c_set_clientdata(i2c, rt5670);
2945
2946 if (pdata)
2947 rt5670->pdata = *pdata;
2948
8e1b1785
PLB		 2949 dmi_check_system(dmi_platform_intel_quirks);
2950 if (quirk_override) {
2951 dev_info(&i2c->dev, "Overriding quirk 0x%x => 0x%x\n",
2952 (unsigned int)rt5670_quirk, quirk_override);
2953 rt5670_quirk = quirk_override;
2954 }
2955
2956 if (rt5670_quirk & RT5670_DEV_GPIO) {
d3ef7054 2957 rt5670->pdata.dev_gpio = true;
8e1b1785
PLB		 2958 dev_info(&i2c->dev, "quirk dev_gpio\n");
2959 }
2960 if (rt5670_quirk & RT5670_IN2_DIFF) {
2961 rt5670->pdata.in2_diff = true;
2962 dev_info(&i2c->dev, "quirk IN2_DIFF\n");
2963 }
2964 if (rt5670_quirk & RT5670_DMIC_EN) {
8cffb503 2965 rt5670->pdata.dmic_en = true;
8e1b1785
PLB		 2966 dev_info(&i2c->dev, "quirk DMIC enabled\n");
2967 }
2968 if (rt5670_quirk & RT5670_DMIC1_IN2P) {
8cffb503 2969 rt5670->pdata.dmic1_data_pin = RT5670_DMIC_DATA_IN2P;
8e1b1785
PLB		 2970 dev_info(&i2c->dev, "quirk DMIC1 on IN2P pin\n");
2971 }
2972 if (rt5670_quirk & RT5670_DMIC1_GPIO6) {
2973 rt5670->pdata.dmic1_data_pin = RT5670_DMIC_DATA_GPIO6;
2974 dev_info(&i2c->dev, "quirk DMIC1 on GPIO6 pin\n");
2975 }
2976 if (rt5670_quirk & RT5670_DMIC1_GPIO7) {
2977 rt5670->pdata.dmic1_data_pin = RT5670_DMIC_DATA_GPIO7;
2978 dev_info(&i2c->dev, "quirk DMIC1 on GPIO7 pin\n");
2979 }
2980 if (rt5670_quirk & RT5670_DMIC2_INR) {
2981 rt5670->pdata.dmic2_data_pin = RT5670_DMIC_DATA_IN3N;
2982 dev_info(&i2c->dev, "quirk DMIC2 on INR pin\n");
2983 }
2984 if (rt5670_quirk & RT5670_DMIC2_GPIO8) {
2985 rt5670->pdata.dmic2_data_pin = RT5670_DMIC_DATA_GPIO8;
2986 dev_info(&i2c->dev, "quirk DMIC2 on GPIO8 pin\n");
2987 }
2988 if (rt5670_quirk & RT5670_DMIC3_GPIO5) {
2989 rt5670->pdata.dmic3_data_pin = RT5670_DMIC_DATA_GPIO5;
2990 dev_info(&i2c->dev, "quirk DMIC3 on GPIO5 pin\n");
2991 }
2992
2993 if (rt5670_quirk & RT5670_JD_MODE1) {
2994 rt5670->pdata.jd_mode = 1;
2995 dev_info(&i2c->dev, "quirk JD mode 1\n");
2996 }
2997 if (rt5670_quirk & RT5670_JD_MODE2) {
8cffb503 2998 rt5670->pdata.jd_mode = 2;
8e1b1785
PLB		 2999 dev_info(&i2c->dev, "quirk JD mode 2\n");
3000 }
3001 if (rt5670_quirk & RT5670_JD_MODE3) {
c26d8389 3002 rt5670->pdata.jd_mode = 3;
8e1b1785 3003 dev_info(&i2c->dev, "quirk JD mode 3\n");
223c055a
BL		 3004 }
3005
5e8351de
BL		 3006 rt5670->regmap = devm_regmap_init_i2c(i2c, &rt5670_regmap);
3007 if (IS_ERR(rt5670->regmap)) {
3008 ret = PTR_ERR(rt5670->regmap);
3009 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
3010 ret);
3011 return ret;
3012 }
3013
3014 regmap_read(rt5670->regmap, RT5670_VENDOR_ID2, &val);
3015 if (val != RT5670_DEVICE_ID) {
3016 dev_err(&i2c->dev,
387ad57f 3017 "Device with ID register %#x is not rt5670/72\n", val);
5e8351de
BL		 3018 return -ENODEV;
3019 }
3020
3021 regmap_write(rt5670->regmap, RT5670_RESET, 0);
3022 regmap_update_bits(rt5670->regmap, RT5670_PWR_ANLG1,
3023 RT5670_PWR_HP_L | RT5670_PWR_HP_R |
3024 RT5670_PWR_VREF2, RT5670_PWR_VREF2);
3025 msleep(100);
3026
3027 regmap_write(rt5670->regmap, RT5670_RESET, 0);
3028
2bf9eba1
BL		 3029 regmap_read(rt5670->regmap, RT5670_VENDOR_ID, &val);
3030 if (val >= 4)
3031 regmap_write(rt5670->regmap, RT5670_GPIO_CTRL3, 0x0980);
3032 else
3033 regmap_write(rt5670->regmap, RT5670_GPIO_CTRL3, 0x0d00);
3034
5e8351de
BL		 3035 ret = regmap_register_patch(rt5670->regmap, init_list,
3036 ARRAY_SIZE(init_list));
3037 if (ret != 0)
3038 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
3039
a5d93da1
BL		 3040 regmap_update_bits(rt5670->regmap, RT5670_DIG_MISC,
3041 RT5670_MCLK_DET, RT5670_MCLK_DET);
3042
5e8351de
BL		 3043 if (rt5670->pdata.in2_diff)
3044 regmap_update_bits(rt5670->regmap, RT5670_IN2,
3045 RT5670_IN_DF2, RT5670_IN_DF2);
3046
d3ef7054
BL		 3047 if (rt5670->pdata.dev_gpio) {
3048 /* for push button */
3049 regmap_write(rt5670->regmap, RT5670_IL_CMD, 0x0000);
3050 regmap_write(rt5670->regmap, RT5670_IL_CMD2, 0x0010);
3051 regmap_write(rt5670->regmap, RT5670_IL_CMD3, 0x0014);
3052 /* for irq */
5e8351de
BL		 3053 regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL1,
3054 RT5670_GP1_PIN_MASK, RT5670_GP1_PIN_IRQ);
3055 regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL2,
3056 RT5670_GP1_PF_MASK, RT5670_GP1_PF_OUT);
5e8351de
BL		 3057 }
3058
3059 if (rt5670->pdata.jd_mode) {
026e7368
BL		 3060 regmap_update_bits(rt5670->regmap, RT5670_GLB_CLK,
3061 RT5670_SCLK_SRC_MASK, RT5670_SCLK_SRC_RCCLK);
3062 rt5670->sysclk = 0;
3063 rt5670->sysclk_src = RT5670_SCLK_S_RCCLK;
5e8351de
BL		 3064 regmap_update_bits(rt5670->regmap, RT5670_PWR_ANLG1,
3065 RT5670_PWR_MB, RT5670_PWR_MB);
3066 regmap_update_bits(rt5670->regmap, RT5670_PWR_ANLG2,
3067 RT5670_PWR_JD1, RT5670_PWR_JD1);
3068 regmap_update_bits(rt5670->regmap, RT5670_IRQ_CTRL1,
3069 RT5670_JD1_1_EN_MASK, RT5670_JD1_1_EN);
3070 regmap_update_bits(rt5670->regmap, RT5670_JD_CTRL3,
3071 RT5670_JD_TRI_CBJ_SEL_MASK |
3072 RT5670_JD_TRI_HPO_SEL_MASK,
3073 RT5670_JD_CBJ_JD1_1 | RT5670_JD_HPO_JD1_1);
3074 switch (rt5670->pdata.jd_mode) {
3075 case 1:
3076 regmap_update_bits(rt5670->regmap, RT5670_A_JD_CTRL1,
3077 RT5670_JD1_MODE_MASK,
3078 RT5670_JD1_MODE_0);
3079 break;
3080 case 2:
3081 regmap_update_bits(rt5670->regmap, RT5670_A_JD_CTRL1,
3082 RT5670_JD1_MODE_MASK,
3083 RT5670_JD1_MODE_1);
3084 break;
3085 case 3:
3086 regmap_update_bits(rt5670->regmap, RT5670_A_JD_CTRL1,
3087 RT5670_JD1_MODE_MASK,
3088 RT5670_JD1_MODE_2);
3089 break;
3090 default:
3091 break;
3092 }
3093 }
3094
3095 if (rt5670->pdata.dmic_en) {
3096 regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL1,
3097 RT5670_GP2_PIN_MASK,
3098 RT5670_GP2_PIN_DMIC1_SCL);
3099
3100 switch (rt5670->pdata.dmic1_data_pin) {
3101 case RT5670_DMIC_DATA_IN2P:
3102 regmap_update_bits(rt5670->regmap, RT5670_DMIC_CTRL1,
3103 RT5670_DMIC_1_DP_MASK,
3104 RT5670_DMIC_1_DP_IN2P);
3105 break;
3106
3107 case RT5670_DMIC_DATA_GPIO6:
3108 regmap_update_bits(rt5670->regmap, RT5670_DMIC_CTRL1,
3109 RT5670_DMIC_1_DP_MASK,
3110 RT5670_DMIC_1_DP_GPIO6);
3111 regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL1,
3112 RT5670_GP6_PIN_MASK,
3113 RT5670_GP6_PIN_DMIC1_SDA);
3114 break;
3115
3116 case RT5670_DMIC_DATA_GPIO7:
3117 regmap_update_bits(rt5670->regmap, RT5670_DMIC_CTRL1,
3118 RT5670_DMIC_1_DP_MASK,
3119 RT5670_DMIC_1_DP_GPIO7);
3120 regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL1,
3121 RT5670_GP7_PIN_MASK,
3122 RT5670_GP7_PIN_DMIC1_SDA);
3123 break;
3124
3125 default:
3126 break;
3127 }
3128
3129 switch (rt5670->pdata.dmic2_data_pin) {
3130 case RT5670_DMIC_DATA_IN3N:
3131 regmap_update_bits(rt5670->regmap, RT5670_DMIC_CTRL1,
3132 RT5670_DMIC_2_DP_MASK,
3133 RT5670_DMIC_2_DP_IN3N);
3134 break;
3135
3136 case RT5670_DMIC_DATA_GPIO8:
3137 regmap_update_bits(rt5670->regmap, RT5670_DMIC_CTRL1,
3138 RT5670_DMIC_2_DP_MASK,
3139 RT5670_DMIC_2_DP_GPIO8);
3140 regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL1,
3141 RT5670_GP8_PIN_MASK,
3142 RT5670_GP8_PIN_DMIC2_SDA);
3143 break;
3144
3145 default:
3146 break;
3147 }
3148
3149 switch (rt5670->pdata.dmic3_data_pin) {
3150 case RT5670_DMIC_DATA_GPIO5:
3151 regmap_update_bits(rt5670->regmap, RT5670_DMIC_CTRL2,
3152 RT5670_DMIC_3_DP_MASK,
3153 RT5670_DMIC_3_DP_GPIO5);
3154 regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL1,
3155 RT5670_GP5_PIN_MASK,
3156 RT5670_GP5_PIN_DMIC3_SDA);
3157 break;
3158
3159 case RT5670_DMIC_DATA_GPIO9:
3160 case RT5670_DMIC_DATA_GPIO10:
3161 dev_err(&i2c->dev,
3162 "Always use GPIO5 as DMIC3 data pin\n");
3163 break;
3164
3165 default:
3166 break;
3167 }
3168
3169 }
3170
64e89e5f
BL		 3171 pm_runtime_enable(&i2c->dev);
3172 pm_request_idle(&i2c->dev);
3173
5e8351de
BL		 3174 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5670,
3175 rt5670_dai, ARRAY_SIZE(rt5670_dai));
3176 if (ret < 0)
3177 goto err;
3178
64e89e5f
BL		 3179 pm_runtime_put(&i2c->dev);
3180
5e8351de
BL		 3181 return 0;
3182err:
64e89e5f
BL		 3183 pm_runtime_disable(&i2c->dev);
3184
5e8351de
BL		 3185 return ret;
3186}
3187
3188static int rt5670_i2c_remove(struct i2c_client *i2c)
3189{
64e89e5f 3190 pm_runtime_disable(&i2c->dev);
5e8351de
BL		 3191 snd_soc_unregister_codec(&i2c->dev);
3192
3193 return 0;
3194}
3195
ff62b958 3196static struct i2c_driver rt5670_i2c_driver = {
5e8351de
BL		 3197 .driver = {
3198 .name = "rt5670",
0605815e 3199 .acpi_match_table = ACPI_PTR(rt5670_acpi_match),
5e8351de
BL		 3200 },
3201 .probe = rt5670_i2c_probe,
3202 .remove = rt5670_i2c_remove,
3203 .id_table = rt5670_i2c_id,
3204};
3205
3206module_i2c_driver(rt5670_i2c_driver);
3207
3208MODULE_DESCRIPTION("ASoC RT5670 driver");
3209MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
3210MODULE_LICENSE("GPL v2");
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