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336cfbb0 VK |
1 | /* |
2 | * sst_acpi.c - SST (LPE) driver init file for ACPI enumeration. | |
3 | * | |
4 | * Copyright (c) 2013, Intel Corporation. | |
5 | * | |
6 | * Authors: Ramesh Babu K V <Ramesh.Babu@intel.com> | |
7 | * Authors: Omair Mohammed Abdullah <omair.m.abdullah@intel.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms and conditions of the GNU General Public License, | |
11 | * version 2, as published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | * more details. | |
17 | * | |
18 | * | |
19 | */ | |
20 | ||
21 | #include <linux/module.h> | |
22 | #include <linux/fs.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/io.h> | |
336cfbb0 VK |
26 | #include <linux/platform_device.h> |
27 | #include <linux/firmware.h> | |
28 | #include <linux/pm_runtime.h> | |
29 | #include <linux/pm_qos.h> | |
73a33f6f | 30 | #include <linux/dmi.h> |
336cfbb0 VK |
31 | #include <linux/acpi.h> |
32 | #include <asm/platform_sst_audio.h> | |
33 | #include <sound/core.h> | |
34 | #include <sound/soc.h> | |
35 | #include <sound/compress_driver.h> | |
36 | #include <acpi/acbuffer.h> | |
37 | #include <acpi/platform/acenv.h> | |
38 | #include <acpi/platform/aclinux.h> | |
39 | #include <acpi/actypes.h> | |
40 | #include <acpi/acpi_bus.h> | |
a68bc0d4 PLB |
41 | #include <asm/cpu_device_id.h> |
42 | #include <asm/iosf_mbi.h> | |
7feb2f78 | 43 | #include <sound/soc-acpi.h> |
60046406 | 44 | #include <sound/soc-acpi-intel-match.h> |
336cfbb0 | 45 | #include "../sst-mfld-platform.h" |
b97169da | 46 | #include "../../common/sst-dsp.h" |
336cfbb0 VK |
47 | #include "sst.h" |
48 | ||
336cfbb0 VK |
49 | /* LPE viewpoint addresses */ |
50 | #define SST_BYT_IRAM_PHY_START 0xff2c0000 | |
51 | #define SST_BYT_IRAM_PHY_END 0xff2d4000 | |
52 | #define SST_BYT_DRAM_PHY_START 0xff300000 | |
53 | #define SST_BYT_DRAM_PHY_END 0xff320000 | |
54 | #define SST_BYT_IMR_VIRT_START 0xc0000000 /* virtual addr in LPE */ | |
55 | #define SST_BYT_IMR_VIRT_END 0xc01fffff | |
56 | #define SST_BYT_SHIM_PHY_ADDR 0xff340000 | |
57 | #define SST_BYT_MBOX_PHY_ADDR 0xff344000 | |
58 | #define SST_BYT_DMA0_PHY_ADDR 0xff298000 | |
59 | #define SST_BYT_DMA1_PHY_ADDR 0xff29c000 | |
60 | #define SST_BYT_SSP0_PHY_ADDR 0xff2a0000 | |
61 | #define SST_BYT_SSP2_PHY_ADDR 0xff2a2000 | |
62 | ||
63 | #define BYT_FW_MOD_TABLE_OFFSET 0x80000 | |
64 | #define BYT_FW_MOD_TABLE_SIZE 0x100 | |
65 | #define BYT_FW_MOD_OFFSET (BYT_FW_MOD_TABLE_OFFSET + BYT_FW_MOD_TABLE_SIZE) | |
66 | ||
67 | static const struct sst_info byt_fwparse_info = { | |
68 | .use_elf = false, | |
69 | .max_streams = 25, | |
70 | .iram_start = SST_BYT_IRAM_PHY_START, | |
71 | .iram_end = SST_BYT_IRAM_PHY_END, | |
72 | .iram_use = true, | |
73 | .dram_start = SST_BYT_DRAM_PHY_START, | |
74 | .dram_end = SST_BYT_DRAM_PHY_END, | |
75 | .dram_use = true, | |
76 | .imr_start = SST_BYT_IMR_VIRT_START, | |
77 | .imr_end = SST_BYT_IMR_VIRT_END, | |
78 | .imr_use = true, | |
79 | .mailbox_start = SST_BYT_MBOX_PHY_ADDR, | |
80 | .num_probes = 0, | |
81 | .lpe_viewpt_rqd = true, | |
82 | }; | |
83 | ||
84 | static const struct sst_ipc_info byt_ipc_info = { | |
85 | .ipc_offset = 0, | |
86 | .mbox_recv_off = 0x400, | |
87 | }; | |
88 | ||
89 | static const struct sst_lib_dnld_info byt_lib_dnld_info = { | |
90 | .mod_base = SST_BYT_IMR_VIRT_START, | |
91 | .mod_end = SST_BYT_IMR_VIRT_END, | |
92 | .mod_table_offset = BYT_FW_MOD_TABLE_OFFSET, | |
93 | .mod_table_size = BYT_FW_MOD_TABLE_SIZE, | |
94 | .mod_ddr_dnld = false, | |
95 | }; | |
96 | ||
97 | static const struct sst_res_info byt_rvp_res_info = { | |
98 | .shim_offset = 0x140000, | |
99 | .shim_size = 0x000100, | |
100 | .shim_phy_addr = SST_BYT_SHIM_PHY_ADDR, | |
101 | .ssp0_offset = 0xa0000, | |
102 | .ssp0_size = 0x1000, | |
103 | .dma0_offset = 0x98000, | |
104 | .dma0_size = 0x4000, | |
105 | .dma1_offset = 0x9c000, | |
106 | .dma1_size = 0x4000, | |
107 | .iram_offset = 0x0c0000, | |
108 | .iram_size = 0x14000, | |
109 | .dram_offset = 0x100000, | |
110 | .dram_size = 0x28000, | |
111 | .mbox_offset = 0x144000, | |
112 | .mbox_size = 0x1000, | |
113 | .acpi_lpe_res_index = 0, | |
114 | .acpi_ddr_index = 2, | |
115 | .acpi_ipc_irq_index = 5, | |
116 | }; | |
117 | ||
a68bc0d4 PLB |
118 | /* BYTCR has different BIOS from BYT */ |
119 | static const struct sst_res_info bytcr_res_info = { | |
120 | .shim_offset = 0x140000, | |
121 | .shim_size = 0x000100, | |
122 | .shim_phy_addr = SST_BYT_SHIM_PHY_ADDR, | |
123 | .ssp0_offset = 0xa0000, | |
124 | .ssp0_size = 0x1000, | |
125 | .dma0_offset = 0x98000, | |
126 | .dma0_size = 0x4000, | |
127 | .dma1_offset = 0x9c000, | |
128 | .dma1_size = 0x4000, | |
129 | .iram_offset = 0x0c0000, | |
130 | .iram_size = 0x14000, | |
131 | .dram_offset = 0x100000, | |
132 | .dram_size = 0x28000, | |
133 | .mbox_offset = 0x144000, | |
134 | .mbox_size = 0x1000, | |
135 | .acpi_lpe_res_index = 0, | |
136 | .acpi_ddr_index = 2, | |
137 | .acpi_ipc_irq_index = 0 | |
138 | }; | |
139 | ||
1a28fc19 | 140 | static struct sst_platform_info byt_rvp_platform_data = { |
336cfbb0 VK |
141 | .probe_data = &byt_fwparse_info, |
142 | .ipc_info = &byt_ipc_info, | |
143 | .lib_info = &byt_lib_dnld_info, | |
144 | .res_info = &byt_rvp_res_info, | |
145 | .platform = "sst-mfld-platform", | |
146 | }; | |
147 | ||
bd01fdc3 ML |
148 | /* Cherryview (Cherrytrail and Braswell) uses same mrfld dpcm fw as Baytrail, |
149 | * so pdata is same as Baytrail. | |
150 | */ | |
14cd7923 | 151 | static struct sst_platform_info chv_platform_data = { |
bd01fdc3 ML |
152 | .probe_data = &byt_fwparse_info, |
153 | .ipc_info = &byt_ipc_info, | |
154 | .lib_info = &byt_lib_dnld_info, | |
155 | .res_info = &byt_rvp_res_info, | |
156 | .platform = "sst-mfld-platform", | |
157 | }; | |
158 | ||
336cfbb0 VK |
159 | static int sst_platform_get_resources(struct intel_sst_drv *ctx) |
160 | { | |
161 | struct resource *rsrc; | |
162 | struct platform_device *pdev = to_platform_device(ctx->dev); | |
163 | ||
164 | /* All ACPI resource request here */ | |
165 | /* Get Shim addr */ | |
166 | rsrc = platform_get_resource(pdev, IORESOURCE_MEM, | |
167 | ctx->pdata->res_info->acpi_lpe_res_index); | |
168 | if (!rsrc) { | |
1635c694 | 169 | dev_err(ctx->dev, "Invalid SHIM base from IFWI\n"); |
336cfbb0 VK |
170 | return -EIO; |
171 | } | |
172 | dev_info(ctx->dev, "LPE base: %#x size:%#x", (unsigned int) rsrc->start, | |
173 | (unsigned int)resource_size(rsrc)); | |
174 | ||
175 | ctx->iram_base = rsrc->start + ctx->pdata->res_info->iram_offset; | |
176 | ctx->iram_end = ctx->iram_base + ctx->pdata->res_info->iram_size - 1; | |
177 | dev_info(ctx->dev, "IRAM base: %#x", ctx->iram_base); | |
178 | ctx->iram = devm_ioremap_nocache(ctx->dev, ctx->iram_base, | |
179 | ctx->pdata->res_info->iram_size); | |
180 | if (!ctx->iram) { | |
1635c694 | 181 | dev_err(ctx->dev, "unable to map IRAM\n"); |
336cfbb0 VK |
182 | return -EIO; |
183 | } | |
184 | ||
185 | ctx->dram_base = rsrc->start + ctx->pdata->res_info->dram_offset; | |
186 | ctx->dram_end = ctx->dram_base + ctx->pdata->res_info->dram_size - 1; | |
187 | dev_info(ctx->dev, "DRAM base: %#x", ctx->dram_base); | |
188 | ctx->dram = devm_ioremap_nocache(ctx->dev, ctx->dram_base, | |
189 | ctx->pdata->res_info->dram_size); | |
190 | if (!ctx->dram) { | |
1635c694 | 191 | dev_err(ctx->dev, "unable to map DRAM\n"); |
336cfbb0 VK |
192 | return -EIO; |
193 | } | |
194 | ||
195 | ctx->shim_phy_add = rsrc->start + ctx->pdata->res_info->shim_offset; | |
196 | dev_info(ctx->dev, "SHIM base: %#x", ctx->shim_phy_add); | |
197 | ctx->shim = devm_ioremap_nocache(ctx->dev, ctx->shim_phy_add, | |
198 | ctx->pdata->res_info->shim_size); | |
199 | if (!ctx->shim) { | |
1635c694 | 200 | dev_err(ctx->dev, "unable to map SHIM\n"); |
336cfbb0 VK |
201 | return -EIO; |
202 | } | |
203 | ||
204 | /* reassign physical address to LPE viewpoint address */ | |
205 | ctx->shim_phy_add = ctx->pdata->res_info->shim_phy_addr; | |
206 | ||
207 | /* Get mailbox addr */ | |
208 | ctx->mailbox_add = rsrc->start + ctx->pdata->res_info->mbox_offset; | |
209 | dev_info(ctx->dev, "Mailbox base: %#x", ctx->mailbox_add); | |
210 | ctx->mailbox = devm_ioremap_nocache(ctx->dev, ctx->mailbox_add, | |
211 | ctx->pdata->res_info->mbox_size); | |
212 | if (!ctx->mailbox) { | |
1635c694 | 213 | dev_err(ctx->dev, "unable to map mailbox\n"); |
336cfbb0 VK |
214 | return -EIO; |
215 | } | |
216 | ||
217 | /* reassign physical address to LPE viewpoint address */ | |
218 | ctx->mailbox_add = ctx->info.mailbox_start; | |
219 | ||
220 | rsrc = platform_get_resource(pdev, IORESOURCE_MEM, | |
221 | ctx->pdata->res_info->acpi_ddr_index); | |
222 | if (!rsrc) { | |
1635c694 | 223 | dev_err(ctx->dev, "Invalid DDR base from IFWI\n"); |
336cfbb0 VK |
224 | return -EIO; |
225 | } | |
226 | ctx->ddr_base = rsrc->start; | |
227 | ctx->ddr_end = rsrc->end; | |
228 | dev_info(ctx->dev, "DDR base: %#x", ctx->ddr_base); | |
229 | ctx->ddr = devm_ioremap_nocache(ctx->dev, ctx->ddr_base, | |
230 | resource_size(rsrc)); | |
231 | if (!ctx->ddr) { | |
1635c694 | 232 | dev_err(ctx->dev, "unable to map DDR\n"); |
336cfbb0 VK |
233 | return -EIO; |
234 | } | |
235 | ||
236 | /* Find the IRQ */ | |
237 | ctx->irq_num = platform_get_irq(pdev, | |
238 | ctx->pdata->res_info->acpi_ipc_irq_index); | |
239 | return 0; | |
240 | } | |
241 | ||
60046406 PLB |
242 | static int is_byt(void) |
243 | { | |
244 | bool status = false; | |
245 | static const struct x86_cpu_id cpu_ids[] = { | |
246 | { X86_VENDOR_INTEL, 6, 55 }, /* Valleyview, Bay Trail */ | |
247 | {} | |
248 | }; | |
249 | if (x86_match_cpu(cpu_ids)) | |
250 | status = true; | |
251 | return status; | |
252 | } | |
a68bc0d4 PLB |
253 | |
254 | static int is_byt_cr(struct device *dev, bool *bytcr) | |
255 | { | |
256 | int status = 0; | |
257 | ||
258 | if (IS_ENABLED(CONFIG_IOSF_MBI)) { | |
a68bc0d4 PLB |
259 | u32 bios_status; |
260 | ||
60046406 | 261 | if (!is_byt() || !iosf_mbi_available()) { |
a68bc0d4 PLB |
262 | /* bail silently */ |
263 | return status; | |
264 | } | |
265 | ||
266 | status = iosf_mbi_read(BT_MBI_UNIT_PMC, /* 0x04 PUNIT */ | |
267 | MBI_REG_READ, /* 0x10 */ | |
268 | 0x006, /* BIOS_CONFIG */ | |
269 | &bios_status); | |
270 | ||
271 | if (status) { | |
272 | dev_err(dev, "could not read PUNIT BIOS_CONFIG\n"); | |
273 | } else { | |
274 | /* bits 26:27 mirror PMIC options */ | |
275 | bios_status = (bios_status >> 26) & 3; | |
276 | ||
277 | if ((bios_status == 1) || (bios_status == 3)) | |
278 | *bytcr = true; | |
279 | else | |
280 | dev_info(dev, "BYT-CR not detected\n"); | |
281 | } | |
282 | } else { | |
283 | dev_info(dev, "IOSF_MBI not enabled, no BYT-CR detection\n"); | |
284 | } | |
285 | return status; | |
286 | } | |
287 | ||
288 | ||
5129ad6e | 289 | static int sst_acpi_probe(struct platform_device *pdev) |
336cfbb0 VK |
290 | { |
291 | struct device *dev = &pdev->dev; | |
292 | int ret = 0; | |
293 | struct intel_sst_drv *ctx; | |
294 | const struct acpi_device_id *id; | |
7feb2f78 | 295 | struct snd_soc_acpi_mach *mach; |
336cfbb0 VK |
296 | struct platform_device *mdev; |
297 | struct platform_device *plat_dev; | |
12cc291b | 298 | struct sst_platform_info *pdata; |
336cfbb0 | 299 | unsigned int dev_id; |
a68bc0d4 | 300 | bool bytcr = false; |
336cfbb0 VK |
301 | |
302 | id = acpi_match_device(dev->driver->acpi_match_table, dev); | |
303 | if (!id) | |
304 | return -ENODEV; | |
1635c694 | 305 | dev_dbg(dev, "for %s\n", id->id); |
336cfbb0 | 306 | |
7feb2f78 PLB |
307 | mach = (struct snd_soc_acpi_mach *)id->driver_data; |
308 | mach = snd_soc_acpi_find_machine(mach); | |
336cfbb0 VK |
309 | if (mach == NULL) { |
310 | dev_err(dev, "No matching machine driver found\n"); | |
311 | return -ENODEV; | |
312 | } | |
73a33f6f | 313 | |
60046406 PLB |
314 | if (is_byt()) |
315 | mach->pdata = &byt_rvp_platform_data; | |
316 | else | |
317 | mach->pdata = &chv_platform_data; | |
12cc291b | 318 | pdata = mach->pdata; |
336cfbb0 VK |
319 | |
320 | ret = kstrtouint(id->id, 16, &dev_id); | |
321 | if (ret < 0) { | |
322 | dev_err(dev, "Unique device id conversion error: %d\n", ret); | |
323 | return ret; | |
324 | } | |
325 | ||
326 | dev_dbg(dev, "ACPI device id: %x\n", dev_id); | |
327 | ||
a68bc0d4 PLB |
328 | ret = sst_alloc_drv_context(&ctx, dev, dev_id); |
329 | if (ret < 0) | |
330 | return ret; | |
331 | ||
332 | ret = is_byt_cr(dev, &bytcr); | |
333 | if (!((ret < 0) || (bytcr == false))) { | |
334 | dev_info(dev, "Detected Baytrail-CR platform\n"); | |
335 | ||
336 | /* override resource info */ | |
337 | byt_rvp_platform_data.res_info = &bytcr_res_info; | |
338 | } | |
339 | ||
caf94ed8 PLB |
340 | plat_dev = platform_device_register_data(dev, pdata->platform, -1, |
341 | NULL, 0); | |
f5d40b40 | 342 | if (IS_ERR(plat_dev)) { |
caf94ed8 PLB |
343 | dev_err(dev, "Failed to create machine device: %s\n", |
344 | pdata->platform); | |
f5d40b40 | 345 | return PTR_ERR(plat_dev); |
336cfbb0 VK |
346 | } |
347 | ||
caf94ed8 PLB |
348 | /* |
349 | * Create platform device for sst machine driver, | |
350 | * pass machine info as pdata | |
351 | */ | |
352 | mdev = platform_device_register_data(dev, mach->drv_name, -1, | |
353 | (const void *)mach, sizeof(*mach)); | |
f5d40b40 | 354 | if (IS_ERR(mdev)) { |
caf94ed8 PLB |
355 | dev_err(dev, "Failed to create machine device: %s\n", |
356 | mach->drv_name); | |
f5d40b40 | 357 | return PTR_ERR(mdev); |
336cfbb0 VK |
358 | } |
359 | ||
336cfbb0 | 360 | /* Fill sst platform data */ |
12cc291b VK |
361 | ctx->pdata = pdata; |
362 | strcpy(ctx->firmware_name, mach->fw_filename); | |
336cfbb0 VK |
363 | |
364 | ret = sst_platform_get_resources(ctx); | |
365 | if (ret) | |
366 | return ret; | |
367 | ||
368 | ret = sst_context_init(ctx); | |
369 | if (ret < 0) | |
370 | return ret; | |
371 | ||
336cfbb0 VK |
372 | sst_configure_runtime_pm(ctx); |
373 | platform_set_drvdata(pdev, ctx); | |
374 | return ret; | |
336cfbb0 VK |
375 | } |
376 | ||
377 | /** | |
378 | * intel_sst_remove - remove function | |
379 | * | |
380 | * @pdev: platform device structure | |
381 | * | |
382 | * This function is called by OS when a device is unloaded | |
383 | * This frees the interrupt etc | |
384 | */ | |
5129ad6e | 385 | static int sst_acpi_remove(struct platform_device *pdev) |
336cfbb0 VK |
386 | { |
387 | struct intel_sst_drv *ctx; | |
388 | ||
389 | ctx = platform_get_drvdata(pdev); | |
390 | sst_context_cleanup(ctx); | |
391 | platform_set_drvdata(pdev, NULL); | |
392 | return 0; | |
393 | } | |
394 | ||
336cfbb0 | 395 | static const struct acpi_device_id sst_acpi_ids[] = { |
60046406 PLB |
396 | { "80860F28", (unsigned long)&snd_soc_acpi_intel_baytrail_machines}, |
397 | { "808622A8", (unsigned long)&snd_soc_acpi_intel_cherrytrail_machines}, | |
336cfbb0 VK |
398 | { }, |
399 | }; | |
400 | ||
eb826a35 ML |
401 | MODULE_DEVICE_TABLE(acpi, sst_acpi_ids); |
402 | ||
336cfbb0 VK |
403 | static struct platform_driver sst_acpi_driver = { |
404 | .driver = { | |
405 | .name = "intel_sst_acpi", | |
336cfbb0 VK |
406 | .acpi_match_table = ACPI_PTR(sst_acpi_ids), |
407 | .pm = &intel_sst_pm, | |
408 | }, | |
409 | .probe = sst_acpi_probe, | |
410 | .remove = sst_acpi_remove, | |
411 | }; | |
412 | ||
413 | module_platform_driver(sst_acpi_driver); | |
414 | ||
415 | MODULE_DESCRIPTION("Intel (R) SST(R) Audio Engine ACPI Driver"); | |
416 | MODULE_AUTHOR("Ramesh Babu K V"); | |
417 | MODULE_AUTHOR("Omair Mohammed Abdullah"); | |
418 | MODULE_LICENSE("GPL v2"); | |
419 | MODULE_ALIAS("sst"); |