[mirror_ubuntu-artful-kernel.git] / sound / soc / omap / omap-mcbsp.c

/*
 * omap-mcbsp.c  --  OMAP ALSA SoC DAI driver using McBSP port
 *
 * Copyright (C) 2008 Nokia Corporation
 *
 * Contact: Jarkko Nikula <jhnikula@gmail.com>
 *          Peter Ujfalusi <peter.ujfalusi@nokia.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
#include <sound/soc.h>

#include <mach/control.h>
#include <mach/dma.h>
#include <mach/mcbsp.h>
#include "omap-mcbsp.h"
#include "omap-pcm.h"

#define OMAP_MCBSP_RATES	(SNDRV_PCM_RATE_8000_96000)

struct omap_mcbsp_data {
	unsigned int			bus_id;
	struct omap_mcbsp_reg_cfg	regs;
	unsigned int			fmt;
	/*
	 * Flags indicating is the bus already activated and configured by
	 * another substream
	 */
	int				active;
	int				configured;
};

#define to_mcbsp(priv)	container_of((priv), struct omap_mcbsp_data, bus_id)

static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];

/*
 * Stream DMA parameters. DMA request line and port address are set runtime
 * since they are different between OMAP1 and later OMAPs
 */
static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];

#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
static const int omap1_dma_reqs[][2] = {
	{ OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
	{ OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
	{ OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
};
static const unsigned long omap1_mcbsp_port[][2] = {
	{ OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
	  OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
	{ OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
	  OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
	{ OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
	  OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
};
#else
static const int omap1_dma_reqs[][2] = {};
static const unsigned long omap1_mcbsp_port[][2] = {};
#endif

#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
static const int omap24xx_dma_reqs[][2] = {
	{ OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
	{ OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
	{ OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
	{ OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
	{ OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
#endif
};
#else
static const int omap24xx_dma_reqs[][2] = {};
#endif

#if defined(CONFIG_ARCH_OMAP2420)
static const unsigned long omap2420_mcbsp_port[][2] = {
	{ OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
	  OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
	{ OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
	  OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
};
#else
static const unsigned long omap2420_mcbsp_port[][2] = {};
#endif

#if defined(CONFIG_ARCH_OMAP2430)
static const unsigned long omap2430_mcbsp_port[][2] = {
	{ OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
	{ OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
	{ OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
	{ OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
	{ OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
};
#else
static const unsigned long omap2430_mcbsp_port[][2] = {};
#endif

#if defined(CONFIG_ARCH_OMAP34XX)
static const unsigned long omap34xx_mcbsp_port[][2] = {
	{ OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
	{ OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
	{ OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
	{ OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
	{ OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
	  OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
};
#else
static const unsigned long omap34xx_mcbsp_port[][2] = {};
#endif

static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
				  struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	int err = 0;

	if (cpu_is_omap343x() && mcbsp_data->bus_id == 1) {
		/*
		 * McBSP2 in OMAP3 has 1024 * 32-bit internal audio buffer.
		 * Set constraint for minimum buffer size to the same than FIFO
		 * size in order to avoid underruns in playback startup because
		 * HW is keeping the DMA request active until FIFO is filled.
		 */
		snd_pcm_hw_constraint_minmax(substream->runtime,
			SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 4096, UINT_MAX);
	}

	if (!cpu_dai->active)
		err = omap_mcbsp_request(mcbsp_data->bus_id);

	return err;
}

static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
				    struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);

	if (!cpu_dai->active) {
		omap_mcbsp_free(mcbsp_data->bus_id);
		mcbsp_data->configured = 0;
	}
}

static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
				  struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		mcbsp_data->active++;
		omap_mcbsp_start(mcbsp_data->bus_id, play, !play);
		/* Make sure data transfer is frame synchronized */
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
			omap_mcbsp_xmit_enable(mcbsp_data->bus_id, 1);
		else
			omap_mcbsp_recv_enable(mcbsp_data->bus_id, 1);
		break;

	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		omap_mcbsp_stop(mcbsp_data->bus_id, play, !play);
		mcbsp_data->active--;
		break;
	default:
		err = -EINVAL;
	}

	return err;
}

static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
				    struct snd_pcm_hw_params *params,
				    struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
	int dma, bus_id = mcbsp_data->bus_id, id = cpu_dai->id;
	int wlen, channels, wpf;
	unsigned long port;
	unsigned int format;

	if (cpu_class_is_omap1()) {
		dma = omap1_dma_reqs[bus_id][substream->stream];
		port = omap1_mcbsp_port[bus_id][substream->stream];
	} else if (cpu_is_omap2420()) {
		dma = omap24xx_dma_reqs[bus_id][substream->stream];
		port = omap2420_mcbsp_port[bus_id][substream->stream];
	} else if (cpu_is_omap2430()) {
		dma = omap24xx_dma_reqs[bus_id][substream->stream];
		port = omap2430_mcbsp_port[bus_id][substream->stream];
	} else if (cpu_is_omap343x()) {
		dma = omap24xx_dma_reqs[bus_id][substream->stream];
		port = omap34xx_mcbsp_port[bus_id][substream->stream];
	} else {
		return -ENODEV;
	}
	omap_mcbsp_dai_dma_params[id][substream->stream].name =
		substream->stream ? "Audio Capture" : "Audio Playback";
	omap_mcbsp_dai_dma_params[id][substream->stream].dma_req = dma;
	omap_mcbsp_dai_dma_params[id][substream->stream].port_addr = port;
	cpu_dai->dma_data = &omap_mcbsp_dai_dma_params[id][substream->stream];

	if (mcbsp_data->configured) {
		/* McBSP already configured by another stream */
		return 0;
	}

	format = mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
	wpf = channels = params_channels(params);
	switch (channels) {
	case 2:
		if (format == SND_SOC_DAIFMT_I2S) {
			/* Use dual-phase frames */
			regs->rcr2	|= RPHASE;
			regs->xcr2	|= XPHASE;
			/* Set 1 word per (McBSP) frame for phase1 and phase2 */
			wpf--;
			regs->rcr2	|= RFRLEN2(wpf - 1);
			regs->xcr2	|= XFRLEN2(wpf - 1);
		}
	case 1:
	case 4:
		/* Set word per (McBSP) frame for phase1 */
		regs->rcr1	|= RFRLEN1(wpf - 1);
		regs->xcr1	|= XFRLEN1(wpf - 1);
		break;
	default:
		/* Unsupported number of channels */
		return -EINVAL;
	}

	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S16_LE:
		/* Set word lengths */
		wlen = 16;
		regs->rcr2	|= RWDLEN2(OMAP_MCBSP_WORD_16);
		regs->rcr1	|= RWDLEN1(OMAP_MCBSP_WORD_16);
		regs->xcr2	|= XWDLEN2(OMAP_MCBSP_WORD_16);
		regs->xcr1	|= XWDLEN1(OMAP_MCBSP_WORD_16);
		break;
	default:
		/* Unsupported PCM format */
		return -EINVAL;
	}

	/* Set FS period and length in terms of bit clock periods */
	switch (format) {
	case SND_SOC_DAIFMT_I2S:
		regs->srgr2	|= FPER(wlen * channels - 1);
		regs->srgr1	|= FWID(wlen - 1);
		break;
	case SND_SOC_DAIFMT_DSP_A:
	case SND_SOC_DAIFMT_DSP_B:
		regs->srgr2	|= FPER(wlen * channels - 1);
		regs->srgr1	|= FWID(0);
		break;
	}

	omap_mcbsp_config(bus_id, &mcbsp_data->regs);
	mcbsp_data->configured = 1;

	return 0;
}

/*
 * This must be called before _set_clkdiv and _set_sysclk since McBSP register
 * cache is initialized here
 */
static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
				      unsigned int fmt)
{
	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
	unsigned int temp_fmt = fmt;

	if (mcbsp_data->configured)
		return 0;

	mcbsp_data->fmt = fmt;
	memset(regs, 0, sizeof(*regs));
	/* Generic McBSP register settings */
	regs->spcr2	|= XINTM(3) | FREE;
	regs->spcr1	|= RINTM(3);
	/* RFIG and XFIG are not defined in 34xx */
	if (!cpu_is_omap34xx()) {
		regs->rcr2	|= RFIG;
		regs->xcr2	|= XFIG;
	}
	if (cpu_is_omap2430() || cpu_is_omap34xx()) {
		regs->xccr = DXENDLY(1) | XDMAEN;
		regs->rccr = RFULL_CYCLE | RDMAEN;
	}

	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_I2S:
		/* 1-bit data delay */
		regs->rcr2	|= RDATDLY(1);
		regs->xcr2	|= XDATDLY(1);
		regs->rccr	|= RFULL_CYCLE | RDMAEN | RDISABLE;
		regs->xccr	|= (DXENDLY(1) | XDMAEN | XDISABLE);
		break;
	case SND_SOC_DAIFMT_DSP_A:
		/* 1-bit data delay */
		regs->rcr2      |= RDATDLY(1);
		regs->xcr2      |= XDATDLY(1);
		regs->rccr	|= RFULL_CYCLE | RDMAEN | RDISABLE;
		regs->xccr	|= (DXENDLY(1) | XDMAEN | XDISABLE);
		/* Invert FS polarity configuration */
		temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
		break;
	case SND_SOC_DAIFMT_DSP_B:
		/* 0-bit data delay */
		regs->rcr2      |= RDATDLY(0);
		regs->xcr2      |= XDATDLY(0);
		/* Invert FS polarity configuration */
		temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
		break;
	default:
		/* Unsupported data format */
		return -EINVAL;
	}

	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		/* McBSP master. Set FS and bit clocks as outputs */
		regs->pcr0	|= FSXM | FSRM |
				   CLKXM | CLKRM;
		/* Sample rate generator drives the FS */
		regs->srgr2	|= FSGM;
		break;
	case SND_SOC_DAIFMT_CBM_CFM:
		/* McBSP slave */
		break;
	default:
		/* Unsupported master/slave configuration */
		return -EINVAL;
	}

	/* Set bit clock (CLKX/CLKR) and FS polarities */
	switch (temp_fmt & SND_SOC_DAIFMT_INV_MASK) {
	case SND_SOC_DAIFMT_NB_NF:
		/*
		 * Normal BCLK + FS.
		 * FS active low. TX data driven on falling edge of bit clock
		 * and RX data sampled on rising edge of bit clock.
		 */
		regs->pcr0	|= FSXP | FSRP |
				   CLKXP | CLKRP;
		break;
	case SND_SOC_DAIFMT_NB_IF:
		regs->pcr0	|= CLKXP | CLKRP;
		break;
	case SND_SOC_DAIFMT_IB_NF:
		regs->pcr0	|= FSXP | FSRP;
		break;
	case SND_SOC_DAIFMT_IB_IF:
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
				     int div_id, int div)
{
	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;

	if (div_id != OMAP_MCBSP_CLKGDV)
		return -ENODEV;

	regs->srgr1	|= CLKGDV(div - 1);

	return 0;
}

static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data,
				       int clk_id)
{
	int sel_bit;
	u16 reg, reg_devconf1 = OMAP243X_CONTROL_DEVCONF1;

	if (cpu_class_is_omap1()) {
		/* OMAP1's can use only external source clock */
		if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK))
			return -EINVAL;
		else
			return 0;
	}

	if (cpu_is_omap2420() && mcbsp_data->bus_id > 1)
		return -EINVAL;

	if (cpu_is_omap343x())
		reg_devconf1 = OMAP343X_CONTROL_DEVCONF1;

	switch (mcbsp_data->bus_id) {
	case 0:
		reg = OMAP2_CONTROL_DEVCONF0;
		sel_bit = 2;
		break;
	case 1:
		reg = OMAP2_CONTROL_DEVCONF0;
		sel_bit = 6;
		break;
	case 2:
		reg = reg_devconf1;
		sel_bit = 0;
		break;
	case 3:
		reg = reg_devconf1;
		sel_bit = 2;
		break;
	case 4:
		reg = reg_devconf1;
		sel_bit = 4;
		break;
	default:
		return -EINVAL;
	}

	if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK)
		omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
	else
		omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);

	return 0;
}

static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
					 int clk_id, unsigned int freq,
					 int dir)
{
	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
	int err = 0;

	switch (clk_id) {
	case OMAP_MCBSP_SYSCLK_CLK:
		regs->srgr2	|= CLKSM;
		break;
	case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
	case OMAP_MCBSP_SYSCLK_CLKS_EXT:
		err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id);
		break;

	case OMAP_MCBSP_SYSCLK_CLKX_EXT:
		regs->srgr2	|= CLKSM;
	case OMAP_MCBSP_SYSCLK_CLKR_EXT:
		regs->pcr0	|= SCLKME;
		break;
	default:
		err = -ENODEV;
	}

	return err;
}

static struct snd_soc_dai_ops omap_mcbsp_dai_ops = {
	.startup	= omap_mcbsp_dai_startup,
	.shutdown	= omap_mcbsp_dai_shutdown,
	.trigger	= omap_mcbsp_dai_trigger,
	.hw_params	= omap_mcbsp_dai_hw_params,
	.set_fmt	= omap_mcbsp_dai_set_dai_fmt,
	.set_clkdiv	= omap_mcbsp_dai_set_clkdiv,
	.set_sysclk	= omap_mcbsp_dai_set_dai_sysclk,
};

#define OMAP_MCBSP_DAI_BUILDER(link_id)				\
{								\
	.name = "omap-mcbsp-dai-"#link_id,			\
	.id = (link_id),					\
	.playback = {						\
		.channels_min = 1,				\
		.channels_max = 4,				\
		.rates = OMAP_MCBSP_RATES,			\
		.formats = SNDRV_PCM_FMTBIT_S16_LE,		\
	},							\
	.capture = {						\
		.channels_min = 1,				\
		.channels_max = 4,				\
		.rates = OMAP_MCBSP_RATES,			\
		.formats = SNDRV_PCM_FMTBIT_S16_LE,		\
	},							\
	.ops = &omap_mcbsp_dai_ops,				\
	.private_data = &mcbsp_data[(link_id)].bus_id,		\
}

struct snd_soc_dai omap_mcbsp_dai[] = {
	OMAP_MCBSP_DAI_BUILDER(0),
	OMAP_MCBSP_DAI_BUILDER(1),
#if NUM_LINKS >= 3
	OMAP_MCBSP_DAI_BUILDER(2),
#endif
#if NUM_LINKS == 5
	OMAP_MCBSP_DAI_BUILDER(3),
	OMAP_MCBSP_DAI_BUILDER(4),
#endif
};

EXPORT_SYMBOL_GPL(omap_mcbsp_dai);

static int __init snd_omap_mcbsp_init(void)
{
	return snd_soc_register_dais(omap_mcbsp_dai,
				     ARRAY_SIZE(omap_mcbsp_dai));
}
module_init(snd_omap_mcbsp_init);

static void __exit snd_omap_mcbsp_exit(void)
{
	snd_soc_unregister_dais(omap_mcbsp_dai, ARRAY_SIZE(omap_mcbsp_dai));
}
module_exit(snd_omap_mcbsp_exit);

MODULE_AUTHOR("Jarkko Nikula <jhnikula@gmail.com>");
MODULE_DESCRIPTION("OMAP I2S SoC Interface");
MODULE_LICENSE("GPL");
Commit	Line	Data
2e74796a JN	1	/*
	2	* omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port
	3	*
	4	* Copyright (C) 2008 Nokia Corporation
	5	*
b08f7a62 JN	6	* Contact: Jarkko Nikula <jhnikula@gmail.com>
b08f7a62 JN	7	* Peter Ujfalusi <peter.ujfalusi@nokia.com>
2e74796a JN	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* version 2 as published by the Free Software Foundation.
	12	*
	13	* This program is distributed in the hope that it will be useful, but
	14	* WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	16	* General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	21	* 02110-1301 USA
	22	*
	23	*/
	24
	25	#include <linux/init.h>
	26	#include <linux/module.h>
	27	#include <linux/device.h>
	28	#include <sound/core.h>
	29	#include <sound/pcm.h>
	30	#include <sound/pcm_params.h>
	31	#include <sound/initval.h>
	32	#include <sound/soc.h>
	33
a09e64fb RK	34	#include <mach/control.h>
	35	#include <mach/dma.h>
	36	#include <mach/mcbsp.h>
2e74796a JN	37	#include "omap-mcbsp.h"
	38	#include "omap-pcm.h"
	39
0b604856	40	#define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000)
2e74796a JN	41
	42	struct omap_mcbsp_data {
	43	unsigned int bus_id;
	44	struct omap_mcbsp_reg_cfg regs;
ba9d0fd0	45	unsigned int fmt;
2e74796a JN	46	/*
	47	* Flags indicating is the bus already activated and configured by
	48	* another substream
	49	*/
	50	int active;
	51	int configured;
	52	};
	53
	54	#define to_mcbsp(priv) container_of((priv), struct omap_mcbsp_data, bus_id)
	55
	56	static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];
	57
	58	/*
	59	* Stream DMA parameters. DMA request line and port address are set runtime
	60	* since they are different between OMAP1 and later OMAPs
	61	*/
2e89713a	62	static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];
2e74796a JN	63
	64	#if defined(CONFIG_ARCH_OMAP15XX) \|\| defined(CONFIG_ARCH_OMAP16XX)
	65	static const int omap1_dma_reqs[][2] = {
	66	{ OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
	67	{ OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
	68	{ OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
	69	};
	70	static const unsigned long omap1_mcbsp_port[][2] = {
	71	{ OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
	72	OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
	73	{ OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
	74	OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
	75	{ OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
	76	OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
	77	};
	78	#else
	79	static const int omap1_dma_reqs[][2] = {};
	80	static const unsigned long omap1_mcbsp_port[][2] = {};
	81	#endif
406e2c48 JN	82
	83	#if defined(CONFIG_ARCH_OMAP24XX) \|\| defined(CONFIG_ARCH_OMAP34XX)
	84	static const int omap24xx_dma_reqs[][2] = {
2e74796a JN	85	{ OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
2e74796a JN	86	{ OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
406e2c48 JN	87	#if defined(CONFIG_ARCH_OMAP2430) \|\| defined(CONFIG_ARCH_OMAP34XX)
	88	{ OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
	89	{ OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
	90	{ OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
	91	#endif
2e74796a	92	};
406e2c48 JN	93	#else
	94	static const int omap24xx_dma_reqs[][2] = {};
	95	#endif
	96
	97	#if defined(CONFIG_ARCH_OMAP2420)
2e74796a JN	98	static const unsigned long omap2420_mcbsp_port[][2] = {
	99	{ OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
	100	OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
	101	{ OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
	102	OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
	103	};
	104	#else
2e74796a JN	105	static const unsigned long omap2420_mcbsp_port[][2] = {};
	106	#endif
	107
406e2c48 JN	108	#if defined(CONFIG_ARCH_OMAP2430)
	109	static const unsigned long omap2430_mcbsp_port[][2] = {
	110	{ OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
	111	OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
	112	{ OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
	113	OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
	114	{ OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
	115	OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
	116	{ OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
	117	OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
	118	{ OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
	119	OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
	120	};
	121	#else
	122	static const unsigned long omap2430_mcbsp_port[][2] = {};
	123	#endif
	124
	125	#if defined(CONFIG_ARCH_OMAP34XX)
	126	static const unsigned long omap34xx_mcbsp_port[][2] = {
	127	{ OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
	128	OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
	129	{ OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
	130	OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
	131	{ OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
	132	OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
	133	{ OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
	134	OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
	135	{ OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
	136	OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
	137	};
	138	#else
	139	static const unsigned long omap34xx_mcbsp_port[][2] = {};
	140	#endif
	141
dee89c4d MB	142	static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
dee89c4d MB	143	struct snd_soc_dai *dai)
2e74796a JN	144	{
2e74796a JN	145	struct snd_soc_pcm_runtime *rtd = substream->private_data;
8687eb8b	146	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
2e74796a JN	147	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	148	int err = 0;
	149
6984992b JN	150	if (cpu_is_omap343x() && mcbsp_data->bus_id == 1) {
	151	/*
	152	* McBSP2 in OMAP3 has 1024 * 32-bit internal audio buffer.
	153	* Set constraint for minimum buffer size to the same than FIFO
	154	* size in order to avoid underruns in playback startup because
	155	* HW is keeping the DMA request active until FIFO is filled.
	156	*/
	157	snd_pcm_hw_constraint_minmax(substream->runtime,
	158	SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 4096, UINT_MAX);
	159	}
	160
2e74796a JN	161	if (!cpu_dai->active)
	162	err = omap_mcbsp_request(mcbsp_data->bus_id);
	163
	164	return err;
	165	}
	166
dee89c4d MB	167	static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
dee89c4d MB	168	struct snd_soc_dai *dai)
2e74796a JN	169	{
2e74796a JN	170	struct snd_soc_pcm_runtime *rtd = substream->private_data;
8687eb8b	171	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
2e74796a JN	172	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	173
	174	if (!cpu_dai->active) {
	175	omap_mcbsp_free(mcbsp_data->bus_id);
	176	mcbsp_data->configured = 0;
	177	}
	178	}
	179
dee89c4d MB	180	static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
dee89c4d MB	181	struct snd_soc_dai *dai)
2e74796a JN	182	{
2e74796a JN	183	struct snd_soc_pcm_runtime *rtd = substream->private_data;
8687eb8b	184	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
2e74796a	185	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
c12abc01	186	int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
2e74796a JN	187
	188	switch (cmd) {
	189	case SNDRV_PCM_TRIGGER_START:
	190	case SNDRV_PCM_TRIGGER_RESUME:
	191	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
c12abc01 JN	192	mcbsp_data->active++;
c12abc01 JN	193	omap_mcbsp_start(mcbsp_data->bus_id, play, !play);
ca6e2ce0 EN	194	/* Make sure data transfer is frame synchronized */
	195	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	196	omap_mcbsp_xmit_enable(mcbsp_data->bus_id, 1);
	197	else
	198	omap_mcbsp_recv_enable(mcbsp_data->bus_id, 1);
2e74796a JN	199	break;
	200
	201	case SNDRV_PCM_TRIGGER_STOP:
	202	case SNDRV_PCM_TRIGGER_SUSPEND:
	203	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
c12abc01 JN	204	omap_mcbsp_stop(mcbsp_data->bus_id, play, !play);
c12abc01 JN	205	mcbsp_data->active--;
2e74796a JN	206	break;
	207	default:
	208	err = -EINVAL;
	209	}
	210
	211	return err;
	212	}
	213
	214	static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
dee89c4d MB	215	struct snd_pcm_hw_params *params,
dee89c4d MB	216	struct snd_soc_dai *dai)
2e74796a JN	217	{
2e74796a JN	218	struct snd_soc_pcm_runtime *rtd = substream->private_data;
8687eb8b	219	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
2e74796a JN	220	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	221	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
	222	int dma, bus_id = mcbsp_data->bus_id, id = cpu_dai->id;
c29b206f	223	int wlen, channels, wpf;
2e74796a	224	unsigned long port;
c29b206f	225	unsigned int format;
2e74796a JN	226
	227	if (cpu_class_is_omap1()) {
	228	dma = omap1_dma_reqs[bus_id][substream->stream];
	229	port = omap1_mcbsp_port[bus_id][substream->stream];
	230	} else if (cpu_is_omap2420()) {
406e2c48	231	dma = omap24xx_dma_reqs[bus_id][substream->stream];
2e74796a	232	port = omap2420_mcbsp_port[bus_id][substream->stream];
406e2c48 JN	233	} else if (cpu_is_omap2430()) {
	234	dma = omap24xx_dma_reqs[bus_id][substream->stream];
	235	port = omap2430_mcbsp_port[bus_id][substream->stream];
	236	} else if (cpu_is_omap343x()) {
	237	dma = omap24xx_dma_reqs[bus_id][substream->stream];
	238	port = omap34xx_mcbsp_port[bus_id][substream->stream];
2e74796a	239	} else {
2e74796a JN	240	return -ENODEV;
2e74796a JN	241	}
2e89713a JN	242	omap_mcbsp_dai_dma_params[id][substream->stream].name =
2e89713a JN	243	substream->stream ? "Audio Capture" : "Audio Playback";
2e74796a JN	244	omap_mcbsp_dai_dma_params[id][substream->stream].dma_req = dma;
	245	omap_mcbsp_dai_dma_params[id][substream->stream].port_addr = port;
	246	cpu_dai->dma_data = &omap_mcbsp_dai_dma_params[id][substream->stream];
	247
	248	if (mcbsp_data->configured) {
	249	/* McBSP already configured by another stream */
	250	return 0;
	251	}
	252
c29b206f PU	253	format = mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
c29b206f PU	254	wpf = channels = params_channels(params);
375e8a7c	255	switch (channels) {
2e74796a	256	case 2:
c29b206f PU	257	if (format == SND_SOC_DAIFMT_I2S) {
	258	/* Use dual-phase frames */
	259	regs->rcr2 \|= RPHASE;
	260	regs->xcr2 \|= XPHASE;
	261	/* Set 1 word per (McBSP) frame for phase1 and phase2 */
	262	wpf--;
	263	regs->rcr2 \|= RFRLEN2(wpf - 1);
	264	regs->xcr2 \|= XFRLEN2(wpf - 1);
	265	}
375e8a7c	266	case 1:
31a00c6b	267	case 4:
c29b206f PU	268	/* Set word per (McBSP) frame for phase1 */
	269	regs->rcr1 \|= RFRLEN1(wpf - 1);
	270	regs->xcr1 \|= XFRLEN1(wpf - 1);
2e74796a JN	271	break;
	272	default:
	273	/* Unsupported number of channels */
	274	return -EINVAL;
	275	}
	276
	277	switch (params_format(params)) {
	278	case SNDRV_PCM_FORMAT_S16_LE:
	279	/* Set word lengths */
ba9d0fd0	280	wlen = 16;
2e74796a JN	281	regs->rcr2 \|= RWDLEN2(OMAP_MCBSP_WORD_16);
	282	regs->rcr1 \|= RWDLEN1(OMAP_MCBSP_WORD_16);
	283	regs->xcr2 \|= XWDLEN2(OMAP_MCBSP_WORD_16);
	284	regs->xcr1 \|= XWDLEN1(OMAP_MCBSP_WORD_16);
2e74796a JN	285	break;
	286	default:
	287	/* Unsupported PCM format */
	288	return -EINVAL;
	289	}
	290
ba9d0fd0	291	/* Set FS period and length in terms of bit clock periods */
c29b206f	292	switch (format) {
ba9d0fd0	293	case SND_SOC_DAIFMT_I2S:
c29b206f	294	regs->srgr2 \|= FPER(wlen * channels - 1);
ba9d0fd0 JN	295	regs->srgr1 \|= FWID(wlen - 1);
ba9d0fd0 JN	296	break;
3ba191ce	297	case SND_SOC_DAIFMT_DSP_A:
bd25867a	298	case SND_SOC_DAIFMT_DSP_B:
375e8a7c	299	regs->srgr2 \|= FPER(wlen * channels - 1);
36ce8582	300	regs->srgr1 \|= FWID(0);
ba9d0fd0 JN	301	break;
	302	}
	303
2e74796a JN	304	omap_mcbsp_config(bus_id, &mcbsp_data->regs);
	305	mcbsp_data->configured = 1;
	306
	307	return 0;
	308	}
	309
	310	/*
	311	* This must be called before _set_clkdiv and _set_sysclk since McBSP register
	312	* cache is initialized here
	313	*/
8687eb8b	314	static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
2e74796a JN	315	unsigned int fmt)
	316	{
	317	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	318	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
36ce8582	319	unsigned int temp_fmt = fmt;
2e74796a JN	320
	321	if (mcbsp_data->configured)
	322	return 0;
	323
ba9d0fd0	324	mcbsp_data->fmt = fmt;
2e74796a JN	325	memset(regs, 0, sizeof(*regs));
	326	/* Generic McBSP register settings */
	327	regs->spcr2 \|= XINTM(3) \| FREE;
	328	regs->spcr1 \|= RINTM(3);
c721bbda EN	329	/* RFIG and XFIG are not defined in 34xx */
	330	if (!cpu_is_omap34xx()) {
	331	regs->rcr2 \|= RFIG;
	332	regs->xcr2 \|= XFIG;
	333	}
ef390c0b MLC	334	if (cpu_is_omap2430() \|\| cpu_is_omap34xx()) {
	335	regs->xccr = DXENDLY(1) \| XDMAEN;
	336	regs->rccr = RFULL_CYCLE \| RDMAEN;
	337	}
2e74796a JN	338
	339	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	340	case SND_SOC_DAIFMT_I2S:
	341	/* 1-bit data delay */
	342	regs->rcr2 \|= RDATDLY(1);
	343	regs->xcr2 \|= XDATDLY(1);
ca6e2ce0 EN	344	regs->rccr \|= RFULL_CYCLE \| RDMAEN \| RDISABLE;
ca6e2ce0 EN	345	regs->xccr \|= (DXENDLY(1) \| XDMAEN \| XDISABLE);
2e74796a	346	break;
3ba191ce PU	347	case SND_SOC_DAIFMT_DSP_A:
	348	/* 1-bit data delay */
	349	regs->rcr2 \|= RDATDLY(1);
	350	regs->xcr2 \|= XDATDLY(1);
ca6e2ce0 EN	351	regs->rccr \|= RFULL_CYCLE \| RDMAEN \| RDISABLE;
ca6e2ce0 EN	352	regs->xccr \|= (DXENDLY(1) \| XDMAEN \| XDISABLE);
3ba191ce PU	353	/* Invert FS polarity configuration */
	354	temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
	355	break;
bd25867a	356	case SND_SOC_DAIFMT_DSP_B:
3336c5b5 AK	357	/* 0-bit data delay */
	358	regs->rcr2 \|= RDATDLY(0);
	359	regs->xcr2 \|= XDATDLY(0);
36ce8582 JN	360	/* Invert FS polarity configuration */
36ce8582 JN	361	temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
3336c5b5	362	break;
2e74796a JN	363	default:
	364	/* Unsupported data format */
	365	return -EINVAL;
	366	}
	367
	368	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	369	case SND_SOC_DAIFMT_CBS_CFS:
	370	/* McBSP master. Set FS and bit clocks as outputs */
	371	regs->pcr0 \|= FSXM \| FSRM \|
	372	CLKXM \| CLKRM;
	373	/* Sample rate generator drives the FS */
	374	regs->srgr2 \|= FSGM;
	375	break;
	376	case SND_SOC_DAIFMT_CBM_CFM:
	377	/* McBSP slave */
	378	break;
	379	default:
	380	/* Unsupported master/slave configuration */
	381	return -EINVAL;
	382	}
	383
	384	/* Set bit clock (CLKX/CLKR) and FS polarities */
36ce8582	385	switch (temp_fmt & SND_SOC_DAIFMT_INV_MASK) {
2e74796a JN	386	case SND_SOC_DAIFMT_NB_NF:
	387	/*
	388	* Normal BCLK + FS.
	389	* FS active low. TX data driven on falling edge of bit clock
	390	* and RX data sampled on rising edge of bit clock.
	391	*/
	392	regs->pcr0 \|= FSXP \| FSRP \|
	393	CLKXP \| CLKRP;
	394	break;
	395	case SND_SOC_DAIFMT_NB_IF:
	396	regs->pcr0 \|= CLKXP \| CLKRP;
	397	break;
	398	case SND_SOC_DAIFMT_IB_NF:
	399	regs->pcr0 \|= FSXP \| FSRP;
	400	break;
	401	case SND_SOC_DAIFMT_IB_IF:
	402	break;
	403	default:
	404	return -EINVAL;
	405	}
	406
	407	return 0;
	408	}
	409
8687eb8b	410	static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
2e74796a JN	411	int div_id, int div)
	412	{
	413	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	414	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
	415
	416	if (div_id != OMAP_MCBSP_CLKGDV)
	417	return -ENODEV;
	418
	419	regs->srgr1 \|= CLKGDV(div - 1);
	420
	421	return 0;
	422	}
	423
	424	static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data,
	425	int clk_id)
	426	{
	427	int sel_bit;
406e2c48	428	u16 reg, reg_devconf1 = OMAP243X_CONTROL_DEVCONF1;
2e74796a JN	429
	430	if (cpu_class_is_omap1()) {
	431	/* OMAP1's can use only external source clock */
	432	if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK))
	433	return -EINVAL;
	434	else
	435	return 0;
	436	}
	437
406e2c48 JN	438	if (cpu_is_omap2420() && mcbsp_data->bus_id > 1)
	439	return -EINVAL;
	440
	441	if (cpu_is_omap343x())
	442	reg_devconf1 = OMAP343X_CONTROL_DEVCONF1;
	443
2e74796a JN	444	switch (mcbsp_data->bus_id) {
	445	case 0:
	446	reg = OMAP2_CONTROL_DEVCONF0;
	447	sel_bit = 2;
	448	break;
	449	case 1:
	450	reg = OMAP2_CONTROL_DEVCONF0;
	451	sel_bit = 6;
	452	break;
406e2c48 JN	453	case 2:
	454	reg = reg_devconf1;
	455	sel_bit = 0;
	456	break;
	457	case 3:
	458	reg = reg_devconf1;
	459	sel_bit = 2;
	460	break;
	461	case 4:
	462	reg = reg_devconf1;
	463	sel_bit = 4;
	464	break;
2e74796a JN	465	default:
	466	return -EINVAL;
	467	}
	468
406e2c48 JN	469	if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK)
	470	omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
	471	else
	472	omap_ctrl_writel(omap_ctrl_readl(reg) \| (1 << sel_bit), reg);
2e74796a JN	473
	474	return 0;
	475	}
	476
8687eb8b	477	static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
2e74796a JN	478	int clk_id, unsigned int freq,
	479	int dir)
	480	{
	481	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
	482	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
	483	int err = 0;
	484
	485	switch (clk_id) {
	486	case OMAP_MCBSP_SYSCLK_CLK:
	487	regs->srgr2 \|= CLKSM;
	488	break;
	489	case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
	490	case OMAP_MCBSP_SYSCLK_CLKS_EXT:
	491	err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id);
	492	break;
	493
	494	case OMAP_MCBSP_SYSCLK_CLKX_EXT:
	495	regs->srgr2 \|= CLKSM;
	496	case OMAP_MCBSP_SYSCLK_CLKR_EXT:
	497	regs->pcr0 \|= SCLKME;
	498	break;
	499	default:
	500	err = -ENODEV;
	501	}
	502
	503	return err;
	504	}
	505
6335d055 EM	506	static struct snd_soc_dai_ops omap_mcbsp_dai_ops = {
	507	.startup = omap_mcbsp_dai_startup,
	508	.shutdown = omap_mcbsp_dai_shutdown,
	509	.trigger = omap_mcbsp_dai_trigger,
	510	.hw_params = omap_mcbsp_dai_hw_params,
	511	.set_fmt = omap_mcbsp_dai_set_dai_fmt,
	512	.set_clkdiv = omap_mcbsp_dai_set_clkdiv,
	513	.set_sysclk = omap_mcbsp_dai_set_dai_sysclk,
	514	};
	515
8def464d JN	516	#define OMAP_MCBSP_DAI_BUILDER(link_id) \
8def464d JN	517	{ \
0c758bdd	518	.name = "omap-mcbsp-dai-"#link_id, \
8def464d	519	.id = (link_id), \
8def464d	520	.playback = { \
375e8a7c	521	.channels_min = 1, \
31a00c6b	522	.channels_max = 4, \
8def464d JN	523	.rates = OMAP_MCBSP_RATES, \
	524	.formats = SNDRV_PCM_FMTBIT_S16_LE, \
	525	}, \
	526	.capture = { \
375e8a7c	527	.channels_min = 1, \
31a00c6b	528	.channels_max = 4, \
8def464d JN	529	.rates = OMAP_MCBSP_RATES, \
	530	.formats = SNDRV_PCM_FMTBIT_S16_LE, \
	531	}, \
6335d055	532	.ops = &omap_mcbsp_dai_ops, \
8def464d JN	533	.private_data = &mcbsp_data[(link_id)].bus_id, \
	534	}
	535
	536	struct snd_soc_dai omap_mcbsp_dai[] = {
	537	OMAP_MCBSP_DAI_BUILDER(0),
	538	OMAP_MCBSP_DAI_BUILDER(1),
	539	#if NUM_LINKS >= 3
	540	OMAP_MCBSP_DAI_BUILDER(2),
	541	#endif
	542	#if NUM_LINKS == 5
	543	OMAP_MCBSP_DAI_BUILDER(3),
	544	OMAP_MCBSP_DAI_BUILDER(4),
	545	#endif
2e74796a	546	};
8def464d	547
2e74796a JN	548	EXPORT_SYMBOL_GPL(omap_mcbsp_dai);
2e74796a JN	549
f73f2a6a	550	static int __init snd_omap_mcbsp_init(void)
3f4b783c MB	551	{
	552	return snd_soc_register_dais(omap_mcbsp_dai,
	553	ARRAY_SIZE(omap_mcbsp_dai));
	554	}
f73f2a6a	555	module_init(snd_omap_mcbsp_init);
3f4b783c	556
f73f2a6a	557	static void __exit snd_omap_mcbsp_exit(void)
3f4b783c MB	558	{
	559	snd_soc_unregister_dais(omap_mcbsp_dai, ARRAY_SIZE(omap_mcbsp_dai));
	560	}
f73f2a6a	561	module_exit(snd_omap_mcbsp_exit);
3f4b783c	562
b08f7a62	563	MODULE_AUTHOR("Jarkko Nikula <jhnikula@gmail.com>");
2e74796a JN	564	MODULE_DESCRIPTION("OMAP I2S SoC Interface");
2e74796a JN	565	MODULE_LICENSE("GPL");