[mirror_ubuntu-zesty-kernel.git] / sound / soc / rockchip / rockchip_i2s.c

/* sound/soc/rockchip/rockchip_i2s.c
 *
 * ALSA SoC Audio Layer - Rockchip I2S Controller driver
 *
 * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
 * Author: Jianqun <jay.xu@rock-chips.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/delay.h>
#include <linux/of_gpio.h>
#include <linux/clk.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <sound/pcm_params.h>
#include <sound/dmaengine_pcm.h>

#include "rockchip_i2s.h"

#define DRV_NAME "rockchip-i2s"

struct rk_i2s_dev {
	struct device *dev;

	struct clk *hclk;
	struct clk *mclk;

	struct snd_dmaengine_dai_dma_data capture_dma_data;
	struct snd_dmaengine_dai_dma_data playback_dma_data;

	struct regmap *regmap;

/*
 * Used to indicate the tx/rx status.
 * I2S controller hopes to start the tx and rx together,
 * also to stop them when they are both try to stop.
*/
	bool tx_start;
	bool rx_start;
};

static int i2s_runtime_suspend(struct device *dev)
{
	struct rk_i2s_dev *i2s = dev_get_drvdata(dev);

	clk_disable_unprepare(i2s->mclk);

	return 0;
}

static int i2s_runtime_resume(struct device *dev)
{
	struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
	int ret;

	ret = clk_prepare_enable(i2s->mclk);
	if (ret) {
		dev_err(i2s->dev, "clock enable failed %d\n", ret);
		return ret;
	}

	return 0;
}

static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
{
	return snd_soc_dai_get_drvdata(dai);
}

static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
{
	unsigned int val = 0;
	int retry = 10;

	if (on) {
		regmap_update_bits(i2s->regmap, I2S_DMACR,
				   I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);

		regmap_update_bits(i2s->regmap, I2S_XFER,
				   I2S_XFER_TXS_START | I2S_XFER_RXS_START,
				   I2S_XFER_TXS_START | I2S_XFER_RXS_START);

		i2s->tx_start = true;
	} else {
		i2s->tx_start = false;

		regmap_update_bits(i2s->regmap, I2S_DMACR,
				   I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);

		if (!i2s->rx_start) {
			regmap_update_bits(i2s->regmap, I2S_XFER,
					   I2S_XFER_TXS_START |
					   I2S_XFER_RXS_START,
					   I2S_XFER_TXS_STOP |
					   I2S_XFER_RXS_STOP);

			regmap_update_bits(i2s->regmap, I2S_CLR,
					   I2S_CLR_TXC | I2S_CLR_RXC,
					   I2S_CLR_TXC | I2S_CLR_RXC);

			regmap_read(i2s->regmap, I2S_CLR, &val);

			/* Should wait for clear operation to finish */
			while (val) {
				regmap_read(i2s->regmap, I2S_CLR, &val);
				retry--;
				if (!retry) {
					dev_warn(i2s->dev, "fail to clear\n");
					break;
				}
			}
		}
	}
}

static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
{
	unsigned int val = 0;
	int retry = 10;

	if (on) {
		regmap_update_bits(i2s->regmap, I2S_DMACR,
				   I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);

		regmap_update_bits(i2s->regmap, I2S_XFER,
				   I2S_XFER_TXS_START | I2S_XFER_RXS_START,
				   I2S_XFER_TXS_START | I2S_XFER_RXS_START);

		i2s->rx_start = true;
	} else {
		i2s->rx_start = false;

		regmap_update_bits(i2s->regmap, I2S_DMACR,
				   I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);

		if (!i2s->tx_start) {
			regmap_update_bits(i2s->regmap, I2S_XFER,
					   I2S_XFER_TXS_START |
					   I2S_XFER_RXS_START,
					   I2S_XFER_TXS_STOP |
					   I2S_XFER_RXS_STOP);

			regmap_update_bits(i2s->regmap, I2S_CLR,
					   I2S_CLR_TXC | I2S_CLR_RXC,
					   I2S_CLR_TXC | I2S_CLR_RXC);

			regmap_read(i2s->regmap, I2S_CLR, &val);

			/* Should wait for clear operation to finish */
			while (val) {
				regmap_read(i2s->regmap, I2S_CLR, &val);
				retry--;
				if (!retry) {
					dev_warn(i2s->dev, "fail to clear\n");
					break;
				}
			}
		}
	}
}

static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
				unsigned int fmt)
{
	struct rk_i2s_dev *i2s = to_info(cpu_dai);
	unsigned int mask = 0, val = 0;

	mask = I2S_CKR_MSS_MASK;
	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		/* Set source clock in Master mode */
		val = I2S_CKR_MSS_MASTER;
		break;
	case SND_SOC_DAIFMT_CBM_CFM:
		val = I2S_CKR_MSS_SLAVE;
		break;
	default:
		return -EINVAL;
	}

	regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);

	mask = I2S_TXCR_IBM_MASK;
	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_RIGHT_J:
		val = I2S_TXCR_IBM_RSJM;
		break;
	case SND_SOC_DAIFMT_LEFT_J:
		val = I2S_TXCR_IBM_LSJM;
		break;
	case SND_SOC_DAIFMT_I2S:
		val = I2S_TXCR_IBM_NORMAL;
		break;
	default:
		return -EINVAL;
	}

	regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);

	mask = I2S_RXCR_IBM_MASK;
	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_RIGHT_J:
		val = I2S_RXCR_IBM_RSJM;
		break;
	case SND_SOC_DAIFMT_LEFT_J:
		val = I2S_RXCR_IBM_LSJM;
		break;
	case SND_SOC_DAIFMT_I2S:
		val = I2S_RXCR_IBM_NORMAL;
		break;
	default:
		return -EINVAL;
	}

	regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);

	return 0;
}

static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
				  struct snd_pcm_hw_params *params,
				  struct snd_soc_dai *dai)
{
	struct rk_i2s_dev *i2s = to_info(dai);
	unsigned int val = 0;

	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S8:
		val |= I2S_TXCR_VDW(8);
		break;
	case SNDRV_PCM_FORMAT_S16_LE:
		val |= I2S_TXCR_VDW(16);
		break;
	case SNDRV_PCM_FORMAT_S20_3LE:
		val |= I2S_TXCR_VDW(20);
		break;
	case SNDRV_PCM_FORMAT_S24_LE:
		val |= I2S_TXCR_VDW(24);
		break;
	default:
		return -EINVAL;
	}

	switch (params_channels(params)) {
	case 8:
		val |= I2S_CHN_8;
		break;
	case 6:
		val |= I2S_CHN_6;
		break;
	case 4:
		val |= I2S_CHN_4;
		break;
	case 2:
		val |= I2S_CHN_2;
		break;
	default:
		dev_err(i2s->dev, "invalid channel: %d\n",
			params_channels(params));
		return -EINVAL;
	}

	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
		regmap_update_bits(i2s->regmap, I2S_RXCR,
				   I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
				   val);
	else
		regmap_update_bits(i2s->regmap, I2S_TXCR,
				   I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
				   val);

	regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
			   I2S_DMACR_TDL(16));
	regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
			   I2S_DMACR_RDL(16));

	return 0;
}

static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
				int cmd, struct snd_soc_dai *dai)
{
	struct rk_i2s_dev *i2s = to_info(dai);
	int ret = 0;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
			rockchip_snd_rxctrl(i2s, 1);
		else
			rockchip_snd_txctrl(i2s, 1);
		break;
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
			rockchip_snd_rxctrl(i2s, 0);
		else
			rockchip_snd_txctrl(i2s, 0);
		break;
	default:
		ret = -EINVAL;
		break;
	}

	return ret;
}

static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
				   unsigned int freq, int dir)
{
	struct rk_i2s_dev *i2s = to_info(cpu_dai);
	int ret;

	ret = clk_set_rate(i2s->mclk, freq);
	if (ret)
		dev_err(i2s->dev, "Fail to set mclk %d\n", ret);

	return ret;
}

static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
{
	struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);

	dai->capture_dma_data = &i2s->capture_dma_data;
	dai->playback_dma_data = &i2s->playback_dma_data;

	return 0;
}

static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
	.hw_params = rockchip_i2s_hw_params,
	.set_sysclk = rockchip_i2s_set_sysclk,
	.set_fmt = rockchip_i2s_set_fmt,
	.trigger = rockchip_i2s_trigger,
};

static struct snd_soc_dai_driver rockchip_i2s_dai = {
	.probe = rockchip_i2s_dai_probe,
	.playback = {
		.stream_name = "Playback",
		.channels_min = 2,
		.channels_max = 8,
		.rates = SNDRV_PCM_RATE_8000_192000,
		.formats = (SNDRV_PCM_FMTBIT_S8 |
			    SNDRV_PCM_FMTBIT_S16_LE |
			    SNDRV_PCM_FMTBIT_S20_3LE |
			    SNDRV_PCM_FMTBIT_S24_LE),
	},
	.capture = {
		.stream_name = "Capture",
		.channels_min = 2,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_192000,
		.formats = (SNDRV_PCM_FMTBIT_S8 |
			    SNDRV_PCM_FMTBIT_S16_LE |
			    SNDRV_PCM_FMTBIT_S20_3LE |
			    SNDRV_PCM_FMTBIT_S24_LE),
	},
	.ops = &rockchip_i2s_dai_ops,
	.symmetric_rates = 1,
};

static const struct snd_soc_component_driver rockchip_i2s_component = {
	.name = DRV_NAME,
};

static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case I2S_TXCR:
	case I2S_RXCR:
	case I2S_CKR:
	case I2S_DMACR:
	case I2S_INTCR:
	case I2S_XFER:
	case I2S_CLR:
	case I2S_TXDR:
		return true;
	default:
		return false;
	}
}

static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case I2S_TXCR:
	case I2S_RXCR:
	case I2S_CKR:
	case I2S_DMACR:
	case I2S_INTCR:
	case I2S_XFER:
	case I2S_CLR:
	case I2S_RXDR:
	case I2S_FIFOLR:
	case I2S_INTSR:
		return true;
	default:
		return false;
	}
}

static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case I2S_INTSR:
	case I2S_CLR:
		return true;
	default:
		return false;
	}
}

static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	default:
		return false;
	}
}

static const struct regmap_config rockchip_i2s_regmap_config = {
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,
	.max_register = I2S_RXDR,
	.writeable_reg = rockchip_i2s_wr_reg,
	.readable_reg = rockchip_i2s_rd_reg,
	.volatile_reg = rockchip_i2s_volatile_reg,
	.precious_reg = rockchip_i2s_precious_reg,
	.cache_type = REGCACHE_FLAT,
};

static int rockchip_i2s_probe(struct platform_device *pdev)
{
	struct device_node *node = pdev->dev.of_node;
	struct rk_i2s_dev *i2s;
	struct resource *res;
	void __iomem *regs;
	int ret;
	int val;

	i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
	if (!i2s) {
		dev_err(&pdev->dev, "Can't allocate rk_i2s_dev\n");
		return -ENOMEM;
	}

	/* try to prepare related clocks */
	i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
	if (IS_ERR(i2s->hclk)) {
		dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
		return PTR_ERR(i2s->hclk);
	}
	ret = clk_prepare_enable(i2s->hclk);
	if (ret) {
		dev_err(i2s->dev, "hclock enable failed %d\n", ret);
		return ret;
	}

	i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
	if (IS_ERR(i2s->mclk)) {
		dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
		return PTR_ERR(i2s->mclk);
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(regs))
		return PTR_ERR(regs);

	i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
					    &rockchip_i2s_regmap_config);
	if (IS_ERR(i2s->regmap)) {
		dev_err(&pdev->dev,
			"Failed to initialise managed register map\n");
		return PTR_ERR(i2s->regmap);
	}

	i2s->playback_dma_data.addr = res->start + I2S_TXDR;
	i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	i2s->playback_dma_data.maxburst = 4;

	i2s->capture_dma_data.addr = res->start + I2S_RXDR;
	i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	i2s->capture_dma_data.maxburst = 4;

	i2s->dev = &pdev->dev;
	dev_set_drvdata(&pdev->dev, i2s);

	pm_runtime_enable(&pdev->dev);
	if (!pm_runtime_enabled(&pdev->dev)) {
		ret = i2s_runtime_resume(&pdev->dev);
		if (ret)
			goto err_pm_disable;
	}

	/* refine capture channels */
	if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
		if (val >= 2 && val <= 8)
			rockchip_i2s_dai.capture.channels_max = val;
		else
			rockchip_i2s_dai.capture.channels_max = 2;
	}

	ret = devm_snd_soc_register_component(&pdev->dev,
					      &rockchip_i2s_component,
					      &rockchip_i2s_dai, 1);
	if (ret) {
		dev_err(&pdev->dev, "Could not register DAI\n");
		goto err_suspend;
	}

	ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
	if (ret) {
		dev_err(&pdev->dev, "Could not register PCM\n");
		return ret;
	}

	return 0;

err_suspend:
	if (!pm_runtime_status_suspended(&pdev->dev))
		i2s_runtime_suspend(&pdev->dev);
err_pm_disable:
	pm_runtime_disable(&pdev->dev);

	return ret;
}

static int rockchip_i2s_remove(struct platform_device *pdev)
{
	struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);

	pm_runtime_disable(&pdev->dev);
	if (!pm_runtime_status_suspended(&pdev->dev))
		i2s_runtime_suspend(&pdev->dev);

	clk_disable_unprepare(i2s->mclk);
	clk_disable_unprepare(i2s->hclk);

	return 0;
}

static const struct of_device_id rockchip_i2s_match[] = {
	{ .compatible = "rockchip,rk3066-i2s", },
	{},
};

static const struct dev_pm_ops rockchip_i2s_pm_ops = {
	SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
			   NULL)
};

static struct platform_driver rockchip_i2s_driver = {
	.probe = rockchip_i2s_probe,
	.remove = rockchip_i2s_remove,
	.driver = {
		.name = DRV_NAME,
		.of_match_table = of_match_ptr(rockchip_i2s_match),
		.pm = &rockchip_i2s_pm_ops,
	},
};
module_platform_driver(rockchip_i2s_driver);

MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRV_NAME);
MODULE_DEVICE_TABLE(of, rockchip_i2s_match);
Commit	Line	Data
4495c89f JX	1	/* sound/soc/rockchip/rockchip_i2s.c
	2	*
	3	* ALSA SoC Audio Layer - Rockchip I2S Controller driver
	4	*
	5	* Copyright (c) 2014 Rockchip Electronics Co. Ltd.
	6	* Author: Jianqun <jay.xu@rock-chips.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
1b21572f	13	#include <linux/module.h>
4495c89f JX	14	#include <linux/delay.h>
	15	#include <linux/of_gpio.h>
	16	#include <linux/clk.h>
	17	#include <linux/pm_runtime.h>
	18	#include <linux/regmap.h>
	19	#include <sound/pcm_params.h>
	20	#include <sound/dmaengine_pcm.h>
	21
	22	#include "rockchip_i2s.h"
	23
	24	#define DRV_NAME "rockchip-i2s"
	25
	26	struct rk_i2s_dev {
	27	struct device *dev;
	28
	29	struct clk *hclk;
	30	struct clk *mclk;
	31
	32	struct snd_dmaengine_dai_dma_data capture_dma_data;
	33	struct snd_dmaengine_dai_dma_data playback_dma_data;
	34
	35	struct regmap *regmap;
	36
	37	/*
	38	* Used to indicate the tx/rx status.
	39	* I2S controller hopes to start the tx and rx together,
	40	* also to stop them when they are both try to stop.
	41	*/
	42	bool tx_start;
	43	bool rx_start;
	44	};
	45
	46	static int i2s_runtime_suspend(struct device *dev)
	47	{
	48	struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
	49
	50	clk_disable_unprepare(i2s->mclk);
	51
	52	return 0;
	53	}
	54
	55	static int i2s_runtime_resume(struct device *dev)
	56	{
	57	struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
	58	int ret;
	59
	60	ret = clk_prepare_enable(i2s->mclk);
	61	if (ret) {
	62	dev_err(i2s->dev, "clock enable failed %d\n", ret);
	63	return ret;
	64	}
	65
	66	return 0;
	67	}
	68
	69	static inline struct rk_i2s_dev to_info(struct snd_soc_dai dai)
	70	{
	71	return snd_soc_dai_get_drvdata(dai);
	72	}
	73
	74	static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
	75	{
	76	unsigned int val = 0;
	77	int retry = 10;
78
79	if (on) {
80	regmap_update_bits(i2s->regmap, I2S_DMACR,
81	I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
82
83	regmap_update_bits(i2s->regmap, I2S_XFER,
84	I2S_XFER_TXS_START \| I2S_XFER_RXS_START,
85	I2S_XFER_TXS_START \| I2S_XFER_RXS_START);
86
87	i2s->tx_start = true;
88	} else {
89	i2s->tx_start = false;
90
91	regmap_update_bits(i2s->regmap, I2S_DMACR,
4c5258ac	92	I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
4495c89f JX	93
	94	if (!i2s->rx_start) {
	95	regmap_update_bits(i2s->regmap, I2S_XFER,
	96	I2S_XFER_TXS_START \|
	97	I2S_XFER_RXS_START,
	98	I2S_XFER_TXS_STOP \|
	99	I2S_XFER_RXS_STOP);
	100
	101	regmap_update_bits(i2s->regmap, I2S_CLR,
4c5258ac	102	I2S_CLR_TXC \| I2S_CLR_RXC,
4c5258ac	103	I2S_CLR_TXC \| I2S_CLR_RXC);
4495c89f JX	104
	105	regmap_read(i2s->regmap, I2S_CLR, &val);
	106
	107	/* Should wait for clear operation to finish */
	108	while (val) {
	109	regmap_read(i2s->regmap, I2S_CLR, &val);
	110	retry--;
528a82b4	111	if (!retry) {
4495c89f	112	dev_warn(i2s->dev, "fail to clear\n");
528a82b4 SR	113	break;
528a82b4 SR	114	}
4495c89f JX	115	}
	116	}
	117	}
	118	}
	119
	120	static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
	121	{
	122	unsigned int val = 0;
	123	int retry = 10;
	124
	125	if (on) {
	126	regmap_update_bits(i2s->regmap, I2S_DMACR,
	127	I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
	128
	129	regmap_update_bits(i2s->regmap, I2S_XFER,
	130	I2S_XFER_TXS_START \| I2S_XFER_RXS_START,
	131	I2S_XFER_TXS_START \| I2S_XFER_RXS_START);
	132
	133	i2s->rx_start = true;
	134	} else {
	135	i2s->rx_start = false;
	136
	137	regmap_update_bits(i2s->regmap, I2S_DMACR,
	138	I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
	139
	140	if (!i2s->tx_start) {
	141	regmap_update_bits(i2s->regmap, I2S_XFER,
	142	I2S_XFER_TXS_START \|
	143	I2S_XFER_RXS_START,
	144	I2S_XFER_TXS_STOP \|
	145	I2S_XFER_RXS_STOP);
	146
	147	regmap_update_bits(i2s->regmap, I2S_CLR,
4c5258ac	148	I2S_CLR_TXC \| I2S_CLR_RXC,
4c5258ac	149	I2S_CLR_TXC \| I2S_CLR_RXC);
4495c89f JX	150
	151	regmap_read(i2s->regmap, I2S_CLR, &val);
	152
	153	/* Should wait for clear operation to finish */
	154	while (val) {
	155	regmap_read(i2s->regmap, I2S_CLR, &val);
	156	retry--;
29f95bd7	157	if (!retry) {
4495c89f	158	dev_warn(i2s->dev, "fail to clear\n");
29f95bd7 J	159	break;
29f95bd7 J	160	}
4495c89f JX	161	}
	162	}
	163	}
	164	}
	165
	166	static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
	167	unsigned int fmt)
	168	{
	169	struct rk_i2s_dev *i2s = to_info(cpu_dai);
	170	unsigned int mask = 0, val = 0;
	171
07833d88	172	mask = I2S_CKR_MSS_MASK;
4495c89f JX	173	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
4495c89f JX	174	case SND_SOC_DAIFMT_CBS_CFS:
07833d88 J	175	/* Set source clock in Master mode */
07833d88 J	176	val = I2S_CKR_MSS_MASTER;
4495c89f JX	177	break;
4495c89f JX	178	case SND_SOC_DAIFMT_CBM_CFM:
07833d88	179	val = I2S_CKR_MSS_SLAVE;
4495c89f JX	180	break;
	181	default:
	182	return -EINVAL;
	183	}
	184
	185	regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
	186
	187	mask = I2S_TXCR_IBM_MASK;
	188	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	189	case SND_SOC_DAIFMT_RIGHT_J:
	190	val = I2S_TXCR_IBM_RSJM;
	191	break;
	192	case SND_SOC_DAIFMT_LEFT_J:
	193	val = I2S_TXCR_IBM_LSJM;
	194	break;
	195	case SND_SOC_DAIFMT_I2S:
	196	val = I2S_TXCR_IBM_NORMAL;
	197	break;
	198	default:
	199	return -EINVAL;
	200	}
	201
	202	regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
	203
	204	mask = I2S_RXCR_IBM_MASK;
	205	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	206	case SND_SOC_DAIFMT_RIGHT_J:
	207	val = I2S_RXCR_IBM_RSJM;
	208	break;
	209	case SND_SOC_DAIFMT_LEFT_J:
	210	val = I2S_RXCR_IBM_LSJM;
	211	break;
	212	case SND_SOC_DAIFMT_I2S:
	213	val = I2S_RXCR_IBM_NORMAL;
	214	break;
	215	default:
	216	return -EINVAL;
	217	}
	218
	219	regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
	220
	221	return 0;
	222	}
	223
	224	static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
	225	struct snd_pcm_hw_params *params,
	226	struct snd_soc_dai *dai)
	227	{
	228	struct rk_i2s_dev *i2s = to_info(dai);
	229	unsigned int val = 0;
	230
	231	switch (params_format(params)) {
	232	case SNDRV_PCM_FORMAT_S8:
	233	val \|= I2S_TXCR_VDW(8);
	234	break;
	235	case SNDRV_PCM_FORMAT_S16_LE:
	236	val \|= I2S_TXCR_VDW(16);
	237	break;
	238	case SNDRV_PCM_FORMAT_S20_3LE:
	239	val \|= I2S_TXCR_VDW(20);
	240	break;
	241	case SNDRV_PCM_FORMAT_S24_LE:
	242	val \|= I2S_TXCR_VDW(24);
	243	break;
244	default:
245	return -EINVAL;
246	}
247
4c9c018b SZ	248	switch (params_channels(params)) {
	249	case 8:
	250	val \|= I2S_CHN_8;
	251	break;
	252	case 6:
	253	val \|= I2S_CHN_6;
	254	break;
	255	case 4:
	256	val \|= I2S_CHN_4;
	257	break;
	258	case 2:
	259	val \|= I2S_CHN_2;
	260	break;
	261	default:
	262	dev_err(i2s->dev, "invalid channel: %d\n",
	263	params_channels(params));
	264	return -EINVAL;
	265	}
	266
	267	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
	268	regmap_update_bits(i2s->regmap, I2S_RXCR,
	269	I2S_RXCR_VDW_MASK \| I2S_RXCR_CSR_MASK,
	270	val);
	271	else
	272	regmap_update_bits(i2s->regmap, I2S_TXCR,
	273	I2S_TXCR_VDW_MASK \| I2S_TXCR_CSR_MASK,
	274	val);
	275
bba14312 JX	276	regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
	277	I2S_DMACR_TDL(16));
	278	regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
	279	I2S_DMACR_RDL(16));
4495c89f	280
4495c89f JX	281	return 0;
	282	}
	283
	284	static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
	285	int cmd, struct snd_soc_dai *dai)
	286	{
	287	struct rk_i2s_dev *i2s = to_info(dai);
	288	int ret = 0;
	289
	290	switch (cmd) {
	291	case SNDRV_PCM_TRIGGER_START:
	292	case SNDRV_PCM_TRIGGER_RESUME:
	293	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	294	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
	295	rockchip_snd_rxctrl(i2s, 1);
	296	else
	297	rockchip_snd_txctrl(i2s, 1);
	298	break;
	299	case SNDRV_PCM_TRIGGER_SUSPEND:
	300	case SNDRV_PCM_TRIGGER_STOP:
	301	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	302	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
	303	rockchip_snd_rxctrl(i2s, 0);
	304	else
	305	rockchip_snd_txctrl(i2s, 0);
	306	break;
	307	default:
	308	ret = -EINVAL;
	309	break;
	310	}
	311
	312	return ret;
	313	}
	314
	315	static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
	316	unsigned int freq, int dir)
	317	{
	318	struct rk_i2s_dev *i2s = to_info(cpu_dai);
	319	int ret;
	320
	321	ret = clk_set_rate(i2s->mclk, freq);
	322	if (ret)
	323	dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
	324
	325	return ret;
	326	}
	327
3b40a802 J	328	static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
	329	{
	330	struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
	331
	332	dai->capture_dma_data = &i2s->capture_dma_data;
	333	dai->playback_dma_data = &i2s->playback_dma_data;
	334
	335	return 0;
	336	}
	337
4495c89f JX	338	static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
	339	.hw_params = rockchip_i2s_hw_params,
	340	.set_sysclk = rockchip_i2s_set_sysclk,
	341	.set_fmt = rockchip_i2s_set_fmt,
	342	.trigger = rockchip_i2s_trigger,
	343	};
	344
	345	static struct snd_soc_dai_driver rockchip_i2s_dai = {
3b40a802	346	.probe = rockchip_i2s_dai_probe,
4495c89f	347	.playback = {
3b40a802	348	.stream_name = "Playback",
4495c89f JX	349	.channels_min = 2,
	350	.channels_max = 8,
	351	.rates = SNDRV_PCM_RATE_8000_192000,
	352	.formats = (SNDRV_PCM_FMTBIT_S8 \|
	353	SNDRV_PCM_FMTBIT_S16_LE \|
	354	SNDRV_PCM_FMTBIT_S20_3LE \|
	355	SNDRV_PCM_FMTBIT_S24_LE),
	356	},
	357	.capture = {
3b40a802	358	.stream_name = "Capture",
4495c89f JX	359	.channels_min = 2,
	360	.channels_max = 2,
	361	.rates = SNDRV_PCM_RATE_8000_192000,
	362	.formats = (SNDRV_PCM_FMTBIT_S8 \|
	363	SNDRV_PCM_FMTBIT_S16_LE \|
	364	SNDRV_PCM_FMTBIT_S20_3LE \|
	365	SNDRV_PCM_FMTBIT_S24_LE),
	366	},
	367	.ops = &rockchip_i2s_dai_ops,
a12d159d	368	.symmetric_rates = 1,
4495c89f JX	369	};
	370
	371	static const struct snd_soc_component_driver rockchip_i2s_component = {
	372	.name = DRV_NAME,
	373	};
	374
	375	static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
	376	{
	377	switch (reg) {
	378	case I2S_TXCR:
	379	case I2S_RXCR:
	380	case I2S_CKR:
	381	case I2S_DMACR:
	382	case I2S_INTCR:
	383	case I2S_XFER:
	384	case I2S_CLR:
	385	case I2S_TXDR:
	386	return true;
	387	default:
	388	return false;
	389	}
	390	}
	391
	392	static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
	393	{
	394	switch (reg) {
	395	case I2S_TXCR:
	396	case I2S_RXCR:
	397	case I2S_CKR:
	398	case I2S_DMACR:
	399	case I2S_INTCR:
	400	case I2S_XFER:
	401	case I2S_CLR:
	402	case I2S_RXDR:
2f1e93f8 J	403	case I2S_FIFOLR:
2f1e93f8 J	404	case I2S_INTSR:
4495c89f JX	405	return true;
	406	default:
	407	return false;
	408	}
	409	}
	410
	411	static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
	412	{
	413	switch (reg) {
4495c89f	414	case I2S_INTSR:
2f1e93f8	415	case I2S_CLR:
4495c89f JX	416	return true;
	417	default:
	418	return false;
	419	}
	420	}
	421
	422	static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
	423	{
	424	switch (reg) {
4495c89f JX	425	default:
	426	return false;
	427	}
	428	}
	429
	430	static const struct regmap_config rockchip_i2s_regmap_config = {
	431	.reg_bits = 32,
	432	.reg_stride = 4,
	433	.val_bits = 32,
	434	.max_register = I2S_RXDR,
	435	.writeable_reg = rockchip_i2s_wr_reg,
	436	.readable_reg = rockchip_i2s_rd_reg,
	437	.volatile_reg = rockchip_i2s_volatile_reg,
	438	.precious_reg = rockchip_i2s_precious_reg,
	439	.cache_type = REGCACHE_FLAT,
	440	};
	441
	442	static int rockchip_i2s_probe(struct platform_device *pdev)
	443	{
4c9c018b	444	struct device_node *node = pdev->dev.of_node;
4495c89f JX	445	struct rk_i2s_dev *i2s;
	446	struct resource *res;
	447	void __iomem *regs;
	448	int ret;
4c9c018b	449	int val;
4495c89f JX	450
	451	i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
	452	if (!i2s) {
	453	dev_err(&pdev->dev, "Can't allocate rk_i2s_dev\n");
	454	return -ENOMEM;
	455	}
	456
	457	/* try to prepare related clocks */
	458	i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
	459	if (IS_ERR(i2s->hclk)) {
	460	dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
	461	return PTR_ERR(i2s->hclk);
	462	}
01605ad1 J	463	ret = clk_prepare_enable(i2s->hclk);
	464	if (ret) {
	465	dev_err(i2s->dev, "hclock enable failed %d\n", ret);
	466	return ret;
	467	}
4495c89f JX	468
	469	i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
	470	if (IS_ERR(i2s->mclk)) {
	471	dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
	472	return PTR_ERR(i2s->mclk);
	473	}
	474
	475	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	476	regs = devm_ioremap_resource(&pdev->dev, res);
55b21944	477	if (IS_ERR(regs))
4495c89f	478	return PTR_ERR(regs);
4495c89f JX	479
	480	i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
	481	&rockchip_i2s_regmap_config);
	482	if (IS_ERR(i2s->regmap)) {
	483	dev_err(&pdev->dev,
	484	"Failed to initialise managed register map\n");
	485	return PTR_ERR(i2s->regmap);
	486	}
	487
	488	i2s->playback_dma_data.addr = res->start + I2S_TXDR;
	489	i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
27fd36ab	490	i2s->playback_dma_data.maxburst = 4;
4495c89f JX	491
	492	i2s->capture_dma_data.addr = res->start + I2S_RXDR;
	493	i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
27fd36ab	494	i2s->capture_dma_data.maxburst = 4;
4495c89f JX	495
	496	i2s->dev = &pdev->dev;
	497	dev_set_drvdata(&pdev->dev, i2s);
	498
	499	pm_runtime_enable(&pdev->dev);
	500	if (!pm_runtime_enabled(&pdev->dev)) {
	501	ret = i2s_runtime_resume(&pdev->dev);
	502	if (ret)
	503	goto err_pm_disable;
	504	}
	505
4c9c018b SZ	506	/* refine capture channels */
	507	if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
	508	if (val >= 2 && val <= 8)
	509	rockchip_i2s_dai.capture.channels_max = val;
	510	else
	511	rockchip_i2s_dai.capture.channels_max = 2;
	512	}
	513
4495c89f JX	514	ret = devm_snd_soc_register_component(&pdev->dev,
	515	&rockchip_i2s_component,
	516	&rockchip_i2s_dai, 1);
	517	if (ret) {
	518	dev_err(&pdev->dev, "Could not register DAI\n");
	519	goto err_suspend;
	520	}
	521
ebb75c0b	522	ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
4495c89f JX	523	if (ret) {
4495c89f JX	524	dev_err(&pdev->dev, "Could not register PCM\n");
ebb75c0b	525	return ret;
4495c89f JX	526	}
	527
	528	return 0;
	529
4495c89f JX	530	err_suspend:
	531	if (!pm_runtime_status_suspended(&pdev->dev))
	532	i2s_runtime_suspend(&pdev->dev);
	533	err_pm_disable:
	534	pm_runtime_disable(&pdev->dev);
	535
	536	return ret;
	537	}
	538
	539	static int rockchip_i2s_remove(struct platform_device *pdev)
	540	{
	541	struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
	542
	543	pm_runtime_disable(&pdev->dev);
	544	if (!pm_runtime_status_suspended(&pdev->dev))
	545	i2s_runtime_suspend(&pdev->dev);
	546
	547	clk_disable_unprepare(i2s->mclk);
	548	clk_disable_unprepare(i2s->hclk);
4495c89f JX	549
	550	return 0;
	551	}
	552
	553	static const struct of_device_id rockchip_i2s_match[] = {
	554	{ .compatible = "rockchip,rk3066-i2s", },
	555	{},
	556	};
	557
	558	static const struct dev_pm_ops rockchip_i2s_pm_ops = {
	559	SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
	560	NULL)
	561	};
	562
	563	static struct platform_driver rockchip_i2s_driver = {
	564	.probe = rockchip_i2s_probe,
	565	.remove = rockchip_i2s_remove,
	566	.driver = {
	567	.name = DRV_NAME,
4495c89f JX	568	.of_match_table = of_match_ptr(rockchip_i2s_match),
	569	.pm = &rockchip_i2s_pm_ops,
	570	},
	571	};
	572	module_platform_driver(rockchip_i2s_driver);
	573
	574	MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
	575	MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
	576	MODULE_LICENSE("GPL v2");
	577	MODULE_ALIAS("platform:" DRV_NAME);
	578	MODULE_DEVICE_TABLE(of, rockchip_i2s_match);