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1 | /* |
2 | * Copyright (C) ST-Ericsson SA 2012 | |
3 | * | |
4 | * Author: Ola Lilja <ola.o.lilja@stericsson.com>, | |
5 | * for ST-Ericsson. | |
6 | * | |
7 | * License terms: | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as published | |
11 | * by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | ||
15 | #ifndef UX500_MSP_I2S_H | |
16 | #define UX500_MSP_I2S_H | |
17 | ||
18 | #include <linux/platform_device.h> | |
19 | ||
20 | #include <mach/board-mop500-msp.h> | |
21 | ||
22 | #define MSP_INPUT_FREQ_APB 48000000 | |
23 | ||
24 | /*** Stereo mode. Used for APB data accesses as 16 bits accesses (mono), | |
25 | * 32 bits accesses (stereo). | |
26 | ***/ | |
27 | enum msp_stereo_mode { | |
28 | MSP_MONO, | |
29 | MSP_STEREO | |
30 | }; | |
31 | ||
32 | /* Direction (Transmit/Receive mode) */ | |
33 | enum msp_direction { | |
34 | MSP_TX = 1, | |
35 | MSP_RX = 2 | |
36 | }; | |
37 | ||
38 | /* Transmit and receive configuration register */ | |
39 | #define MSP_BIG_ENDIAN 0x00000000 | |
40 | #define MSP_LITTLE_ENDIAN 0x00001000 | |
41 | #define MSP_UNEXPECTED_FS_ABORT 0x00000000 | |
42 | #define MSP_UNEXPECTED_FS_IGNORE 0x00008000 | |
43 | #define MSP_NON_MODE_BIT_MASK 0x00009000 | |
44 | ||
45 | /* Global configuration register */ | |
46 | #define RX_ENABLE 0x00000001 | |
47 | #define RX_FIFO_ENABLE 0x00000002 | |
48 | #define RX_SYNC_SRG 0x00000010 | |
49 | #define RX_CLK_POL_RISING 0x00000020 | |
50 | #define RX_CLK_SEL_SRG 0x00000040 | |
51 | #define TX_ENABLE 0x00000100 | |
52 | #define TX_FIFO_ENABLE 0x00000200 | |
53 | #define TX_SYNC_SRG_PROG 0x00001800 | |
54 | #define TX_SYNC_SRG_AUTO 0x00001000 | |
55 | #define TX_CLK_POL_RISING 0x00002000 | |
56 | #define TX_CLK_SEL_SRG 0x00004000 | |
57 | #define TX_EXTRA_DELAY_ENABLE 0x00008000 | |
58 | #define SRG_ENABLE 0x00010000 | |
59 | #define FRAME_GEN_ENABLE 0x00100000 | |
60 | #define SRG_CLK_SEL_APB 0x00000000 | |
61 | #define RX_FIFO_SYNC_HI 0x00000000 | |
62 | #define TX_FIFO_SYNC_HI 0x00000000 | |
63 | #define SPI_CLK_MODE_NORMAL 0x00000000 | |
64 | ||
65 | #define MSP_FRAME_SIZE_AUTO -1 | |
66 | ||
67 | #define MSP_DR 0x00 | |
68 | #define MSP_GCR 0x04 | |
69 | #define MSP_TCF 0x08 | |
70 | #define MSP_RCF 0x0c | |
71 | #define MSP_SRG 0x10 | |
72 | #define MSP_FLR 0x14 | |
73 | #define MSP_DMACR 0x18 | |
74 | ||
75 | #define MSP_IMSC 0x20 | |
76 | #define MSP_RIS 0x24 | |
77 | #define MSP_MIS 0x28 | |
78 | #define MSP_ICR 0x2c | |
79 | #define MSP_MCR 0x30 | |
80 | #define MSP_RCV 0x34 | |
81 | #define MSP_RCM 0x38 | |
82 | ||
83 | #define MSP_TCE0 0x40 | |
84 | #define MSP_TCE1 0x44 | |
85 | #define MSP_TCE2 0x48 | |
86 | #define MSP_TCE3 0x4c | |
87 | ||
88 | #define MSP_RCE0 0x60 | |
89 | #define MSP_RCE1 0x64 | |
90 | #define MSP_RCE2 0x68 | |
91 | #define MSP_RCE3 0x6c | |
92 | #define MSP_IODLY 0x70 | |
93 | ||
94 | #define MSP_ITCR 0x80 | |
95 | #define MSP_ITIP 0x84 | |
96 | #define MSP_ITOP 0x88 | |
97 | #define MSP_TSTDR 0x8c | |
98 | ||
99 | #define MSP_PID0 0xfe0 | |
100 | #define MSP_PID1 0xfe4 | |
101 | #define MSP_PID2 0xfe8 | |
102 | #define MSP_PID3 0xfec | |
103 | ||
104 | #define MSP_CID0 0xff0 | |
105 | #define MSP_CID1 0xff4 | |
106 | #define MSP_CID2 0xff8 | |
107 | #define MSP_CID3 0xffc | |
108 | ||
109 | /* Protocol dependant parameters list */ | |
110 | #define RX_ENABLE_MASK BIT(0) | |
111 | #define RX_FIFO_ENABLE_MASK BIT(1) | |
112 | #define RX_FSYNC_MASK BIT(2) | |
113 | #define DIRECT_COMPANDING_MASK BIT(3) | |
114 | #define RX_SYNC_SEL_MASK BIT(4) | |
115 | #define RX_CLK_POL_MASK BIT(5) | |
116 | #define RX_CLK_SEL_MASK BIT(6) | |
117 | #define LOOPBACK_MASK BIT(7) | |
118 | #define TX_ENABLE_MASK BIT(8) | |
119 | #define TX_FIFO_ENABLE_MASK BIT(9) | |
120 | #define TX_FSYNC_MASK BIT(10) | |
121 | #define TX_MSP_TDR_TSR BIT(11) | |
122 | #define TX_SYNC_SEL_MASK (BIT(12) | BIT(11)) | |
123 | #define TX_CLK_POL_MASK BIT(13) | |
124 | #define TX_CLK_SEL_MASK BIT(14) | |
125 | #define TX_EXTRA_DELAY_MASK BIT(15) | |
126 | #define SRG_ENABLE_MASK BIT(16) | |
127 | #define SRG_CLK_POL_MASK BIT(17) | |
128 | #define SRG_CLK_SEL_MASK (BIT(19) | BIT(18)) | |
129 | #define FRAME_GEN_EN_MASK BIT(20) | |
130 | #define SPI_CLK_MODE_MASK (BIT(22) | BIT(21)) | |
131 | #define SPI_BURST_MODE_MASK BIT(23) | |
132 | ||
133 | #define RXEN_SHIFT 0 | |
134 | #define RFFEN_SHIFT 1 | |
135 | #define RFSPOL_SHIFT 2 | |
136 | #define DCM_SHIFT 3 | |
137 | #define RFSSEL_SHIFT 4 | |
138 | #define RCKPOL_SHIFT 5 | |
139 | #define RCKSEL_SHIFT 6 | |
140 | #define LBM_SHIFT 7 | |
141 | #define TXEN_SHIFT 8 | |
142 | #define TFFEN_SHIFT 9 | |
143 | #define TFSPOL_SHIFT 10 | |
144 | #define TFSSEL_SHIFT 11 | |
145 | #define TCKPOL_SHIFT 13 | |
146 | #define TCKSEL_SHIFT 14 | |
147 | #define TXDDL_SHIFT 15 | |
148 | #define SGEN_SHIFT 16 | |
149 | #define SCKPOL_SHIFT 17 | |
150 | #define SCKSEL_SHIFT 18 | |
151 | #define FGEN_SHIFT 20 | |
152 | #define SPICKM_SHIFT 21 | |
153 | #define TBSWAP_SHIFT 28 | |
154 | ||
155 | #define RCKPOL_MASK BIT(0) | |
156 | #define TCKPOL_MASK BIT(0) | |
157 | #define SPICKM_MASK (BIT(1) | BIT(0)) | |
158 | #define MSP_RX_CLKPOL_BIT(n) ((n & RCKPOL_MASK) << RCKPOL_SHIFT) | |
159 | #define MSP_TX_CLKPOL_BIT(n) ((n & TCKPOL_MASK) << TCKPOL_SHIFT) | |
160 | ||
161 | #define P1ELEN_SHIFT 0 | |
162 | #define P1FLEN_SHIFT 3 | |
163 | #define DTYP_SHIFT 10 | |
164 | #define ENDN_SHIFT 12 | |
165 | #define DDLY_SHIFT 13 | |
166 | #define FSIG_SHIFT 15 | |
167 | #define P2ELEN_SHIFT 16 | |
168 | #define P2FLEN_SHIFT 19 | |
169 | #define P2SM_SHIFT 26 | |
170 | #define P2EN_SHIFT 27 | |
171 | #define FSYNC_SHIFT 15 | |
172 | ||
173 | #define P1ELEN_MASK 0x00000007 | |
174 | #define P2ELEN_MASK 0x00070000 | |
175 | #define P1FLEN_MASK 0x00000378 | |
176 | #define P2FLEN_MASK 0x03780000 | |
177 | #define DDLY_MASK 0x00003000 | |
178 | #define DTYP_MASK 0x00000600 | |
179 | #define P2SM_MASK 0x04000000 | |
180 | #define P2EN_MASK 0x08000000 | |
181 | #define ENDN_MASK 0x00001000 | |
182 | #define TFSPOL_MASK 0x00000400 | |
183 | #define TBSWAP_MASK 0x30000000 | |
184 | #define COMPANDING_MODE_MASK 0x00000c00 | |
185 | #define FSYNC_MASK 0x00008000 | |
186 | ||
187 | #define MSP_P1_ELEM_LEN_BITS(n) (n & P1ELEN_MASK) | |
188 | #define MSP_P2_ELEM_LEN_BITS(n) (((n) << P2ELEN_SHIFT) & P2ELEN_MASK) | |
189 | #define MSP_P1_FRAME_LEN_BITS(n) (((n) << P1FLEN_SHIFT) & P1FLEN_MASK) | |
190 | #define MSP_P2_FRAME_LEN_BITS(n) (((n) << P2FLEN_SHIFT) & P2FLEN_MASK) | |
191 | #define MSP_DATA_DELAY_BITS(n) (((n) << DDLY_SHIFT) & DDLY_MASK) | |
192 | #define MSP_DATA_TYPE_BITS(n) (((n) << DTYP_SHIFT) & DTYP_MASK) | |
193 | #define MSP_P2_START_MODE_BIT(n) ((n << P2SM_SHIFT) & P2SM_MASK) | |
194 | #define MSP_P2_ENABLE_BIT(n) ((n << P2EN_SHIFT) & P2EN_MASK) | |
195 | #define MSP_SET_ENDIANNES_BIT(n) ((n << ENDN_SHIFT) & ENDN_MASK) | |
196 | #define MSP_FSYNC_POL(n) ((n << TFSPOL_SHIFT) & TFSPOL_MASK) | |
197 | #define MSP_DATA_WORD_SWAP(n) ((n << TBSWAP_SHIFT) & TBSWAP_MASK) | |
198 | #define MSP_SET_COMPANDING_MODE(n) ((n << DTYP_SHIFT) & \ | |
199 | COMPANDING_MODE_MASK) | |
200 | #define MSP_SET_FSYNC_IGNORE(n) ((n << FSYNC_SHIFT) & FSYNC_MASK) | |
201 | ||
202 | /* Flag register */ | |
203 | #define RX_BUSY BIT(0) | |
204 | #define RX_FIFO_EMPTY BIT(1) | |
205 | #define RX_FIFO_FULL BIT(2) | |
206 | #define TX_BUSY BIT(3) | |
207 | #define TX_FIFO_EMPTY BIT(4) | |
208 | #define TX_FIFO_FULL BIT(5) | |
209 | ||
210 | #define RBUSY_SHIFT 0 | |
211 | #define RFE_SHIFT 1 | |
212 | #define RFU_SHIFT 2 | |
213 | #define TBUSY_SHIFT 3 | |
214 | #define TFE_SHIFT 4 | |
215 | #define TFU_SHIFT 5 | |
216 | ||
217 | /* Multichannel control register */ | |
218 | #define RMCEN_SHIFT 0 | |
219 | #define RMCSF_SHIFT 1 | |
220 | #define RCMPM_SHIFT 3 | |
221 | #define TMCEN_SHIFT 5 | |
222 | #define TNCSF_SHIFT 6 | |
223 | ||
224 | /* Sample rate generator register */ | |
225 | #define SCKDIV_SHIFT 0 | |
226 | #define FRWID_SHIFT 10 | |
227 | #define FRPER_SHIFT 16 | |
228 | ||
229 | #define SCK_DIV_MASK 0x0000003FF | |
230 | #define FRAME_WIDTH_BITS(n) (((n) << FRWID_SHIFT) & 0x0000FC00) | |
231 | #define FRAME_PERIOD_BITS(n) (((n) << FRPER_SHIFT) & 0x1FFF0000) | |
232 | ||
233 | /* DMA controller register */ | |
234 | #define RX_DMA_ENABLE BIT(0) | |
235 | #define TX_DMA_ENABLE BIT(1) | |
236 | ||
237 | #define RDMAE_SHIFT 0 | |
238 | #define TDMAE_SHIFT 1 | |
239 | ||
240 | /* Interrupt Register */ | |
241 | #define RX_SERVICE_INT BIT(0) | |
242 | #define RX_OVERRUN_ERROR_INT BIT(1) | |
243 | #define RX_FSYNC_ERR_INT BIT(2) | |
244 | #define RX_FSYNC_INT BIT(3) | |
245 | #define TX_SERVICE_INT BIT(4) | |
246 | #define TX_UNDERRUN_ERR_INT BIT(5) | |
247 | #define TX_FSYNC_ERR_INT BIT(6) | |
248 | #define TX_FSYNC_INT BIT(7) | |
249 | #define ALL_INT 0x000000ff | |
250 | ||
251 | /* MSP test control register */ | |
252 | #define MSP_ITCR_ITEN BIT(0) | |
253 | #define MSP_ITCR_TESTFIFO BIT(1) | |
254 | ||
255 | #define RMCEN_BIT 0 | |
256 | #define RMCSF_BIT 1 | |
257 | #define RCMPM_BIT 3 | |
258 | #define TMCEN_BIT 5 | |
259 | #define TNCSF_BIT 6 | |
260 | ||
261 | /* Single or dual phase mode */ | |
262 | enum msp_phase_mode { | |
263 | MSP_SINGLE_PHASE, | |
264 | MSP_DUAL_PHASE | |
265 | }; | |
266 | ||
267 | /* Frame length */ | |
268 | enum msp_frame_length { | |
269 | MSP_FRAME_LEN_1 = 0, | |
270 | MSP_FRAME_LEN_2 = 1, | |
271 | MSP_FRAME_LEN_4 = 3, | |
272 | MSP_FRAME_LEN_8 = 7, | |
273 | MSP_FRAME_LEN_12 = 11, | |
274 | MSP_FRAME_LEN_16 = 15, | |
275 | MSP_FRAME_LEN_20 = 19, | |
276 | MSP_FRAME_LEN_32 = 31, | |
277 | MSP_FRAME_LEN_48 = 47, | |
278 | MSP_FRAME_LEN_64 = 63 | |
279 | }; | |
280 | ||
281 | /* Element length */ | |
282 | enum msp_elem_length { | |
283 | MSP_ELEM_LEN_8 = 0, | |
284 | MSP_ELEM_LEN_10 = 1, | |
285 | MSP_ELEM_LEN_12 = 2, | |
286 | MSP_ELEM_LEN_14 = 3, | |
287 | MSP_ELEM_LEN_16 = 4, | |
288 | MSP_ELEM_LEN_20 = 5, | |
289 | MSP_ELEM_LEN_24 = 6, | |
290 | MSP_ELEM_LEN_32 = 7 | |
291 | }; | |
292 | ||
293 | enum msp_data_xfer_width { | |
294 | MSP_DATA_TRANSFER_WIDTH_BYTE, | |
295 | MSP_DATA_TRANSFER_WIDTH_HALFWORD, | |
296 | MSP_DATA_TRANSFER_WIDTH_WORD | |
297 | }; | |
298 | ||
299 | enum msp_frame_sync { | |
300 | MSP_FSYNC_UNIGNORE = 0, | |
301 | MSP_FSYNC_IGNORE = 1, | |
302 | }; | |
303 | ||
304 | enum msp_phase2_start_mode { | |
305 | MSP_PHASE2_START_MODE_IMEDIATE, | |
306 | MSP_PHASE2_START_MODE_FSYNC | |
307 | }; | |
308 | ||
309 | enum msp_btf { | |
310 | MSP_BTF_MS_BIT_FIRST = 0, | |
311 | MSP_BTF_LS_BIT_FIRST = 1 | |
312 | }; | |
313 | ||
314 | enum msp_fsync_pol { | |
315 | MSP_FSYNC_POL_ACT_HI = 0, | |
316 | MSP_FSYNC_POL_ACT_LO = 1 | |
317 | }; | |
318 | ||
319 | /* Data delay (in bit clock cycles) */ | |
320 | enum msp_delay { | |
321 | MSP_DELAY_0 = 0, | |
322 | MSP_DELAY_1 = 1, | |
323 | MSP_DELAY_2 = 2, | |
324 | MSP_DELAY_3 = 3 | |
325 | }; | |
326 | ||
327 | /* Configurations of clocks (transmit, receive or sample rate generator) */ | |
328 | enum msp_edge { | |
329 | MSP_FALLING_EDGE = 0, | |
330 | MSP_RISING_EDGE = 1, | |
331 | }; | |
332 | ||
333 | enum msp_hws { | |
334 | MSP_SWAP_NONE = 0, | |
335 | MSP_SWAP_BYTE_PER_WORD = 1, | |
336 | MSP_SWAP_BYTE_PER_HALF_WORD = 2, | |
337 | MSP_SWAP_HALF_WORD_PER_WORD = 3 | |
338 | }; | |
339 | ||
340 | enum msp_compress_mode { | |
341 | MSP_COMPRESS_MODE_LINEAR = 0, | |
342 | MSP_COMPRESS_MODE_MU_LAW = 2, | |
343 | MSP_COMPRESS_MODE_A_LAW = 3 | |
344 | }; | |
345 | ||
346 | enum msp_spi_burst_mode { | |
347 | MSP_SPI_BURST_MODE_DISABLE = 0, | |
348 | MSP_SPI_BURST_MODE_ENABLE = 1 | |
349 | }; | |
350 | ||
351 | enum msp_expand_mode { | |
352 | MSP_EXPAND_MODE_LINEAR = 0, | |
353 | MSP_EXPAND_MODE_LINEAR_SIGNED = 1, | |
354 | MSP_EXPAND_MODE_MU_LAW = 2, | |
355 | MSP_EXPAND_MODE_A_LAW = 3 | |
356 | }; | |
357 | ||
358 | #define MSP_FRAME_PERIOD_IN_MONO_MODE 256 | |
359 | #define MSP_FRAME_PERIOD_IN_STEREO_MODE 32 | |
360 | #define MSP_FRAME_WIDTH_IN_STEREO_MODE 16 | |
361 | ||
362 | enum msp_protocol { | |
363 | MSP_I2S_PROTOCOL, | |
364 | MSP_PCM_PROTOCOL, | |
365 | MSP_PCM_COMPAND_PROTOCOL, | |
366 | MSP_INVALID_PROTOCOL | |
367 | }; | |
368 | ||
369 | /* | |
370 | * No of registers to backup during | |
371 | * suspend resume | |
372 | */ | |
373 | #define MAX_MSP_BACKUP_REGS 36 | |
374 | ||
375 | enum enum_i2s_controller { | |
376 | MSP_0_I2S_CONTROLLER = 0, | |
377 | MSP_1_I2S_CONTROLLER, | |
378 | MSP_2_I2S_CONTROLLER, | |
379 | MSP_3_I2S_CONTROLLER, | |
380 | }; | |
381 | ||
382 | enum i2s_direction_t { | |
383 | MSP_DIR_TX = 0x01, | |
384 | MSP_DIR_RX = 0x02, | |
385 | }; | |
386 | ||
387 | enum msp_data_size { | |
388 | MSP_DATA_BITS_DEFAULT = -1, | |
389 | MSP_DATA_BITS_8 = 0x00, | |
390 | MSP_DATA_BITS_10, | |
391 | MSP_DATA_BITS_12, | |
392 | MSP_DATA_BITS_14, | |
393 | MSP_DATA_BITS_16, | |
394 | MSP_DATA_BITS_20, | |
395 | MSP_DATA_BITS_24, | |
396 | MSP_DATA_BITS_32, | |
397 | }; | |
398 | ||
399 | enum msp_state { | |
400 | MSP_STATE_IDLE = 0, | |
401 | MSP_STATE_CONFIGURED = 1, | |
402 | MSP_STATE_RUNNING = 2, | |
403 | }; | |
404 | ||
405 | enum msp_rx_comparison_enable_mode { | |
406 | MSP_COMPARISON_DISABLED = 0, | |
407 | MSP_COMPARISON_NONEQUAL_ENABLED = 2, | |
408 | MSP_COMPARISON_EQUAL_ENABLED = 3 | |
409 | }; | |
410 | ||
411 | struct msp_multichannel_config { | |
412 | bool rx_multichannel_enable; | |
413 | bool tx_multichannel_enable; | |
414 | enum msp_rx_comparison_enable_mode rx_comparison_enable_mode; | |
415 | u8 padding; | |
416 | u32 comparison_value; | |
417 | u32 comparison_mask; | |
418 | u32 rx_channel_0_enable; | |
419 | u32 rx_channel_1_enable; | |
420 | u32 rx_channel_2_enable; | |
421 | u32 rx_channel_3_enable; | |
422 | u32 tx_channel_0_enable; | |
423 | u32 tx_channel_1_enable; | |
424 | u32 tx_channel_2_enable; | |
425 | u32 tx_channel_3_enable; | |
426 | }; | |
427 | ||
428 | struct msp_protdesc { | |
429 | u32 rx_phase_mode; | |
430 | u32 tx_phase_mode; | |
431 | u32 rx_phase2_start_mode; | |
432 | u32 tx_phase2_start_mode; | |
433 | u32 rx_byte_order; | |
434 | u32 tx_byte_order; | |
435 | u32 rx_frame_len_1; | |
436 | u32 rx_frame_len_2; | |
437 | u32 tx_frame_len_1; | |
438 | u32 tx_frame_len_2; | |
439 | u32 rx_elem_len_1; | |
440 | u32 rx_elem_len_2; | |
441 | u32 tx_elem_len_1; | |
442 | u32 tx_elem_len_2; | |
443 | u32 rx_data_delay; | |
444 | u32 tx_data_delay; | |
445 | u32 rx_clk_pol; | |
446 | u32 tx_clk_pol; | |
447 | u32 rx_fsync_pol; | |
448 | u32 tx_fsync_pol; | |
449 | u32 rx_half_word_swap; | |
450 | u32 tx_half_word_swap; | |
451 | u32 compression_mode; | |
452 | u32 expansion_mode; | |
453 | u32 frame_sync_ignore; | |
454 | u32 frame_period; | |
455 | u32 frame_width; | |
456 | u32 clocks_per_frame; | |
457 | }; | |
458 | ||
459 | struct i2s_message { | |
460 | enum i2s_direction_t i2s_direction; | |
461 | void *txdata; | |
462 | void *rxdata; | |
463 | size_t txbytes; | |
464 | size_t rxbytes; | |
465 | int dma_flag; | |
466 | int tx_offset; | |
467 | int rx_offset; | |
468 | bool cyclic_dma; | |
469 | dma_addr_t buf_addr; | |
470 | size_t buf_len; | |
471 | size_t period_len; | |
472 | }; | |
473 | ||
474 | struct i2s_controller { | |
475 | struct module *owner; | |
476 | unsigned int id; | |
477 | unsigned int class; | |
478 | const struct i2s_algorithm *algo; /* the algorithm to access the bus */ | |
479 | void *data; | |
480 | struct mutex bus_lock; | |
481 | struct device dev; /* the controller device */ | |
482 | char name[48]; | |
483 | }; | |
484 | ||
485 | struct ux500_msp_config { | |
486 | unsigned int f_inputclk; | |
487 | unsigned int rx_clk_sel; | |
488 | unsigned int tx_clk_sel; | |
489 | unsigned int srg_clk_sel; | |
490 | unsigned int rx_fsync_pol; | |
491 | unsigned int tx_fsync_pol; | |
492 | unsigned int rx_fsync_sel; | |
493 | unsigned int tx_fsync_sel; | |
494 | unsigned int rx_fifo_config; | |
495 | unsigned int tx_fifo_config; | |
496 | unsigned int spi_clk_mode; | |
497 | unsigned int spi_burst_mode; | |
498 | unsigned int loopback_enable; | |
499 | unsigned int tx_data_enable; | |
500 | unsigned int default_protdesc; | |
501 | struct msp_protdesc protdesc; | |
502 | int multichannel_configured; | |
503 | struct msp_multichannel_config multichannel_config; | |
504 | unsigned int direction; | |
505 | unsigned int protocol; | |
506 | unsigned int frame_freq; | |
507 | unsigned int frame_size; | |
508 | enum msp_data_size data_size; | |
509 | unsigned int def_elem_len; | |
510 | unsigned int iodelay; | |
511 | void (*handler) (void *data); | |
512 | void *tx_callback_data; | |
513 | void *rx_callback_data; | |
514 | }; | |
515 | ||
516 | struct ux500_msp { | |
517 | enum enum_i2s_controller id; | |
518 | void __iomem *registers; | |
519 | struct device *dev; | |
520 | struct i2s_controller *i2s_cont; | |
521 | struct stedma40_chan_cfg *dma_cfg_rx; | |
522 | struct stedma40_chan_cfg *dma_cfg_tx; | |
523 | struct dma_chan *tx_pipeid; | |
524 | struct dma_chan *rx_pipeid; | |
525 | enum msp_state msp_state; | |
526 | int (*transfer) (struct ux500_msp *msp, struct i2s_message *message); | |
527 | int (*plat_init) (void); | |
528 | int (*plat_exit) (void); | |
529 | struct timer_list notify_timer; | |
530 | int def_elem_len; | |
531 | unsigned int dir_busy; | |
532 | int loopback_enable; | |
533 | u32 backup_regs[MAX_MSP_BACKUP_REGS]; | |
534 | unsigned int f_bitclk; | |
535 | }; | |
536 | ||
537 | struct ux500_msp_dma_params { | |
538 | unsigned int data_size; | |
539 | struct stedma40_chan_cfg *dma_cfg; | |
540 | }; | |
541 | ||
542 | int ux500_msp_i2s_init_msp(struct platform_device *pdev, | |
543 | struct ux500_msp **msp_p, | |
544 | struct msp_i2s_platform_data *platform_data); | |
545 | void ux500_msp_i2s_cleanup_msp(struct platform_device *pdev, | |
546 | struct ux500_msp *msp); | |
547 | int ux500_msp_i2s_open(struct ux500_msp *msp, struct ux500_msp_config *config); | |
548 | int ux500_msp_i2s_close(struct ux500_msp *msp, | |
549 | unsigned int dir); | |
550 | int ux500_msp_i2s_trigger(struct ux500_msp *msp, int cmd, | |
551 | int direction); | |
552 | ||
553 | #endif |