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5dab11d8 JA |
1 | /* |
2 | * intel_hdmi_audio.c - Intel HDMI audio driver | |
3 | * | |
4 | * Copyright (C) 2016 Intel Corp | |
5 | * Authors: Sailaja Bandarupalli <sailaja.bandarupalli@intel.com> | |
6 | * Ramesh Babu K V <ramesh.babu@intel.com> | |
7 | * Vaibhav Agarwal <vaibhav.agarwal@intel.com> | |
8 | * Jerome Anand <jerome.anand@intel.com> | |
9 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; version 2 of the License. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, but | |
16 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
18 | * General Public License for more details. | |
19 | * | |
20 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
21 | * ALSA driver for Intel HDMI audio | |
22 | */ | |
23 | ||
03c34377 | 24 | #include <linux/types.h> |
5dab11d8 JA |
25 | #include <linux/platform_device.h> |
26 | #include <linux/io.h> | |
27 | #include <linux/slab.h> | |
28 | #include <linux/module.h> | |
da864809 | 29 | #include <linux/interrupt.h> |
03c34377 | 30 | #include <linux/pm_runtime.h> |
412bbe7d | 31 | #include <linux/dma-mapping.h> |
5dab11d8 | 32 | #include <asm/cacheflush.h> |
5dab11d8 | 33 | #include <sound/core.h> |
03c34377 TI |
34 | #include <sound/asoundef.h> |
35 | #include <sound/pcm.h> | |
5dab11d8 JA |
36 | #include <sound/pcm_params.h> |
37 | #include <sound/initval.h> | |
38 | #include <sound/control.h> | |
03c34377 | 39 | #include <drm/drm_edid.h> |
da864809 | 40 | #include <drm/intel_lpe_audio.h> |
5dab11d8 JA |
41 | #include "intel_hdmi_audio.h" |
42 | ||
5dab11d8 JA |
43 | /*standard module options for ALSA. This module supports only one card*/ |
44 | static int hdmi_card_index = SNDRV_DEFAULT_IDX1; | |
45 | static char *hdmi_card_id = SNDRV_DEFAULT_STR1; | |
5dab11d8 JA |
46 | |
47 | module_param_named(index, hdmi_card_index, int, 0444); | |
48 | MODULE_PARM_DESC(index, | |
49 | "Index value for INTEL Intel HDMI Audio controller."); | |
50 | module_param_named(id, hdmi_card_id, charp, 0444); | |
51 | MODULE_PARM_DESC(id, | |
52 | "ID string for INTEL Intel HDMI Audio controller."); | |
53 | ||
54 | /* | |
55 | * ELD SA bits in the CEA Speaker Allocation data block | |
56 | */ | |
4a5ddb2c | 57 | static const int eld_speaker_allocation_bits[] = { |
5dab11d8 JA |
58 | [0] = FL | FR, |
59 | [1] = LFE, | |
60 | [2] = FC, | |
61 | [3] = RL | RR, | |
62 | [4] = RC, | |
63 | [5] = FLC | FRC, | |
64 | [6] = RLC | RRC, | |
65 | /* the following are not defined in ELD yet */ | |
66 | [7] = 0, | |
67 | }; | |
68 | ||
69 | /* | |
70 | * This is an ordered list! | |
71 | * | |
72 | * The preceding ones have better chances to be selected by | |
73 | * hdmi_channel_allocation(). | |
74 | */ | |
75 | static struct cea_channel_speaker_allocation channel_allocations[] = { | |
76 | /* channel: 7 6 5 4 3 2 1 0 */ | |
77 | { .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } }, | |
78 | /* 2.1 */ | |
79 | { .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } }, | |
80 | /* Dolby Surround */ | |
81 | { .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } }, | |
82 | /* surround40 */ | |
83 | { .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } }, | |
84 | /* surround41 */ | |
85 | { .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } }, | |
86 | /* surround50 */ | |
87 | { .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } }, | |
88 | /* surround51 */ | |
89 | { .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } }, | |
90 | /* 6.1 */ | |
91 | { .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } }, | |
92 | /* surround71 */ | |
93 | { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } }, | |
94 | ||
95 | { .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } }, | |
96 | { .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } }, | |
97 | { .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } }, | |
98 | { .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } }, | |
99 | { .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } }, | |
100 | { .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } }, | |
101 | { .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } }, | |
102 | { .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } }, | |
103 | { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } }, | |
104 | { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } }, | |
105 | { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } }, | |
106 | { .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } }, | |
107 | { .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } }, | |
108 | { .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } }, | |
109 | { .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } }, | |
110 | { .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } }, | |
111 | { .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } }, | |
112 | { .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } }, | |
113 | { .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } }, | |
114 | { .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } }, | |
115 | { .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } }, | |
116 | { .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } }, | |
117 | { .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } }, | |
118 | }; | |
119 | ||
4a5ddb2c | 120 | static const struct channel_map_table map_tables[] = { |
5dab11d8 JA |
121 | { SNDRV_CHMAP_FL, 0x00, FL }, |
122 | { SNDRV_CHMAP_FR, 0x01, FR }, | |
123 | { SNDRV_CHMAP_RL, 0x04, RL }, | |
124 | { SNDRV_CHMAP_RR, 0x05, RR }, | |
125 | { SNDRV_CHMAP_LFE, 0x02, LFE }, | |
126 | { SNDRV_CHMAP_FC, 0x03, FC }, | |
127 | { SNDRV_CHMAP_RLC, 0x06, RLC }, | |
128 | { SNDRV_CHMAP_RRC, 0x07, RRC }, | |
129 | {} /* terminator */ | |
130 | }; | |
131 | ||
132 | /* hardware capability structure */ | |
b556290f | 133 | static const struct snd_pcm_hardware had_pcm_hardware = { |
5dab11d8 | 134 | .info = (SNDRV_PCM_INFO_INTERLEAVED | |
a9ebdd0e TI |
135 | SNDRV_PCM_INFO_MMAP | |
136 | SNDRV_PCM_INFO_MMAP_VALID), | |
3e21a76c | 137 | .formats = SNDRV_PCM_FMTBIT_S24, |
5dab11d8 JA |
138 | .rates = SNDRV_PCM_RATE_32000 | |
139 | SNDRV_PCM_RATE_44100 | | |
140 | SNDRV_PCM_RATE_48000 | | |
141 | SNDRV_PCM_RATE_88200 | | |
142 | SNDRV_PCM_RATE_96000 | | |
143 | SNDRV_PCM_RATE_176400 | | |
144 | SNDRV_PCM_RATE_192000, | |
145 | .rate_min = HAD_MIN_RATE, | |
146 | .rate_max = HAD_MAX_RATE, | |
147 | .channels_min = HAD_MIN_CHANNEL, | |
148 | .channels_max = HAD_MAX_CHANNEL, | |
149 | .buffer_bytes_max = HAD_MAX_BUFFER, | |
150 | .period_bytes_min = HAD_MIN_PERIOD_BYTES, | |
151 | .period_bytes_max = HAD_MAX_PERIOD_BYTES, | |
152 | .periods_min = HAD_MIN_PERIODS, | |
153 | .periods_max = HAD_MAX_PERIODS, | |
154 | .fifo_size = HAD_FIFO_SIZE, | |
155 | }; | |
156 | ||
313d9f28 TI |
157 | /* Get the active PCM substream; |
158 | * Call had_substream_put() for unreferecing. | |
159 | * Don't call this inside had_spinlock, as it takes by itself | |
160 | */ | |
161 | static struct snd_pcm_substream * | |
162 | had_substream_get(struct snd_intelhad *intelhaddata) | |
163 | { | |
164 | struct snd_pcm_substream *substream; | |
165 | unsigned long flags; | |
166 | ||
167 | spin_lock_irqsave(&intelhaddata->had_spinlock, flags); | |
168 | substream = intelhaddata->stream_info.substream; | |
169 | if (substream) | |
170 | intelhaddata->stream_info.substream_refcount++; | |
171 | spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags); | |
172 | return substream; | |
173 | } | |
174 | ||
175 | /* Unref the active PCM substream; | |
176 | * Don't call this inside had_spinlock, as it takes by itself | |
177 | */ | |
178 | static void had_substream_put(struct snd_intelhad *intelhaddata) | |
179 | { | |
180 | unsigned long flags; | |
181 | ||
182 | spin_lock_irqsave(&intelhaddata->had_spinlock, flags); | |
183 | intelhaddata->stream_info.substream_refcount--; | |
184 | spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags); | |
185 | } | |
186 | ||
5dab11d8 | 187 | /* Register access functions */ |
83af57dd | 188 | static void had_read_register(struct snd_intelhad *ctx, u32 reg, u32 *val) |
5dab11d8 | 189 | { |
da864809 | 190 | *val = ioread32(ctx->mmio_start + ctx->had_config_offset + reg); |
5dab11d8 JA |
191 | } |
192 | ||
83af57dd | 193 | static void had_write_register(struct snd_intelhad *ctx, u32 reg, u32 val) |
5dab11d8 | 194 | { |
da864809 | 195 | iowrite32(val, ctx->mmio_start + ctx->had_config_offset + reg); |
5dab11d8 JA |
196 | } |
197 | ||
da864809 | 198 | /* |
313d9f28 TI |
199 | * enable / disable audio configuration |
200 | * | |
83af57dd | 201 | * The normal read/modify should not directly be used on VLV2 for |
da864809 | 202 | * updating AUD_CONFIG register. |
5dab11d8 JA |
203 | * This is because: |
204 | * Bit6 of AUD_CONFIG register is writeonly due to a silicon bug on VLV2 | |
205 | * HDMI IP. As a result a read-modify of AUD_CONFIG regiter will always | |
206 | * clear bit6. AUD_CONFIG[6:4] represents the "channels" field of the | |
207 | * register. This field should be 1xy binary for configuration with 6 or | |
208 | * more channels. Read-modify of AUD_CONFIG (Eg. for enabling audio) | |
209 | * causes the "channels" field to be updated as 0xy binary resulting in | |
210 | * bad audio. The fix is to always write the AUD_CONFIG[6:4] with | |
211 | * appropriate value when doing read-modify of AUD_CONFIG register. | |
5dab11d8 | 212 | */ |
40ce4b5d | 213 | static void had_enable_audio(struct snd_intelhad *intelhaddata, |
b556290f | 214 | bool enable) |
5dab11d8 | 215 | { |
40ce4b5d TI |
216 | /* update the cached value */ |
217 | intelhaddata->aud_config.regx.aud_en = enable; | |
218 | had_write_register(intelhaddata, AUD_CONFIG, | |
219 | intelhaddata->aud_config.regval); | |
5dab11d8 JA |
220 | } |
221 | ||
075a1d46 TI |
222 | /* forcibly ACKs to both BUFFER_DONE and BUFFER_UNDERRUN interrupts */ |
223 | static void had_ack_irqs(struct snd_intelhad *ctx) | |
da864809 TI |
224 | { |
225 | u32 status_reg; | |
226 | ||
075a1d46 TI |
227 | had_read_register(ctx, AUD_HDMI_STATUS, &status_reg); |
228 | status_reg |= HDMI_AUDIO_BUFFER_DONE | HDMI_AUDIO_UNDERRUN; | |
229 | had_write_register(ctx, AUD_HDMI_STATUS, status_reg); | |
230 | had_read_register(ctx, AUD_HDMI_STATUS, &status_reg); | |
da864809 TI |
231 | } |
232 | ||
f4566aa1 TI |
233 | /* Reset buffer pointers */ |
234 | static void had_reset_audio(struct snd_intelhad *intelhaddata) | |
5dab11d8 | 235 | { |
77531bee TI |
236 | had_write_register(intelhaddata, AUD_HDMI_STATUS, |
237 | AUD_HDMI_STATUSG_MASK_FUNCRST); | |
f4566aa1 | 238 | had_write_register(intelhaddata, AUD_HDMI_STATUS, 0); |
5dab11d8 JA |
239 | } |
240 | ||
2e52f5e5 | 241 | /* |
5dab11d8 JA |
242 | * initialize audio channel status registers |
243 | * This function is called in the prepare callback | |
244 | */ | |
245 | static int had_prog_status_reg(struct snd_pcm_substream *substream, | |
246 | struct snd_intelhad *intelhaddata) | |
247 | { | |
7ceba75f TI |
248 | union aud_cfg cfg_val = {.regval = 0}; |
249 | union aud_ch_status_0 ch_stat0 = {.regval = 0}; | |
250 | union aud_ch_status_1 ch_stat1 = {.regval = 0}; | |
5dab11d8 JA |
251 | int format; |
252 | ||
7ceba75f | 253 | ch_stat0.regx.lpcm_id = (intelhaddata->aes_bits & |
2e52f5e5 | 254 | IEC958_AES0_NONAUDIO) >> 1; |
7ceba75f | 255 | ch_stat0.regx.clk_acc = (intelhaddata->aes_bits & |
2e52f5e5 | 256 | IEC958_AES3_CON_CLOCK) >> 4; |
7ceba75f | 257 | cfg_val.regx.val_bit = ch_stat0.regx.lpcm_id; |
5dab11d8 JA |
258 | |
259 | switch (substream->runtime->rate) { | |
260 | case AUD_SAMPLE_RATE_32: | |
7ceba75f | 261 | ch_stat0.regx.samp_freq = CH_STATUS_MAP_32KHZ; |
5dab11d8 JA |
262 | break; |
263 | ||
264 | case AUD_SAMPLE_RATE_44_1: | |
7ceba75f | 265 | ch_stat0.regx.samp_freq = CH_STATUS_MAP_44KHZ; |
5dab11d8 JA |
266 | break; |
267 | case AUD_SAMPLE_RATE_48: | |
7ceba75f | 268 | ch_stat0.regx.samp_freq = CH_STATUS_MAP_48KHZ; |
5dab11d8 JA |
269 | break; |
270 | case AUD_SAMPLE_RATE_88_2: | |
7ceba75f | 271 | ch_stat0.regx.samp_freq = CH_STATUS_MAP_88KHZ; |
5dab11d8 JA |
272 | break; |
273 | case AUD_SAMPLE_RATE_96: | |
7ceba75f | 274 | ch_stat0.regx.samp_freq = CH_STATUS_MAP_96KHZ; |
5dab11d8 JA |
275 | break; |
276 | case AUD_SAMPLE_RATE_176_4: | |
7ceba75f | 277 | ch_stat0.regx.samp_freq = CH_STATUS_MAP_176KHZ; |
5dab11d8 JA |
278 | break; |
279 | case AUD_SAMPLE_RATE_192: | |
7ceba75f | 280 | ch_stat0.regx.samp_freq = CH_STATUS_MAP_192KHZ; |
5dab11d8 JA |
281 | break; |
282 | ||
283 | default: | |
284 | /* control should never come here */ | |
285 | return -EINVAL; | |
5dab11d8 | 286 | } |
2e52f5e5 | 287 | |
79dda75a | 288 | had_write_register(intelhaddata, |
7ceba75f | 289 | AUD_CH_STATUS_0, ch_stat0.regval); |
5dab11d8 JA |
290 | |
291 | format = substream->runtime->format; | |
292 | ||
293 | if (format == SNDRV_PCM_FORMAT_S16_LE) { | |
7ceba75f TI |
294 | ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_20; |
295 | ch_stat1.regx.wrd_len = SMPL_WIDTH_16BITS; | |
5dab11d8 | 296 | } else if (format == SNDRV_PCM_FORMAT_S24_LE) { |
7ceba75f TI |
297 | ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_24; |
298 | ch_stat1.regx.wrd_len = SMPL_WIDTH_24BITS; | |
5dab11d8 | 299 | } else { |
7ceba75f TI |
300 | ch_stat1.regx.max_wrd_len = 0; |
301 | ch_stat1.regx.wrd_len = 0; | |
5dab11d8 | 302 | } |
2e52f5e5 | 303 | |
79dda75a | 304 | had_write_register(intelhaddata, |
7ceba75f | 305 | AUD_CH_STATUS_1, ch_stat1.regval); |
5dab11d8 JA |
306 | return 0; |
307 | } | |
308 | ||
76296ef0 | 309 | /* |
5dab11d8 JA |
310 | * function to initialize audio |
311 | * registers and buffer confgiuration registers | |
312 | * This function is called in the prepare callback | |
313 | */ | |
b556290f TI |
314 | static int had_init_audio_ctrl(struct snd_pcm_substream *substream, |
315 | struct snd_intelhad *intelhaddata) | |
5dab11d8 | 316 | { |
7ceba75f TI |
317 | union aud_cfg cfg_val = {.regval = 0}; |
318 | union aud_buf_config buf_cfg = {.regval = 0}; | |
5dab11d8 JA |
319 | u8 channels; |
320 | ||
321 | had_prog_status_reg(substream, intelhaddata); | |
322 | ||
7ceba75f TI |
323 | buf_cfg.regx.audio_fifo_watermark = FIFO_THRESHOLD; |
324 | buf_cfg.regx.dma_fifo_watermark = DMA_FIFO_THRESHOLD; | |
325 | buf_cfg.regx.aud_delay = 0; | |
326 | had_write_register(intelhaddata, AUD_BUF_CONFIG, buf_cfg.regval); | |
5dab11d8 JA |
327 | |
328 | channels = substream->runtime->channels; | |
7ceba75f | 329 | cfg_val.regx.num_ch = channels - 2; |
5dab11d8 | 330 | if (channels <= 2) |
7ceba75f | 331 | cfg_val.regx.layout = LAYOUT0; |
5dab11d8 | 332 | else |
7ceba75f | 333 | cfg_val.regx.layout = LAYOUT1; |
5dab11d8 | 334 | |
7ceba75f | 335 | cfg_val.regx.val_bit = 1; |
83af57dd TI |
336 | |
337 | /* fix up the DP bits */ | |
338 | if (intelhaddata->dp_output) { | |
339 | cfg_val.regx.dp_modei = 1; | |
340 | cfg_val.regx.set = 1; | |
341 | } | |
342 | ||
7ceba75f | 343 | had_write_register(intelhaddata, AUD_CONFIG, cfg_val.regval); |
40ce4b5d | 344 | intelhaddata->aud_config = cfg_val; |
5dab11d8 JA |
345 | return 0; |
346 | } | |
347 | ||
5dab11d8 JA |
348 | /* |
349 | * Compute derived values in channel_allocations[]. | |
350 | */ | |
351 | static void init_channel_allocations(void) | |
352 | { | |
353 | int i, j; | |
354 | struct cea_channel_speaker_allocation *p; | |
355 | ||
5dab11d8 JA |
356 | for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { |
357 | p = channel_allocations + i; | |
358 | p->channels = 0; | |
359 | p->spk_mask = 0; | |
360 | for (j = 0; j < ARRAY_SIZE(p->speakers); j++) | |
361 | if (p->speakers[j]) { | |
362 | p->channels++; | |
363 | p->spk_mask |= p->speakers[j]; | |
364 | } | |
365 | } | |
366 | } | |
367 | ||
368 | /* | |
369 | * The transformation takes two steps: | |
370 | * | |
371 | * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask | |
372 | * spk_mask => (channel_allocations[]) => ai->CA | |
373 | * | |
374 | * TODO: it could select the wrong CA from multiple candidates. | |
375 | */ | |
b556290f TI |
376 | static int had_channel_allocation(struct snd_intelhad *intelhaddata, |
377 | int channels) | |
5dab11d8 JA |
378 | { |
379 | int i; | |
380 | int ca = 0; | |
381 | int spk_mask = 0; | |
382 | ||
383 | /* | |
384 | * CA defaults to 0 for basic stereo audio | |
385 | */ | |
386 | if (channels <= 2) | |
387 | return 0; | |
388 | ||
389 | /* | |
390 | * expand ELD's speaker allocation mask | |
391 | * | |
392 | * ELD tells the speaker mask in a compact(paired) form, | |
393 | * expand ELD's notions to match the ones used by Audio InfoFrame. | |
394 | */ | |
395 | ||
396 | for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) { | |
df0435db | 397 | if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i)) |
5dab11d8 JA |
398 | spk_mask |= eld_speaker_allocation_bits[i]; |
399 | } | |
400 | ||
401 | /* search for the first working match in the CA table */ | |
402 | for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { | |
403 | if (channels == channel_allocations[i].channels && | |
404 | (spk_mask & channel_allocations[i].spk_mask) == | |
405 | channel_allocations[i].spk_mask) { | |
406 | ca = channel_allocations[i].ca_index; | |
407 | break; | |
408 | } | |
409 | } | |
410 | ||
c75b0476 | 411 | dev_dbg(intelhaddata->dev, "select CA 0x%x for %d\n", ca, channels); |
5dab11d8 JA |
412 | |
413 | return ca; | |
414 | } | |
415 | ||
416 | /* from speaker bit mask to ALSA API channel position */ | |
417 | static int spk_to_chmap(int spk) | |
418 | { | |
4a5ddb2c | 419 | const struct channel_map_table *t = map_tables; |
5dab11d8 JA |
420 | |
421 | for (; t->map; t++) { | |
422 | if (t->spk_mask == spk) | |
423 | return t->map; | |
424 | } | |
425 | return 0; | |
426 | } | |
427 | ||
372d855f | 428 | static void had_build_channel_allocation_map(struct snd_intelhad *intelhaddata) |
5dab11d8 | 429 | { |
2e52f5e5 | 430 | int i, c; |
5dab11d8 JA |
431 | int spk_mask = 0; |
432 | struct snd_pcm_chmap_elem *chmap; | |
433 | u8 eld_high, eld_high_mask = 0xF0; | |
434 | u8 high_msb; | |
435 | ||
436 | chmap = kzalloc(sizeof(*chmap), GFP_KERNEL); | |
2e52f5e5 | 437 | if (!chmap) { |
5dab11d8 JA |
438 | intelhaddata->chmap->chmap = NULL; |
439 | return; | |
440 | } | |
441 | ||
df0435db TI |
442 | dev_dbg(intelhaddata->dev, "eld speaker = %x\n", |
443 | intelhaddata->eld[DRM_ELD_SPEAKER]); | |
5dab11d8 JA |
444 | |
445 | /* WA: Fix the max channel supported to 8 */ | |
446 | ||
447 | /* | |
448 | * Sink may support more than 8 channels, if eld_high has more than | |
449 | * one bit set. SOC supports max 8 channels. | |
450 | * Refer eld_speaker_allocation_bits, for sink speaker allocation | |
451 | */ | |
452 | ||
453 | /* if 0x2F < eld < 0x4F fall back to 0x2f, else fall back to 0x4F */ | |
df0435db | 454 | eld_high = intelhaddata->eld[DRM_ELD_SPEAKER] & eld_high_mask; |
5dab11d8 JA |
455 | if ((eld_high & (eld_high-1)) && (eld_high > 0x1F)) { |
456 | /* eld_high & (eld_high-1): if more than 1 bit set */ | |
457 | /* 0x1F: 7 channels */ | |
458 | for (i = 1; i < 4; i++) { | |
459 | high_msb = eld_high & (0x80 >> i); | |
460 | if (high_msb) { | |
df0435db | 461 | intelhaddata->eld[DRM_ELD_SPEAKER] &= |
5dab11d8 JA |
462 | high_msb | 0xF; |
463 | break; | |
464 | } | |
465 | } | |
466 | } | |
467 | ||
468 | for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) { | |
df0435db | 469 | if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i)) |
5dab11d8 JA |
470 | spk_mask |= eld_speaker_allocation_bits[i]; |
471 | } | |
472 | ||
473 | for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { | |
474 | if (spk_mask == channel_allocations[i].spk_mask) { | |
475 | for (c = 0; c < channel_allocations[i].channels; c++) { | |
476 | chmap->map[c] = spk_to_chmap( | |
477 | channel_allocations[i].speakers[ | |
2e52f5e5 | 478 | (MAX_SPEAKERS - 1) - c]); |
5dab11d8 JA |
479 | } |
480 | chmap->channels = channel_allocations[i].channels; | |
481 | intelhaddata->chmap->chmap = chmap; | |
482 | break; | |
483 | } | |
484 | } | |
485 | if (i >= ARRAY_SIZE(channel_allocations)) { | |
486 | intelhaddata->chmap->chmap = NULL; | |
487 | kfree(chmap); | |
488 | } | |
489 | } | |
490 | ||
491 | /* | |
492 | * ALSA API channel-map control callbacks | |
493 | */ | |
494 | static int had_chmap_ctl_info(struct snd_kcontrol *kcontrol, | |
495 | struct snd_ctl_elem_info *uinfo) | |
496 | { | |
497 | struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol); | |
498 | struct snd_intelhad *intelhaddata = info->private_data; | |
499 | ||
91b0cb0c | 500 | if (!intelhaddata->connected) |
5dab11d8 JA |
501 | return -ENODEV; |
502 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; | |
503 | uinfo->count = HAD_MAX_CHANNEL; | |
504 | uinfo->value.integer.min = 0; | |
505 | uinfo->value.integer.max = SNDRV_CHMAP_LAST; | |
506 | return 0; | |
507 | } | |
508 | ||
509 | static int had_chmap_ctl_get(struct snd_kcontrol *kcontrol, | |
510 | struct snd_ctl_elem_value *ucontrol) | |
511 | { | |
512 | struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol); | |
513 | struct snd_intelhad *intelhaddata = info->private_data; | |
2e52f5e5 | 514 | int i; |
5dab11d8 JA |
515 | const struct snd_pcm_chmap_elem *chmap; |
516 | ||
91b0cb0c | 517 | if (!intelhaddata->connected) |
5dab11d8 | 518 | return -ENODEV; |
8f8d1d7f TI |
519 | |
520 | mutex_lock(&intelhaddata->mutex); | |
521 | if (!intelhaddata->chmap->chmap) { | |
522 | mutex_unlock(&intelhaddata->mutex); | |
5dab11d8 | 523 | return -ENODATA; |
8f8d1d7f TI |
524 | } |
525 | ||
5dab11d8 | 526 | chmap = intelhaddata->chmap->chmap; |
c75b0476 | 527 | for (i = 0; i < chmap->channels; i++) |
5dab11d8 | 528 | ucontrol->value.integer.value[i] = chmap->map[i]; |
8f8d1d7f | 529 | mutex_unlock(&intelhaddata->mutex); |
5dab11d8 JA |
530 | |
531 | return 0; | |
532 | } | |
533 | ||
534 | static int had_register_chmap_ctls(struct snd_intelhad *intelhaddata, | |
535 | struct snd_pcm *pcm) | |
536 | { | |
2e52f5e5 | 537 | int err; |
5dab11d8 JA |
538 | |
539 | err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, | |
540 | NULL, 0, (unsigned long)intelhaddata, | |
541 | &intelhaddata->chmap); | |
542 | if (err < 0) | |
543 | return err; | |
544 | ||
545 | intelhaddata->chmap->private_data = intelhaddata; | |
e9d65abf TI |
546 | intelhaddata->chmap->kctl->info = had_chmap_ctl_info; |
547 | intelhaddata->chmap->kctl->get = had_chmap_ctl_get; | |
5dab11d8 JA |
548 | intelhaddata->chmap->chmap = NULL; |
549 | return 0; | |
550 | } | |
551 | ||
76296ef0 | 552 | /* |
44684f61 | 553 | * Initialize Data Island Packets registers |
5dab11d8 JA |
554 | * This function is called in the prepare callback |
555 | */ | |
b556290f TI |
556 | static void had_prog_dip(struct snd_pcm_substream *substream, |
557 | struct snd_intelhad *intelhaddata) | |
5dab11d8 JA |
558 | { |
559 | int i; | |
7ceba75f TI |
560 | union aud_ctrl_st ctrl_state = {.regval = 0}; |
561 | union aud_info_frame2 frame2 = {.regval = 0}; | |
562 | union aud_info_frame3 frame3 = {.regval = 0}; | |
5dab11d8 | 563 | u8 checksum = 0; |
964ca808 | 564 | u32 info_frame; |
5dab11d8 | 565 | int channels; |
36ed3466 | 566 | int ca; |
5dab11d8 JA |
567 | |
568 | channels = substream->runtime->channels; | |
569 | ||
7ceba75f | 570 | had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval); |
5dab11d8 | 571 | |
b556290f | 572 | ca = had_channel_allocation(intelhaddata, channels); |
964ca808 PLB |
573 | if (intelhaddata->dp_output) { |
574 | info_frame = DP_INFO_FRAME_WORD1; | |
36ed3466 | 575 | frame2.regval = (substream->runtime->channels - 1) | (ca << 24); |
964ca808 PLB |
576 | } else { |
577 | info_frame = HDMI_INFO_FRAME_WORD1; | |
7ceba75f | 578 | frame2.regx.chnl_cnt = substream->runtime->channels - 1; |
36ed3466 | 579 | frame3.regx.chnl_alloc = ca; |
5dab11d8 | 580 | |
2e52f5e5 | 581 | /* Calculte the byte wide checksum for all valid DIP words */ |
964ca808 | 582 | for (i = 0; i < BYTES_PER_WORD; i++) |
7ceba75f | 583 | checksum += (info_frame >> (i * 8)) & 0xff; |
964ca808 | 584 | for (i = 0; i < BYTES_PER_WORD; i++) |
7ceba75f | 585 | checksum += (frame2.regval >> (i * 8)) & 0xff; |
964ca808 | 586 | for (i = 0; i < BYTES_PER_WORD; i++) |
7ceba75f | 587 | checksum += (frame3.regval >> (i * 8)) & 0xff; |
5dab11d8 | 588 | |
7ceba75f | 589 | frame2.regx.chksum = -(checksum); |
964ca808 | 590 | } |
5dab11d8 | 591 | |
4151ee84 | 592 | had_write_register(intelhaddata, AUD_HDMIW_INFOFR, info_frame); |
7ceba75f TI |
593 | had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame2.regval); |
594 | had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame3.regval); | |
5dab11d8 JA |
595 | |
596 | /* program remaining DIP words with zero */ | |
597 | for (i = 0; i < HAD_MAX_DIP_WORDS-VALID_DIP_WORDS; i++) | |
4151ee84 | 598 | had_write_register(intelhaddata, AUD_HDMIW_INFOFR, 0x0); |
5dab11d8 | 599 | |
7ceba75f TI |
600 | ctrl_state.regx.dip_freq = 1; |
601 | ctrl_state.regx.dip_en_sta = 1; | |
602 | had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval); | |
5dab11d8 JA |
603 | } |
604 | ||
964ca808 PLB |
605 | static int had_calculate_maud_value(u32 aud_samp_freq, u32 link_rate) |
606 | { | |
607 | u32 maud_val; | |
608 | ||
2e52f5e5 | 609 | /* Select maud according to DP 1.2 spec */ |
964ca808 PLB |
610 | if (link_rate == DP_2_7_GHZ) { |
611 | switch (aud_samp_freq) { | |
612 | case AUD_SAMPLE_RATE_32: | |
613 | maud_val = AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL; | |
614 | break; | |
615 | ||
616 | case AUD_SAMPLE_RATE_44_1: | |
617 | maud_val = AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL; | |
618 | break; | |
619 | ||
620 | case AUD_SAMPLE_RATE_48: | |
621 | maud_val = AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL; | |
622 | break; | |
623 | ||
624 | case AUD_SAMPLE_RATE_88_2: | |
625 | maud_val = AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL; | |
626 | break; | |
627 | ||
628 | case AUD_SAMPLE_RATE_96: | |
629 | maud_val = AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL; | |
630 | break; | |
631 | ||
632 | case AUD_SAMPLE_RATE_176_4: | |
633 | maud_val = AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL; | |
634 | break; | |
635 | ||
636 | case HAD_MAX_RATE: | |
637 | maud_val = HAD_MAX_RATE_DP_2_7_MAUD_VAL; | |
638 | break; | |
639 | ||
640 | default: | |
641 | maud_val = -EINVAL; | |
642 | break; | |
643 | } | |
644 | } else if (link_rate == DP_1_62_GHZ) { | |
645 | switch (aud_samp_freq) { | |
646 | case AUD_SAMPLE_RATE_32: | |
647 | maud_val = AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL; | |
648 | break; | |
649 | ||
650 | case AUD_SAMPLE_RATE_44_1: | |
651 | maud_val = AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL; | |
652 | break; | |
653 | ||
654 | case AUD_SAMPLE_RATE_48: | |
655 | maud_val = AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL; | |
656 | break; | |
657 | ||
658 | case AUD_SAMPLE_RATE_88_2: | |
659 | maud_val = AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL; | |
660 | break; | |
661 | ||
662 | case AUD_SAMPLE_RATE_96: | |
663 | maud_val = AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL; | |
664 | break; | |
665 | ||
666 | case AUD_SAMPLE_RATE_176_4: | |
667 | maud_val = AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL; | |
668 | break; | |
669 | ||
670 | case HAD_MAX_RATE: | |
671 | maud_val = HAD_MAX_RATE_DP_1_62_MAUD_VAL; | |
672 | break; | |
673 | ||
674 | default: | |
675 | maud_val = -EINVAL; | |
676 | break; | |
677 | } | |
678 | } else | |
679 | maud_val = -EINVAL; | |
680 | ||
681 | return maud_val; | |
682 | } | |
683 | ||
76296ef0 | 684 | /* |
44684f61 | 685 | * Program HDMI audio CTS value |
5dab11d8 JA |
686 | * |
687 | * @aud_samp_freq: sampling frequency of audio data | |
688 | * @tmds: sampling frequency of the display data | |
b556290f | 689 | * @link_rate: DP link rate |
5dab11d8 | 690 | * @n_param: N value, depends on aud_samp_freq |
b556290f | 691 | * @intelhaddata: substream private data |
5dab11d8 JA |
692 | * |
693 | * Program CTS register based on the audio and display sampling frequency | |
694 | */ | |
b556290f TI |
695 | static void had_prog_cts(u32 aud_samp_freq, u32 tmds, u32 link_rate, |
696 | u32 n_param, struct snd_intelhad *intelhaddata) | |
5dab11d8 JA |
697 | { |
698 | u32 cts_val; | |
699 | u64 dividend, divisor; | |
700 | ||
964ca808 PLB |
701 | if (intelhaddata->dp_output) { |
702 | /* Substitute cts_val with Maud according to DP 1.2 spec*/ | |
703 | cts_val = had_calculate_maud_value(aud_samp_freq, link_rate); | |
704 | } else { | |
705 | /* Calculate CTS according to HDMI 1.3a spec*/ | |
706 | dividend = (u64)tmds * n_param*1000; | |
707 | divisor = 128 * aud_samp_freq; | |
708 | cts_val = div64_u64(dividend, divisor); | |
709 | } | |
c75b0476 | 710 | dev_dbg(intelhaddata->dev, "TMDS value=%d, N value=%d, CTS Value=%d\n", |
964ca808 | 711 | tmds, n_param, cts_val); |
79dda75a | 712 | had_write_register(intelhaddata, AUD_HDMI_CTS, (BIT(24) | cts_val)); |
5dab11d8 JA |
713 | } |
714 | ||
715 | static int had_calculate_n_value(u32 aud_samp_freq) | |
716 | { | |
2e52f5e5 | 717 | int n_val; |
5dab11d8 JA |
718 | |
719 | /* Select N according to HDMI 1.3a spec*/ | |
720 | switch (aud_samp_freq) { | |
721 | case AUD_SAMPLE_RATE_32: | |
722 | n_val = 4096; | |
2e52f5e5 | 723 | break; |
5dab11d8 JA |
724 | |
725 | case AUD_SAMPLE_RATE_44_1: | |
726 | n_val = 6272; | |
2e52f5e5 | 727 | break; |
5dab11d8 JA |
728 | |
729 | case AUD_SAMPLE_RATE_48: | |
730 | n_val = 6144; | |
2e52f5e5 | 731 | break; |
5dab11d8 JA |
732 | |
733 | case AUD_SAMPLE_RATE_88_2: | |
734 | n_val = 12544; | |
2e52f5e5 | 735 | break; |
5dab11d8 JA |
736 | |
737 | case AUD_SAMPLE_RATE_96: | |
738 | n_val = 12288; | |
2e52f5e5 | 739 | break; |
5dab11d8 JA |
740 | |
741 | case AUD_SAMPLE_RATE_176_4: | |
742 | n_val = 25088; | |
2e52f5e5 | 743 | break; |
5dab11d8 JA |
744 | |
745 | case HAD_MAX_RATE: | |
746 | n_val = 24576; | |
2e52f5e5 | 747 | break; |
5dab11d8 JA |
748 | |
749 | default: | |
750 | n_val = -EINVAL; | |
2e52f5e5 | 751 | break; |
5dab11d8 JA |
752 | } |
753 | return n_val; | |
754 | } | |
755 | ||
76296ef0 | 756 | /* |
44684f61 | 757 | * Program HDMI audio N value |
5dab11d8 JA |
758 | * |
759 | * @aud_samp_freq: sampling frequency of audio data | |
760 | * @n_param: N value, depends on aud_samp_freq | |
b556290f | 761 | * @intelhaddata: substream private data |
5dab11d8 JA |
762 | * |
763 | * This function is called in the prepare callback. | |
764 | * It programs based on the audio and display sampling frequency | |
765 | */ | |
b556290f TI |
766 | static int had_prog_n(u32 aud_samp_freq, u32 *n_param, |
767 | struct snd_intelhad *intelhaddata) | |
5dab11d8 | 768 | { |
2e52f5e5 | 769 | int n_val; |
5dab11d8 | 770 | |
964ca808 PLB |
771 | if (intelhaddata->dp_output) { |
772 | /* | |
773 | * According to DP specs, Maud and Naud values hold | |
774 | * a relationship, which is stated as: | |
775 | * Maud/Naud = 512 * fs / f_LS_Clk | |
776 | * where, fs is the sampling frequency of the audio stream | |
777 | * and Naud is 32768 for Async clock. | |
778 | */ | |
779 | ||
780 | n_val = DP_NAUD_VAL; | |
781 | } else | |
782 | n_val = had_calculate_n_value(aud_samp_freq); | |
5dab11d8 JA |
783 | |
784 | if (n_val < 0) | |
785 | return n_val; | |
786 | ||
79dda75a | 787 | had_write_register(intelhaddata, AUD_N_ENABLE, (BIT(24) | n_val)); |
5dab11d8 JA |
788 | *n_param = n_val; |
789 | return 0; | |
790 | } | |
791 | ||
e1b239f3 TI |
792 | /* |
793 | * PCM ring buffer handling | |
794 | * | |
795 | * The hardware provides a ring buffer with the fixed 4 buffer descriptors | |
796 | * (BDs). The driver maps these 4 BDs onto the PCM ring buffer. The mapping | |
797 | * moves at each period elapsed. The below illustrates how it works: | |
798 | * | |
799 | * At time=0 | |
800 | * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1| | |
801 | * BD | 0 | 1 | 2 | 3 | | |
802 | * | |
803 | * At time=1 (period elapsed) | |
804 | * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1| | |
805 | * BD | 1 | 2 | 3 | 0 | | |
806 | * | |
807 | * At time=2 (second period elapsed) | |
808 | * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1| | |
809 | * BD | 2 | 3 | 0 | 1 | | |
810 | * | |
811 | * The bd_head field points to the index of the BD to be read. It's also the | |
812 | * position to be filled at next. The pcm_head and the pcm_filled fields | |
813 | * point to the indices of the current position and of the next position to | |
814 | * be filled, respectively. For PCM buffer there are both _head and _filled | |
815 | * because they may be difference when nperiods > 4. For example, in the | |
816 | * example above at t=1, bd_head=1 and pcm_head=1 while pcm_filled=5: | |
817 | * | |
818 | * pcm_head (=1) --v v-- pcm_filled (=5) | |
819 | * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1| | |
820 | * BD | 1 | 2 | 3 | 0 | | |
821 | * bd_head (=1) --^ ^-- next to fill (= bd_head) | |
822 | * | |
823 | * For nperiods < 4, the remaining BDs out of 4 are marked as invalid, so that | |
824 | * the hardware skips those BDs in the loop. | |
825 | */ | |
826 | ||
827 | #define AUD_BUF_ADDR(x) (AUD_BUF_A_ADDR + (x) * HAD_REG_WIDTH) | |
828 | #define AUD_BUF_LEN(x) (AUD_BUF_A_LENGTH + (x) * HAD_REG_WIDTH) | |
829 | ||
830 | /* Set up a buffer descriptor at the "filled" position */ | |
831 | static void had_prog_bd(struct snd_pcm_substream *substream, | |
832 | struct snd_intelhad *intelhaddata) | |
833 | { | |
834 | int idx = intelhaddata->bd_head; | |
835 | int ofs = intelhaddata->pcmbuf_filled * intelhaddata->period_bytes; | |
836 | u32 addr = substream->runtime->dma_addr + ofs; | |
837 | ||
838 | addr |= AUD_BUF_VALID | AUD_BUF_INTR_EN; | |
839 | had_write_register(intelhaddata, AUD_BUF_ADDR(idx), addr); | |
840 | had_write_register(intelhaddata, AUD_BUF_LEN(idx), | |
841 | intelhaddata->period_bytes); | |
842 | ||
843 | /* advance the indices to the next */ | |
844 | intelhaddata->bd_head++; | |
845 | intelhaddata->bd_head %= intelhaddata->num_bds; | |
846 | intelhaddata->pcmbuf_filled++; | |
847 | intelhaddata->pcmbuf_filled %= substream->runtime->periods; | |
848 | } | |
849 | ||
850 | /* invalidate a buffer descriptor with the given index */ | |
851 | static void had_invalidate_bd(struct snd_intelhad *intelhaddata, | |
852 | int idx) | |
853 | { | |
854 | had_write_register(intelhaddata, AUD_BUF_ADDR(idx), 0); | |
855 | had_write_register(intelhaddata, AUD_BUF_LEN(idx), 0); | |
856 | } | |
857 | ||
858 | /* Initial programming of ring buffer */ | |
859 | static void had_init_ringbuf(struct snd_pcm_substream *substream, | |
860 | struct snd_intelhad *intelhaddata) | |
861 | { | |
862 | struct snd_pcm_runtime *runtime = substream->runtime; | |
863 | int i, num_periods; | |
864 | ||
865 | num_periods = runtime->periods; | |
866 | intelhaddata->num_bds = min(num_periods, HAD_NUM_OF_RING_BUFS); | |
867 | intelhaddata->period_bytes = | |
868 | frames_to_bytes(runtime, runtime->period_size); | |
869 | WARN_ON(intelhaddata->period_bytes & 0x3f); | |
870 | ||
871 | intelhaddata->bd_head = 0; | |
872 | intelhaddata->pcmbuf_head = 0; | |
873 | intelhaddata->pcmbuf_filled = 0; | |
874 | ||
875 | for (i = 0; i < HAD_NUM_OF_RING_BUFS; i++) { | |
876 | if (i < num_periods) | |
877 | had_prog_bd(substream, intelhaddata); | |
878 | else /* invalidate the rest */ | |
879 | had_invalidate_bd(intelhaddata, i); | |
880 | } | |
881 | ||
882 | intelhaddata->bd_head = 0; /* reset at head again before starting */ | |
883 | } | |
884 | ||
885 | /* process a bd, advance to the next */ | |
886 | static void had_advance_ringbuf(struct snd_pcm_substream *substream, | |
887 | struct snd_intelhad *intelhaddata) | |
888 | { | |
889 | int num_periods = substream->runtime->periods; | |
890 | ||
891 | /* reprogram the next buffer */ | |
892 | had_prog_bd(substream, intelhaddata); | |
893 | ||
894 | /* proceed to next */ | |
895 | intelhaddata->pcmbuf_head++; | |
896 | intelhaddata->pcmbuf_head %= num_periods; | |
897 | } | |
898 | ||
899 | /* process the current BD(s); | |
900 | * returns the current PCM buffer byte position, or -EPIPE for underrun. | |
901 | */ | |
902 | static int had_process_ringbuf(struct snd_pcm_substream *substream, | |
903 | struct snd_intelhad *intelhaddata) | |
904 | { | |
905 | int len, processed; | |
906 | unsigned long flags; | |
907 | ||
908 | processed = 0; | |
909 | spin_lock_irqsave(&intelhaddata->had_spinlock, flags); | |
910 | for (;;) { | |
911 | /* get the remaining bytes on the buffer */ | |
912 | had_read_register(intelhaddata, | |
913 | AUD_BUF_LEN(intelhaddata->bd_head), | |
914 | &len); | |
915 | if (len < 0 || len > intelhaddata->period_bytes) { | |
916 | dev_dbg(intelhaddata->dev, "Invalid buf length %d\n", | |
917 | len); | |
918 | len = -EPIPE; | |
919 | goto out; | |
920 | } | |
921 | ||
922 | if (len > 0) /* OK, this is the current buffer */ | |
923 | break; | |
924 | ||
925 | /* len=0 => already empty, check the next buffer */ | |
926 | if (++processed >= intelhaddata->num_bds) { | |
927 | len = -EPIPE; /* all empty? - report underrun */ | |
928 | goto out; | |
929 | } | |
930 | had_advance_ringbuf(substream, intelhaddata); | |
931 | } | |
932 | ||
933 | len = intelhaddata->period_bytes - len; | |
934 | len += intelhaddata->period_bytes * intelhaddata->pcmbuf_head; | |
935 | out: | |
936 | spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags); | |
937 | return len; | |
938 | } | |
939 | ||
940 | /* called from irq handler */ | |
941 | static void had_process_buffer_done(struct snd_intelhad *intelhaddata) | |
942 | { | |
943 | struct snd_pcm_substream *substream; | |
944 | ||
945 | if (!intelhaddata->connected) | |
946 | return; /* disconnected? - bail out */ | |
947 | ||
948 | substream = had_substream_get(intelhaddata); | |
949 | if (!substream) | |
950 | return; /* no stream? - bail out */ | |
951 | ||
952 | /* process or stop the stream */ | |
953 | if (had_process_ringbuf(substream, intelhaddata) < 0) | |
954 | snd_pcm_stop_xrun(substream); | |
955 | else | |
956 | snd_pcm_period_elapsed(substream); | |
957 | ||
958 | had_substream_put(intelhaddata); | |
959 | } | |
960 | ||
03c34377 TI |
961 | #define MAX_CNT 0xFF |
962 | ||
e1b239f3 TI |
963 | /* |
964 | * The interrupt status 'sticky' bits might not be cleared by | |
965 | * setting '1' to that bit once... | |
966 | */ | |
967 | static void wait_clear_underrun_bit(struct snd_intelhad *intelhaddata) | |
968 | { | |
969 | int i; | |
970 | u32 val; | |
971 | ||
972 | for (i = 0; i < MAX_CNT; i++) { | |
973 | /* clear bit30, 31 AUD_HDMI_STATUS */ | |
974 | had_read_register(intelhaddata, AUD_HDMI_STATUS, &val); | |
77531bee | 975 | if (!(val & AUD_HDMI_STATUS_MASK_UNDERRUN)) |
e1b239f3 TI |
976 | return; |
977 | had_write_register(intelhaddata, AUD_HDMI_STATUS, val); | |
978 | } | |
979 | dev_err(intelhaddata->dev, "Unable to clear UNDERRUN bits\n"); | |
980 | } | |
981 | ||
982 | /* called from irq handler */ | |
983 | static void had_process_buffer_underrun(struct snd_intelhad *intelhaddata) | |
5dab11d8 | 984 | { |
e1b239f3 | 985 | struct snd_pcm_substream *substream; |
5dab11d8 JA |
986 | |
987 | /* Handle Underrun interrupt within Audio Unit */ | |
79dda75a | 988 | had_write_register(intelhaddata, AUD_CONFIG, 0); |
40ce4b5d | 989 | intelhaddata->aud_config.regval = 0; |
5dab11d8 | 990 | /* Reset buffer pointers */ |
f4566aa1 | 991 | had_reset_audio(intelhaddata); |
e1b239f3 TI |
992 | |
993 | wait_clear_underrun_bit(intelhaddata); | |
994 | ||
995 | if (!intelhaddata->connected) | |
996 | return; /* disconnected? - bail out */ | |
997 | ||
998 | /* Report UNDERRUN error to above layers */ | |
999 | substream = had_substream_get(intelhaddata); | |
1000 | if (substream) { | |
1001 | snd_pcm_stop_xrun(substream); | |
1002 | had_substream_put(intelhaddata); | |
1003 | } | |
5dab11d8 JA |
1004 | } |
1005 | ||
2e52f5e5 | 1006 | /* |
44684f61 | 1007 | * ALSA PCM open callback |
5dab11d8 | 1008 | */ |
b556290f | 1009 | static int had_pcm_open(struct snd_pcm_substream *substream) |
5dab11d8 JA |
1010 | { |
1011 | struct snd_intelhad *intelhaddata; | |
1012 | struct snd_pcm_runtime *runtime; | |
5dab11d8 JA |
1013 | int retval; |
1014 | ||
5dab11d8 | 1015 | intelhaddata = snd_pcm_substream_chip(substream); |
5dab11d8 JA |
1016 | runtime = substream->runtime; |
1017 | ||
182cdf23 | 1018 | pm_runtime_get_sync(intelhaddata->dev); |
5dab11d8 | 1019 | |
91b0cb0c | 1020 | if (!intelhaddata->connected) { |
c75b0476 TI |
1021 | dev_dbg(intelhaddata->dev, "%s: HDMI cable plugged-out\n", |
1022 | __func__); | |
5dab11d8 | 1023 | retval = -ENODEV; |
fa5dfe6a | 1024 | goto error; |
5dab11d8 JA |
1025 | } |
1026 | ||
1027 | /* set the runtime hw parameter with local snd_pcm_hardware struct */ | |
b556290f | 1028 | runtime->hw = had_pcm_hardware; |
5dab11d8 | 1029 | |
5dab11d8 JA |
1030 | retval = snd_pcm_hw_constraint_integer(runtime, |
1031 | SNDRV_PCM_HW_PARAM_PERIODS); | |
1032 | if (retval < 0) | |
fa5dfe6a | 1033 | goto error; |
5dab11d8 JA |
1034 | |
1035 | /* Make sure, that the period size is always aligned | |
1036 | * 64byte boundary | |
1037 | */ | |
1038 | retval = snd_pcm_hw_constraint_step(substream->runtime, 0, | |
1039 | SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64); | |
73997b05 | 1040 | if (retval < 0) |
fa5dfe6a | 1041 | goto error; |
5dab11d8 | 1042 | |
73997b05 | 1043 | /* expose PCM substream */ |
313d9f28 TI |
1044 | spin_lock_irq(&intelhaddata->had_spinlock); |
1045 | intelhaddata->stream_info.substream = substream; | |
1046 | intelhaddata->stream_info.substream_refcount++; | |
1047 | spin_unlock_irq(&intelhaddata->had_spinlock); | |
1048 | ||
5dab11d8 | 1049 | return retval; |
fa5dfe6a | 1050 | error: |
5dab11d8 | 1051 | pm_runtime_put(intelhaddata->dev); |
5dab11d8 JA |
1052 | return retval; |
1053 | } | |
1054 | ||
2e52f5e5 | 1055 | /* |
44684f61 | 1056 | * ALSA PCM close callback |
5dab11d8 | 1057 | */ |
b556290f | 1058 | static int had_pcm_close(struct snd_pcm_substream *substream) |
5dab11d8 JA |
1059 | { |
1060 | struct snd_intelhad *intelhaddata; | |
5dab11d8 | 1061 | |
5dab11d8 | 1062 | intelhaddata = snd_pcm_substream_chip(substream); |
5dab11d8 | 1063 | |
73997b05 | 1064 | /* unreference and sync with the pending PCM accesses */ |
313d9f28 TI |
1065 | spin_lock_irq(&intelhaddata->had_spinlock); |
1066 | intelhaddata->stream_info.substream = NULL; | |
1067 | intelhaddata->stream_info.substream_refcount--; | |
1068 | while (intelhaddata->stream_info.substream_refcount > 0) { | |
1069 | spin_unlock_irq(&intelhaddata->had_spinlock); | |
1070 | cpu_relax(); | |
1071 | spin_lock_irq(&intelhaddata->had_spinlock); | |
1072 | } | |
1073 | spin_unlock_irq(&intelhaddata->had_spinlock); | |
5dab11d8 | 1074 | |
5dab11d8 JA |
1075 | pm_runtime_put(intelhaddata->dev); |
1076 | return 0; | |
1077 | } | |
1078 | ||
2e52f5e5 | 1079 | /* |
44684f61 | 1080 | * ALSA PCM hw_params callback |
5dab11d8 | 1081 | */ |
b556290f TI |
1082 | static int had_pcm_hw_params(struct snd_pcm_substream *substream, |
1083 | struct snd_pcm_hw_params *hw_params) | |
5dab11d8 | 1084 | { |
c75b0476 | 1085 | struct snd_intelhad *intelhaddata; |
5dab11d8 JA |
1086 | unsigned long addr; |
1087 | int pages, buf_size, retval; | |
1088 | ||
c75b0476 | 1089 | intelhaddata = snd_pcm_substream_chip(substream); |
5dab11d8 JA |
1090 | buf_size = params_buffer_bytes(hw_params); |
1091 | retval = snd_pcm_lib_malloc_pages(substream, buf_size); | |
1092 | if (retval < 0) | |
1093 | return retval; | |
c75b0476 TI |
1094 | dev_dbg(intelhaddata->dev, "%s:allocated memory = %d\n", |
1095 | __func__, buf_size); | |
5dab11d8 JA |
1096 | /* mark the pages as uncached region */ |
1097 | addr = (unsigned long) substream->runtime->dma_area; | |
1098 | pages = (substream->runtime->dma_bytes + PAGE_SIZE - 1) / PAGE_SIZE; | |
1099 | retval = set_memory_uc(addr, pages); | |
1100 | if (retval) { | |
c75b0476 TI |
1101 | dev_err(intelhaddata->dev, "set_memory_uc failed.Error:%d\n", |
1102 | retval); | |
5dab11d8 JA |
1103 | return retval; |
1104 | } | |
1105 | memset(substream->runtime->dma_area, 0, buf_size); | |
1106 | ||
1107 | return retval; | |
1108 | } | |
1109 | ||
2e52f5e5 | 1110 | /* |
44684f61 | 1111 | * ALSA PCM hw_free callback |
5dab11d8 | 1112 | */ |
b556290f | 1113 | static int had_pcm_hw_free(struct snd_pcm_substream *substream) |
5dab11d8 JA |
1114 | { |
1115 | unsigned long addr; | |
1116 | u32 pages; | |
1117 | ||
5dab11d8 JA |
1118 | /* mark back the pages as cached/writeback region before the free */ |
1119 | if (substream->runtime->dma_area != NULL) { | |
1120 | addr = (unsigned long) substream->runtime->dma_area; | |
1121 | pages = (substream->runtime->dma_bytes + PAGE_SIZE - 1) / | |
1122 | PAGE_SIZE; | |
1123 | set_memory_wb(addr, pages); | |
1124 | return snd_pcm_lib_free_pages(substream); | |
1125 | } | |
1126 | return 0; | |
1127 | } | |
1128 | ||
2e52f5e5 | 1129 | /* |
44684f61 | 1130 | * ALSA PCM trigger callback |
5dab11d8 | 1131 | */ |
b556290f | 1132 | static int had_pcm_trigger(struct snd_pcm_substream *substream, int cmd) |
5dab11d8 | 1133 | { |
da864809 | 1134 | int retval = 0; |
5dab11d8 | 1135 | struct snd_intelhad *intelhaddata; |
5dab11d8 | 1136 | |
5dab11d8 | 1137 | intelhaddata = snd_pcm_substream_chip(substream); |
5dab11d8 JA |
1138 | |
1139 | switch (cmd) { | |
1140 | case SNDRV_PCM_TRIGGER_START: | |
182cdf23 TI |
1141 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
1142 | case SNDRV_PCM_TRIGGER_RESUME: | |
5dab11d8 | 1143 | /* Disable local INTRs till register prgmng is done */ |
91b0cb0c | 1144 | if (!intelhaddata->connected) { |
c75b0476 TI |
1145 | dev_dbg(intelhaddata->dev, |
1146 | "_START: HDMI cable plugged-out\n"); | |
5dab11d8 JA |
1147 | retval = -ENODEV; |
1148 | break; | |
1149 | } | |
5dab11d8 | 1150 | |
f69bd104 | 1151 | intelhaddata->stream_info.running = true; |
5dab11d8 JA |
1152 | |
1153 | /* Enable Audio */ | |
075a1d46 | 1154 | had_ack_irqs(intelhaddata); /* FIXME: do we need this? */ |
40ce4b5d | 1155 | had_enable_audio(intelhaddata, true); |
5dab11d8 JA |
1156 | break; |
1157 | ||
1158 | case SNDRV_PCM_TRIGGER_STOP: | |
182cdf23 TI |
1159 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
1160 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
bcce775c | 1161 | spin_lock(&intelhaddata->had_spinlock); |
5dab11d8 | 1162 | |
c75b0476 | 1163 | /* Stop reporting BUFFER_DONE/UNDERRUN to above layers */ |
5dab11d8 | 1164 | |
f69bd104 | 1165 | intelhaddata->stream_info.running = false; |
bcce775c | 1166 | spin_unlock(&intelhaddata->had_spinlock); |
5dab11d8 | 1167 | /* Disable Audio */ |
40ce4b5d | 1168 | had_enable_audio(intelhaddata, false); |
5dab11d8 | 1169 | /* Reset buffer pointers */ |
f4566aa1 | 1170 | had_reset_audio(intelhaddata); |
5dab11d8 JA |
1171 | break; |
1172 | ||
1173 | default: | |
1174 | retval = -EINVAL; | |
1175 | } | |
1176 | return retval; | |
1177 | } | |
1178 | ||
2e52f5e5 | 1179 | /* |
44684f61 | 1180 | * ALSA PCM prepare callback |
5dab11d8 | 1181 | */ |
b556290f | 1182 | static int had_pcm_prepare(struct snd_pcm_substream *substream) |
5dab11d8 JA |
1183 | { |
1184 | int retval; | |
1185 | u32 disp_samp_freq, n_param; | |
964ca808 | 1186 | u32 link_rate = 0; |
5dab11d8 JA |
1187 | struct snd_intelhad *intelhaddata; |
1188 | struct snd_pcm_runtime *runtime; | |
5dab11d8 | 1189 | |
5dab11d8 JA |
1190 | intelhaddata = snd_pcm_substream_chip(substream); |
1191 | runtime = substream->runtime; | |
5dab11d8 | 1192 | |
91b0cb0c | 1193 | if (!intelhaddata->connected) { |
c75b0476 TI |
1194 | dev_dbg(intelhaddata->dev, "%s: HDMI cable plugged-out\n", |
1195 | __func__); | |
5dab11d8 JA |
1196 | retval = -ENODEV; |
1197 | goto prep_end; | |
1198 | } | |
1199 | ||
c75b0476 | 1200 | dev_dbg(intelhaddata->dev, "period_size=%d\n", |
5dab11d8 | 1201 | (int)frames_to_bytes(runtime, runtime->period_size)); |
c75b0476 TI |
1202 | dev_dbg(intelhaddata->dev, "periods=%d\n", runtime->periods); |
1203 | dev_dbg(intelhaddata->dev, "buffer_size=%d\n", | |
1204 | (int)snd_pcm_lib_buffer_bytes(substream)); | |
1205 | dev_dbg(intelhaddata->dev, "rate=%d\n", runtime->rate); | |
1206 | dev_dbg(intelhaddata->dev, "channels=%d\n", runtime->channels); | |
5dab11d8 | 1207 | |
5dab11d8 | 1208 | /* Get N value in KHz */ |
da864809 | 1209 | disp_samp_freq = intelhaddata->tmds_clock_speed; |
5dab11d8 | 1210 | |
b556290f | 1211 | retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata); |
5dab11d8 | 1212 | if (retval) { |
c75b0476 TI |
1213 | dev_err(intelhaddata->dev, |
1214 | "programming N value failed %#x\n", retval); | |
5dab11d8 JA |
1215 | goto prep_end; |
1216 | } | |
964ca808 PLB |
1217 | |
1218 | if (intelhaddata->dp_output) | |
da864809 | 1219 | link_rate = intelhaddata->link_rate; |
964ca808 | 1220 | |
b556290f TI |
1221 | had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate, |
1222 | n_param, intelhaddata); | |
5dab11d8 | 1223 | |
b556290f | 1224 | had_prog_dip(substream, intelhaddata); |
5dab11d8 | 1225 | |
b556290f | 1226 | retval = had_init_audio_ctrl(substream, intelhaddata); |
5dab11d8 JA |
1227 | |
1228 | /* Prog buffer address */ | |
e1b239f3 | 1229 | had_init_ringbuf(substream, intelhaddata); |
5dab11d8 JA |
1230 | |
1231 | /* | |
1232 | * Program channel mapping in following order: | |
1233 | * FL, FR, C, LFE, RL, RR | |
1234 | */ | |
1235 | ||
79dda75a | 1236 | had_write_register(intelhaddata, AUD_BUF_CH_SWAP, SWAP_LFE_CENTER); |
5dab11d8 JA |
1237 | |
1238 | prep_end: | |
1239 | return retval; | |
1240 | } | |
1241 | ||
2e52f5e5 | 1242 | /* |
44684f61 | 1243 | * ALSA PCM pointer callback |
5dab11d8 | 1244 | */ |
b556290f | 1245 | static snd_pcm_uframes_t had_pcm_pointer(struct snd_pcm_substream *substream) |
5dab11d8 JA |
1246 | { |
1247 | struct snd_intelhad *intelhaddata; | |
e1b239f3 | 1248 | int len; |
5dab11d8 | 1249 | |
5dab11d8 JA |
1250 | intelhaddata = snd_pcm_substream_chip(substream); |
1251 | ||
91b0cb0c | 1252 | if (!intelhaddata->connected) |
79f439ea TI |
1253 | return SNDRV_PCM_POS_XRUN; |
1254 | ||
e1b239f3 TI |
1255 | len = had_process_ringbuf(substream, intelhaddata); |
1256 | if (len < 0) | |
1257 | return SNDRV_PCM_POS_XRUN; | |
1258 | return bytes_to_frames(substream->runtime, len); | |
5dab11d8 JA |
1259 | } |
1260 | ||
2e52f5e5 | 1261 | /* |
44684f61 | 1262 | * ALSA PCM mmap callback |
5dab11d8 | 1263 | */ |
b556290f TI |
1264 | static int had_pcm_mmap(struct snd_pcm_substream *substream, |
1265 | struct vm_area_struct *vma) | |
5dab11d8 | 1266 | { |
5dab11d8 JA |
1267 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); |
1268 | return remap_pfn_range(vma, vma->vm_start, | |
1269 | substream->dma_buffer.addr >> PAGE_SHIFT, | |
1270 | vma->vm_end - vma->vm_start, vma->vm_page_prot); | |
1271 | } | |
1272 | ||
73997b05 TI |
1273 | /* |
1274 | * ALSA PCM ops | |
1275 | */ | |
b556290f TI |
1276 | static const struct snd_pcm_ops had_pcm_ops = { |
1277 | .open = had_pcm_open, | |
1278 | .close = had_pcm_close, | |
73997b05 | 1279 | .ioctl = snd_pcm_lib_ioctl, |
b556290f TI |
1280 | .hw_params = had_pcm_hw_params, |
1281 | .hw_free = had_pcm_hw_free, | |
1282 | .prepare = had_pcm_prepare, | |
1283 | .trigger = had_pcm_trigger, | |
1284 | .pointer = had_pcm_pointer, | |
1285 | .mmap = had_pcm_mmap, | |
73997b05 TI |
1286 | }; |
1287 | ||
8f8d1d7f | 1288 | /* process mode change of the running stream; called in mutex */ |
b556290f | 1289 | static int had_process_mode_change(struct snd_intelhad *intelhaddata) |
5dab11d8 | 1290 | { |
da864809 | 1291 | struct snd_pcm_substream *substream; |
5dab11d8 JA |
1292 | int retval = 0; |
1293 | u32 disp_samp_freq, n_param; | |
964ca808 | 1294 | u32 link_rate = 0; |
5dab11d8 | 1295 | |
313d9f28 TI |
1296 | substream = had_substream_get(intelhaddata); |
1297 | if (!substream) | |
da864809 | 1298 | return 0; |
5dab11d8 JA |
1299 | |
1300 | /* Disable Audio */ | |
40ce4b5d | 1301 | had_enable_audio(intelhaddata, false); |
5dab11d8 JA |
1302 | |
1303 | /* Update CTS value */ | |
da864809 | 1304 | disp_samp_freq = intelhaddata->tmds_clock_speed; |
5dab11d8 | 1305 | |
b556290f | 1306 | retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata); |
5dab11d8 | 1307 | if (retval) { |
c75b0476 TI |
1308 | dev_err(intelhaddata->dev, |
1309 | "programming N value failed %#x\n", retval); | |
5dab11d8 JA |
1310 | goto out; |
1311 | } | |
964ca808 PLB |
1312 | |
1313 | if (intelhaddata->dp_output) | |
da864809 | 1314 | link_rate = intelhaddata->link_rate; |
964ca808 | 1315 | |
b556290f TI |
1316 | had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate, |
1317 | n_param, intelhaddata); | |
5dab11d8 JA |
1318 | |
1319 | /* Enable Audio */ | |
40ce4b5d | 1320 | had_enable_audio(intelhaddata, true); |
5dab11d8 JA |
1321 | |
1322 | out: | |
313d9f28 | 1323 | had_substream_put(intelhaddata); |
5dab11d8 JA |
1324 | return retval; |
1325 | } | |
1326 | ||
8f8d1d7f | 1327 | /* process hot plug, called from wq with mutex locked */ |
0e9c67d7 | 1328 | static void had_process_hot_plug(struct snd_intelhad *intelhaddata) |
372d855f | 1329 | { |
372d855f | 1330 | struct snd_pcm_substream *substream; |
372d855f | 1331 | |
bcce775c | 1332 | spin_lock_irq(&intelhaddata->had_spinlock); |
91b0cb0c | 1333 | if (intelhaddata->connected) { |
c75b0476 | 1334 | dev_dbg(intelhaddata->dev, "Device already connected\n"); |
bcce775c | 1335 | spin_unlock_irq(&intelhaddata->had_spinlock); |
0e9c67d7 | 1336 | return; |
372d855f | 1337 | } |
0e9c67d7 | 1338 | |
91b0cb0c | 1339 | intelhaddata->connected = true; |
c75b0476 TI |
1340 | dev_dbg(intelhaddata->dev, |
1341 | "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_CONNECTED\n", | |
372d855f | 1342 | __func__, __LINE__); |
bcce775c | 1343 | spin_unlock_irq(&intelhaddata->had_spinlock); |
372d855f | 1344 | |
372d855f | 1345 | /* Safety check */ |
313d9f28 | 1346 | substream = had_substream_get(intelhaddata); |
372d855f | 1347 | if (substream) { |
c75b0476 TI |
1348 | dev_dbg(intelhaddata->dev, |
1349 | "Force to stop the active stream by disconnection\n"); | |
372d855f TI |
1350 | /* Set runtime->state to hw_params done */ |
1351 | snd_pcm_stop(substream, SNDRV_PCM_STATE_SETUP); | |
313d9f28 | 1352 | had_substream_put(intelhaddata); |
372d855f TI |
1353 | } |
1354 | ||
1355 | had_build_channel_allocation_map(intelhaddata); | |
372d855f TI |
1356 | } |
1357 | ||
8f8d1d7f | 1358 | /* process hot unplug, called from wq with mutex locked */ |
0e9c67d7 | 1359 | static void had_process_hot_unplug(struct snd_intelhad *intelhaddata) |
372d855f | 1360 | { |
313d9f28 | 1361 | struct snd_pcm_substream *substream; |
372d855f | 1362 | |
313d9f28 TI |
1363 | substream = had_substream_get(intelhaddata); |
1364 | ||
bcce775c | 1365 | spin_lock_irq(&intelhaddata->had_spinlock); |
372d855f | 1366 | |
91b0cb0c | 1367 | if (!intelhaddata->connected) { |
c75b0476 | 1368 | dev_dbg(intelhaddata->dev, "Device already disconnected\n"); |
bcce775c | 1369 | spin_unlock_irq(&intelhaddata->had_spinlock); |
313d9f28 | 1370 | goto out; |
372d855f | 1371 | |
372d855f TI |
1372 | } |
1373 | ||
0e9c67d7 | 1374 | /* Disable Audio */ |
40ce4b5d | 1375 | had_enable_audio(intelhaddata, false); |
0e9c67d7 | 1376 | |
91b0cb0c | 1377 | intelhaddata->connected = false; |
c75b0476 TI |
1378 | dev_dbg(intelhaddata->dev, |
1379 | "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_DISCONNECTED\n", | |
372d855f | 1380 | __func__, __LINE__); |
313d9f28 | 1381 | spin_unlock_irq(&intelhaddata->had_spinlock); |
372d855f TI |
1382 | |
1383 | /* Report to above ALSA layer */ | |
313d9f28 TI |
1384 | if (substream) |
1385 | snd_pcm_stop(substream, SNDRV_PCM_STATE_SETUP); | |
372d855f | 1386 | |
313d9f28 TI |
1387 | out: |
1388 | if (substream) | |
1389 | had_substream_put(intelhaddata); | |
372d855f TI |
1390 | kfree(intelhaddata->chmap->chmap); |
1391 | intelhaddata->chmap->chmap = NULL; | |
372d855f TI |
1392 | } |
1393 | ||
73997b05 TI |
1394 | /* |
1395 | * ALSA iec958 and ELD controls | |
1396 | */ | |
5dab11d8 | 1397 | |
5dab11d8 JA |
1398 | static int had_iec958_info(struct snd_kcontrol *kcontrol, |
1399 | struct snd_ctl_elem_info *uinfo) | |
1400 | { | |
1401 | uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; | |
1402 | uinfo->count = 1; | |
1403 | return 0; | |
1404 | } | |
1405 | ||
1406 | static int had_iec958_get(struct snd_kcontrol *kcontrol, | |
1407 | struct snd_ctl_elem_value *ucontrol) | |
1408 | { | |
1409 | struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol); | |
1410 | ||
8f8d1d7f | 1411 | mutex_lock(&intelhaddata->mutex); |
5dab11d8 JA |
1412 | ucontrol->value.iec958.status[0] = (intelhaddata->aes_bits >> 0) & 0xff; |
1413 | ucontrol->value.iec958.status[1] = (intelhaddata->aes_bits >> 8) & 0xff; | |
1414 | ucontrol->value.iec958.status[2] = | |
1415 | (intelhaddata->aes_bits >> 16) & 0xff; | |
1416 | ucontrol->value.iec958.status[3] = | |
1417 | (intelhaddata->aes_bits >> 24) & 0xff; | |
8f8d1d7f | 1418 | mutex_unlock(&intelhaddata->mutex); |
5dab11d8 JA |
1419 | return 0; |
1420 | } | |
372d855f | 1421 | |
5dab11d8 JA |
1422 | static int had_iec958_mask_get(struct snd_kcontrol *kcontrol, |
1423 | struct snd_ctl_elem_value *ucontrol) | |
1424 | { | |
1425 | ucontrol->value.iec958.status[0] = 0xff; | |
1426 | ucontrol->value.iec958.status[1] = 0xff; | |
1427 | ucontrol->value.iec958.status[2] = 0xff; | |
1428 | ucontrol->value.iec958.status[3] = 0xff; | |
1429 | return 0; | |
1430 | } | |
372d855f | 1431 | |
5dab11d8 JA |
1432 | static int had_iec958_put(struct snd_kcontrol *kcontrol, |
1433 | struct snd_ctl_elem_value *ucontrol) | |
1434 | { | |
1435 | unsigned int val; | |
1436 | struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol); | |
8f8d1d7f | 1437 | int changed = 0; |
5dab11d8 | 1438 | |
5dab11d8 JA |
1439 | val = (ucontrol->value.iec958.status[0] << 0) | |
1440 | (ucontrol->value.iec958.status[1] << 8) | | |
1441 | (ucontrol->value.iec958.status[2] << 16) | | |
1442 | (ucontrol->value.iec958.status[3] << 24); | |
8f8d1d7f | 1443 | mutex_lock(&intelhaddata->mutex); |
5dab11d8 JA |
1444 | if (intelhaddata->aes_bits != val) { |
1445 | intelhaddata->aes_bits = val; | |
8f8d1d7f | 1446 | changed = 1; |
5dab11d8 | 1447 | } |
8f8d1d7f TI |
1448 | mutex_unlock(&intelhaddata->mutex); |
1449 | return changed; | |
5dab11d8 JA |
1450 | } |
1451 | ||
4aedb946 TI |
1452 | static int had_ctl_eld_info(struct snd_kcontrol *kcontrol, |
1453 | struct snd_ctl_elem_info *uinfo) | |
1454 | { | |
1455 | uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; | |
1456 | uinfo->count = HDMI_MAX_ELD_BYTES; | |
1457 | return 0; | |
1458 | } | |
1459 | ||
1460 | static int had_ctl_eld_get(struct snd_kcontrol *kcontrol, | |
1461 | struct snd_ctl_elem_value *ucontrol) | |
1462 | { | |
1463 | struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol); | |
1464 | ||
1465 | mutex_lock(&intelhaddata->mutex); | |
1466 | memcpy(ucontrol->value.bytes.data, intelhaddata->eld, | |
1467 | HDMI_MAX_ELD_BYTES); | |
1468 | mutex_unlock(&intelhaddata->mutex); | |
1469 | return 0; | |
1470 | } | |
5dab11d8 | 1471 | |
73997b05 | 1472 | static const struct snd_kcontrol_new had_controls[] = { |
4aedb946 TI |
1473 | { |
1474 | .access = SNDRV_CTL_ELEM_ACCESS_READ, | |
1475 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, | |
1476 | .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK), | |
1477 | .info = had_iec958_info, /* shared */ | |
1478 | .get = had_iec958_mask_get, | |
1479 | }, | |
1480 | { | |
1481 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, | |
1482 | .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), | |
1483 | .info = had_iec958_info, | |
1484 | .get = had_iec958_get, | |
1485 | .put = had_iec958_put, | |
1486 | }, | |
1487 | { | |
1488 | .access = (SNDRV_CTL_ELEM_ACCESS_READ | | |
1489 | SNDRV_CTL_ELEM_ACCESS_VOLATILE), | |
1490 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, | |
1491 | .name = "ELD", | |
1492 | .info = had_ctl_eld_info, | |
1493 | .get = had_ctl_eld_get, | |
1494 | }, | |
5dab11d8 JA |
1495 | }; |
1496 | ||
73997b05 TI |
1497 | /* |
1498 | * audio interrupt handler | |
1499 | */ | |
da864809 TI |
1500 | static irqreturn_t display_pipe_interrupt_handler(int irq, void *dev_id) |
1501 | { | |
1502 | struct snd_intelhad *ctx = dev_id; | |
1503 | u32 audio_stat, audio_reg; | |
1504 | ||
4151ee84 | 1505 | audio_reg = AUD_HDMI_STATUS; |
83af57dd | 1506 | had_read_register(ctx, audio_reg, &audio_stat); |
da864809 TI |
1507 | |
1508 | if (audio_stat & HDMI_AUDIO_UNDERRUN) { | |
83af57dd | 1509 | had_write_register(ctx, audio_reg, HDMI_AUDIO_UNDERRUN); |
da864809 TI |
1510 | had_process_buffer_underrun(ctx); |
1511 | } | |
1512 | ||
1513 | if (audio_stat & HDMI_AUDIO_BUFFER_DONE) { | |
83af57dd | 1514 | had_write_register(ctx, audio_reg, HDMI_AUDIO_BUFFER_DONE); |
da864809 TI |
1515 | had_process_buffer_done(ctx); |
1516 | } | |
1517 | ||
1518 | return IRQ_HANDLED; | |
1519 | } | |
1520 | ||
73997b05 TI |
1521 | /* |
1522 | * monitor plug/unplug notification from i915; just kick off the work | |
1523 | */ | |
da864809 TI |
1524 | static void notify_audio_lpe(struct platform_device *pdev) |
1525 | { | |
1526 | struct snd_intelhad *ctx = platform_get_drvdata(pdev); | |
da864809 | 1527 | |
99b2ab9d TI |
1528 | schedule_work(&ctx->hdmi_audio_wq); |
1529 | } | |
da864809 | 1530 | |
73997b05 | 1531 | /* the work to handle monitor hot plug/unplug */ |
99b2ab9d TI |
1532 | static void had_audio_wq(struct work_struct *work) |
1533 | { | |
1534 | struct snd_intelhad *ctx = | |
1535 | container_of(work, struct snd_intelhad, hdmi_audio_wq); | |
1536 | struct intel_hdmi_lpe_audio_pdata *pdata = ctx->dev->platform_data; | |
da864809 | 1537 | |
182cdf23 | 1538 | pm_runtime_get_sync(ctx->dev); |
8f8d1d7f | 1539 | mutex_lock(&ctx->mutex); |
99b2ab9d TI |
1540 | if (!pdata->hdmi_connected) { |
1541 | dev_dbg(ctx->dev, "%s: Event: HAD_NOTIFY_HOT_UNPLUG\n", | |
1542 | __func__); | |
4aedb946 | 1543 | memset(ctx->eld, 0, sizeof(ctx->eld)); /* clear the old ELD */ |
0e9c67d7 | 1544 | had_process_hot_unplug(ctx); |
da864809 TI |
1545 | } else { |
1546 | struct intel_hdmi_lpe_audio_eld *eld = &pdata->eld; | |
1547 | ||
0e9c67d7 TI |
1548 | dev_dbg(ctx->dev, "%s: HAD_NOTIFY_ELD : port = %d, tmds = %d\n", |
1549 | __func__, eld->port_id, pdata->tmds_clock_speed); | |
1550 | ||
da864809 TI |
1551 | switch (eld->pipe_id) { |
1552 | case 0: | |
1553 | ctx->had_config_offset = AUDIO_HDMI_CONFIG_A; | |
1554 | break; | |
1555 | case 1: | |
1556 | ctx->had_config_offset = AUDIO_HDMI_CONFIG_B; | |
1557 | break; | |
1558 | case 2: | |
1559 | ctx->had_config_offset = AUDIO_HDMI_CONFIG_C; | |
1560 | break; | |
1561 | default: | |
99b2ab9d | 1562 | dev_dbg(ctx->dev, "Invalid pipe %d\n", |
da864809 TI |
1563 | eld->pipe_id); |
1564 | break; | |
1565 | } | |
1566 | ||
df0435db | 1567 | memcpy(ctx->eld, eld->eld_data, sizeof(ctx->eld)); |
da864809 | 1568 | |
0e9c67d7 TI |
1569 | ctx->dp_output = pdata->dp_output; |
1570 | ctx->tmds_clock_speed = pdata->tmds_clock_speed; | |
1571 | ctx->link_rate = pdata->link_rate; | |
da864809 | 1572 | |
0e9c67d7 | 1573 | had_process_hot_plug(ctx); |
da864809 | 1574 | |
0e9c67d7 | 1575 | /* Process mode change if stream is active */ |
b556290f | 1576 | had_process_mode_change(ctx); |
da864809 | 1577 | } |
8f8d1d7f | 1578 | mutex_unlock(&ctx->mutex); |
182cdf23 TI |
1579 | pm_runtime_put(ctx->dev); |
1580 | } | |
1581 | ||
1582 | /* | |
1583 | * PM callbacks | |
1584 | */ | |
1585 | ||
1586 | static int hdmi_lpe_audio_runtime_suspend(struct device *dev) | |
1587 | { | |
1588 | struct snd_intelhad *ctx = dev_get_drvdata(dev); | |
1589 | struct snd_pcm_substream *substream; | |
1590 | ||
1591 | substream = had_substream_get(ctx); | |
1592 | if (substream) { | |
1593 | snd_pcm_suspend(substream); | |
1594 | had_substream_put(ctx); | |
1595 | } | |
1596 | ||
1597 | return 0; | |
1598 | } | |
1599 | ||
1df98924 | 1600 | static int __maybe_unused hdmi_lpe_audio_suspend(struct device *dev) |
182cdf23 TI |
1601 | { |
1602 | struct snd_intelhad *ctx = dev_get_drvdata(dev); | |
1603 | int err; | |
1604 | ||
1605 | err = hdmi_lpe_audio_runtime_suspend(dev); | |
1606 | if (!err) | |
1607 | snd_power_change_state(ctx->card, SNDRV_CTL_POWER_D3hot); | |
1608 | return err; | |
1609 | } | |
1610 | ||
1df98924 | 1611 | static int __maybe_unused hdmi_lpe_audio_resume(struct device *dev) |
182cdf23 TI |
1612 | { |
1613 | struct snd_intelhad *ctx = dev_get_drvdata(dev); | |
1614 | ||
1615 | snd_power_change_state(ctx->card, SNDRV_CTL_POWER_D0); | |
1616 | return 0; | |
da864809 TI |
1617 | } |
1618 | ||
1619 | /* release resources */ | |
1620 | static void hdmi_lpe_audio_free(struct snd_card *card) | |
1621 | { | |
1622 | struct snd_intelhad *ctx = card->private_data; | |
1623 | ||
99b2ab9d TI |
1624 | cancel_work_sync(&ctx->hdmi_audio_wq); |
1625 | ||
da864809 TI |
1626 | if (ctx->mmio_start) |
1627 | iounmap(ctx->mmio_start); | |
1628 | if (ctx->irq >= 0) | |
1629 | free_irq(ctx->irq, ctx); | |
1630 | } | |
1631 | ||
79dda75a | 1632 | /* |
da864809 | 1633 | * hdmi_lpe_audio_probe - start bridge with i915 |
5dab11d8 | 1634 | * |
da864809 | 1635 | * This function is called when the i915 driver creates the |
2e52f5e5 | 1636 | * hdmi-lpe-audio platform device. |
5dab11d8 | 1637 | */ |
da864809 | 1638 | static int hdmi_lpe_audio_probe(struct platform_device *pdev) |
5dab11d8 | 1639 | { |
5dab11d8 | 1640 | struct snd_card *card; |
da864809 TI |
1641 | struct snd_intelhad *ctx; |
1642 | struct snd_pcm *pcm; | |
1643 | struct intel_hdmi_lpe_audio_pdata *pdata; | |
1644 | int irq; | |
1645 | struct resource *res_mmio; | |
4aedb946 | 1646 | int i, ret; |
da864809 | 1647 | |
da864809 TI |
1648 | pdata = pdev->dev.platform_data; |
1649 | if (!pdata) { | |
1650 | dev_err(&pdev->dev, "%s: quit: pdata not allocated by i915!!\n", __func__); | |
1651 | return -EINVAL; | |
1652 | } | |
5dab11d8 | 1653 | |
da864809 TI |
1654 | /* get resources */ |
1655 | irq = platform_get_irq(pdev, 0); | |
1656 | if (irq < 0) { | |
1657 | dev_err(&pdev->dev, "Could not get irq resource\n"); | |
1658 | return -ENODEV; | |
1659 | } | |
1660 | ||
1661 | res_mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1662 | if (!res_mmio) { | |
1663 | dev_err(&pdev->dev, "Could not get IO_MEM resources\n"); | |
1664 | return -ENXIO; | |
1665 | } | |
5dab11d8 | 1666 | |
5647aec2 | 1667 | /* create a card instance with ALSA framework */ |
da864809 TI |
1668 | ret = snd_card_new(&pdev->dev, hdmi_card_index, hdmi_card_id, |
1669 | THIS_MODULE, sizeof(*ctx), &card); | |
1670 | if (ret) | |
1671 | return ret; | |
1672 | ||
1673 | ctx = card->private_data; | |
1674 | spin_lock_init(&ctx->had_spinlock); | |
8f8d1d7f | 1675 | mutex_init(&ctx->mutex); |
91b0cb0c | 1676 | ctx->connected = false; |
da864809 TI |
1677 | ctx->dev = &pdev->dev; |
1678 | ctx->card = card; | |
da864809 TI |
1679 | ctx->aes_bits = SNDRV_PCM_DEFAULT_CON_SPDIF; |
1680 | strcpy(card->driver, INTEL_HAD); | |
873ab035 TI |
1681 | strcpy(card->shortname, "Intel HDMI/DP LPE Audio"); |
1682 | strcpy(card->longname, "Intel HDMI/DP LPE Audio"); | |
da864809 TI |
1683 | |
1684 | ctx->irq = -1; | |
1685 | ctx->tmds_clock_speed = DIS_SAMPLE_RATE_148_5; | |
99b2ab9d | 1686 | INIT_WORK(&ctx->hdmi_audio_wq, had_audio_wq); |
da864809 TI |
1687 | |
1688 | card->private_free = hdmi_lpe_audio_free; | |
1689 | ||
1690 | /* assume pipe A as default */ | |
1691 | ctx->had_config_offset = AUDIO_HDMI_CONFIG_A; | |
1692 | ||
1693 | platform_set_drvdata(pdev, ctx); | |
1694 | ||
1695 | dev_dbg(&pdev->dev, "%s: mmio_start = 0x%x, mmio_end = 0x%x\n", | |
1696 | __func__, (unsigned int)res_mmio->start, | |
1697 | (unsigned int)res_mmio->end); | |
1698 | ||
1699 | ctx->mmio_start = ioremap_nocache(res_mmio->start, | |
1700 | (size_t)(resource_size(res_mmio))); | |
1701 | if (!ctx->mmio_start) { | |
1702 | dev_err(&pdev->dev, "Could not get ioremap\n"); | |
1703 | ret = -EACCES; | |
1704 | goto err; | |
1705 | } | |
5dab11d8 | 1706 | |
da864809 TI |
1707 | /* setup interrupt handler */ |
1708 | ret = request_irq(irq, display_pipe_interrupt_handler, 0, | |
1709 | pdev->name, ctx); | |
1710 | if (ret < 0) { | |
1711 | dev_err(&pdev->dev, "request_irq failed\n"); | |
1712 | goto err; | |
1713 | } | |
5dab11d8 | 1714 | |
da864809 TI |
1715 | ctx->irq = irq; |
1716 | ||
1717 | ret = snd_pcm_new(card, INTEL_HAD, PCM_INDEX, MAX_PB_STREAMS, | |
1718 | MAX_CAP_STREAMS, &pcm); | |
1719 | if (ret) | |
5dab11d8 JA |
1720 | goto err; |
1721 | ||
1722 | /* setup private data which can be retrieved when required */ | |
da864809 | 1723 | pcm->private_data = ctx; |
5dab11d8 JA |
1724 | pcm->info_flags = 0; |
1725 | strncpy(pcm->name, card->shortname, strlen(card->shortname)); | |
da864809 | 1726 | /* setup the ops for playabck */ |
b556290f | 1727 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &had_pcm_ops); |
412bbe7d TI |
1728 | |
1729 | /* only 32bit addressable */ | |
1730 | dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); | |
1731 | dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); | |
1732 | ||
e1b239f3 TI |
1733 | /* allocate dma pages; |
1734 | * try to allocate 600k buffer as default which is large enough | |
5dab11d8 | 1735 | */ |
da864809 | 1736 | snd_pcm_lib_preallocate_pages_for_all(pcm, |
5dab11d8 | 1737 | SNDRV_DMA_TYPE_DEV, NULL, |
e1b239f3 | 1738 | HAD_DEFAULT_BUFFER, HAD_MAX_BUFFER); |
5dab11d8 | 1739 | |
4aedb946 TI |
1740 | /* create controls */ |
1741 | for (i = 0; i < ARRAY_SIZE(had_controls); i++) { | |
1742 | ret = snd_ctl_add(card, snd_ctl_new1(&had_controls[i], ctx)); | |
1743 | if (ret < 0) | |
1744 | goto err; | |
1745 | } | |
5dab11d8 JA |
1746 | |
1747 | init_channel_allocations(); | |
1748 | ||
1749 | /* Register channel map controls */ | |
da864809 TI |
1750 | ret = had_register_chmap_ctls(ctx, pcm); |
1751 | if (ret < 0) | |
5dab11d8 JA |
1752 | goto err; |
1753 | ||
da864809 TI |
1754 | ret = snd_card_register(card); |
1755 | if (ret) | |
36ec0d99 TI |
1756 | goto err; |
1757 | ||
bcce775c | 1758 | spin_lock_irq(&pdata->lpe_audio_slock); |
da864809 | 1759 | pdata->notify_audio_lpe = notify_audio_lpe; |
99b2ab9d | 1760 | pdata->notify_pending = false; |
bcce775c | 1761 | spin_unlock_irq(&pdata->lpe_audio_slock); |
da864809 TI |
1762 | |
1763 | pm_runtime_set_active(&pdev->dev); | |
1764 | pm_runtime_enable(&pdev->dev); | |
1765 | ||
99b2ab9d | 1766 | dev_dbg(&pdev->dev, "%s: handle pending notification\n", __func__); |
da864809 | 1767 | schedule_work(&ctx->hdmi_audio_wq); |
5dab11d8 | 1768 | |
79dda75a | 1769 | return 0; |
5647aec2 | 1770 | |
5dab11d8 JA |
1771 | err: |
1772 | snd_card_free(card); | |
da864809 | 1773 | return ret; |
5dab11d8 JA |
1774 | } |
1775 | ||
79dda75a | 1776 | /* |
da864809 | 1777 | * hdmi_lpe_audio_remove - stop bridge with i915 |
5dab11d8 | 1778 | * |
2e52f5e5 | 1779 | * This function is called when the platform device is destroyed. |
5dab11d8 | 1780 | */ |
da864809 | 1781 | static int hdmi_lpe_audio_remove(struct platform_device *pdev) |
5dab11d8 | 1782 | { |
da864809 | 1783 | struct snd_intelhad *ctx = platform_get_drvdata(pdev); |
5dab11d8 | 1784 | |
da864809 | 1785 | snd_card_free(ctx->card); |
5dab11d8 JA |
1786 | return 0; |
1787 | } | |
1788 | ||
182cdf23 TI |
1789 | static const struct dev_pm_ops hdmi_lpe_audio_pm = { |
1790 | SET_SYSTEM_SLEEP_PM_OPS(hdmi_lpe_audio_suspend, hdmi_lpe_audio_resume) | |
1791 | SET_RUNTIME_PM_OPS(hdmi_lpe_audio_runtime_suspend, NULL, NULL) | |
1792 | }; | |
1793 | ||
da864809 TI |
1794 | static struct platform_driver hdmi_lpe_audio_driver = { |
1795 | .driver = { | |
1796 | .name = "hdmi-lpe-audio", | |
182cdf23 | 1797 | .pm = &hdmi_lpe_audio_pm, |
da864809 TI |
1798 | }, |
1799 | .probe = hdmi_lpe_audio_probe, | |
1800 | .remove = hdmi_lpe_audio_remove, | |
da864809 TI |
1801 | }; |
1802 | ||
1803 | module_platform_driver(hdmi_lpe_audio_driver); | |
1804 | MODULE_ALIAS("platform:hdmi_lpe_audio"); | |
1805 | ||
5dab11d8 JA |
1806 | MODULE_AUTHOR("Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>"); |
1807 | MODULE_AUTHOR("Ramesh Babu K V <ramesh.babu@intel.com>"); | |
1808 | MODULE_AUTHOR("Vaibhav Agarwal <vaibhav.agarwal@intel.com>"); | |
1809 | MODULE_AUTHOR("Jerome Anand <jerome.anand@intel.com>"); | |
1810 | MODULE_DESCRIPTION("Intel HDMI Audio driver"); | |
1811 | MODULE_LICENSE("GPL v2"); | |
1812 | MODULE_SUPPORTED_DEVICE("{Intel,Intel_HAD}"); |