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1 | //==- HexagonRegisterInfo.h - Hexagon Register Information Impl --*- C++ -*-==// |
2 | // | |
3 | // The LLVM Compiler Infrastructure | |
4 | // | |
5 | // This file is distributed under the University of Illinois Open Source | |
6 | // License. See LICENSE.TXT for details. | |
7 | // | |
8 | //===----------------------------------------------------------------------===// | |
9 | // | |
10 | // This file contains the Hexagon implementation of the TargetRegisterInfo | |
11 | // class. | |
12 | // | |
13 | //===----------------------------------------------------------------------===// | |
14 | ||
1a4d82fc JJ |
15 | #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONREGISTERINFO_H |
16 | #define LLVM_LIB_TARGET_HEXAGON_HEXAGONREGISTERINFO_H | |
223e47cc | 17 | |
223e47cc | 18 | #include "llvm/MC/MachineLocation.h" |
970d7e83 | 19 | #include "llvm/Target/TargetRegisterInfo.h" |
223e47cc LB |
20 | |
21 | #define GET_REGINFO_HEADER | |
22 | #include "HexagonGenRegisterInfo.inc" | |
23 | ||
24 | // | |
25 | // We try not to hard code the reserved registers in our code, | |
26 | // so the following two macros were defined. However, there | |
27 | // are still a few places that R11 and R10 are hard wired. | |
28 | // See below. If, in the future, we decided to change the reserved | |
29 | // register. Don't forget changing the following places. | |
30 | // | |
31 | // 1. the "Defs" set of STriw_pred in HexagonInstrInfo.td | |
32 | // 2. the "Defs" set of LDri_pred in HexagonInstrInfo.td | |
33 | // 3. the definition of "IntRegs" in HexagonRegisterInfo.td | |
34 | // 4. the definition of "DoubleRegs" in HexagonRegisterInfo.td | |
35 | // | |
36 | #define HEXAGON_RESERVED_REG_1 Hexagon::R10 | |
37 | #define HEXAGON_RESERVED_REG_2 Hexagon::R11 | |
38 | ||
39 | namespace llvm { | |
40 | ||
41 | class HexagonSubtarget; | |
42 | class HexagonInstrInfo; | |
43 | class Type; | |
44 | ||
45 | struct HexagonRegisterInfo : public HexagonGenRegisterInfo { | |
46 | HexagonSubtarget &Subtarget; | |
223e47cc | 47 | |
1a4d82fc | 48 | HexagonRegisterInfo(HexagonSubtarget &st); |
223e47cc LB |
49 | |
50 | /// Code Generation virtual methods... | |
1a4d82fc JJ |
51 | const MCPhysReg * |
52 | getCalleeSavedRegs(const MachineFunction *MF = nullptr) const override; | |
223e47cc | 53 | |
1a4d82fc JJ |
54 | const TargetRegisterClass* const* |
55 | getCalleeSavedRegClasses(const MachineFunction *MF = nullptr) const; | |
223e47cc | 56 | |
1a4d82fc | 57 | BitVector getReservedRegs(const MachineFunction &MF) const override; |
223e47cc | 58 | |
223e47cc | 59 | void eliminateFrameIndex(MachineBasicBlock::iterator II, |
970d7e83 | 60 | int SPAdj, unsigned FIOperandNum, |
1a4d82fc | 61 | RegScavenger *RS = nullptr) const override; |
223e47cc LB |
62 | |
63 | /// determineFrameLayout - Determine the size of the frame and maximum call | |
64 | /// frame size. | |
65 | void determineFrameLayout(MachineFunction &MF) const; | |
66 | ||
67 | /// requiresRegisterScavenging - returns true since we may need scavenging for | |
68 | /// a temporary register when generating hardware loop instructions. | |
1a4d82fc | 69 | bool requiresRegisterScavenging(const MachineFunction &MF) const override { |
223e47cc LB |
70 | return true; |
71 | } | |
72 | ||
1a4d82fc | 73 | bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override { |
223e47cc LB |
74 | return true; |
75 | } | |
76 | ||
77 | // Debug information queries. | |
78 | unsigned getRARegister() const; | |
1a4d82fc | 79 | unsigned getFrameRegister(const MachineFunction &MF) const override; |
223e47cc | 80 | unsigned getFrameRegister() const; |
223e47cc | 81 | unsigned getStackRegister() const; |
223e47cc LB |
82 | }; |
83 | ||
84 | } // end namespace llvm | |
85 | ||
86 | #endif |