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1 | //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=// |
2 | // | |
3 | // The LLVM Compiler Infrastructure | |
4 | // | |
5 | // This file is distributed under the University of Illinois Open Source | |
6 | // License. See LICENSE.TXT for details. | |
7 | // | |
8 | /// \file | |
9 | //===----------------------------------------------------------------------===// | |
10 | ||
1a4d82fc JJ |
11 | #ifndef LLVM_LIB_TARGET_R600_AMDGPU_H |
12 | #define LLVM_LIB_TARGET_R600_AMDGPU_H | |
970d7e83 | 13 | |
970d7e83 LB |
14 | #include "llvm/Support/TargetRegistry.h" |
15 | #include "llvm/Target/TargetMachine.h" | |
16 | ||
17 | namespace llvm { | |
18 | ||
1a4d82fc JJ |
19 | class AMDGPUInstrPrinter; |
20 | class AMDGPUSubtarget; | |
970d7e83 | 21 | class AMDGPUTargetMachine; |
1a4d82fc JJ |
22 | class FunctionPass; |
23 | class MCAsmInfo; | |
24 | class raw_ostream; | |
25 | class Target; | |
26 | class TargetMachine; | |
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27 | |
28 | // R600 Passes | |
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29 | FunctionPass *createR600VectorRegMerger(TargetMachine &tm); |
30 | FunctionPass *createR600TextureIntrinsicsReplacer(); | |
970d7e83 | 31 | FunctionPass *createR600ExpandSpecialInstrsPass(TargetMachine &tm); |
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32 | FunctionPass *createR600EmitClauseMarkers(); |
33 | FunctionPass *createR600ClauseMergePass(TargetMachine &tm); | |
34 | FunctionPass *createR600Packetizer(TargetMachine &tm); | |
35 | FunctionPass *createR600ControlFlowFinalizer(TargetMachine &tm); | |
36 | FunctionPass *createAMDGPUCFGStructurizerPass(); | |
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37 | |
38 | // SI Passes | |
1a4d82fc | 39 | FunctionPass *createSITypeRewriter(); |
970d7e83 | 40 | FunctionPass *createSIAnnotateControlFlowPass(); |
1a4d82fc JJ |
41 | FunctionPass *createSILowerI1CopiesPass(); |
42 | FunctionPass *createSIShrinkInstructionsPass(); | |
970d7e83 | 43 | FunctionPass *createSILowerControlFlowPass(TargetMachine &tm); |
1a4d82fc JJ |
44 | FunctionPass *createSIFixSGPRCopiesPass(TargetMachine &tm); |
45 | FunctionPass *createSIFixSGPRLiveRangesPass(); | |
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46 | FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS); |
47 | FunctionPass *createSIInsertWaits(TargetMachine &tm); | |
48 | ||
1a4d82fc JJ |
49 | void initializeSILowerI1CopiesPass(PassRegistry &); |
50 | extern char &SILowerI1CopiesID; | |
51 | ||
970d7e83 | 52 | // Passes common to R600 and SI |
1a4d82fc | 53 | FunctionPass *createAMDGPUPromoteAlloca(const AMDGPUSubtarget &ST); |
970d7e83 | 54 | Pass *createAMDGPUStructurizeCFGPass(); |
1a4d82fc JJ |
55 | FunctionPass *createAMDGPUISelDag(TargetMachine &tm); |
56 | ||
57 | /// \brief Creates an AMDGPU-specific Target Transformation Info pass. | |
58 | ImmutablePass * | |
59 | createAMDGPUTargetTransformInfoPass(const AMDGPUTargetMachine *TM); | |
60 | ||
61 | void initializeSIFixSGPRLiveRangesPass(PassRegistry&); | |
62 | extern char &SIFixSGPRLiveRangesID; | |
63 | ||
64 | ||
65 | extern Target TheAMDGPUTarget; | |
66 | ||
67 | namespace AMDGPU { | |
68 | enum TargetIndex { | |
69 | TI_CONSTDATA_START | |
70 | }; | |
71 | } | |
72 | ||
73 | #define END_OF_TEXT_LABEL_NAME "EndOfTextLabel" | |
970d7e83 LB |
74 | |
75 | } // End namespace llvm | |
76 | ||
77 | namespace ShaderType { | |
78 | enum Type { | |
79 | PIXEL = 0, | |
80 | VERTEX = 1, | |
81 | GEOMETRY = 2, | |
82 | COMPUTE = 3 | |
83 | }; | |
84 | } | |
85 | ||
1a4d82fc JJ |
86 | /// OpenCL uses address spaces to differentiate between |
87 | /// various memory regions on the hardware. On the CPU | |
88 | /// all of the address spaces point to the same memory, | |
89 | /// however on the GPU, each address space points to | |
90 | /// a separate piece of memory that is unique from other | |
91 | /// memory locations. | |
92 | namespace AMDGPUAS { | |
93 | enum AddressSpaces { | |
94 | PRIVATE_ADDRESS = 0, ///< Address space for private memory. | |
95 | GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0). | |
96 | CONSTANT_ADDRESS = 2, ///< Address space for constant memory | |
97 | LOCAL_ADDRESS = 3, ///< Address space for local memory. | |
98 | FLAT_ADDRESS = 4, ///< Address space for flat memory. | |
99 | REGION_ADDRESS = 5, ///< Address space for region memory. | |
100 | PARAM_D_ADDRESS = 6, ///< Address space for direct addressible parameter memory (CONST0) | |
101 | PARAM_I_ADDRESS = 7, ///< Address space for indirect addressible parameter memory (VTX1) | |
102 | ||
103 | // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on this | |
104 | // order to be able to dynamically index a constant buffer, for example: | |
105 | // | |
106 | // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx | |
107 | ||
108 | CONSTANT_BUFFER_0 = 8, | |
109 | CONSTANT_BUFFER_1 = 9, | |
110 | CONSTANT_BUFFER_2 = 10, | |
111 | CONSTANT_BUFFER_3 = 11, | |
112 | CONSTANT_BUFFER_4 = 12, | |
113 | CONSTANT_BUFFER_5 = 13, | |
114 | CONSTANT_BUFFER_6 = 14, | |
115 | CONSTANT_BUFFER_7 = 15, | |
116 | CONSTANT_BUFFER_8 = 16, | |
117 | CONSTANT_BUFFER_9 = 17, | |
118 | CONSTANT_BUFFER_10 = 18, | |
119 | CONSTANT_BUFFER_11 = 19, | |
120 | CONSTANT_BUFFER_12 = 20, | |
121 | CONSTANT_BUFFER_13 = 21, | |
122 | CONSTANT_BUFFER_14 = 22, | |
123 | CONSTANT_BUFFER_15 = 23, | |
124 | ADDRESS_NONE = 24, ///< Address space for unknown memory. | |
125 | LAST_ADDRESS = ADDRESS_NONE | |
126 | }; | |
127 | ||
128 | } // namespace AMDGPUAS | |
129 | ||
130 | #endif |