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223e47cc LB |
1 | //===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===// |
2 | // | |
3 | // The LLVM Compiler Infrastructure | |
4 | // | |
5 | // This file is distributed under the University of Illinois Open Source | |
6 | // License. See LICENSE.TXT for details. | |
7 | // | |
8 | //===----------------------------------------------------------------------===// | |
9 | // | |
10 | // This file implements the interfaces that Sparc uses to lower LLVM code into a | |
11 | // selection DAG. | |
12 | // | |
13 | //===----------------------------------------------------------------------===// | |
14 | ||
15 | #include "SparcISelLowering.h" | |
1a4d82fc | 16 | #include "MCTargetDesc/SparcMCExpr.h" |
223e47cc | 17 | #include "SparcMachineFunctionInfo.h" |
1a4d82fc | 18 | #include "SparcRegisterInfo.h" |
970d7e83 | 19 | #include "SparcTargetMachine.h" |
1a4d82fc | 20 | #include "SparcTargetObjectFile.h" |
223e47cc LB |
21 | #include "llvm/CodeGen/CallingConvLower.h" |
22 | #include "llvm/CodeGen/MachineFrameInfo.h" | |
23 | #include "llvm/CodeGen/MachineFunction.h" | |
24 | #include "llvm/CodeGen/MachineInstrBuilder.h" | |
25 | #include "llvm/CodeGen/MachineRegisterInfo.h" | |
26 | #include "llvm/CodeGen/SelectionDAG.h" | |
27 | #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" | |
970d7e83 LB |
28 | #include "llvm/IR/DerivedTypes.h" |
29 | #include "llvm/IR/Function.h" | |
30 | #include "llvm/IR/Module.h" | |
223e47cc LB |
31 | #include "llvm/Support/ErrorHandling.h" |
32 | using namespace llvm; | |
33 | ||
34 | ||
35 | //===----------------------------------------------------------------------===// | |
36 | // Calling Convention Implementation | |
37 | //===----------------------------------------------------------------------===// | |
38 | ||
39 | static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT, | |
40 | MVT &LocVT, CCValAssign::LocInfo &LocInfo, | |
41 | ISD::ArgFlagsTy &ArgFlags, CCState &State) | |
42 | { | |
43 | assert (ArgFlags.isSRet()); | |
44 | ||
1a4d82fc | 45 | // Assign SRet argument. |
223e47cc LB |
46 | State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, |
47 | 0, | |
48 | LocVT, LocInfo)); | |
49 | return true; | |
50 | } | |
51 | ||
52 | static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT, | |
53 | MVT &LocVT, CCValAssign::LocInfo &LocInfo, | |
54 | ISD::ArgFlagsTy &ArgFlags, CCState &State) | |
55 | { | |
1a4d82fc | 56 | static const MCPhysReg RegList[] = { |
223e47cc LB |
57 | SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 |
58 | }; | |
1a4d82fc | 59 | // Try to get first reg. |
223e47cc LB |
60 | if (unsigned Reg = State.AllocateReg(RegList, 6)) { |
61 | State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | |
62 | } else { | |
1a4d82fc | 63 | // Assign whole thing in stack. |
223e47cc LB |
64 | State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, |
65 | State.AllocateStack(8,4), | |
66 | LocVT, LocInfo)); | |
67 | return true; | |
68 | } | |
69 | ||
1a4d82fc | 70 | // Try to get second reg. |
223e47cc LB |
71 | if (unsigned Reg = State.AllocateReg(RegList, 6)) |
72 | State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | |
73 | else | |
74 | State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, | |
75 | State.AllocateStack(4,4), | |
76 | LocVT, LocInfo)); | |
77 | return true; | |
78 | } | |
79 | ||
1a4d82fc JJ |
80 | // Allocate a full-sized argument for the 64-bit ABI. |
81 | static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, | |
82 | MVT &LocVT, CCValAssign::LocInfo &LocInfo, | |
83 | ISD::ArgFlagsTy &ArgFlags, CCState &State) { | |
84 | assert((LocVT == MVT::f32 || LocVT == MVT::f128 | |
85 | || LocVT.getSizeInBits() == 64) && | |
86 | "Can't handle non-64 bits locations"); | |
87 | ||
88 | // Stack space is allocated for all arguments starting from [%fp+BIAS+128]. | |
89 | unsigned size = (LocVT == MVT::f128) ? 16 : 8; | |
90 | unsigned alignment = (LocVT == MVT::f128) ? 16 : 8; | |
91 | unsigned Offset = State.AllocateStack(size, alignment); | |
92 | unsigned Reg = 0; | |
93 | ||
94 | if (LocVT == MVT::i64 && Offset < 6*8) | |
95 | // Promote integers to %i0-%i5. | |
96 | Reg = SP::I0 + Offset/8; | |
97 | else if (LocVT == MVT::f64 && Offset < 16*8) | |
98 | // Promote doubles to %d0-%d30. (Which LLVM calls D0-D15). | |
99 | Reg = SP::D0 + Offset/8; | |
100 | else if (LocVT == MVT::f32 && Offset < 16*8) | |
101 | // Promote floats to %f1, %f3, ... | |
102 | Reg = SP::F1 + Offset/4; | |
103 | else if (LocVT == MVT::f128 && Offset < 16*8) | |
104 | // Promote long doubles to %q0-%q28. (Which LLVM calls Q0-Q7). | |
105 | Reg = SP::Q0 + Offset/16; | |
106 | ||
107 | // Promote to register when possible, otherwise use the stack slot. | |
108 | if (Reg) { | |
109 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | |
110 | return true; | |
111 | } | |
112 | ||
113 | // This argument goes on the stack in an 8-byte slot. | |
114 | // When passing floats, LocVT is smaller than 8 bytes. Adjust the offset to | |
115 | // the right-aligned float. The first 4 bytes of the stack slot are undefined. | |
116 | if (LocVT == MVT::f32) | |
117 | Offset += 4; | |
118 | ||
119 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); | |
120 | return true; | |
121 | } | |
122 | ||
123 | // Allocate a half-sized argument for the 64-bit ABI. | |
124 | // | |
125 | // This is used when passing { float, int } structs by value in registers. | |
126 | static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, | |
127 | MVT &LocVT, CCValAssign::LocInfo &LocInfo, | |
128 | ISD::ArgFlagsTy &ArgFlags, CCState &State) { | |
129 | assert(LocVT.getSizeInBits() == 32 && "Can't handle non-32 bits locations"); | |
130 | unsigned Offset = State.AllocateStack(4, 4); | |
131 | ||
132 | if (LocVT == MVT::f32 && Offset < 16*8) { | |
133 | // Promote floats to %f0-%f31. | |
134 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, SP::F0 + Offset/4, | |
135 | LocVT, LocInfo)); | |
136 | return true; | |
137 | } | |
138 | ||
139 | if (LocVT == MVT::i32 && Offset < 6*8) { | |
140 | // Promote integers to %i0-%i5, using half the register. | |
141 | unsigned Reg = SP::I0 + Offset/8; | |
142 | LocVT = MVT::i64; | |
143 | LocInfo = CCValAssign::AExt; | |
144 | ||
145 | // Set the Custom bit if this i32 goes in the high bits of a register. | |
146 | if (Offset % 8 == 0) | |
147 | State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, | |
148 | LocVT, LocInfo)); | |
149 | else | |
150 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | |
151 | return true; | |
152 | } | |
153 | ||
154 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); | |
155 | return true; | |
156 | } | |
157 | ||
223e47cc LB |
158 | #include "SparcGenCallingConv.inc" |
159 | ||
1a4d82fc JJ |
160 | // The calling conventions in SparcCallingConv.td are described in terms of the |
161 | // callee's register window. This function translates registers to the | |
162 | // corresponding caller window %o register. | |
163 | static unsigned toCallerWindow(unsigned Reg) { | |
164 | assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7 && "Unexpected enum"); | |
165 | if (Reg >= SP::I0 && Reg <= SP::I7) | |
166 | return Reg - SP::I0 + SP::O0; | |
167 | return Reg; | |
168 | } | |
169 | ||
223e47cc LB |
170 | SDValue |
171 | SparcTargetLowering::LowerReturn(SDValue Chain, | |
1a4d82fc | 172 | CallingConv::ID CallConv, bool IsVarArg, |
223e47cc LB |
173 | const SmallVectorImpl<ISD::OutputArg> &Outs, |
174 | const SmallVectorImpl<SDValue> &OutVals, | |
1a4d82fc JJ |
175 | SDLoc DL, SelectionDAG &DAG) const { |
176 | if (Subtarget->is64Bit()) | |
177 | return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG); | |
178 | return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG); | |
179 | } | |
223e47cc | 180 | |
1a4d82fc JJ |
181 | SDValue |
182 | SparcTargetLowering::LowerReturn_32(SDValue Chain, | |
183 | CallingConv::ID CallConv, bool IsVarArg, | |
184 | const SmallVectorImpl<ISD::OutputArg> &Outs, | |
185 | const SmallVectorImpl<SDValue> &OutVals, | |
186 | SDLoc DL, SelectionDAG &DAG) const { | |
223e47cc LB |
187 | MachineFunction &MF = DAG.getMachineFunction(); |
188 | ||
189 | // CCValAssign - represent the assignment of the return value to locations. | |
190 | SmallVector<CCValAssign, 16> RVLocs; | |
191 | ||
192 | // CCState - Info about the registers and stack slot. | |
1a4d82fc JJ |
193 | CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, |
194 | *DAG.getContext()); | |
223e47cc | 195 | |
1a4d82fc | 196 | // Analyze return values. |
223e47cc LB |
197 | CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32); |
198 | ||
223e47cc | 199 | SDValue Flag; |
970d7e83 LB |
200 | SmallVector<SDValue, 4> RetOps(1, Chain); |
201 | // Make room for the return address offset. | |
202 | RetOps.push_back(SDValue()); | |
223e47cc LB |
203 | |
204 | // Copy the result values into the output registers. | |
205 | for (unsigned i = 0; i != RVLocs.size(); ++i) { | |
206 | CCValAssign &VA = RVLocs[i]; | |
207 | assert(VA.isRegLoc() && "Can only return in registers!"); | |
208 | ||
1a4d82fc | 209 | Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), |
223e47cc LB |
210 | OutVals[i], Flag); |
211 | ||
212 | // Guarantee that all emitted copies are stuck together with flags. | |
213 | Flag = Chain.getValue(1); | |
970d7e83 | 214 | RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); |
223e47cc LB |
215 | } |
216 | ||
1a4d82fc | 217 | unsigned RetAddrOffset = 8; // Call Inst + Delay Slot |
223e47cc LB |
218 | // If the function returns a struct, copy the SRetReturnReg to I0 |
219 | if (MF.getFunction()->hasStructRetAttr()) { | |
220 | SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>(); | |
221 | unsigned Reg = SFI->getSRetReturnReg(); | |
222 | if (!Reg) | |
223 | llvm_unreachable("sret virtual register not created in the entry block"); | |
1a4d82fc JJ |
224 | SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy()); |
225 | Chain = DAG.getCopyToReg(Chain, DL, SP::I0, Val, Flag); | |
223e47cc | 226 | Flag = Chain.getValue(1); |
970d7e83 | 227 | RetOps.push_back(DAG.getRegister(SP::I0, getPointerTy())); |
223e47cc LB |
228 | RetAddrOffset = 12; // CallInst + Delay Slot + Unimp |
229 | } | |
230 | ||
970d7e83 LB |
231 | RetOps[0] = Chain; // Update chain. |
232 | RetOps[1] = DAG.getConstant(RetAddrOffset, MVT::i32); | |
223e47cc | 233 | |
970d7e83 | 234 | // Add the flag if we have it. |
223e47cc | 235 | if (Flag.getNode()) |
970d7e83 LB |
236 | RetOps.push_back(Flag); |
237 | ||
1a4d82fc | 238 | return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, RetOps); |
223e47cc LB |
239 | } |
240 | ||
1a4d82fc JJ |
241 | // Lower return values for the 64-bit ABI. |
242 | // Return values are passed the exactly the same way as function arguments. | |
223e47cc | 243 | SDValue |
1a4d82fc JJ |
244 | SparcTargetLowering::LowerReturn_64(SDValue Chain, |
245 | CallingConv::ID CallConv, bool IsVarArg, | |
246 | const SmallVectorImpl<ISD::OutputArg> &Outs, | |
247 | const SmallVectorImpl<SDValue> &OutVals, | |
248 | SDLoc DL, SelectionDAG &DAG) const { | |
249 | // CCValAssign - represent the assignment of the return value to locations. | |
250 | SmallVector<CCValAssign, 16> RVLocs; | |
251 | ||
252 | // CCState - Info about the registers and stack slot. | |
253 | CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, | |
254 | *DAG.getContext()); | |
223e47cc | 255 | |
1a4d82fc JJ |
256 | // Analyze return values. |
257 | CCInfo.AnalyzeReturn(Outs, RetCC_Sparc64); | |
258 | ||
259 | SDValue Flag; | |
260 | SmallVector<SDValue, 4> RetOps(1, Chain); | |
261 | ||
262 | // The second operand on the return instruction is the return address offset. | |
263 | // The return address is always %i7+8 with the 64-bit ABI. | |
264 | RetOps.push_back(DAG.getConstant(8, MVT::i32)); | |
265 | ||
266 | // Copy the result values into the output registers. | |
267 | for (unsigned i = 0; i != RVLocs.size(); ++i) { | |
268 | CCValAssign &VA = RVLocs[i]; | |
269 | assert(VA.isRegLoc() && "Can only return in registers!"); | |
270 | SDValue OutVal = OutVals[i]; | |
271 | ||
272 | // Integer return values must be sign or zero extended by the callee. | |
273 | switch (VA.getLocInfo()) { | |
274 | case CCValAssign::Full: break; | |
275 | case CCValAssign::SExt: | |
276 | OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal); | |
277 | break; | |
278 | case CCValAssign::ZExt: | |
279 | OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal); | |
280 | break; | |
281 | case CCValAssign::AExt: | |
282 | OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal); | |
283 | break; | |
284 | default: | |
285 | llvm_unreachable("Unknown loc info!"); | |
286 | } | |
287 | ||
288 | // The custom bit on an i32 return value indicates that it should be passed | |
289 | // in the high bits of the register. | |
290 | if (VA.getValVT() == MVT::i32 && VA.needsCustom()) { | |
291 | OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal, | |
292 | DAG.getConstant(32, MVT::i32)); | |
293 | ||
294 | // The next value may go in the low bits of the same register. | |
295 | // Handle both at once. | |
296 | if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) { | |
297 | SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]); | |
298 | OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV); | |
299 | // Skip the next value, it's already done. | |
300 | ++i; | |
301 | } | |
302 | } | |
303 | ||
304 | Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag); | |
305 | ||
306 | // Guarantee that all emitted copies are stuck together with flags. | |
307 | Flag = Chain.getValue(1); | |
308 | RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); | |
309 | } | |
310 | ||
311 | RetOps[0] = Chain; // Update chain. | |
312 | ||
313 | // Add the flag if we have it. | |
314 | if (Flag.getNode()) | |
315 | RetOps.push_back(Flag); | |
316 | ||
317 | return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, RetOps); | |
318 | } | |
319 | ||
320 | SDValue SparcTargetLowering:: | |
321 | LowerFormalArguments(SDValue Chain, | |
322 | CallingConv::ID CallConv, | |
323 | bool IsVarArg, | |
324 | const SmallVectorImpl<ISD::InputArg> &Ins, | |
325 | SDLoc DL, | |
326 | SelectionDAG &DAG, | |
327 | SmallVectorImpl<SDValue> &InVals) const { | |
328 | if (Subtarget->is64Bit()) | |
329 | return LowerFormalArguments_64(Chain, CallConv, IsVarArg, Ins, | |
330 | DL, DAG, InVals); | |
331 | return LowerFormalArguments_32(Chain, CallConv, IsVarArg, Ins, | |
332 | DL, DAG, InVals); | |
333 | } | |
334 | ||
335 | /// LowerFormalArguments32 - V8 uses a very simple ABI, where all values are | |
336 | /// passed in either one or two GPRs, including FP values. TODO: we should | |
337 | /// pass FP values in FP registers for fastcc functions. | |
338 | SDValue SparcTargetLowering:: | |
339 | LowerFormalArguments_32(SDValue Chain, | |
340 | CallingConv::ID CallConv, | |
341 | bool isVarArg, | |
342 | const SmallVectorImpl<ISD::InputArg> &Ins, | |
343 | SDLoc dl, | |
344 | SelectionDAG &DAG, | |
345 | SmallVectorImpl<SDValue> &InVals) const { | |
223e47cc LB |
346 | MachineFunction &MF = DAG.getMachineFunction(); |
347 | MachineRegisterInfo &RegInfo = MF.getRegInfo(); | |
348 | SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>(); | |
349 | ||
350 | // Assign locations to all of the incoming arguments. | |
351 | SmallVector<CCValAssign, 16> ArgLocs; | |
1a4d82fc JJ |
352 | CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, |
353 | *DAG.getContext()); | |
223e47cc LB |
354 | CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32); |
355 | ||
356 | const unsigned StackOffset = 92; | |
357 | ||
1a4d82fc JJ |
358 | unsigned InIdx = 0; |
359 | for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i, ++InIdx) { | |
223e47cc LB |
360 | CCValAssign &VA = ArgLocs[i]; |
361 | ||
1a4d82fc JJ |
362 | if (Ins[InIdx].Flags.isSRet()) { |
363 | if (InIdx != 0) | |
364 | report_fatal_error("sparc only supports sret on the first parameter"); | |
365 | // Get SRet from [%fp+64]. | |
223e47cc LB |
366 | int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, 64, true); |
367 | SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); | |
368 | SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, | |
369 | MachinePointerInfo(), | |
370 | false, false, false, 0); | |
371 | InVals.push_back(Arg); | |
372 | continue; | |
373 | } | |
374 | ||
375 | if (VA.isRegLoc()) { | |
376 | if (VA.needsCustom()) { | |
377 | assert(VA.getLocVT() == MVT::f64); | |
378 | unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); | |
379 | MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi); | |
380 | SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32); | |
381 | ||
382 | assert(i+1 < e); | |
383 | CCValAssign &NextVA = ArgLocs[++i]; | |
384 | ||
385 | SDValue LoVal; | |
386 | if (NextVA.isMemLoc()) { | |
387 | int FrameIdx = MF.getFrameInfo()-> | |
388 | CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true); | |
389 | SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); | |
390 | LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, | |
391 | MachinePointerInfo(), | |
392 | false, false, false, 0); | |
393 | } else { | |
394 | unsigned loReg = MF.addLiveIn(NextVA.getLocReg(), | |
395 | &SP::IntRegsRegClass); | |
396 | LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32); | |
397 | } | |
398 | SDValue WholeValue = | |
399 | DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); | |
400 | WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue); | |
401 | InVals.push_back(WholeValue); | |
402 | continue; | |
403 | } | |
404 | unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); | |
405 | MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg); | |
406 | SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); | |
407 | if (VA.getLocVT() == MVT::f32) | |
408 | Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg); | |
409 | else if (VA.getLocVT() != MVT::i32) { | |
410 | Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg, | |
411 | DAG.getValueType(VA.getLocVT())); | |
412 | Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg); | |
413 | } | |
414 | InVals.push_back(Arg); | |
415 | continue; | |
416 | } | |
417 | ||
418 | assert(VA.isMemLoc()); | |
419 | ||
420 | unsigned Offset = VA.getLocMemOffset()+StackOffset; | |
421 | ||
422 | if (VA.needsCustom()) { | |
423 | assert(VA.getValVT() == MVT::f64); | |
1a4d82fc | 424 | // If it is double-word aligned, just load. |
223e47cc LB |
425 | if (Offset % 8 == 0) { |
426 | int FI = MF.getFrameInfo()->CreateFixedObject(8, | |
427 | Offset, | |
428 | true); | |
429 | SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); | |
430 | SDValue Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, | |
431 | MachinePointerInfo(), | |
432 | false,false, false, 0); | |
433 | InVals.push_back(Load); | |
434 | continue; | |
435 | } | |
436 | ||
437 | int FI = MF.getFrameInfo()->CreateFixedObject(4, | |
438 | Offset, | |
439 | true); | |
440 | SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); | |
441 | SDValue HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, | |
442 | MachinePointerInfo(), | |
443 | false, false, false, 0); | |
444 | int FI2 = MF.getFrameInfo()->CreateFixedObject(4, | |
445 | Offset+4, | |
446 | true); | |
447 | SDValue FIPtr2 = DAG.getFrameIndex(FI2, getPointerTy()); | |
448 | ||
449 | SDValue LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr2, | |
450 | MachinePointerInfo(), | |
451 | false, false, false, 0); | |
452 | ||
453 | SDValue WholeValue = | |
454 | DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); | |
455 | WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue); | |
456 | InVals.push_back(WholeValue); | |
457 | continue; | |
458 | } | |
459 | ||
460 | int FI = MF.getFrameInfo()->CreateFixedObject(4, | |
461 | Offset, | |
462 | true); | |
463 | SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); | |
464 | SDValue Load ; | |
465 | if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) { | |
466 | Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, | |
467 | MachinePointerInfo(), | |
468 | false, false, false, 0); | |
469 | } else { | |
470 | ISD::LoadExtType LoadOp = ISD::SEXTLOAD; | |
471 | // Sparc is big endian, so add an offset based on the ObjectVT. | |
472 | unsigned Offset = 4-std::max(1U, VA.getValVT().getSizeInBits()/8); | |
473 | FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr, | |
474 | DAG.getConstant(Offset, MVT::i32)); | |
475 | Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr, | |
476 | MachinePointerInfo(), | |
1a4d82fc | 477 | VA.getValVT(), false, false, false,0); |
223e47cc LB |
478 | Load = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Load); |
479 | } | |
480 | InVals.push_back(Load); | |
481 | } | |
482 | ||
483 | if (MF.getFunction()->hasStructRetAttr()) { | |
1a4d82fc | 484 | // Copy the SRet Argument to SRetReturnReg. |
223e47cc LB |
485 | SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>(); |
486 | unsigned Reg = SFI->getSRetReturnReg(); | |
487 | if (!Reg) { | |
488 | Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass); | |
489 | SFI->setSRetReturnReg(Reg); | |
490 | } | |
491 | SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); | |
492 | Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); | |
493 | } | |
494 | ||
495 | // Store remaining ArgRegs to the stack if this is a varargs function. | |
496 | if (isVarArg) { | |
1a4d82fc | 497 | static const MCPhysReg ArgRegs[] = { |
223e47cc LB |
498 | SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 |
499 | }; | |
500 | unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs, 6); | |
1a4d82fc | 501 | const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6; |
223e47cc LB |
502 | unsigned ArgOffset = CCInfo.getNextStackOffset(); |
503 | if (NumAllocated == 6) | |
504 | ArgOffset += StackOffset; | |
505 | else { | |
506 | assert(!ArgOffset); | |
507 | ArgOffset = 68+4*NumAllocated; | |
508 | } | |
509 | ||
510 | // Remember the vararg offset for the va_start implementation. | |
511 | FuncInfo->setVarArgsFrameOffset(ArgOffset); | |
512 | ||
513 | std::vector<SDValue> OutChains; | |
514 | ||
515 | for (; CurArgReg != ArgRegEnd; ++CurArgReg) { | |
516 | unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); | |
517 | MF.getRegInfo().addLiveIn(*CurArgReg, VReg); | |
518 | SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32); | |
519 | ||
520 | int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset, | |
521 | true); | |
522 | SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); | |
523 | ||
524 | OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr, | |
525 | MachinePointerInfo(), | |
526 | false, false, 0)); | |
527 | ArgOffset += 4; | |
528 | } | |
529 | ||
530 | if (!OutChains.empty()) { | |
531 | OutChains.push_back(Chain); | |
1a4d82fc JJ |
532 | Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains); |
533 | } | |
534 | } | |
535 | ||
536 | return Chain; | |
537 | } | |
538 | ||
539 | // Lower formal arguments for the 64 bit ABI. | |
540 | SDValue SparcTargetLowering:: | |
541 | LowerFormalArguments_64(SDValue Chain, | |
542 | CallingConv::ID CallConv, | |
543 | bool IsVarArg, | |
544 | const SmallVectorImpl<ISD::InputArg> &Ins, | |
545 | SDLoc DL, | |
546 | SelectionDAG &DAG, | |
547 | SmallVectorImpl<SDValue> &InVals) const { | |
548 | MachineFunction &MF = DAG.getMachineFunction(); | |
549 | ||
550 | // Analyze arguments according to CC_Sparc64. | |
551 | SmallVector<CCValAssign, 16> ArgLocs; | |
552 | CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, | |
553 | *DAG.getContext()); | |
554 | CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc64); | |
555 | ||
556 | // The argument array begins at %fp+BIAS+128, after the register save area. | |
557 | const unsigned ArgArea = 128; | |
558 | ||
559 | for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { | |
560 | CCValAssign &VA = ArgLocs[i]; | |
561 | if (VA.isRegLoc()) { | |
562 | // This argument is passed in a register. | |
563 | // All integer register arguments are promoted by the caller to i64. | |
564 | ||
565 | // Create a virtual register for the promoted live-in value. | |
566 | unsigned VReg = MF.addLiveIn(VA.getLocReg(), | |
567 | getRegClassFor(VA.getLocVT())); | |
568 | SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT()); | |
569 | ||
570 | // Get the high bits for i32 struct elements. | |
571 | if (VA.getValVT() == MVT::i32 && VA.needsCustom()) | |
572 | Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg, | |
573 | DAG.getConstant(32, MVT::i32)); | |
574 | ||
575 | // The caller promoted the argument, so insert an Assert?ext SDNode so we | |
576 | // won't promote the value again in this function. | |
577 | switch (VA.getLocInfo()) { | |
578 | case CCValAssign::SExt: | |
579 | Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg, | |
580 | DAG.getValueType(VA.getValVT())); | |
581 | break; | |
582 | case CCValAssign::ZExt: | |
583 | Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg, | |
584 | DAG.getValueType(VA.getValVT())); | |
585 | break; | |
586 | default: | |
587 | break; | |
588 | } | |
589 | ||
590 | // Truncate the register down to the argument type. | |
591 | if (VA.isExtInLoc()) | |
592 | Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg); | |
593 | ||
594 | InVals.push_back(Arg); | |
595 | continue; | |
223e47cc | 596 | } |
1a4d82fc JJ |
597 | |
598 | // The registers are exhausted. This argument was passed on the stack. | |
599 | assert(VA.isMemLoc()); | |
600 | // The CC_Sparc64_Full/Half functions compute stack offsets relative to the | |
601 | // beginning of the arguments area at %fp+BIAS+128. | |
602 | unsigned Offset = VA.getLocMemOffset() + ArgArea; | |
603 | unsigned ValSize = VA.getValVT().getSizeInBits() / 8; | |
604 | // Adjust offset for extended arguments, SPARC is big-endian. | |
605 | // The caller will have written the full slot with extended bytes, but we | |
606 | // prefer our own extending loads. | |
607 | if (VA.isExtInLoc()) | |
608 | Offset += 8 - ValSize; | |
609 | int FI = MF.getFrameInfo()->CreateFixedObject(ValSize, Offset, true); | |
610 | InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain, | |
611 | DAG.getFrameIndex(FI, getPointerTy()), | |
612 | MachinePointerInfo::getFixedStack(FI), | |
613 | false, false, false, 0)); | |
614 | } | |
615 | ||
616 | if (!IsVarArg) | |
617 | return Chain; | |
618 | ||
619 | // This function takes variable arguments, some of which may have been passed | |
620 | // in registers %i0-%i5. Variable floating point arguments are never passed | |
621 | // in floating point registers. They go on %i0-%i5 or on the stack like | |
622 | // integer arguments. | |
623 | // | |
624 | // The va_start intrinsic needs to know the offset to the first variable | |
625 | // argument. | |
626 | unsigned ArgOffset = CCInfo.getNextStackOffset(); | |
627 | SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>(); | |
628 | // Skip the 128 bytes of register save area. | |
629 | FuncInfo->setVarArgsFrameOffset(ArgOffset + ArgArea + | |
630 | Subtarget->getStackPointerBias()); | |
631 | ||
632 | // Save the variable arguments that were passed in registers. | |
633 | // The caller is required to reserve stack space for 6 arguments regardless | |
634 | // of how many arguments were actually passed. | |
635 | SmallVector<SDValue, 8> OutChains; | |
636 | for (; ArgOffset < 6*8; ArgOffset += 8) { | |
637 | unsigned VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass); | |
638 | SDValue VArg = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64); | |
639 | int FI = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset + ArgArea, true); | |
640 | OutChains.push_back(DAG.getStore(Chain, DL, VArg, | |
641 | DAG.getFrameIndex(FI, getPointerTy()), | |
642 | MachinePointerInfo::getFixedStack(FI), | |
643 | false, false, 0)); | |
223e47cc LB |
644 | } |
645 | ||
1a4d82fc JJ |
646 | if (!OutChains.empty()) |
647 | Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains); | |
648 | ||
223e47cc LB |
649 | return Chain; |
650 | } | |
651 | ||
652 | SDValue | |
653 | SparcTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, | |
654 | SmallVectorImpl<SDValue> &InVals) const { | |
1a4d82fc JJ |
655 | if (Subtarget->is64Bit()) |
656 | return LowerCall_64(CLI, InVals); | |
657 | return LowerCall_32(CLI, InVals); | |
658 | } | |
659 | ||
660 | static bool hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee, | |
661 | ImmutableCallSite *CS) { | |
662 | if (CS) | |
663 | return CS->hasFnAttr(Attribute::ReturnsTwice); | |
664 | ||
665 | const Function *CalleeFn = nullptr; | |
666 | if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { | |
667 | CalleeFn = dyn_cast<Function>(G->getGlobal()); | |
668 | } else if (ExternalSymbolSDNode *E = | |
669 | dyn_cast<ExternalSymbolSDNode>(Callee)) { | |
670 | const Function *Fn = DAG.getMachineFunction().getFunction(); | |
671 | const Module *M = Fn->getParent(); | |
672 | const char *CalleeName = E->getSymbol(); | |
673 | CalleeFn = M->getFunction(CalleeName); | |
674 | } | |
675 | ||
676 | if (!CalleeFn) | |
677 | return false; | |
678 | return CalleeFn->hasFnAttribute(Attribute::ReturnsTwice); | |
679 | } | |
680 | ||
681 | // Lower a call for the 32-bit ABI. | |
682 | SDValue | |
683 | SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI, | |
684 | SmallVectorImpl<SDValue> &InVals) const { | |
223e47cc | 685 | SelectionDAG &DAG = CLI.DAG; |
1a4d82fc JJ |
686 | SDLoc &dl = CLI.DL; |
687 | SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; | |
688 | SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; | |
689 | SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; | |
223e47cc LB |
690 | SDValue Chain = CLI.Chain; |
691 | SDValue Callee = CLI.Callee; | |
692 | bool &isTailCall = CLI.IsTailCall; | |
693 | CallingConv::ID CallConv = CLI.CallConv; | |
694 | bool isVarArg = CLI.IsVarArg; | |
695 | ||
696 | // Sparc target does not yet support tail call optimization. | |
697 | isTailCall = false; | |
698 | ||
699 | // Analyze operands of the call, assigning locations to each operand. | |
700 | SmallVector<CCValAssign, 16> ArgLocs; | |
1a4d82fc JJ |
701 | CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, |
702 | *DAG.getContext()); | |
223e47cc LB |
703 | CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32); |
704 | ||
705 | // Get the size of the outgoing arguments stack space requirement. | |
706 | unsigned ArgsSize = CCInfo.getNextStackOffset(); | |
707 | ||
708 | // Keep stack frames 8-byte aligned. | |
709 | ArgsSize = (ArgsSize+7) & ~7; | |
710 | ||
711 | MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); | |
712 | ||
1a4d82fc | 713 | // Create local copies for byval args. |
223e47cc LB |
714 | SmallVector<SDValue, 8> ByValArgs; |
715 | for (unsigned i = 0, e = Outs.size(); i != e; ++i) { | |
716 | ISD::ArgFlagsTy Flags = Outs[i].Flags; | |
717 | if (!Flags.isByVal()) | |
718 | continue; | |
719 | ||
720 | SDValue Arg = OutVals[i]; | |
721 | unsigned Size = Flags.getByValSize(); | |
722 | unsigned Align = Flags.getByValAlign(); | |
723 | ||
724 | int FI = MFI->CreateStackObject(Size, Align, false); | |
725 | SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); | |
726 | SDValue SizeNode = DAG.getConstant(Size, MVT::i32); | |
727 | ||
728 | Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align, | |
1a4d82fc JJ |
729 | false, // isVolatile, |
730 | (Size <= 32), // AlwaysInline if size <= 32 | |
223e47cc LB |
731 | MachinePointerInfo(), MachinePointerInfo()); |
732 | ByValArgs.push_back(FIPtr); | |
733 | } | |
734 | ||
1a4d82fc JJ |
735 | Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true), |
736 | dl); | |
223e47cc LB |
737 | |
738 | SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; | |
739 | SmallVector<SDValue, 8> MemOpChains; | |
740 | ||
741 | const unsigned StackOffset = 92; | |
742 | bool hasStructRetAttr = false; | |
743 | // Walk the register/memloc assignments, inserting copies/loads. | |
744 | for (unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.size(); | |
745 | i != e; | |
746 | ++i, ++realArgIdx) { | |
747 | CCValAssign &VA = ArgLocs[i]; | |
748 | SDValue Arg = OutVals[realArgIdx]; | |
749 | ||
750 | ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; | |
751 | ||
1a4d82fc | 752 | // Use local copy if it is a byval arg. |
223e47cc LB |
753 | if (Flags.isByVal()) |
754 | Arg = ByValArgs[byvalArgIdx++]; | |
755 | ||
756 | // Promote the value if needed. | |
757 | switch (VA.getLocInfo()) { | |
758 | default: llvm_unreachable("Unknown loc info!"); | |
759 | case CCValAssign::Full: break; | |
760 | case CCValAssign::SExt: | |
761 | Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); | |
762 | break; | |
763 | case CCValAssign::ZExt: | |
764 | Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); | |
765 | break; | |
766 | case CCValAssign::AExt: | |
767 | Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); | |
768 | break; | |
769 | case CCValAssign::BCvt: | |
770 | Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); | |
771 | break; | |
772 | } | |
773 | ||
774 | if (Flags.isSRet()) { | |
775 | assert(VA.needsCustom()); | |
776 | // store SRet argument in %sp+64 | |
777 | SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); | |
778 | SDValue PtrOff = DAG.getIntPtrConstant(64); | |
779 | PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); | |
780 | MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, | |
781 | MachinePointerInfo(), | |
782 | false, false, 0)); | |
783 | hasStructRetAttr = true; | |
784 | continue; | |
785 | } | |
786 | ||
787 | if (VA.needsCustom()) { | |
788 | assert(VA.getLocVT() == MVT::f64); | |
789 | ||
790 | if (VA.isMemLoc()) { | |
791 | unsigned Offset = VA.getLocMemOffset() + StackOffset; | |
1a4d82fc | 792 | // if it is double-word aligned, just store. |
223e47cc LB |
793 | if (Offset % 8 == 0) { |
794 | SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); | |
795 | SDValue PtrOff = DAG.getIntPtrConstant(Offset); | |
796 | PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); | |
797 | MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, | |
798 | MachinePointerInfo(), | |
799 | false, false, 0)); | |
800 | continue; | |
801 | } | |
802 | } | |
803 | ||
804 | SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32); | |
805 | SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, | |
806 | Arg, StackPtr, MachinePointerInfo(), | |
807 | false, false, 0); | |
808 | // Sparc is big-endian, so the high part comes first. | |
809 | SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr, | |
810 | MachinePointerInfo(), false, false, false, 0); | |
811 | // Increment the pointer to the other half. | |
812 | StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, | |
813 | DAG.getIntPtrConstant(4)); | |
814 | // Load the low part. | |
815 | SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr, | |
816 | MachinePointerInfo(), false, false, false, 0); | |
817 | ||
818 | if (VA.isRegLoc()) { | |
819 | RegsToPass.push_back(std::make_pair(VA.getLocReg(), Hi)); | |
820 | assert(i+1 != e); | |
821 | CCValAssign &NextVA = ArgLocs[++i]; | |
822 | if (NextVA.isRegLoc()) { | |
823 | RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo)); | |
824 | } else { | |
1a4d82fc | 825 | // Store the low part in stack. |
223e47cc LB |
826 | unsigned Offset = NextVA.getLocMemOffset() + StackOffset; |
827 | SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); | |
828 | SDValue PtrOff = DAG.getIntPtrConstant(Offset); | |
829 | PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); | |
830 | MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff, | |
831 | MachinePointerInfo(), | |
832 | false, false, 0)); | |
833 | } | |
834 | } else { | |
835 | unsigned Offset = VA.getLocMemOffset() + StackOffset; | |
836 | // Store the high part. | |
837 | SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); | |
838 | SDValue PtrOff = DAG.getIntPtrConstant(Offset); | |
839 | PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); | |
840 | MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff, | |
841 | MachinePointerInfo(), | |
842 | false, false, 0)); | |
843 | // Store the low part. | |
844 | PtrOff = DAG.getIntPtrConstant(Offset+4); | |
845 | PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); | |
846 | MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff, | |
847 | MachinePointerInfo(), | |
848 | false, false, 0)); | |
849 | } | |
850 | continue; | |
851 | } | |
852 | ||
853 | // Arguments that can be passed on register must be kept at | |
854 | // RegsToPass vector | |
855 | if (VA.isRegLoc()) { | |
856 | if (VA.getLocVT() != MVT::f32) { | |
857 | RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); | |
858 | continue; | |
859 | } | |
860 | Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); | |
861 | RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); | |
862 | continue; | |
863 | } | |
864 | ||
865 | assert(VA.isMemLoc()); | |
866 | ||
867 | // Create a store off the stack pointer for this argument. | |
868 | SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); | |
869 | SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+StackOffset); | |
870 | PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); | |
871 | MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, | |
872 | MachinePointerInfo(), | |
873 | false, false, 0)); | |
874 | } | |
875 | ||
876 | ||
877 | // Emit all stores, make sure the occur before any copies into physregs. | |
878 | if (!MemOpChains.empty()) | |
1a4d82fc | 879 | Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); |
223e47cc LB |
880 | |
881 | // Build a sequence of copy-to-reg nodes chained together with token | |
882 | // chain and flag operands which copy the outgoing args into registers. | |
883 | // The InFlag in necessary since all emitted instructions must be | |
884 | // stuck together. | |
885 | SDValue InFlag; | |
886 | for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { | |
1a4d82fc | 887 | unsigned Reg = toCallerWindow(RegsToPass[i].first); |
223e47cc LB |
888 | Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag); |
889 | InFlag = Chain.getValue(1); | |
890 | } | |
891 | ||
892 | unsigned SRetArgSize = (hasStructRetAttr)? getSRetArgSize(DAG, Callee):0; | |
1a4d82fc | 893 | bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CS); |
223e47cc LB |
894 | |
895 | // If the callee is a GlobalAddress node (quite common, every direct call is) | |
896 | // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. | |
897 | // Likewise ExternalSymbol -> TargetExternalSymbol. | |
1a4d82fc JJ |
898 | unsigned TF = ((getTargetMachine().getRelocationModel() == Reloc::PIC_) |
899 | ? SparcMCExpr::VK_Sparc_WPLT30 : 0); | |
223e47cc | 900 | if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) |
1a4d82fc | 901 | Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32, 0, TF); |
223e47cc | 902 | else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) |
1a4d82fc | 903 | Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32, TF); |
223e47cc LB |
904 | |
905 | // Returns a chain & a flag for retval copy to use | |
906 | SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); | |
907 | SmallVector<SDValue, 8> Ops; | |
908 | Ops.push_back(Chain); | |
909 | Ops.push_back(Callee); | |
910 | if (hasStructRetAttr) | |
911 | Ops.push_back(DAG.getTargetConstant(SRetArgSize, MVT::i32)); | |
1a4d82fc JJ |
912 | for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) |
913 | Ops.push_back(DAG.getRegister(toCallerWindow(RegsToPass[i].first), | |
914 | RegsToPass[i].second.getValueType())); | |
915 | ||
916 | // Add a register mask operand representing the call-preserved registers. | |
917 | const SparcRegisterInfo *TRI = | |
918 | getTargetMachine().getSubtarget<SparcSubtarget>().getRegisterInfo(); | |
919 | const uint32_t *Mask = ((hasReturnsTwice) | |
920 | ? TRI->getRTCallPreservedMask(CallConv) | |
921 | : TRI->getCallPreservedMask(CallConv)); | |
922 | assert(Mask && "Missing call preserved mask for calling convention"); | |
923 | Ops.push_back(DAG.getRegisterMask(Mask)); | |
223e47cc | 924 | |
223e47cc LB |
925 | if (InFlag.getNode()) |
926 | Ops.push_back(InFlag); | |
927 | ||
1a4d82fc | 928 | Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, Ops); |
223e47cc LB |
929 | InFlag = Chain.getValue(1); |
930 | ||
931 | Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true), | |
1a4d82fc | 932 | DAG.getIntPtrConstant(0, true), InFlag, dl); |
223e47cc LB |
933 | InFlag = Chain.getValue(1); |
934 | ||
935 | // Assign locations to each value returned by this call. | |
936 | SmallVector<CCValAssign, 16> RVLocs; | |
1a4d82fc JJ |
937 | CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, |
938 | *DAG.getContext()); | |
223e47cc LB |
939 | |
940 | RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32); | |
941 | ||
942 | // Copy all of the result registers out of their specified physreg. | |
943 | for (unsigned i = 0; i != RVLocs.size(); ++i) { | |
1a4d82fc | 944 | Chain = DAG.getCopyFromReg(Chain, dl, toCallerWindow(RVLocs[i].getLocReg()), |
223e47cc LB |
945 | RVLocs[i].getValVT(), InFlag).getValue(1); |
946 | InFlag = Chain.getValue(2); | |
947 | InVals.push_back(Chain.getValue(0)); | |
948 | } | |
949 | ||
950 | return Chain; | |
951 | } | |
952 | ||
1a4d82fc JJ |
953 | // This functions returns true if CalleeName is a ABI function that returns |
954 | // a long double (fp128). | |
955 | static bool isFP128ABICall(const char *CalleeName) | |
956 | { | |
957 | static const char *const ABICalls[] = | |
958 | { "_Q_add", "_Q_sub", "_Q_mul", "_Q_div", | |
959 | "_Q_sqrt", "_Q_neg", | |
960 | "_Q_itoq", "_Q_stoq", "_Q_dtoq", "_Q_utoq", | |
961 | "_Q_lltoq", "_Q_ulltoq", | |
962 | nullptr | |
963 | }; | |
964 | for (const char * const *I = ABICalls; *I != nullptr; ++I) | |
965 | if (strcmp(CalleeName, *I) == 0) | |
966 | return true; | |
967 | return false; | |
968 | } | |
969 | ||
223e47cc LB |
970 | unsigned |
971 | SparcTargetLowering::getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const | |
972 | { | |
1a4d82fc | 973 | const Function *CalleeFn = nullptr; |
223e47cc LB |
974 | if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { |
975 | CalleeFn = dyn_cast<Function>(G->getGlobal()); | |
976 | } else if (ExternalSymbolSDNode *E = | |
977 | dyn_cast<ExternalSymbolSDNode>(Callee)) { | |
978 | const Function *Fn = DAG.getMachineFunction().getFunction(); | |
979 | const Module *M = Fn->getParent(); | |
1a4d82fc JJ |
980 | const char *CalleeName = E->getSymbol(); |
981 | CalleeFn = M->getFunction(CalleeName); | |
982 | if (!CalleeFn && isFP128ABICall(CalleeName)) | |
983 | return 16; // Return sizeof(fp128) | |
223e47cc LB |
984 | } |
985 | ||
986 | if (!CalleeFn) | |
987 | return 0; | |
988 | ||
989 | assert(CalleeFn->hasStructRetAttr() && | |
990 | "Callee does not have the StructRet attribute."); | |
991 | ||
992 | PointerType *Ty = cast<PointerType>(CalleeFn->arg_begin()->getType()); | |
993 | Type *ElementTy = Ty->getElementType(); | |
970d7e83 | 994 | return getDataLayout()->getTypeAllocSize(ElementTy); |
223e47cc LB |
995 | } |
996 | ||
1a4d82fc JJ |
997 | |
998 | // Fixup floating point arguments in the ... part of a varargs call. | |
999 | // | |
1000 | // The SPARC v9 ABI requires that floating point arguments are treated the same | |
1001 | // as integers when calling a varargs function. This does not apply to the | |
1002 | // fixed arguments that are part of the function's prototype. | |
1003 | // | |
1004 | // This function post-processes a CCValAssign array created by | |
1005 | // AnalyzeCallOperands(). | |
1006 | static void fixupVariableFloatArgs(SmallVectorImpl<CCValAssign> &ArgLocs, | |
1007 | ArrayRef<ISD::OutputArg> Outs) { | |
1008 | for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { | |
1009 | const CCValAssign &VA = ArgLocs[i]; | |
1010 | MVT ValTy = VA.getLocVT(); | |
1011 | // FIXME: What about f32 arguments? C promotes them to f64 when calling | |
1012 | // varargs functions. | |
1013 | if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128)) | |
1014 | continue; | |
1015 | // The fixed arguments to a varargs function still go in FP registers. | |
1016 | if (Outs[VA.getValNo()].IsFixed) | |
1017 | continue; | |
1018 | ||
1019 | // This floating point argument should be reassigned. | |
1020 | CCValAssign NewVA; | |
1021 | ||
1022 | // Determine the offset into the argument array. | |
1023 | unsigned firstReg = (ValTy == MVT::f64) ? SP::D0 : SP::Q0; | |
1024 | unsigned argSize = (ValTy == MVT::f64) ? 8 : 16; | |
1025 | unsigned Offset = argSize * (VA.getLocReg() - firstReg); | |
1026 | assert(Offset < 16*8 && "Offset out of range, bad register enum?"); | |
1027 | ||
1028 | if (Offset < 6*8) { | |
1029 | // This argument should go in %i0-%i5. | |
1030 | unsigned IReg = SP::I0 + Offset/8; | |
1031 | if (ValTy == MVT::f64) | |
1032 | // Full register, just bitconvert into i64. | |
1033 | NewVA = CCValAssign::getReg(VA.getValNo(), VA.getValVT(), | |
1034 | IReg, MVT::i64, CCValAssign::BCvt); | |
1035 | else { | |
1036 | assert(ValTy == MVT::f128 && "Unexpected type!"); | |
1037 | // Full register, just bitconvert into i128 -- We will lower this into | |
1038 | // two i64s in LowerCall_64. | |
1039 | NewVA = CCValAssign::getCustomReg(VA.getValNo(), VA.getValVT(), | |
1040 | IReg, MVT::i128, CCValAssign::BCvt); | |
1041 | } | |
1042 | } else { | |
1043 | // This needs to go to memory, we're out of integer registers. | |
1044 | NewVA = CCValAssign::getMem(VA.getValNo(), VA.getValVT(), | |
1045 | Offset, VA.getLocVT(), VA.getLocInfo()); | |
1046 | } | |
1047 | ArgLocs[i] = NewVA; | |
1048 | } | |
1049 | } | |
1050 | ||
1051 | // Lower a call for the 64-bit ABI. | |
1052 | SDValue | |
1053 | SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI, | |
1054 | SmallVectorImpl<SDValue> &InVals) const { | |
1055 | SelectionDAG &DAG = CLI.DAG; | |
1056 | SDLoc DL = CLI.DL; | |
1057 | SDValue Chain = CLI.Chain; | |
1058 | ||
1059 | // Sparc target does not yet support tail call optimization. | |
1060 | CLI.IsTailCall = false; | |
1061 | ||
1062 | // Analyze operands of the call, assigning locations to each operand. | |
1063 | SmallVector<CCValAssign, 16> ArgLocs; | |
1064 | CCState CCInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), ArgLocs, | |
1065 | *DAG.getContext()); | |
1066 | CCInfo.AnalyzeCallOperands(CLI.Outs, CC_Sparc64); | |
1067 | ||
1068 | // Get the size of the outgoing arguments stack space requirement. | |
1069 | // The stack offset computed by CC_Sparc64 includes all arguments. | |
1070 | // Called functions expect 6 argument words to exist in the stack frame, used | |
1071 | // or not. | |
1072 | unsigned ArgsSize = std::max(6*8u, CCInfo.getNextStackOffset()); | |
1073 | ||
1074 | // Keep stack frames 16-byte aligned. | |
1075 | ArgsSize = RoundUpToAlignment(ArgsSize, 16); | |
1076 | ||
1077 | // Varargs calls require special treatment. | |
1078 | if (CLI.IsVarArg) | |
1079 | fixupVariableFloatArgs(ArgLocs, CLI.Outs); | |
1080 | ||
1081 | // Adjust the stack pointer to make room for the arguments. | |
1082 | // FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls | |
1083 | // with more than 6 arguments. | |
1084 | Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true), | |
1085 | DL); | |
1086 | ||
1087 | // Collect the set of registers to pass to the function and their values. | |
1088 | // This will be emitted as a sequence of CopyToReg nodes glued to the call | |
1089 | // instruction. | |
1090 | SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; | |
1091 | ||
1092 | // Collect chains from all the memory opeations that copy arguments to the | |
1093 | // stack. They must follow the stack pointer adjustment above and precede the | |
1094 | // call instruction itself. | |
1095 | SmallVector<SDValue, 8> MemOpChains; | |
1096 | ||
1097 | for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { | |
1098 | const CCValAssign &VA = ArgLocs[i]; | |
1099 | SDValue Arg = CLI.OutVals[i]; | |
1100 | ||
1101 | // Promote the value if needed. | |
1102 | switch (VA.getLocInfo()) { | |
1103 | default: | |
1104 | llvm_unreachable("Unknown location info!"); | |
1105 | case CCValAssign::Full: | |
1106 | break; | |
1107 | case CCValAssign::SExt: | |
1108 | Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg); | |
1109 | break; | |
1110 | case CCValAssign::ZExt: | |
1111 | Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); | |
1112 | break; | |
1113 | case CCValAssign::AExt: | |
1114 | Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); | |
1115 | break; | |
1116 | case CCValAssign::BCvt: | |
1117 | // fixupVariableFloatArgs() may create bitcasts from f128 to i128. But | |
1118 | // SPARC does not support i128 natively. Lower it into two i64, see below. | |
1119 | if (!VA.needsCustom() || VA.getValVT() != MVT::f128 | |
1120 | || VA.getLocVT() != MVT::i128) | |
1121 | Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg); | |
1122 | break; | |
1123 | } | |
1124 | ||
1125 | if (VA.isRegLoc()) { | |
1126 | if (VA.needsCustom() && VA.getValVT() == MVT::f128 | |
1127 | && VA.getLocVT() == MVT::i128) { | |
1128 | // Store and reload into the interger register reg and reg+1. | |
1129 | unsigned Offset = 8 * (VA.getLocReg() - SP::I0); | |
1130 | unsigned StackOffset = Offset + Subtarget->getStackPointerBias() + 128; | |
1131 | SDValue StackPtr = DAG.getRegister(SP::O6, getPointerTy()); | |
1132 | SDValue HiPtrOff = DAG.getIntPtrConstant(StackOffset); | |
1133 | HiPtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, | |
1134 | HiPtrOff); | |
1135 | SDValue LoPtrOff = DAG.getIntPtrConstant(StackOffset + 8); | |
1136 | LoPtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, | |
1137 | LoPtrOff); | |
1138 | ||
1139 | // Store to %sp+BIAS+128+Offset | |
1140 | SDValue Store = DAG.getStore(Chain, DL, Arg, HiPtrOff, | |
1141 | MachinePointerInfo(), | |
1142 | false, false, 0); | |
1143 | // Load into Reg and Reg+1 | |
1144 | SDValue Hi64 = DAG.getLoad(MVT::i64, DL, Store, HiPtrOff, | |
1145 | MachinePointerInfo(), | |
1146 | false, false, false, 0); | |
1147 | SDValue Lo64 = DAG.getLoad(MVT::i64, DL, Store, LoPtrOff, | |
1148 | MachinePointerInfo(), | |
1149 | false, false, false, 0); | |
1150 | RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()), | |
1151 | Hi64)); | |
1152 | RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()+1), | |
1153 | Lo64)); | |
1154 | continue; | |
1155 | } | |
1156 | ||
1157 | // The custom bit on an i32 return value indicates that it should be | |
1158 | // passed in the high bits of the register. | |
1159 | if (VA.getValVT() == MVT::i32 && VA.needsCustom()) { | |
1160 | Arg = DAG.getNode(ISD::SHL, DL, MVT::i64, Arg, | |
1161 | DAG.getConstant(32, MVT::i32)); | |
1162 | ||
1163 | // The next value may go in the low bits of the same register. | |
1164 | // Handle both at once. | |
1165 | if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() && | |
1166 | ArgLocs[i+1].getLocReg() == VA.getLocReg()) { | |
1167 | SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, | |
1168 | CLI.OutVals[i+1]); | |
1169 | Arg = DAG.getNode(ISD::OR, DL, MVT::i64, Arg, NV); | |
1170 | // Skip the next value, it's already done. | |
1171 | ++i; | |
1172 | } | |
1173 | } | |
1174 | RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()), Arg)); | |
1175 | continue; | |
1176 | } | |
1177 | ||
1178 | assert(VA.isMemLoc()); | |
1179 | ||
1180 | // Create a store off the stack pointer for this argument. | |
1181 | SDValue StackPtr = DAG.getRegister(SP::O6, getPointerTy()); | |
1182 | // The argument area starts at %fp+BIAS+128 in the callee frame, | |
1183 | // %sp+BIAS+128 in ours. | |
1184 | SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() + | |
1185 | Subtarget->getStackPointerBias() + | |
1186 | 128); | |
1187 | PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff); | |
1188 | MemOpChains.push_back(DAG.getStore(Chain, DL, Arg, PtrOff, | |
1189 | MachinePointerInfo(), | |
1190 | false, false, 0)); | |
1191 | } | |
1192 | ||
1193 | // Emit all stores, make sure they occur before the call. | |
1194 | if (!MemOpChains.empty()) | |
1195 | Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); | |
1196 | ||
1197 | // Build a sequence of CopyToReg nodes glued together with token chain and | |
1198 | // glue operands which copy the outgoing args into registers. The InGlue is | |
1199 | // necessary since all emitted instructions must be stuck together in order | |
1200 | // to pass the live physical registers. | |
1201 | SDValue InGlue; | |
1202 | for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { | |
1203 | Chain = DAG.getCopyToReg(Chain, DL, | |
1204 | RegsToPass[i].first, RegsToPass[i].second, InGlue); | |
1205 | InGlue = Chain.getValue(1); | |
1206 | } | |
1207 | ||
1208 | // If the callee is a GlobalAddress node (quite common, every direct call is) | |
1209 | // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. | |
1210 | // Likewise ExternalSymbol -> TargetExternalSymbol. | |
1211 | SDValue Callee = CLI.Callee; | |
1212 | bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CS); | |
1213 | unsigned TF = ((getTargetMachine().getRelocationModel() == Reloc::PIC_) | |
1214 | ? SparcMCExpr::VK_Sparc_WPLT30 : 0); | |
1215 | if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) | |
1216 | Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy(), 0, | |
1217 | TF); | |
1218 | else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) | |
1219 | Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy(), TF); | |
1220 | ||
1221 | // Build the operands for the call instruction itself. | |
1222 | SmallVector<SDValue, 8> Ops; | |
1223 | Ops.push_back(Chain); | |
1224 | Ops.push_back(Callee); | |
1225 | for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) | |
1226 | Ops.push_back(DAG.getRegister(RegsToPass[i].first, | |
1227 | RegsToPass[i].second.getValueType())); | |
1228 | ||
1229 | // Add a register mask operand representing the call-preserved registers. | |
1230 | const SparcRegisterInfo *TRI = | |
1231 | getTargetMachine().getSubtarget<SparcSubtarget>().getRegisterInfo(); | |
1232 | const uint32_t *Mask = | |
1233 | ((hasReturnsTwice) ? TRI->getRTCallPreservedMask(CLI.CallConv) | |
1234 | : TRI->getCallPreservedMask(CLI.CallConv)); | |
1235 | assert(Mask && "Missing call preserved mask for calling convention"); | |
1236 | Ops.push_back(DAG.getRegisterMask(Mask)); | |
1237 | ||
1238 | // Make sure the CopyToReg nodes are glued to the call instruction which | |
1239 | // consumes the registers. | |
1240 | if (InGlue.getNode()) | |
1241 | Ops.push_back(InGlue); | |
1242 | ||
1243 | // Now the call itself. | |
1244 | SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); | |
1245 | Chain = DAG.getNode(SPISD::CALL, DL, NodeTys, Ops); | |
1246 | InGlue = Chain.getValue(1); | |
1247 | ||
1248 | // Revert the stack pointer immediately after the call. | |
1249 | Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true), | |
1250 | DAG.getIntPtrConstant(0, true), InGlue, DL); | |
1251 | InGlue = Chain.getValue(1); | |
1252 | ||
1253 | // Now extract the return values. This is more or less the same as | |
1254 | // LowerFormalArguments_64. | |
1255 | ||
1256 | // Assign locations to each value returned by this call. | |
1257 | SmallVector<CCValAssign, 16> RVLocs; | |
1258 | CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), RVLocs, | |
1259 | *DAG.getContext()); | |
1260 | ||
1261 | // Set inreg flag manually for codegen generated library calls that | |
1262 | // return float. | |
1263 | if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && CLI.CS == nullptr) | |
1264 | CLI.Ins[0].Flags.setInReg(); | |
1265 | ||
1266 | RVInfo.AnalyzeCallResult(CLI.Ins, RetCC_Sparc64); | |
1267 | ||
1268 | // Copy all of the result registers out of their specified physreg. | |
1269 | for (unsigned i = 0; i != RVLocs.size(); ++i) { | |
1270 | CCValAssign &VA = RVLocs[i]; | |
1271 | unsigned Reg = toCallerWindow(VA.getLocReg()); | |
1272 | ||
1273 | // When returning 'inreg {i32, i32 }', two consecutive i32 arguments can | |
1274 | // reside in the same register in the high and low bits. Reuse the | |
1275 | // CopyFromReg previous node to avoid duplicate copies. | |
1276 | SDValue RV; | |
1277 | if (RegisterSDNode *SrcReg = dyn_cast<RegisterSDNode>(Chain.getOperand(1))) | |
1278 | if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg) | |
1279 | RV = Chain.getValue(0); | |
1280 | ||
1281 | // But usually we'll create a new CopyFromReg for a different register. | |
1282 | if (!RV.getNode()) { | |
1283 | RV = DAG.getCopyFromReg(Chain, DL, Reg, RVLocs[i].getLocVT(), InGlue); | |
1284 | Chain = RV.getValue(1); | |
1285 | InGlue = Chain.getValue(2); | |
1286 | } | |
1287 | ||
1288 | // Get the high bits for i32 struct elements. | |
1289 | if (VA.getValVT() == MVT::i32 && VA.needsCustom()) | |
1290 | RV = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), RV, | |
1291 | DAG.getConstant(32, MVT::i32)); | |
1292 | ||
1293 | // The callee promoted the return value, so insert an Assert?ext SDNode so | |
1294 | // we won't promote the value again in this function. | |
1295 | switch (VA.getLocInfo()) { | |
1296 | case CCValAssign::SExt: | |
1297 | RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV, | |
1298 | DAG.getValueType(VA.getValVT())); | |
1299 | break; | |
1300 | case CCValAssign::ZExt: | |
1301 | RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV, | |
1302 | DAG.getValueType(VA.getValVT())); | |
1303 | break; | |
1304 | default: | |
1305 | break; | |
1306 | } | |
1307 | ||
1308 | // Truncate the register down to the return value type. | |
1309 | if (VA.isExtInLoc()) | |
1310 | RV = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), RV); | |
1311 | ||
1312 | InVals.push_back(RV); | |
1313 | } | |
1314 | ||
1315 | return Chain; | |
1316 | } | |
1317 | ||
223e47cc LB |
1318 | //===----------------------------------------------------------------------===// |
1319 | // TargetLowering Implementation | |
1320 | //===----------------------------------------------------------------------===// | |
1321 | ||
1322 | /// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC | |
1323 | /// condition. | |
1324 | static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { | |
1325 | switch (CC) { | |
1326 | default: llvm_unreachable("Unknown integer condition code!"); | |
1327 | case ISD::SETEQ: return SPCC::ICC_E; | |
1328 | case ISD::SETNE: return SPCC::ICC_NE; | |
1329 | case ISD::SETLT: return SPCC::ICC_L; | |
1330 | case ISD::SETGT: return SPCC::ICC_G; | |
1331 | case ISD::SETLE: return SPCC::ICC_LE; | |
1332 | case ISD::SETGE: return SPCC::ICC_GE; | |
1333 | case ISD::SETULT: return SPCC::ICC_CS; | |
1334 | case ISD::SETULE: return SPCC::ICC_LEU; | |
1335 | case ISD::SETUGT: return SPCC::ICC_GU; | |
1336 | case ISD::SETUGE: return SPCC::ICC_CC; | |
1337 | } | |
1338 | } | |
1339 | ||
1340 | /// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC | |
1341 | /// FCC condition. | |
1342 | static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { | |
1343 | switch (CC) { | |
1344 | default: llvm_unreachable("Unknown fp condition code!"); | |
1345 | case ISD::SETEQ: | |
1346 | case ISD::SETOEQ: return SPCC::FCC_E; | |
1347 | case ISD::SETNE: | |
1348 | case ISD::SETUNE: return SPCC::FCC_NE; | |
1349 | case ISD::SETLT: | |
1350 | case ISD::SETOLT: return SPCC::FCC_L; | |
1351 | case ISD::SETGT: | |
1352 | case ISD::SETOGT: return SPCC::FCC_G; | |
1353 | case ISD::SETLE: | |
1354 | case ISD::SETOLE: return SPCC::FCC_LE; | |
1355 | case ISD::SETGE: | |
1356 | case ISD::SETOGE: return SPCC::FCC_GE; | |
1357 | case ISD::SETULT: return SPCC::FCC_UL; | |
1358 | case ISD::SETULE: return SPCC::FCC_ULE; | |
1359 | case ISD::SETUGT: return SPCC::FCC_UG; | |
1360 | case ISD::SETUGE: return SPCC::FCC_UGE; | |
1361 | case ISD::SETUO: return SPCC::FCC_U; | |
1362 | case ISD::SETO: return SPCC::FCC_O; | |
1363 | case ISD::SETONE: return SPCC::FCC_LG; | |
1364 | case ISD::SETUEQ: return SPCC::FCC_UE; | |
1365 | } | |
1366 | } | |
1367 | ||
1368 | SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) | |
85aaf69f | 1369 | : TargetLowering(TM) { |
1a4d82fc | 1370 | Subtarget = &TM.getSubtarget<SparcSubtarget>(); |
223e47cc LB |
1371 | |
1372 | // Set up the register classes. | |
1373 | addRegisterClass(MVT::i32, &SP::IntRegsRegClass); | |
1374 | addRegisterClass(MVT::f32, &SP::FPRegsRegClass); | |
1375 | addRegisterClass(MVT::f64, &SP::DFPRegsRegClass); | |
1a4d82fc JJ |
1376 | addRegisterClass(MVT::f128, &SP::QFPRegsRegClass); |
1377 | if (Subtarget->is64Bit()) | |
1378 | addRegisterClass(MVT::i64, &SP::I64RegsRegClass); | |
223e47cc LB |
1379 | |
1380 | // Turn FP extload into load/fextend | |
85aaf69f SL |
1381 | for (MVT VT : MVT::fp_valuetypes()) { |
1382 | setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); | |
1383 | setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand); | |
1384 | } | |
1a4d82fc | 1385 | |
223e47cc | 1386 | // Sparc doesn't have i1 sign extending load |
85aaf69f SL |
1387 | for (MVT VT : MVT::integer_valuetypes()) |
1388 | setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); | |
1a4d82fc | 1389 | |
223e47cc LB |
1390 | // Turn FP truncstore into trunc + store. |
1391 | setTruncStoreAction(MVT::f64, MVT::f32, Expand); | |
1a4d82fc JJ |
1392 | setTruncStoreAction(MVT::f128, MVT::f32, Expand); |
1393 | setTruncStoreAction(MVT::f128, MVT::f64, Expand); | |
223e47cc LB |
1394 | |
1395 | // Custom legalize GlobalAddress nodes into LO/HI parts. | |
1a4d82fc JJ |
1396 | setOperationAction(ISD::GlobalAddress, getPointerTy(), Custom); |
1397 | setOperationAction(ISD::GlobalTLSAddress, getPointerTy(), Custom); | |
1398 | setOperationAction(ISD::ConstantPool, getPointerTy(), Custom); | |
1399 | setOperationAction(ISD::BlockAddress, getPointerTy(), Custom); | |
223e47cc LB |
1400 | |
1401 | // Sparc doesn't have sext_inreg, replace them with shl/sra | |
1402 | setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); | |
1403 | setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); | |
1404 | setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); | |
1405 | ||
1406 | // Sparc has no REM or DIVREM operations. | |
1407 | setOperationAction(ISD::UREM, MVT::i32, Expand); | |
1408 | setOperationAction(ISD::SREM, MVT::i32, Expand); | |
1409 | setOperationAction(ISD::SDIVREM, MVT::i32, Expand); | |
1410 | setOperationAction(ISD::UDIVREM, MVT::i32, Expand); | |
1411 | ||
1a4d82fc JJ |
1412 | // ... nor does SparcV9. |
1413 | if (Subtarget->is64Bit()) { | |
1414 | setOperationAction(ISD::UREM, MVT::i64, Expand); | |
1415 | setOperationAction(ISD::SREM, MVT::i64, Expand); | |
1416 | setOperationAction(ISD::SDIVREM, MVT::i64, Expand); | |
1417 | setOperationAction(ISD::UDIVREM, MVT::i64, Expand); | |
1418 | } | |
1419 | ||
223e47cc LB |
1420 | // Custom expand fp<->sint |
1421 | setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); | |
1422 | setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); | |
1a4d82fc JJ |
1423 | setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); |
1424 | setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); | |
223e47cc | 1425 | |
1a4d82fc JJ |
1426 | // Custom Expand fp<->uint |
1427 | setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); | |
1428 | setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); | |
1429 | setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); | |
1430 | setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); | |
223e47cc LB |
1431 | |
1432 | setOperationAction(ISD::BITCAST, MVT::f32, Expand); | |
1433 | setOperationAction(ISD::BITCAST, MVT::i32, Expand); | |
1434 | ||
1435 | // Sparc has no select or setcc: expand to SELECT_CC. | |
1436 | setOperationAction(ISD::SELECT, MVT::i32, Expand); | |
1437 | setOperationAction(ISD::SELECT, MVT::f32, Expand); | |
1438 | setOperationAction(ISD::SELECT, MVT::f64, Expand); | |
1a4d82fc JJ |
1439 | setOperationAction(ISD::SELECT, MVT::f128, Expand); |
1440 | ||
223e47cc LB |
1441 | setOperationAction(ISD::SETCC, MVT::i32, Expand); |
1442 | setOperationAction(ISD::SETCC, MVT::f32, Expand); | |
1443 | setOperationAction(ISD::SETCC, MVT::f64, Expand); | |
1a4d82fc | 1444 | setOperationAction(ISD::SETCC, MVT::f128, Expand); |
223e47cc LB |
1445 | |
1446 | // Sparc doesn't have BRCOND either, it has BR_CC. | |
1447 | setOperationAction(ISD::BRCOND, MVT::Other, Expand); | |
1448 | setOperationAction(ISD::BRIND, MVT::Other, Expand); | |
1449 | setOperationAction(ISD::BR_JT, MVT::Other, Expand); | |
1450 | setOperationAction(ISD::BR_CC, MVT::i32, Custom); | |
1451 | setOperationAction(ISD::BR_CC, MVT::f32, Custom); | |
1452 | setOperationAction(ISD::BR_CC, MVT::f64, Custom); | |
1a4d82fc | 1453 | setOperationAction(ISD::BR_CC, MVT::f128, Custom); |
223e47cc LB |
1454 | |
1455 | setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); | |
1456 | setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); | |
1457 | setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); | |
1a4d82fc JJ |
1458 | setOperationAction(ISD::SELECT_CC, MVT::f128, Custom); |
1459 | ||
1460 | if (Subtarget->is64Bit()) { | |
1461 | setOperationAction(ISD::ADDC, MVT::i64, Custom); | |
1462 | setOperationAction(ISD::ADDE, MVT::i64, Custom); | |
1463 | setOperationAction(ISD::SUBC, MVT::i64, Custom); | |
1464 | setOperationAction(ISD::SUBE, MVT::i64, Custom); | |
1465 | setOperationAction(ISD::BITCAST, MVT::f64, Expand); | |
1466 | setOperationAction(ISD::BITCAST, MVT::i64, Expand); | |
1467 | setOperationAction(ISD::SELECT, MVT::i64, Expand); | |
1468 | setOperationAction(ISD::SETCC, MVT::i64, Expand); | |
1469 | setOperationAction(ISD::BR_CC, MVT::i64, Custom); | |
1470 | setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); | |
1471 | ||
1472 | setOperationAction(ISD::CTPOP, MVT::i64, | |
1473 | Subtarget->usePopc() ? Legal : Expand); | |
1474 | setOperationAction(ISD::CTTZ , MVT::i64, Expand); | |
1475 | setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); | |
1476 | setOperationAction(ISD::CTLZ , MVT::i64, Expand); | |
1477 | setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); | |
1478 | setOperationAction(ISD::BSWAP, MVT::i64, Expand); | |
1479 | setOperationAction(ISD::ROTL , MVT::i64, Expand); | |
1480 | setOperationAction(ISD::ROTR , MVT::i64, Expand); | |
1481 | setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom); | |
1482 | } | |
1483 | ||
1484 | // ATOMICs. | |
1485 | // FIXME: We insert fences for each atomics and generate sub-optimal code | |
1486 | // for PSO/TSO. Also, implement other atomicrmw operations. | |
1487 | ||
1488 | setInsertFencesForAtomic(true); | |
1489 | ||
1490 | setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Legal); | |
1491 | setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, | |
1492 | (Subtarget->isV9() ? Legal: Expand)); | |
223e47cc | 1493 | |
223e47cc | 1494 | |
1a4d82fc JJ |
1495 | setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Legal); |
1496 | ||
1497 | // Custom Lower Atomic LOAD/STORE | |
1498 | setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom); | |
1499 | setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom); | |
1500 | ||
1501 | if (Subtarget->is64Bit()) { | |
1502 | setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Legal); | |
1503 | setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Legal); | |
1504 | setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom); | |
1505 | setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Custom); | |
1506 | } | |
1507 | ||
1508 | if (!Subtarget->isV9()) { | |
1509 | // SparcV8 does not have FNEGD and FABSD. | |
1510 | setOperationAction(ISD::FNEG, MVT::f64, Custom); | |
1511 | setOperationAction(ISD::FABS, MVT::f64, Custom); | |
1512 | } | |
1513 | ||
1514 | setOperationAction(ISD::FSIN , MVT::f128, Expand); | |
1515 | setOperationAction(ISD::FCOS , MVT::f128, Expand); | |
1516 | setOperationAction(ISD::FSINCOS, MVT::f128, Expand); | |
1517 | setOperationAction(ISD::FREM , MVT::f128, Expand); | |
1518 | setOperationAction(ISD::FMA , MVT::f128, Expand); | |
223e47cc LB |
1519 | setOperationAction(ISD::FSIN , MVT::f64, Expand); |
1520 | setOperationAction(ISD::FCOS , MVT::f64, Expand); | |
970d7e83 | 1521 | setOperationAction(ISD::FSINCOS, MVT::f64, Expand); |
223e47cc LB |
1522 | setOperationAction(ISD::FREM , MVT::f64, Expand); |
1523 | setOperationAction(ISD::FMA , MVT::f64, Expand); | |
1524 | setOperationAction(ISD::FSIN , MVT::f32, Expand); | |
1525 | setOperationAction(ISD::FCOS , MVT::f32, Expand); | |
970d7e83 | 1526 | setOperationAction(ISD::FSINCOS, MVT::f32, Expand); |
223e47cc LB |
1527 | setOperationAction(ISD::FREM , MVT::f32, Expand); |
1528 | setOperationAction(ISD::FMA , MVT::f32, Expand); | |
223e47cc LB |
1529 | setOperationAction(ISD::CTTZ , MVT::i32, Expand); |
1530 | setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); | |
1531 | setOperationAction(ISD::CTLZ , MVT::i32, Expand); | |
1532 | setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); | |
1533 | setOperationAction(ISD::ROTL , MVT::i32, Expand); | |
1534 | setOperationAction(ISD::ROTR , MVT::i32, Expand); | |
1535 | setOperationAction(ISD::BSWAP, MVT::i32, Expand); | |
1a4d82fc | 1536 | setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand); |
223e47cc LB |
1537 | setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); |
1538 | setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); | |
1a4d82fc | 1539 | setOperationAction(ISD::FPOW , MVT::f128, Expand); |
223e47cc LB |
1540 | setOperationAction(ISD::FPOW , MVT::f64, Expand); |
1541 | setOperationAction(ISD::FPOW , MVT::f32, Expand); | |
1542 | ||
1543 | setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); | |
1544 | setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); | |
1545 | setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); | |
1546 | ||
1547 | // FIXME: Sparc provides these multiplies, but we don't have them yet. | |
1548 | setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); | |
1549 | setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); | |
1550 | ||
1a4d82fc JJ |
1551 | if (Subtarget->is64Bit()) { |
1552 | setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); | |
1553 | setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); | |
1554 | setOperationAction(ISD::MULHU, MVT::i64, Expand); | |
1555 | setOperationAction(ISD::MULHS, MVT::i64, Expand); | |
1556 | ||
1557 | setOperationAction(ISD::UMULO, MVT::i64, Custom); | |
1558 | setOperationAction(ISD::SMULO, MVT::i64, Custom); | |
1559 | ||
1560 | setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand); | |
1561 | setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand); | |
1562 | setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand); | |
1563 | } | |
223e47cc LB |
1564 | |
1565 | // VASTART needs to be custom lowered to use the VarArgsFrameIndex. | |
1566 | setOperationAction(ISD::VASTART , MVT::Other, Custom); | |
1567 | // VAARG needs to be lowered to not do unaligned accesses for doubles. | |
1568 | setOperationAction(ISD::VAARG , MVT::Other, Custom); | |
1569 | ||
1a4d82fc JJ |
1570 | setOperationAction(ISD::TRAP , MVT::Other, Legal); |
1571 | ||
223e47cc LB |
1572 | // Use the default implementation. |
1573 | setOperationAction(ISD::VACOPY , MVT::Other, Expand); | |
1574 | setOperationAction(ISD::VAEND , MVT::Other, Expand); | |
1575 | setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); | |
1576 | setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); | |
1577 | setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); | |
1578 | ||
1a4d82fc JJ |
1579 | setExceptionPointerRegister(SP::I0); |
1580 | setExceptionSelectorRegister(SP::I1); | |
223e47cc LB |
1581 | |
1582 | setStackPointerRegisterToSaveRestore(SP::O6); | |
1583 | ||
1a4d82fc JJ |
1584 | setOperationAction(ISD::CTPOP, MVT::i32, |
1585 | Subtarget->usePopc() ? Legal : Expand); | |
1586 | ||
1587 | if (Subtarget->isV9() && Subtarget->hasHardQuad()) { | |
1588 | setOperationAction(ISD::LOAD, MVT::f128, Legal); | |
1589 | setOperationAction(ISD::STORE, MVT::f128, Legal); | |
1590 | } else { | |
1591 | setOperationAction(ISD::LOAD, MVT::f128, Custom); | |
1592 | setOperationAction(ISD::STORE, MVT::f128, Custom); | |
1593 | } | |
1594 | ||
1595 | if (Subtarget->hasHardQuad()) { | |
1596 | setOperationAction(ISD::FADD, MVT::f128, Legal); | |
1597 | setOperationAction(ISD::FSUB, MVT::f128, Legal); | |
1598 | setOperationAction(ISD::FMUL, MVT::f128, Legal); | |
1599 | setOperationAction(ISD::FDIV, MVT::f128, Legal); | |
1600 | setOperationAction(ISD::FSQRT, MVT::f128, Legal); | |
1601 | setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal); | |
1602 | setOperationAction(ISD::FP_ROUND, MVT::f64, Legal); | |
1603 | if (Subtarget->isV9()) { | |
1604 | setOperationAction(ISD::FNEG, MVT::f128, Legal); | |
1605 | setOperationAction(ISD::FABS, MVT::f128, Legal); | |
1606 | } else { | |
1607 | setOperationAction(ISD::FNEG, MVT::f128, Custom); | |
1608 | setOperationAction(ISD::FABS, MVT::f128, Custom); | |
1609 | } | |
1610 | ||
1611 | if (!Subtarget->is64Bit()) { | |
1612 | setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Q_qtoll"); | |
1613 | setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Q_qtoull"); | |
1614 | setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Q_lltoq"); | |
1615 | setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Q_ulltoq"); | |
1616 | } | |
1617 | ||
1618 | } else { | |
1619 | // Custom legalize f128 operations. | |
1620 | ||
1621 | setOperationAction(ISD::FADD, MVT::f128, Custom); | |
1622 | setOperationAction(ISD::FSUB, MVT::f128, Custom); | |
1623 | setOperationAction(ISD::FMUL, MVT::f128, Custom); | |
1624 | setOperationAction(ISD::FDIV, MVT::f128, Custom); | |
1625 | setOperationAction(ISD::FSQRT, MVT::f128, Custom); | |
1626 | setOperationAction(ISD::FNEG, MVT::f128, Custom); | |
1627 | setOperationAction(ISD::FABS, MVT::f128, Custom); | |
1628 | ||
1629 | setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom); | |
1630 | setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); | |
1631 | setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); | |
1632 | ||
1633 | // Setup Runtime library names. | |
1634 | if (Subtarget->is64Bit()) { | |
1635 | setLibcallName(RTLIB::ADD_F128, "_Qp_add"); | |
1636 | setLibcallName(RTLIB::SUB_F128, "_Qp_sub"); | |
1637 | setLibcallName(RTLIB::MUL_F128, "_Qp_mul"); | |
1638 | setLibcallName(RTLIB::DIV_F128, "_Qp_div"); | |
1639 | setLibcallName(RTLIB::SQRT_F128, "_Qp_sqrt"); | |
1640 | setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Qp_qtoi"); | |
1641 | setLibcallName(RTLIB::FPTOUINT_F128_I32, "_Qp_qtoui"); | |
1642 | setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Qp_itoq"); | |
1643 | setLibcallName(RTLIB::UINTTOFP_I32_F128, "_Qp_uitoq"); | |
1644 | setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Qp_qtox"); | |
1645 | setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Qp_qtoux"); | |
1646 | setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Qp_xtoq"); | |
1647 | setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Qp_uxtoq"); | |
1648 | setLibcallName(RTLIB::FPEXT_F32_F128, "_Qp_stoq"); | |
1649 | setLibcallName(RTLIB::FPEXT_F64_F128, "_Qp_dtoq"); | |
1650 | setLibcallName(RTLIB::FPROUND_F128_F32, "_Qp_qtos"); | |
1651 | setLibcallName(RTLIB::FPROUND_F128_F64, "_Qp_qtod"); | |
1652 | } else { | |
1653 | setLibcallName(RTLIB::ADD_F128, "_Q_add"); | |
1654 | setLibcallName(RTLIB::SUB_F128, "_Q_sub"); | |
1655 | setLibcallName(RTLIB::MUL_F128, "_Q_mul"); | |
1656 | setLibcallName(RTLIB::DIV_F128, "_Q_div"); | |
1657 | setLibcallName(RTLIB::SQRT_F128, "_Q_sqrt"); | |
1658 | setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Q_qtoi"); | |
1659 | setLibcallName(RTLIB::FPTOUINT_F128_I32, "_Q_qtou"); | |
1660 | setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Q_itoq"); | |
1661 | setLibcallName(RTLIB::UINTTOFP_I32_F128, "_Q_utoq"); | |
1662 | setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Q_qtoll"); | |
1663 | setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Q_qtoull"); | |
1664 | setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Q_lltoq"); | |
1665 | setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Q_ulltoq"); | |
1666 | setLibcallName(RTLIB::FPEXT_F32_F128, "_Q_stoq"); | |
1667 | setLibcallName(RTLIB::FPEXT_F64_F128, "_Q_dtoq"); | |
1668 | setLibcallName(RTLIB::FPROUND_F128_F32, "_Q_qtos"); | |
1669 | setLibcallName(RTLIB::FPROUND_F128_F64, "_Q_qtod"); | |
1670 | } | |
1671 | } | |
223e47cc LB |
1672 | |
1673 | setMinFunctionAlignment(2); | |
1674 | ||
1675 | computeRegisterProperties(); | |
1676 | } | |
1677 | ||
1678 | const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { | |
1679 | switch (Opcode) { | |
1a4d82fc | 1680 | default: return nullptr; |
223e47cc LB |
1681 | case SPISD::CMPICC: return "SPISD::CMPICC"; |
1682 | case SPISD::CMPFCC: return "SPISD::CMPFCC"; | |
1683 | case SPISD::BRICC: return "SPISD::BRICC"; | |
1a4d82fc | 1684 | case SPISD::BRXCC: return "SPISD::BRXCC"; |
223e47cc LB |
1685 | case SPISD::BRFCC: return "SPISD::BRFCC"; |
1686 | case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC"; | |
1a4d82fc | 1687 | case SPISD::SELECT_XCC: return "SPISD::SELECT_XCC"; |
223e47cc LB |
1688 | case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC"; |
1689 | case SPISD::Hi: return "SPISD::Hi"; | |
1690 | case SPISD::Lo: return "SPISD::Lo"; | |
1691 | case SPISD::FTOI: return "SPISD::FTOI"; | |
1692 | case SPISD::ITOF: return "SPISD::ITOF"; | |
1a4d82fc JJ |
1693 | case SPISD::FTOX: return "SPISD::FTOX"; |
1694 | case SPISD::XTOF: return "SPISD::XTOF"; | |
223e47cc LB |
1695 | case SPISD::CALL: return "SPISD::CALL"; |
1696 | case SPISD::RET_FLAG: return "SPISD::RET_FLAG"; | |
1697 | case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG"; | |
1698 | case SPISD::FLUSHW: return "SPISD::FLUSHW"; | |
1a4d82fc JJ |
1699 | case SPISD::TLS_ADD: return "SPISD::TLS_ADD"; |
1700 | case SPISD::TLS_LD: return "SPISD::TLS_LD"; | |
1701 | case SPISD::TLS_CALL: return "SPISD::TLS_CALL"; | |
223e47cc LB |
1702 | } |
1703 | } | |
1704 | ||
1a4d82fc JJ |
1705 | EVT SparcTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const { |
1706 | if (!VT.isVector()) | |
1707 | return MVT::i32; | |
1708 | return VT.changeVectorElementTypeToInteger(); | |
1709 | } | |
1710 | ||
223e47cc LB |
1711 | /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to |
1712 | /// be zero. Op is expected to be a target specific node. Used by DAG | |
1713 | /// combiner. | |
1a4d82fc JJ |
1714 | void SparcTargetLowering::computeKnownBitsForTargetNode |
1715 | (const SDValue Op, | |
1716 | APInt &KnownZero, | |
1717 | APInt &KnownOne, | |
1718 | const SelectionDAG &DAG, | |
1719 | unsigned Depth) const { | |
223e47cc LB |
1720 | APInt KnownZero2, KnownOne2; |
1721 | KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0); | |
1722 | ||
1723 | switch (Op.getOpcode()) { | |
1724 | default: break; | |
1725 | case SPISD::SELECT_ICC: | |
1a4d82fc | 1726 | case SPISD::SELECT_XCC: |
223e47cc | 1727 | case SPISD::SELECT_FCC: |
1a4d82fc JJ |
1728 | DAG.computeKnownBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1); |
1729 | DAG.computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1); | |
223e47cc LB |
1730 | |
1731 | // Only known if known in both the LHS and RHS. | |
1732 | KnownOne &= KnownOne2; | |
1733 | KnownZero &= KnownZero2; | |
1734 | break; | |
1735 | } | |
1736 | } | |
1737 | ||
1738 | // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so | |
1739 | // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition. | |
1740 | static void LookThroughSetCC(SDValue &LHS, SDValue &RHS, | |
1741 | ISD::CondCode CC, unsigned &SPCC) { | |
1742 | if (isa<ConstantSDNode>(RHS) && | |
1743 | cast<ConstantSDNode>(RHS)->isNullValue() && | |
1744 | CC == ISD::SETNE && | |
1a4d82fc JJ |
1745 | (((LHS.getOpcode() == SPISD::SELECT_ICC || |
1746 | LHS.getOpcode() == SPISD::SELECT_XCC) && | |
223e47cc LB |
1747 | LHS.getOperand(3).getOpcode() == SPISD::CMPICC) || |
1748 | (LHS.getOpcode() == SPISD::SELECT_FCC && | |
1749 | LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) && | |
1750 | isa<ConstantSDNode>(LHS.getOperand(0)) && | |
1751 | isa<ConstantSDNode>(LHS.getOperand(1)) && | |
1752 | cast<ConstantSDNode>(LHS.getOperand(0))->isOne() && | |
1753 | cast<ConstantSDNode>(LHS.getOperand(1))->isNullValue()) { | |
1754 | SDValue CMPCC = LHS.getOperand(3); | |
1755 | SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue(); | |
1756 | LHS = CMPCC.getOperand(0); | |
1757 | RHS = CMPCC.getOperand(1); | |
1758 | } | |
1759 | } | |
1760 | ||
1a4d82fc JJ |
1761 | // Convert to a target node and set target flags. |
1762 | SDValue SparcTargetLowering::withTargetFlags(SDValue Op, unsigned TF, | |
1763 | SelectionDAG &DAG) const { | |
1764 | if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op)) | |
1765 | return DAG.getTargetGlobalAddress(GA->getGlobal(), | |
1766 | SDLoc(GA), | |
1767 | GA->getValueType(0), | |
1768 | GA->getOffset(), TF); | |
1769 | ||
1770 | if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) | |
1771 | return DAG.getTargetConstantPool(CP->getConstVal(), | |
1772 | CP->getValueType(0), | |
1773 | CP->getAlignment(), | |
1774 | CP->getOffset(), TF); | |
1775 | ||
1776 | if (const BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) | |
1777 | return DAG.getTargetBlockAddress(BA->getBlockAddress(), | |
1778 | Op.getValueType(), | |
1779 | 0, | |
1780 | TF); | |
1781 | ||
1782 | if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) | |
1783 | return DAG.getTargetExternalSymbol(ES->getSymbol(), | |
1784 | ES->getValueType(0), TF); | |
1785 | ||
1786 | llvm_unreachable("Unhandled address SDNode"); | |
1787 | } | |
1788 | ||
1789 | // Split Op into high and low parts according to HiTF and LoTF. | |
1790 | // Return an ADD node combining the parts. | |
1791 | SDValue SparcTargetLowering::makeHiLoPair(SDValue Op, | |
1792 | unsigned HiTF, unsigned LoTF, | |
1793 | SelectionDAG &DAG) const { | |
1794 | SDLoc DL(Op); | |
1795 | EVT VT = Op.getValueType(); | |
1796 | SDValue Hi = DAG.getNode(SPISD::Hi, DL, VT, withTargetFlags(Op, HiTF, DAG)); | |
1797 | SDValue Lo = DAG.getNode(SPISD::Lo, DL, VT, withTargetFlags(Op, LoTF, DAG)); | |
1798 | return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo); | |
1799 | } | |
223e47cc | 1800 | |
1a4d82fc JJ |
1801 | // Build SDNodes for producing an address from a GlobalAddress, ConstantPool, |
1802 | // or ExternalSymbol SDNode. | |
1803 | SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const { | |
1804 | SDLoc DL(Op); | |
1805 | EVT VT = getPointerTy(); | |
1806 | ||
1807 | // Handle PIC mode first. | |
1808 | if (getTargetMachine().getRelocationModel() == Reloc::PIC_) { | |
1809 | // This is the pic32 code model, the GOT is known to be smaller than 4GB. | |
1810 | SDValue HiLo = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_GOT22, | |
1811 | SparcMCExpr::VK_Sparc_GOT10, DAG); | |
1812 | SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, VT); | |
1813 | SDValue AbsAddr = DAG.getNode(ISD::ADD, DL, VT, GlobalBase, HiLo); | |
1814 | // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this | |
1815 | // function has calls. | |
1816 | MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); | |
1817 | MFI->setHasCalls(true); | |
1818 | return DAG.getLoad(VT, DL, DAG.getEntryNode(), AbsAddr, | |
1819 | MachinePointerInfo::getGOT(), false, false, false, 0); | |
1820 | } | |
223e47cc | 1821 | |
1a4d82fc JJ |
1822 | // This is one of the absolute code models. |
1823 | switch(getTargetMachine().getCodeModel()) { | |
1824 | default: | |
1825 | llvm_unreachable("Unsupported absolute code model"); | |
1826 | case CodeModel::Small: | |
1827 | // abs32. | |
1828 | return makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HI, | |
1829 | SparcMCExpr::VK_Sparc_LO, DAG); | |
1830 | case CodeModel::Medium: { | |
1831 | // abs44. | |
1832 | SDValue H44 = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_H44, | |
1833 | SparcMCExpr::VK_Sparc_M44, DAG); | |
1834 | H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, MVT::i32)); | |
1835 | SDValue L44 = withTargetFlags(Op, SparcMCExpr::VK_Sparc_L44, DAG); | |
1836 | L44 = DAG.getNode(SPISD::Lo, DL, VT, L44); | |
1837 | return DAG.getNode(ISD::ADD, DL, VT, H44, L44); | |
1838 | } | |
1839 | case CodeModel::Large: { | |
1840 | // abs64. | |
1841 | SDValue Hi = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HH, | |
1842 | SparcMCExpr::VK_Sparc_HM, DAG); | |
1843 | Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, MVT::i32)); | |
1844 | SDValue Lo = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HI, | |
1845 | SparcMCExpr::VK_Sparc_LO, DAG); | |
1846 | return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo); | |
1847 | } | |
1848 | } | |
1849 | } | |
1850 | ||
1851 | SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op, | |
1852 | SelectionDAG &DAG) const { | |
1853 | return makeAddress(Op, DAG); | |
223e47cc LB |
1854 | } |
1855 | ||
1856 | SDValue SparcTargetLowering::LowerConstantPool(SDValue Op, | |
1857 | SelectionDAG &DAG) const { | |
1a4d82fc JJ |
1858 | return makeAddress(Op, DAG); |
1859 | } | |
1860 | ||
1861 | SDValue SparcTargetLowering::LowerBlockAddress(SDValue Op, | |
1862 | SelectionDAG &DAG) const { | |
1863 | return makeAddress(Op, DAG); | |
1864 | } | |
1865 | ||
1866 | SDValue SparcTargetLowering::LowerGlobalTLSAddress(SDValue Op, | |
1867 | SelectionDAG &DAG) const { | |
1868 | ||
1869 | GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); | |
1870 | SDLoc DL(GA); | |
1871 | const GlobalValue *GV = GA->getGlobal(); | |
1872 | EVT PtrVT = getPointerTy(); | |
1873 | ||
1874 | TLSModel::Model model = getTargetMachine().getTLSModel(GV); | |
1875 | ||
1876 | if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { | |
1877 | unsigned HiTF = ((model == TLSModel::GeneralDynamic) | |
1878 | ? SparcMCExpr::VK_Sparc_TLS_GD_HI22 | |
1879 | : SparcMCExpr::VK_Sparc_TLS_LDM_HI22); | |
1880 | unsigned LoTF = ((model == TLSModel::GeneralDynamic) | |
1881 | ? SparcMCExpr::VK_Sparc_TLS_GD_LO10 | |
1882 | : SparcMCExpr::VK_Sparc_TLS_LDM_LO10); | |
1883 | unsigned addTF = ((model == TLSModel::GeneralDynamic) | |
1884 | ? SparcMCExpr::VK_Sparc_TLS_GD_ADD | |
1885 | : SparcMCExpr::VK_Sparc_TLS_LDM_ADD); | |
1886 | unsigned callTF = ((model == TLSModel::GeneralDynamic) | |
1887 | ? SparcMCExpr::VK_Sparc_TLS_GD_CALL | |
1888 | : SparcMCExpr::VK_Sparc_TLS_LDM_CALL); | |
1889 | ||
1890 | SDValue HiLo = makeHiLoPair(Op, HiTF, LoTF, DAG); | |
1891 | SDValue Base = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, PtrVT); | |
1892 | SDValue Argument = DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, Base, HiLo, | |
1893 | withTargetFlags(Op, addTF, DAG)); | |
1894 | ||
1895 | SDValue Chain = DAG.getEntryNode(); | |
1896 | SDValue InFlag; | |
1897 | ||
1898 | Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(1, true), DL); | |
1899 | Chain = DAG.getCopyToReg(Chain, DL, SP::O0, Argument, InFlag); | |
1900 | InFlag = Chain.getValue(1); | |
1901 | SDValue Callee = DAG.getTargetExternalSymbol("__tls_get_addr", PtrVT); | |
1902 | SDValue Symbol = withTargetFlags(Op, callTF, DAG); | |
1903 | ||
1904 | SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); | |
1905 | SmallVector<SDValue, 4> Ops; | |
1906 | Ops.push_back(Chain); | |
1907 | Ops.push_back(Callee); | |
1908 | Ops.push_back(Symbol); | |
1909 | Ops.push_back(DAG.getRegister(SP::O0, PtrVT)); | |
1910 | const uint32_t *Mask = getTargetMachine() | |
1911 | .getSubtargetImpl() | |
1912 | ->getRegisterInfo() | |
1913 | ->getCallPreservedMask(CallingConv::C); | |
1914 | assert(Mask && "Missing call preserved mask for calling convention"); | |
1915 | Ops.push_back(DAG.getRegisterMask(Mask)); | |
1916 | Ops.push_back(InFlag); | |
1917 | Chain = DAG.getNode(SPISD::TLS_CALL, DL, NodeTys, Ops); | |
1918 | InFlag = Chain.getValue(1); | |
1919 | Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(1, true), | |
1920 | DAG.getIntPtrConstant(0, true), InFlag, DL); | |
1921 | InFlag = Chain.getValue(1); | |
1922 | SDValue Ret = DAG.getCopyFromReg(Chain, DL, SP::O0, PtrVT, InFlag); | |
1923 | ||
1924 | if (model != TLSModel::LocalDynamic) | |
1925 | return Ret; | |
1926 | ||
1927 | SDValue Hi = DAG.getNode(SPISD::Hi, DL, PtrVT, | |
1928 | withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LDO_HIX22, DAG)); | |
1929 | SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT, | |
1930 | withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LDO_LOX10, DAG)); | |
1931 | HiLo = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo); | |
1932 | return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, Ret, HiLo, | |
1933 | withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LDO_ADD, DAG)); | |
1934 | } | |
1935 | ||
1936 | if (model == TLSModel::InitialExec) { | |
1937 | unsigned ldTF = ((PtrVT == MVT::i64)? SparcMCExpr::VK_Sparc_TLS_IE_LDX | |
1938 | : SparcMCExpr::VK_Sparc_TLS_IE_LD); | |
1939 | ||
1940 | SDValue Base = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, PtrVT); | |
1941 | ||
1942 | // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this | |
1943 | // function has calls. | |
1944 | MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); | |
1945 | MFI->setHasCalls(true); | |
1946 | ||
1947 | SDValue TGA = makeHiLoPair(Op, | |
1948 | SparcMCExpr::VK_Sparc_TLS_IE_HI22, | |
1949 | SparcMCExpr::VK_Sparc_TLS_IE_LO10, DAG); | |
1950 | SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Base, TGA); | |
1951 | SDValue Offset = DAG.getNode(SPISD::TLS_LD, | |
1952 | DL, PtrVT, Ptr, | |
1953 | withTargetFlags(Op, ldTF, DAG)); | |
1954 | return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, | |
1955 | DAG.getRegister(SP::G7, PtrVT), Offset, | |
1956 | withTargetFlags(Op, | |
1957 | SparcMCExpr::VK_Sparc_TLS_IE_ADD, DAG)); | |
1958 | } | |
1959 | ||
1960 | assert(model == TLSModel::LocalExec); | |
1961 | SDValue Hi = DAG.getNode(SPISD::Hi, DL, PtrVT, | |
1962 | withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LE_HIX22, DAG)); | |
1963 | SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT, | |
1964 | withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LE_LOX10, DAG)); | |
1965 | SDValue Offset = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo); | |
1966 | ||
1967 | return DAG.getNode(ISD::ADD, DL, PtrVT, | |
1968 | DAG.getRegister(SP::G7, PtrVT), Offset); | |
1969 | } | |
1970 | ||
1971 | SDValue | |
1972 | SparcTargetLowering::LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args, | |
1973 | SDValue Arg, SDLoc DL, | |
1974 | SelectionDAG &DAG) const { | |
1975 | MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); | |
1976 | EVT ArgVT = Arg.getValueType(); | |
1977 | Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); | |
1978 | ||
1979 | ArgListEntry Entry; | |
1980 | Entry.Node = Arg; | |
1981 | Entry.Ty = ArgTy; | |
1982 | ||
1983 | if (ArgTy->isFP128Ty()) { | |
1984 | // Create a stack object and pass the pointer to the library function. | |
1985 | int FI = MFI->CreateStackObject(16, 8, false); | |
1986 | SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); | |
1987 | Chain = DAG.getStore(Chain, | |
1988 | DL, | |
1989 | Entry.Node, | |
1990 | FIPtr, | |
1991 | MachinePointerInfo(), | |
1992 | false, | |
1993 | false, | |
1994 | 8); | |
1995 | ||
1996 | Entry.Node = FIPtr; | |
1997 | Entry.Ty = PointerType::getUnqual(ArgTy); | |
1998 | } | |
1999 | Args.push_back(Entry); | |
2000 | return Chain; | |
2001 | } | |
2002 | ||
2003 | SDValue | |
2004 | SparcTargetLowering::LowerF128Op(SDValue Op, SelectionDAG &DAG, | |
2005 | const char *LibFuncName, | |
2006 | unsigned numArgs) const { | |
2007 | ||
2008 | ArgListTy Args; | |
2009 | ||
2010 | MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); | |
2011 | ||
2012 | SDValue Callee = DAG.getExternalSymbol(LibFuncName, getPointerTy()); | |
2013 | Type *RetTy = Op.getValueType().getTypeForEVT(*DAG.getContext()); | |
2014 | Type *RetTyABI = RetTy; | |
2015 | SDValue Chain = DAG.getEntryNode(); | |
2016 | SDValue RetPtr; | |
2017 | ||
2018 | if (RetTy->isFP128Ty()) { | |
2019 | // Create a Stack Object to receive the return value of type f128. | |
2020 | ArgListEntry Entry; | |
2021 | int RetFI = MFI->CreateStackObject(16, 8, false); | |
2022 | RetPtr = DAG.getFrameIndex(RetFI, getPointerTy()); | |
2023 | Entry.Node = RetPtr; | |
2024 | Entry.Ty = PointerType::getUnqual(RetTy); | |
2025 | if (!Subtarget->is64Bit()) | |
2026 | Entry.isSRet = true; | |
2027 | Entry.isReturned = false; | |
2028 | Args.push_back(Entry); | |
2029 | RetTyABI = Type::getVoidTy(*DAG.getContext()); | |
2030 | } | |
2031 | ||
2032 | assert(Op->getNumOperands() >= numArgs && "Not enough operands!"); | |
2033 | for (unsigned i = 0, e = numArgs; i != e; ++i) { | |
2034 | Chain = LowerF128_LibCallArg(Chain, Args, Op.getOperand(i), SDLoc(Op), DAG); | |
2035 | } | |
2036 | TargetLowering::CallLoweringInfo CLI(DAG); | |
2037 | CLI.setDebugLoc(SDLoc(Op)).setChain(Chain) | |
2038 | .setCallee(CallingConv::C, RetTyABI, Callee, std::move(Args), 0); | |
2039 | ||
2040 | std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI); | |
2041 | ||
2042 | // chain is in second result. | |
2043 | if (RetTyABI == RetTy) | |
2044 | return CallInfo.first; | |
2045 | ||
2046 | assert (RetTy->isFP128Ty() && "Unexpected return type!"); | |
2047 | ||
2048 | Chain = CallInfo.second; | |
2049 | ||
2050 | // Load RetPtr to get the return value. | |
2051 | return DAG.getLoad(Op.getValueType(), | |
2052 | SDLoc(Op), | |
2053 | Chain, | |
2054 | RetPtr, | |
2055 | MachinePointerInfo(), | |
2056 | false, false, false, 8); | |
2057 | } | |
2058 | ||
2059 | SDValue | |
2060 | SparcTargetLowering::LowerF128Compare(SDValue LHS, SDValue RHS, | |
2061 | unsigned &SPCC, | |
2062 | SDLoc DL, | |
2063 | SelectionDAG &DAG) const { | |
2064 | ||
2065 | const char *LibCall = nullptr; | |
2066 | bool is64Bit = Subtarget->is64Bit(); | |
2067 | switch(SPCC) { | |
2068 | default: llvm_unreachable("Unhandled conditional code!"); | |
2069 | case SPCC::FCC_E : LibCall = is64Bit? "_Qp_feq" : "_Q_feq"; break; | |
2070 | case SPCC::FCC_NE : LibCall = is64Bit? "_Qp_fne" : "_Q_fne"; break; | |
2071 | case SPCC::FCC_L : LibCall = is64Bit? "_Qp_flt" : "_Q_flt"; break; | |
2072 | case SPCC::FCC_G : LibCall = is64Bit? "_Qp_fgt" : "_Q_fgt"; break; | |
2073 | case SPCC::FCC_LE : LibCall = is64Bit? "_Qp_fle" : "_Q_fle"; break; | |
2074 | case SPCC::FCC_GE : LibCall = is64Bit? "_Qp_fge" : "_Q_fge"; break; | |
2075 | case SPCC::FCC_UL : | |
2076 | case SPCC::FCC_ULE: | |
2077 | case SPCC::FCC_UG : | |
2078 | case SPCC::FCC_UGE: | |
2079 | case SPCC::FCC_U : | |
2080 | case SPCC::FCC_O : | |
2081 | case SPCC::FCC_LG : | |
2082 | case SPCC::FCC_UE : LibCall = is64Bit? "_Qp_cmp" : "_Q_cmp"; break; | |
2083 | } | |
2084 | ||
2085 | SDValue Callee = DAG.getExternalSymbol(LibCall, getPointerTy()); | |
2086 | Type *RetTy = Type::getInt32Ty(*DAG.getContext()); | |
2087 | ArgListTy Args; | |
2088 | SDValue Chain = DAG.getEntryNode(); | |
2089 | Chain = LowerF128_LibCallArg(Chain, Args, LHS, DL, DAG); | |
2090 | Chain = LowerF128_LibCallArg(Chain, Args, RHS, DL, DAG); | |
2091 | ||
2092 | TargetLowering::CallLoweringInfo CLI(DAG); | |
2093 | CLI.setDebugLoc(DL).setChain(Chain) | |
2094 | .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0); | |
2095 | ||
2096 | std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI); | |
2097 | ||
2098 | // result is in first, and chain is in second result. | |
2099 | SDValue Result = CallInfo.first; | |
2100 | ||
2101 | switch(SPCC) { | |
2102 | default: { | |
2103 | SDValue RHS = DAG.getTargetConstant(0, Result.getValueType()); | |
2104 | SPCC = SPCC::ICC_NE; | |
2105 | return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); | |
2106 | } | |
2107 | case SPCC::FCC_UL : { | |
2108 | SDValue Mask = DAG.getTargetConstant(1, Result.getValueType()); | |
2109 | Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask); | |
2110 | SDValue RHS = DAG.getTargetConstant(0, Result.getValueType()); | |
2111 | SPCC = SPCC::ICC_NE; | |
2112 | return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); | |
2113 | } | |
2114 | case SPCC::FCC_ULE: { | |
2115 | SDValue RHS = DAG.getTargetConstant(2, Result.getValueType()); | |
2116 | SPCC = SPCC::ICC_NE; | |
2117 | return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); | |
2118 | } | |
2119 | case SPCC::FCC_UG : { | |
2120 | SDValue RHS = DAG.getTargetConstant(1, Result.getValueType()); | |
2121 | SPCC = SPCC::ICC_G; | |
2122 | return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); | |
2123 | } | |
2124 | case SPCC::FCC_UGE: { | |
2125 | SDValue RHS = DAG.getTargetConstant(1, Result.getValueType()); | |
2126 | SPCC = SPCC::ICC_NE; | |
2127 | return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); | |
2128 | } | |
2129 | ||
2130 | case SPCC::FCC_U : { | |
2131 | SDValue RHS = DAG.getTargetConstant(3, Result.getValueType()); | |
2132 | SPCC = SPCC::ICC_E; | |
2133 | return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); | |
2134 | } | |
2135 | case SPCC::FCC_O : { | |
2136 | SDValue RHS = DAG.getTargetConstant(3, Result.getValueType()); | |
2137 | SPCC = SPCC::ICC_NE; | |
2138 | return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); | |
2139 | } | |
2140 | case SPCC::FCC_LG : { | |
2141 | SDValue Mask = DAG.getTargetConstant(3, Result.getValueType()); | |
2142 | Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask); | |
2143 | SDValue RHS = DAG.getTargetConstant(0, Result.getValueType()); | |
2144 | SPCC = SPCC::ICC_NE; | |
2145 | return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); | |
2146 | } | |
2147 | case SPCC::FCC_UE : { | |
2148 | SDValue Mask = DAG.getTargetConstant(3, Result.getValueType()); | |
2149 | Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask); | |
2150 | SDValue RHS = DAG.getTargetConstant(0, Result.getValueType()); | |
2151 | SPCC = SPCC::ICC_E; | |
2152 | return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); | |
2153 | } | |
2154 | } | |
2155 | } | |
2156 | ||
2157 | static SDValue | |
2158 | LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG, | |
2159 | const SparcTargetLowering &TLI) { | |
2160 | ||
2161 | if (Op.getOperand(0).getValueType() == MVT::f64) | |
2162 | return TLI.LowerF128Op(Op, DAG, | |
2163 | TLI.getLibcallName(RTLIB::FPEXT_F64_F128), 1); | |
2164 | ||
2165 | if (Op.getOperand(0).getValueType() == MVT::f32) | |
2166 | return TLI.LowerF128Op(Op, DAG, | |
2167 | TLI.getLibcallName(RTLIB::FPEXT_F32_F128), 1); | |
2168 | ||
2169 | llvm_unreachable("fpextend with non-float operand!"); | |
2170 | return SDValue(); | |
2171 | } | |
2172 | ||
2173 | static SDValue | |
2174 | LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG, | |
2175 | const SparcTargetLowering &TLI) { | |
2176 | // FP_ROUND on f64 and f32 are legal. | |
2177 | if (Op.getOperand(0).getValueType() != MVT::f128) | |
2178 | return Op; | |
2179 | ||
2180 | if (Op.getValueType() == MVT::f64) | |
2181 | return TLI.LowerF128Op(Op, DAG, | |
2182 | TLI.getLibcallName(RTLIB::FPROUND_F128_F64), 1); | |
2183 | if (Op.getValueType() == MVT::f32) | |
2184 | return TLI.LowerF128Op(Op, DAG, | |
2185 | TLI.getLibcallName(RTLIB::FPROUND_F128_F32), 1); | |
2186 | ||
2187 | llvm_unreachable("fpround to non-float!"); | |
2188 | return SDValue(); | |
2189 | } | |
2190 | ||
2191 | static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG, | |
2192 | const SparcTargetLowering &TLI, | |
2193 | bool hasHardQuad) { | |
2194 | SDLoc dl(Op); | |
2195 | EVT VT = Op.getValueType(); | |
2196 | assert(VT == MVT::i32 || VT == MVT::i64); | |
2197 | ||
2198 | // Expand f128 operations to fp128 abi calls. | |
2199 | if (Op.getOperand(0).getValueType() == MVT::f128 | |
2200 | && (!hasHardQuad || !TLI.isTypeLegal(VT))) { | |
2201 | const char *libName = TLI.getLibcallName(VT == MVT::i32 | |
2202 | ? RTLIB::FPTOSINT_F128_I32 | |
2203 | : RTLIB::FPTOSINT_F128_I64); | |
2204 | return TLI.LowerF128Op(Op, DAG, libName, 1); | |
2205 | } | |
2206 | ||
2207 | // Expand if the resulting type is illegal. | |
2208 | if (!TLI.isTypeLegal(VT)) | |
2209 | return SDValue(); | |
2210 | ||
2211 | // Otherwise, Convert the fp value to integer in an FP register. | |
2212 | if (VT == MVT::i32) | |
2213 | Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0)); | |
2214 | else | |
2215 | Op = DAG.getNode(SPISD::FTOX, dl, MVT::f64, Op.getOperand(0)); | |
2216 | ||
2217 | return DAG.getNode(ISD::BITCAST, dl, VT, Op); | |
2218 | } | |
2219 | ||
2220 | static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG, | |
2221 | const SparcTargetLowering &TLI, | |
2222 | bool hasHardQuad) { | |
2223 | SDLoc dl(Op); | |
2224 | EVT OpVT = Op.getOperand(0).getValueType(); | |
2225 | assert(OpVT == MVT::i32 || (OpVT == MVT::i64)); | |
2226 | ||
2227 | EVT floatVT = (OpVT == MVT::i32) ? MVT::f32 : MVT::f64; | |
2228 | ||
2229 | // Expand f128 operations to fp128 ABI calls. | |
2230 | if (Op.getValueType() == MVT::f128 | |
2231 | && (!hasHardQuad || !TLI.isTypeLegal(OpVT))) { | |
2232 | const char *libName = TLI.getLibcallName(OpVT == MVT::i32 | |
2233 | ? RTLIB::SINTTOFP_I32_F128 | |
2234 | : RTLIB::SINTTOFP_I64_F128); | |
2235 | return TLI.LowerF128Op(Op, DAG, libName, 1); | |
2236 | } | |
2237 | ||
2238 | // Expand if the operand type is illegal. | |
2239 | if (!TLI.isTypeLegal(OpVT)) | |
2240 | return SDValue(); | |
2241 | ||
2242 | // Otherwise, Convert the int value to FP in an FP register. | |
2243 | SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, floatVT, Op.getOperand(0)); | |
2244 | unsigned opcode = (OpVT == MVT::i32)? SPISD::ITOF : SPISD::XTOF; | |
2245 | return DAG.getNode(opcode, dl, Op.getValueType(), Tmp); | |
2246 | } | |
2247 | ||
2248 | static SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG, | |
2249 | const SparcTargetLowering &TLI, | |
2250 | bool hasHardQuad) { | |
2251 | SDLoc dl(Op); | |
2252 | EVT VT = Op.getValueType(); | |
2253 | ||
2254 | // Expand if it does not involve f128 or the target has support for | |
2255 | // quad floating point instructions and the resulting type is legal. | |
2256 | if (Op.getOperand(0).getValueType() != MVT::f128 || | |
2257 | (hasHardQuad && TLI.isTypeLegal(VT))) | |
2258 | return SDValue(); | |
2259 | ||
2260 | assert(VT == MVT::i32 || VT == MVT::i64); | |
2261 | ||
2262 | return TLI.LowerF128Op(Op, DAG, | |
2263 | TLI.getLibcallName(VT == MVT::i32 | |
2264 | ? RTLIB::FPTOUINT_F128_I32 | |
2265 | : RTLIB::FPTOUINT_F128_I64), | |
2266 | 1); | |
2267 | } | |
2268 | ||
2269 | static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG, | |
2270 | const SparcTargetLowering &TLI, | |
2271 | bool hasHardQuad) { | |
2272 | SDLoc dl(Op); | |
2273 | EVT OpVT = Op.getOperand(0).getValueType(); | |
2274 | assert(OpVT == MVT::i32 || OpVT == MVT::i64); | |
2275 | ||
2276 | // Expand if it does not involve f128 or the target has support for | |
2277 | // quad floating point instructions and the operand type is legal. | |
2278 | if (Op.getValueType() != MVT::f128 || (hasHardQuad && TLI.isTypeLegal(OpVT))) | |
2279 | return SDValue(); | |
2280 | ||
2281 | return TLI.LowerF128Op(Op, DAG, | |
2282 | TLI.getLibcallName(OpVT == MVT::i32 | |
2283 | ? RTLIB::UINTTOFP_I32_F128 | |
2284 | : RTLIB::UINTTOFP_I64_F128), | |
2285 | 1); | |
2286 | } | |
2287 | ||
2288 | static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG, | |
2289 | const SparcTargetLowering &TLI, | |
2290 | bool hasHardQuad) { | |
223e47cc LB |
2291 | SDValue Chain = Op.getOperand(0); |
2292 | ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); | |
2293 | SDValue LHS = Op.getOperand(2); | |
2294 | SDValue RHS = Op.getOperand(3); | |
2295 | SDValue Dest = Op.getOperand(4); | |
1a4d82fc | 2296 | SDLoc dl(Op); |
223e47cc LB |
2297 | unsigned Opc, SPCC = ~0U; |
2298 | ||
2299 | // If this is a br_cc of a "setcc", and if the setcc got lowered into | |
2300 | // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. | |
2301 | LookThroughSetCC(LHS, RHS, CC, SPCC); | |
2302 | ||
2303 | // Get the condition flag. | |
2304 | SDValue CompareFlag; | |
1a4d82fc JJ |
2305 | if (LHS.getValueType().isInteger()) { |
2306 | CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS); | |
223e47cc | 2307 | if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); |
1a4d82fc JJ |
2308 | // 32-bit compares use the icc flags, 64-bit uses the xcc flags. |
2309 | Opc = LHS.getValueType() == MVT::i32 ? SPISD::BRICC : SPISD::BRXCC; | |
223e47cc | 2310 | } else { |
1a4d82fc JJ |
2311 | if (!hasHardQuad && LHS.getValueType() == MVT::f128) { |
2312 | if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); | |
2313 | CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG); | |
2314 | Opc = SPISD::BRICC; | |
2315 | } else { | |
2316 | CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS); | |
2317 | if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); | |
2318 | Opc = SPISD::BRFCC; | |
2319 | } | |
223e47cc LB |
2320 | } |
2321 | return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest, | |
2322 | DAG.getConstant(SPCC, MVT::i32), CompareFlag); | |
2323 | } | |
2324 | ||
1a4d82fc JJ |
2325 | static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, |
2326 | const SparcTargetLowering &TLI, | |
2327 | bool hasHardQuad) { | |
223e47cc LB |
2328 | SDValue LHS = Op.getOperand(0); |
2329 | SDValue RHS = Op.getOperand(1); | |
2330 | ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); | |
2331 | SDValue TrueVal = Op.getOperand(2); | |
2332 | SDValue FalseVal = Op.getOperand(3); | |
1a4d82fc | 2333 | SDLoc dl(Op); |
223e47cc LB |
2334 | unsigned Opc, SPCC = ~0U; |
2335 | ||
2336 | // If this is a select_cc of a "setcc", and if the setcc got lowered into | |
2337 | // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. | |
2338 | LookThroughSetCC(LHS, RHS, CC, SPCC); | |
2339 | ||
2340 | SDValue CompareFlag; | |
1a4d82fc JJ |
2341 | if (LHS.getValueType().isInteger()) { |
2342 | CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS); | |
2343 | Opc = LHS.getValueType() == MVT::i32 ? | |
2344 | SPISD::SELECT_ICC : SPISD::SELECT_XCC; | |
223e47cc LB |
2345 | if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); |
2346 | } else { | |
1a4d82fc JJ |
2347 | if (!hasHardQuad && LHS.getValueType() == MVT::f128) { |
2348 | if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); | |
2349 | CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG); | |
2350 | Opc = SPISD::SELECT_ICC; | |
2351 | } else { | |
2352 | CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS); | |
2353 | Opc = SPISD::SELECT_FCC; | |
2354 | if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); | |
2355 | } | |
223e47cc LB |
2356 | } |
2357 | return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal, | |
2358 | DAG.getConstant(SPCC, MVT::i32), CompareFlag); | |
2359 | } | |
2360 | ||
2361 | static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, | |
2362 | const SparcTargetLowering &TLI) { | |
2363 | MachineFunction &MF = DAG.getMachineFunction(); | |
2364 | SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>(); | |
2365 | ||
1a4d82fc JJ |
2366 | // Need frame address to find the address of VarArgsFrameIndex. |
2367 | MF.getFrameInfo()->setFrameAddressIsTaken(true); | |
2368 | ||
223e47cc LB |
2369 | // vastart just stores the address of the VarArgsFrameIndex slot into the |
2370 | // memory location argument. | |
1a4d82fc | 2371 | SDLoc DL(Op); |
223e47cc | 2372 | SDValue Offset = |
1a4d82fc JJ |
2373 | DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), |
2374 | DAG.getRegister(SP::I6, TLI.getPointerTy()), | |
2375 | DAG.getIntPtrConstant(FuncInfo->getVarArgsFrameOffset())); | |
223e47cc | 2376 | const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); |
1a4d82fc | 2377 | return DAG.getStore(Op.getOperand(0), DL, Offset, Op.getOperand(1), |
223e47cc LB |
2378 | MachinePointerInfo(SV), false, false, 0); |
2379 | } | |
2380 | ||
2381 | static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) { | |
2382 | SDNode *Node = Op.getNode(); | |
2383 | EVT VT = Node->getValueType(0); | |
2384 | SDValue InChain = Node->getOperand(0); | |
2385 | SDValue VAListPtr = Node->getOperand(1); | |
1a4d82fc | 2386 | EVT PtrVT = VAListPtr.getValueType(); |
223e47cc | 2387 | const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); |
1a4d82fc JJ |
2388 | SDLoc DL(Node); |
2389 | SDValue VAList = DAG.getLoad(PtrVT, DL, InChain, VAListPtr, | |
223e47cc | 2390 | MachinePointerInfo(SV), false, false, false, 0); |
1a4d82fc JJ |
2391 | // Increment the pointer, VAList, to the next vaarg. |
2392 | SDValue NextPtr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList, | |
2393 | DAG.getIntPtrConstant(VT.getSizeInBits()/8)); | |
2394 | // Store the incremented VAList to the legalized pointer. | |
2395 | InChain = DAG.getStore(VAList.getValue(1), DL, NextPtr, | |
223e47cc | 2396 | VAListPtr, MachinePointerInfo(SV), false, false, 0); |
1a4d82fc JJ |
2397 | // Load the actual argument out of the pointer VAList. |
2398 | // We can't count on greater alignment than the word size. | |
2399 | return DAG.getLoad(VT, DL, InChain, VAList, MachinePointerInfo(), | |
2400 | false, false, false, | |
2401 | std::min(PtrVT.getSizeInBits(), VT.getSizeInBits())/8); | |
223e47cc LB |
2402 | } |
2403 | ||
1a4d82fc JJ |
2404 | static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, |
2405 | const SparcSubtarget *Subtarget) { | |
223e47cc LB |
2406 | SDValue Chain = Op.getOperand(0); // Legalize the chain. |
2407 | SDValue Size = Op.getOperand(1); // Legalize the size. | |
1a4d82fc JJ |
2408 | EVT VT = Size->getValueType(0); |
2409 | SDLoc dl(Op); | |
223e47cc LB |
2410 | |
2411 | unsigned SPReg = SP::O6; | |
1a4d82fc JJ |
2412 | SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); |
2413 | SDValue NewSP = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value | |
223e47cc LB |
2414 | Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain |
2415 | ||
2416 | // The resultant pointer is actually 16 words from the bottom of the stack, | |
2417 | // to provide a register spill area. | |
1a4d82fc JJ |
2418 | unsigned regSpillArea = Subtarget->is64Bit() ? 128 : 96; |
2419 | regSpillArea += Subtarget->getStackPointerBias(); | |
2420 | ||
2421 | SDValue NewVal = DAG.getNode(ISD::ADD, dl, VT, NewSP, | |
2422 | DAG.getConstant(regSpillArea, VT)); | |
223e47cc | 2423 | SDValue Ops[2] = { NewVal, Chain }; |
1a4d82fc | 2424 | return DAG.getMergeValues(Ops, dl); |
223e47cc LB |
2425 | } |
2426 | ||
2427 | ||
2428 | static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG) { | |
1a4d82fc | 2429 | SDLoc dl(Op); |
223e47cc LB |
2430 | SDValue Chain = DAG.getNode(SPISD::FLUSHW, |
2431 | dl, MVT::Other, DAG.getEntryNode()); | |
2432 | return Chain; | |
2433 | } | |
2434 | ||
1a4d82fc JJ |
2435 | static SDValue getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG, |
2436 | const SparcSubtarget *Subtarget) { | |
223e47cc LB |
2437 | MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); |
2438 | MFI->setFrameAddressIsTaken(true); | |
2439 | ||
2440 | EVT VT = Op.getValueType(); | |
1a4d82fc | 2441 | SDLoc dl(Op); |
223e47cc | 2442 | unsigned FrameReg = SP::I6; |
1a4d82fc | 2443 | unsigned stackBias = Subtarget->getStackPointerBias(); |
223e47cc LB |
2444 | |
2445 | SDValue FrameAddr; | |
1a4d82fc JJ |
2446 | |
2447 | if (depth == 0) { | |
223e47cc | 2448 | FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); |
1a4d82fc JJ |
2449 | if (Subtarget->is64Bit()) |
2450 | FrameAddr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr, | |
2451 | DAG.getIntPtrConstant(stackBias)); | |
2452 | return FrameAddr; | |
223e47cc | 2453 | } |
1a4d82fc JJ |
2454 | |
2455 | // flush first to make sure the windowed registers' values are in stack | |
2456 | SDValue Chain = getFLUSHW(Op, DAG); | |
2457 | FrameAddr = DAG.getCopyFromReg(Chain, dl, FrameReg, VT); | |
2458 | ||
2459 | unsigned Offset = (Subtarget->is64Bit()) ? (stackBias + 112) : 56; | |
2460 | ||
2461 | while (depth--) { | |
2462 | SDValue Ptr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr, | |
2463 | DAG.getIntPtrConstant(Offset)); | |
2464 | FrameAddr = DAG.getLoad(VT, dl, Chain, Ptr, MachinePointerInfo(), | |
2465 | false, false, false, 0); | |
2466 | } | |
2467 | if (Subtarget->is64Bit()) | |
2468 | FrameAddr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr, | |
2469 | DAG.getIntPtrConstant(stackBias)); | |
223e47cc LB |
2470 | return FrameAddr; |
2471 | } | |
2472 | ||
1a4d82fc JJ |
2473 | |
2474 | static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, | |
2475 | const SparcSubtarget *Subtarget) { | |
2476 | ||
2477 | uint64_t depth = Op.getConstantOperandVal(0); | |
2478 | ||
2479 | return getFRAMEADDR(depth, Op, DAG, Subtarget); | |
2480 | ||
2481 | } | |
2482 | ||
2483 | static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, | |
2484 | const SparcTargetLowering &TLI, | |
2485 | const SparcSubtarget *Subtarget) { | |
2486 | MachineFunction &MF = DAG.getMachineFunction(); | |
2487 | MachineFrameInfo *MFI = MF.getFrameInfo(); | |
223e47cc LB |
2488 | MFI->setReturnAddressIsTaken(true); |
2489 | ||
1a4d82fc JJ |
2490 | if (TLI.verifyReturnAddressArgumentIsConstant(Op, DAG)) |
2491 | return SDValue(); | |
223e47cc | 2492 | |
1a4d82fc JJ |
2493 | EVT VT = Op.getValueType(); |
2494 | SDLoc dl(Op); | |
223e47cc LB |
2495 | uint64_t depth = Op.getConstantOperandVal(0); |
2496 | ||
2497 | SDValue RetAddr; | |
1a4d82fc JJ |
2498 | if (depth == 0) { |
2499 | unsigned RetReg = MF.addLiveIn(SP::I7, | |
2500 | TLI.getRegClassFor(TLI.getPointerTy())); | |
223e47cc | 2501 | RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT); |
1a4d82fc | 2502 | return RetAddr; |
223e47cc | 2503 | } |
1a4d82fc JJ |
2504 | |
2505 | // Need frame address to find return address of the caller. | |
2506 | SDValue FrameAddr = getFRAMEADDR(depth - 1, Op, DAG, Subtarget); | |
2507 | ||
2508 | unsigned Offset = (Subtarget->is64Bit()) ? 120 : 60; | |
2509 | SDValue Ptr = DAG.getNode(ISD::ADD, | |
2510 | dl, VT, | |
2511 | FrameAddr, | |
2512 | DAG.getIntPtrConstant(Offset)); | |
2513 | RetAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), Ptr, | |
2514 | MachinePointerInfo(), false, false, false, 0); | |
2515 | ||
223e47cc LB |
2516 | return RetAddr; |
2517 | } | |
2518 | ||
1a4d82fc JJ |
2519 | static SDValue LowerF64Op(SDValue Op, SelectionDAG &DAG, unsigned opcode) |
2520 | { | |
2521 | SDLoc dl(Op); | |
2522 | ||
2523 | assert(Op.getValueType() == MVT::f64 && "LowerF64Op called on non-double!"); | |
2524 | assert(opcode == ISD::FNEG || opcode == ISD::FABS); | |
2525 | ||
2526 | // Lower fneg/fabs on f64 to fneg/fabs on f32. | |
2527 | // fneg f64 => fneg f32:sub_even, fmov f32:sub_odd. | |
2528 | // fabs f64 => fabs f32:sub_even, fmov f32:sub_odd. | |
2529 | ||
2530 | SDValue SrcReg64 = Op.getOperand(0); | |
2531 | SDValue Hi32 = DAG.getTargetExtractSubreg(SP::sub_even, dl, MVT::f32, | |
2532 | SrcReg64); | |
2533 | SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32, | |
2534 | SrcReg64); | |
2535 | ||
2536 | Hi32 = DAG.getNode(opcode, dl, MVT::f32, Hi32); | |
2537 | ||
2538 | SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, | |
2539 | dl, MVT::f64), 0); | |
2540 | DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64, | |
2541 | DstReg64, Hi32); | |
2542 | DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64, | |
2543 | DstReg64, Lo32); | |
2544 | return DstReg64; | |
2545 | } | |
2546 | ||
2547 | // Lower a f128 load into two f64 loads. | |
2548 | static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG) | |
2549 | { | |
2550 | SDLoc dl(Op); | |
2551 | LoadSDNode *LdNode = dyn_cast<LoadSDNode>(Op.getNode()); | |
2552 | assert(LdNode && LdNode->getOffset().getOpcode() == ISD::UNDEF | |
2553 | && "Unexpected node type"); | |
2554 | ||
2555 | unsigned alignment = LdNode->getAlignment(); | |
2556 | if (alignment > 8) | |
2557 | alignment = 8; | |
2558 | ||
2559 | SDValue Hi64 = DAG.getLoad(MVT::f64, | |
2560 | dl, | |
2561 | LdNode->getChain(), | |
2562 | LdNode->getBasePtr(), | |
2563 | LdNode->getPointerInfo(), | |
2564 | false, false, false, alignment); | |
2565 | EVT addrVT = LdNode->getBasePtr().getValueType(); | |
2566 | SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT, | |
2567 | LdNode->getBasePtr(), | |
2568 | DAG.getConstant(8, addrVT)); | |
2569 | SDValue Lo64 = DAG.getLoad(MVT::f64, | |
2570 | dl, | |
2571 | LdNode->getChain(), | |
2572 | LoPtr, | |
2573 | LdNode->getPointerInfo(), | |
2574 | false, false, false, alignment); | |
2575 | ||
2576 | SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, MVT::i32); | |
2577 | SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, MVT::i32); | |
2578 | ||
2579 | SDNode *InFP128 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, | |
2580 | dl, MVT::f128); | |
2581 | InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, | |
2582 | MVT::f128, | |
2583 | SDValue(InFP128, 0), | |
2584 | Hi64, | |
2585 | SubRegEven); | |
2586 | InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, | |
2587 | MVT::f128, | |
2588 | SDValue(InFP128, 0), | |
2589 | Lo64, | |
2590 | SubRegOdd); | |
2591 | SDValue OutChains[2] = { SDValue(Hi64.getNode(), 1), | |
2592 | SDValue(Lo64.getNode(), 1) }; | |
2593 | SDValue OutChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains); | |
2594 | SDValue Ops[2] = {SDValue(InFP128,0), OutChain}; | |
2595 | return DAG.getMergeValues(Ops, dl); | |
2596 | } | |
2597 | ||
2598 | // Lower a f128 store into two f64 stores. | |
2599 | static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG) { | |
2600 | SDLoc dl(Op); | |
2601 | StoreSDNode *StNode = dyn_cast<StoreSDNode>(Op.getNode()); | |
2602 | assert(StNode && StNode->getOffset().getOpcode() == ISD::UNDEF | |
2603 | && "Unexpected node type"); | |
2604 | SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, MVT::i32); | |
2605 | SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, MVT::i32); | |
2606 | ||
2607 | SDNode *Hi64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, | |
2608 | dl, | |
2609 | MVT::f64, | |
2610 | StNode->getValue(), | |
2611 | SubRegEven); | |
2612 | SDNode *Lo64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, | |
2613 | dl, | |
2614 | MVT::f64, | |
2615 | StNode->getValue(), | |
2616 | SubRegOdd); | |
2617 | ||
2618 | unsigned alignment = StNode->getAlignment(); | |
2619 | if (alignment > 8) | |
2620 | alignment = 8; | |
2621 | ||
2622 | SDValue OutChains[2]; | |
2623 | OutChains[0] = DAG.getStore(StNode->getChain(), | |
2624 | dl, | |
2625 | SDValue(Hi64, 0), | |
2626 | StNode->getBasePtr(), | |
2627 | MachinePointerInfo(), | |
2628 | false, false, alignment); | |
2629 | EVT addrVT = StNode->getBasePtr().getValueType(); | |
2630 | SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT, | |
2631 | StNode->getBasePtr(), | |
2632 | DAG.getConstant(8, addrVT)); | |
2633 | OutChains[1] = DAG.getStore(StNode->getChain(), | |
2634 | dl, | |
2635 | SDValue(Lo64, 0), | |
2636 | LoPtr, | |
2637 | MachinePointerInfo(), | |
2638 | false, false, alignment); | |
2639 | return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains); | |
2640 | } | |
2641 | ||
2642 | static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) { | |
2643 | assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS) | |
2644 | && "invalid opcode"); | |
2645 | ||
2646 | if (Op.getValueType() == MVT::f64) | |
2647 | return LowerF64Op(Op, DAG, Op.getOpcode()); | |
2648 | if (Op.getValueType() != MVT::f128) | |
2649 | return Op; | |
2650 | ||
2651 | // Lower fabs/fneg on f128 to fabs/fneg on f64 | |
2652 | // fabs/fneg f128 => fabs/fneg f64:sub_even64, fmov f64:sub_odd64 | |
2653 | ||
2654 | SDLoc dl(Op); | |
2655 | SDValue SrcReg128 = Op.getOperand(0); | |
2656 | SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, dl, MVT::f64, | |
2657 | SrcReg128); | |
2658 | SDValue Lo64 = DAG.getTargetExtractSubreg(SP::sub_odd64, dl, MVT::f64, | |
2659 | SrcReg128); | |
2660 | if (isV9) | |
2661 | Hi64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Hi64); | |
2662 | else | |
2663 | Hi64 = LowerF64Op(Hi64, DAG, Op.getOpcode()); | |
2664 | ||
2665 | SDValue DstReg128 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, | |
2666 | dl, MVT::f128), 0); | |
2667 | DstReg128 = DAG.getTargetInsertSubreg(SP::sub_even64, dl, MVT::f128, | |
2668 | DstReg128, Hi64); | |
2669 | DstReg128 = DAG.getTargetInsertSubreg(SP::sub_odd64, dl, MVT::f128, | |
2670 | DstReg128, Lo64); | |
2671 | return DstReg128; | |
2672 | } | |
2673 | ||
2674 | static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { | |
2675 | ||
2676 | if (Op.getValueType() != MVT::i64) | |
2677 | return Op; | |
2678 | ||
2679 | SDLoc dl(Op); | |
2680 | SDValue Src1 = Op.getOperand(0); | |
2681 | SDValue Src1Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1); | |
2682 | SDValue Src1Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src1, | |
2683 | DAG.getConstant(32, MVT::i64)); | |
2684 | Src1Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1Hi); | |
2685 | ||
2686 | SDValue Src2 = Op.getOperand(1); | |
2687 | SDValue Src2Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2); | |
2688 | SDValue Src2Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src2, | |
2689 | DAG.getConstant(32, MVT::i64)); | |
2690 | Src2Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2Hi); | |
2691 | ||
2692 | ||
2693 | bool hasChain = false; | |
2694 | unsigned hiOpc = Op.getOpcode(); | |
2695 | switch (Op.getOpcode()) { | |
2696 | default: llvm_unreachable("Invalid opcode"); | |
2697 | case ISD::ADDC: hiOpc = ISD::ADDE; break; | |
2698 | case ISD::ADDE: hasChain = true; break; | |
2699 | case ISD::SUBC: hiOpc = ISD::SUBE; break; | |
2700 | case ISD::SUBE: hasChain = true; break; | |
2701 | } | |
2702 | SDValue Lo; | |
2703 | SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Glue); | |
2704 | if (hasChain) { | |
2705 | Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo, | |
2706 | Op.getOperand(2)); | |
2707 | } else { | |
2708 | Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo); | |
2709 | } | |
2710 | SDValue Hi = DAG.getNode(hiOpc, dl, VTs, Src1Hi, Src2Hi, Lo.getValue(1)); | |
2711 | SDValue Carry = Hi.getValue(1); | |
2712 | ||
2713 | Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Lo); | |
2714 | Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Hi); | |
2715 | Hi = DAG.getNode(ISD::SHL, dl, MVT::i64, Hi, | |
2716 | DAG.getConstant(32, MVT::i64)); | |
2717 | ||
2718 | SDValue Dst = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, Lo); | |
2719 | SDValue Ops[2] = { Dst, Carry }; | |
2720 | return DAG.getMergeValues(Ops, dl); | |
2721 | } | |
2722 | ||
2723 | // Custom lower UMULO/SMULO for SPARC. This code is similar to ExpandNode() | |
2724 | // in LegalizeDAG.cpp except the order of arguments to the library function. | |
2725 | static SDValue LowerUMULO_SMULO(SDValue Op, SelectionDAG &DAG, | |
2726 | const SparcTargetLowering &TLI) | |
2727 | { | |
2728 | unsigned opcode = Op.getOpcode(); | |
2729 | assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode."); | |
2730 | ||
2731 | bool isSigned = (opcode == ISD::SMULO); | |
2732 | EVT VT = MVT::i64; | |
2733 | EVT WideVT = MVT::i128; | |
2734 | SDLoc dl(Op); | |
2735 | SDValue LHS = Op.getOperand(0); | |
2736 | ||
2737 | if (LHS.getValueType() != VT) | |
2738 | return Op; | |
2739 | ||
2740 | SDValue ShiftAmt = DAG.getConstant(63, VT); | |
2741 | ||
2742 | SDValue RHS = Op.getOperand(1); | |
2743 | SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, ShiftAmt); | |
2744 | SDValue HiRHS = DAG.getNode(ISD::SRA, dl, MVT::i64, RHS, ShiftAmt); | |
2745 | SDValue Args[] = { HiLHS, LHS, HiRHS, RHS }; | |
2746 | ||
2747 | SDValue MulResult = TLI.makeLibCall(DAG, | |
2748 | RTLIB::MUL_I128, WideVT, | |
2749 | Args, 4, isSigned, dl).first; | |
2750 | SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, | |
2751 | MulResult, DAG.getIntPtrConstant(0)); | |
2752 | SDValue TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, | |
2753 | MulResult, DAG.getIntPtrConstant(1)); | |
2754 | if (isSigned) { | |
2755 | SDValue Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt); | |
2756 | TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, Tmp1, ISD::SETNE); | |
2757 | } else { | |
2758 | TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, DAG.getConstant(0, VT), | |
2759 | ISD::SETNE); | |
2760 | } | |
2761 | // MulResult is a node with an illegal type. Because such things are not | |
2762 | // generally permitted during this phase of legalization, ensure that | |
2763 | // nothing is left using the node. The above EXTRACT_ELEMENT nodes should have | |
2764 | // been folded. | |
2765 | assert(MulResult->use_empty() && "Illegally typed node still in use!"); | |
2766 | ||
2767 | SDValue Ops[2] = { BottomHalf, TopHalf } ; | |
2768 | return DAG.getMergeValues(Ops, dl); | |
2769 | } | |
2770 | ||
2771 | static SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) { | |
2772 | // Monotonic load/stores are legal. | |
2773 | if (cast<AtomicSDNode>(Op)->getOrdering() <= Monotonic) | |
2774 | return Op; | |
2775 | ||
2776 | // Otherwise, expand with a fence. | |
2777 | return SDValue(); | |
2778 | } | |
2779 | ||
2780 | ||
223e47cc LB |
2781 | SDValue SparcTargetLowering:: |
2782 | LowerOperation(SDValue Op, SelectionDAG &DAG) const { | |
1a4d82fc JJ |
2783 | |
2784 | bool hasHardQuad = Subtarget->hasHardQuad(); | |
2785 | bool isV9 = Subtarget->isV9(); | |
2786 | ||
223e47cc LB |
2787 | switch (Op.getOpcode()) { |
2788 | default: llvm_unreachable("Should not custom lower this!"); | |
1a4d82fc JJ |
2789 | |
2790 | case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG, *this, | |
2791 | Subtarget); | |
2792 | case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG, | |
2793 | Subtarget); | |
2794 | case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); | |
223e47cc | 2795 | case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); |
1a4d82fc | 2796 | case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); |
223e47cc | 2797 | case ISD::ConstantPool: return LowerConstantPool(Op, DAG); |
1a4d82fc JJ |
2798 | case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, *this, |
2799 | hasHardQuad); | |
2800 | case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG, *this, | |
2801 | hasHardQuad); | |
2802 | case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG, *this, | |
2803 | hasHardQuad); | |
2804 | case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG, *this, | |
2805 | hasHardQuad); | |
2806 | case ISD::BR_CC: return LowerBR_CC(Op, DAG, *this, | |
2807 | hasHardQuad); | |
2808 | case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, *this, | |
2809 | hasHardQuad); | |
223e47cc LB |
2810 | case ISD::VASTART: return LowerVASTART(Op, DAG, *this); |
2811 | case ISD::VAARG: return LowerVAARG(Op, DAG); | |
1a4d82fc JJ |
2812 | case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG, |
2813 | Subtarget); | |
2814 | ||
2815 | case ISD::LOAD: return LowerF128Load(Op, DAG); | |
2816 | case ISD::STORE: return LowerF128Store(Op, DAG); | |
2817 | case ISD::FADD: return LowerF128Op(Op, DAG, | |
2818 | getLibcallName(RTLIB::ADD_F128), 2); | |
2819 | case ISD::FSUB: return LowerF128Op(Op, DAG, | |
2820 | getLibcallName(RTLIB::SUB_F128), 2); | |
2821 | case ISD::FMUL: return LowerF128Op(Op, DAG, | |
2822 | getLibcallName(RTLIB::MUL_F128), 2); | |
2823 | case ISD::FDIV: return LowerF128Op(Op, DAG, | |
2824 | getLibcallName(RTLIB::DIV_F128), 2); | |
2825 | case ISD::FSQRT: return LowerF128Op(Op, DAG, | |
2826 | getLibcallName(RTLIB::SQRT_F128),1); | |
2827 | case ISD::FABS: | |
2828 | case ISD::FNEG: return LowerFNEGorFABS(Op, DAG, isV9); | |
2829 | case ISD::FP_EXTEND: return LowerF128_FPEXTEND(Op, DAG, *this); | |
2830 | case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, *this); | |
2831 | case ISD::ADDC: | |
2832 | case ISD::ADDE: | |
2833 | case ISD::SUBC: | |
2834 | case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); | |
2835 | case ISD::UMULO: | |
2836 | case ISD::SMULO: return LowerUMULO_SMULO(Op, DAG, *this); | |
2837 | case ISD::ATOMIC_LOAD: | |
2838 | case ISD::ATOMIC_STORE: return LowerATOMIC_LOAD_STORE(Op, DAG); | |
223e47cc LB |
2839 | } |
2840 | } | |
2841 | ||
2842 | MachineBasicBlock * | |
2843 | SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, | |
2844 | MachineBasicBlock *BB) const { | |
223e47cc LB |
2845 | switch (MI->getOpcode()) { |
2846 | default: llvm_unreachable("Unknown SELECT_CC!"); | |
2847 | case SP::SELECT_CC_Int_ICC: | |
2848 | case SP::SELECT_CC_FP_ICC: | |
2849 | case SP::SELECT_CC_DFP_ICC: | |
1a4d82fc JJ |
2850 | case SP::SELECT_CC_QFP_ICC: |
2851 | return expandSelectCC(MI, BB, SP::BCOND); | |
223e47cc LB |
2852 | case SP::SELECT_CC_Int_FCC: |
2853 | case SP::SELECT_CC_FP_FCC: | |
2854 | case SP::SELECT_CC_DFP_FCC: | |
1a4d82fc JJ |
2855 | case SP::SELECT_CC_QFP_FCC: |
2856 | return expandSelectCC(MI, BB, SP::FBCOND); | |
2857 | ||
2858 | case SP::ATOMIC_LOAD_ADD_32: | |
2859 | return expandAtomicRMW(MI, BB, SP::ADDrr); | |
2860 | case SP::ATOMIC_LOAD_ADD_64: | |
2861 | return expandAtomicRMW(MI, BB, SP::ADDXrr); | |
2862 | case SP::ATOMIC_LOAD_SUB_32: | |
2863 | return expandAtomicRMW(MI, BB, SP::SUBrr); | |
2864 | case SP::ATOMIC_LOAD_SUB_64: | |
2865 | return expandAtomicRMW(MI, BB, SP::SUBXrr); | |
2866 | case SP::ATOMIC_LOAD_AND_32: | |
2867 | return expandAtomicRMW(MI, BB, SP::ANDrr); | |
2868 | case SP::ATOMIC_LOAD_AND_64: | |
2869 | return expandAtomicRMW(MI, BB, SP::ANDXrr); | |
2870 | case SP::ATOMIC_LOAD_OR_32: | |
2871 | return expandAtomicRMW(MI, BB, SP::ORrr); | |
2872 | case SP::ATOMIC_LOAD_OR_64: | |
2873 | return expandAtomicRMW(MI, BB, SP::ORXrr); | |
2874 | case SP::ATOMIC_LOAD_XOR_32: | |
2875 | return expandAtomicRMW(MI, BB, SP::XORrr); | |
2876 | case SP::ATOMIC_LOAD_XOR_64: | |
2877 | return expandAtomicRMW(MI, BB, SP::XORXrr); | |
2878 | case SP::ATOMIC_LOAD_NAND_32: | |
2879 | return expandAtomicRMW(MI, BB, SP::ANDrr); | |
2880 | case SP::ATOMIC_LOAD_NAND_64: | |
2881 | return expandAtomicRMW(MI, BB, SP::ANDXrr); | |
2882 | ||
2883 | case SP::ATOMIC_SWAP_64: | |
2884 | return expandAtomicRMW(MI, BB, 0); | |
2885 | ||
2886 | case SP::ATOMIC_LOAD_MAX_32: | |
2887 | return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_G); | |
2888 | case SP::ATOMIC_LOAD_MAX_64: | |
2889 | return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_G); | |
2890 | case SP::ATOMIC_LOAD_MIN_32: | |
2891 | return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_LE); | |
2892 | case SP::ATOMIC_LOAD_MIN_64: | |
2893 | return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_LE); | |
2894 | case SP::ATOMIC_LOAD_UMAX_32: | |
2895 | return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_GU); | |
2896 | case SP::ATOMIC_LOAD_UMAX_64: | |
2897 | return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_GU); | |
2898 | case SP::ATOMIC_LOAD_UMIN_32: | |
2899 | return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_LEU); | |
2900 | case SP::ATOMIC_LOAD_UMIN_64: | |
2901 | return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_LEU); | |
223e47cc | 2902 | } |
1a4d82fc | 2903 | } |
223e47cc | 2904 | |
1a4d82fc JJ |
2905 | MachineBasicBlock* |
2906 | SparcTargetLowering::expandSelectCC(MachineInstr *MI, | |
2907 | MachineBasicBlock *BB, | |
2908 | unsigned BROpcode) const { | |
2909 | const TargetInstrInfo &TII = | |
2910 | *getTargetMachine().getSubtargetImpl()->getInstrInfo(); | |
2911 | DebugLoc dl = MI->getDebugLoc(); | |
2912 | unsigned CC = (SPCC::CondCodes)MI->getOperand(3).getImm(); | |
223e47cc LB |
2913 | |
2914 | // To "insert" a SELECT_CC instruction, we actually have to insert the diamond | |
2915 | // control-flow pattern. The incoming instruction knows the destination vreg | |
2916 | // to set, the condition code register to branch on, the true/false values to | |
2917 | // select between, and a branch opcode to use. | |
2918 | const BasicBlock *LLVM_BB = BB->getBasicBlock(); | |
2919 | MachineFunction::iterator It = BB; | |
2920 | ++It; | |
2921 | ||
2922 | // thisMBB: | |
2923 | // ... | |
2924 | // TrueVal = ... | |
2925 | // [f]bCC copy1MBB | |
2926 | // fallthrough --> copy0MBB | |
2927 | MachineBasicBlock *thisMBB = BB; | |
2928 | MachineFunction *F = BB->getParent(); | |
2929 | MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); | |
2930 | MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); | |
2931 | F->insert(It, copy0MBB); | |
2932 | F->insert(It, sinkMBB); | |
2933 | ||
2934 | // Transfer the remainder of BB and its successor edges to sinkMBB. | |
2935 | sinkMBB->splice(sinkMBB->begin(), BB, | |
1a4d82fc | 2936 | std::next(MachineBasicBlock::iterator(MI)), |
223e47cc LB |
2937 | BB->end()); |
2938 | sinkMBB->transferSuccessorsAndUpdatePHIs(BB); | |
2939 | ||
2940 | // Add the true and fallthrough blocks as its successors. | |
2941 | BB->addSuccessor(copy0MBB); | |
2942 | BB->addSuccessor(sinkMBB); | |
2943 | ||
2944 | BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC); | |
2945 | ||
2946 | // copy0MBB: | |
2947 | // %FalseValue = ... | |
2948 | // # fallthrough to sinkMBB | |
2949 | BB = copy0MBB; | |
2950 | ||
2951 | // Update machine-CFG edges | |
2952 | BB->addSuccessor(sinkMBB); | |
2953 | ||
2954 | // sinkMBB: | |
2955 | // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] | |
2956 | // ... | |
2957 | BB = sinkMBB; | |
2958 | BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg()) | |
2959 | .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) | |
2960 | .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); | |
2961 | ||
2962 | MI->eraseFromParent(); // The pseudo instruction is gone now. | |
2963 | return BB; | |
2964 | } | |
2965 | ||
1a4d82fc JJ |
2966 | MachineBasicBlock* |
2967 | SparcTargetLowering::expandAtomicRMW(MachineInstr *MI, | |
2968 | MachineBasicBlock *MBB, | |
2969 | unsigned Opcode, | |
2970 | unsigned CondCode) const { | |
2971 | const TargetInstrInfo &TII = | |
2972 | *getTargetMachine().getSubtargetImpl()->getInstrInfo(); | |
2973 | MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); | |
2974 | DebugLoc DL = MI->getDebugLoc(); | |
2975 | ||
2976 | // MI is an atomic read-modify-write instruction of the form: | |
2977 | // | |
2978 | // rd = atomicrmw<op> addr, rs2 | |
2979 | // | |
2980 | // All three operands are registers. | |
2981 | unsigned DestReg = MI->getOperand(0).getReg(); | |
2982 | unsigned AddrReg = MI->getOperand(1).getReg(); | |
2983 | unsigned Rs2Reg = MI->getOperand(2).getReg(); | |
2984 | ||
2985 | // SelectionDAG has already inserted memory barriers before and after MI, so | |
2986 | // we simply have to implement the operatiuon in terms of compare-and-swap. | |
2987 | // | |
2988 | // %val0 = load %addr | |
2989 | // loop: | |
2990 | // %val = phi %val0, %dest | |
2991 | // %upd = op %val, %rs2 | |
2992 | // %dest = cas %addr, %val, %upd | |
2993 | // cmp %val, %dest | |
2994 | // bne loop | |
2995 | // done: | |
2996 | // | |
2997 | bool is64Bit = SP::I64RegsRegClass.hasSubClassEq(MRI.getRegClass(DestReg)); | |
2998 | const TargetRegisterClass *ValueRC = | |
2999 | is64Bit ? &SP::I64RegsRegClass : &SP::IntRegsRegClass; | |
3000 | unsigned Val0Reg = MRI.createVirtualRegister(ValueRC); | |
3001 | ||
3002 | BuildMI(*MBB, MI, DL, TII.get(is64Bit ? SP::LDXri : SP::LDri), Val0Reg) | |
3003 | .addReg(AddrReg).addImm(0); | |
3004 | ||
3005 | // Split the basic block MBB before MI and insert the loop block in the hole. | |
3006 | MachineFunction::iterator MFI = MBB; | |
3007 | const BasicBlock *LLVM_BB = MBB->getBasicBlock(); | |
3008 | MachineFunction *MF = MBB->getParent(); | |
3009 | MachineBasicBlock *LoopMBB = MF->CreateMachineBasicBlock(LLVM_BB); | |
3010 | MachineBasicBlock *DoneMBB = MF->CreateMachineBasicBlock(LLVM_BB); | |
3011 | ++MFI; | |
3012 | MF->insert(MFI, LoopMBB); | |
3013 | MF->insert(MFI, DoneMBB); | |
3014 | ||
3015 | // Move MI and following instructions to DoneMBB. | |
3016 | DoneMBB->splice(DoneMBB->begin(), MBB, MI, MBB->end()); | |
3017 | DoneMBB->transferSuccessorsAndUpdatePHIs(MBB); | |
3018 | ||
3019 | // Connect the CFG again. | |
3020 | MBB->addSuccessor(LoopMBB); | |
3021 | LoopMBB->addSuccessor(LoopMBB); | |
3022 | LoopMBB->addSuccessor(DoneMBB); | |
3023 | ||
3024 | // Build the loop block. | |
3025 | unsigned ValReg = MRI.createVirtualRegister(ValueRC); | |
3026 | // Opcode == 0 means try to write Rs2Reg directly (ATOMIC_SWAP). | |
3027 | unsigned UpdReg = (Opcode ? MRI.createVirtualRegister(ValueRC) : Rs2Reg); | |
3028 | ||
3029 | BuildMI(LoopMBB, DL, TII.get(SP::PHI), ValReg) | |
3030 | .addReg(Val0Reg).addMBB(MBB) | |
3031 | .addReg(DestReg).addMBB(LoopMBB); | |
3032 | ||
3033 | if (CondCode) { | |
3034 | // This is one of the min/max operations. We need a CMPrr followed by a | |
3035 | // MOVXCC/MOVICC. | |
3036 | BuildMI(LoopMBB, DL, TII.get(SP::CMPrr)).addReg(ValReg).addReg(Rs2Reg); | |
3037 | BuildMI(LoopMBB, DL, TII.get(Opcode), UpdReg) | |
3038 | .addReg(ValReg).addReg(Rs2Reg).addImm(CondCode); | |
3039 | } else if (Opcode) { | |
3040 | BuildMI(LoopMBB, DL, TII.get(Opcode), UpdReg) | |
3041 | .addReg(ValReg).addReg(Rs2Reg); | |
3042 | } | |
3043 | ||
3044 | if (MI->getOpcode() == SP::ATOMIC_LOAD_NAND_32 || | |
3045 | MI->getOpcode() == SP::ATOMIC_LOAD_NAND_64) { | |
3046 | unsigned TmpReg = UpdReg; | |
3047 | UpdReg = MRI.createVirtualRegister(ValueRC); | |
3048 | BuildMI(LoopMBB, DL, TII.get(SP::XORri), UpdReg).addReg(TmpReg).addImm(-1); | |
3049 | } | |
3050 | ||
3051 | BuildMI(LoopMBB, DL, TII.get(is64Bit ? SP::CASXrr : SP::CASrr), DestReg) | |
3052 | .addReg(AddrReg).addReg(ValReg).addReg(UpdReg) | |
3053 | .setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); | |
3054 | BuildMI(LoopMBB, DL, TII.get(SP::CMPrr)).addReg(ValReg).addReg(DestReg); | |
3055 | BuildMI(LoopMBB, DL, TII.get(is64Bit ? SP::BPXCC : SP::BCOND)) | |
3056 | .addMBB(LoopMBB).addImm(SPCC::ICC_NE); | |
3057 | ||
3058 | MI->eraseFromParent(); | |
3059 | return DoneMBB; | |
3060 | } | |
3061 | ||
223e47cc LB |
3062 | //===----------------------------------------------------------------------===// |
3063 | // Sparc Inline Assembly Support | |
3064 | //===----------------------------------------------------------------------===// | |
3065 | ||
3066 | /// getConstraintType - Given a constraint letter, return the type of | |
3067 | /// constraint it is for this target. | |
3068 | SparcTargetLowering::ConstraintType | |
3069 | SparcTargetLowering::getConstraintType(const std::string &Constraint) const { | |
3070 | if (Constraint.size() == 1) { | |
3071 | switch (Constraint[0]) { | |
3072 | default: break; | |
3073 | case 'r': return C_RegisterClass; | |
1a4d82fc JJ |
3074 | case 'I': // SIMM13 |
3075 | return C_Other; | |
223e47cc LB |
3076 | } |
3077 | } | |
3078 | ||
3079 | return TargetLowering::getConstraintType(Constraint); | |
3080 | } | |
3081 | ||
1a4d82fc JJ |
3082 | TargetLowering::ConstraintWeight SparcTargetLowering:: |
3083 | getSingleConstraintMatchWeight(AsmOperandInfo &info, | |
3084 | const char *constraint) const { | |
3085 | ConstraintWeight weight = CW_Invalid; | |
3086 | Value *CallOperandVal = info.CallOperandVal; | |
3087 | // If we don't have a value, we can't do a match, | |
3088 | // but allow it at the lowest weight. | |
3089 | if (!CallOperandVal) | |
3090 | return CW_Default; | |
3091 | ||
3092 | // Look at the constraint type. | |
3093 | switch (*constraint) { | |
3094 | default: | |
3095 | weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); | |
3096 | break; | |
3097 | case 'I': // SIMM13 | |
3098 | if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) { | |
3099 | if (isInt<13>(C->getSExtValue())) | |
3100 | weight = CW_Constant; | |
3101 | } | |
3102 | break; | |
3103 | } | |
3104 | return weight; | |
3105 | } | |
3106 | ||
3107 | /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops | |
3108 | /// vector. If it is invalid, don't add anything to Ops. | |
3109 | void SparcTargetLowering:: | |
3110 | LowerAsmOperandForConstraint(SDValue Op, | |
3111 | std::string &Constraint, | |
3112 | std::vector<SDValue> &Ops, | |
3113 | SelectionDAG &DAG) const { | |
3114 | SDValue Result(nullptr, 0); | |
3115 | ||
3116 | // Only support length 1 constraints for now. | |
3117 | if (Constraint.length() > 1) | |
3118 | return; | |
3119 | ||
3120 | char ConstraintLetter = Constraint[0]; | |
3121 | switch (ConstraintLetter) { | |
3122 | default: break; | |
3123 | case 'I': | |
3124 | if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { | |
3125 | if (isInt<13>(C->getSExtValue())) { | |
3126 | Result = DAG.getTargetConstant(C->getSExtValue(), Op.getValueType()); | |
3127 | break; | |
3128 | } | |
3129 | return; | |
3130 | } | |
3131 | } | |
3132 | ||
3133 | if (Result.getNode()) { | |
3134 | Ops.push_back(Result); | |
3135 | return; | |
3136 | } | |
3137 | TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); | |
3138 | } | |
3139 | ||
223e47cc LB |
3140 | std::pair<unsigned, const TargetRegisterClass*> |
3141 | SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, | |
1a4d82fc | 3142 | MVT VT) const { |
223e47cc LB |
3143 | if (Constraint.size() == 1) { |
3144 | switch (Constraint[0]) { | |
3145 | case 'r': | |
3146 | return std::make_pair(0U, &SP::IntRegsRegClass); | |
3147 | } | |
1a4d82fc JJ |
3148 | } else if (!Constraint.empty() && Constraint.size() <= 5 |
3149 | && Constraint[0] == '{' && *(Constraint.end()-1) == '}') { | |
3150 | // constraint = '{r<d>}' | |
3151 | // Remove the braces from around the name. | |
3152 | StringRef name(Constraint.data()+1, Constraint.size()-2); | |
3153 | // Handle register aliases: | |
3154 | // r0-r7 -> g0-g7 | |
3155 | // r8-r15 -> o0-o7 | |
3156 | // r16-r23 -> l0-l7 | |
3157 | // r24-r31 -> i0-i7 | |
3158 | uint64_t intVal = 0; | |
3159 | if (name.substr(0, 1).equals("r") | |
3160 | && !name.substr(1).getAsInteger(10, intVal) && intVal <= 31) { | |
3161 | const char regTypes[] = { 'g', 'o', 'l', 'i' }; | |
3162 | char regType = regTypes[intVal/8]; | |
3163 | char regIdx = '0' + (intVal % 8); | |
3164 | char tmp[] = { '{', regType, regIdx, '}', 0 }; | |
3165 | std::string newConstraint = std::string(tmp); | |
3166 | return TargetLowering::getRegForInlineAsmConstraint(newConstraint, VT); | |
3167 | } | |
223e47cc LB |
3168 | } |
3169 | ||
3170 | return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); | |
3171 | } | |
3172 | ||
3173 | bool | |
3174 | SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { | |
3175 | // The Sparc target isn't yet aware of offsets. | |
3176 | return false; | |
3177 | } | |
1a4d82fc JJ |
3178 | |
3179 | void SparcTargetLowering::ReplaceNodeResults(SDNode *N, | |
3180 | SmallVectorImpl<SDValue>& Results, | |
3181 | SelectionDAG &DAG) const { | |
3182 | ||
3183 | SDLoc dl(N); | |
3184 | ||
3185 | RTLIB::Libcall libCall = RTLIB::UNKNOWN_LIBCALL; | |
3186 | ||
3187 | switch (N->getOpcode()) { | |
3188 | default: | |
3189 | llvm_unreachable("Do not know how to custom type legalize this operation!"); | |
3190 | ||
3191 | case ISD::FP_TO_SINT: | |
3192 | case ISD::FP_TO_UINT: | |
3193 | // Custom lower only if it involves f128 or i64. | |
3194 | if (N->getOperand(0).getValueType() != MVT::f128 | |
3195 | || N->getValueType(0) != MVT::i64) | |
3196 | return; | |
3197 | libCall = ((N->getOpcode() == ISD::FP_TO_SINT) | |
3198 | ? RTLIB::FPTOSINT_F128_I64 | |
3199 | : RTLIB::FPTOUINT_F128_I64); | |
3200 | ||
3201 | Results.push_back(LowerF128Op(SDValue(N, 0), | |
3202 | DAG, | |
3203 | getLibcallName(libCall), | |
3204 | 1)); | |
3205 | return; | |
3206 | ||
3207 | case ISD::SINT_TO_FP: | |
3208 | case ISD::UINT_TO_FP: | |
3209 | // Custom lower only if it involves f128 or i64. | |
3210 | if (N->getValueType(0) != MVT::f128 | |
3211 | || N->getOperand(0).getValueType() != MVT::i64) | |
3212 | return; | |
3213 | ||
3214 | libCall = ((N->getOpcode() == ISD::SINT_TO_FP) | |
3215 | ? RTLIB::SINTTOFP_I64_F128 | |
3216 | : RTLIB::UINTTOFP_I64_F128); | |
3217 | ||
3218 | Results.push_back(LowerF128Op(SDValue(N, 0), | |
3219 | DAG, | |
3220 | getLibcallName(libCall), | |
3221 | 1)); | |
3222 | return; | |
3223 | } | |
3224 | } |