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New upstream version 1.42.0+dfsg0+pve1
[rustc.git] / src / stdarch / crates / core_arch / src / arm / neon.rs
CommitLineData
0531ce1d
XL		 1//! ARMv7 NEON intrinsics
2
532ac7d7 3use crate::{core_arch::simd_llvm::*, mem::transmute};
0531ce1d 4#[cfg(test)]
416331ca 5use stdarch_test::assert_instr;
0531ce1d 6
83c7162d
XL		 7types! {
8 /// ARM-specific 64-bit wide vector of eight packed `i8`.
9 pub struct int8x8_t(i8, i8, i8, i8, i8, i8, i8, i8);
10 /// ARM-specific 64-bit wide vector of eight packed `u8`.
11 pub struct uint8x8_t(u8, u8, u8, u8, u8, u8, u8, u8);
12 /// ARM-specific 64-bit wide polynomial vector of eight packed `u8`.
13 pub struct poly8x8_t(u8, u8, u8, u8, u8, u8, u8, u8);
14 /// ARM-specific 64-bit wide vector of four packed `i16`.
15 pub struct int16x4_t(i16, i16, i16, i16);
16 /// ARM-specific 64-bit wide vector of four packed `u16`.
17 pub struct uint16x4_t(u16, u16, u16, u16);
18 // FIXME: ARM-specific 64-bit wide vector of four packed `f16`.
19 // pub struct float16x4_t(f16, f16, f16, f16);
20 /// ARM-specific 64-bit wide vector of four packed `u16`.
21 pub struct poly16x4_t(u16, u16, u16, u16);
22 /// ARM-specific 64-bit wide vector of two packed `i32`.
23 pub struct int32x2_t(i32, i32);
24 /// ARM-specific 64-bit wide vector of two packed `u32`.
25 pub struct uint32x2_t(u32, u32);
26 /// ARM-specific 64-bit wide vector of two packed `f32`.
27 pub struct float32x2_t(f32, f32);
28 /// ARM-specific 64-bit wide vector of one packed `i64`.
29 pub struct int64x1_t(i64);
30 /// ARM-specific 64-bit wide vector of one packed `u64`.
31 pub struct uint64x1_t(u64);
32
8faf50e0 33 /// ARM-specific 128-bit wide vector of sixteen packed `i8`.
83c7162d
XL		 34 pub struct int8x16_t(
35 i8, i8 ,i8, i8, i8, i8 ,i8, i8,
36 i8, i8 ,i8, i8, i8, i8 ,i8, i8,
37 );
38 /// ARM-specific 128-bit wide vector of sixteen packed `u8`.
39 pub struct uint8x16_t(
40 u8, u8 ,u8, u8, u8, u8 ,u8, u8,
41 u8, u8 ,u8, u8, u8, u8 ,u8, u8,
42 );
43 /// ARM-specific 128-bit wide vector of sixteen packed `u8`.
44 pub struct poly8x16_t(
45 u8, u8, u8, u8, u8, u8, u8, u8,
46 u8, u8, u8, u8, u8, u8, u8, u8
47 );
48 /// ARM-specific 128-bit wide vector of eight packed `i16`.
49 pub struct int16x8_t(i16, i16, i16, i16, i16, i16, i16, i16);
50 /// ARM-specific 128-bit wide vector of eight packed `u16`.
51 pub struct uint16x8_t(u16, u16, u16, u16, u16, u16, u16, u16);
52 // FIXME: ARM-specific 128-bit wide vector of eight packed `f16`.
53 // pub struct float16x8_t(f16, f16, f16, f16, f16, f16, f16);
54 /// ARM-specific 128-bit wide vector of eight packed `u16`.
55 pub struct poly16x8_t(u16, u16, u16, u16, u16, u16, u16, u16);
56 /// ARM-specific 128-bit wide vector of four packed `i32`.
57 pub struct int32x4_t(i32, i32, i32, i32);
58 /// ARM-specific 128-bit wide vector of four packed `u32`.
59 pub struct uint32x4_t(u32, u32, u32, u32);
60 /// ARM-specific 128-bit wide vector of four packed `f32`.
61 pub struct float32x4_t(f32, f32, f32, f32);
62 /// ARM-specific 128-bit wide vector of two packed `i64`.
63 pub struct int64x2_t(i64, i64);
64 /// ARM-specific 128-bit wide vector of two packed `u64`.
65 pub struct uint64x2_t(u64, u64);
66}
67
0bf4aa26
XL		 68/// ARM-specific type containing two `int8x8_t` vectors.
69#[derive(Copy, Clone)]
70pub struct int8x8x2_t(pub int8x8_t, pub int8x8_t);
71/// ARM-specific type containing three `int8x8_t` vectors.
72#[derive(Copy, Clone)]
73pub struct int8x8x3_t(pub int8x8_t, pub int8x8_t, pub int8x8_t);
74/// ARM-specific type containing four `int8x8_t` vectors.
75#[derive(Copy, Clone)]
76pub struct int8x8x4_t(pub int8x8_t, pub int8x8_t, pub int8x8_t, pub int8x8_t);
77
78/// ARM-specific type containing two `uint8x8_t` vectors.
79#[derive(Copy, Clone)]
80pub struct uint8x8x2_t(pub uint8x8_t, pub uint8x8_t);
81/// ARM-specific type containing three `uint8x8_t` vectors.
82#[derive(Copy, Clone)]
83pub struct uint8x8x3_t(pub uint8x8_t, pub uint8x8_t, pub uint8x8_t);
84/// ARM-specific type containing four `uint8x8_t` vectors.
85#[derive(Copy, Clone)]
0731742a 86pub struct uint8x8x4_t(pub uint8x8_t, pub uint8x8_t, pub uint8x8_t, pub uint8x8_t);
0bf4aa26
XL		 87
88/// ARM-specific type containing two `poly8x8_t` vectors.
89#[derive(Copy, Clone)]
90pub struct poly8x8x2_t(pub poly8x8_t, pub poly8x8_t);
91/// ARM-specific type containing three `poly8x8_t` vectors.
92#[derive(Copy, Clone)]
93pub struct poly8x8x3_t(pub poly8x8_t, pub poly8x8_t, pub poly8x8_t);
94/// ARM-specific type containing four `poly8x8_t` vectors.
95#[derive(Copy, Clone)]
0731742a 96pub struct poly8x8x4_t(pub poly8x8_t, pub poly8x8_t, pub poly8x8_t, pub poly8x8_t);
0bf4aa26 97
83c7162d
XL		 98#[allow(improper_ctypes)]
99extern "C" {
0731742a
XL		 100 #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.frsqrte.v2f32")]
101 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v2f32")]
83c7162d
XL		 102 fn frsqrte_v2f32(a: float32x2_t) -> float32x2_t;
103
104 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v8i8")]
0731742a 105 #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sminp.v8i8")]
83c7162d 106 fn vpmins_v8i8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
0731742a
XL		 107 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v4i16")]
108 #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sminp.v4i16")]
83c7162d 109 fn vpmins_v4i16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
0731742a
XL		 110 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v2i32")]
111 #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.sminp.v2i32")]
83c7162d
XL		 112 fn vpmins_v2i32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
113 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpminu.v8i8")]
0731742a 114 #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uminp.v8i8")]
83c7162d 115 fn vpminu_v8i8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
0731742a
XL		 116 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpminu.v4i16")]
117 #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uminp.v4i16")]
83c7162d 118 fn vpminu_v4i16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
0731742a
XL		 119 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpminu.v2i32")]
120 #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.uminp.v2i32")]
83c7162d 121 fn vpminu_v2i32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
0731742a
XL		 122 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v2f32")]
123 #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fminp.v2f32")]
83c7162d
XL		 124 fn vpminf_v2f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
125
126 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v8i8")]
0731742a 127 #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.smaxp.v8i8")]
83c7162d 128 fn vpmaxs_v8i8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
0731742a
XL		 129 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v4i16")]
130 #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.smaxp.v4i16")]
83c7162d 131 fn vpmaxs_v4i16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
0731742a
XL		 132 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v2i32")]
133 #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.smaxp.v2i32")]
83c7162d
XL		 134 fn vpmaxs_v2i32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
135 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxu.v8i8")]
0731742a 136 #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.umaxp.v8i8")]
83c7162d 137 fn vpmaxu_v8i8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
0731742a
XL		 138 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxu.v4i16")]
139 #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.umaxp.v4i16")]
83c7162d 140 fn vpmaxu_v4i16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
0731742a
XL		 141 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxu.v2i32")]
142 #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.umaxp.v2i32")]
83c7162d 143 fn vpmaxu_v2i32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
0731742a
XL		 144 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v2f32")]
145 #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.neon.fmaxp.v2f32")]
83c7162d
XL		 146 fn vpmaxf_v2f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
147}
0531ce1d 148
0bf4aa26
XL		 149#[cfg(target_arch = "arm")]
150#[allow(improper_ctypes)]
151extern "C" {
152 #[link_name = "llvm.arm.neon.vtbl1"]
153 fn vtbl1(a: int8x8_t, b: int8x8_t) -> int8x8_t;
154 #[link_name = "llvm.arm.neon.vtbl2"]
155 fn vtbl2(a: int8x8_t, b: int8x8_t, b: int8x8_t) -> int8x8_t;
156 #[link_name = "llvm.arm.neon.vtbl3"]
157 fn vtbl3(a: int8x8_t, b: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t;
158 #[link_name = "llvm.arm.neon.vtbl4"]
0731742a 159 fn vtbl4(a: int8x8_t, b: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t;
0bf4aa26
XL		 160
161 #[link_name = "llvm.arm.neon.vtbx1"]
162 fn vtbx1(a: int8x8_t, b: int8x8_t, b: int8x8_t) -> int8x8_t;
163 #[link_name = "llvm.arm.neon.vtbx2"]
164 fn vtbx2(a: int8x8_t, b: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t;
165 #[link_name = "llvm.arm.neon.vtbx3"]
0731742a 166 fn vtbx3(a: int8x8_t, b: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t;
0bf4aa26
XL		 167 #[link_name = "llvm.arm.neon.vtbx4"]
168 fn vtbx4(
0731742a
XL		 169 a: int8x8_t,
170 b: int8x8_t,
171 b: int8x8_t,
172 c: int8x8_t,
173 d: int8x8_t,
0bf4aa26
XL		 174 e: int8x8_t,
175 ) -> int8x8_t;
176}
177
0531ce1d
XL		 178/// Vector add.
179#[inline]
180#[target_feature(enable = "neon")]
83c7162d
XL		 181#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
182#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
183#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(add))]
184pub unsafe fn vadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
0531ce1d
XL		 185 simd_add(a, b)
186}
187
188/// Vector add.
189#[inline]
190#[target_feature(enable = "neon")]
83c7162d
XL		 191#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
192#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
193#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(add))]
194pub unsafe fn vaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
0531ce1d
XL		 195 simd_add(a, b)
196}
197
198/// Vector add.
199#[inline]
200#[target_feature(enable = "neon")]
83c7162d
XL		 201#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
202#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
203#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(add))]
204pub unsafe fn vadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
0531ce1d
XL		 205 simd_add(a, b)
206}
207
208/// Vector add.
209#[inline]
210#[target_feature(enable = "neon")]
83c7162d
XL		 211#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
212#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
213#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(add))]
214pub unsafe fn vaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
0531ce1d
XL		 215 simd_add(a, b)
216}
217
218/// Vector add.
219#[inline]
220#[target_feature(enable = "neon")]
83c7162d
XL		 221#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
222#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
223#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(add))]
224pub unsafe fn vadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
0531ce1d
XL		 225 simd_add(a, b)
226}
227
228/// Vector add.
229#[inline]
230#[target_feature(enable = "neon")]
83c7162d
XL		 231#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
232#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
233#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(add))]
234pub unsafe fn vaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
0531ce1d
XL		 235 simd_add(a, b)
236}
237
238/// Vector add.
239#[inline]
240#[target_feature(enable = "neon")]
83c7162d
XL		 241#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
242#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
243#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(add))]
244pub unsafe fn vaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
0531ce1d
XL		 245 simd_add(a, b)
246}
247
248/// Vector add.
249#[inline]
250#[target_feature(enable = "neon")]
83c7162d
XL		 251#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
252#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
253#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(add))]
254pub unsafe fn vadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
0531ce1d
XL		 255 simd_add(a, b)
256}
257
258/// Vector add.
259#[inline]
260#[target_feature(enable = "neon")]
83c7162d
XL		 261#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
262#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
263#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(add))]
264pub unsafe fn vaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
0531ce1d
XL		 265 simd_add(a, b)
266}
267
268/// Vector add.
269#[inline]
270#[target_feature(enable = "neon")]
83c7162d
XL		 271#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
272#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
273#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(add))]
274pub unsafe fn vadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
0531ce1d
XL		 275 simd_add(a, b)
276}
277
278/// Vector add.
279#[inline]
280#[target_feature(enable = "neon")]
83c7162d
XL		 281#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
282#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
283#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(add))]
284pub unsafe fn vaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
0531ce1d
XL		 285 simd_add(a, b)
286}
287
288/// Vector add.
289#[inline]
290#[target_feature(enable = "neon")]
83c7162d
XL		 291#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
292#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
293#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(add))]
294pub unsafe fn vadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
0531ce1d
XL		 295 simd_add(a, b)
296}
297
298/// Vector add.
299#[inline]
300#[target_feature(enable = "neon")]
83c7162d
XL		 301#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
302#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
303#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(add))]
304pub unsafe fn vaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
0531ce1d
XL		 305 simd_add(a, b)
306}
307
308/// Vector add.
309#[inline]
310#[target_feature(enable = "neon")]
83c7162d
XL		 311#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
312#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
313#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(add))]
314pub unsafe fn vaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
0531ce1d
XL		 315 simd_add(a, b)
316}
317
318/// Vector add.
319#[inline]
320#[target_feature(enable = "neon")]
83c7162d
XL		 321#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
322#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
323#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(fadd))]
324pub unsafe fn vadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
0531ce1d
XL		 325 simd_add(a, b)
326}
327
328/// Vector add.
329#[inline]
330#[target_feature(enable = "neon")]
83c7162d
XL		 331#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
332#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
333#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(fadd))]
334pub unsafe fn vaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
0531ce1d
XL		 335 simd_add(a, b)
336}
337
338/// Vector long add.
339#[inline]
340#[target_feature(enable = "neon")]
83c7162d
XL		 341#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
342#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
343#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(saddl))]
344pub unsafe fn vaddl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t {
345 let a: int16x8_t = simd_cast(a);
346 let b: int16x8_t = simd_cast(b);
0531ce1d
XL		 347 simd_add(a, b)
348}
349
350/// Vector long add.
351#[inline]
352#[target_feature(enable = "neon")]
83c7162d
XL		 353#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
354#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
355#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(saddl))]
356pub unsafe fn vaddl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
357 let a: int32x4_t = simd_cast(a);
358 let b: int32x4_t = simd_cast(b);
0531ce1d
XL		 359 simd_add(a, b)
360}
361
362/// Vector long add.
363#[inline]
364#[target_feature(enable = "neon")]
83c7162d
XL		 365#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
366#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
367#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(saddl))]
368pub unsafe fn vaddl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
369 let a: int64x2_t = simd_cast(a);
370 let b: int64x2_t = simd_cast(b);
0531ce1d
XL		 371 simd_add(a, b)
372}
373
374/// Vector long add.
375#[inline]
376#[target_feature(enable = "neon")]
83c7162d
XL		 377#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
378#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
379#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uaddl))]
380pub unsafe fn vaddl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t {
381 let a: uint16x8_t = simd_cast(a);
382 let b: uint16x8_t = simd_cast(b);
0531ce1d
XL		 383 simd_add(a, b)
384}
385
386/// Vector long add.
387#[inline]
388#[target_feature(enable = "neon")]
83c7162d
XL		 389#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
390#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
391#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uaddl))]
392pub unsafe fn vaddl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
393 let a: uint32x4_t = simd_cast(a);
394 let b: uint32x4_t = simd_cast(b);
0531ce1d
XL		 395 simd_add(a, b)
396}
397
398/// Vector long add.
399#[inline]
400#[target_feature(enable = "neon")]
83c7162d
XL		 401#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
402#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
403#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uaddl))]
404pub unsafe fn vaddl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
405 let a: uint64x2_t = simd_cast(a);
406 let b: uint64x2_t = simd_cast(b);
0531ce1d
XL		 407 simd_add(a, b)
408}
409
0531ce1d
XL		 410/// Vector narrow integer.
411#[inline]
412#[target_feature(enable = "neon")]
83c7162d
XL		 413#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
414#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
415#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(xtn))]
416pub unsafe fn vmovn_s16(a: int16x8_t) -> int8x8_t {
417 simd_cast(a)
0531ce1d
XL		 418}
419
420/// Vector narrow integer.
421#[inline]
422#[target_feature(enable = "neon")]
83c7162d
XL		 423#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
424#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
425#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(xtn))]
426pub unsafe fn vmovn_s32(a: int32x4_t) -> int16x4_t {
427 simd_cast(a)
0531ce1d
XL		 428}
429
430/// Vector narrow integer.
431#[inline]
432#[target_feature(enable = "neon")]
83c7162d
XL		 433#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
434#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
435#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(xtn))]
436pub unsafe fn vmovn_s64(a: int64x2_t) -> int32x2_t {
437 simd_cast(a)
0531ce1d
XL		 438}
439
440/// Vector narrow integer.
441#[inline]
442#[target_feature(enable = "neon")]
83c7162d
XL		 443#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
444#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
445#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(xtn))]
446pub unsafe fn vmovn_u16(a: uint16x8_t) -> uint8x8_t {
447 simd_cast(a)
0531ce1d
XL		 448}
449
450/// Vector narrow integer.
451#[inline]
452#[target_feature(enable = "neon")]
83c7162d
XL		 453#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
454#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
455#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(xtn))]
456pub unsafe fn vmovn_u32(a: uint32x4_t) -> uint16x4_t {
457 simd_cast(a)
0531ce1d
XL		 458}
459
460/// Vector narrow integer.
461#[inline]
462#[target_feature(enable = "neon")]
83c7162d
XL		 463#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
464#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
465#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(xtn))]
466pub unsafe fn vmovn_u64(a: uint64x2_t) -> uint32x2_t {
467 simd_cast(a)
0531ce1d
XL		 468}
469
470/// Vector long move.
471#[inline]
472#[target_feature(enable = "neon")]
83c7162d
XL		 473#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
474#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
0531ce1d 475#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sxtl))]
83c7162d
XL		 476pub unsafe fn vmovl_s8(a: int8x8_t) -> int16x8_t {
477 simd_cast(a)
0531ce1d
XL		 478}
479
480/// Vector long move.
481#[inline]
482#[target_feature(enable = "neon")]
83c7162d
XL		 483#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
484#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
0531ce1d 485#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sxtl))]
83c7162d
XL		 486pub unsafe fn vmovl_s16(a: int16x4_t) -> int32x4_t {
487 simd_cast(a)
0531ce1d
XL		 488}
489
490/// Vector long move.
491#[inline]
492#[target_feature(enable = "neon")]
83c7162d
XL		 493#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
494#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
0531ce1d 495#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sxtl))]
83c7162d
XL		 496pub unsafe fn vmovl_s32(a: int32x2_t) -> int64x2_t {
497 simd_cast(a)
0531ce1d
XL		 498}
499
500/// Vector long move.
501#[inline]
502#[target_feature(enable = "neon")]
83c7162d
XL		 503#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
504#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
0531ce1d 505#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uxtl))]
83c7162d
XL		 506pub unsafe fn vmovl_u8(a: uint8x8_t) -> uint16x8_t {
507 simd_cast(a)
0531ce1d
XL		 508}
509
510/// Vector long move.
511#[inline]
512#[target_feature(enable = "neon")]
83c7162d
XL		 513#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
514#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
0531ce1d 515#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uxtl))]
83c7162d
XL		 516pub unsafe fn vmovl_u16(a: uint16x4_t) -> uint32x4_t {
517 simd_cast(a)
0531ce1d
XL		 518}
519
520/// Vector long move.
521#[inline]
522#[target_feature(enable = "neon")]
83c7162d
XL		 523#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
524#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
0531ce1d 525#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uxtl))]
83c7162d
XL		 526pub unsafe fn vmovl_u32(a: uint32x2_t) -> uint64x2_t {
527 simd_cast(a)
528}
529
530/// Reciprocal square-root estimate.
531#[inline]
532#[target_feature(enable = "neon")]
533#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(frsqrte))]
534#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
535pub unsafe fn vrsqrte_f32(a: float32x2_t) -> float32x2_t {
536 frsqrte_v2f32(a)
537}
538
416331ca
XL		 539/// Vector bitwise not.
540#[inline]
541#[target_feature(enable = "neon")]
542#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
543#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
544#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mvn))]
545pub unsafe fn vmvn_s8(a: int8x8_t) -> int8x8_t {
546 let b = int8x8_t(-1, -1, -1, -1, -1, -1, -1, -1);
547 simd_xor(a, b)
548}
549
550/// Vector bitwise not.
551#[inline]
552#[target_feature(enable = "neon")]
553#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
554#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
555#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mvn))]
556pub unsafe fn vmvnq_s8(a: int8x16_t) -> int8x16_t {
557 let b = int8x16_t(
558 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
559 );
560 simd_xor(a, b)
561}
562
563/// Vector bitwise not.
564#[inline]
565#[target_feature(enable = "neon")]
566#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
567#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
568#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mvn))]
569pub unsafe fn vmvn_s16(a: int16x4_t) -> int16x4_t {
570 let b = int16x4_t(-1, -1, -1, -1);
571 simd_xor(a, b)
572}
573
574/// Vector bitwise not.
575#[inline]
576#[target_feature(enable = "neon")]
577#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
578#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
579#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mvn))]
580pub unsafe fn vmvnq_s16(a: int16x8_t) -> int16x8_t {
581 let b = int16x8_t(-1, -1, -1, -1, -1, -1, -1, -1);
582 simd_xor(a, b)
583}
584
585/// Vector bitwise not.
586#[inline]
587#[target_feature(enable = "neon")]
588#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
589#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
590#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mvn))]
591pub unsafe fn vmvn_s32(a: int32x2_t) -> int32x2_t {
592 let b = int32x2_t(-1, -1);
593 simd_xor(a, b)
594}
595
596/// Vector bitwise not.
597#[inline]
598#[target_feature(enable = "neon")]
599#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
600#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
601#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mvn))]
602pub unsafe fn vmvnq_s32(a: int32x4_t) -> int32x4_t {
603 let b = int32x4_t(-1, -1, -1, -1);
604 simd_xor(a, b)
605}
606
607/// Vector bitwise not.
608#[inline]
609#[target_feature(enable = "neon")]
610#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
611#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
612#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mvn))]
613pub unsafe fn vmvn_u8(a: uint8x8_t) -> uint8x8_t {
614 let b = uint8x8_t(255, 255, 255, 255, 255, 255, 255, 255);
615 simd_xor(a, b)
616}
617
618/// Vector bitwise not.
619#[inline]
620#[target_feature(enable = "neon")]
621#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
622#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
623#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mvn))]
624pub unsafe fn vmvnq_u8(a: uint8x16_t) -> uint8x16_t {
625 let b = uint8x16_t(
626 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
627 );
628 simd_xor(a, b)
629}
630
631/// Vector bitwise not.
632#[inline]
633#[target_feature(enable = "neon")]
634#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
635#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
636#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mvn))]
637pub unsafe fn vmvn_u16(a: uint16x4_t) -> uint16x4_t {
638 let b = uint16x4_t(65_535, 65_535, 65_535, 65_535);
639 simd_xor(a, b)
640}
641
642/// Vector bitwise not.
643#[inline]
644#[target_feature(enable = "neon")]
645#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
646#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
647#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mvn))]
648pub unsafe fn vmvnq_u16(a: uint16x8_t) -> uint16x8_t {
649 let b = uint16x8_t(
650 65_535, 65_535, 65_535, 65_535, 65_535, 65_535, 65_535, 65_535,
651 );
652 simd_xor(a, b)
653}
654
655/// Vector bitwise not.
656#[inline]
657#[target_feature(enable = "neon")]
658#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
659#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
660#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mvn))]
661pub unsafe fn vmvn_u32(a: uint32x2_t) -> uint32x2_t {
662 let b = uint32x2_t(4_294_967_295, 4_294_967_295);
663 simd_xor(a, b)
664}
665
666/// Vector bitwise not.
667#[inline]
668#[target_feature(enable = "neon")]
669#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
670#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
671#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mvn))]
672pub unsafe fn vmvnq_u32(a: uint32x4_t) -> uint32x4_t {
673 let b = uint32x4_t(4_294_967_295, 4_294_967_295, 4_294_967_295, 4_294_967_295);
674 simd_xor(a, b)
675}
676
677/// Vector bitwise not.
678#[inline]
679#[target_feature(enable = "neon")]
680#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
681#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
682#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mvn))]
683pub unsafe fn vmvn_p8(a: poly8x8_t) -> poly8x8_t {
684 let b = poly8x8_t(255, 255, 255, 255, 255, 255, 255, 255);
685 simd_xor(a, b)
686}
687
688/// Vector bitwise not.
689#[inline]
690#[target_feature(enable = "neon")]
691#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
692#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
693#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mvn))]
694pub unsafe fn vmvnq_p8(a: poly8x16_t) -> poly8x16_t {
695 let b = poly8x16_t(
696 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
697 );
698 simd_xor(a, b)
699}
700
83c7162d
XL		 701/// Folding minimum of adjacent pairs
702#[inline]
703#[target_feature(enable = "neon")]
704#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
705#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
706#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sminp))]
8faf50e0 707pub unsafe fn vpmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
83c7162d
XL		 708 vpmins_v8i8(a, b)
709}
710
711/// Folding minimum of adjacent pairs
712#[inline]
713#[target_feature(enable = "neon")]
714#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
715#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
716#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sminp))]
8faf50e0 717pub unsafe fn vpmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
83c7162d
XL		 718 vpmins_v4i16(a, b)
719}
720
721/// Folding minimum of adjacent pairs
722#[inline]
723#[target_feature(enable = "neon")]
724#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
725#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
726#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sminp))]
8faf50e0 727pub unsafe fn vpmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
83c7162d 728 vpmins_v2i32(a, b)
0531ce1d
XL		 729}
730
83c7162d
XL		 731/// Folding minimum of adjacent pairs
732#[inline]
733#[target_feature(enable = "neon")]
734#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
735#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
736#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uminp))]
8faf50e0 737pub unsafe fn vpmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
83c7162d
XL		 738 vpminu_v8i8(a, b)
739}
740
741/// Folding minimum of adjacent pairs
742#[inline]
743#[target_feature(enable = "neon")]
744#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
745#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
746#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uminp))]
8faf50e0 747pub unsafe fn vpmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
83c7162d
XL		 748 vpminu_v4i16(a, b)
749}
750
751/// Folding minimum of adjacent pairs
752#[inline]
753#[target_feature(enable = "neon")]
754#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
755#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
756#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(uminp))]
8faf50e0 757pub unsafe fn vpmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
83c7162d
XL		 758 vpminu_v2i32(a, b)
759}
760
761/// Folding minimum of adjacent pairs
762#[inline]
763#[target_feature(enable = "neon")]
764#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
765#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
766#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(fminp))]
8faf50e0 767pub unsafe fn vpmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
83c7162d
XL		 768 vpminf_v2f32(a, b)
769}
770
771/// Folding maximum of adjacent pairs
772#[inline]
773#[target_feature(enable = "neon")]
774#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
775#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
776#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(smaxp))]
8faf50e0 777pub unsafe fn vpmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
83c7162d
XL		 778 vpmaxs_v8i8(a, b)
779}
780
781/// Folding maximum of adjacent pairs
782#[inline]
783#[target_feature(enable = "neon")]
784#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
785#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
786#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(smaxp))]
8faf50e0 787pub unsafe fn vpmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
83c7162d
XL		 788 vpmaxs_v4i16(a, b)
789}
790
791/// Folding maximum of adjacent pairs
792#[inline]
793#[target_feature(enable = "neon")]
794#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
795#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
796#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(smaxp))]
8faf50e0 797pub unsafe fn vpmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
83c7162d
XL		 798 vpmaxs_v2i32(a, b)
799}
800
801/// Folding maximum of adjacent pairs
802#[inline]
803#[target_feature(enable = "neon")]
804#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
805#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
806#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(umaxp))]
8faf50e0 807pub unsafe fn vpmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
83c7162d
XL		 808 vpmaxu_v8i8(a, b)
809}
810
811/// Folding maximum of adjacent pairs
812#[inline]
813#[target_feature(enable = "neon")]
814#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
815#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
816#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(umaxp))]
8faf50e0 817pub unsafe fn vpmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
83c7162d
XL		 818 vpmaxu_v4i16(a, b)
819}
820
821/// Folding maximum of adjacent pairs
822#[inline]
823#[target_feature(enable = "neon")]
824#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
825#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
826#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(umaxp))]
8faf50e0 827pub unsafe fn vpmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
83c7162d
XL		 828 vpmaxu_v2i32(a, b)
829}
830
831/// Folding maximum of adjacent pairs
832#[inline]
833#[target_feature(enable = "neon")]
834#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
835#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
836#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(fmaxp))]
8faf50e0 837pub unsafe fn vpmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
83c7162d
XL		 838 vpmaxf_v2f32(a, b)
839}
840
0bf4aa26
XL		 841/// Table look-up
842#[inline]
843#[cfg(target_arch = "arm")]
844#[cfg(target_endian = "little")]
845#[target_feature(enable = "neon,v7")]
846#[cfg_attr(test, assert_instr(vtbl))]
847pub unsafe fn vtbl1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
848 vtbl1(a, b)
849}
850
851/// Table look-up
852#[inline]
853#[cfg(target_arch = "arm")]
854#[cfg(target_endian = "little")]
855#[target_feature(enable = "neon,v7")]
856#[cfg_attr(test, assert_instr(vtbl))]
857pub unsafe fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
532ac7d7 858 transmute(vtbl1(transmute(a), transmute(b)))
0bf4aa26
XL		 859}
860
861/// Table look-up
862#[inline]
863#[cfg(target_arch = "arm")]
864#[cfg(target_endian = "little")]
865#[target_feature(enable = "neon,v7")]
866#[cfg_attr(test, assert_instr(vtbl))]
0731742a 867pub unsafe fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t {
532ac7d7 868 transmute(vtbl1(transmute(a), transmute(b)))
0bf4aa26
XL		 869}
870
871/// Table look-up
872#[inline]
873#[cfg(target_arch = "arm")]
874#[cfg(target_endian = "little")]
875#[target_feature(enable = "neon,v7")]
876#[cfg_attr(test, assert_instr(vtbl))]
877pub unsafe fn vtbl2_s8(a: int8x8x2_t, b: int8x8_t) -> int8x8_t {
878 vtbl2(a.0, a.1, b)
879}
880
881/// Table look-up
882#[inline]
883#[cfg(target_arch = "arm")]
884#[cfg(target_endian = "little")]
885#[target_feature(enable = "neon,v7")]
886#[cfg_attr(test, assert_instr(vtbl))]
887pub unsafe fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t {
532ac7d7 888 transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b)))
0bf4aa26
XL		 889}
890
891/// Table look-up
892#[inline]
893#[cfg(target_arch = "arm")]
894#[cfg(target_endian = "little")]
895#[target_feature(enable = "neon,v7")]
896#[cfg_attr(test, assert_instr(vtbl))]
897pub unsafe fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t {
532ac7d7 898 transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b)))
0bf4aa26
XL		 899}
900
901/// Table look-up
902#[inline]
903#[cfg(target_arch = "arm")]
904#[cfg(target_endian = "little")]
905#[target_feature(enable = "neon,v7")]
906#[cfg_attr(test, assert_instr(vtbl))]
907pub unsafe fn vtbl3_s8(a: int8x8x3_t, b: int8x8_t) -> int8x8_t {
908 vtbl3(a.0, a.1, a.2, b)
909}
910
911/// Table look-up
912#[inline]
913#[cfg(target_arch = "arm")]
914#[cfg(target_endian = "little")]
915#[target_feature(enable = "neon,v7")]
916#[cfg_attr(test, assert_instr(vtbl))]
917pub unsafe fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t {
532ac7d7
XL		 918 transmute(vtbl3(
919 transmute(a.0),
920 transmute(a.1),
921 transmute(a.2),
922 transmute(b),
0bf4aa26
XL		 923 ))
924}
925
926/// Table look-up
927#[inline]
928#[cfg(target_arch = "arm")]
929#[cfg(target_endian = "little")]
930#[target_feature(enable = "neon,v7")]
931#[cfg_attr(test, assert_instr(vtbl))]
932pub unsafe fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t {
532ac7d7
XL		 933 transmute(vtbl3(
934 transmute(a.0),
935 transmute(a.1),
936 transmute(a.2),
937 transmute(b),
0bf4aa26
XL		 938 ))
939}
940
941/// Table look-up
942#[inline]
943#[cfg(target_arch = "arm")]
944#[cfg(target_endian = "little")]
945#[target_feature(enable = "neon,v7")]
946#[cfg_attr(test, assert_instr(vtbl))]
947pub unsafe fn vtbl4_s8(a: int8x8x4_t, b: int8x8_t) -> int8x8_t {
948 vtbl4(a.0, a.1, a.2, a.3, b)
949}
950
951/// Table look-up
952#[inline]
953#[cfg(target_arch = "arm")]
954#[cfg(target_endian = "little")]
955#[target_feature(enable = "neon,v7")]
956#[cfg_attr(test, assert_instr(vtbl))]
957pub unsafe fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t {
532ac7d7
XL		 958 transmute(vtbl4(
959 transmute(a.0),
960 transmute(a.1),
961 transmute(a.2),
962 transmute(a.3),
963 transmute(b),
0bf4aa26
XL		 964 ))
965}
966
967/// Table look-up
968#[inline]
969#[cfg(target_arch = "arm")]
970#[cfg(target_endian = "little")]
971#[target_feature(enable = "neon,v7")]
972#[cfg_attr(test, assert_instr(vtbl))]
973pub unsafe fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t {
532ac7d7
XL		 974 transmute(vtbl4(
975 transmute(a.0),
976 transmute(a.1),
977 transmute(a.2),
978 transmute(a.3),
979 transmute(b),
0bf4aa26
XL		 980 ))
981}
982
983/// Extended table look-up
984#[inline]
985#[cfg(target_arch = "arm")]
986#[cfg(target_endian = "little")]
987#[target_feature(enable = "neon,v7")]
988#[cfg_attr(test, assert_instr(vtbx))]
989pub unsafe fn vtbx1_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
990 vtbx1(a, b, c)
991}
992
993/// Extended table look-up
994#[inline]
995#[cfg(target_arch = "arm")]
996#[cfg(target_endian = "little")]
997#[target_feature(enable = "neon,v7")]
998#[cfg_attr(test, assert_instr(vtbx))]
999pub unsafe fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
532ac7d7 1000 transmute(vtbx1(transmute(a), transmute(b), transmute(c)))
0bf4aa26
XL		 1001}
1002
1003/// Extended table look-up
1004#[inline]
1005#[cfg(target_arch = "arm")]
1006#[cfg(target_endian = "little")]
1007#[target_feature(enable = "neon,v7")]
1008#[cfg_attr(test, assert_instr(vtbx))]
1009pub unsafe fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t {
532ac7d7 1010 transmute(vtbx1(transmute(a), transmute(b), transmute(c)))
0bf4aa26
XL		 1011}
1012
1013/// Extended table look-up
1014#[inline]
1015#[cfg(target_arch = "arm")]
1016#[cfg(target_endian = "little")]
1017#[target_feature(enable = "neon,v7")]
1018#[cfg_attr(test, assert_instr(vtbx))]
1019pub unsafe fn vtbx2_s8(a: int8x8_t, b: int8x8x2_t, c: int8x8_t) -> int8x8_t {
1020 vtbx2(a, b.0, b.1, c)
1021}
1022
1023/// Extended table look-up
1024#[inline]
1025#[cfg(target_arch = "arm")]
1026#[cfg(target_endian = "little")]
1027#[target_feature(enable = "neon,v7")]
1028#[cfg_attr(test, assert_instr(vtbx))]
0731742a 1029pub unsafe fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t {
532ac7d7
XL		 1030 transmute(vtbx2(
1031 transmute(a),
1032 transmute(b.0),
1033 transmute(b.1),
1034 transmute(c),
0bf4aa26
XL		 1035 ))
1036}
1037
1038/// Extended table look-up
1039#[inline]
1040#[cfg(target_arch = "arm")]
1041#[cfg(target_endian = "little")]
1042#[target_feature(enable = "neon,v7")]
1043#[cfg_attr(test, assert_instr(vtbx))]
0731742a 1044pub unsafe fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t {
532ac7d7
XL		 1045 transmute(vtbx2(
1046 transmute(a),
1047 transmute(b.0),
1048 transmute(b.1),
1049 transmute(c),
0bf4aa26
XL		 1050 ))
1051}
1052
1053/// Extended table look-up
1054#[inline]
1055#[cfg(target_arch = "arm")]
1056#[cfg(target_endian = "little")]
1057#[target_feature(enable = "neon,v7")]
1058#[cfg_attr(test, assert_instr(vtbx))]
1059pub unsafe fn vtbx3_s8(a: int8x8_t, b: int8x8x3_t, c: int8x8_t) -> int8x8_t {
1060 vtbx3(a, b.0, b.1, b.2, c)
1061}
1062
1063/// Extended table look-up
1064#[inline]
1065#[cfg(target_arch = "arm")]
1066#[cfg(target_endian = "little")]
1067#[target_feature(enable = "neon,v7")]
1068#[cfg_attr(test, assert_instr(vtbx))]
0731742a 1069pub unsafe fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t {
532ac7d7
XL		 1070 transmute(vtbx3(
1071 transmute(a),
1072 transmute(b.0),
1073 transmute(b.1),
1074 transmute(b.2),
1075 transmute(c),
0bf4aa26
XL		 1076 ))
1077}
1078
1079/// Extended table look-up
1080#[inline]
1081#[cfg(target_arch = "arm")]
1082#[cfg(target_endian = "little")]
1083#[target_feature(enable = "neon,v7")]
1084#[cfg_attr(test, assert_instr(vtbx))]
0731742a 1085pub unsafe fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t {
532ac7d7
XL		 1086 transmute(vtbx3(
1087 transmute(a),
1088 transmute(b.0),
1089 transmute(b.1),
1090 transmute(b.2),
1091 transmute(c),
0bf4aa26
XL		 1092 ))
1093}
1094
1095/// Extended table look-up
1096#[inline]
1097#[cfg(target_arch = "arm")]
1098#[cfg(target_endian = "little")]
1099#[target_feature(enable = "neon,v7")]
1100#[cfg_attr(test, assert_instr(vtbx))]
1101pub unsafe fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t {
1102 vtbx4(a, b.0, b.1, b.2, b.3, c)
1103}
1104
1105/// Extended table look-up
1106#[inline]
1107#[cfg(target_arch = "arm")]
1108#[cfg(target_endian = "little")]
1109#[target_feature(enable = "neon,v7")]
1110#[cfg_attr(test, assert_instr(vtbx))]
0731742a 1111pub unsafe fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t {
532ac7d7
XL		 1112 transmute(vtbx4(
1113 transmute(a),
1114 transmute(b.0),
1115 transmute(b.1),
1116 transmute(b.2),
1117 transmute(b.3),
1118 transmute(c),
0bf4aa26
XL		 1119 ))
1120}
1121
1122/// Extended table look-up
1123#[inline]
1124#[cfg(target_arch = "arm")]
1125#[cfg(target_endian = "little")]
1126#[target_feature(enable = "neon,v7")]
1127#[cfg_attr(test, assert_instr(vtbx))]
0731742a 1128pub unsafe fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t {
532ac7d7
XL		 1129 transmute(vtbx4(
1130 transmute(a),
1131 transmute(b.0),
1132 transmute(b.1),
1133 transmute(b.2),
1134 transmute(b.3),
1135 transmute(c),
0bf4aa26
XL		 1136 ))
1137}
1138
0531ce1d
XL		 1139#[cfg(test)]
1140mod tests {
532ac7d7 1141 use crate::core_arch::{arm::*, simd::*};
48663c56 1142 use std::{i16, i32, i8, mem::transmute, u16, u32, u8};
416331ca 1143 use stdarch_test::simd_test;
0531ce1d 1144
83c7162d
XL		 1145 #[simd_test(enable = "neon")]
1146 unsafe fn test_vadd_s8() {
0531ce1d
XL		 1147 let a = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
1148 let b = i8x8::new(8, 7, 6, 5, 4, 3, 2, 1);
1149 let e = i8x8::new(9, 9, 9, 9, 9, 9, 9, 9);
532ac7d7 1150 let r: i8x8 = transmute(vadd_s8(transmute(a), transmute(b)));
0531ce1d
XL		 1151 assert_eq!(r, e);
1152 }
1153
83c7162d
XL		 1154 #[simd_test(enable = "neon")]
1155 unsafe fn test_vaddq_s8() {
0531ce1d
XL		 1156 let a = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
1157 let b = i8x16::new(8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1);
1158 let e = i8x16::new(9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9);
532ac7d7 1159 let r: i8x16 = transmute(vaddq_s8(transmute(a), transmute(b)));
0531ce1d
XL		 1160 assert_eq!(r, e);
1161 }
1162
83c7162d
XL		 1163 #[simd_test(enable = "neon")]
1164 unsafe fn test_vadd_s16() {
0531ce1d
XL		 1165 let a = i16x4::new(1, 2, 3, 4);
1166 let b = i16x4::new(8, 7, 6, 5);
1167 let e = i16x4::new(9, 9, 9, 9);
532ac7d7 1168 let r: i16x4 = transmute(vadd_s16(transmute(a), transmute(b)));
0531ce1d
XL		 1169 assert_eq!(r, e);
1170 }
1171
83c7162d
XL		 1172 #[simd_test(enable = "neon")]
1173 unsafe fn test_vaddq_s16() {
0531ce1d
XL		 1174 let a = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
1175 let b = i16x8::new(8, 7, 6, 5, 4, 3, 2, 1);
1176 let e = i16x8::new(9, 9, 9, 9, 9, 9, 9, 9);
532ac7d7 1177 let r: i16x8 = transmute(vaddq_s16(transmute(a), transmute(b)));
0531ce1d
XL		 1178 assert_eq!(r, e);
1179 }
1180
83c7162d
XL		 1181 #[simd_test(enable = "neon")]
1182 unsafe fn test_vadd_s32() {
0531ce1d
XL		 1183 let a = i32x2::new(1, 2);
1184 let b = i32x2::new(8, 7);
1185 let e = i32x2::new(9, 9);
532ac7d7 1186 let r: i32x2 = transmute(vadd_s32(transmute(a), transmute(b)));
0531ce1d
XL		 1187 assert_eq!(r, e);
1188 }
1189
83c7162d
XL		 1190 #[simd_test(enable = "neon")]
1191 unsafe fn test_vaddq_s32() {
0531ce1d
XL		 1192 let a = i32x4::new(1, 2, 3, 4);
1193 let b = i32x4::new(8, 7, 6, 5);
1194 let e = i32x4::new(9, 9, 9, 9);
532ac7d7 1195 let r: i32x4 = transmute(vaddq_s32(transmute(a), transmute(b)));
0531ce1d
XL		 1196 assert_eq!(r, e);
1197 }
1198
83c7162d
XL		 1199 #[simd_test(enable = "neon")]
1200 unsafe fn test_vadd_u8() {
0531ce1d
XL		 1201 let a = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
1202 let b = u8x8::new(8, 7, 6, 5, 4, 3, 2, 1);
1203 let e = u8x8::new(9, 9, 9, 9, 9, 9, 9, 9);
532ac7d7 1204 let r: u8x8 = transmute(vadd_u8(transmute(a), transmute(b)));
0531ce1d
XL		 1205 assert_eq!(r, e);
1206 }
1207
83c7162d
XL		 1208 #[simd_test(enable = "neon")]
1209 unsafe fn test_vaddq_u8() {
0531ce1d
XL		 1210 let a = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
1211 let b = u8x16::new(8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1);
1212 let e = u8x16::new(9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9);
532ac7d7 1213 let r: u8x16 = transmute(vaddq_u8(transmute(a), transmute(b)));
0531ce1d
XL		 1214 assert_eq!(r, e);
1215 }
1216
83c7162d
XL		 1217 #[simd_test(enable = "neon")]
1218 unsafe fn test_vadd_u16() {
0531ce1d
XL		 1219 let a = u16x4::new(1, 2, 3, 4);
1220 let b = u16x4::new(8, 7, 6, 5);
1221 let e = u16x4::new(9, 9, 9, 9);
532ac7d7 1222 let r: u16x4 = transmute(vadd_u16(transmute(a), transmute(b)));
0531ce1d
XL		 1223 assert_eq!(r, e);
1224 }
1225
83c7162d
XL		 1226 #[simd_test(enable = "neon")]
1227 unsafe fn test_vaddq_u16() {
0531ce1d
XL		 1228 let a = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
1229 let b = u16x8::new(8, 7, 6, 5, 4, 3, 2, 1);
1230 let e = u16x8::new(9, 9, 9, 9, 9, 9, 9, 9);
532ac7d7 1231 let r: u16x8 = transmute(vaddq_u16(transmute(a), transmute(b)));
0531ce1d
XL		 1232 assert_eq!(r, e);
1233 }
1234
83c7162d
XL		 1235 #[simd_test(enable = "neon")]
1236 unsafe fn test_vadd_u32() {
0531ce1d
XL		 1237 let a = u32x2::new(1, 2);
1238 let b = u32x2::new(8, 7);
1239 let e = u32x2::new(9, 9);
532ac7d7 1240 let r: u32x2 = transmute(vadd_u32(transmute(a), transmute(b)));
0531ce1d
XL		 1241 assert_eq!(r, e);
1242 }
1243
83c7162d
XL		 1244 #[simd_test(enable = "neon")]
1245 unsafe fn test_vaddq_u32() {
0531ce1d
XL		 1246 let a = u32x4::new(1, 2, 3, 4);
1247 let b = u32x4::new(8, 7, 6, 5);
1248 let e = u32x4::new(9, 9, 9, 9);
532ac7d7 1249 let r: u32x4 = transmute(vaddq_u32(transmute(a), transmute(b)));
0531ce1d
XL		 1250 assert_eq!(r, e);
1251 }
1252
83c7162d
XL		 1253 #[simd_test(enable = "neon")]
1254 unsafe fn test_vadd_f32() {
0531ce1d
XL		 1255 let a = f32x2::new(1., 2.);
1256 let b = f32x2::new(8., 7.);
1257 let e = f32x2::new(9., 9.);
532ac7d7 1258 let r: f32x2 = transmute(vadd_f32(transmute(a), transmute(b)));
0531ce1d
XL		 1259 assert_eq!(r, e);
1260 }
1261
83c7162d
XL		 1262 #[simd_test(enable = "neon")]
1263 unsafe fn test_vaddq_f32() {
0531ce1d
XL		 1264 let a = f32x4::new(1., 2., 3., 4.);
1265 let b = f32x4::new(8., 7., 6., 5.);
1266 let e = f32x4::new(9., 9., 9., 9.);
532ac7d7 1267 let r: f32x4 = transmute(vaddq_f32(transmute(a), transmute(b)));
0531ce1d
XL		 1268 assert_eq!(r, e);
1269 }
1270
83c7162d
XL		 1271 #[simd_test(enable = "neon")]
1272 unsafe fn test_vaddl_s8() {
48663c56 1273 let v = i8::MAX;
0531ce1d
XL		 1274 let a = i8x8::new(v, v, v, v, v, v, v, v);
1275 let v = 2 * (v as i16);
1276 let e = i16x8::new(v, v, v, v, v, v, v, v);
532ac7d7 1277 let r: i16x8 = transmute(vaddl_s8(transmute(a), transmute(a)));
0531ce1d
XL		 1278 assert_eq!(r, e);
1279 }
1280
83c7162d
XL		 1281 #[simd_test(enable = "neon")]
1282 unsafe fn test_vaddl_s16() {
48663c56 1283 let v = i16::MAX;
0531ce1d
XL		 1284 let a = i16x4::new(v, v, v, v);
1285 let v = 2 * (v as i32);
1286 let e = i32x4::new(v, v, v, v);
532ac7d7 1287 let r: i32x4 = transmute(vaddl_s16(transmute(a), transmute(a)));
0531ce1d
XL		 1288 assert_eq!(r, e);
1289 }
1290
83c7162d
XL		 1291 #[simd_test(enable = "neon")]
1292 unsafe fn test_vaddl_s32() {
48663c56 1293 let v = i32::MAX;
0531ce1d
XL		 1294 let a = i32x2::new(v, v);
1295 let v = 2 * (v as i64);
1296 let e = i64x2::new(v, v);
532ac7d7 1297 let r: i64x2 = transmute(vaddl_s32(transmute(a), transmute(a)));
0531ce1d
XL		 1298 assert_eq!(r, e);
1299 }
1300
83c7162d
XL		 1301 #[simd_test(enable = "neon")]
1302 unsafe fn test_vaddl_u8() {
48663c56 1303 let v = u8::MAX;
0531ce1d
XL		 1304 let a = u8x8::new(v, v, v, v, v, v, v, v);
1305 let v = 2 * (v as u16);
1306 let e = u16x8::new(v, v, v, v, v, v, v, v);
532ac7d7 1307 let r: u16x8 = transmute(vaddl_u8(transmute(a), transmute(a)));
0531ce1d
XL		 1308 assert_eq!(r, e);
1309 }
1310
83c7162d
XL		 1311 #[simd_test(enable = "neon")]
1312 unsafe fn test_vaddl_u16() {
48663c56 1313 let v = u16::MAX;
0531ce1d
XL		 1314 let a = u16x4::new(v, v, v, v);
1315 let v = 2 * (v as u32);
1316 let e = u32x4::new(v, v, v, v);
532ac7d7 1317 let r: u32x4 = transmute(vaddl_u16(transmute(a), transmute(a)));
0531ce1d
XL		 1318 assert_eq!(r, e);
1319 }
1320
83c7162d
XL		 1321 #[simd_test(enable = "neon")]
1322 unsafe fn test_vaddl_u32() {
48663c56 1323 let v = u32::MAX;
0531ce1d
XL		 1324 let a = u32x2::new(v, v);
1325 let v = 2 * (v as u64);
1326 let e = u64x2::new(v, v);
532ac7d7 1327 let r: u64x2 = transmute(vaddl_u32(transmute(a), transmute(a)));
0531ce1d
XL		 1328 assert_eq!(r, e);
1329 }
1330
416331ca
XL		 1331 #[simd_test(enable = "neon")]
1332 unsafe fn test_vmvn_s8() {
1333 let a = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
1334 let e = i8x8::new(-1, -2, -3, -4, -5, -6, -7, -8);
1335 let r: i8x8 = transmute(vmvn_s8(transmute(a)));
1336 assert_eq!(r, e);
1337 }
1338
1339 #[simd_test(enable = "neon")]
1340 unsafe fn test_vmvnq_s8() {
1341 let a = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
1342 let e = i8x16::new(
1343 -1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11, -12, -13, -14, -15, -16,
1344 );
1345 let r: i8x16 = transmute(vmvnq_s8(transmute(a)));
1346 assert_eq!(r, e);
1347 }
1348
1349 #[simd_test(enable = "neon")]
1350 unsafe fn test_vmvn_s16() {
1351 let a = i16x4::new(0, 1, 2, 3);
1352 let e = i16x4::new(-1, -2, -3, -4);
1353 let r: i16x4 = transmute(vmvn_s16(transmute(a)));
1354 assert_eq!(r, e);
1355 }
1356
1357 #[simd_test(enable = "neon")]
1358 unsafe fn test_vmvnq_s16() {
1359 let a = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
1360 let e = i16x8::new(-1, -2, -3, -4, -5, -6, -7, -8);
1361 let r: i16x8 = transmute(vmvnq_s16(transmute(a)));
1362 assert_eq!(r, e);
1363 }
1364
1365 #[simd_test(enable = "neon")]
1366 unsafe fn test_vmvn_s32() {
1367 let a = i32x2::new(0, 1);
1368 let e = i32x2::new(-1, -2);
1369 let r: i32x2 = transmute(vmvn_s32(transmute(a)));
1370 assert_eq!(r, e);
1371 }
1372
1373 #[simd_test(enable = "neon")]
1374 unsafe fn test_vmvnq_s32() {
1375 let a = i32x4::new(0, 1, 2, 3);
1376 let e = i32x4::new(-1, -2, -3, -4);
1377 let r: i32x4 = transmute(vmvnq_s32(transmute(a)));
1378 assert_eq!(r, e);
1379 }
1380
1381 #[simd_test(enable = "neon")]
1382 unsafe fn test_vmvn_u8() {
1383 let a = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
1384 let e = u8x8::new(255, 254, 253, 252, 251, 250, 249, 248);
1385 let r: u8x8 = transmute(vmvn_u8(transmute(a)));
1386 assert_eq!(r, e);
1387 }
1388
1389 #[simd_test(enable = "neon")]
1390 unsafe fn test_vmvnq_u8() {
1391 let a = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
1392 let e = u8x16::new(
1393 255, 254, 253, 252, 251, 250, 249, 248, 247, 246, 245, 244, 243, 242, 241, 240,
1394 );
1395 let r: u8x16 = transmute(vmvnq_u8(transmute(a)));
1396 assert_eq!(r, e);
1397 }
1398
1399 #[simd_test(enable = "neon")]
1400 unsafe fn test_vmvn_u16() {
1401 let a = u16x4::new(0, 1, 2, 3);
1402 let e = u16x4::new(65_535, 65_534, 65_533, 65_532);
1403 let r: u16x4 = transmute(vmvn_u16(transmute(a)));
1404 assert_eq!(r, e);
1405 }
1406
1407 #[simd_test(enable = "neon")]
1408 unsafe fn test_vmvnq_u16() {
1409 let a = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
1410 let e = u16x8::new(
1411 65_535, 65_534, 65_533, 65_532, 65_531, 65_530, 65_529, 65_528,
1412 );
1413 let r: u16x8 = transmute(vmvnq_u16(transmute(a)));
1414 assert_eq!(r, e);
1415 }
1416
1417 #[simd_test(enable = "neon")]
1418 unsafe fn test_vmvn_u32() {
1419 let a = u32x2::new(0, 1);
1420 let e = u32x2::new(4_294_967_295, 4_294_967_294);
1421 let r: u32x2 = transmute(vmvn_u32(transmute(a)));
1422 assert_eq!(r, e);
1423 }
1424
1425 #[simd_test(enable = "neon")]
1426 unsafe fn test_vmvnq_u32() {
1427 let a = u32x4::new(0, 1, 2, 3);
1428 let e = u32x4::new(4_294_967_295, 4_294_967_294, 4_294_967_293, 4_294_967_292);
1429 let r: u32x4 = transmute(vmvnq_u32(transmute(a)));
1430 assert_eq!(r, e);
1431 }
1432
1433 #[simd_test(enable = "neon")]
1434 unsafe fn test_vmvn_p8() {
1435 let a = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
1436 let e = u8x8::new(255, 254, 253, 252, 251, 250, 249, 248);
1437 let r: u8x8 = transmute(vmvn_p8(transmute(a)));
1438 assert_eq!(r, e);
1439 }
1440
1441 #[simd_test(enable = "neon")]
1442 unsafe fn test_vmvnq_p8() {
1443 let a = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
1444 let e = u8x16::new(
1445 255, 254, 253, 252, 251, 250, 249, 248, 247, 246, 245, 244, 243, 242, 241, 240,
1446 );
1447 let r: u8x16 = transmute(vmvnq_p8(transmute(a)));
1448 assert_eq!(r, e);
1449 }
1450
83c7162d
XL		 1451 #[simd_test(enable = "neon")]
1452 unsafe fn test_vmovn_s16() {
0531ce1d
XL		 1453 let a = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
1454 let e = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
532ac7d7 1455 let r: i8x8 = transmute(vmovn_s16(transmute(a)));
0531ce1d
XL		 1456 assert_eq!(r, e);
1457 }
1458
83c7162d
XL		 1459 #[simd_test(enable = "neon")]
1460 unsafe fn test_vmovn_s32() {
0531ce1d
XL		 1461 let a = i32x4::new(1, 2, 3, 4);
1462 let e = i16x4::new(1, 2, 3, 4);
532ac7d7 1463 let r: i16x4 = transmute(vmovn_s32(transmute(a)));
0531ce1d
XL		 1464 assert_eq!(r, e);
1465 }
1466
83c7162d
XL		 1467 #[simd_test(enable = "neon")]
1468 unsafe fn test_vmovn_s64() {
0531ce1d
XL		 1469 let a = i64x2::new(1, 2);
1470 let e = i32x2::new(1, 2);
532ac7d7 1471 let r: i32x2 = transmute(vmovn_s64(transmute(a)));
0531ce1d
XL		 1472 assert_eq!(r, e);
1473 }
1474
83c7162d
XL		 1475 #[simd_test(enable = "neon")]
1476 unsafe fn test_vmovn_u16() {
0531ce1d
XL		 1477 let a = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
1478 let e = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
532ac7d7 1479 let r: u8x8 = transmute(vmovn_u16(transmute(a)));
0531ce1d
XL		 1480 assert_eq!(r, e);
1481 }
1482
83c7162d
XL		 1483 #[simd_test(enable = "neon")]
1484 unsafe fn test_vmovn_u32() {
0531ce1d
XL		 1485 let a = u32x4::new(1, 2, 3, 4);
1486 let e = u16x4::new(1, 2, 3, 4);
532ac7d7 1487 let r: u16x4 = transmute(vmovn_u32(transmute(a)));
0531ce1d
XL		 1488 assert_eq!(r, e);
1489 }
1490
83c7162d
XL		 1491 #[simd_test(enable = "neon")]
1492 unsafe fn test_vmovn_u64() {
0531ce1d
XL		 1493 let a = u64x2::new(1, 2);
1494 let e = u32x2::new(1, 2);
532ac7d7 1495 let r: u32x2 = transmute(vmovn_u64(transmute(a)));
0531ce1d
XL		 1496 assert_eq!(r, e);
1497 }
1498
83c7162d
XL		 1499 #[simd_test(enable = "neon")]
1500 unsafe fn test_vmovl_s8() {
0531ce1d
XL		 1501 let e = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
1502 let a = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
532ac7d7 1503 let r: i16x8 = transmute(vmovl_s8(transmute(a)));
0531ce1d
XL		 1504 assert_eq!(r, e);
1505 }
1506
83c7162d
XL		 1507 #[simd_test(enable = "neon")]
1508 unsafe fn test_vmovl_s16() {
0531ce1d
XL		 1509 let e = i32x4::new(1, 2, 3, 4);
1510 let a = i16x4::new(1, 2, 3, 4);
532ac7d7 1511 let r: i32x4 = transmute(vmovl_s16(transmute(a)));
0531ce1d
XL		 1512 assert_eq!(r, e);
1513 }
1514
83c7162d
XL		 1515 #[simd_test(enable = "neon")]
1516 unsafe fn test_vmovl_s32() {
0531ce1d
XL		 1517 let e = i64x2::new(1, 2);
1518 let a = i32x2::new(1, 2);
532ac7d7 1519 let r: i64x2 = transmute(vmovl_s32(transmute(a)));
0531ce1d
XL		 1520 assert_eq!(r, e);
1521 }
1522
83c7162d
XL		 1523 #[simd_test(enable = "neon")]
1524 unsafe fn test_vmovl_u8() {
0531ce1d
XL		 1525 let e = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
1526 let a = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
532ac7d7 1527 let r: u16x8 = transmute(vmovl_u8(transmute(a)));
0531ce1d
XL		 1528 assert_eq!(r, e);
1529 }
1530
83c7162d
XL		 1531 #[simd_test(enable = "neon")]
1532 unsafe fn test_vmovl_u16() {
0531ce1d
XL		 1533 let e = u32x4::new(1, 2, 3, 4);
1534 let a = u16x4::new(1, 2, 3, 4);
532ac7d7 1535 let r: u32x4 = transmute(vmovl_u16(transmute(a)));
0531ce1d
XL		 1536 assert_eq!(r, e);
1537 }
1538
83c7162d
XL		 1539 #[simd_test(enable = "neon")]
1540 unsafe fn test_vmovl_u32() {
0531ce1d
XL		 1541 let e = u64x2::new(1, 2);
1542 let a = u32x2::new(1, 2);
532ac7d7 1543 let r: u64x2 = transmute(vmovl_u32(transmute(a)));
83c7162d
XL		 1544 assert_eq!(r, e);
1545 }
1546
1547 #[simd_test(enable = "neon")]
1548 unsafe fn test_vrsqrt_f32() {
1549 let a = f32x2::new(1.0, 2.0);
1550 let e = f32x2::new(0.9980469, 0.7050781);
532ac7d7 1551 let r: f32x2 = transmute(vrsqrte_f32(transmute(a)));
83c7162d
XL		 1552 assert_eq!(r, e);
1553 }
1554
1555 #[simd_test(enable = "neon")]
1556 unsafe fn test_vpmin_s8() {
1557 let a = i8x8::new(1, -2, 3, -4, 5, 6, 7, 8);
1558 let b = i8x8::new(0, 3, 2, 5, 4, 7, 6, 9);
1559 let e = i8x8::new(-2, -4, 5, 7, 0, 2, 4, 6);
532ac7d7 1560 let r: i8x8 = transmute(vpmin_s8(transmute(a), transmute(b)));
83c7162d
XL		 1561 assert_eq!(r, e);
1562 }
1563
1564 #[simd_test(enable = "neon")]
1565 unsafe fn test_vpmin_s16() {
1566 let a = i16x4::new(1, 2, 3, -4);
1567 let b = i16x4::new(0, 3, 2, 5);
1568 let e = i16x4::new(1, -4, 0, 2);
532ac7d7 1569 let r: i16x4 = transmute(vpmin_s16(transmute(a), transmute(b)));
83c7162d
XL		 1570 assert_eq!(r, e);
1571 }
1572
1573 #[simd_test(enable = "neon")]
1574 unsafe fn test_vpmin_s32() {
1575 let a = i32x2::new(1, -2);
1576 let b = i32x2::new(0, 3);
1577 let e = i32x2::new(-2, 0);
532ac7d7 1578 let r: i32x2 = transmute(vpmin_s32(transmute(a), transmute(b)));
83c7162d
XL		 1579 assert_eq!(r, e);
1580 }
1581
1582 #[simd_test(enable = "neon")]
1583 unsafe fn test_vpmin_u8() {
1584 let a = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
1585 let b = u8x8::new(0, 3, 2, 5, 4, 7, 6, 9);
1586 let e = u8x8::new(1, 3, 5, 7, 0, 2, 4, 6);
532ac7d7 1587 let r: u8x8 = transmute(vpmin_u8(transmute(a), transmute(b)));
83c7162d
XL		 1588 assert_eq!(r, e);
1589 }
1590
1591 #[simd_test(enable = "neon")]
1592 unsafe fn test_vpmin_u16() {
1593 let a = u16x4::new(1, 2, 3, 4);
1594 let b = u16x4::new(0, 3, 2, 5);
1595 let e = u16x4::new(1, 3, 0, 2);
532ac7d7 1596 let r: u16x4 = transmute(vpmin_u16(transmute(a), transmute(b)));
83c7162d
XL		 1597 assert_eq!(r, e);
1598 }
1599
1600 #[simd_test(enable = "neon")]
1601 unsafe fn test_vpmin_u32() {
1602 let a = u32x2::new(1, 2);
1603 let b = u32x2::new(0, 3);
1604 let e = u32x2::new(1, 0);
532ac7d7 1605 let r: u32x2 = transmute(vpmin_u32(transmute(a), transmute(b)));
83c7162d
XL		 1606 assert_eq!(r, e);
1607 }
1608
1609 #[simd_test(enable = "neon")]
1610 unsafe fn test_vpmin_f32() {
1611 let a = f32x2::new(1., -2.);
1612 let b = f32x2::new(0., 3.);
1613 let e = f32x2::new(-2., 0.);
532ac7d7 1614 let r: f32x2 = transmute(vpmin_f32(transmute(a), transmute(b)));
83c7162d
XL		 1615 assert_eq!(r, e);
1616 }
1617
1618 #[simd_test(enable = "neon")]
1619 unsafe fn test_vpmax_s8() {
1620 let a = i8x8::new(1, -2, 3, -4, 5, 6, 7, 8);
1621 let b = i8x8::new(0, 3, 2, 5, 4, 7, 6, 9);
1622 let e = i8x8::new(1, 3, 6, 8, 3, 5, 7, 9);
532ac7d7 1623 let r: i8x8 = transmute(vpmax_s8(transmute(a), transmute(b)));
83c7162d
XL		 1624 assert_eq!(r, e);
1625 }
1626
1627 #[simd_test(enable = "neon")]
1628 unsafe fn test_vpmax_s16() {
1629 let a = i16x4::new(1, 2, 3, -4);
1630 let b = i16x4::new(0, 3, 2, 5);
1631 let e = i16x4::new(2, 3, 3, 5);
532ac7d7 1632 let r: i16x4 = transmute(vpmax_s16(transmute(a), transmute(b)));
83c7162d
XL		 1633 assert_eq!(r, e);
1634 }
1635
1636 #[simd_test(enable = "neon")]
1637 unsafe fn test_vpmax_s32() {
1638 let a = i32x2::new(1, -2);
1639 let b = i32x2::new(0, 3);
1640 let e = i32x2::new(1, 3);
532ac7d7 1641 let r: i32x2 = transmute(vpmax_s32(transmute(a), transmute(b)));
83c7162d
XL		 1642 assert_eq!(r, e);
1643 }
1644
1645 #[simd_test(enable = "neon")]
1646 unsafe fn test_vpmax_u8() {
1647 let a = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
1648 let b = u8x8::new(0, 3, 2, 5, 4, 7, 6, 9);
1649 let e = u8x8::new(2, 4, 6, 8, 3, 5, 7, 9);
532ac7d7 1650 let r: u8x8 = transmute(vpmax_u8(transmute(a), transmute(b)));
83c7162d
XL		 1651 assert_eq!(r, e);
1652 }
1653
1654 #[simd_test(enable = "neon")]
1655 unsafe fn test_vpmax_u16() {
1656 let a = u16x4::new(1, 2, 3, 4);
1657 let b = u16x4::new(0, 3, 2, 5);
1658 let e = u16x4::new(2, 4, 3, 5);
532ac7d7 1659 let r: u16x4 = transmute(vpmax_u16(transmute(a), transmute(b)));
83c7162d
XL		 1660 assert_eq!(r, e);
1661 }
1662
1663 #[simd_test(enable = "neon")]
1664 unsafe fn test_vpmax_u32() {
1665 let a = u32x2::new(1, 2);
1666 let b = u32x2::new(0, 3);
1667 let e = u32x2::new(2, 3);
532ac7d7 1668 let r: u32x2 = transmute(vpmax_u32(transmute(a), transmute(b)));
83c7162d
XL		 1669 assert_eq!(r, e);
1670 }
1671
1672 #[simd_test(enable = "neon")]
1673 unsafe fn test_vpmax_f32() {
1674 let a = f32x2::new(1., -2.);
1675 let b = f32x2::new(0., 3.);
1676 let e = f32x2::new(1., 3.);
532ac7d7 1677 let r: f32x2 = transmute(vpmax_f32(transmute(a), transmute(b)));
0531ce1d
XL		 1678 assert_eq!(r, e);
1679 }
1680}
0bf4aa26
XL		 1681
1682#[cfg(test)]
1683#[cfg(target_endian = "little")]
1684#[path = "table_lookup_tests.rs"]
1685mod table_lookup_tests;
backport for Debian buster