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Merge tag 'pull-riscv-to-apply-20230224' of github.com:palmer-dabbelt/qemu into staging
[mirror_qemu.git] / target / arm / cpu_tcg.c
CommitLineData
2465b07c
PMD		 1/*
2 * QEMU ARM TCG CPUs.
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This code is licensed under the GNU GPL v2 or later.
7 *
8 * SPDX-License-Identifier: GPL-2.0-or-later
9 */
10
11#include "qemu/osdep.h"
12#include "cpu.h"
78271684
CF		 13#ifdef CONFIG_TCG
14#include "hw/core/tcg-cpu-ops.h"
15#endif /* CONFIG_TCG */
2465b07c 16#include "internals.h"
6e937ba7 17#include "target/arm/idau.h"
80485d88
PMD		 18#if !defined(CONFIG_USER_ONLY)
19#include "hw/boards.h"
20#endif
cf7c6d10 21#include "cpregs.h"
165876f2
PMD		 22#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
23#include "hw/intc/armv7m_nvic.h"
24#endif
2465b07c 25
b6f8b358
RH		 26
27/* Share AArch32 -cpu max features with AArch64. */
28void aa32_max_features(ARMCPU *cpu)
29{
30 uint32_t t;
31
32 /* Add additional features supported by QEMU */
33 t = cpu->isar.id_isar5;
ef696cfb
RH		 34 t = FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */
35 t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */
36 t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */
b6f8b358 37 t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
ef696cfb
RH		 38 t = FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */
39 t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */
b6f8b358
RH		 40 cpu->isar.id_isar5 = t;
41
42 t = cpu->isar.id_isar6;
ef696cfb
RH		 43 t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */
44 t = FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */
45 t = FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */
46 t = FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */
47 t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */
48 t = FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */
49 t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */
b6f8b358
RH		 50 cpu->isar.id_isar6 = t;
51
52 t = cpu->isar.mvfr1;
ef696cfb
RH		 53 t = FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */
54 t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */
b6f8b358
RH		 55 cpu->isar.mvfr1 = t;
56
57 t = cpu->isar.mvfr2;
ef696cfb
RH		 58 t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
59 t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
b6f8b358
RH		 60 cpu->isar.mvfr2 = t;
61
62 t = cpu->isar.id_mmfr3;
ef696cfb 63 t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */
b6f8b358
RH		 64 cpu->isar.id_mmfr3 = t;
65
66 t = cpu->isar.id_mmfr4;
ef696cfb
RH		 67 t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* FEAT_AA32HPD */
68 t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
69 t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */
bb7d9021 70 t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */
41654f12 71 t = FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT */
b6f8b358
RH		 72 cpu->isar.id_mmfr4 = t;
73
3fe72e21
PM		 74 t = cpu->isar.id_mmfr5;
75 t = FIELD_DP32(t, ID_MMFR5, ETS, 1); /* FEAT_ETS */
76 cpu->isar.id_mmfr5 = t;
77
b6f8b358 78 t = cpu->isar.id_pfr0;
74b17e16 79 t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */
ef696cfb 80 t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
e95c74c5 81 t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */
b6f8b358
RH		 82 cpu->isar.id_pfr0 = t;
83
84 t = cpu->isar.id_pfr2;
3082b86b 85 t = FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */
ef696cfb 86 t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */
b6f8b358
RH		 87 cpu->isar.id_pfr2 = t;
88
89 t = cpu->isar.id_dfr0;
8fc756b6
RH		 90 t = FIELD_DP32(t, ID_DFR0, COPDBG, 9); /* FEAT_Debugv8p4 */
91 t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */
e31e0f56 92 t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */
b6f8b358
RH		 93 cpu->isar.id_dfr0 = t;
94}
95
7c1aaf98
RH		 96#ifndef CONFIG_USER_ONLY
97static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
98{
99 ARMCPU *cpu = env_archcpu(env);
100
101 /* Number of cores is in [25:24]; otherwise we RAZ */
102 return (cpu->core_count - 1) << 24;
103}
104
105static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
106 { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
107 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
108 .access = PL1_RW, .readfn = l2ctlr_read,
109 .writefn = arm_cp_write_ignore },
110 { .name = "L2CTLR",
111 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
112 .access = PL1_RW, .readfn = l2ctlr_read,
113 .writefn = arm_cp_write_ignore },
114 { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
115 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
116 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
117 { .name = "L2ECTLR",
118 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
119 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
120 { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
121 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
122 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
123 { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
124 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
125 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
126 { .name = "CPUACTLR",
127 .cp = 15, .opc1 = 0, .crm = 15,
128 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
129 { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
130 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
131 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
132 { .name = "CPUECTLR",
133 .cp = 15, .opc1 = 1, .crm = 15,
134 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
135 { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
136 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
137 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
138 { .name = "CPUMERRSR",
139 .cp = 15, .opc1 = 2, .crm = 15,
140 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
141 { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
142 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
143 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
144 { .name = "L2MERRSR",
145 .cp = 15, .opc1 = 3, .crm = 15,
146 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
147};
148
149void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu)
150{
151 define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
152}
153#endif /* !CONFIG_USER_ONLY */
154
2465b07c
PMD		 155/* CPU models. These are not needed for the AArch64 linux-user build. */
156#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
157
083afd18 158#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
2465b07c
PMD		 159static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
160{
161 CPUClass *cc = CPU_GET_CLASS(cs);
162 ARMCPU *cpu = ARM_CPU(cs);
163 CPUARMState *env = &cpu->env;
164 bool ret = false;
165
166 /*
167 * ARMv7-M interrupt masking works differently than -A or -R.
168 * There is no FIQ/IRQ distinction. Instead of I and F bits
169 * masking FIQ and IRQ interrupts, an exception is taken only
170 * if it is higher priority than the current execution priority
171 * (which depends on state like BASEPRI, FAULTMASK and the
172 * currently active exception).
173 */
174 if (interrupt_request & CPU_INTERRUPT_HARD
175 && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
176 cs->exception_index = EXCP_IRQ;
78271684 177 cc->tcg_ops->do_interrupt(cs);
2465b07c
PMD		 178 ret = true;
179 }
180 return ret;
181}
083afd18 182#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
2465b07c
PMD		 183
184static void arm926_initfn(Object *obj)
185{
186 ARMCPU *cpu = ARM_CPU(obj);
187
188 cpu->dtb_compatible = "arm,arm926";
189 set_feature(&cpu->env, ARM_FEATURE_V5);
190 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
191 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
192 cpu->midr = 0x41069265;
193 cpu->reset_fpsid = 0x41011090;
194 cpu->ctr = 0x1dd20d2;
195 cpu->reset_sctlr = 0x00090078;
196
197 /*
198 * ARMv5 does not have the ID_ISAR registers, but we can still
199 * set the field to indicate Jazelle support within QEMU.
200 */
201 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
202 /*
203 * Similarly, we need to set MVFR0 fields to enable vfp and short vector
204 * support even though ARMv5 doesn't have this register.
205 */
206 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
207 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
208 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
209}
210
211static void arm946_initfn(Object *obj)
212{
213 ARMCPU *cpu = ARM_CPU(obj);
214
215 cpu->dtb_compatible = "arm,arm946";
216 set_feature(&cpu->env, ARM_FEATURE_V5);
217 set_feature(&cpu->env, ARM_FEATURE_PMSA);
218 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
219 cpu->midr = 0x41059461;
220 cpu->ctr = 0x0f004006;
221 cpu->reset_sctlr = 0x00000078;
222}
223
224static void arm1026_initfn(Object *obj)
225{
226 ARMCPU *cpu = ARM_CPU(obj);
227
228 cpu->dtb_compatible = "arm,arm1026";
229 set_feature(&cpu->env, ARM_FEATURE_V5);
230 set_feature(&cpu->env, ARM_FEATURE_AUXCR);
231 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
232 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
233 cpu->midr = 0x4106a262;
234 cpu->reset_fpsid = 0x410110a0;
235 cpu->ctr = 0x1dd20d2;
236 cpu->reset_sctlr = 0x00090078;
237 cpu->reset_auxcr = 1;
238
239 /*
240 * ARMv5 does not have the ID_ISAR registers, but we can still
241 * set the field to indicate Jazelle support within QEMU.
242 */
243 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
244 /*
245 * Similarly, we need to set MVFR0 fields to enable vfp and short vector
246 * support even though ARMv5 doesn't have this register.
247 */
248 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
249 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
250 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
251
252 {
253 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
254 ARMCPRegInfo ifar = {
255 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
256 .access = PL1_RW,
257 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
258 .resetvalue = 0
259 };
260 define_one_arm_cp_reg(cpu, &ifar);
261 }
262}
263
264static void arm1136_r2_initfn(Object *obj)
265{
266 ARMCPU *cpu = ARM_CPU(obj);
267 /*
268 * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
269 * older core than plain "arm1136". In particular this does not
270 * have the v6K features.
271 * These ID register values are correct for 1136 but may be wrong
272 * for 1136_r2 (in particular r0p2 does not actually implement most
273 * of the ID registers).
274 */
275
276 cpu->dtb_compatible = "arm,arm1136";
277 set_feature(&cpu->env, ARM_FEATURE_V6);
278 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
279 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
280 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
281 cpu->midr = 0x4107b362;
282 cpu->reset_fpsid = 0x410120b4;
283 cpu->isar.mvfr0 = 0x11111111;
284 cpu->isar.mvfr1 = 0x00000000;
285 cpu->ctr = 0x1dd20d2;
286 cpu->reset_sctlr = 0x00050078;
8a130a7b
PM		 287 cpu->isar.id_pfr0 = 0x111;
288 cpu->isar.id_pfr1 = 0x1;
2465b07c
PMD		 289 cpu->isar.id_dfr0 = 0x2;
290 cpu->id_afr0 = 0x3;
291 cpu->isar.id_mmfr0 = 0x01130003;
292 cpu->isar.id_mmfr1 = 0x10030302;
293 cpu->isar.id_mmfr2 = 0x01222110;
294 cpu->isar.id_isar0 = 0x00140011;
295 cpu->isar.id_isar1 = 0x12002111;
296 cpu->isar.id_isar2 = 0x11231111;
297 cpu->isar.id_isar3 = 0x01102131;
298 cpu->isar.id_isar4 = 0x141;
299 cpu->reset_auxcr = 7;
300}
301
302static void arm1136_initfn(Object *obj)
303{
304 ARMCPU *cpu = ARM_CPU(obj);
305
306 cpu->dtb_compatible = "arm,arm1136";
307 set_feature(&cpu->env, ARM_FEATURE_V6K);
308 set_feature(&cpu->env, ARM_FEATURE_V6);
309 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
310 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
311 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
312 cpu->midr = 0x4117b363;
313 cpu->reset_fpsid = 0x410120b4;
314 cpu->isar.mvfr0 = 0x11111111;
315 cpu->isar.mvfr1 = 0x00000000;
316 cpu->ctr = 0x1dd20d2;
317 cpu->reset_sctlr = 0x00050078;
8a130a7b
PM		 318 cpu->isar.id_pfr0 = 0x111;
319 cpu->isar.id_pfr1 = 0x1;
2465b07c
PMD		 320 cpu->isar.id_dfr0 = 0x2;
321 cpu->id_afr0 = 0x3;
322 cpu->isar.id_mmfr0 = 0x01130003;
323 cpu->isar.id_mmfr1 = 0x10030302;
324 cpu->isar.id_mmfr2 = 0x01222110;
325 cpu->isar.id_isar0 = 0x00140011;
326 cpu->isar.id_isar1 = 0x12002111;
327 cpu->isar.id_isar2 = 0x11231111;
328 cpu->isar.id_isar3 = 0x01102131;
329 cpu->isar.id_isar4 = 0x141;
330 cpu->reset_auxcr = 7;
331}
332
333static void arm1176_initfn(Object *obj)
334{
335 ARMCPU *cpu = ARM_CPU(obj);
336
337 cpu->dtb_compatible = "arm,arm1176";
338 set_feature(&cpu->env, ARM_FEATURE_V6K);
339 set_feature(&cpu->env, ARM_FEATURE_VAPA);
340 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
341 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
342 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
343 set_feature(&cpu->env, ARM_FEATURE_EL3);
344 cpu->midr = 0x410fb767;
345 cpu->reset_fpsid = 0x410120b5;
346 cpu->isar.mvfr0 = 0x11111111;
347 cpu->isar.mvfr1 = 0x00000000;
348 cpu->ctr = 0x1dd20d2;
349 cpu->reset_sctlr = 0x00050078;
8a130a7b
PM		 350 cpu->isar.id_pfr0 = 0x111;
351 cpu->isar.id_pfr1 = 0x11;
2465b07c
PMD		 352 cpu->isar.id_dfr0 = 0x33;
353 cpu->id_afr0 = 0;
354 cpu->isar.id_mmfr0 = 0x01130003;
355 cpu->isar.id_mmfr1 = 0x10030302;
356 cpu->isar.id_mmfr2 = 0x01222100;
357 cpu->isar.id_isar0 = 0x0140011;
358 cpu->isar.id_isar1 = 0x12002111;
359 cpu->isar.id_isar2 = 0x11231121;
360 cpu->isar.id_isar3 = 0x01102131;
361 cpu->isar.id_isar4 = 0x01141;
362 cpu->reset_auxcr = 7;
363}
364
365static void arm11mpcore_initfn(Object *obj)
366{
367 ARMCPU *cpu = ARM_CPU(obj);
368
369 cpu->dtb_compatible = "arm,arm11mpcore";
370 set_feature(&cpu->env, ARM_FEATURE_V6K);
371 set_feature(&cpu->env, ARM_FEATURE_VAPA);
372 set_feature(&cpu->env, ARM_FEATURE_MPIDR);
373 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
374 cpu->midr = 0x410fb022;
375 cpu->reset_fpsid = 0x410120b4;
376 cpu->isar.mvfr0 = 0x11111111;
377 cpu->isar.mvfr1 = 0x00000000;
378 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
8a130a7b
PM		 379 cpu->isar.id_pfr0 = 0x111;
380 cpu->isar.id_pfr1 = 0x1;
2465b07c
PMD		 381 cpu->isar.id_dfr0 = 0;
382 cpu->id_afr0 = 0x2;
383 cpu->isar.id_mmfr0 = 0x01100103;
384 cpu->isar.id_mmfr1 = 0x10020302;
385 cpu->isar.id_mmfr2 = 0x01222000;
386 cpu->isar.id_isar0 = 0x00100011;
387 cpu->isar.id_isar1 = 0x12002111;
388 cpu->isar.id_isar2 = 0x11221011;
389 cpu->isar.id_isar3 = 0x01102131;
390 cpu->isar.id_isar4 = 0x141;
391 cpu->reset_auxcr = 1;
392}
393
80485d88
PMD		 394static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
395 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
396 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
397 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
398 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
80485d88
PMD		 399};
400
401static void cortex_a8_initfn(Object *obj)
402{
403 ARMCPU *cpu = ARM_CPU(obj);
404
405 cpu->dtb_compatible = "arm,cortex-a8";
406 set_feature(&cpu->env, ARM_FEATURE_V7);
407 set_feature(&cpu->env, ARM_FEATURE_NEON);
408 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
409 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
410 set_feature(&cpu->env, ARM_FEATURE_EL3);
411 cpu->midr = 0x410fc080;
412 cpu->reset_fpsid = 0x410330c0;
413 cpu->isar.mvfr0 = 0x11110222;
414 cpu->isar.mvfr1 = 0x00011111;
415 cpu->ctr = 0x82048004;
416 cpu->reset_sctlr = 0x00c50078;
417 cpu->isar.id_pfr0 = 0x1031;
418 cpu->isar.id_pfr1 = 0x11;
419 cpu->isar.id_dfr0 = 0x400;
420 cpu->id_afr0 = 0;
421 cpu->isar.id_mmfr0 = 0x31100003;
422 cpu->isar.id_mmfr1 = 0x20000000;
423 cpu->isar.id_mmfr2 = 0x01202000;
424 cpu->isar.id_mmfr3 = 0x11;
425 cpu->isar.id_isar0 = 0x00101111;
426 cpu->isar.id_isar1 = 0x12112111;
427 cpu->isar.id_isar2 = 0x21232031;
428 cpu->isar.id_isar3 = 0x11112131;
429 cpu->isar.id_isar4 = 0x00111142;
430 cpu->isar.dbgdidr = 0x15141000;
431 cpu->clidr = (1 << 27) | (2 << 24) | 3;
432 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
433 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
434 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
435 cpu->reset_auxcr = 2;
24526bb9 436 cpu->isar.reset_pmcr_el0 = 0x41002000;
80485d88
PMD		 437 define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
438}
439
440static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
441 /*
442 * power_control should be set to maximum latency. Again,
443 * default to 0 and set by private hook
444 */
445 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
446 .access = PL1_RW, .resetvalue = 0,
447 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
448 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
449 .access = PL1_RW, .resetvalue = 0,
450 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
451 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
452 .access = PL1_RW, .resetvalue = 0,
453 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
454 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
455 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
456 /* TLB lockdown control */
457 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
458 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
459 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
460 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
461 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
462 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
463 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
464 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
465 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
466 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
80485d88
PMD		 467};
468
469static void cortex_a9_initfn(Object *obj)
470{
471 ARMCPU *cpu = ARM_CPU(obj);
472
473 cpu->dtb_compatible = "arm,cortex-a9";
474 set_feature(&cpu->env, ARM_FEATURE_V7);
475 set_feature(&cpu->env, ARM_FEATURE_NEON);
476 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
477 set_feature(&cpu->env, ARM_FEATURE_EL3);
478 /*
479 * Note that A9 supports the MP extensions even for
480 * A9UP and single-core A9MP (which are both different
481 * and valid configurations; we don't model A9UP).
482 */
483 set_feature(&cpu->env, ARM_FEATURE_V7MP);
484 set_feature(&cpu->env, ARM_FEATURE_CBAR);
485 cpu->midr = 0x410fc090;
486 cpu->reset_fpsid = 0x41033090;
487 cpu->isar.mvfr0 = 0x11110222;
488 cpu->isar.mvfr1 = 0x01111111;
489 cpu->ctr = 0x80038003;
490 cpu->reset_sctlr = 0x00c50078;
491 cpu->isar.id_pfr0 = 0x1031;
492 cpu->isar.id_pfr1 = 0x11;
493 cpu->isar.id_dfr0 = 0x000;
494 cpu->id_afr0 = 0;
495 cpu->isar.id_mmfr0 = 0x00100103;
496 cpu->isar.id_mmfr1 = 0x20000000;
497 cpu->isar.id_mmfr2 = 0x01230000;
498 cpu->isar.id_mmfr3 = 0x00002111;
499 cpu->isar.id_isar0 = 0x00101111;
500 cpu->isar.id_isar1 = 0x13112111;
501 cpu->isar.id_isar2 = 0x21232041;
502 cpu->isar.id_isar3 = 0x11112131;
503 cpu->isar.id_isar4 = 0x00111142;
504 cpu->isar.dbgdidr = 0x35141000;
505 cpu->clidr = (1 << 27) | (1 << 24) | 3;
506 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
507 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
24526bb9 508 cpu->isar.reset_pmcr_el0 = 0x41093000;
80485d88
PMD		 509 define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
510}
511
512#ifndef CONFIG_USER_ONLY
513static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
514{
515 MachineState *ms = MACHINE(qdev_get_machine());
516
517 /*
518 * Linux wants the number of processors from here.
519 * Might as well set the interrupt-controller bit too.
520 */
521 return ((ms->smp.cpus - 1) << 24) | (1 << 23);
522}
523#endif
524
525static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
526#ifndef CONFIG_USER_ONLY
527 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
528 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
529 .writefn = arm_cp_write_ignore, },
530#endif
531 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
532 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
80485d88
PMD		 533};
534
535static void cortex_a7_initfn(Object *obj)
536{
537 ARMCPU *cpu = ARM_CPU(obj);
538
539 cpu->dtb_compatible = "arm,cortex-a7";
540 set_feature(&cpu->env, ARM_FEATURE_V7VE);
541 set_feature(&cpu->env, ARM_FEATURE_NEON);
542 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
543 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
544 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
545 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
546 set_feature(&cpu->env, ARM_FEATURE_EL2);
547 set_feature(&cpu->env, ARM_FEATURE_EL3);
548 set_feature(&cpu->env, ARM_FEATURE_PMU);
549 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
550 cpu->midr = 0x410fc075;
551 cpu->reset_fpsid = 0x41023075;
552 cpu->isar.mvfr0 = 0x10110222;
553 cpu->isar.mvfr1 = 0x11111111;
554 cpu->ctr = 0x84448003;
555 cpu->reset_sctlr = 0x00c50078;
556 cpu->isar.id_pfr0 = 0x00001131;
557 cpu->isar.id_pfr1 = 0x00011011;
558 cpu->isar.id_dfr0 = 0x02010555;
559 cpu->id_afr0 = 0x00000000;
560 cpu->isar.id_mmfr0 = 0x10101105;
561 cpu->isar.id_mmfr1 = 0x40000000;
562 cpu->isar.id_mmfr2 = 0x01240000;
563 cpu->isar.id_mmfr3 = 0x02102211;
564 /*
565 * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
566 * table 4-41 gives 0x02101110, which includes the arm div insns.
567 */
568 cpu->isar.id_isar0 = 0x02101110;
569 cpu->isar.id_isar1 = 0x13112111;
570 cpu->isar.id_isar2 = 0x21232041;
571 cpu->isar.id_isar3 = 0x11112131;
572 cpu->isar.id_isar4 = 0x10011142;
573 cpu->isar.dbgdidr = 0x3515f005;
09754ca8
PM		 574 cpu->isar.dbgdevid = 0x01110f13;
575 cpu->isar.dbgdevid1 = 0x1;
80485d88
PMD		 576 cpu->clidr = 0x0a200023;
577 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
578 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
579 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
24526bb9 580 cpu->isar.reset_pmcr_el0 = 0x41072000;
80485d88
PMD		 581 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
582}
583
584static void cortex_a15_initfn(Object *obj)
585{
586 ARMCPU *cpu = ARM_CPU(obj);
587
588 cpu->dtb_compatible = "arm,cortex-a15";
589 set_feature(&cpu->env, ARM_FEATURE_V7VE);
590 set_feature(&cpu->env, ARM_FEATURE_NEON);
591 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
592 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
593 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
594 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
595 set_feature(&cpu->env, ARM_FEATURE_EL2);
596 set_feature(&cpu->env, ARM_FEATURE_EL3);
597 set_feature(&cpu->env, ARM_FEATURE_PMU);
598 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
947692e7
AB		 599 /* r4p0 cpu, not requiring expensive tlb flush errata */
600 cpu->midr = 0x414fc0f0;
601 cpu->revidr = 0x0;
80485d88
PMD		 602 cpu->reset_fpsid = 0x410430f0;
603 cpu->isar.mvfr0 = 0x10110222;
604 cpu->isar.mvfr1 = 0x11111111;
605 cpu->ctr = 0x8444c004;
606 cpu->reset_sctlr = 0x00c50078;
607 cpu->isar.id_pfr0 = 0x00001131;
608 cpu->isar.id_pfr1 = 0x00011011;
609 cpu->isar.id_dfr0 = 0x02010555;
610 cpu->id_afr0 = 0x00000000;
611 cpu->isar.id_mmfr0 = 0x10201105;
612 cpu->isar.id_mmfr1 = 0x20000000;
613 cpu->isar.id_mmfr2 = 0x01240000;
614 cpu->isar.id_mmfr3 = 0x02102211;
615 cpu->isar.id_isar0 = 0x02101110;
616 cpu->isar.id_isar1 = 0x13112111;
617 cpu->isar.id_isar2 = 0x21232041;
618 cpu->isar.id_isar3 = 0x11112131;
619 cpu->isar.id_isar4 = 0x10011142;
620 cpu->isar.dbgdidr = 0x3515f021;
09754ca8
PM		 621 cpu->isar.dbgdevid = 0x01110f13;
622 cpu->isar.dbgdevid1 = 0x0;
80485d88
PMD		 623 cpu->clidr = 0x0a200023;
624 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
625 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
626 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
24526bb9 627 cpu->isar.reset_pmcr_el0 = 0x410F3000;
80485d88
PMD		 628 define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
629}
630
2465b07c
PMD		 631static void cortex_m0_initfn(Object *obj)
632{
633 ARMCPU *cpu = ARM_CPU(obj);
634 set_feature(&cpu->env, ARM_FEATURE_V6);
635 set_feature(&cpu->env, ARM_FEATURE_M);
636
637 cpu->midr = 0x410cc200;
51cb228a
PM		 638
639 /*
640 * These ID register values are not guest visible, because
641 * we do not implement the Main Extension. They must be set
642 * to values corresponding to the Cortex-M0's implemented
643 * features, because QEMU generally controls its emulation
644 * by looking at ID register fields. We use the same values as
645 * for the M3.
646 */
647 cpu->isar.id_pfr0 = 0x00000030;
648 cpu->isar.id_pfr1 = 0x00000200;
649 cpu->isar.id_dfr0 = 0x00100000;
650 cpu->id_afr0 = 0x00000000;
651 cpu->isar.id_mmfr0 = 0x00000030;
652 cpu->isar.id_mmfr1 = 0x00000000;
653 cpu->isar.id_mmfr2 = 0x00000000;
654 cpu->isar.id_mmfr3 = 0x00000000;
655 cpu->isar.id_isar0 = 0x01141110;
656 cpu->isar.id_isar1 = 0x02111000;
657 cpu->isar.id_isar2 = 0x21112231;
658 cpu->isar.id_isar3 = 0x01111110;
659 cpu->isar.id_isar4 = 0x01310102;
660 cpu->isar.id_isar5 = 0x00000000;
661 cpu->isar.id_isar6 = 0x00000000;
2465b07c
PMD		 662}
663
664static void cortex_m3_initfn(Object *obj)
665{
666 ARMCPU *cpu = ARM_CPU(obj);
667 set_feature(&cpu->env, ARM_FEATURE_V7);
668 set_feature(&cpu->env, ARM_FEATURE_M);
669 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
670 cpu->midr = 0x410fc231;
671 cpu->pmsav7_dregion = 8;
8a130a7b
PM		 672 cpu->isar.id_pfr0 = 0x00000030;
673 cpu->isar.id_pfr1 = 0x00000200;
2465b07c
PMD		 674 cpu->isar.id_dfr0 = 0x00100000;
675 cpu->id_afr0 = 0x00000000;
676 cpu->isar.id_mmfr0 = 0x00000030;
677 cpu->isar.id_mmfr1 = 0x00000000;
678 cpu->isar.id_mmfr2 = 0x00000000;
679 cpu->isar.id_mmfr3 = 0x00000000;
680 cpu->isar.id_isar0 = 0x01141110;
681 cpu->isar.id_isar1 = 0x02111000;
682 cpu->isar.id_isar2 = 0x21112231;
683 cpu->isar.id_isar3 = 0x01111110;
684 cpu->isar.id_isar4 = 0x01310102;
685 cpu->isar.id_isar5 = 0x00000000;
686 cpu->isar.id_isar6 = 0x00000000;
687}
688
689static void cortex_m4_initfn(Object *obj)
690{
691 ARMCPU *cpu = ARM_CPU(obj);
692
693 set_feature(&cpu->env, ARM_FEATURE_V7);
694 set_feature(&cpu->env, ARM_FEATURE_M);
695 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
696 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
697 cpu->midr = 0x410fc240; /* r0p0 */
698 cpu->pmsav7_dregion = 8;
699 cpu->isar.mvfr0 = 0x10110021;
700 cpu->isar.mvfr1 = 0x11000011;
701 cpu->isar.mvfr2 = 0x00000000;
8a130a7b
PM		 702 cpu->isar.id_pfr0 = 0x00000030;
703 cpu->isar.id_pfr1 = 0x00000200;
2465b07c
PMD		 704 cpu->isar.id_dfr0 = 0x00100000;
705 cpu->id_afr0 = 0x00000000;
706 cpu->isar.id_mmfr0 = 0x00000030;
707 cpu->isar.id_mmfr1 = 0x00000000;
708 cpu->isar.id_mmfr2 = 0x00000000;
709 cpu->isar.id_mmfr3 = 0x00000000;
710 cpu->isar.id_isar0 = 0x01141110;
711 cpu->isar.id_isar1 = 0x02111000;
712 cpu->isar.id_isar2 = 0x21112231;
713 cpu->isar.id_isar3 = 0x01111110;
714 cpu->isar.id_isar4 = 0x01310102;
715 cpu->isar.id_isar5 = 0x00000000;
716 cpu->isar.id_isar6 = 0x00000000;
717}
718
719static void cortex_m7_initfn(Object *obj)
720{
721 ARMCPU *cpu = ARM_CPU(obj);
722
723 set_feature(&cpu->env, ARM_FEATURE_V7);
724 set_feature(&cpu->env, ARM_FEATURE_M);
725 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
726 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
727 cpu->midr = 0x411fc272; /* r1p2 */
728 cpu->pmsav7_dregion = 8;
729 cpu->isar.mvfr0 = 0x10110221;
730 cpu->isar.mvfr1 = 0x12000011;
731 cpu->isar.mvfr2 = 0x00000040;
8a130a7b
PM		 732 cpu->isar.id_pfr0 = 0x00000030;
733 cpu->isar.id_pfr1 = 0x00000200;
2465b07c
PMD		 734 cpu->isar.id_dfr0 = 0x00100000;
735 cpu->id_afr0 = 0x00000000;
736 cpu->isar.id_mmfr0 = 0x00100030;
737 cpu->isar.id_mmfr1 = 0x00000000;
738 cpu->isar.id_mmfr2 = 0x01000000;
739 cpu->isar.id_mmfr3 = 0x00000000;
740 cpu->isar.id_isar0 = 0x01101110;
741 cpu->isar.id_isar1 = 0x02112000;
742 cpu->isar.id_isar2 = 0x20232231;
743 cpu->isar.id_isar3 = 0x01111131;
744 cpu->isar.id_isar4 = 0x01310132;
745 cpu->isar.id_isar5 = 0x00000000;
746 cpu->isar.id_isar6 = 0x00000000;
747}
748
749static void cortex_m33_initfn(Object *obj)
750{
751 ARMCPU *cpu = ARM_CPU(obj);
752
753 set_feature(&cpu->env, ARM_FEATURE_V8);
754 set_feature(&cpu->env, ARM_FEATURE_M);
755 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
756 set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
757 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
758 cpu->midr = 0x410fd213; /* r0p3 */
759 cpu->pmsav7_dregion = 16;
760 cpu->sau_sregion = 8;
761 cpu->isar.mvfr0 = 0x10110021;
762 cpu->isar.mvfr1 = 0x11000011;
763 cpu->isar.mvfr2 = 0x00000040;
8a130a7b
PM		 764 cpu->isar.id_pfr0 = 0x00000030;
765 cpu->isar.id_pfr1 = 0x00000210;
2465b07c
PMD		 766 cpu->isar.id_dfr0 = 0x00200000;
767 cpu->id_afr0 = 0x00000000;
768 cpu->isar.id_mmfr0 = 0x00101F40;
769 cpu->isar.id_mmfr1 = 0x00000000;
770 cpu->isar.id_mmfr2 = 0x01000000;
771 cpu->isar.id_mmfr3 = 0x00000000;
772 cpu->isar.id_isar0 = 0x01101110;
773 cpu->isar.id_isar1 = 0x02212000;
774 cpu->isar.id_isar2 = 0x20232232;
775 cpu->isar.id_isar3 = 0x01111131;
776 cpu->isar.id_isar4 = 0x01310132;
777 cpu->isar.id_isar5 = 0x00000000;
778 cpu->isar.id_isar6 = 0x00000000;
779 cpu->clidr = 0x00000000;
780 cpu->ctr = 0x8000c000;
781}
782
590e05d6
PM		 783static void cortex_m55_initfn(Object *obj)
784{
785 ARMCPU *cpu = ARM_CPU(obj);
786
787 set_feature(&cpu->env, ARM_FEATURE_V8);
788 set_feature(&cpu->env, ARM_FEATURE_V8_1M);
789 set_feature(&cpu->env, ARM_FEATURE_M);
790 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
791 set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
792 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
793 cpu->midr = 0x410fd221; /* r0p1 */
794 cpu->revidr = 0;
795 cpu->pmsav7_dregion = 16;
796 cpu->sau_sregion = 8;
d4cc1c21 797 /* These are the MVFR* values for the FPU + full MVE configuration */
590e05d6 798 cpu->isar.mvfr0 = 0x10110221;
d4cc1c21 799 cpu->isar.mvfr1 = 0x12100211;
590e05d6
PM		 800 cpu->isar.mvfr2 = 0x00000040;
801 cpu->isar.id_pfr0 = 0x20000030;
802 cpu->isar.id_pfr1 = 0x00000230;
803 cpu->isar.id_dfr0 = 0x10200000;
804 cpu->id_afr0 = 0x00000000;
805 cpu->isar.id_mmfr0 = 0x00111040;
806 cpu->isar.id_mmfr1 = 0x00000000;
807 cpu->isar.id_mmfr2 = 0x01000000;
808 cpu->isar.id_mmfr3 = 0x00000011;
809 cpu->isar.id_isar0 = 0x01103110;
810 cpu->isar.id_isar1 = 0x02212000;
811 cpu->isar.id_isar2 = 0x20232232;
812 cpu->isar.id_isar3 = 0x01111131;
813 cpu->isar.id_isar4 = 0x01310132;
814 cpu->isar.id_isar5 = 0x00000000;
815 cpu->isar.id_isar6 = 0x00000000;
816 cpu->clidr = 0x00000000; /* caches not implemented */
817 cpu->ctr = 0x8303c003;
818}
819
2465b07c
PMD		 820static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
821 /* Dummy the TCM region regs for the moment */
822 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
823 .access = PL1_RW, .type = ARM_CP_CONST },
824 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
825 .access = PL1_RW, .type = ARM_CP_CONST },
826 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
827 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
2465b07c
PMD		 828};
829
830static void cortex_r5_initfn(Object *obj)
831{
832 ARMCPU *cpu = ARM_CPU(obj);
833
834 set_feature(&cpu->env, ARM_FEATURE_V7);
835 set_feature(&cpu->env, ARM_FEATURE_V7MP);
836 set_feature(&cpu->env, ARM_FEATURE_PMSA);
837 set_feature(&cpu->env, ARM_FEATURE_PMU);
838 cpu->midr = 0x411fc153; /* r1p3 */
8a130a7b
PM		 839 cpu->isar.id_pfr0 = 0x0131;
840 cpu->isar.id_pfr1 = 0x001;
2465b07c
PMD		 841 cpu->isar.id_dfr0 = 0x010400;
842 cpu->id_afr0 = 0x0;
843 cpu->isar.id_mmfr0 = 0x0210030;
844 cpu->isar.id_mmfr1 = 0x00000000;
845 cpu->isar.id_mmfr2 = 0x01200000;
846 cpu->isar.id_mmfr3 = 0x0211;
847 cpu->isar.id_isar0 = 0x02101111;
848 cpu->isar.id_isar1 = 0x13112111;
849 cpu->isar.id_isar2 = 0x21232141;
850 cpu->isar.id_isar3 = 0x01112131;
851 cpu->isar.id_isar4 = 0x0010142;
852 cpu->isar.id_isar5 = 0x0;
853 cpu->isar.id_isar6 = 0x0;
854 cpu->mp_is_up = true;
855 cpu->pmsav7_dregion = 16;
24526bb9 856 cpu->isar.reset_pmcr_el0 = 0x41151800;
2465b07c
PMD		 857 define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
858}
859
5f536d01
TR		 860static void cortex_r52_initfn(Object *obj)
861{
862 ARMCPU *cpu = ARM_CPU(obj);
863
864 set_feature(&cpu->env, ARM_FEATURE_V8);
865 set_feature(&cpu->env, ARM_FEATURE_EL2);
866 set_feature(&cpu->env, ARM_FEATURE_PMSA);
867 set_feature(&cpu->env, ARM_FEATURE_NEON);
868 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
869 cpu->midr = 0x411fd133; /* r1p3 */
870 cpu->revidr = 0x00000000;
871 cpu->reset_fpsid = 0x41034023;
872 cpu->isar.mvfr0 = 0x10110222;
873 cpu->isar.mvfr1 = 0x12111111;
874 cpu->isar.mvfr2 = 0x00000043;
875 cpu->ctr = 0x8144c004;
876 cpu->reset_sctlr = 0x30c50838;
877 cpu->isar.id_pfr0 = 0x00000131;
878 cpu->isar.id_pfr1 = 0x10111001;
879 cpu->isar.id_dfr0 = 0x03010006;
880 cpu->id_afr0 = 0x00000000;
881 cpu->isar.id_mmfr0 = 0x00211040;
882 cpu->isar.id_mmfr1 = 0x40000000;
883 cpu->isar.id_mmfr2 = 0x01200000;
884 cpu->isar.id_mmfr3 = 0xf0102211;
885 cpu->isar.id_mmfr4 = 0x00000010;
886 cpu->isar.id_isar0 = 0x02101110;
887 cpu->isar.id_isar1 = 0x13112111;
888 cpu->isar.id_isar2 = 0x21232142;
889 cpu->isar.id_isar3 = 0x01112131;
890 cpu->isar.id_isar4 = 0x00010142;
891 cpu->isar.id_isar5 = 0x00010001;
892 cpu->isar.dbgdidr = 0x77168000;
893 cpu->clidr = (1 << 27) | (1 << 24) | 0x3;
894 cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
895 cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
896
897 cpu->pmsav7_dregion = 16;
898 cpu->pmsav8r_hdregion = 16;
899}
900
2465b07c
PMD		 901static void cortex_r5f_initfn(Object *obj)
902{
903 ARMCPU *cpu = ARM_CPU(obj);
904
905 cortex_r5_initfn(obj);
906 cpu->isar.mvfr0 = 0x10110221;
907 cpu->isar.mvfr1 = 0x00000011;
908}
909
910static void ti925t_initfn(Object *obj)
911{
912 ARMCPU *cpu = ARM_CPU(obj);
913 set_feature(&cpu->env, ARM_FEATURE_V4T);
914 set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
915 cpu->midr = ARM_CPUID_TI925T;
916 cpu->ctr = 0x5109149;
917 cpu->reset_sctlr = 0x00000070;
918}
919
920static void sa1100_initfn(Object *obj)
921{
922 ARMCPU *cpu = ARM_CPU(obj);
923
924 cpu->dtb_compatible = "intel,sa1100";
925 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
926 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
927 cpu->midr = 0x4401A11B;
928 cpu->reset_sctlr = 0x00000070;
929}
930
931static void sa1110_initfn(Object *obj)
932{
933 ARMCPU *cpu = ARM_CPU(obj);
934 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
935 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
936 cpu->midr = 0x6901B119;
937 cpu->reset_sctlr = 0x00000070;
938}
939
940static void pxa250_initfn(Object *obj)
941{
942 ARMCPU *cpu = ARM_CPU(obj);
943
944 cpu->dtb_compatible = "marvell,xscale";
945 set_feature(&cpu->env, ARM_FEATURE_V5);
946 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
947 cpu->midr = 0x69052100;
948 cpu->ctr = 0xd172172;
949 cpu->reset_sctlr = 0x00000078;
950}
951
952static void pxa255_initfn(Object *obj)
953{
954 ARMCPU *cpu = ARM_CPU(obj);
955
956 cpu->dtb_compatible = "marvell,xscale";
957 set_feature(&cpu->env, ARM_FEATURE_V5);
958 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
959 cpu->midr = 0x69052d00;
960 cpu->ctr = 0xd172172;
961 cpu->reset_sctlr = 0x00000078;
962}
963
964static void pxa260_initfn(Object *obj)
965{
966 ARMCPU *cpu = ARM_CPU(obj);
967
968 cpu->dtb_compatible = "marvell,xscale";
969 set_feature(&cpu->env, ARM_FEATURE_V5);
970 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
971 cpu->midr = 0x69052903;
972 cpu->ctr = 0xd172172;
973 cpu->reset_sctlr = 0x00000078;
974}
975
976static void pxa261_initfn(Object *obj)
977{
978 ARMCPU *cpu = ARM_CPU(obj);
979
980 cpu->dtb_compatible = "marvell,xscale";
981 set_feature(&cpu->env, ARM_FEATURE_V5);
982 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
983 cpu->midr = 0x69052d05;
984 cpu->ctr = 0xd172172;
985 cpu->reset_sctlr = 0x00000078;
986}
987
988static void pxa262_initfn(Object *obj)
989{
990 ARMCPU *cpu = ARM_CPU(obj);
991
992 cpu->dtb_compatible = "marvell,xscale";
993 set_feature(&cpu->env, ARM_FEATURE_V5);
994 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
995 cpu->midr = 0x69052d06;
996 cpu->ctr = 0xd172172;
997 cpu->reset_sctlr = 0x00000078;
998}
999
1000static void pxa270a0_initfn(Object *obj)
1001{
1002 ARMCPU *cpu = ARM_CPU(obj);
1003
1004 cpu->dtb_compatible = "marvell,xscale";
1005 set_feature(&cpu->env, ARM_FEATURE_V5);
1006 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1007 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1008 cpu->midr = 0x69054110;
1009 cpu->ctr = 0xd172172;
1010 cpu->reset_sctlr = 0x00000078;
1011}
1012
1013static void pxa270a1_initfn(Object *obj)
1014{
1015 ARMCPU *cpu = ARM_CPU(obj);
1016
1017 cpu->dtb_compatible = "marvell,xscale";
1018 set_feature(&cpu->env, ARM_FEATURE_V5);
1019 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1020 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1021 cpu->midr = 0x69054111;
1022 cpu->ctr = 0xd172172;
1023 cpu->reset_sctlr = 0x00000078;
1024}
1025
1026static void pxa270b0_initfn(Object *obj)
1027{
1028 ARMCPU *cpu = ARM_CPU(obj);
1029
1030 cpu->dtb_compatible = "marvell,xscale";
1031 set_feature(&cpu->env, ARM_FEATURE_V5);
1032 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1033 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1034 cpu->midr = 0x69054112;
1035 cpu->ctr = 0xd172172;
1036 cpu->reset_sctlr = 0x00000078;
1037}
1038
1039static void pxa270b1_initfn(Object *obj)
1040{
1041 ARMCPU *cpu = ARM_CPU(obj);
1042
1043 cpu->dtb_compatible = "marvell,xscale";
1044 set_feature(&cpu->env, ARM_FEATURE_V5);
1045 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1046 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1047 cpu->midr = 0x69054113;
1048 cpu->ctr = 0xd172172;
1049 cpu->reset_sctlr = 0x00000078;
1050}
1051
1052static void pxa270c0_initfn(Object *obj)
1053{
1054 ARMCPU *cpu = ARM_CPU(obj);
1055
1056 cpu->dtb_compatible = "marvell,xscale";
1057 set_feature(&cpu->env, ARM_FEATURE_V5);
1058 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1059 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1060 cpu->midr = 0x69054114;
1061 cpu->ctr = 0xd172172;
1062 cpu->reset_sctlr = 0x00000078;
1063}
1064
1065static void pxa270c5_initfn(Object *obj)
1066{
1067 ARMCPU *cpu = ARM_CPU(obj);
1068
1069 cpu->dtb_compatible = "marvell,xscale";
1070 set_feature(&cpu->env, ARM_FEATURE_V5);
1071 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1072 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1073 cpu->midr = 0x69054117;
1074 cpu->ctr = 0xd172172;
1075 cpu->reset_sctlr = 0x00000078;
1076}
1077
78271684 1078#ifdef CONFIG_TCG
11906557 1079static const struct TCGCPUOps arm_v7m_tcg_ops = {
78271684
CF		 1080 .initialize = arm_translate_init,
1081 .synchronize_from_tb = arm_cpu_synchronize_from_tb,
78271684 1082 .debug_excp_handler = arm_debug_excp_handler,
475e56b6 1083 .restore_state_to_opc = arm_restore_state_to_opc,
78271684 1084
9b12b6b4
RH		 1085#ifdef CONFIG_USER_ONLY
1086 .record_sigsegv = arm_cpu_record_sigsegv,
39a099ca 1087 .record_sigbus = arm_cpu_record_sigbus,
9b12b6b4
RH		 1088#else
1089 .tlb_fill = arm_cpu_tlb_fill,
083afd18 1090 .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt,
78271684
CF		 1091 .do_interrupt = arm_v7m_cpu_do_interrupt,
1092 .do_transaction_failed = arm_cpu_do_transaction_failed,
1093 .do_unaligned_access = arm_cpu_do_unaligned_access,
1094 .adjust_watchpoint_address = arm_adjust_watchpoint_address,
1095 .debug_check_watchpoint = arm_debug_check_watchpoint,
b00d86bc 1096 .debug_check_breakpoint = arm_debug_check_breakpoint,
78271684
CF		 1097#endif /* !CONFIG_USER_ONLY */
1098};
1099#endif /* CONFIG_TCG */
1100
2465b07c
PMD		 1101static void arm_v7m_class_init(ObjectClass *oc, void *data)
1102{
1103 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1104 CPUClass *cc = CPU_CLASS(oc);
1105
1106 acc->info = data;
48c1a3e3 1107#ifdef CONFIG_TCG
78271684 1108 cc->tcg_ops = &arm_v7m_tcg_ops;
48c1a3e3
EH		 1109#endif /* CONFIG_TCG */
1110
c888f7e0 1111 cc->gdb_core_xml_file = "arm-m-profile.xml";
2465b07c
PMD		 1112}
1113
80485d88
PMD		 1114#ifndef TARGET_AARCH64
1115/*
1116 * -cpu max: a CPU with as many features enabled as our emulation supports.
1117 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
1118 * this only needs to handle 32 bits, and need not care about KVM.
1119 */
1120static void arm_max_initfn(Object *obj)
1121{
1122 ARMCPU *cpu = ARM_CPU(obj);
1123
7e834daf
RH		 1124 /* aarch64_a57_initfn, advertising none of the aarch64 features */
1125 cpu->dtb_compatible = "arm,cortex-a57";
1126 set_feature(&cpu->env, ARM_FEATURE_V8);
1127 set_feature(&cpu->env, ARM_FEATURE_NEON);
1128 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
1129 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
1130 set_feature(&cpu->env, ARM_FEATURE_EL2);
1131 set_feature(&cpu->env, ARM_FEATURE_EL3);
1132 set_feature(&cpu->env, ARM_FEATURE_PMU);
1133 cpu->midr = 0x411fd070;
1134 cpu->revidr = 0x00000000;
1135 cpu->reset_fpsid = 0x41034070;
1136 cpu->isar.mvfr0 = 0x10110222;
1137 cpu->isar.mvfr1 = 0x12111111;
1138 cpu->isar.mvfr2 = 0x00000043;
1139 cpu->ctr = 0x8444c004;
1140 cpu->reset_sctlr = 0x00c50838;
1141 cpu->isar.id_pfr0 = 0x00000131;
1142 cpu->isar.id_pfr1 = 0x00011011;
1143 cpu->isar.id_dfr0 = 0x03010066;
1144 cpu->id_afr0 = 0x00000000;
1145 cpu->isar.id_mmfr0 = 0x10101105;
1146 cpu->isar.id_mmfr1 = 0x40000000;
1147 cpu->isar.id_mmfr2 = 0x01260000;
1148 cpu->isar.id_mmfr3 = 0x02102211;
1149 cpu->isar.id_isar0 = 0x02101110;
1150 cpu->isar.id_isar1 = 0x13112111;
1151 cpu->isar.id_isar2 = 0x21232042;
1152 cpu->isar.id_isar3 = 0x01112131;
1153 cpu->isar.id_isar4 = 0x00011142;
1154 cpu->isar.id_isar5 = 0x00011121;
1155 cpu->isar.id_isar6 = 0;
1156 cpu->isar.dbgdidr = 0x3516d000;
09754ca8
PM		 1157 cpu->isar.dbgdevid = 0x00110f13;
1158 cpu->isar.dbgdevid1 = 0x2;
24526bb9 1159 cpu->isar.reset_pmcr_el0 = 0x41013000;
7e834daf
RH		 1160 cpu->clidr = 0x0a200023;
1161 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
1162 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
1163 cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
1164 define_cortex_a72_a57_a53_cp_reginfo(cpu);
1165
b6f8b358 1166 aa32_max_features(cpu);
e14cc941 1167
80485d88
PMD		 1168#ifdef CONFIG_USER_ONLY
1169 /*
7e834daf
RH		 1170 * Break with true ARMv8 and add back old-style VFP short-vector support.
1171 * Only do this for user-mode, where -cpu max is the default, so that
1172 * older v6 and v7 programs are more likely to work without adjustment.
80485d88 1173 */
7e834daf
RH		 1174 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
1175#endif
80485d88
PMD		 1176}
1177#endif /* !TARGET_AARCH64 */
1178
2465b07c
PMD		 1179static const ARMCPUInfo arm_tcg_cpus[] = {
1180 { .name = "arm926", .initfn = arm926_initfn },
1181 { .name = "arm946", .initfn = arm946_initfn },
1182 { .name = "arm1026", .initfn = arm1026_initfn },
1183 /*
1184 * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1185 * older core than plain "arm1136". In particular this does not
1186 * have the v6K features.
1187 */
1188 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
1189 { .name = "arm1136", .initfn = arm1136_initfn },
1190 { .name = "arm1176", .initfn = arm1176_initfn },
1191 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
80485d88
PMD		 1192 { .name = "cortex-a7", .initfn = cortex_a7_initfn },
1193 { .name = "cortex-a8", .initfn = cortex_a8_initfn },
1194 { .name = "cortex-a9", .initfn = cortex_a9_initfn },
1195 { .name = "cortex-a15", .initfn = cortex_a15_initfn },
2465b07c
PMD		 1196 { .name = "cortex-m0", .initfn = cortex_m0_initfn,
1197 .class_init = arm_v7m_class_init },
1198 { .name = "cortex-m3", .initfn = cortex_m3_initfn,
1199 .class_init = arm_v7m_class_init },
1200 { .name = "cortex-m4", .initfn = cortex_m4_initfn,
1201 .class_init = arm_v7m_class_init },
1202 { .name = "cortex-m7", .initfn = cortex_m7_initfn,
1203 .class_init = arm_v7m_class_init },
1204 { .name = "cortex-m33", .initfn = cortex_m33_initfn,
1205 .class_init = arm_v7m_class_init },
590e05d6
PM		 1206 { .name = "cortex-m55", .initfn = cortex_m55_initfn,
1207 .class_init = arm_v7m_class_init },
2465b07c
PMD		 1208 { .name = "cortex-r5", .initfn = cortex_r5_initfn },
1209 { .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
5f536d01 1210 { .name = "cortex-r52", .initfn = cortex_r52_initfn },
2465b07c
PMD		 1211 { .name = "ti925t", .initfn = ti925t_initfn },
1212 { .name = "sa1100", .initfn = sa1100_initfn },
1213 { .name = "sa1110", .initfn = sa1110_initfn },
1214 { .name = "pxa250", .initfn = pxa250_initfn },
1215 { .name = "pxa255", .initfn = pxa255_initfn },
1216 { .name = "pxa260", .initfn = pxa260_initfn },
1217 { .name = "pxa261", .initfn = pxa261_initfn },
1218 { .name = "pxa262", .initfn = pxa262_initfn },
1219 /* "pxa270" is an alias for "pxa270-a0" */
1220 { .name = "pxa270", .initfn = pxa270a0_initfn },
1221 { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
1222 { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
1223 { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
1224 { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
1225 { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
1226 { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
80485d88
PMD		 1227#ifndef TARGET_AARCH64
1228 { .name = "max", .initfn = arm_max_initfn },
1229#endif
1230#ifdef CONFIG_USER_ONLY
1231 { .name = "any", .initfn = arm_max_initfn },
1232#endif
2465b07c
PMD		 1233};
1234
6e937ba7
PMD		 1235static const TypeInfo idau_interface_type_info = {
1236 .name = TYPE_IDAU_INTERFACE,
1237 .parent = TYPE_INTERFACE,
1238 .class_size = sizeof(IDAUInterfaceClass),
1239};
1240
2465b07c
PMD		 1241static void arm_tcg_cpu_register_types(void)
1242{
1243 size_t i;
1244
6e937ba7 1245 type_register_static(&idau_interface_type_info);
2465b07c
PMD		 1246 for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) {
1247 arm_cpu_register(&arm_tcg_cpus[i]);
1248 }
1249}
1250
1251type_init(arm_tcg_cpu_register_types)
1252
1253#endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */
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