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Commit | Line | Data |
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8ae08860 RH |
1 | /* |
2 | * ARM page table walking. | |
3 | * | |
4 | * This code is licensed under the GNU GPL v2 or later. | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0-or-later | |
7 | */ | |
8 | ||
9 | #include "qemu/osdep.h" | |
10 | #include "qemu/log.h" | |
1f2e87e5 | 11 | #include "qemu/range.h" |
71943a1e | 12 | #include "qemu/main-loop.h" |
f3639a64 | 13 | #include "exec/exec-all.h" |
8ae08860 RH |
14 | #include "cpu.h" |
15 | #include "internals.h" | |
2c1f429d | 16 | #include "idau.h" |
007cd176 RH |
17 | #ifdef CONFIG_TCG |
18 | # include "tcg/oversized-guest.h" | |
19 | #endif | |
8ae08860 | 20 | |
6d2654ff RH |
21 | typedef struct S1Translate { |
22 | ARMMMUIdx in_mmu_idx; | |
48da29e4 | 23 | ARMMMUIdx in_ptw_idx; |
90c66293 | 24 | ARMSecuritySpace in_space; |
6d2654ff | 25 | bool in_secure; |
4a358556 | 26 | bool in_debug; |
6d2654ff | 27 | bool out_secure; |
71943a1e | 28 | bool out_rw; |
4e7a2c98 | 29 | bool out_be; |
90c66293 | 30 | ARMSecuritySpace out_space; |
71943a1e | 31 | hwaddr out_virt; |
6d2654ff | 32 | hwaddr out_phys; |
f3639a64 | 33 | void *out_host; |
6d2654ff RH |
34 | } S1Translate; |
35 | ||
36 | static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, | |
37 | uint64_t address, | |
38 | MMUAccessType access_type, bool s1_is_el0, | |
86a438b4 | 39 | GetPhysAddrResult *result, ARMMMUFaultInfo *fi); |
11552bb0 | 40 | |
3f5a74c5 RH |
41 | static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, |
42 | target_ulong address, | |
43 | MMUAccessType access_type, | |
44 | GetPhysAddrResult *result, | |
86a438b4 | 45 | ARMMMUFaultInfo *fi); |
3f5a74c5 | 46 | |
1c73d848 RH |
47 | /* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */ |
48 | static const uint8_t pamax_map[] = { | |
49 | [0] = 32, | |
50 | [1] = 36, | |
51 | [2] = 40, | |
52 | [3] = 42, | |
53 | [4] = 44, | |
54 | [5] = 48, | |
55 | [6] = 52, | |
56 | }; | |
57 | ||
58 | /* The cpu-specific constant value of PAMax; also used by hw/arm/virt. */ | |
59 | unsigned int arm_pamax(ARMCPU *cpu) | |
60 | { | |
22536b13 RH |
61 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { |
62 | unsigned int parange = | |
63 | FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); | |
1c73d848 | 64 | |
22536b13 RH |
65 | /* |
66 | * id_aa64mmfr0 is a read-only register so values outside of the | |
67 | * supported mappings can be considered an implementation error. | |
68 | */ | |
69 | assert(parange < ARRAY_SIZE(pamax_map)); | |
70 | return pamax_map[parange]; | |
71 | } | |
59e1b8a2 RH |
72 | |
73 | /* | |
74 | * In machvirt_init, we call arm_pamax on a cpu that is not fully | |
75 | * initialized, so we can't rely on the propagation done in realize. | |
76 | */ | |
77 | if (arm_feature(&cpu->env, ARM_FEATURE_LPAE) || | |
78 | arm_feature(&cpu->env, ARM_FEATURE_V7VE)) { | |
22536b13 RH |
79 | /* v7 with LPAE */ |
80 | return 40; | |
81 | } | |
82 | /* Anything else */ | |
83 | return 32; | |
1c73d848 RH |
84 | } |
85 | ||
1d261255 RH |
86 | /* |
87 | * Convert a possible stage1+2 MMU index into the appropriate stage 1 MMU index | |
88 | */ | |
89 | ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) | |
90 | { | |
91 | switch (mmu_idx) { | |
1d261255 RH |
92 | case ARMMMUIdx_E10_0: |
93 | return ARMMMUIdx_Stage1_E0; | |
94 | case ARMMMUIdx_E10_1: | |
95 | return ARMMMUIdx_Stage1_E1; | |
96 | case ARMMMUIdx_E10_1_PAN: | |
97 | return ARMMMUIdx_Stage1_E1_PAN; | |
98 | default: | |
99 | return mmu_idx; | |
100 | } | |
101 | } | |
102 | ||
103 | ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) | |
104 | { | |
105 | return stage_1_mmu_idx(arm_mmu_idx(env)); | |
106 | } | |
107 | ||
fcc0b041 PM |
108 | /* |
109 | * Return where we should do ptw loads from for a stage 2 walk. | |
110 | * This depends on whether the address we are looking up is a | |
111 | * Secure IPA or a NonSecure IPA, which we know from whether this is | |
112 | * Stage2 or Stage2_S. | |
113 | * If this is the Secure EL1&0 regime we need to check the NSW and SW bits. | |
114 | */ | |
115 | static ARMMMUIdx ptw_idx_for_stage_2(CPUARMState *env, ARMMMUIdx stage2idx) | |
116 | { | |
117 | bool s2walk_secure; | |
118 | ||
119 | /* | |
120 | * We're OK to check the current state of the CPU here because | |
121 | * (1) we always invalidate all TLBs when the SCR_EL3.NS bit changes | |
122 | * (2) there's no way to do a lookup that cares about Stage 2 for a | |
123 | * different security state to the current one for AArch64, and AArch32 | |
124 | * never has a secure EL2. (AArch32 ATS12NSO[UP][RW] allow EL3 to do | |
125 | * an NS stage 1+2 lookup while the NS bit is 0.) | |
126 | */ | |
127 | if (!arm_is_secure_below_el3(env) || !arm_el_is_aa64(env, 3)) { | |
128 | return ARMMMUIdx_Phys_NS; | |
129 | } | |
130 | if (stage2idx == ARMMMUIdx_Stage2_S) { | |
131 | s2walk_secure = !(env->cp15.vstcr_el2 & VSTCR_SW); | |
132 | } else { | |
133 | s2walk_secure = !(env->cp15.vtcr_el2 & VTCR_NSW); | |
134 | } | |
135 | return s2walk_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS; | |
136 | ||
137 | } | |
138 | ||
11552bb0 RH |
139 | static bool regime_translation_big_endian(CPUARMState *env, ARMMMUIdx mmu_idx) |
140 | { | |
141 | return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0; | |
142 | } | |
143 | ||
3b318aae RH |
144 | /* Return the TTBR associated with this translation regime */ |
145 | static uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, int ttbrn) | |
146 | { | |
147 | if (mmu_idx == ARMMMUIdx_Stage2) { | |
148 | return env->cp15.vttbr_el2; | |
149 | } | |
150 | if (mmu_idx == ARMMMUIdx_Stage2_S) { | |
151 | return env->cp15.vsttbr_el2; | |
152 | } | |
153 | if (ttbrn == 0) { | |
154 | return env->cp15.ttbr0_el[regime_el(env, mmu_idx)]; | |
155 | } else { | |
156 | return env->cp15.ttbr1_el[regime_el(env, mmu_idx)]; | |
157 | } | |
158 | } | |
159 | ||
8db1a3a0 | 160 | /* Return true if the specified stage of address translation is disabled */ |
7e80c0a4 RH |
161 | static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx, |
162 | bool is_secure) | |
8db1a3a0 RH |
163 | { |
164 | uint64_t hcr_el2; | |
165 | ||
166 | if (arm_feature(env, ARM_FEATURE_M)) { | |
7e80c0a4 | 167 | switch (env->v7m.mpu_ctrl[is_secure] & |
8db1a3a0 RH |
168 | (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) { |
169 | case R_V7M_MPU_CTRL_ENABLE_MASK: | |
170 | /* Enabled, but not for HardFault and NMI */ | |
171 | return mmu_idx & ARM_MMU_IDX_M_NEGPRI; | |
172 | case R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK: | |
173 | /* Enabled for all cases */ | |
174 | return false; | |
175 | case 0: | |
176 | default: | |
177 | /* | |
178 | * HFNMIENA set and ENABLE clear is UNPREDICTABLE, but | |
179 | * we warned about that in armv7m_nvic.c when the guest set it. | |
180 | */ | |
181 | return true; | |
182 | } | |
183 | } | |
184 | ||
2189c798 | 185 | hcr_el2 = arm_hcr_el2_eff_secstate(env, is_secure); |
8db1a3a0 | 186 | |
3b2af993 RH |
187 | switch (mmu_idx) { |
188 | case ARMMMUIdx_Stage2: | |
189 | case ARMMMUIdx_Stage2_S: | |
8db1a3a0 RH |
190 | /* HCR.DC means HCR.VM behaves as 1 */ |
191 | return (hcr_el2 & (HCR_DC | HCR_VM)) == 0; | |
8db1a3a0 | 192 | |
3b2af993 RH |
193 | case ARMMMUIdx_E10_0: |
194 | case ARMMMUIdx_E10_1: | |
195 | case ARMMMUIdx_E10_1_PAN: | |
fdf12933 RH |
196 | /* TGE means that EL0/1 act as if SCTLR_EL1.M is zero */ |
197 | if (hcr_el2 & HCR_TGE) { | |
8db1a3a0 RH |
198 | return true; |
199 | } | |
3b2af993 | 200 | break; |
8db1a3a0 | 201 | |
3b2af993 RH |
202 | case ARMMMUIdx_Stage1_E0: |
203 | case ARMMMUIdx_Stage1_E1: | |
204 | case ARMMMUIdx_Stage1_E1_PAN: | |
8db1a3a0 | 205 | /* HCR.DC means SCTLR_EL1.M behaves as 0 */ |
3b2af993 RH |
206 | if (hcr_el2 & HCR_DC) { |
207 | return true; | |
208 | } | |
209 | break; | |
210 | ||
211 | case ARMMMUIdx_E20_0: | |
212 | case ARMMMUIdx_E20_2: | |
213 | case ARMMMUIdx_E20_2_PAN: | |
214 | case ARMMMUIdx_E2: | |
215 | case ARMMMUIdx_E3: | |
216 | break; | |
217 | ||
a1ce3084 | 218 | case ARMMMUIdx_Phys_S: |
bb5cc2c8 RH |
219 | case ARMMMUIdx_Phys_NS: |
220 | case ARMMMUIdx_Phys_Root: | |
221 | case ARMMMUIdx_Phys_Realm: | |
a1ce3084 RH |
222 | /* No translation for physical address spaces. */ |
223 | return true; | |
224 | ||
3b2af993 RH |
225 | default: |
226 | g_assert_not_reached(); | |
8db1a3a0 RH |
227 | } |
228 | ||
229 | return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0; | |
230 | } | |
231 | ||
f3639a64 | 232 | static bool S2_attrs_are_device(uint64_t hcr, uint8_t attrs) |
11552bb0 RH |
233 | { |
234 | /* | |
235 | * For an S1 page table walk, the stage 1 attributes are always | |
236 | * some form of "this is Normal memory". The combined S1+S2 | |
237 | * attributes are therefore only Device if stage 2 specifies Device. | |
238 | * With HCR_EL2.FWB == 0 this is when descriptor bits [5:4] are 0b00, | |
239 | * ie when cacheattrs.attrs bits [3:2] are 0b00. | |
240 | * With HCR_EL2.FWB == 1 this is when descriptor bit [4] is 0, ie | |
241 | * when cacheattrs.attrs bit [2] is 0. | |
242 | */ | |
ac76c2e5 | 243 | if (hcr & HCR_FWB) { |
f3639a64 | 244 | return (attrs & 0x4) == 0; |
11552bb0 | 245 | } else { |
f3639a64 | 246 | return (attrs & 0xc) == 0; |
11552bb0 RH |
247 | } |
248 | } | |
249 | ||
250 | /* Translate a S1 pagetable walk through S2 if needed. */ | |
6d2654ff RH |
251 | static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, |
252 | hwaddr addr, ARMMMUFaultInfo *fi) | |
11552bb0 | 253 | { |
90c66293 | 254 | ARMSecuritySpace space = ptw->in_space; |
6d2654ff | 255 | bool is_secure = ptw->in_secure; |
f3639a64 | 256 | ARMMMUIdx mmu_idx = ptw->in_mmu_idx; |
48da29e4 | 257 | ARMMMUIdx s2_mmu_idx = ptw->in_ptw_idx; |
f3639a64 | 258 | uint8_t pte_attrs; |
f3639a64 | 259 | |
71943a1e RH |
260 | ptw->out_virt = addr; |
261 | ||
f3639a64 RH |
262 | if (unlikely(ptw->in_debug)) { |
263 | /* | |
264 | * From gdbstub, do not use softmmu so that we don't modify the | |
265 | * state of the cpu at all, including softmmu tlb contents. | |
266 | */ | |
48da29e4 | 267 | if (regime_is_stage2(s2_mmu_idx)) { |
f3639a64 RH |
268 | S1Translate s2ptw = { |
269 | .in_mmu_idx = s2_mmu_idx, | |
fcc0b041 PM |
270 | .in_ptw_idx = ptw_idx_for_stage_2(env, s2_mmu_idx), |
271 | .in_secure = s2_mmu_idx == ARMMMUIdx_Stage2_S, | |
90c66293 RH |
272 | .in_space = (s2_mmu_idx == ARMMMUIdx_Stage2_S ? ARMSS_Secure |
273 | : space == ARMSS_Realm ? ARMSS_Realm | |
274 | : ARMSS_NonSecure), | |
f3639a64 RH |
275 | .in_debug = true, |
276 | }; | |
277 | GetPhysAddrResult s2 = { }; | |
48da29e4 | 278 | |
4a1103af RH |
279 | if (get_phys_addr_lpae(env, &s2ptw, addr, MMU_DATA_LOAD, |
280 | false, &s2, fi)) { | |
f3639a64 RH |
281 | goto fail; |
282 | } | |
283 | ptw->out_phys = s2.f.phys_addr; | |
284 | pte_attrs = s2.cacheattrs.attrs; | |
fcc0b041 | 285 | ptw->out_secure = s2.f.attrs.secure; |
90c66293 | 286 | ptw->out_space = s2.f.attrs.space; |
48da29e4 RH |
287 | } else { |
288 | /* Regime is physical. */ | |
289 | ptw->out_phys = addr; | |
290 | pte_attrs = 0; | |
fcc0b041 | 291 | ptw->out_secure = s2_mmu_idx == ARMMMUIdx_Phys_S; |
90c66293 RH |
292 | ptw->out_space = (s2_mmu_idx == ARMMMUIdx_Phys_S ? ARMSS_Secure |
293 | : space == ARMSS_Realm ? ARMSS_Realm | |
294 | : ARMSS_NonSecure); | |
11552bb0 | 295 | } |
f3639a64 | 296 | ptw->out_host = NULL; |
71943a1e | 297 | ptw->out_rw = false; |
f3639a64 | 298 | } else { |
0d3de77a | 299 | #ifdef CONFIG_TCG |
f3639a64 RH |
300 | CPUTLBEntryFull *full; |
301 | int flags; | |
302 | ||
303 | env->tlb_fi = fi; | |
d507e6c5 | 304 | flags = probe_access_full(env, addr, 0, MMU_DATA_LOAD, |
f3639a64 RH |
305 | arm_to_core_mmu_idx(s2_mmu_idx), |
306 | true, &ptw->out_host, &full, 0); | |
307 | env->tlb_fi = NULL; | |
308 | ||
309 | if (unlikely(flags & TLB_INVALID_MASK)) { | |
310 | goto fail; | |
311 | } | |
9d2617ac | 312 | ptw->out_phys = full->phys_addr | (addr & ~TARGET_PAGE_MASK); |
71943a1e | 313 | ptw->out_rw = full->prot & PAGE_WRITE; |
f3639a64 | 314 | pte_attrs = full->pte_attrs; |
fcc0b041 | 315 | ptw->out_secure = full->attrs.secure; |
90c66293 | 316 | ptw->out_space = full->attrs.space; |
0d3de77a FR |
317 | #else |
318 | g_assert_not_reached(); | |
319 | #endif | |
f3639a64 | 320 | } |
ac76c2e5 | 321 | |
48da29e4 | 322 | if (regime_is_stage2(s2_mmu_idx)) { |
f3639a64 RH |
323 | uint64_t hcr = arm_hcr_el2_eff_secstate(env, is_secure); |
324 | ||
325 | if ((hcr & HCR_PTW) && S2_attrs_are_device(hcr, pte_attrs)) { | |
11552bb0 RH |
326 | /* |
327 | * PTW set and S1 walk touched S2 Device memory: | |
328 | * generate Permission fault. | |
329 | */ | |
330 | fi->type = ARMFault_Permission; | |
331 | fi->s2addr = addr; | |
332 | fi->stage2 = true; | |
333 | fi->s1ptw = true; | |
ab1f7885 | 334 | fi->s1ns = !is_secure; |
6d2654ff | 335 | return false; |
11552bb0 | 336 | } |
11552bb0 | 337 | } |
6d2654ff | 338 | |
f3639a64 | 339 | ptw->out_be = regime_translation_big_endian(env, mmu_idx); |
6d2654ff | 340 | return true; |
f3639a64 RH |
341 | |
342 | fail: | |
343 | assert(fi->type != ARMFault_None); | |
344 | fi->s2addr = addr; | |
345 | fi->stage2 = true; | |
346 | fi->s1ptw = true; | |
347 | fi->s1ns = !is_secure; | |
348 | return false; | |
11552bb0 RH |
349 | } |
350 | ||
351 | /* All loads done in the course of a page table walk go through here. */ | |
93e5b3a6 | 352 | static uint32_t arm_ldl_ptw(CPUARMState *env, S1Translate *ptw, |
6d2654ff | 353 | ARMMMUFaultInfo *fi) |
11552bb0 | 354 | { |
5e79887b | 355 | CPUState *cs = env_cpu(env); |
71943a1e | 356 | void *host = ptw->out_host; |
11552bb0 RH |
357 | uint32_t data; |
358 | ||
71943a1e | 359 | if (likely(host)) { |
f3639a64 | 360 | /* Page tables are in RAM, and we have the host address. */ |
71943a1e | 361 | data = qatomic_read((uint32_t *)host); |
f3639a64 | 362 | if (ptw->out_be) { |
71943a1e | 363 | data = be32_to_cpu(data); |
f3639a64 | 364 | } else { |
71943a1e | 365 | data = le32_to_cpu(data); |
f3639a64 | 366 | } |
11552bb0 | 367 | } else { |
f3639a64 | 368 | /* Page tables are in MMIO. */ |
90c66293 RH |
369 | MemTxAttrs attrs = { |
370 | .secure = ptw->out_secure, | |
371 | .space = ptw->out_space, | |
372 | }; | |
f3639a64 RH |
373 | AddressSpace *as = arm_addressspace(cs, attrs); |
374 | MemTxResult result = MEMTX_OK; | |
375 | ||
376 | if (ptw->out_be) { | |
377 | data = address_space_ldl_be(as, ptw->out_phys, attrs, &result); | |
378 | } else { | |
379 | data = address_space_ldl_le(as, ptw->out_phys, attrs, &result); | |
380 | } | |
381 | if (unlikely(result != MEMTX_OK)) { | |
382 | fi->type = ARMFault_SyncExternalOnWalk; | |
383 | fi->ea = arm_extabort_type(result); | |
384 | return 0; | |
385 | } | |
11552bb0 | 386 | } |
f3639a64 | 387 | return data; |
11552bb0 RH |
388 | } |
389 | ||
93e5b3a6 | 390 | static uint64_t arm_ldq_ptw(CPUARMState *env, S1Translate *ptw, |
6d2654ff | 391 | ARMMMUFaultInfo *fi) |
11552bb0 | 392 | { |
5e79887b | 393 | CPUState *cs = env_cpu(env); |
71943a1e | 394 | void *host = ptw->out_host; |
11552bb0 RH |
395 | uint64_t data; |
396 | ||
71943a1e | 397 | if (likely(host)) { |
f3639a64 | 398 | /* Page tables are in RAM, and we have the host address. */ |
71943a1e RH |
399 | #ifdef CONFIG_ATOMIC64 |
400 | data = qatomic_read__nocheck((uint64_t *)host); | |
401 | if (ptw->out_be) { | |
402 | data = be64_to_cpu(data); | |
403 | } else { | |
404 | data = le64_to_cpu(data); | |
405 | } | |
406 | #else | |
f3639a64 | 407 | if (ptw->out_be) { |
71943a1e | 408 | data = ldq_be_p(host); |
f3639a64 | 409 | } else { |
71943a1e | 410 | data = ldq_le_p(host); |
f3639a64 | 411 | } |
71943a1e | 412 | #endif |
11552bb0 | 413 | } else { |
f3639a64 | 414 | /* Page tables are in MMIO. */ |
90c66293 RH |
415 | MemTxAttrs attrs = { |
416 | .secure = ptw->out_secure, | |
417 | .space = ptw->out_space, | |
418 | }; | |
f3639a64 RH |
419 | AddressSpace *as = arm_addressspace(cs, attrs); |
420 | MemTxResult result = MEMTX_OK; | |
421 | ||
422 | if (ptw->out_be) { | |
423 | data = address_space_ldq_be(as, ptw->out_phys, attrs, &result); | |
424 | } else { | |
425 | data = address_space_ldq_le(as, ptw->out_phys, attrs, &result); | |
426 | } | |
427 | if (unlikely(result != MEMTX_OK)) { | |
428 | fi->type = ARMFault_SyncExternalOnWalk; | |
429 | fi->ea = arm_extabort_type(result); | |
430 | return 0; | |
431 | } | |
11552bb0 | 432 | } |
f3639a64 | 433 | return data; |
11552bb0 RH |
434 | } |
435 | ||
71943a1e RH |
436 | static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val, |
437 | uint64_t new_val, S1Translate *ptw, | |
438 | ARMMMUFaultInfo *fi) | |
439 | { | |
d3ae5f5d | 440 | #ifdef TARGET_AARCH64 |
71943a1e RH |
441 | uint64_t cur_val; |
442 | void *host = ptw->out_host; | |
443 | ||
444 | if (unlikely(!host)) { | |
445 | fi->type = ARMFault_UnsuppAtomicUpdate; | |
446 | fi->s1ptw = true; | |
447 | return 0; | |
448 | } | |
449 | ||
450 | /* | |
451 | * Raising a stage2 Protection fault for an atomic update to a read-only | |
452 | * page is delayed until it is certain that there is a change to make. | |
453 | */ | |
454 | if (unlikely(!ptw->out_rw)) { | |
455 | int flags; | |
456 | void *discard; | |
457 | ||
458 | env->tlb_fi = fi; | |
1770b2f2 | 459 | flags = probe_access_flags(env, ptw->out_virt, 0, MMU_DATA_STORE, |
71943a1e RH |
460 | arm_to_core_mmu_idx(ptw->in_ptw_idx), |
461 | true, &discard, 0); | |
462 | env->tlb_fi = NULL; | |
463 | ||
464 | if (unlikely(flags & TLB_INVALID_MASK)) { | |
465 | assert(fi->type != ARMFault_None); | |
466 | fi->s2addr = ptw->out_virt; | |
467 | fi->stage2 = true; | |
468 | fi->s1ptw = true; | |
469 | fi->s1ns = !ptw->in_secure; | |
470 | return 0; | |
471 | } | |
472 | ||
473 | /* In case CAS mismatches and we loop, remember writability. */ | |
474 | ptw->out_rw = true; | |
475 | } | |
476 | ||
477 | #ifdef CONFIG_ATOMIC64 | |
478 | if (ptw->out_be) { | |
479 | old_val = cpu_to_be64(old_val); | |
480 | new_val = cpu_to_be64(new_val); | |
481 | cur_val = qatomic_cmpxchg__nocheck((uint64_t *)host, old_val, new_val); | |
482 | cur_val = be64_to_cpu(cur_val); | |
483 | } else { | |
484 | old_val = cpu_to_le64(old_val); | |
485 | new_val = cpu_to_le64(new_val); | |
486 | cur_val = qatomic_cmpxchg__nocheck((uint64_t *)host, old_val, new_val); | |
487 | cur_val = le64_to_cpu(cur_val); | |
488 | } | |
489 | #else | |
490 | /* | |
491 | * We can't support the full 64-bit atomic cmpxchg on the host. | |
492 | * Because this is only used for FEAT_HAFDBS, which is only for AA64, | |
493 | * we know that TCG_OVERSIZED_GUEST is set, which means that we are | |
494 | * running in round-robin mode and could only race with dma i/o. | |
495 | */ | |
d3ae5f5d | 496 | #if !TCG_OVERSIZED_GUEST |
71943a1e RH |
497 | # error "Unexpected configuration" |
498 | #endif | |
499 | bool locked = qemu_mutex_iothread_locked(); | |
500 | if (!locked) { | |
501 | qemu_mutex_lock_iothread(); | |
502 | } | |
503 | if (ptw->out_be) { | |
504 | cur_val = ldq_be_p(host); | |
505 | if (cur_val == old_val) { | |
506 | stq_be_p(host, new_val); | |
507 | } | |
508 | } else { | |
509 | cur_val = ldq_le_p(host); | |
510 | if (cur_val == old_val) { | |
511 | stq_le_p(host, new_val); | |
512 | } | |
513 | } | |
514 | if (!locked) { | |
515 | qemu_mutex_unlock_iothread(); | |
516 | } | |
517 | #endif | |
518 | ||
519 | return cur_val; | |
d3ae5f5d RH |
520 | #else |
521 | /* AArch32 does not have FEAT_HADFS. */ | |
522 | g_assert_not_reached(); | |
523 | #endif | |
71943a1e RH |
524 | } |
525 | ||
4c74ab15 RH |
526 | static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, |
527 | uint32_t *table, uint32_t address) | |
528 | { | |
529 | /* Note that we can only get here for an AArch32 PL0/PL1 lookup */ | |
c1547bba | 530 | uint64_t tcr = regime_tcr(env, mmu_idx); |
9e70e26c PM |
531 | int maskshift = extract32(tcr, 0, 3); |
532 | uint32_t mask = ~(((uint32_t)0xffffffffu) >> maskshift); | |
533 | uint32_t base_mask; | |
4c74ab15 | 534 | |
9e70e26c PM |
535 | if (address & mask) { |
536 | if (tcr & TTBCR_PD1) { | |
4c74ab15 RH |
537 | /* Translation table walk disabled for TTBR1 */ |
538 | return false; | |
539 | } | |
540 | *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000; | |
541 | } else { | |
9e70e26c | 542 | if (tcr & TTBCR_PD0) { |
4c74ab15 RH |
543 | /* Translation table walk disabled for TTBR0 */ |
544 | return false; | |
545 | } | |
9e70e26c PM |
546 | base_mask = ~((uint32_t)0x3fffu >> maskshift); |
547 | *table = regime_ttbr(env, mmu_idx, 0) & base_mask; | |
4c74ab15 RH |
548 | } |
549 | *table |= (address >> 18) & 0x3ffc; | |
550 | return true; | |
551 | } | |
552 | ||
4845d3be RH |
553 | /* |
554 | * Translate section/page access permissions to page R/W protection flags | |
555 | * @env: CPUARMState | |
556 | * @mmu_idx: MMU index indicating required translation regime | |
557 | * @ap: The 3-bit access permissions (AP[2:0]) | |
558 | * @domain_prot: The 2-bit domain access permissions | |
6f2d9d74 | 559 | * @is_user: TRUE if accessing from PL0 |
4845d3be | 560 | */ |
6f2d9d74 TK |
561 | static int ap_to_rw_prot_is_user(CPUARMState *env, ARMMMUIdx mmu_idx, |
562 | int ap, int domain_prot, bool is_user) | |
4845d3be | 563 | { |
4845d3be RH |
564 | if (domain_prot == 3) { |
565 | return PAGE_READ | PAGE_WRITE; | |
566 | } | |
567 | ||
568 | switch (ap) { | |
569 | case 0: | |
570 | if (arm_feature(env, ARM_FEATURE_V7)) { | |
571 | return 0; | |
572 | } | |
573 | switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) { | |
574 | case SCTLR_S: | |
575 | return is_user ? 0 : PAGE_READ; | |
576 | case SCTLR_R: | |
577 | return PAGE_READ; | |
578 | default: | |
579 | return 0; | |
580 | } | |
581 | case 1: | |
582 | return is_user ? 0 : PAGE_READ | PAGE_WRITE; | |
583 | case 2: | |
584 | if (is_user) { | |
585 | return PAGE_READ; | |
586 | } else { | |
587 | return PAGE_READ | PAGE_WRITE; | |
588 | } | |
589 | case 3: | |
590 | return PAGE_READ | PAGE_WRITE; | |
591 | case 4: /* Reserved. */ | |
592 | return 0; | |
593 | case 5: | |
594 | return is_user ? 0 : PAGE_READ; | |
595 | case 6: | |
596 | return PAGE_READ; | |
597 | case 7: | |
598 | if (!arm_feature(env, ARM_FEATURE_V6K)) { | |
599 | return 0; | |
600 | } | |
601 | return PAGE_READ; | |
602 | default: | |
603 | g_assert_not_reached(); | |
604 | } | |
605 | } | |
606 | ||
6f2d9d74 TK |
607 | /* |
608 | * Translate section/page access permissions to page R/W protection flags | |
609 | * @env: CPUARMState | |
610 | * @mmu_idx: MMU index indicating required translation regime | |
611 | * @ap: The 3-bit access permissions (AP[2:0]) | |
612 | * @domain_prot: The 2-bit domain access permissions | |
613 | */ | |
614 | static int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, | |
615 | int ap, int domain_prot) | |
616 | { | |
617 | return ap_to_rw_prot_is_user(env, mmu_idx, ap, domain_prot, | |
618 | regime_is_user(env, mmu_idx)); | |
619 | } | |
620 | ||
4845d3be RH |
621 | /* |
622 | * Translate section/page access permissions to page R/W protection flags. | |
623 | * @ap: The 2-bit simple AP (AP[2:1]) | |
624 | * @is_user: TRUE if accessing from PL0 | |
625 | */ | |
626 | static int simple_ap_to_rw_prot_is_user(int ap, bool is_user) | |
627 | { | |
628 | switch (ap) { | |
629 | case 0: | |
630 | return is_user ? 0 : PAGE_READ | PAGE_WRITE; | |
631 | case 1: | |
632 | return PAGE_READ | PAGE_WRITE; | |
633 | case 2: | |
634 | return is_user ? 0 : PAGE_READ; | |
635 | case 3: | |
636 | return PAGE_READ; | |
637 | default: | |
638 | g_assert_not_reached(); | |
639 | } | |
640 | } | |
641 | ||
642 | static int simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap) | |
643 | { | |
644 | return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx)); | |
645 | } | |
646 | ||
6d2654ff RH |
647 | static bool get_phys_addr_v5(CPUARMState *env, S1Translate *ptw, |
648 | uint32_t address, MMUAccessType access_type, | |
649 | GetPhysAddrResult *result, ARMMMUFaultInfo *fi) | |
f2d2f5ce | 650 | { |
f2d2f5ce RH |
651 | int level = 1; |
652 | uint32_t table; | |
653 | uint32_t desc; | |
654 | int type; | |
655 | int ap; | |
656 | int domain = 0; | |
657 | int domain_prot; | |
658 | hwaddr phys_addr; | |
659 | uint32_t dacr; | |
660 | ||
661 | /* Pagetable walk. */ | |
662 | /* Lookup l1 descriptor. */ | |
6d2654ff | 663 | if (!get_level1_table_address(env, ptw->in_mmu_idx, &table, address)) { |
f2d2f5ce RH |
664 | /* Section translation fault if page walk is disabled by PD0 or PD1 */ |
665 | fi->type = ARMFault_Translation; | |
666 | goto do_fault; | |
667 | } | |
93e5b3a6 RH |
668 | if (!S1_ptw_translate(env, ptw, table, fi)) { |
669 | goto do_fault; | |
670 | } | |
671 | desc = arm_ldl_ptw(env, ptw, fi); | |
f2d2f5ce RH |
672 | if (fi->type != ARMFault_None) { |
673 | goto do_fault; | |
674 | } | |
675 | type = (desc & 3); | |
676 | domain = (desc >> 5) & 0x0f; | |
6d2654ff | 677 | if (regime_el(env, ptw->in_mmu_idx) == 1) { |
f2d2f5ce RH |
678 | dacr = env->cp15.dacr_ns; |
679 | } else { | |
680 | dacr = env->cp15.dacr_s; | |
681 | } | |
682 | domain_prot = (dacr >> (domain * 2)) & 3; | |
683 | if (type == 0) { | |
684 | /* Section translation fault. */ | |
685 | fi->type = ARMFault_Translation; | |
686 | goto do_fault; | |
687 | } | |
688 | if (type != 2) { | |
689 | level = 2; | |
690 | } | |
691 | if (domain_prot == 0 || domain_prot == 2) { | |
692 | fi->type = ARMFault_Domain; | |
693 | goto do_fault; | |
694 | } | |
695 | if (type == 2) { | |
696 | /* 1Mb section. */ | |
697 | phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); | |
698 | ap = (desc >> 10) & 3; | |
7fa7ea8f | 699 | result->f.lg_page_size = 20; /* 1MB */ |
f2d2f5ce RH |
700 | } else { |
701 | /* Lookup l2 entry. */ | |
702 | if (type == 1) { | |
703 | /* Coarse pagetable. */ | |
704 | table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); | |
705 | } else { | |
706 | /* Fine pagetable. */ | |
707 | table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); | |
708 | } | |
93e5b3a6 RH |
709 | if (!S1_ptw_translate(env, ptw, table, fi)) { |
710 | goto do_fault; | |
711 | } | |
712 | desc = arm_ldl_ptw(env, ptw, fi); | |
f2d2f5ce RH |
713 | if (fi->type != ARMFault_None) { |
714 | goto do_fault; | |
715 | } | |
716 | switch (desc & 3) { | |
717 | case 0: /* Page translation fault. */ | |
718 | fi->type = ARMFault_Translation; | |
719 | goto do_fault; | |
720 | case 1: /* 64k page. */ | |
721 | phys_addr = (desc & 0xffff0000) | (address & 0xffff); | |
722 | ap = (desc >> (4 + ((address >> 13) & 6))) & 3; | |
7fa7ea8f | 723 | result->f.lg_page_size = 16; |
f2d2f5ce RH |
724 | break; |
725 | case 2: /* 4k page. */ | |
726 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
727 | ap = (desc >> (4 + ((address >> 9) & 6))) & 3; | |
7fa7ea8f | 728 | result->f.lg_page_size = 12; |
f2d2f5ce RH |
729 | break; |
730 | case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */ | |
731 | if (type == 1) { | |
732 | /* ARMv6/XScale extended small page format */ | |
733 | if (arm_feature(env, ARM_FEATURE_XSCALE) | |
734 | || arm_feature(env, ARM_FEATURE_V6)) { | |
735 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
7fa7ea8f | 736 | result->f.lg_page_size = 12; |
f2d2f5ce RH |
737 | } else { |
738 | /* | |
739 | * UNPREDICTABLE in ARMv5; we choose to take a | |
740 | * page translation fault. | |
741 | */ | |
742 | fi->type = ARMFault_Translation; | |
743 | goto do_fault; | |
744 | } | |
745 | } else { | |
746 | phys_addr = (desc & 0xfffffc00) | (address & 0x3ff); | |
7fa7ea8f | 747 | result->f.lg_page_size = 10; |
f2d2f5ce RH |
748 | } |
749 | ap = (desc >> 4) & 3; | |
750 | break; | |
751 | default: | |
752 | /* Never happens, but compiler isn't smart enough to tell. */ | |
753 | g_assert_not_reached(); | |
754 | } | |
755 | } | |
6d2654ff | 756 | result->f.prot = ap_to_rw_prot(env, ptw->in_mmu_idx, ap, domain_prot); |
7fa7ea8f RH |
757 | result->f.prot |= result->f.prot ? PAGE_EXEC : 0; |
758 | if (!(result->f.prot & (1 << access_type))) { | |
f2d2f5ce RH |
759 | /* Access permission fault. */ |
760 | fi->type = ARMFault_Permission; | |
761 | goto do_fault; | |
762 | } | |
7fa7ea8f | 763 | result->f.phys_addr = phys_addr; |
f2d2f5ce | 764 | return false; |
53c038ef RH |
765 | do_fault: |
766 | fi->domain = domain; | |
767 | fi->level = level; | |
768 | return true; | |
769 | } | |
770 | ||
6d2654ff RH |
771 | static bool get_phys_addr_v6(CPUARMState *env, S1Translate *ptw, |
772 | uint32_t address, MMUAccessType access_type, | |
773 | GetPhysAddrResult *result, ARMMMUFaultInfo *fi) | |
53c038ef | 774 | { |
53c038ef | 775 | ARMCPU *cpu = env_archcpu(env); |
6d2654ff | 776 | ARMMMUIdx mmu_idx = ptw->in_mmu_idx; |
53c038ef RH |
777 | int level = 1; |
778 | uint32_t table; | |
779 | uint32_t desc; | |
780 | uint32_t xn; | |
781 | uint32_t pxn = 0; | |
782 | int type; | |
783 | int ap; | |
784 | int domain = 0; | |
785 | int domain_prot; | |
786 | hwaddr phys_addr; | |
787 | uint32_t dacr; | |
788 | bool ns; | |
6f2d9d74 | 789 | int user_prot; |
53c038ef RH |
790 | |
791 | /* Pagetable walk. */ | |
792 | /* Lookup l1 descriptor. */ | |
793 | if (!get_level1_table_address(env, mmu_idx, &table, address)) { | |
794 | /* Section translation fault if page walk is disabled by PD0 or PD1 */ | |
795 | fi->type = ARMFault_Translation; | |
796 | goto do_fault; | |
797 | } | |
93e5b3a6 RH |
798 | if (!S1_ptw_translate(env, ptw, table, fi)) { |
799 | goto do_fault; | |
800 | } | |
801 | desc = arm_ldl_ptw(env, ptw, fi); | |
53c038ef RH |
802 | if (fi->type != ARMFault_None) { |
803 | goto do_fault; | |
804 | } | |
805 | type = (desc & 3); | |
806 | if (type == 0 || (type == 3 && !cpu_isar_feature(aa32_pxn, cpu))) { | |
807 | /* Section translation fault, or attempt to use the encoding | |
808 | * which is Reserved on implementations without PXN. | |
809 | */ | |
810 | fi->type = ARMFault_Translation; | |
811 | goto do_fault; | |
812 | } | |
813 | if ((type == 1) || !(desc & (1 << 18))) { | |
814 | /* Page or Section. */ | |
815 | domain = (desc >> 5) & 0x0f; | |
816 | } | |
817 | if (regime_el(env, mmu_idx) == 1) { | |
818 | dacr = env->cp15.dacr_ns; | |
819 | } else { | |
820 | dacr = env->cp15.dacr_s; | |
821 | } | |
822 | if (type == 1) { | |
823 | level = 2; | |
824 | } | |
825 | domain_prot = (dacr >> (domain * 2)) & 3; | |
826 | if (domain_prot == 0 || domain_prot == 2) { | |
827 | /* Section or Page domain fault */ | |
828 | fi->type = ARMFault_Domain; | |
829 | goto do_fault; | |
830 | } | |
831 | if (type != 1) { | |
832 | if (desc & (1 << 18)) { | |
833 | /* Supersection. */ | |
834 | phys_addr = (desc & 0xff000000) | (address & 0x00ffffff); | |
835 | phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32; | |
836 | phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36; | |
7fa7ea8f | 837 | result->f.lg_page_size = 24; /* 16MB */ |
53c038ef RH |
838 | } else { |
839 | /* Section. */ | |
840 | phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); | |
7fa7ea8f | 841 | result->f.lg_page_size = 20; /* 1MB */ |
53c038ef RH |
842 | } |
843 | ap = ((desc >> 10) & 3) | ((desc >> 13) & 4); | |
844 | xn = desc & (1 << 4); | |
845 | pxn = desc & 1; | |
846 | ns = extract32(desc, 19, 1); | |
847 | } else { | |
848 | if (cpu_isar_feature(aa32_pxn, cpu)) { | |
849 | pxn = (desc >> 2) & 1; | |
850 | } | |
851 | ns = extract32(desc, 3, 1); | |
852 | /* Lookup l2 entry. */ | |
853 | table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); | |
93e5b3a6 RH |
854 | if (!S1_ptw_translate(env, ptw, table, fi)) { |
855 | goto do_fault; | |
856 | } | |
857 | desc = arm_ldl_ptw(env, ptw, fi); | |
53c038ef RH |
858 | if (fi->type != ARMFault_None) { |
859 | goto do_fault; | |
860 | } | |
861 | ap = ((desc >> 4) & 3) | ((desc >> 7) & 4); | |
862 | switch (desc & 3) { | |
863 | case 0: /* Page translation fault. */ | |
864 | fi->type = ARMFault_Translation; | |
865 | goto do_fault; | |
866 | case 1: /* 64k page. */ | |
867 | phys_addr = (desc & 0xffff0000) | (address & 0xffff); | |
868 | xn = desc & (1 << 15); | |
7fa7ea8f | 869 | result->f.lg_page_size = 16; |
53c038ef RH |
870 | break; |
871 | case 2: case 3: /* 4k page. */ | |
872 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
873 | xn = desc & 1; | |
7fa7ea8f | 874 | result->f.lg_page_size = 12; |
53c038ef RH |
875 | break; |
876 | default: | |
877 | /* Never happens, but compiler isn't smart enough to tell. */ | |
878 | g_assert_not_reached(); | |
879 | } | |
880 | } | |
881 | if (domain_prot == 3) { | |
7fa7ea8f | 882 | result->f.prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
53c038ef RH |
883 | } else { |
884 | if (pxn && !regime_is_user(env, mmu_idx)) { | |
885 | xn = 1; | |
886 | } | |
887 | if (xn && access_type == MMU_INST_FETCH) { | |
888 | fi->type = ARMFault_Permission; | |
889 | goto do_fault; | |
890 | } | |
891 | ||
892 | if (arm_feature(env, ARM_FEATURE_V6K) && | |
893 | (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) { | |
894 | /* The simplified model uses AP[0] as an access control bit. */ | |
895 | if ((ap & 1) == 0) { | |
896 | /* Access flag fault. */ | |
897 | fi->type = ARMFault_AccessFlag; | |
898 | goto do_fault; | |
899 | } | |
7fa7ea8f | 900 | result->f.prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1); |
6f2d9d74 | 901 | user_prot = simple_ap_to_rw_prot_is_user(ap >> 1, 1); |
53c038ef | 902 | } else { |
7fa7ea8f | 903 | result->f.prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); |
6f2d9d74 | 904 | user_prot = ap_to_rw_prot_is_user(env, mmu_idx, ap, domain_prot, 1); |
53c038ef | 905 | } |
7fa7ea8f RH |
906 | if (result->f.prot && !xn) { |
907 | result->f.prot |= PAGE_EXEC; | |
53c038ef | 908 | } |
7fa7ea8f | 909 | if (!(result->f.prot & (1 << access_type))) { |
53c038ef RH |
910 | /* Access permission fault. */ |
911 | fi->type = ARMFault_Permission; | |
912 | goto do_fault; | |
913 | } | |
6f2d9d74 TK |
914 | if (regime_is_pan(env, mmu_idx) && |
915 | !regime_is_user(env, mmu_idx) && | |
916 | user_prot && | |
917 | access_type != MMU_INST_FETCH) { | |
918 | /* Privileged Access Never fault */ | |
919 | fi->type = ARMFault_Permission; | |
920 | goto do_fault; | |
921 | } | |
53c038ef RH |
922 | } |
923 | if (ns) { | |
924 | /* The NS bit will (as required by the architecture) have no effect if | |
925 | * the CPU doesn't support TZ or this is a non-secure translation | |
926 | * regime, because the attribute will already be non-secure. | |
927 | */ | |
7fa7ea8f | 928 | result->f.attrs.secure = false; |
90c66293 | 929 | result->f.attrs.space = ARMSS_NonSecure; |
53c038ef | 930 | } |
7fa7ea8f | 931 | result->f.phys_addr = phys_addr; |
53c038ef | 932 | return false; |
f2d2f5ce RH |
933 | do_fault: |
934 | fi->domain = domain; | |
935 | fi->level = level; | |
936 | return true; | |
937 | } | |
938 | ||
f8526edc RH |
939 | /* |
940 | * Translate S2 section/page access permissions to protection flags | |
941 | * @env: CPUARMState | |
942 | * @s2ap: The 2-bit stage2 access permissions (S2AP) | |
943 | * @xn: XN (execute-never) bits | |
944 | * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0 | |
945 | */ | |
946 | static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0) | |
947 | { | |
948 | int prot = 0; | |
949 | ||
950 | if (s2ap & 1) { | |
951 | prot |= PAGE_READ; | |
952 | } | |
953 | if (s2ap & 2) { | |
954 | prot |= PAGE_WRITE; | |
955 | } | |
956 | ||
957 | if (cpu_isar_feature(any_tts2uxn, env_archcpu(env))) { | |
958 | switch (xn) { | |
959 | case 0: | |
960 | prot |= PAGE_EXEC; | |
961 | break; | |
962 | case 1: | |
963 | if (s1_is_el0) { | |
964 | prot |= PAGE_EXEC; | |
965 | } | |
966 | break; | |
967 | case 2: | |
968 | break; | |
969 | case 3: | |
970 | if (!s1_is_el0) { | |
971 | prot |= PAGE_EXEC; | |
972 | } | |
973 | break; | |
974 | default: | |
975 | g_assert_not_reached(); | |
976 | } | |
977 | } else { | |
978 | if (!extract32(xn, 1, 1)) { | |
979 | if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) { | |
980 | prot |= PAGE_EXEC; | |
981 | } | |
982 | } | |
983 | } | |
984 | return prot; | |
985 | } | |
986 | ||
987 | /* | |
988 | * Translate section/page access permissions to protection flags | |
989 | * @env: CPUARMState | |
990 | * @mmu_idx: MMU index indicating required translation regime | |
991 | * @is_aa64: TRUE if AArch64 | |
992 | * @ap: The 2-bit simple AP (AP[2:1]) | |
993 | * @ns: NS (non-secure) bit | |
994 | * @xn: XN (execute-never) bit | |
995 | * @pxn: PXN (privileged execute-never) bit | |
996 | */ | |
997 | static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, | |
998 | int ap, int ns, int xn, int pxn) | |
999 | { | |
dd17143f | 1000 | ARMCPU *cpu = env_archcpu(env); |
f8526edc RH |
1001 | bool is_user = regime_is_user(env, mmu_idx); |
1002 | int prot_rw, user_rw; | |
1003 | bool have_wxn; | |
1004 | int wxn = 0; | |
1005 | ||
edc05dd4 | 1006 | assert(!regime_is_stage2(mmu_idx)); |
f8526edc RH |
1007 | |
1008 | user_rw = simple_ap_to_rw_prot_is_user(ap, true); | |
1009 | if (is_user) { | |
1010 | prot_rw = user_rw; | |
1011 | } else { | |
dd17143f PM |
1012 | /* |
1013 | * PAN controls can forbid data accesses but don't affect insn fetch. | |
1014 | * Plain PAN forbids data accesses if EL0 has data permissions; | |
1015 | * PAN3 forbids data accesses if EL0 has either data or exec perms. | |
1016 | * Note that for AArch64 the 'user can exec' case is exactly !xn. | |
1017 | * We make the IMPDEF choices that SCR_EL3.SIF and Realm EL2&0 | |
1018 | * do not affect EPAN. | |
1019 | */ | |
f8526edc | 1020 | if (user_rw && regime_is_pan(env, mmu_idx)) { |
dd17143f PM |
1021 | prot_rw = 0; |
1022 | } else if (cpu_isar_feature(aa64_pan3, cpu) && is_aa64 && | |
1023 | regime_is_pan(env, mmu_idx) && | |
1024 | (regime_sctlr(env, mmu_idx) & SCTLR_EPAN) && !xn) { | |
f8526edc RH |
1025 | prot_rw = 0; |
1026 | } else { | |
1027 | prot_rw = simple_ap_to_rw_prot_is_user(ap, false); | |
1028 | } | |
1029 | } | |
1030 | ||
1031 | if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) { | |
1032 | return prot_rw; | |
1033 | } | |
1034 | ||
1035 | /* TODO have_wxn should be replaced with | |
1036 | * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2) | |
1037 | * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE | |
1038 | * compatible processors have EL2, which is required for [U]WXN. | |
1039 | */ | |
1040 | have_wxn = arm_feature(env, ARM_FEATURE_LPAE); | |
1041 | ||
1042 | if (have_wxn) { | |
1043 | wxn = regime_sctlr(env, mmu_idx) & SCTLR_WXN; | |
1044 | } | |
1045 | ||
1046 | if (is_aa64) { | |
1047 | if (regime_has_2_ranges(mmu_idx) && !is_user) { | |
1048 | xn = pxn || (user_rw & PAGE_WRITE); | |
1049 | } | |
1050 | } else if (arm_feature(env, ARM_FEATURE_V7)) { | |
1051 | switch (regime_el(env, mmu_idx)) { | |
1052 | case 1: | |
1053 | case 3: | |
1054 | if (is_user) { | |
1055 | xn = xn || !(user_rw & PAGE_READ); | |
1056 | } else { | |
1057 | int uwxn = 0; | |
1058 | if (have_wxn) { | |
1059 | uwxn = regime_sctlr(env, mmu_idx) & SCTLR_UWXN; | |
1060 | } | |
1061 | xn = xn || !(prot_rw & PAGE_READ) || pxn || | |
1062 | (uwxn && (user_rw & PAGE_WRITE)); | |
1063 | } | |
1064 | break; | |
1065 | case 2: | |
1066 | break; | |
1067 | } | |
1068 | } else { | |
1069 | xn = wxn = 0; | |
1070 | } | |
1071 | ||
1072 | if (xn || (wxn && (prot_rw & PAGE_WRITE))) { | |
1073 | return prot_rw; | |
1074 | } | |
1075 | return prot_rw | PAGE_EXEC; | |
1076 | } | |
1077 | ||
2f0ec92e RH |
1078 | static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, |
1079 | ARMMMUIdx mmu_idx) | |
1080 | { | |
c1547bba | 1081 | uint64_t tcr = regime_tcr(env, mmu_idx); |
2f0ec92e RH |
1082 | uint32_t el = regime_el(env, mmu_idx); |
1083 | int select, tsz; | |
1084 | bool epd, hpd; | |
1085 | ||
1086 | assert(mmu_idx != ARMMMUIdx_Stage2_S); | |
1087 | ||
1088 | if (mmu_idx == ARMMMUIdx_Stage2) { | |
1089 | /* VTCR */ | |
1090 | bool sext = extract32(tcr, 4, 1); | |
1091 | bool sign = extract32(tcr, 3, 1); | |
1092 | ||
1093 | /* | |
1094 | * If the sign-extend bit is not the same as t0sz[3], the result | |
1095 | * is unpredictable. Flag this as a guest error. | |
1096 | */ | |
1097 | if (sign != sext) { | |
1098 | qemu_log_mask(LOG_GUEST_ERROR, | |
1099 | "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n"); | |
1100 | } | |
1101 | tsz = sextract32(tcr, 0, 4) + 8; | |
1102 | select = 0; | |
1103 | hpd = false; | |
1104 | epd = false; | |
1105 | } else if (el == 2) { | |
1106 | /* HTCR */ | |
1107 | tsz = extract32(tcr, 0, 3); | |
1108 | select = 0; | |
1109 | hpd = extract64(tcr, 24, 1); | |
1110 | epd = false; | |
1111 | } else { | |
1112 | int t0sz = extract32(tcr, 0, 3); | |
1113 | int t1sz = extract32(tcr, 16, 3); | |
1114 | ||
1115 | if (t1sz == 0) { | |
1116 | select = va > (0xffffffffu >> t0sz); | |
1117 | } else { | |
1118 | /* Note that we will detect errors later. */ | |
1119 | select = va >= ~(0xffffffffu >> t1sz); | |
1120 | } | |
1121 | if (!select) { | |
1122 | tsz = t0sz; | |
1123 | epd = extract32(tcr, 7, 1); | |
1124 | hpd = extract64(tcr, 41, 1); | |
1125 | } else { | |
1126 | tsz = t1sz; | |
1127 | epd = extract32(tcr, 23, 1); | |
1128 | hpd = extract64(tcr, 42, 1); | |
1129 | } | |
1130 | /* For aarch32, hpd0 is not enabled without t2e as well. */ | |
1131 | hpd &= extract32(tcr, 6, 1); | |
1132 | } | |
1133 | ||
1134 | return (ARMVAParameters) { | |
1135 | .tsz = tsz, | |
1136 | .select = select, | |
1137 | .epd = epd, | |
1138 | .hpd = hpd, | |
1139 | }; | |
1140 | } | |
1141 | ||
c5168785 RH |
1142 | /* |
1143 | * check_s2_mmu_setup | |
1144 | * @cpu: ARMCPU | |
1145 | * @is_aa64: True if the translation regime is in AArch64 state | |
0ffe5b7b RH |
1146 | * @tcr: VTCR_EL2 or VSTCR_EL2 |
1147 | * @ds: Effective value of TCR.DS. | |
1148 | * @iasize: Bitsize of IPAs | |
c5168785 RH |
1149 | * @stride: Page-table stride (See the ARM ARM) |
1150 | * | |
0ffe5b7b RH |
1151 | * Decode the starting level of the S2 lookup, returning INT_MIN if |
1152 | * the configuration is invalid. | |
c5168785 | 1153 | */ |
0ffe5b7b RH |
1154 | static int check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, uint64_t tcr, |
1155 | bool ds, int iasize, int stride) | |
c5168785 | 1156 | { |
0ffe5b7b RH |
1157 | int sl0, sl2, startlevel, granulebits, levels; |
1158 | int s1_min_iasize, s1_max_iasize; | |
c5168785 | 1159 | |
0ffe5b7b | 1160 | sl0 = extract32(tcr, 6, 2); |
c5168785 | 1161 | if (is_aa64) { |
0ffe5b7b RH |
1162 | /* |
1163 | * AArch64.S2InvalidSL: Interpretation of SL depends on the page size, | |
1164 | * so interleave AArch64.S2StartLevel. | |
1165 | */ | |
c5168785 | 1166 | switch (stride) { |
0ffe5b7b RH |
1167 | case 9: /* 4KB */ |
1168 | /* SL2 is RES0 unless DS=1 & 4KB granule. */ | |
1169 | sl2 = extract64(tcr, 33, 1); | |
1170 | if (ds && sl2) { | |
1171 | if (sl0 != 0) { | |
1172 | goto fail; | |
1173 | } | |
1174 | startlevel = -1; | |
1175 | } else { | |
1176 | startlevel = 2 - sl0; | |
1177 | switch (sl0) { | |
1178 | case 2: | |
1179 | if (arm_pamax(cpu) < 44) { | |
1180 | goto fail; | |
1181 | } | |
1182 | break; | |
1183 | case 3: | |
1184 | if (!cpu_isar_feature(aa64_st, cpu)) { | |
1185 | goto fail; | |
1186 | } | |
1187 | startlevel = 3; | |
1188 | break; | |
1189 | } | |
c5168785 RH |
1190 | } |
1191 | break; | |
0ffe5b7b RH |
1192 | case 11: /* 16KB */ |
1193 | switch (sl0) { | |
1194 | case 2: | |
1195 | if (arm_pamax(cpu) < 42) { | |
1196 | goto fail; | |
1197 | } | |
1198 | break; | |
1199 | case 3: | |
1200 | if (!ds) { | |
1201 | goto fail; | |
1202 | } | |
1203 | break; | |
c5168785 | 1204 | } |
0ffe5b7b | 1205 | startlevel = 3 - sl0; |
c5168785 | 1206 | break; |
0ffe5b7b RH |
1207 | case 13: /* 64KB */ |
1208 | switch (sl0) { | |
1209 | case 2: | |
1210 | if (arm_pamax(cpu) < 44) { | |
1211 | goto fail; | |
1212 | } | |
1213 | break; | |
1214 | case 3: | |
1215 | goto fail; | |
c5168785 | 1216 | } |
0ffe5b7b | 1217 | startlevel = 3 - sl0; |
c5168785 RH |
1218 | break; |
1219 | default: | |
1220 | g_assert_not_reached(); | |
1221 | } | |
c5168785 | 1222 | } else { |
0ffe5b7b RH |
1223 | /* |
1224 | * Things are simpler for AArch32 EL2, with only 4k pages. | |
1225 | * There is no separate S2InvalidSL function, but AArch32.S2Walk | |
1226 | * begins with walkparms.sl0 in {'1x'}. | |
1227 | */ | |
c5168785 | 1228 | assert(stride == 9); |
0ffe5b7b RH |
1229 | if (sl0 >= 2) { |
1230 | goto fail; | |
c5168785 | 1231 | } |
0ffe5b7b | 1232 | startlevel = 2 - sl0; |
c5168785 | 1233 | } |
0ffe5b7b RH |
1234 | |
1235 | /* AArch{64,32}.S2InconsistentSL are functionally equivalent. */ | |
1236 | levels = 3 - startlevel; | |
1237 | granulebits = stride + 3; | |
1238 | ||
1239 | s1_min_iasize = levels * stride + granulebits + 1; | |
1240 | s1_max_iasize = s1_min_iasize + (stride - 1) + 4; | |
1241 | ||
1242 | if (iasize >= s1_min_iasize && iasize <= s1_max_iasize) { | |
1243 | return startlevel; | |
1244 | } | |
1245 | ||
1246 | fail: | |
1247 | return INT_MIN; | |
c5168785 RH |
1248 | } |
1249 | ||
3283222a RH |
1250 | /** |
1251 | * get_phys_addr_lpae: perform one stage of page table walk, LPAE format | |
1252 | * | |
1253 | * Returns false if the translation was successful. Otherwise, phys_ptr, | |
1254 | * attrs, prot and page_size may not be filled in, and the populated fsr | |
1255 | * value provides information on why the translation aborted, in the format | |
1256 | * of a long-format DFSR/IFSR fault register, with the following caveat: | |
1257 | * the WnR bit is never set (the caller must do this). | |
1258 | * | |
1259 | * @env: CPUARMState | |
6d2654ff | 1260 | * @ptw: Current and next stage parameters for the walk. |
3283222a RH |
1261 | * @address: virtual address to get physical address for |
1262 | * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH | |
6d2654ff RH |
1263 | * @s1_is_el0: if @ptw->in_mmu_idx is ARMMMUIdx_Stage2 |
1264 | * (so this is a stage 2 page table walk), | |
1265 | * must be true if this is stage 2 of a stage 1+2 | |
3283222a RH |
1266 | * walk for an EL0 access. If @mmu_idx is anything else, |
1267 | * @s1_is_el0 is ignored. | |
03ee9bbe | 1268 | * @result: set on translation success, |
3283222a | 1269 | * @fi: set to fault info if the translation fails |
3283222a | 1270 | */ |
6d2654ff RH |
1271 | static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, |
1272 | uint64_t address, | |
1273 | MMUAccessType access_type, bool s1_is_el0, | |
c23f08a5 | 1274 | GetPhysAddrResult *result, ARMMMUFaultInfo *fi) |
3283222a RH |
1275 | { |
1276 | ARMCPU *cpu = env_archcpu(env); | |
6d2654ff RH |
1277 | ARMMMUIdx mmu_idx = ptw->in_mmu_idx; |
1278 | bool is_secure = ptw->in_secure; | |
15f8f467 | 1279 | int32_t level; |
3283222a RH |
1280 | ARMVAParameters param; |
1281 | uint64_t ttbr; | |
1282 | hwaddr descaddr, indexmask, indexmask_grainsize; | |
1283 | uint32_t tableattrs; | |
1284 | target_ulong page_size; | |
45666091 | 1285 | uint64_t attrs; |
3283222a RH |
1286 | int32_t stride; |
1287 | int addrsize, inputsize, outputsize; | |
c1547bba | 1288 | uint64_t tcr = regime_tcr(env, mmu_idx); |
3283222a RH |
1289 | int ap, ns, xn, pxn; |
1290 | uint32_t el = regime_el(env, mmu_idx); | |
1291 | uint64_t descaddrmask; | |
1292 | bool aarch64 = arm_el_is_aa64(env, el); | |
71943a1e | 1293 | uint64_t descriptor, new_descriptor; |
fe4ddc15 | 1294 | bool nstable; |
3283222a RH |
1295 | |
1296 | /* TODO: This code does not support shareability levels. */ | |
1297 | if (aarch64) { | |
1298 | int ps; | |
1299 | ||
1300 | param = aa64_va_parameters(env, address, mmu_idx, | |
478dccbb PM |
1301 | access_type != MMU_INST_FETCH, |
1302 | !arm_el_is_aa64(env, 1)); | |
3283222a RH |
1303 | level = 0; |
1304 | ||
1305 | /* | |
1306 | * If TxSZ is programmed to a value larger than the maximum, | |
1307 | * or smaller than the effective minimum, it is IMPLEMENTATION | |
1308 | * DEFINED whether we behave as if the field were programmed | |
1309 | * within bounds, or if a level 0 Translation fault is generated. | |
1310 | * | |
1311 | * With FEAT_LVA, fault on less than minimum becomes required, | |
1312 | * so our choice is to always raise the fault. | |
1313 | */ | |
1314 | if (param.tsz_oob) { | |
27c1b81d | 1315 | goto do_translation_fault; |
3283222a RH |
1316 | } |
1317 | ||
1318 | addrsize = 64 - 8 * param.tbi; | |
1319 | inputsize = 64 - param.tsz; | |
1320 | ||
1321 | /* | |
1322 | * Bound PS by PARANGE to find the effective output address size. | |
1323 | * ID_AA64MMFR0 is a read-only register so values outside of the | |
1324 | * supported mappings can be considered an implementation error. | |
1325 | */ | |
1326 | ps = FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); | |
1327 | ps = MIN(ps, param.ps); | |
1328 | assert(ps < ARRAY_SIZE(pamax_map)); | |
1329 | outputsize = pamax_map[ps]; | |
312b71ab AB |
1330 | |
1331 | /* | |
1332 | * With LPA2, the effective output address (OA) size is at most 48 bits | |
1333 | * unless TCR.DS == 1 | |
1334 | */ | |
1335 | if (!param.ds && param.gran != Gran64K) { | |
1336 | outputsize = MIN(outputsize, 48); | |
1337 | } | |
3283222a RH |
1338 | } else { |
1339 | param = aa32_va_parameters(env, address, mmu_idx); | |
1340 | level = 1; | |
1341 | addrsize = (mmu_idx == ARMMMUIdx_Stage2 ? 40 : 32); | |
1342 | inputsize = addrsize - param.tsz; | |
1343 | outputsize = 40; | |
1344 | } | |
1345 | ||
1346 | /* | |
1347 | * We determined the region when collecting the parameters, but we | |
1348 | * have not yet validated that the address is valid for the region. | |
1349 | * Extract the top bits and verify that they all match select. | |
1350 | * | |
1351 | * For aa32, if inputsize == addrsize, then we have selected the | |
1352 | * region by exclusion in aa32_va_parameters and there is no more | |
1353 | * validation to do here. | |
1354 | */ | |
1355 | if (inputsize < addrsize) { | |
1356 | target_ulong top_bits = sextract64(address, inputsize, | |
1357 | addrsize - inputsize); | |
1358 | if (-top_bits != param.select) { | |
1359 | /* The gap between the two regions is a Translation fault */ | |
27c1b81d | 1360 | goto do_translation_fault; |
3283222a RH |
1361 | } |
1362 | } | |
1363 | ||
3c003f70 | 1364 | stride = arm_granule_bits(param.gran) - 3; |
3283222a RH |
1365 | |
1366 | /* | |
1367 | * Note that QEMU ignores shareability and cacheability attributes, | |
1368 | * so we don't need to do anything with the SH, ORGN, IRGN fields | |
1369 | * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the | |
1370 | * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently | |
1371 | * implement any ASID-like capability so we can ignore it (instead | |
1372 | * we will always flush the TLB any time the ASID is changed). | |
1373 | */ | |
1374 | ttbr = regime_ttbr(env, mmu_idx, param.select); | |
1375 | ||
1376 | /* | |
1377 | * Here we should have set up all the parameters for the translation: | |
1378 | * inputsize, ttbr, epd, stride, tbi | |
1379 | */ | |
1380 | ||
1381 | if (param.epd) { | |
1382 | /* | |
1383 | * Translation table walk disabled => Translation fault on TLB miss | |
1384 | * Note: This is always 0 on 64-bit EL2 and EL3. | |
1385 | */ | |
27c1b81d | 1386 | goto do_translation_fault; |
3283222a RH |
1387 | } |
1388 | ||
edc05dd4 | 1389 | if (!regime_is_stage2(mmu_idx)) { |
3283222a RH |
1390 | /* |
1391 | * The starting level depends on the virtual address size (which can | |
1392 | * be up to 48 bits) and the translation granule size. It indicates | |
1393 | * the number of strides (stride bits at a time) needed to | |
1394 | * consume the bits of the input address. In the pseudocode this is: | |
1395 | * level = 4 - RoundUp((inputsize - grainsize) / stride) | |
1396 | * where their 'inputsize' is our 'inputsize', 'grainsize' is | |
1397 | * our 'stride + 3' and 'stride' is our 'stride'. | |
1398 | * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying: | |
1399 | * = 4 - (inputsize - stride - 3 + stride - 1) / stride | |
1400 | * = 4 - (inputsize - 4) / stride; | |
1401 | */ | |
1402 | level = 4 - (inputsize - 4) / stride; | |
1403 | } else { | |
0ffe5b7b RH |
1404 | int startlevel = check_s2_mmu_setup(cpu, aarch64, tcr, param.ds, |
1405 | inputsize, stride); | |
1406 | if (startlevel == INT_MIN) { | |
1407 | level = 0; | |
27c1b81d | 1408 | goto do_translation_fault; |
3283222a RH |
1409 | } |
1410 | level = startlevel; | |
1411 | } | |
1412 | ||
1413 | indexmask_grainsize = MAKE_64BIT_MASK(0, stride + 3); | |
1414 | indexmask = MAKE_64BIT_MASK(0, inputsize - (stride * (4 - level))); | |
1415 | ||
1416 | /* Now we can extract the actual base address from the TTBR */ | |
1417 | descaddr = extract64(ttbr, 0, 48); | |
1418 | ||
1419 | /* | |
1420 | * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [5:2] of TTBR. | |
1421 | * | |
1422 | * Otherwise, if the base address is out of range, raise AddressSizeFault. | |
1423 | * In the pseudocode, this is !IsZero(baseregister<47:outputsize>), | |
1424 | * but we've just cleared the bits above 47, so simplify the test. | |
1425 | */ | |
1426 | if (outputsize > 48) { | |
1427 | descaddr |= extract64(ttbr, 2, 4) << 48; | |
1428 | } else if (descaddr >> outputsize) { | |
1429 | level = 0; | |
27c1b81d | 1430 | fi->type = ARMFault_AddressSize; |
3283222a RH |
1431 | goto do_fault; |
1432 | } | |
1433 | ||
1434 | /* | |
1435 | * We rely on this masking to clear the RES0 bits at the bottom of the TTBR | |
1436 | * and also to mask out CnP (bit 0) which could validly be non-zero. | |
1437 | */ | |
1438 | descaddr &= ~indexmask; | |
1439 | ||
1440 | /* | |
1441 | * For AArch32, the address field in the descriptor goes up to bit 39 | |
1442 | * for both v7 and v8. However, for v8 the SBZ bits [47:40] must be 0 | |
1443 | * or an AddressSize fault is raised. So for v8 we extract those SBZ | |
1444 | * bits as part of the address, which will be checked via outputsize. | |
1445 | * For AArch64, the address field goes up to bit 47, or 49 with FEAT_LPA2; | |
1446 | * the highest bits of a 52-bit output are placed elsewhere. | |
1447 | */ | |
1448 | if (param.ds) { | |
1449 | descaddrmask = MAKE_64BIT_MASK(0, 50); | |
1450 | } else if (arm_feature(env, ARM_FEATURE_V8)) { | |
1451 | descaddrmask = MAKE_64BIT_MASK(0, 48); | |
1452 | } else { | |
1453 | descaddrmask = MAKE_64BIT_MASK(0, 40); | |
1454 | } | |
1455 | descaddrmask &= ~indexmask_grainsize; | |
1456 | ||
1457 | /* | |
21a4ab83 | 1458 | * Secure stage 1 accesses start with the page table in secure memory and |
3283222a RH |
1459 | * can be downgraded to non-secure at any step. Non-secure accesses |
1460 | * remain non-secure. We implement this by just ORing in the NSTable/NS | |
1461 | * bits at each step. | |
21a4ab83 | 1462 | * Stage 2 never gets this kind of downgrade. |
3283222a | 1463 | */ |
c23f08a5 | 1464 | tableattrs = is_secure ? 0 : (1 << 4); |
3283222a | 1465 | |
fe4ddc15 RH |
1466 | next_level: |
1467 | descaddr |= (address >> (stride * (4 - level))) & indexmask; | |
1468 | descaddr &= ~7ULL; | |
21a4ab83 | 1469 | nstable = !regime_is_stage2(mmu_idx) && extract32(tableattrs, 4, 1); |
d38fa967 | 1470 | if (nstable && ptw->in_secure) { |
3283222a | 1471 | /* |
fe4ddc15 | 1472 | * Stage2_S -> Stage2 or Phys_S -> Phys_NS |
d38fa967 | 1473 | * Assert the relative order of the secure/non-secure indexes. |
3283222a | 1474 | */ |
d38fa967 RH |
1475 | QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_S + 1 != ARMMMUIdx_Phys_NS); |
1476 | QEMU_BUILD_BUG_ON(ARMMMUIdx_Stage2_S + 1 != ARMMMUIdx_Stage2); | |
1477 | ptw->in_ptw_idx += 1; | |
fe4ddc15 RH |
1478 | ptw->in_secure = false; |
1479 | } | |
1480 | if (!S1_ptw_translate(env, ptw, descaddr, fi)) { | |
1481 | goto do_fault; | |
1482 | } | |
1483 | descriptor = arm_ldq_ptw(env, ptw, fi); | |
1484 | if (fi->type != ARMFault_None) { | |
1485 | goto do_fault; | |
1486 | } | |
71943a1e | 1487 | new_descriptor = descriptor; |
3283222a | 1488 | |
71943a1e | 1489 | restart_atomic_update: |
fe4ddc15 RH |
1490 | if (!(descriptor & 1) || (!(descriptor & 2) && (level == 3))) { |
1491 | /* Invalid, or the Reserved level 3 encoding */ | |
27c1b81d | 1492 | goto do_translation_fault; |
fe4ddc15 RH |
1493 | } |
1494 | ||
1495 | descaddr = descriptor & descaddrmask; | |
1496 | ||
1497 | /* | |
1498 | * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [15:12] | |
1499 | * of descriptor. For FEAT_LPA2 and effective DS, bits [51:50] of | |
1500 | * descaddr are in [9:8]. Otherwise, if descaddr is out of range, | |
1501 | * raise AddressSizeFault. | |
1502 | */ | |
1503 | if (outputsize > 48) { | |
1504 | if (param.ds) { | |
1505 | descaddr |= extract64(descriptor, 8, 2) << 50; | |
1506 | } else { | |
1507 | descaddr |= extract64(descriptor, 12, 4) << 48; | |
3283222a | 1508 | } |
fe4ddc15 | 1509 | } else if (descaddr >> outputsize) { |
27c1b81d | 1510 | fi->type = ARMFault_AddressSize; |
fe4ddc15 RH |
1511 | goto do_fault; |
1512 | } | |
1513 | ||
1514 | if ((descriptor & 2) && (level < 3)) { | |
3283222a | 1515 | /* |
fe4ddc15 RH |
1516 | * Table entry. The top five bits are attributes which may |
1517 | * propagate down through lower levels of the table (and | |
1518 | * which are all arranged so that 0 means "no effect", so | |
1519 | * we can gather them up by ORing in the bits at each level). | |
3283222a | 1520 | */ |
fe4ddc15 RH |
1521 | tableattrs |= extract64(descriptor, 59, 5); |
1522 | level++; | |
1523 | indexmask = indexmask_grainsize; | |
1524 | goto next_level; | |
3283222a | 1525 | } |
fe4ddc15 RH |
1526 | |
1527 | /* | |
1528 | * Block entry at level 1 or 2, or page entry at level 3. | |
1529 | * These are basically the same thing, although the number | |
1530 | * of bits we pull in from the vaddr varies. Note that although | |
1531 | * descaddrmask masks enough of the low bits of the descriptor | |
1532 | * to give a correct page or table address, the address field | |
1533 | * in a block descriptor is smaller; so we need to explicitly | |
1534 | * clear the lower bits here before ORing in the low vaddr bits. | |
71943a1e RH |
1535 | * |
1536 | * Afterward, descaddr is the final physical address. | |
fe4ddc15 RH |
1537 | */ |
1538 | page_size = (1ULL << ((stride * (4 - level)) + 3)); | |
1539 | descaddr &= ~(hwaddr)(page_size - 1); | |
1540 | descaddr |= (address & (page_size - 1)); | |
fe4ddc15 | 1541 | |
71943a1e RH |
1542 | if (likely(!ptw->in_debug)) { |
1543 | /* | |
1544 | * Access flag. | |
1545 | * If HA is enabled, prepare to update the descriptor below. | |
1546 | * Otherwise, pass the access fault on to software. | |
1547 | */ | |
1548 | if (!(descriptor & (1 << 10))) { | |
1549 | if (param.ha) { | |
1550 | new_descriptor |= 1 << 10; /* AF */ | |
1551 | } else { | |
1552 | fi->type = ARMFault_AccessFlag; | |
1553 | goto do_fault; | |
1554 | } | |
1555 | } | |
65c123fd RH |
1556 | |
1557 | /* | |
1558 | * Dirty Bit. | |
1559 | * If HD is enabled, pre-emptively set/clear the appropriate AP/S2AP | |
1560 | * bit for writeback. The actual write protection test may still be | |
1561 | * overridden by tableattrs, to be merged below. | |
1562 | */ | |
1563 | if (param.hd | |
1564 | && extract64(descriptor, 51, 1) /* DBM */ | |
1565 | && access_type == MMU_DATA_STORE) { | |
1566 | if (regime_is_stage2(mmu_idx)) { | |
1567 | new_descriptor |= 1ull << 7; /* set S2AP[1] */ | |
1568 | } else { | |
1569 | new_descriptor &= ~(1ull << 7); /* clear AP[2] */ | |
1570 | } | |
1571 | } | |
71943a1e RH |
1572 | } |
1573 | ||
fe4ddc15 | 1574 | /* |
71943a1e RH |
1575 | * Extract attributes from the (modified) descriptor, and apply |
1576 | * table descriptors. Stage 2 table descriptors do not include | |
1577 | * any attribute fields. HPD disables all the table attributes | |
1578 | * except NSTable. | |
fe4ddc15 | 1579 | */ |
71943a1e | 1580 | attrs = new_descriptor & (MAKE_64BIT_MASK(2, 10) | MAKE_64BIT_MASK(50, 14)); |
34a57fae RH |
1581 | if (!regime_is_stage2(mmu_idx)) { |
1582 | attrs |= nstable << 5; /* NS */ | |
1583 | if (!param.hpd) { | |
1584 | attrs |= extract64(tableattrs, 0, 2) << 53; /* XN, PXN */ | |
1585 | /* | |
1586 | * The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1 | |
1587 | * means "force PL1 access only", which means forcing AP[1] to 0. | |
1588 | */ | |
1589 | attrs &= ~(extract64(tableattrs, 2, 1) << 6); /* !APT[0] => AP[1] */ | |
1590 | attrs |= extract32(tableattrs, 3, 1) << 7; /* APT[1] => AP[2] */ | |
1591 | } | |
1592 | } | |
fe4ddc15 | 1593 | |
45666091 | 1594 | ap = extract32(attrs, 6, 2); |
edc05dd4 | 1595 | if (regime_is_stage2(mmu_idx)) { |
3283222a | 1596 | ns = mmu_idx == ARMMMUIdx_Stage2; |
45666091 | 1597 | xn = extract64(attrs, 53, 2); |
7fa7ea8f | 1598 | result->f.prot = get_S2prot(env, ap, xn, s1_is_el0); |
3283222a | 1599 | } else { |
45666091 RH |
1600 | ns = extract32(attrs, 5, 1); |
1601 | xn = extract64(attrs, 54, 1); | |
1602 | pxn = extract64(attrs, 53, 1); | |
7fa7ea8f | 1603 | result->f.prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn); |
3283222a RH |
1604 | } |
1605 | ||
7fa7ea8f | 1606 | if (!(result->f.prot & (1 << access_type))) { |
27c1b81d | 1607 | fi->type = ARMFault_Permission; |
3283222a RH |
1608 | goto do_fault; |
1609 | } | |
1610 | ||
71943a1e RH |
1611 | /* If FEAT_HAFDBS has made changes, update the PTE. */ |
1612 | if (new_descriptor != descriptor) { | |
1613 | new_descriptor = arm_casq_ptw(env, descriptor, new_descriptor, ptw, fi); | |
1614 | if (fi->type != ARMFault_None) { | |
1615 | goto do_fault; | |
1616 | } | |
1617 | /* | |
1618 | * I_YZSVV says that if the in-memory descriptor has changed, | |
1619 | * then we must use the information in that new value | |
1620 | * (which might include a different output address, different | |
1621 | * attributes, or generate a fault). | |
1622 | * Restart the handling of the descriptor value from scratch. | |
1623 | */ | |
1624 | if (new_descriptor != descriptor) { | |
1625 | descriptor = new_descriptor; | |
1626 | goto restart_atomic_update; | |
1627 | } | |
1628 | } | |
1629 | ||
3283222a RH |
1630 | if (ns) { |
1631 | /* | |
1632 | * The NS bit will (as required by the architecture) have no effect if | |
1633 | * the CPU doesn't support TZ or this is a non-secure translation | |
1634 | * regime, because the attribute will already be non-secure. | |
1635 | */ | |
7fa7ea8f | 1636 | result->f.attrs.secure = false; |
90c66293 | 1637 | result->f.attrs.space = ARMSS_NonSecure; |
3283222a | 1638 | } |
937f2245 | 1639 | |
edc05dd4 | 1640 | if (regime_is_stage2(mmu_idx)) { |
03ee9bbe | 1641 | result->cacheattrs.is_s2_format = true; |
45666091 | 1642 | result->cacheattrs.attrs = extract32(attrs, 2, 4); |
3283222a RH |
1643 | } else { |
1644 | /* Index into MAIR registers for cache attributes */ | |
45666091 | 1645 | uint8_t attrindx = extract32(attrs, 2, 3); |
3283222a RH |
1646 | uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)]; |
1647 | assert(attrindx <= 7); | |
03ee9bbe RH |
1648 | result->cacheattrs.is_s2_format = false; |
1649 | result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8); | |
6a3b1e44 RH |
1650 | |
1651 | /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */ | |
1652 | if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { | |
1653 | result->f.guarded = extract64(attrs, 50, 1); /* GP */ | |
1654 | } | |
3283222a RH |
1655 | } |
1656 | ||
1657 | /* | |
1658 | * For FEAT_LPA2 and effective DS, the SH field in the attributes | |
1659 | * was re-purposed for output address bits. The SH attribute in | |
1660 | * that case comes from TCR_ELx, which we extracted earlier. | |
1661 | */ | |
1662 | if (param.ds) { | |
03ee9bbe | 1663 | result->cacheattrs.shareability = param.sh; |
3283222a | 1664 | } else { |
45666091 | 1665 | result->cacheattrs.shareability = extract32(attrs, 8, 2); |
3283222a RH |
1666 | } |
1667 | ||
7fa7ea8f RH |
1668 | result->f.phys_addr = descaddr; |
1669 | result->f.lg_page_size = ctz64(page_size); | |
3283222a RH |
1670 | return false; |
1671 | ||
27c1b81d RH |
1672 | do_translation_fault: |
1673 | fi->type = ARMFault_Translation; | |
1674 | do_fault: | |
3283222a RH |
1675 | fi->level = level; |
1676 | /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ | |
edc05dd4 | 1677 | fi->stage2 = fi->s1ptw || regime_is_stage2(mmu_idx); |
3283222a RH |
1678 | fi->s1ns = mmu_idx == ARMMMUIdx_Stage2; |
1679 | return true; | |
1680 | } | |
1681 | ||
9a12fb36 RH |
1682 | static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, |
1683 | MMUAccessType access_type, ARMMMUIdx mmu_idx, | |
a5b5092f | 1684 | bool is_secure, GetPhysAddrResult *result, |
9a12fb36 RH |
1685 | ARMMMUFaultInfo *fi) |
1686 | { | |
1687 | int n; | |
1688 | uint32_t mask; | |
1689 | uint32_t base; | |
1690 | bool is_user = regime_is_user(env, mmu_idx); | |
1691 | ||
7e80c0a4 | 1692 | if (regime_translation_disabled(env, mmu_idx, is_secure)) { |
9a12fb36 | 1693 | /* MPU disabled. */ |
7fa7ea8f RH |
1694 | result->f.phys_addr = address; |
1695 | result->f.prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
9a12fb36 RH |
1696 | return false; |
1697 | } | |
1698 | ||
7fa7ea8f | 1699 | result->f.phys_addr = address; |
9a12fb36 RH |
1700 | for (n = 7; n >= 0; n--) { |
1701 | base = env->cp15.c6_region[n]; | |
1702 | if ((base & 1) == 0) { | |
1703 | continue; | |
1704 | } | |
1705 | mask = 1 << ((base >> 1) & 0x1f); | |
1706 | /* Keep this shift separate from the above to avoid an | |
1707 | (undefined) << 32. */ | |
1708 | mask = (mask << 1) - 1; | |
1709 | if (((base ^ address) & ~mask) == 0) { | |
1710 | break; | |
1711 | } | |
1712 | } | |
1713 | if (n < 0) { | |
1714 | fi->type = ARMFault_Background; | |
1715 | return true; | |
1716 | } | |
1717 | ||
1718 | if (access_type == MMU_INST_FETCH) { | |
1719 | mask = env->cp15.pmsav5_insn_ap; | |
1720 | } else { | |
1721 | mask = env->cp15.pmsav5_data_ap; | |
1722 | } | |
1723 | mask = (mask >> (n * 4)) & 0xf; | |
1724 | switch (mask) { | |
1725 | case 0: | |
1726 | fi->type = ARMFault_Permission; | |
1727 | fi->level = 1; | |
1728 | return true; | |
1729 | case 1: | |
1730 | if (is_user) { | |
1731 | fi->type = ARMFault_Permission; | |
1732 | fi->level = 1; | |
1733 | return true; | |
1734 | } | |
7fa7ea8f | 1735 | result->f.prot = PAGE_READ | PAGE_WRITE; |
9a12fb36 RH |
1736 | break; |
1737 | case 2: | |
7fa7ea8f | 1738 | result->f.prot = PAGE_READ; |
9a12fb36 | 1739 | if (!is_user) { |
7fa7ea8f | 1740 | result->f.prot |= PAGE_WRITE; |
9a12fb36 RH |
1741 | } |
1742 | break; | |
1743 | case 3: | |
7fa7ea8f | 1744 | result->f.prot = PAGE_READ | PAGE_WRITE; |
9a12fb36 RH |
1745 | break; |
1746 | case 5: | |
1747 | if (is_user) { | |
1748 | fi->type = ARMFault_Permission; | |
1749 | fi->level = 1; | |
1750 | return true; | |
1751 | } | |
7fa7ea8f | 1752 | result->f.prot = PAGE_READ; |
9a12fb36 RH |
1753 | break; |
1754 | case 6: | |
7fa7ea8f | 1755 | result->f.prot = PAGE_READ; |
9a12fb36 RH |
1756 | break; |
1757 | default: | |
1758 | /* Bad permission. */ | |
1759 | fi->type = ARMFault_Permission; | |
1760 | fi->level = 1; | |
1761 | return true; | |
1762 | } | |
7fa7ea8f | 1763 | result->f.prot |= PAGE_EXEC; |
9a12fb36 RH |
1764 | return false; |
1765 | } | |
1766 | ||
fedbaa05 | 1767 | static void get_phys_addr_pmsav7_default(CPUARMState *env, ARMMMUIdx mmu_idx, |
7fa7ea8f | 1768 | int32_t address, uint8_t *prot) |
7d2e08c9 RH |
1769 | { |
1770 | if (!arm_feature(env, ARM_FEATURE_M)) { | |
1771 | *prot = PAGE_READ | PAGE_WRITE; | |
1772 | switch (address) { | |
1773 | case 0xF0000000 ... 0xFFFFFFFF: | |
1774 | if (regime_sctlr(env, mmu_idx) & SCTLR_V) { | |
1775 | /* hivecs execing is ok */ | |
1776 | *prot |= PAGE_EXEC; | |
1777 | } | |
1778 | break; | |
1779 | case 0x00000000 ... 0x7FFFFFFF: | |
1780 | *prot |= PAGE_EXEC; | |
1781 | break; | |
1782 | } | |
1783 | } else { | |
1784 | /* Default system address map for M profile cores. | |
1785 | * The architecture specifies which regions are execute-never; | |
1786 | * at the MPU level no other checks are defined. | |
1787 | */ | |
1788 | switch (address) { | |
1789 | case 0x00000000 ... 0x1fffffff: /* ROM */ | |
1790 | case 0x20000000 ... 0x3fffffff: /* SRAM */ | |
1791 | case 0x60000000 ... 0x7fffffff: /* RAM */ | |
1792 | case 0x80000000 ... 0x9fffffff: /* RAM */ | |
1793 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
1794 | break; | |
1795 | case 0x40000000 ... 0x5fffffff: /* Peripheral */ | |
1796 | case 0xa0000000 ... 0xbfffffff: /* Device */ | |
1797 | case 0xc0000000 ... 0xdfffffff: /* Device */ | |
1798 | case 0xe0000000 ... 0xffffffff: /* System */ | |
1799 | *prot = PAGE_READ | PAGE_WRITE; | |
1800 | break; | |
1801 | default: | |
1802 | g_assert_not_reached(); | |
1803 | } | |
1804 | } | |
1805 | } | |
1806 | ||
47ff5ba9 RH |
1807 | static bool m_is_ppb_region(CPUARMState *env, uint32_t address) |
1808 | { | |
1809 | /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */ | |
1810 | return arm_feature(env, ARM_FEATURE_M) && | |
1811 | extract32(address, 20, 12) == 0xe00; | |
1812 | } | |
1813 | ||
1814 | static bool m_is_system_region(CPUARMState *env, uint32_t address) | |
1815 | { | |
1816 | /* | |
1817 | * True if address is in the M profile system region | |
1818 | * 0xe0000000 - 0xffffffff | |
1819 | */ | |
1820 | return arm_feature(env, ARM_FEATURE_M) && extract32(address, 29, 3) == 0x7; | |
1821 | } | |
1822 | ||
c8e436c9 | 1823 | static bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx, |
1a469cf7 | 1824 | bool is_secure, bool is_user) |
c8e436c9 RH |
1825 | { |
1826 | /* | |
1827 | * Return true if we should use the default memory map as a | |
1828 | * "background" region if there are no hits against any MPU regions. | |
1829 | */ | |
1830 | CPUARMState *env = &cpu->env; | |
1831 | ||
1832 | if (is_user) { | |
1833 | return false; | |
1834 | } | |
1835 | ||
1836 | if (arm_feature(env, ARM_FEATURE_M)) { | |
1a469cf7 | 1837 | return env->v7m.mpu_ctrl[is_secure] & R_V7M_MPU_CTRL_PRIVDEFENA_MASK; |
c8e436c9 | 1838 | } |
fca45e34 TR |
1839 | |
1840 | if (mmu_idx == ARMMMUIdx_Stage2) { | |
1841 | return false; | |
1842 | } | |
1843 | ||
1844 | return regime_sctlr(env, mmu_idx) & SCTLR_BR; | |
c8e436c9 RH |
1845 | } |
1846 | ||
1f2e87e5 RH |
1847 | static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, |
1848 | MMUAccessType access_type, ARMMMUIdx mmu_idx, | |
957a0bb7 | 1849 | bool secure, GetPhysAddrResult *result, |
1f2e87e5 RH |
1850 | ARMMMUFaultInfo *fi) |
1851 | { | |
1852 | ARMCPU *cpu = env_archcpu(env); | |
1853 | int n; | |
1854 | bool is_user = regime_is_user(env, mmu_idx); | |
1855 | ||
7fa7ea8f RH |
1856 | result->f.phys_addr = address; |
1857 | result->f.lg_page_size = TARGET_PAGE_BITS; | |
1858 | result->f.prot = 0; | |
1f2e87e5 | 1859 | |
7e80c0a4 | 1860 | if (regime_translation_disabled(env, mmu_idx, secure) || |
1f2e87e5 RH |
1861 | m_is_ppb_region(env, address)) { |
1862 | /* | |
1863 | * MPU disabled or M profile PPB access: use default memory map. | |
1864 | * The other case which uses the default memory map in the | |
1865 | * v7M ARM ARM pseudocode is exception vector reads from the vector | |
1866 | * table. In QEMU those accesses are done in arm_v7m_load_vector(), | |
1867 | * which always does a direct read using address_space_ldl(), rather | |
1868 | * than going via this function, so we don't need to check that here. | |
1869 | */ | |
7fa7ea8f | 1870 | get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->f.prot); |
1f2e87e5 RH |
1871 | } else { /* MPU enabled */ |
1872 | for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) { | |
1873 | /* region search */ | |
1874 | uint32_t base = env->pmsav7.drbar[n]; | |
1875 | uint32_t rsize = extract32(env->pmsav7.drsr[n], 1, 5); | |
1876 | uint32_t rmask; | |
1877 | bool srdis = false; | |
1878 | ||
1879 | if (!(env->pmsav7.drsr[n] & 0x1)) { | |
1880 | continue; | |
1881 | } | |
1882 | ||
1883 | if (!rsize) { | |
1884 | qemu_log_mask(LOG_GUEST_ERROR, | |
1885 | "DRSR[%d]: Rsize field cannot be 0\n", n); | |
1886 | continue; | |
1887 | } | |
1888 | rsize++; | |
1889 | rmask = (1ull << rsize) - 1; | |
1890 | ||
1891 | if (base & rmask) { | |
1892 | qemu_log_mask(LOG_GUEST_ERROR, | |
1893 | "DRBAR[%d]: 0x%" PRIx32 " misaligned " | |
1894 | "to DRSR region size, mask = 0x%" PRIx32 "\n", | |
1895 | n, base, rmask); | |
1896 | continue; | |
1897 | } | |
1898 | ||
1899 | if (address < base || address > base + rmask) { | |
1900 | /* | |
1901 | * Address not in this region. We must check whether the | |
1902 | * region covers addresses in the same page as our address. | |
1903 | * In that case we must not report a size that covers the | |
1904 | * whole page for a subsequent hit against a different MPU | |
1905 | * region or the background region, because it would result in | |
1906 | * incorrect TLB hits for subsequent accesses to addresses that | |
1907 | * are in this MPU region. | |
1908 | */ | |
1909 | if (ranges_overlap(base, rmask, | |
1910 | address & TARGET_PAGE_MASK, | |
1911 | TARGET_PAGE_SIZE)) { | |
7fa7ea8f | 1912 | result->f.lg_page_size = 0; |
1f2e87e5 RH |
1913 | } |
1914 | continue; | |
1915 | } | |
1916 | ||
1917 | /* Region matched */ | |
1918 | ||
1919 | if (rsize >= 8) { /* no subregions for regions < 256 bytes */ | |
1920 | int i, snd; | |
1921 | uint32_t srdis_mask; | |
1922 | ||
1923 | rsize -= 3; /* sub region size (power of 2) */ | |
1924 | snd = ((address - base) >> rsize) & 0x7; | |
1925 | srdis = extract32(env->pmsav7.drsr[n], snd + 8, 1); | |
1926 | ||
1927 | srdis_mask = srdis ? 0x3 : 0x0; | |
1928 | for (i = 2; i <= 8 && rsize < TARGET_PAGE_BITS; i *= 2) { | |
1929 | /* | |
1930 | * This will check in groups of 2, 4 and then 8, whether | |
1931 | * the subregion bits are consistent. rsize is incremented | |
1932 | * back up to give the region size, considering consistent | |
1933 | * adjacent subregions as one region. Stop testing if rsize | |
1934 | * is already big enough for an entire QEMU page. | |
1935 | */ | |
1936 | int snd_rounded = snd & ~(i - 1); | |
1937 | uint32_t srdis_multi = extract32(env->pmsav7.drsr[n], | |
1938 | snd_rounded + 8, i); | |
1939 | if (srdis_mask ^ srdis_multi) { | |
1940 | break; | |
1941 | } | |
1942 | srdis_mask = (srdis_mask << i) | srdis_mask; | |
1943 | rsize++; | |
1944 | } | |
1945 | } | |
1946 | if (srdis) { | |
1947 | continue; | |
1948 | } | |
1949 | if (rsize < TARGET_PAGE_BITS) { | |
7fa7ea8f | 1950 | result->f.lg_page_size = rsize; |
1f2e87e5 RH |
1951 | } |
1952 | break; | |
1953 | } | |
1954 | ||
1955 | if (n == -1) { /* no hits */ | |
1a469cf7 | 1956 | if (!pmsav7_use_background_region(cpu, mmu_idx, secure, is_user)) { |
1f2e87e5 RH |
1957 | /* background fault */ |
1958 | fi->type = ARMFault_Background; | |
1959 | return true; | |
1960 | } | |
7fa7ea8f RH |
1961 | get_phys_addr_pmsav7_default(env, mmu_idx, address, |
1962 | &result->f.prot); | |
1f2e87e5 RH |
1963 | } else { /* a MPU hit! */ |
1964 | uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3); | |
1965 | uint32_t xn = extract32(env->pmsav7.dracr[n], 12, 1); | |
1966 | ||
1967 | if (m_is_system_region(env, address)) { | |
1968 | /* System space is always execute never */ | |
1969 | xn = 1; | |
1970 | } | |
1971 | ||
1972 | if (is_user) { /* User mode AP bit decoding */ | |
1973 | switch (ap) { | |
1974 | case 0: | |
1975 | case 1: | |
1976 | case 5: | |
1977 | break; /* no access */ | |
1978 | case 3: | |
7fa7ea8f | 1979 | result->f.prot |= PAGE_WRITE; |
1f2e87e5 RH |
1980 | /* fall through */ |
1981 | case 2: | |
1982 | case 6: | |
7fa7ea8f | 1983 | result->f.prot |= PAGE_READ | PAGE_EXEC; |
1f2e87e5 RH |
1984 | break; |
1985 | case 7: | |
1986 | /* for v7M, same as 6; for R profile a reserved value */ | |
1987 | if (arm_feature(env, ARM_FEATURE_M)) { | |
7fa7ea8f | 1988 | result->f.prot |= PAGE_READ | PAGE_EXEC; |
1f2e87e5 RH |
1989 | break; |
1990 | } | |
1991 | /* fall through */ | |
1992 | default: | |
1993 | qemu_log_mask(LOG_GUEST_ERROR, | |
1994 | "DRACR[%d]: Bad value for AP bits: 0x%" | |
1995 | PRIx32 "\n", n, ap); | |
1996 | } | |
1997 | } else { /* Priv. mode AP bits decoding */ | |
1998 | switch (ap) { | |
1999 | case 0: | |
2000 | break; /* no access */ | |
2001 | case 1: | |
2002 | case 2: | |
2003 | case 3: | |
7fa7ea8f | 2004 | result->f.prot |= PAGE_WRITE; |
1f2e87e5 RH |
2005 | /* fall through */ |
2006 | case 5: | |
2007 | case 6: | |
7fa7ea8f | 2008 | result->f.prot |= PAGE_READ | PAGE_EXEC; |
1f2e87e5 RH |
2009 | break; |
2010 | case 7: | |
2011 | /* for v7M, same as 6; for R profile a reserved value */ | |
2012 | if (arm_feature(env, ARM_FEATURE_M)) { | |
7fa7ea8f | 2013 | result->f.prot |= PAGE_READ | PAGE_EXEC; |
1f2e87e5 RH |
2014 | break; |
2015 | } | |
2016 | /* fall through */ | |
2017 | default: | |
2018 | qemu_log_mask(LOG_GUEST_ERROR, | |
2019 | "DRACR[%d]: Bad value for AP bits: 0x%" | |
2020 | PRIx32 "\n", n, ap); | |
2021 | } | |
2022 | } | |
2023 | ||
2024 | /* execute never */ | |
2025 | if (xn) { | |
7fa7ea8f | 2026 | result->f.prot &= ~PAGE_EXEC; |
1f2e87e5 RH |
2027 | } |
2028 | } | |
2029 | } | |
2030 | ||
2031 | fi->type = ARMFault_Permission; | |
2032 | fi->level = 1; | |
7fa7ea8f | 2033 | return !(result->f.prot & (1 << access_type)); |
1f2e87e5 RH |
2034 | } |
2035 | ||
fca45e34 TR |
2036 | static uint32_t *regime_rbar(CPUARMState *env, ARMMMUIdx mmu_idx, |
2037 | uint32_t secure) | |
2038 | { | |
2039 | if (regime_el(env, mmu_idx) == 2) { | |
2040 | return env->pmsav8.hprbar; | |
2041 | } else { | |
2042 | return env->pmsav8.rbar[secure]; | |
2043 | } | |
2044 | } | |
2045 | ||
2046 | static uint32_t *regime_rlar(CPUARMState *env, ARMMMUIdx mmu_idx, | |
2047 | uint32_t secure) | |
2048 | { | |
2049 | if (regime_el(env, mmu_idx) == 2) { | |
2050 | return env->pmsav8.hprlar; | |
2051 | } else { | |
2052 | return env->pmsav8.rlar[secure]; | |
2053 | } | |
2054 | } | |
2055 | ||
fedbaa05 RH |
2056 | bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, |
2057 | MMUAccessType access_type, ARMMMUIdx mmu_idx, | |
e9fb7090 RH |
2058 | bool secure, GetPhysAddrResult *result, |
2059 | ARMMMUFaultInfo *fi, uint32_t *mregion) | |
fedbaa05 RH |
2060 | { |
2061 | /* | |
2062 | * Perform a PMSAv8 MPU lookup (without also doing the SAU check | |
2063 | * that a full phys-to-virt translation does). | |
2064 | * mregion is (if not NULL) set to the region number which matched, | |
2065 | * or -1 if no region number is returned (MPU off, address did not | |
2066 | * hit a region, address hit in multiple regions). | |
652c750e RH |
2067 | * If the region hit doesn't cover the entire TARGET_PAGE the address |
2068 | * is within, then we set the result page_size to 1 to force the | |
2069 | * memory system to use a subpage. | |
fedbaa05 RH |
2070 | */ |
2071 | ARMCPU *cpu = env_archcpu(env); | |
2072 | bool is_user = regime_is_user(env, mmu_idx); | |
fedbaa05 RH |
2073 | int n; |
2074 | int matchregion = -1; | |
2075 | bool hit = false; | |
2076 | uint32_t addr_page_base = address & TARGET_PAGE_MASK; | |
2077 | uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1); | |
fca45e34 TR |
2078 | int region_counter; |
2079 | ||
2080 | if (regime_el(env, mmu_idx) == 2) { | |
2081 | region_counter = cpu->pmsav8r_hdregion; | |
2082 | } else { | |
2083 | region_counter = cpu->pmsav7_dregion; | |
2084 | } | |
fedbaa05 | 2085 | |
7fa7ea8f RH |
2086 | result->f.lg_page_size = TARGET_PAGE_BITS; |
2087 | result->f.phys_addr = address; | |
2088 | result->f.prot = 0; | |
fedbaa05 RH |
2089 | if (mregion) { |
2090 | *mregion = -1; | |
2091 | } | |
2092 | ||
fca45e34 TR |
2093 | if (mmu_idx == ARMMMUIdx_Stage2) { |
2094 | fi->stage2 = true; | |
2095 | } | |
2096 | ||
fedbaa05 RH |
2097 | /* |
2098 | * Unlike the ARM ARM pseudocode, we don't need to check whether this | |
2099 | * was an exception vector read from the vector table (which is always | |
2100 | * done using the default system address map), because those accesses | |
2101 | * are done in arm_v7m_load_vector(), which always does a direct | |
2102 | * read using address_space_ldl(), rather than going via this function. | |
2103 | */ | |
7e80c0a4 | 2104 | if (regime_translation_disabled(env, mmu_idx, secure)) { /* MPU disabled */ |
fedbaa05 RH |
2105 | hit = true; |
2106 | } else if (m_is_ppb_region(env, address)) { | |
2107 | hit = true; | |
2108 | } else { | |
1a469cf7 | 2109 | if (pmsav7_use_background_region(cpu, mmu_idx, secure, is_user)) { |
fedbaa05 RH |
2110 | hit = true; |
2111 | } | |
2112 | ||
fca45e34 TR |
2113 | uint32_t bitmask; |
2114 | if (arm_feature(env, ARM_FEATURE_M)) { | |
2115 | bitmask = 0x1f; | |
2116 | } else { | |
2117 | bitmask = 0x3f; | |
2118 | fi->level = 0; | |
2119 | } | |
2120 | ||
2121 | for (n = region_counter - 1; n >= 0; n--) { | |
fedbaa05 RH |
2122 | /* region search */ |
2123 | /* | |
fca45e34 TR |
2124 | * Note that the base address is bits [31:x] from the register |
2125 | * with bits [x-1:0] all zeroes, but the limit address is bits | |
2126 | * [31:x] from the register with bits [x:0] all ones. Where x is | |
2127 | * 5 for Cortex-M and 6 for Cortex-R | |
fedbaa05 | 2128 | */ |
fca45e34 TR |
2129 | uint32_t base = regime_rbar(env, mmu_idx, secure)[n] & ~bitmask; |
2130 | uint32_t limit = regime_rlar(env, mmu_idx, secure)[n] | bitmask; | |
fedbaa05 | 2131 | |
fca45e34 | 2132 | if (!(regime_rlar(env, mmu_idx, secure)[n] & 0x1)) { |
fedbaa05 RH |
2133 | /* Region disabled */ |
2134 | continue; | |
2135 | } | |
2136 | ||
2137 | if (address < base || address > limit) { | |
2138 | /* | |
2139 | * Address not in this region. We must check whether the | |
2140 | * region covers addresses in the same page as our address. | |
2141 | * In that case we must not report a size that covers the | |
2142 | * whole page for a subsequent hit against a different MPU | |
2143 | * region or the background region, because it would result in | |
2144 | * incorrect TLB hits for subsequent accesses to addresses that | |
2145 | * are in this MPU region. | |
2146 | */ | |
2147 | if (limit >= base && | |
2148 | ranges_overlap(base, limit - base + 1, | |
2149 | addr_page_base, | |
2150 | TARGET_PAGE_SIZE)) { | |
7fa7ea8f | 2151 | result->f.lg_page_size = 0; |
fedbaa05 RH |
2152 | } |
2153 | continue; | |
2154 | } | |
2155 | ||
2156 | if (base > addr_page_base || limit < addr_page_limit) { | |
7fa7ea8f | 2157 | result->f.lg_page_size = 0; |
fedbaa05 RH |
2158 | } |
2159 | ||
2160 | if (matchregion != -1) { | |
2161 | /* | |
2162 | * Multiple regions match -- always a failure (unlike | |
2163 | * PMSAv7 where highest-numbered-region wins) | |
2164 | */ | |
2165 | fi->type = ARMFault_Permission; | |
fca45e34 TR |
2166 | if (arm_feature(env, ARM_FEATURE_M)) { |
2167 | fi->level = 1; | |
2168 | } | |
fedbaa05 RH |
2169 | return true; |
2170 | } | |
2171 | ||
2172 | matchregion = n; | |
2173 | hit = true; | |
2174 | } | |
2175 | } | |
2176 | ||
2177 | if (!hit) { | |
fca45e34 TR |
2178 | if (arm_feature(env, ARM_FEATURE_M)) { |
2179 | fi->type = ARMFault_Background; | |
2180 | } else { | |
2181 | fi->type = ARMFault_Permission; | |
2182 | } | |
fedbaa05 RH |
2183 | return true; |
2184 | } | |
2185 | ||
2186 | if (matchregion == -1) { | |
2187 | /* hit using the background region */ | |
7fa7ea8f | 2188 | get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->f.prot); |
fedbaa05 | 2189 | } else { |
fca45e34 TR |
2190 | uint32_t matched_rbar = regime_rbar(env, mmu_idx, secure)[matchregion]; |
2191 | uint32_t matched_rlar = regime_rlar(env, mmu_idx, secure)[matchregion]; | |
2192 | uint32_t ap = extract32(matched_rbar, 1, 2); | |
2193 | uint32_t xn = extract32(matched_rbar, 0, 1); | |
fedbaa05 RH |
2194 | bool pxn = false; |
2195 | ||
2196 | if (arm_feature(env, ARM_FEATURE_V8_1M)) { | |
fca45e34 | 2197 | pxn = extract32(matched_rlar, 4, 1); |
fedbaa05 RH |
2198 | } |
2199 | ||
2200 | if (m_is_system_region(env, address)) { | |
2201 | /* System space is always execute never */ | |
2202 | xn = 1; | |
2203 | } | |
2204 | ||
fca45e34 TR |
2205 | if (regime_el(env, mmu_idx) == 2) { |
2206 | result->f.prot = simple_ap_to_rw_prot_is_user(ap, | |
2207 | mmu_idx != ARMMMUIdx_E2); | |
2208 | } else { | |
2209 | result->f.prot = simple_ap_to_rw_prot(env, mmu_idx, ap); | |
2210 | } | |
2211 | ||
2212 | if (!arm_feature(env, ARM_FEATURE_M)) { | |
2213 | uint8_t attrindx = extract32(matched_rlar, 1, 3); | |
2214 | uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)]; | |
2215 | uint8_t sh = extract32(matched_rlar, 3, 2); | |
2216 | ||
2217 | if (regime_sctlr(env, mmu_idx) & SCTLR_WXN && | |
2218 | result->f.prot & PAGE_WRITE && mmu_idx != ARMMMUIdx_Stage2) { | |
2219 | xn = 0x1; | |
2220 | } | |
2221 | ||
2222 | if ((regime_el(env, mmu_idx) == 1) && | |
2223 | regime_sctlr(env, mmu_idx) & SCTLR_UWXN && ap == 0x1) { | |
2224 | pxn = 0x1; | |
2225 | } | |
2226 | ||
2227 | result->cacheattrs.is_s2_format = false; | |
2228 | result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8); | |
2229 | result->cacheattrs.shareability = sh; | |
2230 | } | |
2231 | ||
7fa7ea8f RH |
2232 | if (result->f.prot && !xn && !(pxn && !is_user)) { |
2233 | result->f.prot |= PAGE_EXEC; | |
fedbaa05 | 2234 | } |
fca45e34 | 2235 | |
fedbaa05 RH |
2236 | if (mregion) { |
2237 | *mregion = matchregion; | |
2238 | } | |
2239 | } | |
2240 | ||
2241 | fi->type = ARMFault_Permission; | |
fca45e34 TR |
2242 | if (arm_feature(env, ARM_FEATURE_M)) { |
2243 | fi->level = 1; | |
2244 | } | |
7fa7ea8f | 2245 | return !(result->f.prot & (1 << access_type)); |
fedbaa05 RH |
2246 | } |
2247 | ||
2c1f429d RH |
2248 | static bool v8m_is_sau_exempt(CPUARMState *env, |
2249 | uint32_t address, MMUAccessType access_type) | |
2250 | { | |
2251 | /* | |
2252 | * The architecture specifies that certain address ranges are | |
2253 | * exempt from v8M SAU/IDAU checks. | |
2254 | */ | |
2255 | return | |
2256 | (access_type == MMU_INST_FETCH && m_is_system_region(env, address)) || | |
2257 | (address >= 0xe0000000 && address <= 0xe0002fff) || | |
2258 | (address >= 0xe000e000 && address <= 0xe000efff) || | |
2259 | (address >= 0xe002e000 && address <= 0xe002efff) || | |
2260 | (address >= 0xe0040000 && address <= 0xe0041fff) || | |
2261 | (address >= 0xe00ff000 && address <= 0xe00fffff); | |
2262 | } | |
2263 | ||
2264 | void v8m_security_lookup(CPUARMState *env, uint32_t address, | |
dbf2a71a RH |
2265 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
2266 | bool is_secure, V8M_SAttributes *sattrs) | |
2c1f429d RH |
2267 | { |
2268 | /* | |
2269 | * Look up the security attributes for this address. Compare the | |
2270 | * pseudocode SecurityCheck() function. | |
2271 | * We assume the caller has zero-initialized *sattrs. | |
2272 | */ | |
2273 | ARMCPU *cpu = env_archcpu(env); | |
2274 | int r; | |
2275 | bool idau_exempt = false, idau_ns = true, idau_nsc = true; | |
2276 | int idau_region = IREGION_NOTVALID; | |
2277 | uint32_t addr_page_base = address & TARGET_PAGE_MASK; | |
2278 | uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1); | |
2279 | ||
2280 | if (cpu->idau) { | |
2281 | IDAUInterfaceClass *iic = IDAU_INTERFACE_GET_CLASS(cpu->idau); | |
2282 | IDAUInterface *ii = IDAU_INTERFACE(cpu->idau); | |
2283 | ||
2284 | iic->check(ii, address, &idau_region, &idau_exempt, &idau_ns, | |
2285 | &idau_nsc); | |
2286 | } | |
2287 | ||
2288 | if (access_type == MMU_INST_FETCH && extract32(address, 28, 4) == 0xf) { | |
2289 | /* 0xf0000000..0xffffffff is always S for insn fetches */ | |
2290 | return; | |
2291 | } | |
2292 | ||
2293 | if (idau_exempt || v8m_is_sau_exempt(env, address, access_type)) { | |
dbf2a71a | 2294 | sattrs->ns = !is_secure; |
2c1f429d RH |
2295 | return; |
2296 | } | |
2297 | ||
2298 | if (idau_region != IREGION_NOTVALID) { | |
2299 | sattrs->irvalid = true; | |
2300 | sattrs->iregion = idau_region; | |
2301 | } | |
2302 | ||
2303 | switch (env->sau.ctrl & 3) { | |
2304 | case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */ | |
2305 | break; | |
2306 | case 2: /* SAU.ENABLE == 0, SAU.ALLNS == 1 */ | |
2307 | sattrs->ns = true; | |
2308 | break; | |
2309 | default: /* SAU.ENABLE == 1 */ | |
2310 | for (r = 0; r < cpu->sau_sregion; r++) { | |
2311 | if (env->sau.rlar[r] & 1) { | |
2312 | uint32_t base = env->sau.rbar[r] & ~0x1f; | |
2313 | uint32_t limit = env->sau.rlar[r] | 0x1f; | |
2314 | ||
2315 | if (base <= address && limit >= address) { | |
2316 | if (base > addr_page_base || limit < addr_page_limit) { | |
2317 | sattrs->subpage = true; | |
2318 | } | |
2319 | if (sattrs->srvalid) { | |
2320 | /* | |
2321 | * If we hit in more than one region then we must report | |
2322 | * as Secure, not NS-Callable, with no valid region | |
2323 | * number info. | |
2324 | */ | |
2325 | sattrs->ns = false; | |
2326 | sattrs->nsc = false; | |
2327 | sattrs->sregion = 0; | |
2328 | sattrs->srvalid = false; | |
2329 | break; | |
2330 | } else { | |
2331 | if (env->sau.rlar[r] & 2) { | |
2332 | sattrs->nsc = true; | |
2333 | } else { | |
2334 | sattrs->ns = true; | |
2335 | } | |
2336 | sattrs->srvalid = true; | |
2337 | sattrs->sregion = r; | |
2338 | } | |
2339 | } else { | |
2340 | /* | |
2341 | * Address not in this region. We must check whether the | |
2342 | * region covers addresses in the same page as our address. | |
2343 | * In that case we must not report a size that covers the | |
2344 | * whole page for a subsequent hit against a different MPU | |
2345 | * region or the background region, because it would result | |
2346 | * in incorrect TLB hits for subsequent accesses to | |
2347 | * addresses that are in this MPU region. | |
2348 | */ | |
2349 | if (limit >= base && | |
2350 | ranges_overlap(base, limit - base + 1, | |
2351 | addr_page_base, | |
2352 | TARGET_PAGE_SIZE)) { | |
2353 | sattrs->subpage = true; | |
2354 | } | |
2355 | } | |
2356 | } | |
2357 | } | |
2358 | break; | |
2359 | } | |
2360 | ||
2361 | /* | |
2362 | * The IDAU will override the SAU lookup results if it specifies | |
2363 | * higher security than the SAU does. | |
2364 | */ | |
2365 | if (!idau_ns) { | |
2366 | if (sattrs->ns || (!idau_nsc && sattrs->nsc)) { | |
2367 | sattrs->ns = false; | |
2368 | sattrs->nsc = idau_nsc; | |
2369 | } | |
2370 | } | |
2371 | } | |
2372 | ||
730d5c31 RH |
2373 | static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, |
2374 | MMUAccessType access_type, ARMMMUIdx mmu_idx, | |
be0ca948 | 2375 | bool secure, GetPhysAddrResult *result, |
730d5c31 RH |
2376 | ARMMMUFaultInfo *fi) |
2377 | { | |
730d5c31 RH |
2378 | V8M_SAttributes sattrs = {}; |
2379 | bool ret; | |
730d5c31 RH |
2380 | |
2381 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | |
dbf2a71a RH |
2382 | v8m_security_lookup(env, address, access_type, mmu_idx, |
2383 | secure, &sattrs); | |
730d5c31 RH |
2384 | if (access_type == MMU_INST_FETCH) { |
2385 | /* | |
2386 | * Instruction fetches always use the MMU bank and the | |
2387 | * transaction attribute determined by the fetch address, | |
2388 | * regardless of CPU state. This is painful for QEMU | |
2389 | * to handle, because it would mean we need to encode | |
2390 | * into the mmu_idx not just the (user, negpri) information | |
2391 | * for the current security state but also that for the | |
2392 | * other security state, which would balloon the number | |
2393 | * of mmu_idx values needed alarmingly. | |
2394 | * Fortunately we can avoid this because it's not actually | |
2395 | * possible to arbitrarily execute code from memory with | |
2396 | * the wrong security attribute: it will always generate | |
2397 | * an exception of some kind or another, apart from the | |
2398 | * special case of an NS CPU executing an SG instruction | |
2399 | * in S&NSC memory. So we always just fail the translation | |
2400 | * here and sort things out in the exception handler | |
2401 | * (including possibly emulating an SG instruction). | |
2402 | */ | |
2403 | if (sattrs.ns != !secure) { | |
2404 | if (sattrs.nsc) { | |
2405 | fi->type = ARMFault_QEMU_NSCExec; | |
2406 | } else { | |
2407 | fi->type = ARMFault_QEMU_SFault; | |
2408 | } | |
7fa7ea8f RH |
2409 | result->f.lg_page_size = sattrs.subpage ? 0 : TARGET_PAGE_BITS; |
2410 | result->f.phys_addr = address; | |
2411 | result->f.prot = 0; | |
730d5c31 RH |
2412 | return true; |
2413 | } | |
2414 | } else { | |
2415 | /* | |
2416 | * For data accesses we always use the MMU bank indicated | |
2417 | * by the current CPU state, but the security attributes | |
2418 | * might downgrade a secure access to nonsecure. | |
2419 | */ | |
2420 | if (sattrs.ns) { | |
7fa7ea8f | 2421 | result->f.attrs.secure = false; |
90c66293 | 2422 | result->f.attrs.space = ARMSS_NonSecure; |
730d5c31 RH |
2423 | } else if (!secure) { |
2424 | /* | |
2425 | * NS access to S memory must fault. | |
2426 | * Architecturally we should first check whether the | |
2427 | * MPU information for this address indicates that we | |
2428 | * are doing an unaligned access to Device memory, which | |
2429 | * should generate a UsageFault instead. QEMU does not | |
2430 | * currently check for that kind of unaligned access though. | |
2431 | * If we added it we would need to do so as a special case | |
2432 | * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt(). | |
2433 | */ | |
2434 | fi->type = ARMFault_QEMU_SFault; | |
7fa7ea8f RH |
2435 | result->f.lg_page_size = sattrs.subpage ? 0 : TARGET_PAGE_BITS; |
2436 | result->f.phys_addr = address; | |
2437 | result->f.prot = 0; | |
730d5c31 RH |
2438 | return true; |
2439 | } | |
2440 | } | |
2441 | } | |
2442 | ||
e9fb7090 | 2443 | ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx, secure, |
652c750e RH |
2444 | result, fi, NULL); |
2445 | if (sattrs.subpage) { | |
7fa7ea8f | 2446 | result->f.lg_page_size = 0; |
652c750e | 2447 | } |
730d5c31 RH |
2448 | return ret; |
2449 | } | |
2450 | ||
966f4bb7 RH |
2451 | /* |
2452 | * Translate from the 4-bit stage 2 representation of | |
2453 | * memory attributes (without cache-allocation hints) to | |
2454 | * the 8-bit representation of the stage 1 MAIR registers | |
2455 | * (which includes allocation hints). | |
2456 | * | |
2457 | * ref: shared/translation/attrs/S2AttrDecode() | |
2458 | * .../S2ConvertAttrsHints() | |
2459 | */ | |
ac76c2e5 | 2460 | static uint8_t convert_stage2_attrs(uint64_t hcr, uint8_t s2attrs) |
966f4bb7 RH |
2461 | { |
2462 | uint8_t hiattr = extract32(s2attrs, 2, 2); | |
2463 | uint8_t loattr = extract32(s2attrs, 0, 2); | |
2464 | uint8_t hihint = 0, lohint = 0; | |
2465 | ||
2466 | if (hiattr != 0) { /* normal memory */ | |
ac76c2e5 | 2467 | if (hcr & HCR_CD) { /* cache disabled */ |
966f4bb7 RH |
2468 | hiattr = loattr = 1; /* non-cacheable */ |
2469 | } else { | |
2470 | if (hiattr != 1) { /* Write-through or write-back */ | |
2471 | hihint = 3; /* RW allocate */ | |
2472 | } | |
2473 | if (loattr != 1) { /* Write-through or write-back */ | |
2474 | lohint = 3; /* RW allocate */ | |
2475 | } | |
2476 | } | |
2477 | } | |
2478 | ||
2479 | return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint; | |
2480 | } | |
2481 | ||
2482 | /* | |
2483 | * Combine either inner or outer cacheability attributes for normal | |
2484 | * memory, according to table D4-42 and pseudocode procedure | |
2485 | * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM). | |
2486 | * | |
2487 | * NB: only stage 1 includes allocation hints (RW bits), leading to | |
2488 | * some asymmetry. | |
2489 | */ | |
2490 | static uint8_t combine_cacheattr_nibble(uint8_t s1, uint8_t s2) | |
2491 | { | |
2492 | if (s1 == 4 || s2 == 4) { | |
2493 | /* non-cacheable has precedence */ | |
2494 | return 4; | |
2495 | } else if (extract32(s1, 2, 2) == 0 || extract32(s1, 2, 2) == 2) { | |
2496 | /* stage 1 write-through takes precedence */ | |
2497 | return s1; | |
2498 | } else if (extract32(s2, 2, 2) == 2) { | |
2499 | /* stage 2 write-through takes precedence, but the allocation hint | |
2500 | * is still taken from stage 1 | |
2501 | */ | |
2502 | return (2 << 2) | extract32(s1, 0, 2); | |
2503 | } else { /* write-back */ | |
2504 | return s1; | |
2505 | } | |
2506 | } | |
2507 | ||
2508 | /* | |
2509 | * Combine the memory type and cacheability attributes of | |
2510 | * s1 and s2 for the HCR_EL2.FWB == 0 case, returning the | |
2511 | * combined attributes in MAIR_EL1 format. | |
2512 | */ | |
ac76c2e5 | 2513 | static uint8_t combined_attrs_nofwb(uint64_t hcr, |
966f4bb7 RH |
2514 | ARMCacheAttrs s1, ARMCacheAttrs s2) |
2515 | { | |
2516 | uint8_t s1lo, s2lo, s1hi, s2hi, s2_mair_attrs, ret_attrs; | |
2517 | ||
faa1451e TR |
2518 | if (s2.is_s2_format) { |
2519 | s2_mair_attrs = convert_stage2_attrs(hcr, s2.attrs); | |
2520 | } else { | |
2521 | s2_mair_attrs = s2.attrs; | |
2522 | } | |
966f4bb7 RH |
2523 | |
2524 | s1lo = extract32(s1.attrs, 0, 4); | |
2525 | s2lo = extract32(s2_mair_attrs, 0, 4); | |
2526 | s1hi = extract32(s1.attrs, 4, 4); | |
2527 | s2hi = extract32(s2_mair_attrs, 4, 4); | |
2528 | ||
2529 | /* Combine memory type and cacheability attributes */ | |
2530 | if (s1hi == 0 || s2hi == 0) { | |
2531 | /* Device has precedence over normal */ | |
2532 | if (s1lo == 0 || s2lo == 0) { | |
2533 | /* nGnRnE has precedence over anything */ | |
2534 | ret_attrs = 0; | |
2535 | } else if (s1lo == 4 || s2lo == 4) { | |
2536 | /* non-Reordering has precedence over Reordering */ | |
2537 | ret_attrs = 4; /* nGnRE */ | |
2538 | } else if (s1lo == 8 || s2lo == 8) { | |
2539 | /* non-Gathering has precedence over Gathering */ | |
2540 | ret_attrs = 8; /* nGRE */ | |
2541 | } else { | |
2542 | ret_attrs = 0xc; /* GRE */ | |
2543 | } | |
2544 | } else { /* Normal memory */ | |
2545 | /* Outer/inner cacheability combine independently */ | |
2546 | ret_attrs = combine_cacheattr_nibble(s1hi, s2hi) << 4 | |
2547 | | combine_cacheattr_nibble(s1lo, s2lo); | |
2548 | } | |
2549 | return ret_attrs; | |
2550 | } | |
2551 | ||
2552 | static uint8_t force_cacheattr_nibble_wb(uint8_t attr) | |
2553 | { | |
2554 | /* | |
2555 | * Given the 4 bits specifying the outer or inner cacheability | |
2556 | * in MAIR format, return a value specifying Normal Write-Back, | |
2557 | * with the allocation and transient hints taken from the input | |
2558 | * if the input specified some kind of cacheable attribute. | |
2559 | */ | |
2560 | if (attr == 0 || attr == 4) { | |
2561 | /* | |
2562 | * 0 == an UNPREDICTABLE encoding | |
2563 | * 4 == Non-cacheable | |
2564 | * Either way, force Write-Back RW allocate non-transient | |
2565 | */ | |
2566 | return 0xf; | |
2567 | } | |
2568 | /* Change WriteThrough to WriteBack, keep allocation and transient hints */ | |
2569 | return attr | 4; | |
2570 | } | |
2571 | ||
2572 | /* | |
2573 | * Combine the memory type and cacheability attributes of | |
2574 | * s1 and s2 for the HCR_EL2.FWB == 1 case, returning the | |
2575 | * combined attributes in MAIR_EL1 format. | |
2576 | */ | |
72cef09c | 2577 | static uint8_t combined_attrs_fwb(ARMCacheAttrs s1, ARMCacheAttrs s2) |
966f4bb7 | 2578 | { |
faa1451e TR |
2579 | assert(s2.is_s2_format && !s1.is_s2_format); |
2580 | ||
966f4bb7 RH |
2581 | switch (s2.attrs) { |
2582 | case 7: | |
2583 | /* Use stage 1 attributes */ | |
2584 | return s1.attrs; | |
2585 | case 6: | |
2586 | /* | |
2587 | * Force Normal Write-Back. Note that if S1 is Normal cacheable | |
2588 | * then we take the allocation hints from it; otherwise it is | |
2589 | * RW allocate, non-transient. | |
2590 | */ | |
2591 | if ((s1.attrs & 0xf0) == 0) { | |
2592 | /* S1 is Device */ | |
2593 | return 0xff; | |
2594 | } | |
2595 | /* Need to check the Inner and Outer nibbles separately */ | |
2596 | return force_cacheattr_nibble_wb(s1.attrs & 0xf) | | |
2597 | force_cacheattr_nibble_wb(s1.attrs >> 4) << 4; | |
2598 | case 5: | |
2599 | /* If S1 attrs are Device, use them; otherwise Normal Non-cacheable */ | |
2600 | if ((s1.attrs & 0xf0) == 0) { | |
2601 | return s1.attrs; | |
2602 | } | |
2603 | return 0x44; | |
2604 | case 0 ... 3: | |
2605 | /* Force Device, of subtype specified by S2 */ | |
2606 | return s2.attrs << 2; | |
2607 | default: | |
2608 | /* | |
2609 | * RESERVED values (including RES0 descriptor bit [5] being nonzero); | |
2610 | * arbitrarily force Device. | |
2611 | */ | |
2612 | return 0; | |
2613 | } | |
2614 | } | |
2615 | ||
2616 | /* | |
2617 | * Combine S1 and S2 cacheability/shareability attributes, per D4.5.4 | |
2618 | * and CombineS1S2Desc() | |
2619 | * | |
2620 | * @env: CPUARMState | |
2621 | * @s1: Attributes from stage 1 walk | |
2622 | * @s2: Attributes from stage 2 walk | |
2623 | */ | |
ac76c2e5 | 2624 | static ARMCacheAttrs combine_cacheattrs(uint64_t hcr, |
966f4bb7 RH |
2625 | ARMCacheAttrs s1, ARMCacheAttrs s2) |
2626 | { | |
2627 | ARMCacheAttrs ret; | |
2628 | bool tagged = false; | |
2629 | ||
faa1451e | 2630 | assert(!s1.is_s2_format); |
966f4bb7 | 2631 | ret.is_s2_format = false; |
8539dc00 | 2632 | ret.guarded = s1.guarded; |
966f4bb7 RH |
2633 | |
2634 | if (s1.attrs == 0xf0) { | |
2635 | tagged = true; | |
2636 | s1.attrs = 0xff; | |
2637 | } | |
2638 | ||
2639 | /* Combine shareability attributes (table D4-43) */ | |
2640 | if (s1.shareability == 2 || s2.shareability == 2) { | |
2641 | /* if either are outer-shareable, the result is outer-shareable */ | |
2642 | ret.shareability = 2; | |
2643 | } else if (s1.shareability == 3 || s2.shareability == 3) { | |
2644 | /* if either are inner-shareable, the result is inner-shareable */ | |
2645 | ret.shareability = 3; | |
2646 | } else { | |
2647 | /* both non-shareable */ | |
2648 | ret.shareability = 0; | |
2649 | } | |
2650 | ||
2651 | /* Combine memory type and cacheability attributes */ | |
ac76c2e5 | 2652 | if (hcr & HCR_FWB) { |
72cef09c | 2653 | ret.attrs = combined_attrs_fwb(s1, s2); |
966f4bb7 | 2654 | } else { |
ac76c2e5 | 2655 | ret.attrs = combined_attrs_nofwb(hcr, s1, s2); |
966f4bb7 RH |
2656 | } |
2657 | ||
2658 | /* | |
2659 | * Any location for which the resultant memory type is any | |
2660 | * type of Device memory is always treated as Outer Shareable. | |
2661 | * Any location for which the resultant memory type is Normal | |
2662 | * Inner Non-cacheable, Outer Non-cacheable is always treated | |
2663 | * as Outer Shareable. | |
2664 | * TODO: FEAT_XS adds another value (0x40) also meaning iNCoNC | |
2665 | */ | |
2666 | if ((ret.attrs & 0xf0) == 0 || ret.attrs == 0x44) { | |
2667 | ret.shareability = 2; | |
2668 | } | |
2669 | ||
2670 | /* TODO: CombineS1S2Desc does not consider transient, only WB, RWA. */ | |
2671 | if (tagged && ret.attrs == 0xff) { | |
2672 | ret.attrs = 0xf0; | |
2673 | } | |
2674 | ||
2675 | return ret; | |
2676 | } | |
2677 | ||
448e42fd RH |
2678 | /* |
2679 | * MMU disabled. S1 addresses within aa64 translation regimes are | |
2680 | * still checked for bounds -- see AArch64.S1DisabledOutput(). | |
2681 | */ | |
2682 | static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address, | |
2683 | MMUAccessType access_type, | |
2684 | ARMMMUIdx mmu_idx, bool is_secure, | |
2685 | GetPhysAddrResult *result, | |
2686 | ARMMMUFaultInfo *fi) | |
2687 | { | |
5b74f9b4 RH |
2688 | uint8_t memattr = 0x00; /* Device nGnRnE */ |
2689 | uint8_t shareability = 0; /* non-sharable */ | |
a1ce3084 | 2690 | int r_el; |
448e42fd | 2691 | |
a1ce3084 RH |
2692 | switch (mmu_idx) { |
2693 | case ARMMMUIdx_Stage2: | |
2694 | case ARMMMUIdx_Stage2_S: | |
a1ce3084 | 2695 | case ARMMMUIdx_Phys_S: |
bb5cc2c8 RH |
2696 | case ARMMMUIdx_Phys_NS: |
2697 | case ARMMMUIdx_Phys_Root: | |
2698 | case ARMMMUIdx_Phys_Realm: | |
a1ce3084 | 2699 | break; |
5b74f9b4 | 2700 | |
a1ce3084 RH |
2701 | default: |
2702 | r_el = regime_el(env, mmu_idx); | |
448e42fd RH |
2703 | if (arm_el_is_aa64(env, r_el)) { |
2704 | int pamax = arm_pamax(env_archcpu(env)); | |
2705 | uint64_t tcr = env->cp15.tcr_el[r_el]; | |
2706 | int addrtop, tbi; | |
2707 | ||
2708 | tbi = aa64_va_parameter_tbi(tcr, mmu_idx); | |
2709 | if (access_type == MMU_INST_FETCH) { | |
2710 | tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx); | |
2711 | } | |
2712 | tbi = (tbi >> extract64(address, 55, 1)) & 1; | |
2713 | addrtop = (tbi ? 55 : 63); | |
2714 | ||
2715 | if (extract64(address, pamax, addrtop - pamax + 1) != 0) { | |
2716 | fi->type = ARMFault_AddressSize; | |
2717 | fi->level = 0; | |
2718 | fi->stage2 = false; | |
2719 | return 1; | |
2720 | } | |
2721 | ||
2722 | /* | |
2723 | * When TBI is disabled, we've just validated that all of the | |
2724 | * bits above PAMax are zero, so logically we only need to | |
2725 | * clear the top byte for TBI. But it's clearer to follow | |
2726 | * the pseudocode set of addrdesc.paddress. | |
2727 | */ | |
2728 | address = extract64(address, 0, 52); | |
2729 | } | |
5b74f9b4 RH |
2730 | |
2731 | /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ | |
2732 | if (r_el == 1) { | |
2733 | uint64_t hcr = arm_hcr_el2_eff_secstate(env, is_secure); | |
2734 | if (hcr & HCR_DC) { | |
2735 | if (hcr & HCR_DCT) { | |
2736 | memattr = 0xf0; /* Tagged, Normal, WB, RWA */ | |
2737 | } else { | |
2738 | memattr = 0xff; /* Normal, WB, RWA */ | |
2739 | } | |
2740 | } | |
2741 | } | |
2742 | if (memattr == 0 && access_type == MMU_INST_FETCH) { | |
2743 | if (regime_sctlr(env, mmu_idx) & SCTLR_I) { | |
2744 | memattr = 0xee; /* Normal, WT, RA, NT */ | |
2745 | } else { | |
2746 | memattr = 0x44; /* Normal, NC, No */ | |
2747 | } | |
2748 | shareability = 2; /* outer sharable */ | |
2749 | } | |
2750 | result->cacheattrs.is_s2_format = false; | |
a1ce3084 | 2751 | break; |
448e42fd RH |
2752 | } |
2753 | ||
7fa7ea8f RH |
2754 | result->f.phys_addr = address; |
2755 | result->f.prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
2756 | result->f.lg_page_size = TARGET_PAGE_BITS; | |
5b74f9b4 | 2757 | result->cacheattrs.shareability = shareability; |
448e42fd | 2758 | result->cacheattrs.attrs = memattr; |
6b72c542 | 2759 | return false; |
448e42fd RH |
2760 | } |
2761 | ||
3f5a74c5 RH |
2762 | static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, |
2763 | target_ulong address, | |
2764 | MMUAccessType access_type, | |
2765 | GetPhysAddrResult *result, | |
2766 | ARMMMUFaultInfo *fi) | |
2767 | { | |
2768 | hwaddr ipa; | |
c8d6c286 | 2769 | int s1_prot, s1_lgpgsz; |
3f5a74c5 | 2770 | bool is_secure = ptw->in_secure; |
fcc0b041 | 2771 | bool ret, ipa_secure; |
3f5a74c5 | 2772 | ARMCacheAttrs cacheattrs1; |
90c66293 | 2773 | ARMSecuritySpace ipa_space; |
3f5a74c5 RH |
2774 | bool is_el0; |
2775 | uint64_t hcr; | |
2776 | ||
2777 | ret = get_phys_addr_with_struct(env, ptw, address, access_type, result, fi); | |
2778 | ||
26ba00cf PM |
2779 | /* If S1 fails, return early. */ |
2780 | if (ret) { | |
3f5a74c5 RH |
2781 | return ret; |
2782 | } | |
2783 | ||
2784 | ipa = result->f.phys_addr; | |
2785 | ipa_secure = result->f.attrs.secure; | |
90c66293 | 2786 | ipa_space = result->f.attrs.space; |
3f5a74c5 RH |
2787 | |
2788 | is_el0 = ptw->in_mmu_idx == ARMMMUIdx_Stage1_E0; | |
fcc0b041 PM |
2789 | ptw->in_mmu_idx = ipa_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; |
2790 | ptw->in_secure = ipa_secure; | |
90c66293 | 2791 | ptw->in_space = ipa_space; |
fcc0b041 | 2792 | ptw->in_ptw_idx = ptw_idx_for_stage_2(env, ptw->in_mmu_idx); |
3f5a74c5 RH |
2793 | |
2794 | /* | |
2795 | * S1 is done, now do S2 translation. | |
2796 | * Save the stage1 results so that we may merge prot and cacheattrs later. | |
2797 | */ | |
2798 | s1_prot = result->f.prot; | |
c8d6c286 | 2799 | s1_lgpgsz = result->f.lg_page_size; |
3f5a74c5 RH |
2800 | cacheattrs1 = result->cacheattrs; |
2801 | memset(result, 0, sizeof(*result)); | |
2802 | ||
fca45e34 TR |
2803 | if (arm_feature(env, ARM_FEATURE_PMSA)) { |
2804 | ret = get_phys_addr_pmsav8(env, ipa, access_type, | |
2805 | ptw->in_mmu_idx, is_secure, result, fi); | |
2806 | } else { | |
2807 | ret = get_phys_addr_lpae(env, ptw, ipa, access_type, | |
2808 | is_el0, result, fi); | |
2809 | } | |
3f5a74c5 RH |
2810 | fi->s2addr = ipa; |
2811 | ||
2812 | /* Combine the S1 and S2 perms. */ | |
2813 | result->f.prot &= s1_prot; | |
2814 | ||
2815 | /* If S2 fails, return early. */ | |
2816 | if (ret) { | |
2817 | return ret; | |
2818 | } | |
2819 | ||
c8d6c286 | 2820 | /* |
9e65f4e6 PM |
2821 | * If either S1 or S2 returned a result smaller than TARGET_PAGE_SIZE, |
2822 | * this means "don't put this in the TLB"; in this case, return a | |
2823 | * result with lg_page_size == 0 to achieve that. Otherwise, | |
2824 | * use the maximum of the S1 & S2 page size, so that invalidation | |
2825 | * of pages > TARGET_PAGE_SIZE works correctly. (This works even though | |
2826 | * we know the combined result permissions etc only cover the minimum | |
2827 | * of the S1 and S2 page size, because we know that the common TLB code | |
2828 | * never actually creates TLB entries bigger than TARGET_PAGE_SIZE, | |
2829 | * and passing a larger page size value only affects invalidations.) | |
c8d6c286 | 2830 | */ |
9e65f4e6 PM |
2831 | if (result->f.lg_page_size < TARGET_PAGE_BITS || |
2832 | s1_lgpgsz < TARGET_PAGE_BITS) { | |
2833 | result->f.lg_page_size = 0; | |
2834 | } else if (result->f.lg_page_size < s1_lgpgsz) { | |
c8d6c286 RH |
2835 | result->f.lg_page_size = s1_lgpgsz; |
2836 | } | |
2837 | ||
3f5a74c5 RH |
2838 | /* Combine the S1 and S2 cache attributes. */ |
2839 | hcr = arm_hcr_el2_eff_secstate(env, is_secure); | |
2840 | if (hcr & HCR_DC) { | |
2841 | /* | |
2842 | * HCR.DC forces the first stage attributes to | |
2843 | * Normal Non-Shareable, | |
2844 | * Inner Write-Back Read-Allocate Write-Allocate, | |
2845 | * Outer Write-Back Read-Allocate Write-Allocate. | |
2846 | * Do not overwrite Tagged within attrs. | |
2847 | */ | |
2848 | if (cacheattrs1.attrs != 0xf0) { | |
2849 | cacheattrs1.attrs = 0xff; | |
2850 | } | |
2851 | cacheattrs1.shareability = 0; | |
2852 | } | |
2853 | result->cacheattrs = combine_cacheattrs(hcr, cacheattrs1, | |
2854 | result->cacheattrs); | |
2855 | ||
2856 | /* | |
2857 | * Check if IPA translates to secure or non-secure PA space. | |
2858 | * Note that VSTCR overrides VTCR and {N}SW overrides {N}SA. | |
2859 | */ | |
2860 | result->f.attrs.secure = | |
2861 | (is_secure | |
2862 | && !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW)) | |
2863 | && (ipa_secure | |
2864 | || !(env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW)))); | |
2865 | ||
6b72c542 | 2866 | return false; |
3f5a74c5 RH |
2867 | } |
2868 | ||
4a358556 RH |
2869 | static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, |
2870 | target_ulong address, | |
2871 | MMUAccessType access_type, | |
2872 | GetPhysAddrResult *result, | |
2873 | ARMMMUFaultInfo *fi) | |
8ae08860 | 2874 | { |
4a358556 | 2875 | ARMMMUIdx mmu_idx = ptw->in_mmu_idx; |
4a358556 | 2876 | bool is_secure = ptw->in_secure; |
48da29e4 | 2877 | ARMMMUIdx s1_mmu_idx; |
8ae08860 | 2878 | |
cead7fa4 | 2879 | /* |
90c66293 RH |
2880 | * The page table entries may downgrade Secure to NonSecure, but |
2881 | * cannot upgrade a NonSecure translation regime's attributes | |
2882 | * to Secure or Realm. | |
cead7fa4 RH |
2883 | */ |
2884 | result->f.attrs.secure = is_secure; | |
90c66293 | 2885 | result->f.attrs.space = ptw->in_space; |
cead7fa4 | 2886 | |
48da29e4 RH |
2887 | switch (mmu_idx) { |
2888 | case ARMMMUIdx_Phys_S: | |
2889 | case ARMMMUIdx_Phys_NS: | |
bb5cc2c8 RH |
2890 | case ARMMMUIdx_Phys_Root: |
2891 | case ARMMMUIdx_Phys_Realm: | |
48da29e4 RH |
2892 | /* Checking Phys early avoids special casing later vs regime_el. */ |
2893 | return get_phys_addr_disabled(env, address, access_type, mmu_idx, | |
2894 | is_secure, result, fi); | |
2895 | ||
2896 | case ARMMMUIdx_Stage1_E0: | |
2897 | case ARMMMUIdx_Stage1_E1: | |
2898 | case ARMMMUIdx_Stage1_E1_PAN: | |
2899 | /* First stage lookup uses second stage for ptw. */ | |
2900 | ptw->in_ptw_idx = is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; | |
2901 | break; | |
2902 | ||
fcc0b041 PM |
2903 | case ARMMMUIdx_Stage2: |
2904 | case ARMMMUIdx_Stage2_S: | |
2905 | /* | |
2906 | * Second stage lookup uses physical for ptw; whether this is S or | |
2907 | * NS may depend on the SW/NSW bits if this is a stage 2 lookup for | |
2908 | * the Secure EL2&0 regime. | |
2909 | */ | |
2910 | ptw->in_ptw_idx = ptw_idx_for_stage_2(env, mmu_idx); | |
2911 | break; | |
2912 | ||
48da29e4 RH |
2913 | case ARMMMUIdx_E10_0: |
2914 | s1_mmu_idx = ARMMMUIdx_Stage1_E0; | |
2915 | goto do_twostage; | |
2916 | case ARMMMUIdx_E10_1: | |
2917 | s1_mmu_idx = ARMMMUIdx_Stage1_E1; | |
2918 | goto do_twostage; | |
2919 | case ARMMMUIdx_E10_1_PAN: | |
2920 | s1_mmu_idx = ARMMMUIdx_Stage1_E1_PAN; | |
2921 | do_twostage: | |
8ae08860 RH |
2922 | /* |
2923 | * Call ourselves recursively to do the stage 1 and then stage 2 | |
3f5a74c5 RH |
2924 | * translations if mmu_idx is a two-stage regime, and EL2 present. |
2925 | * Otherwise, a stage1+stage2 translation is just stage 1. | |
8ae08860 | 2926 | */ |
3f5a74c5 | 2927 | ptw->in_mmu_idx = mmu_idx = s1_mmu_idx; |
26ba00cf PM |
2928 | if (arm_feature(env, ARM_FEATURE_EL2) && |
2929 | !regime_translation_disabled(env, ARMMMUIdx_Stage2, is_secure)) { | |
3f5a74c5 RH |
2930 | return get_phys_addr_twostage(env, ptw, address, access_type, |
2931 | result, fi); | |
8ae08860 | 2932 | } |
48da29e4 RH |
2933 | /* fall through */ |
2934 | ||
2935 | default: | |
fcc0b041 | 2936 | /* Single stage uses physical for ptw. */ |
90c66293 | 2937 | ptw->in_ptw_idx = arm_space_to_phys(ptw->in_space); |
48da29e4 | 2938 | break; |
8ae08860 RH |
2939 | } |
2940 | ||
7fa7ea8f | 2941 | result->f.attrs.user = regime_is_user(env, mmu_idx); |
8ae08860 RH |
2942 | |
2943 | /* | |
2944 | * Fast Context Switch Extension. This doesn't exist at all in v8. | |
2945 | * In v7 and earlier it affects all stage 1 translations. | |
2946 | */ | |
2947 | if (address < 0x02000000 && mmu_idx != ARMMMUIdx_Stage2 | |
2948 | && !arm_feature(env, ARM_FEATURE_V8)) { | |
2949 | if (regime_el(env, mmu_idx) == 3) { | |
2950 | address += env->cp15.fcseidr_s; | |
2951 | } else { | |
2952 | address += env->cp15.fcseidr_ns; | |
2953 | } | |
2954 | } | |
2955 | ||
2956 | if (arm_feature(env, ARM_FEATURE_PMSA)) { | |
2957 | bool ret; | |
7fa7ea8f | 2958 | result->f.lg_page_size = TARGET_PAGE_BITS; |
8ae08860 RH |
2959 | |
2960 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
2961 | /* PMSAv8 */ | |
2962 | ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx, | |
be0ca948 | 2963 | is_secure, result, fi); |
8ae08860 RH |
2964 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
2965 | /* PMSAv7 */ | |
2966 | ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, | |
957a0bb7 | 2967 | is_secure, result, fi); |
8ae08860 RH |
2968 | } else { |
2969 | /* Pre-v7 MPU */ | |
2970 | ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx, | |
a5b5092f | 2971 | is_secure, result, fi); |
8ae08860 RH |
2972 | } |
2973 | qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32 | |
2974 | " mmu_idx %u -> %s (prot %c%c%c)\n", | |
2975 | access_type == MMU_DATA_LOAD ? "reading" : | |
2976 | (access_type == MMU_DATA_STORE ? "writing" : "execute"), | |
2977 | (uint32_t)address, mmu_idx, | |
2978 | ret ? "Miss" : "Hit", | |
7fa7ea8f RH |
2979 | result->f.prot & PAGE_READ ? 'r' : '-', |
2980 | result->f.prot & PAGE_WRITE ? 'w' : '-', | |
2981 | result->f.prot & PAGE_EXEC ? 'x' : '-'); | |
8ae08860 RH |
2982 | |
2983 | return ret; | |
2984 | } | |
2985 | ||
2986 | /* Definitely a real MMU, not an MPU */ | |
2987 | ||
7e80c0a4 | 2988 | if (regime_translation_disabled(env, mmu_idx, is_secure)) { |
448e42fd RH |
2989 | return get_phys_addr_disabled(env, address, access_type, mmu_idx, |
2990 | is_secure, result, fi); | |
8ae08860 | 2991 | } |
6d2654ff | 2992 | |
8ae08860 | 2993 | if (regime_using_lpae_format(env, mmu_idx)) { |
4a358556 | 2994 | return get_phys_addr_lpae(env, ptw, address, access_type, false, |
6d2654ff | 2995 | result, fi); |
6f2d9d74 TK |
2996 | } else if (arm_feature(env, ARM_FEATURE_V7) || |
2997 | regime_sctlr(env, mmu_idx) & SCTLR_XP) { | |
4a358556 | 2998 | return get_phys_addr_v6(env, ptw, address, access_type, result, fi); |
8ae08860 | 2999 | } else { |
4a358556 | 3000 | return get_phys_addr_v5(env, ptw, address, access_type, result, fi); |
8ae08860 RH |
3001 | } |
3002 | } | |
23971205 | 3003 | |
4a358556 RH |
3004 | bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, |
3005 | MMUAccessType access_type, ARMMMUIdx mmu_idx, | |
3006 | bool is_secure, GetPhysAddrResult *result, | |
3007 | ARMMMUFaultInfo *fi) | |
3008 | { | |
3009 | S1Translate ptw = { | |
3010 | .in_mmu_idx = mmu_idx, | |
3011 | .in_secure = is_secure, | |
90c66293 | 3012 | .in_space = arm_secure_to_space(is_secure), |
4a358556 RH |
3013 | }; |
3014 | return get_phys_addr_with_struct(env, &ptw, address, access_type, | |
3015 | result, fi); | |
3016 | } | |
3017 | ||
def8aa5b RH |
3018 | bool get_phys_addr(CPUARMState *env, target_ulong address, |
3019 | MMUAccessType access_type, ARMMMUIdx mmu_idx, | |
3020 | GetPhysAddrResult *result, ARMMMUFaultInfo *fi) | |
3021 | { | |
90c66293 RH |
3022 | S1Translate ptw = { |
3023 | .in_mmu_idx = mmu_idx, | |
3024 | }; | |
3025 | ARMSecuritySpace ss; | |
03bea66e RH |
3026 | |
3027 | switch (mmu_idx) { | |
3028 | case ARMMMUIdx_E10_0: | |
3029 | case ARMMMUIdx_E10_1: | |
3030 | case ARMMMUIdx_E10_1_PAN: | |
3031 | case ARMMMUIdx_E20_0: | |
3032 | case ARMMMUIdx_E20_2: | |
3033 | case ARMMMUIdx_E20_2_PAN: | |
3034 | case ARMMMUIdx_Stage1_E0: | |
3035 | case ARMMMUIdx_Stage1_E1: | |
3036 | case ARMMMUIdx_Stage1_E1_PAN: | |
3037 | case ARMMMUIdx_E2: | |
90c66293 | 3038 | ss = arm_security_space_below_el3(env); |
d902ae75 | 3039 | break; |
03bea66e | 3040 | case ARMMMUIdx_Stage2: |
90c66293 RH |
3041 | /* |
3042 | * For Secure EL2, we need this index to be NonSecure; | |
3043 | * otherwise this will already be NonSecure or Realm. | |
3044 | */ | |
3045 | ss = arm_security_space_below_el3(env); | |
3046 | if (ss == ARMSS_Secure) { | |
3047 | ss = ARMSS_NonSecure; | |
3048 | } | |
3049 | break; | |
a1ce3084 | 3050 | case ARMMMUIdx_Phys_NS: |
03bea66e RH |
3051 | case ARMMMUIdx_MPrivNegPri: |
3052 | case ARMMMUIdx_MUserNegPri: | |
3053 | case ARMMMUIdx_MPriv: | |
3054 | case ARMMMUIdx_MUser: | |
90c66293 | 3055 | ss = ARMSS_NonSecure; |
03bea66e | 3056 | break; |
03bea66e | 3057 | case ARMMMUIdx_Stage2_S: |
a1ce3084 | 3058 | case ARMMMUIdx_Phys_S: |
03bea66e RH |
3059 | case ARMMMUIdx_MSPrivNegPri: |
3060 | case ARMMMUIdx_MSUserNegPri: | |
3061 | case ARMMMUIdx_MSPriv: | |
3062 | case ARMMMUIdx_MSUser: | |
90c66293 RH |
3063 | ss = ARMSS_Secure; |
3064 | break; | |
3065 | case ARMMMUIdx_E3: | |
3066 | if (arm_feature(env, ARM_FEATURE_AARCH64) && | |
3067 | cpu_isar_feature(aa64_rme, env_archcpu(env))) { | |
3068 | ss = ARMSS_Root; | |
3069 | } else { | |
3070 | ss = ARMSS_Secure; | |
3071 | } | |
3072 | break; | |
3073 | case ARMMMUIdx_Phys_Root: | |
3074 | ss = ARMSS_Root; | |
3075 | break; | |
3076 | case ARMMMUIdx_Phys_Realm: | |
3077 | ss = ARMSS_Realm; | |
03bea66e RH |
3078 | break; |
3079 | default: | |
3080 | g_assert_not_reached(); | |
3081 | } | |
90c66293 RH |
3082 | |
3083 | ptw.in_space = ss; | |
3084 | ptw.in_secure = arm_space_is_secure(ss); | |
3085 | return get_phys_addr_with_struct(env, &ptw, address, access_type, | |
3086 | result, fi); | |
def8aa5b RH |
3087 | } |
3088 | ||
23971205 RH |
3089 | hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, |
3090 | MemTxAttrs *attrs) | |
3091 | { | |
3092 | ARMCPU *cpu = ARM_CPU(cs); | |
3093 | CPUARMState *env = &cpu->env; | |
90c66293 RH |
3094 | ARMMMUIdx mmu_idx = arm_mmu_idx(env); |
3095 | ARMSecuritySpace ss = arm_security_space(env); | |
4a358556 | 3096 | S1Translate ptw = { |
90c66293 RH |
3097 | .in_mmu_idx = mmu_idx, |
3098 | .in_space = ss, | |
3099 | .in_secure = arm_space_is_secure(ss), | |
4a358556 RH |
3100 | .in_debug = true, |
3101 | }; | |
de05a709 | 3102 | GetPhysAddrResult res = {}; |
23971205 | 3103 | ARMMMUFaultInfo fi = {}; |
de05a709 | 3104 | bool ret; |
23971205 | 3105 | |
4a358556 | 3106 | ret = get_phys_addr_with_struct(env, &ptw, addr, MMU_DATA_LOAD, &res, &fi); |
7fa7ea8f | 3107 | *attrs = res.f.attrs; |
23971205 RH |
3108 | |
3109 | if (ret) { | |
3110 | return -1; | |
3111 | } | |
7fa7ea8f | 3112 | return res.f.phys_addr; |
23971205 | 3113 | } |