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38388f7e RH |
1 | /* |
2 | * AArch64 SVE translation | |
3 | * | |
4 | * Copyright (c) 2018 Linaro, Ltd | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
21 | #include "cpu.h" | |
22 | #include "exec/exec-all.h" | |
23 | #include "tcg-op.h" | |
24 | #include "tcg-op-gvec.h" | |
028e2a7b | 25 | #include "tcg-gvec-desc.h" |
38388f7e RH |
26 | #include "qemu/log.h" |
27 | #include "arm_ldst.h" | |
28 | #include "translate.h" | |
29 | #include "internals.h" | |
30 | #include "exec/helper-proto.h" | |
31 | #include "exec/helper-gen.h" | |
32 | #include "exec/log.h" | |
33 | #include "trace-tcg.h" | |
34 | #include "translate-a64.h" | |
35 | ||
ccd841c3 RH |
36 | /* |
37 | * Helpers for extracting complex instruction fields. | |
38 | */ | |
39 | ||
40 | /* See e.g. ASR (immediate, predicated). | |
41 | * Returns -1 for unallocated encoding; diagnose later. | |
42 | */ | |
43 | static int tszimm_esz(int x) | |
44 | { | |
45 | x >>= 3; /* discard imm3 */ | |
46 | return 31 - clz32(x); | |
47 | } | |
48 | ||
49 | static int tszimm_shr(int x) | |
50 | { | |
51 | return (16 << tszimm_esz(x)) - x; | |
52 | } | |
53 | ||
54 | /* See e.g. LSL (immediate, predicated). */ | |
55 | static int tszimm_shl(int x) | |
56 | { | |
57 | return x - (8 << tszimm_esz(x)); | |
58 | } | |
59 | ||
38388f7e RH |
60 | /* |
61 | * Include the generated decoder. | |
62 | */ | |
63 | ||
64 | #include "decode-sve.inc.c" | |
65 | ||
66 | /* | |
67 | * Implement all of the translator functions referenced by the decoder. | |
68 | */ | |
69 | ||
d1822297 RH |
70 | /* Return the offset info CPUARMState of the predicate vector register Pn. |
71 | * Note for this purpose, FFR is P16. | |
72 | */ | |
73 | static inline int pred_full_reg_offset(DisasContext *s, int regno) | |
74 | { | |
75 | return offsetof(CPUARMState, vfp.pregs[regno]); | |
76 | } | |
77 | ||
78 | /* Return the byte size of the whole predicate register, VL / 64. */ | |
79 | static inline int pred_full_reg_size(DisasContext *s) | |
80 | { | |
81 | return s->sve_len >> 3; | |
82 | } | |
83 | ||
516e246a RH |
84 | /* Round up the size of a register to a size allowed by |
85 | * the tcg vector infrastructure. Any operation which uses this | |
86 | * size may assume that the bits above pred_full_reg_size are zero, | |
87 | * and must leave them the same way. | |
88 | * | |
89 | * Note that this is not needed for the vector registers as they | |
90 | * are always properly sized for tcg vectors. | |
91 | */ | |
92 | static int size_for_gvec(int size) | |
93 | { | |
94 | if (size <= 8) { | |
95 | return 8; | |
96 | } else { | |
97 | return QEMU_ALIGN_UP(size, 16); | |
98 | } | |
99 | } | |
100 | ||
101 | static int pred_gvec_reg_size(DisasContext *s) | |
102 | { | |
103 | return size_for_gvec(pred_full_reg_size(s)); | |
104 | } | |
105 | ||
39eea561 RH |
106 | /* Invoke a vector expander on two Zregs. */ |
107 | static bool do_vector2_z(DisasContext *s, GVecGen2Fn *gvec_fn, | |
108 | int esz, int rd, int rn) | |
38388f7e | 109 | { |
39eea561 RH |
110 | if (sve_access_check(s)) { |
111 | unsigned vsz = vec_full_reg_size(s); | |
112 | gvec_fn(esz, vec_full_reg_offset(s, rd), | |
113 | vec_full_reg_offset(s, rn), vsz, vsz); | |
114 | } | |
115 | return true; | |
38388f7e RH |
116 | } |
117 | ||
39eea561 RH |
118 | /* Invoke a vector expander on three Zregs. */ |
119 | static bool do_vector3_z(DisasContext *s, GVecGen3Fn *gvec_fn, | |
120 | int esz, int rd, int rn, int rm) | |
38388f7e | 121 | { |
39eea561 RH |
122 | if (sve_access_check(s)) { |
123 | unsigned vsz = vec_full_reg_size(s); | |
124 | gvec_fn(esz, vec_full_reg_offset(s, rd), | |
125 | vec_full_reg_offset(s, rn), | |
126 | vec_full_reg_offset(s, rm), vsz, vsz); | |
127 | } | |
128 | return true; | |
38388f7e RH |
129 | } |
130 | ||
39eea561 RH |
131 | /* Invoke a vector move on two Zregs. */ |
132 | static bool do_mov_z(DisasContext *s, int rd, int rn) | |
38388f7e | 133 | { |
39eea561 | 134 | return do_vector2_z(s, tcg_gen_gvec_mov, 0, rd, rn); |
38388f7e RH |
135 | } |
136 | ||
516e246a RH |
137 | /* Invoke a vector expander on two Pregs. */ |
138 | static bool do_vector2_p(DisasContext *s, GVecGen2Fn *gvec_fn, | |
139 | int esz, int rd, int rn) | |
140 | { | |
141 | if (sve_access_check(s)) { | |
142 | unsigned psz = pred_gvec_reg_size(s); | |
143 | gvec_fn(esz, pred_full_reg_offset(s, rd), | |
144 | pred_full_reg_offset(s, rn), psz, psz); | |
145 | } | |
146 | return true; | |
147 | } | |
148 | ||
149 | /* Invoke a vector expander on three Pregs. */ | |
150 | static bool do_vector3_p(DisasContext *s, GVecGen3Fn *gvec_fn, | |
151 | int esz, int rd, int rn, int rm) | |
152 | { | |
153 | if (sve_access_check(s)) { | |
154 | unsigned psz = pred_gvec_reg_size(s); | |
155 | gvec_fn(esz, pred_full_reg_offset(s, rd), | |
156 | pred_full_reg_offset(s, rn), | |
157 | pred_full_reg_offset(s, rm), psz, psz); | |
158 | } | |
159 | return true; | |
160 | } | |
161 | ||
162 | /* Invoke a vector operation on four Pregs. */ | |
163 | static bool do_vecop4_p(DisasContext *s, const GVecGen4 *gvec_op, | |
164 | int rd, int rn, int rm, int rg) | |
165 | { | |
166 | if (sve_access_check(s)) { | |
167 | unsigned psz = pred_gvec_reg_size(s); | |
168 | tcg_gen_gvec_4(pred_full_reg_offset(s, rd), | |
169 | pred_full_reg_offset(s, rn), | |
170 | pred_full_reg_offset(s, rm), | |
171 | pred_full_reg_offset(s, rg), | |
172 | psz, psz, gvec_op); | |
173 | } | |
174 | return true; | |
175 | } | |
176 | ||
177 | /* Invoke a vector move on two Pregs. */ | |
178 | static bool do_mov_p(DisasContext *s, int rd, int rn) | |
179 | { | |
180 | return do_vector2_p(s, tcg_gen_gvec_mov, 0, rd, rn); | |
181 | } | |
182 | ||
9e18d7a6 RH |
183 | /* Set the cpu flags as per a return from an SVE helper. */ |
184 | static void do_pred_flags(TCGv_i32 t) | |
185 | { | |
186 | tcg_gen_mov_i32(cpu_NF, t); | |
187 | tcg_gen_andi_i32(cpu_ZF, t, 2); | |
188 | tcg_gen_andi_i32(cpu_CF, t, 1); | |
189 | tcg_gen_movi_i32(cpu_VF, 0); | |
190 | } | |
191 | ||
192 | /* Subroutines computing the ARM PredTest psuedofunction. */ | |
193 | static void do_predtest1(TCGv_i64 d, TCGv_i64 g) | |
194 | { | |
195 | TCGv_i32 t = tcg_temp_new_i32(); | |
196 | ||
197 | gen_helper_sve_predtest1(t, d, g); | |
198 | do_pred_flags(t); | |
199 | tcg_temp_free_i32(t); | |
200 | } | |
201 | ||
202 | static void do_predtest(DisasContext *s, int dofs, int gofs, int words) | |
203 | { | |
204 | TCGv_ptr dptr = tcg_temp_new_ptr(); | |
205 | TCGv_ptr gptr = tcg_temp_new_ptr(); | |
206 | TCGv_i32 t; | |
207 | ||
208 | tcg_gen_addi_ptr(dptr, cpu_env, dofs); | |
209 | tcg_gen_addi_ptr(gptr, cpu_env, gofs); | |
210 | t = tcg_const_i32(words); | |
211 | ||
212 | gen_helper_sve_predtest(t, dptr, gptr, t); | |
213 | tcg_temp_free_ptr(dptr); | |
214 | tcg_temp_free_ptr(gptr); | |
215 | ||
216 | do_pred_flags(t); | |
217 | tcg_temp_free_i32(t); | |
218 | } | |
219 | ||
028e2a7b RH |
220 | /* For each element size, the bits within a predicate word that are active. */ |
221 | const uint64_t pred_esz_masks[4] = { | |
222 | 0xffffffffffffffffull, 0x5555555555555555ull, | |
223 | 0x1111111111111111ull, 0x0101010101010101ull | |
224 | }; | |
225 | ||
39eea561 RH |
226 | /* |
227 | *** SVE Logical - Unpredicated Group | |
228 | */ | |
229 | ||
230 | static bool trans_AND_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) | |
231 | { | |
232 | return do_vector3_z(s, tcg_gen_gvec_and, 0, a->rd, a->rn, a->rm); | |
233 | } | |
234 | ||
235 | static bool trans_ORR_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) | |
236 | { | |
237 | if (a->rn == a->rm) { /* MOV */ | |
238 | return do_mov_z(s, a->rd, a->rn); | |
239 | } else { | |
240 | return do_vector3_z(s, tcg_gen_gvec_or, 0, a->rd, a->rn, a->rm); | |
241 | } | |
242 | } | |
243 | ||
244 | static bool trans_EOR_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) | |
245 | { | |
246 | return do_vector3_z(s, tcg_gen_gvec_xor, 0, a->rd, a->rn, a->rm); | |
247 | } | |
248 | ||
249 | static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) | |
38388f7e | 250 | { |
39eea561 | 251 | return do_vector3_z(s, tcg_gen_gvec_andc, 0, a->rd, a->rn, a->rm); |
38388f7e | 252 | } |
d1822297 | 253 | |
fea98f9c RH |
254 | /* |
255 | *** SVE Integer Arithmetic - Unpredicated Group | |
256 | */ | |
257 | ||
258 | static bool trans_ADD_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) | |
259 | { | |
260 | return do_vector3_z(s, tcg_gen_gvec_add, a->esz, a->rd, a->rn, a->rm); | |
261 | } | |
262 | ||
263 | static bool trans_SUB_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) | |
264 | { | |
265 | return do_vector3_z(s, tcg_gen_gvec_sub, a->esz, a->rd, a->rn, a->rm); | |
266 | } | |
267 | ||
268 | static bool trans_SQADD_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) | |
269 | { | |
270 | return do_vector3_z(s, tcg_gen_gvec_ssadd, a->esz, a->rd, a->rn, a->rm); | |
271 | } | |
272 | ||
273 | static bool trans_SQSUB_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) | |
274 | { | |
275 | return do_vector3_z(s, tcg_gen_gvec_sssub, a->esz, a->rd, a->rn, a->rm); | |
276 | } | |
277 | ||
278 | static bool trans_UQADD_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) | |
279 | { | |
280 | return do_vector3_z(s, tcg_gen_gvec_usadd, a->esz, a->rd, a->rn, a->rm); | |
281 | } | |
282 | ||
283 | static bool trans_UQSUB_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) | |
284 | { | |
285 | return do_vector3_z(s, tcg_gen_gvec_ussub, a->esz, a->rd, a->rn, a->rm); | |
286 | } | |
287 | ||
f97cfd59 RH |
288 | /* |
289 | *** SVE Integer Arithmetic - Binary Predicated Group | |
290 | */ | |
291 | ||
292 | static bool do_zpzz_ool(DisasContext *s, arg_rprr_esz *a, gen_helper_gvec_4 *fn) | |
293 | { | |
294 | unsigned vsz = vec_full_reg_size(s); | |
295 | if (fn == NULL) { | |
296 | return false; | |
297 | } | |
298 | if (sve_access_check(s)) { | |
299 | tcg_gen_gvec_4_ool(vec_full_reg_offset(s, a->rd), | |
300 | vec_full_reg_offset(s, a->rn), | |
301 | vec_full_reg_offset(s, a->rm), | |
302 | pred_full_reg_offset(s, a->pg), | |
303 | vsz, vsz, 0, fn); | |
304 | } | |
305 | return true; | |
306 | } | |
307 | ||
308 | #define DO_ZPZZ(NAME, name) \ | |
309 | static bool trans_##NAME##_zpzz(DisasContext *s, arg_rprr_esz *a, \ | |
310 | uint32_t insn) \ | |
311 | { \ | |
312 | static gen_helper_gvec_4 * const fns[4] = { \ | |
313 | gen_helper_sve_##name##_zpzz_b, gen_helper_sve_##name##_zpzz_h, \ | |
314 | gen_helper_sve_##name##_zpzz_s, gen_helper_sve_##name##_zpzz_d, \ | |
315 | }; \ | |
316 | return do_zpzz_ool(s, a, fns[a->esz]); \ | |
317 | } | |
318 | ||
319 | DO_ZPZZ(AND, and) | |
320 | DO_ZPZZ(EOR, eor) | |
321 | DO_ZPZZ(ORR, orr) | |
322 | DO_ZPZZ(BIC, bic) | |
323 | ||
324 | DO_ZPZZ(ADD, add) | |
325 | DO_ZPZZ(SUB, sub) | |
326 | ||
327 | DO_ZPZZ(SMAX, smax) | |
328 | DO_ZPZZ(UMAX, umax) | |
329 | DO_ZPZZ(SMIN, smin) | |
330 | DO_ZPZZ(UMIN, umin) | |
331 | DO_ZPZZ(SABD, sabd) | |
332 | DO_ZPZZ(UABD, uabd) | |
333 | ||
334 | DO_ZPZZ(MUL, mul) | |
335 | DO_ZPZZ(SMULH, smulh) | |
336 | DO_ZPZZ(UMULH, umulh) | |
337 | ||
27721dbb RH |
338 | DO_ZPZZ(ASR, asr) |
339 | DO_ZPZZ(LSR, lsr) | |
340 | DO_ZPZZ(LSL, lsl) | |
341 | ||
f97cfd59 RH |
342 | static bool trans_SDIV_zpzz(DisasContext *s, arg_rprr_esz *a, uint32_t insn) |
343 | { | |
344 | static gen_helper_gvec_4 * const fns[4] = { | |
345 | NULL, NULL, gen_helper_sve_sdiv_zpzz_s, gen_helper_sve_sdiv_zpzz_d | |
346 | }; | |
347 | return do_zpzz_ool(s, a, fns[a->esz]); | |
348 | } | |
349 | ||
350 | static bool trans_UDIV_zpzz(DisasContext *s, arg_rprr_esz *a, uint32_t insn) | |
351 | { | |
352 | static gen_helper_gvec_4 * const fns[4] = { | |
353 | NULL, NULL, gen_helper_sve_udiv_zpzz_s, gen_helper_sve_udiv_zpzz_d | |
354 | }; | |
355 | return do_zpzz_ool(s, a, fns[a->esz]); | |
356 | } | |
357 | ||
358 | #undef DO_ZPZZ | |
359 | ||
afac6d04 RH |
360 | /* |
361 | *** SVE Integer Arithmetic - Unary Predicated Group | |
362 | */ | |
363 | ||
364 | static bool do_zpz_ool(DisasContext *s, arg_rpr_esz *a, gen_helper_gvec_3 *fn) | |
365 | { | |
366 | if (fn == NULL) { | |
367 | return false; | |
368 | } | |
369 | if (sve_access_check(s)) { | |
370 | unsigned vsz = vec_full_reg_size(s); | |
371 | tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd), | |
372 | vec_full_reg_offset(s, a->rn), | |
373 | pred_full_reg_offset(s, a->pg), | |
374 | vsz, vsz, 0, fn); | |
375 | } | |
376 | return true; | |
377 | } | |
378 | ||
379 | #define DO_ZPZ(NAME, name) \ | |
380 | static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a, uint32_t insn) \ | |
381 | { \ | |
382 | static gen_helper_gvec_3 * const fns[4] = { \ | |
383 | gen_helper_sve_##name##_b, gen_helper_sve_##name##_h, \ | |
384 | gen_helper_sve_##name##_s, gen_helper_sve_##name##_d, \ | |
385 | }; \ | |
386 | return do_zpz_ool(s, a, fns[a->esz]); \ | |
387 | } | |
388 | ||
389 | DO_ZPZ(CLS, cls) | |
390 | DO_ZPZ(CLZ, clz) | |
391 | DO_ZPZ(CNT_zpz, cnt_zpz) | |
392 | DO_ZPZ(CNOT, cnot) | |
393 | DO_ZPZ(NOT_zpz, not_zpz) | |
394 | DO_ZPZ(ABS, abs) | |
395 | DO_ZPZ(NEG, neg) | |
396 | ||
397 | static bool trans_FABS(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | |
398 | { | |
399 | static gen_helper_gvec_3 * const fns[4] = { | |
400 | NULL, | |
401 | gen_helper_sve_fabs_h, | |
402 | gen_helper_sve_fabs_s, | |
403 | gen_helper_sve_fabs_d | |
404 | }; | |
405 | return do_zpz_ool(s, a, fns[a->esz]); | |
406 | } | |
407 | ||
408 | static bool trans_FNEG(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | |
409 | { | |
410 | static gen_helper_gvec_3 * const fns[4] = { | |
411 | NULL, | |
412 | gen_helper_sve_fneg_h, | |
413 | gen_helper_sve_fneg_s, | |
414 | gen_helper_sve_fneg_d | |
415 | }; | |
416 | return do_zpz_ool(s, a, fns[a->esz]); | |
417 | } | |
418 | ||
419 | static bool trans_SXTB(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | |
420 | { | |
421 | static gen_helper_gvec_3 * const fns[4] = { | |
422 | NULL, | |
423 | gen_helper_sve_sxtb_h, | |
424 | gen_helper_sve_sxtb_s, | |
425 | gen_helper_sve_sxtb_d | |
426 | }; | |
427 | return do_zpz_ool(s, a, fns[a->esz]); | |
428 | } | |
429 | ||
430 | static bool trans_UXTB(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | |
431 | { | |
432 | static gen_helper_gvec_3 * const fns[4] = { | |
433 | NULL, | |
434 | gen_helper_sve_uxtb_h, | |
435 | gen_helper_sve_uxtb_s, | |
436 | gen_helper_sve_uxtb_d | |
437 | }; | |
438 | return do_zpz_ool(s, a, fns[a->esz]); | |
439 | } | |
440 | ||
441 | static bool trans_SXTH(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | |
442 | { | |
443 | static gen_helper_gvec_3 * const fns[4] = { | |
444 | NULL, NULL, | |
445 | gen_helper_sve_sxth_s, | |
446 | gen_helper_sve_sxth_d | |
447 | }; | |
448 | return do_zpz_ool(s, a, fns[a->esz]); | |
449 | } | |
450 | ||
451 | static bool trans_UXTH(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | |
452 | { | |
453 | static gen_helper_gvec_3 * const fns[4] = { | |
454 | NULL, NULL, | |
455 | gen_helper_sve_uxth_s, | |
456 | gen_helper_sve_uxth_d | |
457 | }; | |
458 | return do_zpz_ool(s, a, fns[a->esz]); | |
459 | } | |
460 | ||
461 | static bool trans_SXTW(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | |
462 | { | |
463 | return do_zpz_ool(s, a, a->esz == 3 ? gen_helper_sve_sxtw_d : NULL); | |
464 | } | |
465 | ||
466 | static bool trans_UXTW(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | |
467 | { | |
468 | return do_zpz_ool(s, a, a->esz == 3 ? gen_helper_sve_uxtw_d : NULL); | |
469 | } | |
470 | ||
471 | #undef DO_ZPZ | |
472 | ||
047cec97 RH |
473 | /* |
474 | *** SVE Integer Reduction Group | |
475 | */ | |
476 | ||
477 | typedef void gen_helper_gvec_reduc(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_i32); | |
478 | static bool do_vpz_ool(DisasContext *s, arg_rpr_esz *a, | |
479 | gen_helper_gvec_reduc *fn) | |
480 | { | |
481 | unsigned vsz = vec_full_reg_size(s); | |
482 | TCGv_ptr t_zn, t_pg; | |
483 | TCGv_i32 desc; | |
484 | TCGv_i64 temp; | |
485 | ||
486 | if (fn == NULL) { | |
487 | return false; | |
488 | } | |
489 | if (!sve_access_check(s)) { | |
490 | return true; | |
491 | } | |
492 | ||
493 | desc = tcg_const_i32(simd_desc(vsz, vsz, 0)); | |
494 | temp = tcg_temp_new_i64(); | |
495 | t_zn = tcg_temp_new_ptr(); | |
496 | t_pg = tcg_temp_new_ptr(); | |
497 | ||
498 | tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, a->rn)); | |
499 | tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg)); | |
500 | fn(temp, t_zn, t_pg, desc); | |
501 | tcg_temp_free_ptr(t_zn); | |
502 | tcg_temp_free_ptr(t_pg); | |
503 | tcg_temp_free_i32(desc); | |
504 | ||
505 | write_fp_dreg(s, a->rd, temp); | |
506 | tcg_temp_free_i64(temp); | |
507 | return true; | |
508 | } | |
509 | ||
510 | #define DO_VPZ(NAME, name) \ | |
511 | static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a, uint32_t insn) \ | |
512 | { \ | |
513 | static gen_helper_gvec_reduc * const fns[4] = { \ | |
514 | gen_helper_sve_##name##_b, gen_helper_sve_##name##_h, \ | |
515 | gen_helper_sve_##name##_s, gen_helper_sve_##name##_d, \ | |
516 | }; \ | |
517 | return do_vpz_ool(s, a, fns[a->esz]); \ | |
518 | } | |
519 | ||
520 | DO_VPZ(ORV, orv) | |
521 | DO_VPZ(ANDV, andv) | |
522 | DO_VPZ(EORV, eorv) | |
523 | ||
524 | DO_VPZ(UADDV, uaddv) | |
525 | DO_VPZ(SMAXV, smaxv) | |
526 | DO_VPZ(UMAXV, umaxv) | |
527 | DO_VPZ(SMINV, sminv) | |
528 | DO_VPZ(UMINV, uminv) | |
529 | ||
530 | static bool trans_SADDV(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | |
531 | { | |
532 | static gen_helper_gvec_reduc * const fns[4] = { | |
533 | gen_helper_sve_saddv_b, gen_helper_sve_saddv_h, | |
534 | gen_helper_sve_saddv_s, NULL | |
535 | }; | |
536 | return do_vpz_ool(s, a, fns[a->esz]); | |
537 | } | |
538 | ||
539 | #undef DO_VPZ | |
540 | ||
ccd841c3 RH |
541 | /* |
542 | *** SVE Shift by Immediate - Predicated Group | |
543 | */ | |
544 | ||
545 | /* Store zero into every active element of Zd. We will use this for two | |
546 | * and three-operand predicated instructions for which logic dictates a | |
547 | * zero result. | |
548 | */ | |
549 | static bool do_clr_zp(DisasContext *s, int rd, int pg, int esz) | |
550 | { | |
551 | static gen_helper_gvec_2 * const fns[4] = { | |
552 | gen_helper_sve_clr_b, gen_helper_sve_clr_h, | |
553 | gen_helper_sve_clr_s, gen_helper_sve_clr_d, | |
554 | }; | |
555 | if (sve_access_check(s)) { | |
556 | unsigned vsz = vec_full_reg_size(s); | |
557 | tcg_gen_gvec_2_ool(vec_full_reg_offset(s, rd), | |
558 | pred_full_reg_offset(s, pg), | |
559 | vsz, vsz, 0, fns[esz]); | |
560 | } | |
561 | return true; | |
562 | } | |
563 | ||
564 | static bool do_zpzi_ool(DisasContext *s, arg_rpri_esz *a, | |
565 | gen_helper_gvec_3 *fn) | |
566 | { | |
567 | if (sve_access_check(s)) { | |
568 | unsigned vsz = vec_full_reg_size(s); | |
569 | tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd), | |
570 | vec_full_reg_offset(s, a->rn), | |
571 | pred_full_reg_offset(s, a->pg), | |
572 | vsz, vsz, a->imm, fn); | |
573 | } | |
574 | return true; | |
575 | } | |
576 | ||
577 | static bool trans_ASR_zpzi(DisasContext *s, arg_rpri_esz *a, uint32_t insn) | |
578 | { | |
579 | static gen_helper_gvec_3 * const fns[4] = { | |
580 | gen_helper_sve_asr_zpzi_b, gen_helper_sve_asr_zpzi_h, | |
581 | gen_helper_sve_asr_zpzi_s, gen_helper_sve_asr_zpzi_d, | |
582 | }; | |
583 | if (a->esz < 0) { | |
584 | /* Invalid tsz encoding -- see tszimm_esz. */ | |
585 | return false; | |
586 | } | |
587 | /* Shift by element size is architecturally valid. For | |
588 | arithmetic right-shift, it's the same as by one less. */ | |
589 | a->imm = MIN(a->imm, (8 << a->esz) - 1); | |
590 | return do_zpzi_ool(s, a, fns[a->esz]); | |
591 | } | |
592 | ||
593 | static bool trans_LSR_zpzi(DisasContext *s, arg_rpri_esz *a, uint32_t insn) | |
594 | { | |
595 | static gen_helper_gvec_3 * const fns[4] = { | |
596 | gen_helper_sve_lsr_zpzi_b, gen_helper_sve_lsr_zpzi_h, | |
597 | gen_helper_sve_lsr_zpzi_s, gen_helper_sve_lsr_zpzi_d, | |
598 | }; | |
599 | if (a->esz < 0) { | |
600 | return false; | |
601 | } | |
602 | /* Shift by element size is architecturally valid. | |
603 | For logical shifts, it is a zeroing operation. */ | |
604 | if (a->imm >= (8 << a->esz)) { | |
605 | return do_clr_zp(s, a->rd, a->pg, a->esz); | |
606 | } else { | |
607 | return do_zpzi_ool(s, a, fns[a->esz]); | |
608 | } | |
609 | } | |
610 | ||
611 | static bool trans_LSL_zpzi(DisasContext *s, arg_rpri_esz *a, uint32_t insn) | |
612 | { | |
613 | static gen_helper_gvec_3 * const fns[4] = { | |
614 | gen_helper_sve_lsl_zpzi_b, gen_helper_sve_lsl_zpzi_h, | |
615 | gen_helper_sve_lsl_zpzi_s, gen_helper_sve_lsl_zpzi_d, | |
616 | }; | |
617 | if (a->esz < 0) { | |
618 | return false; | |
619 | } | |
620 | /* Shift by element size is architecturally valid. | |
621 | For logical shifts, it is a zeroing operation. */ | |
622 | if (a->imm >= (8 << a->esz)) { | |
623 | return do_clr_zp(s, a->rd, a->pg, a->esz); | |
624 | } else { | |
625 | return do_zpzi_ool(s, a, fns[a->esz]); | |
626 | } | |
627 | } | |
628 | ||
629 | static bool trans_ASRD(DisasContext *s, arg_rpri_esz *a, uint32_t insn) | |
630 | { | |
631 | static gen_helper_gvec_3 * const fns[4] = { | |
632 | gen_helper_sve_asrd_b, gen_helper_sve_asrd_h, | |
633 | gen_helper_sve_asrd_s, gen_helper_sve_asrd_d, | |
634 | }; | |
635 | if (a->esz < 0) { | |
636 | return false; | |
637 | } | |
638 | /* Shift by element size is architecturally valid. For arithmetic | |
639 | right shift for division, it is a zeroing operation. */ | |
640 | if (a->imm >= (8 << a->esz)) { | |
641 | return do_clr_zp(s, a->rd, a->pg, a->esz); | |
642 | } else { | |
643 | return do_zpzi_ool(s, a, fns[a->esz]); | |
644 | } | |
645 | } | |
646 | ||
fe7f8dfb RH |
647 | /* |
648 | *** SVE Bitwise Shift - Predicated Group | |
649 | */ | |
650 | ||
651 | #define DO_ZPZW(NAME, name) \ | |
652 | static bool trans_##NAME##_zpzw(DisasContext *s, arg_rprr_esz *a, \ | |
653 | uint32_t insn) \ | |
654 | { \ | |
655 | static gen_helper_gvec_4 * const fns[3] = { \ | |
656 | gen_helper_sve_##name##_zpzw_b, gen_helper_sve_##name##_zpzw_h, \ | |
657 | gen_helper_sve_##name##_zpzw_s, \ | |
658 | }; \ | |
659 | if (a->esz < 0 || a->esz >= 3) { \ | |
660 | return false; \ | |
661 | } \ | |
662 | return do_zpzz_ool(s, a, fns[a->esz]); \ | |
663 | } | |
664 | ||
665 | DO_ZPZW(ASR, asr) | |
666 | DO_ZPZW(LSR, lsr) | |
667 | DO_ZPZW(LSL, lsl) | |
668 | ||
669 | #undef DO_ZPZW | |
670 | ||
96a36e4a RH |
671 | /* |
672 | *** SVE Integer Multiply-Add Group | |
673 | */ | |
674 | ||
675 | static bool do_zpzzz_ool(DisasContext *s, arg_rprrr_esz *a, | |
676 | gen_helper_gvec_5 *fn) | |
677 | { | |
678 | if (sve_access_check(s)) { | |
679 | unsigned vsz = vec_full_reg_size(s); | |
680 | tcg_gen_gvec_5_ool(vec_full_reg_offset(s, a->rd), | |
681 | vec_full_reg_offset(s, a->ra), | |
682 | vec_full_reg_offset(s, a->rn), | |
683 | vec_full_reg_offset(s, a->rm), | |
684 | pred_full_reg_offset(s, a->pg), | |
685 | vsz, vsz, 0, fn); | |
686 | } | |
687 | return true; | |
688 | } | |
689 | ||
690 | #define DO_ZPZZZ(NAME, name) \ | |
691 | static bool trans_##NAME(DisasContext *s, arg_rprrr_esz *a, uint32_t insn) \ | |
692 | { \ | |
693 | static gen_helper_gvec_5 * const fns[4] = { \ | |
694 | gen_helper_sve_##name##_b, gen_helper_sve_##name##_h, \ | |
695 | gen_helper_sve_##name##_s, gen_helper_sve_##name##_d, \ | |
696 | }; \ | |
697 | return do_zpzzz_ool(s, a, fns[a->esz]); \ | |
698 | } | |
699 | ||
700 | DO_ZPZZZ(MLA, mla) | |
701 | DO_ZPZZZ(MLS, mls) | |
702 | ||
703 | #undef DO_ZPZZZ | |
704 | ||
9a56c9c3 RH |
705 | /* |
706 | *** SVE Index Generation Group | |
707 | */ | |
708 | ||
709 | static void do_index(DisasContext *s, int esz, int rd, | |
710 | TCGv_i64 start, TCGv_i64 incr) | |
711 | { | |
712 | unsigned vsz = vec_full_reg_size(s); | |
713 | TCGv_i32 desc = tcg_const_i32(simd_desc(vsz, vsz, 0)); | |
714 | TCGv_ptr t_zd = tcg_temp_new_ptr(); | |
715 | ||
716 | tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, rd)); | |
717 | if (esz == 3) { | |
718 | gen_helper_sve_index_d(t_zd, start, incr, desc); | |
719 | } else { | |
720 | typedef void index_fn(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32); | |
721 | static index_fn * const fns[3] = { | |
722 | gen_helper_sve_index_b, | |
723 | gen_helper_sve_index_h, | |
724 | gen_helper_sve_index_s, | |
725 | }; | |
726 | TCGv_i32 s32 = tcg_temp_new_i32(); | |
727 | TCGv_i32 i32 = tcg_temp_new_i32(); | |
728 | ||
729 | tcg_gen_extrl_i64_i32(s32, start); | |
730 | tcg_gen_extrl_i64_i32(i32, incr); | |
731 | fns[esz](t_zd, s32, i32, desc); | |
732 | ||
733 | tcg_temp_free_i32(s32); | |
734 | tcg_temp_free_i32(i32); | |
735 | } | |
736 | tcg_temp_free_ptr(t_zd); | |
737 | tcg_temp_free_i32(desc); | |
738 | } | |
739 | ||
740 | static bool trans_INDEX_ii(DisasContext *s, arg_INDEX_ii *a, uint32_t insn) | |
741 | { | |
742 | if (sve_access_check(s)) { | |
743 | TCGv_i64 start = tcg_const_i64(a->imm1); | |
744 | TCGv_i64 incr = tcg_const_i64(a->imm2); | |
745 | do_index(s, a->esz, a->rd, start, incr); | |
746 | tcg_temp_free_i64(start); | |
747 | tcg_temp_free_i64(incr); | |
748 | } | |
749 | return true; | |
750 | } | |
751 | ||
752 | static bool trans_INDEX_ir(DisasContext *s, arg_INDEX_ir *a, uint32_t insn) | |
753 | { | |
754 | if (sve_access_check(s)) { | |
755 | TCGv_i64 start = tcg_const_i64(a->imm); | |
756 | TCGv_i64 incr = cpu_reg(s, a->rm); | |
757 | do_index(s, a->esz, a->rd, start, incr); | |
758 | tcg_temp_free_i64(start); | |
759 | } | |
760 | return true; | |
761 | } | |
762 | ||
763 | static bool trans_INDEX_ri(DisasContext *s, arg_INDEX_ri *a, uint32_t insn) | |
764 | { | |
765 | if (sve_access_check(s)) { | |
766 | TCGv_i64 start = cpu_reg(s, a->rn); | |
767 | TCGv_i64 incr = tcg_const_i64(a->imm); | |
768 | do_index(s, a->esz, a->rd, start, incr); | |
769 | tcg_temp_free_i64(incr); | |
770 | } | |
771 | return true; | |
772 | } | |
773 | ||
774 | static bool trans_INDEX_rr(DisasContext *s, arg_INDEX_rr *a, uint32_t insn) | |
775 | { | |
776 | if (sve_access_check(s)) { | |
777 | TCGv_i64 start = cpu_reg(s, a->rn); | |
778 | TCGv_i64 incr = cpu_reg(s, a->rm); | |
779 | do_index(s, a->esz, a->rd, start, incr); | |
780 | } | |
781 | return true; | |
782 | } | |
783 | ||
96f922cc RH |
784 | /* |
785 | *** SVE Stack Allocation Group | |
786 | */ | |
787 | ||
788 | static bool trans_ADDVL(DisasContext *s, arg_ADDVL *a, uint32_t insn) | |
789 | { | |
790 | TCGv_i64 rd = cpu_reg_sp(s, a->rd); | |
791 | TCGv_i64 rn = cpu_reg_sp(s, a->rn); | |
792 | tcg_gen_addi_i64(rd, rn, a->imm * vec_full_reg_size(s)); | |
793 | return true; | |
794 | } | |
795 | ||
796 | static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a, uint32_t insn) | |
797 | { | |
798 | TCGv_i64 rd = cpu_reg_sp(s, a->rd); | |
799 | TCGv_i64 rn = cpu_reg_sp(s, a->rn); | |
800 | tcg_gen_addi_i64(rd, rn, a->imm * pred_full_reg_size(s)); | |
801 | return true; | |
802 | } | |
803 | ||
804 | static bool trans_RDVL(DisasContext *s, arg_RDVL *a, uint32_t insn) | |
805 | { | |
806 | TCGv_i64 reg = cpu_reg(s, a->rd); | |
807 | tcg_gen_movi_i64(reg, a->imm * vec_full_reg_size(s)); | |
808 | return true; | |
809 | } | |
810 | ||
516e246a RH |
811 | /* |
812 | *** SVE Predicate Logical Operations Group | |
813 | */ | |
814 | ||
815 | static bool do_pppp_flags(DisasContext *s, arg_rprr_s *a, | |
816 | const GVecGen4 *gvec_op) | |
817 | { | |
818 | if (!sve_access_check(s)) { | |
819 | return true; | |
820 | } | |
821 | ||
822 | unsigned psz = pred_gvec_reg_size(s); | |
823 | int dofs = pred_full_reg_offset(s, a->rd); | |
824 | int nofs = pred_full_reg_offset(s, a->rn); | |
825 | int mofs = pred_full_reg_offset(s, a->rm); | |
826 | int gofs = pred_full_reg_offset(s, a->pg); | |
827 | ||
828 | if (psz == 8) { | |
829 | /* Do the operation and the flags generation in temps. */ | |
830 | TCGv_i64 pd = tcg_temp_new_i64(); | |
831 | TCGv_i64 pn = tcg_temp_new_i64(); | |
832 | TCGv_i64 pm = tcg_temp_new_i64(); | |
833 | TCGv_i64 pg = tcg_temp_new_i64(); | |
834 | ||
835 | tcg_gen_ld_i64(pn, cpu_env, nofs); | |
836 | tcg_gen_ld_i64(pm, cpu_env, mofs); | |
837 | tcg_gen_ld_i64(pg, cpu_env, gofs); | |
838 | ||
839 | gvec_op->fni8(pd, pn, pm, pg); | |
840 | tcg_gen_st_i64(pd, cpu_env, dofs); | |
841 | ||
842 | do_predtest1(pd, pg); | |
843 | ||
844 | tcg_temp_free_i64(pd); | |
845 | tcg_temp_free_i64(pn); | |
846 | tcg_temp_free_i64(pm); | |
847 | tcg_temp_free_i64(pg); | |
848 | } else { | |
849 | /* The operation and flags generation is large. The computation | |
850 | * of the flags depends on the original contents of the guarding | |
851 | * predicate. If the destination overwrites the guarding predicate, | |
852 | * then the easiest way to get this right is to save a copy. | |
853 | */ | |
854 | int tofs = gofs; | |
855 | if (a->rd == a->pg) { | |
856 | tofs = offsetof(CPUARMState, vfp.preg_tmp); | |
857 | tcg_gen_gvec_mov(0, tofs, gofs, psz, psz); | |
858 | } | |
859 | ||
860 | tcg_gen_gvec_4(dofs, nofs, mofs, gofs, psz, psz, gvec_op); | |
861 | do_predtest(s, dofs, tofs, psz / 8); | |
862 | } | |
863 | return true; | |
864 | } | |
865 | ||
866 | static void gen_and_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg) | |
867 | { | |
868 | tcg_gen_and_i64(pd, pn, pm); | |
869 | tcg_gen_and_i64(pd, pd, pg); | |
870 | } | |
871 | ||
872 | static void gen_and_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, | |
873 | TCGv_vec pm, TCGv_vec pg) | |
874 | { | |
875 | tcg_gen_and_vec(vece, pd, pn, pm); | |
876 | tcg_gen_and_vec(vece, pd, pd, pg); | |
877 | } | |
878 | ||
879 | static bool trans_AND_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn) | |
880 | { | |
881 | static const GVecGen4 op = { | |
882 | .fni8 = gen_and_pg_i64, | |
883 | .fniv = gen_and_pg_vec, | |
884 | .fno = gen_helper_sve_and_pppp, | |
885 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
886 | }; | |
887 | if (a->s) { | |
888 | return do_pppp_flags(s, a, &op); | |
889 | } else if (a->rn == a->rm) { | |
890 | if (a->pg == a->rn) { | |
891 | return do_mov_p(s, a->rd, a->rn); | |
892 | } else { | |
893 | return do_vector3_p(s, tcg_gen_gvec_and, 0, a->rd, a->rn, a->pg); | |
894 | } | |
895 | } else if (a->pg == a->rn || a->pg == a->rm) { | |
896 | return do_vector3_p(s, tcg_gen_gvec_and, 0, a->rd, a->rn, a->rm); | |
897 | } else { | |
898 | return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg); | |
899 | } | |
900 | } | |
901 | ||
902 | static void gen_bic_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg) | |
903 | { | |
904 | tcg_gen_andc_i64(pd, pn, pm); | |
905 | tcg_gen_and_i64(pd, pd, pg); | |
906 | } | |
907 | ||
908 | static void gen_bic_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, | |
909 | TCGv_vec pm, TCGv_vec pg) | |
910 | { | |
911 | tcg_gen_andc_vec(vece, pd, pn, pm); | |
912 | tcg_gen_and_vec(vece, pd, pd, pg); | |
913 | } | |
914 | ||
915 | static bool trans_BIC_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn) | |
916 | { | |
917 | static const GVecGen4 op = { | |
918 | .fni8 = gen_bic_pg_i64, | |
919 | .fniv = gen_bic_pg_vec, | |
920 | .fno = gen_helper_sve_bic_pppp, | |
921 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
922 | }; | |
923 | if (a->s) { | |
924 | return do_pppp_flags(s, a, &op); | |
925 | } else if (a->pg == a->rn) { | |
926 | return do_vector3_p(s, tcg_gen_gvec_andc, 0, a->rd, a->rn, a->rm); | |
927 | } else { | |
928 | return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg); | |
929 | } | |
930 | } | |
931 | ||
932 | static void gen_eor_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg) | |
933 | { | |
934 | tcg_gen_xor_i64(pd, pn, pm); | |
935 | tcg_gen_and_i64(pd, pd, pg); | |
936 | } | |
937 | ||
938 | static void gen_eor_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, | |
939 | TCGv_vec pm, TCGv_vec pg) | |
940 | { | |
941 | tcg_gen_xor_vec(vece, pd, pn, pm); | |
942 | tcg_gen_and_vec(vece, pd, pd, pg); | |
943 | } | |
944 | ||
945 | static bool trans_EOR_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn) | |
946 | { | |
947 | static const GVecGen4 op = { | |
948 | .fni8 = gen_eor_pg_i64, | |
949 | .fniv = gen_eor_pg_vec, | |
950 | .fno = gen_helper_sve_eor_pppp, | |
951 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
952 | }; | |
953 | if (a->s) { | |
954 | return do_pppp_flags(s, a, &op); | |
955 | } else { | |
956 | return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg); | |
957 | } | |
958 | } | |
959 | ||
960 | static void gen_sel_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg) | |
961 | { | |
962 | tcg_gen_and_i64(pn, pn, pg); | |
963 | tcg_gen_andc_i64(pm, pm, pg); | |
964 | tcg_gen_or_i64(pd, pn, pm); | |
965 | } | |
966 | ||
967 | static void gen_sel_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, | |
968 | TCGv_vec pm, TCGv_vec pg) | |
969 | { | |
970 | tcg_gen_and_vec(vece, pn, pn, pg); | |
971 | tcg_gen_andc_vec(vece, pm, pm, pg); | |
972 | tcg_gen_or_vec(vece, pd, pn, pm); | |
973 | } | |
974 | ||
975 | static bool trans_SEL_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn) | |
976 | { | |
977 | static const GVecGen4 op = { | |
978 | .fni8 = gen_sel_pg_i64, | |
979 | .fniv = gen_sel_pg_vec, | |
980 | .fno = gen_helper_sve_sel_pppp, | |
981 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
982 | }; | |
983 | if (a->s) { | |
984 | return false; | |
985 | } else { | |
986 | return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg); | |
987 | } | |
988 | } | |
989 | ||
990 | static void gen_orr_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg) | |
991 | { | |
992 | tcg_gen_or_i64(pd, pn, pm); | |
993 | tcg_gen_and_i64(pd, pd, pg); | |
994 | } | |
995 | ||
996 | static void gen_orr_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, | |
997 | TCGv_vec pm, TCGv_vec pg) | |
998 | { | |
999 | tcg_gen_or_vec(vece, pd, pn, pm); | |
1000 | tcg_gen_and_vec(vece, pd, pd, pg); | |
1001 | } | |
1002 | ||
1003 | static bool trans_ORR_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn) | |
1004 | { | |
1005 | static const GVecGen4 op = { | |
1006 | .fni8 = gen_orr_pg_i64, | |
1007 | .fniv = gen_orr_pg_vec, | |
1008 | .fno = gen_helper_sve_orr_pppp, | |
1009 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
1010 | }; | |
1011 | if (a->s) { | |
1012 | return do_pppp_flags(s, a, &op); | |
1013 | } else if (a->pg == a->rn && a->rn == a->rm) { | |
1014 | return do_mov_p(s, a->rd, a->rn); | |
1015 | } else { | |
1016 | return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg); | |
1017 | } | |
1018 | } | |
1019 | ||
1020 | static void gen_orn_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg) | |
1021 | { | |
1022 | tcg_gen_orc_i64(pd, pn, pm); | |
1023 | tcg_gen_and_i64(pd, pd, pg); | |
1024 | } | |
1025 | ||
1026 | static void gen_orn_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, | |
1027 | TCGv_vec pm, TCGv_vec pg) | |
1028 | { | |
1029 | tcg_gen_orc_vec(vece, pd, pn, pm); | |
1030 | tcg_gen_and_vec(vece, pd, pd, pg); | |
1031 | } | |
1032 | ||
1033 | static bool trans_ORN_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn) | |
1034 | { | |
1035 | static const GVecGen4 op = { | |
1036 | .fni8 = gen_orn_pg_i64, | |
1037 | .fniv = gen_orn_pg_vec, | |
1038 | .fno = gen_helper_sve_orn_pppp, | |
1039 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
1040 | }; | |
1041 | if (a->s) { | |
1042 | return do_pppp_flags(s, a, &op); | |
1043 | } else { | |
1044 | return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg); | |
1045 | } | |
1046 | } | |
1047 | ||
1048 | static void gen_nor_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg) | |
1049 | { | |
1050 | tcg_gen_or_i64(pd, pn, pm); | |
1051 | tcg_gen_andc_i64(pd, pg, pd); | |
1052 | } | |
1053 | ||
1054 | static void gen_nor_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, | |
1055 | TCGv_vec pm, TCGv_vec pg) | |
1056 | { | |
1057 | tcg_gen_or_vec(vece, pd, pn, pm); | |
1058 | tcg_gen_andc_vec(vece, pd, pg, pd); | |
1059 | } | |
1060 | ||
1061 | static bool trans_NOR_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn) | |
1062 | { | |
1063 | static const GVecGen4 op = { | |
1064 | .fni8 = gen_nor_pg_i64, | |
1065 | .fniv = gen_nor_pg_vec, | |
1066 | .fno = gen_helper_sve_nor_pppp, | |
1067 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
1068 | }; | |
1069 | if (a->s) { | |
1070 | return do_pppp_flags(s, a, &op); | |
1071 | } else { | |
1072 | return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg); | |
1073 | } | |
1074 | } | |
1075 | ||
1076 | static void gen_nand_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg) | |
1077 | { | |
1078 | tcg_gen_and_i64(pd, pn, pm); | |
1079 | tcg_gen_andc_i64(pd, pg, pd); | |
1080 | } | |
1081 | ||
1082 | static void gen_nand_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, | |
1083 | TCGv_vec pm, TCGv_vec pg) | |
1084 | { | |
1085 | tcg_gen_and_vec(vece, pd, pn, pm); | |
1086 | tcg_gen_andc_vec(vece, pd, pg, pd); | |
1087 | } | |
1088 | ||
1089 | static bool trans_NAND_pppp(DisasContext *s, arg_rprr_s *a, uint32_t insn) | |
1090 | { | |
1091 | static const GVecGen4 op = { | |
1092 | .fni8 = gen_nand_pg_i64, | |
1093 | .fniv = gen_nand_pg_vec, | |
1094 | .fno = gen_helper_sve_nand_pppp, | |
1095 | .prefer_i64 = TCG_TARGET_REG_BITS == 64, | |
1096 | }; | |
1097 | if (a->s) { | |
1098 | return do_pppp_flags(s, a, &op); | |
1099 | } else { | |
1100 | return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg); | |
1101 | } | |
1102 | } | |
1103 | ||
9e18d7a6 RH |
1104 | /* |
1105 | *** SVE Predicate Misc Group | |
1106 | */ | |
1107 | ||
1108 | static bool trans_PTEST(DisasContext *s, arg_PTEST *a, uint32_t insn) | |
1109 | { | |
1110 | if (sve_access_check(s)) { | |
1111 | int nofs = pred_full_reg_offset(s, a->rn); | |
1112 | int gofs = pred_full_reg_offset(s, a->pg); | |
1113 | int words = DIV_ROUND_UP(pred_full_reg_size(s), 8); | |
1114 | ||
1115 | if (words == 1) { | |
1116 | TCGv_i64 pn = tcg_temp_new_i64(); | |
1117 | TCGv_i64 pg = tcg_temp_new_i64(); | |
1118 | ||
1119 | tcg_gen_ld_i64(pn, cpu_env, nofs); | |
1120 | tcg_gen_ld_i64(pg, cpu_env, gofs); | |
1121 | do_predtest1(pn, pg); | |
1122 | ||
1123 | tcg_temp_free_i64(pn); | |
1124 | tcg_temp_free_i64(pg); | |
1125 | } else { | |
1126 | do_predtest(s, nofs, gofs, words); | |
1127 | } | |
1128 | } | |
1129 | return true; | |
1130 | } | |
1131 | ||
028e2a7b RH |
1132 | /* See the ARM pseudocode DecodePredCount. */ |
1133 | static unsigned decode_pred_count(unsigned fullsz, int pattern, int esz) | |
1134 | { | |
1135 | unsigned elements = fullsz >> esz; | |
1136 | unsigned bound; | |
1137 | ||
1138 | switch (pattern) { | |
1139 | case 0x0: /* POW2 */ | |
1140 | return pow2floor(elements); | |
1141 | case 0x1: /* VL1 */ | |
1142 | case 0x2: /* VL2 */ | |
1143 | case 0x3: /* VL3 */ | |
1144 | case 0x4: /* VL4 */ | |
1145 | case 0x5: /* VL5 */ | |
1146 | case 0x6: /* VL6 */ | |
1147 | case 0x7: /* VL7 */ | |
1148 | case 0x8: /* VL8 */ | |
1149 | bound = pattern; | |
1150 | break; | |
1151 | case 0x9: /* VL16 */ | |
1152 | case 0xa: /* VL32 */ | |
1153 | case 0xb: /* VL64 */ | |
1154 | case 0xc: /* VL128 */ | |
1155 | case 0xd: /* VL256 */ | |
1156 | bound = 16 << (pattern - 9); | |
1157 | break; | |
1158 | case 0x1d: /* MUL4 */ | |
1159 | return elements - elements % 4; | |
1160 | case 0x1e: /* MUL3 */ | |
1161 | return elements - elements % 3; | |
1162 | case 0x1f: /* ALL */ | |
1163 | return elements; | |
1164 | default: /* #uimm5 */ | |
1165 | return 0; | |
1166 | } | |
1167 | return elements >= bound ? bound : 0; | |
1168 | } | |
1169 | ||
1170 | /* This handles all of the predicate initialization instructions, | |
1171 | * PTRUE, PFALSE, SETFFR. For PFALSE, we will have set PAT == 32 | |
1172 | * so that decode_pred_count returns 0. For SETFFR, we will have | |
1173 | * set RD == 16 == FFR. | |
1174 | */ | |
1175 | static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag) | |
1176 | { | |
1177 | if (!sve_access_check(s)) { | |
1178 | return true; | |
1179 | } | |
1180 | ||
1181 | unsigned fullsz = vec_full_reg_size(s); | |
1182 | unsigned ofs = pred_full_reg_offset(s, rd); | |
1183 | unsigned numelem, setsz, i; | |
1184 | uint64_t word, lastword; | |
1185 | TCGv_i64 t; | |
1186 | ||
1187 | numelem = decode_pred_count(fullsz, pat, esz); | |
1188 | ||
1189 | /* Determine what we must store into each bit, and how many. */ | |
1190 | if (numelem == 0) { | |
1191 | lastword = word = 0; | |
1192 | setsz = fullsz; | |
1193 | } else { | |
1194 | setsz = numelem << esz; | |
1195 | lastword = word = pred_esz_masks[esz]; | |
1196 | if (setsz % 64) { | |
1197 | lastword &= ~(-1ull << (setsz % 64)); | |
1198 | } | |
1199 | } | |
1200 | ||
1201 | t = tcg_temp_new_i64(); | |
1202 | if (fullsz <= 64) { | |
1203 | tcg_gen_movi_i64(t, lastword); | |
1204 | tcg_gen_st_i64(t, cpu_env, ofs); | |
1205 | goto done; | |
1206 | } | |
1207 | ||
1208 | if (word == lastword) { | |
1209 | unsigned maxsz = size_for_gvec(fullsz / 8); | |
1210 | unsigned oprsz = size_for_gvec(setsz / 8); | |
1211 | ||
1212 | if (oprsz * 8 == setsz) { | |
1213 | tcg_gen_gvec_dup64i(ofs, oprsz, maxsz, word); | |
1214 | goto done; | |
1215 | } | |
1216 | if (oprsz * 8 == setsz + 8) { | |
1217 | tcg_gen_gvec_dup64i(ofs, oprsz, maxsz, word); | |
1218 | tcg_gen_movi_i64(t, 0); | |
1219 | tcg_gen_st_i64(t, cpu_env, ofs + oprsz - 8); | |
1220 | goto done; | |
1221 | } | |
1222 | } | |
1223 | ||
1224 | setsz /= 8; | |
1225 | fullsz /= 8; | |
1226 | ||
1227 | tcg_gen_movi_i64(t, word); | |
1228 | for (i = 0; i < setsz; i += 8) { | |
1229 | tcg_gen_st_i64(t, cpu_env, ofs + i); | |
1230 | } | |
1231 | if (lastword != word) { | |
1232 | tcg_gen_movi_i64(t, lastword); | |
1233 | tcg_gen_st_i64(t, cpu_env, ofs + i); | |
1234 | i += 8; | |
1235 | } | |
1236 | if (i < fullsz) { | |
1237 | tcg_gen_movi_i64(t, 0); | |
1238 | for (; i < fullsz; i += 8) { | |
1239 | tcg_gen_st_i64(t, cpu_env, ofs + i); | |
1240 | } | |
1241 | } | |
1242 | ||
1243 | done: | |
1244 | tcg_temp_free_i64(t); | |
1245 | ||
1246 | /* PTRUES */ | |
1247 | if (setflag) { | |
1248 | tcg_gen_movi_i32(cpu_NF, -(word != 0)); | |
1249 | tcg_gen_movi_i32(cpu_CF, word == 0); | |
1250 | tcg_gen_movi_i32(cpu_VF, 0); | |
1251 | tcg_gen_mov_i32(cpu_ZF, cpu_NF); | |
1252 | } | |
1253 | return true; | |
1254 | } | |
1255 | ||
1256 | static bool trans_PTRUE(DisasContext *s, arg_PTRUE *a, uint32_t insn) | |
1257 | { | |
1258 | return do_predset(s, a->esz, a->rd, a->pat, a->s); | |
1259 | } | |
1260 | ||
1261 | static bool trans_SETFFR(DisasContext *s, arg_SETFFR *a, uint32_t insn) | |
1262 | { | |
1263 | /* Note pat == 31 is #all, to set all elements. */ | |
1264 | return do_predset(s, 0, FFR_PRED_NUM, 31, false); | |
1265 | } | |
1266 | ||
1267 | static bool trans_PFALSE(DisasContext *s, arg_PFALSE *a, uint32_t insn) | |
1268 | { | |
1269 | /* Note pat == 32 is #unimp, to set no elements. */ | |
1270 | return do_predset(s, 0, a->rd, 32, false); | |
1271 | } | |
1272 | ||
1273 | static bool trans_RDFFR_p(DisasContext *s, arg_RDFFR_p *a, uint32_t insn) | |
1274 | { | |
1275 | /* The path through do_pppp_flags is complicated enough to want to avoid | |
1276 | * duplication. Frob the arguments into the form of a predicated AND. | |
1277 | */ | |
1278 | arg_rprr_s alt_a = { | |
1279 | .rd = a->rd, .pg = a->pg, .s = a->s, | |
1280 | .rn = FFR_PRED_NUM, .rm = FFR_PRED_NUM, | |
1281 | }; | |
1282 | return trans_AND_pppp(s, &alt_a, insn); | |
1283 | } | |
1284 | ||
1285 | static bool trans_RDFFR(DisasContext *s, arg_RDFFR *a, uint32_t insn) | |
1286 | { | |
1287 | return do_mov_p(s, a->rd, FFR_PRED_NUM); | |
1288 | } | |
1289 | ||
1290 | static bool trans_WRFFR(DisasContext *s, arg_WRFFR *a, uint32_t insn) | |
1291 | { | |
1292 | return do_mov_p(s, FFR_PRED_NUM, a->rn); | |
1293 | } | |
1294 | ||
1295 | static bool do_pfirst_pnext(DisasContext *s, arg_rr_esz *a, | |
1296 | void (*gen_fn)(TCGv_i32, TCGv_ptr, | |
1297 | TCGv_ptr, TCGv_i32)) | |
1298 | { | |
1299 | if (!sve_access_check(s)) { | |
1300 | return true; | |
1301 | } | |
1302 | ||
1303 | TCGv_ptr t_pd = tcg_temp_new_ptr(); | |
1304 | TCGv_ptr t_pg = tcg_temp_new_ptr(); | |
1305 | TCGv_i32 t; | |
1306 | unsigned desc; | |
1307 | ||
1308 | desc = DIV_ROUND_UP(pred_full_reg_size(s), 8); | |
1309 | desc = deposit32(desc, SIMD_DATA_SHIFT, 2, a->esz); | |
1310 | ||
1311 | tcg_gen_addi_ptr(t_pd, cpu_env, pred_full_reg_offset(s, a->rd)); | |
1312 | tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->rn)); | |
1313 | t = tcg_const_i32(desc); | |
1314 | ||
1315 | gen_fn(t, t_pd, t_pg, t); | |
1316 | tcg_temp_free_ptr(t_pd); | |
1317 | tcg_temp_free_ptr(t_pg); | |
1318 | ||
1319 | do_pred_flags(t); | |
1320 | tcg_temp_free_i32(t); | |
1321 | return true; | |
1322 | } | |
1323 | ||
1324 | static bool trans_PFIRST(DisasContext *s, arg_rr_esz *a, uint32_t insn) | |
1325 | { | |
1326 | return do_pfirst_pnext(s, a, gen_helper_sve_pfirst); | |
1327 | } | |
1328 | ||
1329 | static bool trans_PNEXT(DisasContext *s, arg_rr_esz *a, uint32_t insn) | |
1330 | { | |
1331 | return do_pfirst_pnext(s, a, gen_helper_sve_pnext); | |
1332 | } | |
1333 | ||
d1822297 RH |
1334 | /* |
1335 | *** SVE Memory - 32-bit Gather and Unsized Contiguous Group | |
1336 | */ | |
1337 | ||
1338 | /* Subroutine loading a vector register at VOFS of LEN bytes. | |
1339 | * The load should begin at the address Rn + IMM. | |
1340 | */ | |
1341 | ||
1342 | static void do_ldr(DisasContext *s, uint32_t vofs, uint32_t len, | |
1343 | int rn, int imm) | |
1344 | { | |
1345 | uint32_t len_align = QEMU_ALIGN_DOWN(len, 8); | |
1346 | uint32_t len_remain = len % 8; | |
1347 | uint32_t nparts = len / 8 + ctpop8(len_remain); | |
1348 | int midx = get_mem_index(s); | |
1349 | TCGv_i64 addr, t0, t1; | |
1350 | ||
1351 | addr = tcg_temp_new_i64(); | |
1352 | t0 = tcg_temp_new_i64(); | |
1353 | ||
1354 | /* Note that unpredicated load/store of vector/predicate registers | |
1355 | * are defined as a stream of bytes, which equates to little-endian | |
1356 | * operations on larger quantities. There is no nice way to force | |
1357 | * a little-endian load for aarch64_be-linux-user out of line. | |
1358 | * | |
1359 | * Attempt to keep code expansion to a minimum by limiting the | |
1360 | * amount of unrolling done. | |
1361 | */ | |
1362 | if (nparts <= 4) { | |
1363 | int i; | |
1364 | ||
1365 | for (i = 0; i < len_align; i += 8) { | |
1366 | tcg_gen_addi_i64(addr, cpu_reg_sp(s, rn), imm + i); | |
1367 | tcg_gen_qemu_ld_i64(t0, addr, midx, MO_LEQ); | |
1368 | tcg_gen_st_i64(t0, cpu_env, vofs + i); | |
1369 | } | |
1370 | } else { | |
1371 | TCGLabel *loop = gen_new_label(); | |
1372 | TCGv_ptr tp, i = tcg_const_local_ptr(0); | |
1373 | ||
1374 | gen_set_label(loop); | |
1375 | ||
1376 | /* Minimize the number of local temps that must be re-read from | |
1377 | * the stack each iteration. Instead, re-compute values other | |
1378 | * than the loop counter. | |
1379 | */ | |
1380 | tp = tcg_temp_new_ptr(); | |
1381 | tcg_gen_addi_ptr(tp, i, imm); | |
1382 | tcg_gen_extu_ptr_i64(addr, tp); | |
1383 | tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, rn)); | |
1384 | ||
1385 | tcg_gen_qemu_ld_i64(t0, addr, midx, MO_LEQ); | |
1386 | ||
1387 | tcg_gen_add_ptr(tp, cpu_env, i); | |
1388 | tcg_gen_addi_ptr(i, i, 8); | |
1389 | tcg_gen_st_i64(t0, tp, vofs); | |
1390 | tcg_temp_free_ptr(tp); | |
1391 | ||
1392 | tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop); | |
1393 | tcg_temp_free_ptr(i); | |
1394 | } | |
1395 | ||
1396 | /* Predicate register loads can be any multiple of 2. | |
1397 | * Note that we still store the entire 64-bit unit into cpu_env. | |
1398 | */ | |
1399 | if (len_remain) { | |
1400 | tcg_gen_addi_i64(addr, cpu_reg_sp(s, rn), imm + len_align); | |
1401 | ||
1402 | switch (len_remain) { | |
1403 | case 2: | |
1404 | case 4: | |
1405 | case 8: | |
1406 | tcg_gen_qemu_ld_i64(t0, addr, midx, MO_LE | ctz32(len_remain)); | |
1407 | break; | |
1408 | ||
1409 | case 6: | |
1410 | t1 = tcg_temp_new_i64(); | |
1411 | tcg_gen_qemu_ld_i64(t0, addr, midx, MO_LEUL); | |
1412 | tcg_gen_addi_i64(addr, addr, 4); | |
1413 | tcg_gen_qemu_ld_i64(t1, addr, midx, MO_LEUW); | |
1414 | tcg_gen_deposit_i64(t0, t0, t1, 32, 32); | |
1415 | tcg_temp_free_i64(t1); | |
1416 | break; | |
1417 | ||
1418 | default: | |
1419 | g_assert_not_reached(); | |
1420 | } | |
1421 | tcg_gen_st_i64(t0, cpu_env, vofs + len_align); | |
1422 | } | |
1423 | tcg_temp_free_i64(addr); | |
1424 | tcg_temp_free_i64(t0); | |
1425 | } | |
1426 | ||
1427 | static bool trans_LDR_zri(DisasContext *s, arg_rri *a, uint32_t insn) | |
1428 | { | |
1429 | if (sve_access_check(s)) { | |
1430 | int size = vec_full_reg_size(s); | |
1431 | int off = vec_full_reg_offset(s, a->rd); | |
1432 | do_ldr(s, off, size, a->rn, a->imm * size); | |
1433 | } | |
1434 | return true; | |
1435 | } | |
1436 | ||
1437 | static bool trans_LDR_pri(DisasContext *s, arg_rri *a, uint32_t insn) | |
1438 | { | |
1439 | if (sve_access_check(s)) { | |
1440 | int size = pred_full_reg_size(s); | |
1441 | int off = pred_full_reg_offset(s, a->rd); | |
1442 | do_ldr(s, off, size, a->rn, a->imm * size); | |
1443 | } | |
1444 | return true; | |
1445 | } |