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qom/cpu: Simplify how CPUClass:cpu_dump_state() prints
[mirror_qemu.git] / target / cris / translate.c
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8170028d
TS		 1/*
2 * CRIS emulation for qemu: main translation routines.
3 *
05ba7d5f 4 * Copyright (c) 2008 AXIS Communications AB
8170028d
TS		 5 * Written by Edgar E. Iglesias.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
8167ee88 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
8170028d
TS		 19 */
20
b41f7df0
EI		 21/*
22 * FIXME:
cf1d97f0 23 * The condition code translation is in need of attention.
b41f7df0
EI		 24 */
25
23b0d7df 26#include "qemu/osdep.h"
8170028d 27#include "cpu.h"
76cad711 28#include "disas/disas.h"
63c91552 29#include "exec/exec-all.h"
57fec1fe 30#include "tcg-op.h"
2ef6175a 31#include "exec/helper-proto.h"
52819664 32#include "mmu.h"
f08b6170 33#include "exec/cpu_ldst.h"
77fc6f5e 34#include "exec/translator.h"
8170028d 35#include "crisv32-decode.h"
90c84c56 36#include "qemu/qemu-print.h"
8170028d 37
2ef6175a 38#include "exec/helper-gen.h"
a7812ae4 39
a7e30d84 40#include "trace-tcg.h"
508127e2 41#include "exec/log.h"
a7e30d84
LV		 42
43
8170028d
TS		 44#define DISAS_CRIS 0
45#if DISAS_CRIS
93fcfe39 46# define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
8170028d 47#else
d12d51d5 48# define LOG_DIS(...) do { } while (0)
8170028d
TS		 49#endif
50
b41f7df0 51#define D(x)
8170028d
TS		 52#define BUG() (gen_BUG(dc, __FILE__, __LINE__))
53#define BUG_ON(x) ({if (x) BUG();})
54
77fc6f5e
LV		 55/* is_jmp field values */
56#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
57#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */
58#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */
59#define DISAS_SWI DISAS_TARGET_3
4f400ab5 60
8170028d
TS		 61/* Used by the decoder. */
62#define EXTRACT_FIELD(src, start, end) \
63 (((src) >> start) & ((1 << (end - start + 1)) - 1))
64
65#define CC_MASK_NZ 0xc
66#define CC_MASK_NZV 0xe
67#define CC_MASK_NZVC 0xf
68#define CC_MASK_RNZV 0x10e
69
9b32fbf8
EI		 70static TCGv cpu_R[16];
71static TCGv cpu_PR[16];
72static TCGv cc_x;
73static TCGv cc_src;
74static TCGv cc_dest;
75static TCGv cc_result;
76static TCGv cc_op;
77static TCGv cc_size;
78static TCGv cc_mask;
79
80static TCGv env_btaken;
81static TCGv env_btarget;
82static TCGv env_pc;
b41f7df0 83
022c62cb 84#include "exec/gen-icount.h"
2e70f6ef 85
8170028d
TS		 86/* This is the state at translation time. */
87typedef struct DisasContext {
0dd106c5 88 CRISCPU *cpu;
7b5eff4d 89 target_ulong pc, ppc;
8170028d 90
7b5eff4d 91 /* Decoder. */
cf7e0c80 92 unsigned int (*decoder)(CPUCRISState *env, struct DisasContext *dc);
7b5eff4d
EV		 93 uint32_t ir;
94 uint32_t opcode;
95 unsigned int op1;
96 unsigned int op2;
97 unsigned int zsize, zzsize;
98 unsigned int mode;
99 unsigned int postinc;
100
101 unsigned int size;
102 unsigned int src;
103 unsigned int dst;
104 unsigned int cond;
105
106 int update_cc;
107 int cc_op;
108 int cc_size;
109 uint32_t cc_mask;
110
111 int cc_size_uptodate; /* -1 invalid or last written value. */
112
67cc32eb
VL		 113 int cc_x_uptodate; /* 1 - ccs, 2 - known | X_FLAG. 0 not up-to-date. */
114 int flags_uptodate; /* Whether or not $ccs is up-to-date. */
115 int flagx_known; /* Whether or not flags_x has the x flag known at
7b5eff4d
EV		 116 translation time. */
117 int flags_x;
118
119 int clear_x; /* Clear x after this insn? */
120 int clear_prefix; /* Clear prefix after this insn? */
121 int clear_locked_irq; /* Clear the irq lockout. */
122 int cpustate_changed;
123 unsigned int tb_flags; /* tb dependent flags. */
124 int is_jmp;
8170028d 125
5cabc5cc
EI		 126#define JMP_NOJMP 0
127#define JMP_DIRECT 1
128#define JMP_DIRECT_CC 2
129#define JMP_INDIRECT 3
7b5eff4d
EV		 130 int jmp; /* 0=nojmp, 1=direct, 2=indirect. */
131 uint32_t jmp_pc;
2a44f7f1 132
7b5eff4d 133 int delayed_branch;
8170028d 134
7b5eff4d
EV		 135 struct TranslationBlock *tb;
136 int singlestep_enabled;
8170028d
TS		 137} DisasContext;
138
7ccfb2eb 139static void gen_BUG(DisasContext *dc, const char *file, int line)
8170028d 140{
ba3fa397 141 cpu_abort(CPU(dc->cpu), "%s:%d pc=%x\n", file, line, dc->pc);
8170028d
TS		 142}
143
17bc37b7 144static const char *regnames_v32[] =
a825e703 145{
7b5eff4d
EV		 146 "$r0", "$r1", "$r2", "$r3",
147 "$r4", "$r5", "$r6", "$r7",
148 "$r8", "$r9", "$r10", "$r11",
149 "$r12", "$r13", "$sp", "$acr",
a825e703 150};
17bc37b7 151static const char *pregnames_v32[] =
a825e703 152{
7b5eff4d
EV		 153 "$bz", "$vr", "$pid", "$srs",
154 "$wz", "$exs", "$eda", "$mof",
155 "$dz", "$ebp", "$erp", "$srp",
156 "$nrp", "$ccs", "$usp", "$spc",
a825e703
EI		 157};
158
05ba7d5f 159/* We need this table to handle preg-moves with implicit width. */
9b32fbf8 160static int preg_sizes[] = {
7b5eff4d
EV		 161 1, /* bz. */
162 1, /* vr. */
163 4, /* pid. */
164 1, /* srs. */
165 2, /* wz. */
166 4, 4, 4,
167 4, 4, 4, 4,
168 4, 4, 4, 4,
05ba7d5f
EI		 169};
170
171#define t_gen_mov_TN_env(tn, member) \
37654d9e 172 tcg_gen_ld_tl(tn, cpu_env, offsetof(CPUCRISState, member))
05ba7d5f 173#define t_gen_mov_env_TN(member, tn) \
37654d9e 174 tcg_gen_st_tl(tn, cpu_env, offsetof(CPUCRISState, member))
05ba7d5f
EI		 175
176static inline void t_gen_mov_TN_preg(TCGv tn, int r)
177{
fae38221 178 assert(r >= 0 && r <= 15);
7b5eff4d
EV		 179 if (r == PR_BZ || r == PR_WZ || r == PR_DZ) {
180 tcg_gen_mov_tl(tn, tcg_const_tl(0));
181 } else if (r == PR_VR) {
182 tcg_gen_mov_tl(tn, tcg_const_tl(32));
183 } else {
184 tcg_gen_mov_tl(tn, cpu_PR[r]);
185 }
05ba7d5f 186}
cf1d97f0 187static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
05ba7d5f 188{
fae38221 189 assert(r >= 0 && r <= 15);
7b5eff4d
EV		 190 if (r == PR_BZ || r == PR_WZ || r == PR_DZ) {
191 return;
192 } else if (r == PR_SRS) {
193 tcg_gen_andi_tl(cpu_PR[r], tn, 3);
194 } else {
195 if (r == PR_PID) {
196 gen_helper_tlb_flush_pid(cpu_env, tn);
197 }
198 if (dc->tb_flags & S_FLAG && r == PR_SPC) {
199 gen_helper_spc_write(cpu_env, tn);
200 } else if (r == PR_CCS) {
201 dc->cpustate_changed = 1;
202 }
203 tcg_gen_mov_tl(cpu_PR[r], tn);
204 }
05ba7d5f
EI		 205}
206
1884533c
EI		 207/* Sign extend at translation time. */
208static int sign_extend(unsigned int val, unsigned int width)
209{
7b5eff4d 210 int sval;
1884533c 211
7b5eff4d
EV		 212 /* LSL. */
213 val <<= 31 - width;
214 sval = val;
215 /* ASR. */
216 sval >>= 31 - width;
217 return sval;
1884533c
EI		 218}
219
cf7e0c80 220static int cris_fetch(CPUCRISState *env, DisasContext *dc, uint32_t addr,
7b5eff4d
EV		 221 unsigned int size, unsigned int sign)
222{
223 int r;
224
225 switch (size) {
226 case 4:
227 {
228 r = cpu_ldl_code(env, addr);
229 break;
230 }
231 case 2:
232 {
233 if (sign) {
234 r = cpu_ldsw_code(env, addr);
235 } else {
236 r = cpu_lduw_code(env, addr);
237 }
238 break;
239 }
240 case 1:
241 {
242 if (sign) {
243 r = cpu_ldsb_code(env, addr);
244 } else {
245 r = cpu_ldub_code(env, addr);
246 }
247 break;
248 }
249 default:
0dd106c5 250 cpu_abort(CPU(dc->cpu), "Invalid fetch size %d\n", size);
7b5eff4d
EV		 251 break;
252 }
253 return r;
7de141cb
EI		 254}
255
40e9eddd
EI		 256static void cris_lock_irq(DisasContext *dc)
257{
7b5eff4d
EV		 258 dc->clear_locked_irq = 0;
259 t_gen_mov_env_TN(locked_irq, tcg_const_tl(1));
40e9eddd
EI		 260}
261
dceaf394 262static inline void t_gen_raise_exception(uint32_t index)
05ba7d5f 263{
a7812ae4 264 TCGv_i32 tmp = tcg_const_i32(index);
febc9920 265 gen_helper_raise_exception(cpu_env, tmp);
a7812ae4 266 tcg_temp_free_i32(tmp);
05ba7d5f
EI		 267}
268
269static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
270{
7b5eff4d 271 TCGv t0, t_31;
05ba7d5f 272
7b5eff4d
EV		 273 t0 = tcg_temp_new();
274 t_31 = tcg_const_tl(31);
275 tcg_gen_shl_tl(d, a, b);
7dcfb089 276
7b5eff4d
EV		 277 tcg_gen_sub_tl(t0, t_31, b);
278 tcg_gen_sar_tl(t0, t0, t_31);
279 tcg_gen_and_tl(t0, t0, d);
280 tcg_gen_xor_tl(d, d, t0);
281 tcg_temp_free(t0);
282 tcg_temp_free(t_31);
05ba7d5f
EI		 283}
284
285static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
286{
7b5eff4d 287 TCGv t0, t_31;
05ba7d5f 288
7b5eff4d
EV		 289 t0 = tcg_temp_new();
290 t_31 = tcg_temp_new();
291 tcg_gen_shr_tl(d, a, b);
7dcfb089 292
7b5eff4d
EV		 293 tcg_gen_movi_tl(t_31, 31);
294 tcg_gen_sub_tl(t0, t_31, b);
295 tcg_gen_sar_tl(t0, t0, t_31);
296 tcg_gen_and_tl(t0, t0, d);
297 tcg_gen_xor_tl(d, d, t0);
298 tcg_temp_free(t0);
299 tcg_temp_free(t_31);
05ba7d5f
EI		 300}
301
302static void t_gen_asr(TCGv d, TCGv a, TCGv b)
303{
7b5eff4d 304 TCGv t0, t_31;
05ba7d5f 305
7b5eff4d
EV		 306 t0 = tcg_temp_new();
307 t_31 = tcg_temp_new();
308 tcg_gen_sar_tl(d, a, b);
7dcfb089 309
7b5eff4d
EV		 310 tcg_gen_movi_tl(t_31, 31);
311 tcg_gen_sub_tl(t0, t_31, b);
312 tcg_gen_sar_tl(t0, t0, t_31);
313 tcg_gen_or_tl(d, d, t0);
314 tcg_temp_free(t0);
315 tcg_temp_free(t_31);
05ba7d5f
EI		 316}
317
30abcfc7 318static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b)
aae6b32a 319{
88174019 320 TCGv t = tcg_temp_new();
aae6b32a 321
7b5eff4d
EV		 322 /*
323 * d <<= 1
324 * if (d >= s)
325 * d -= s;
326 */
327 tcg_gen_shli_tl(d, a, 1);
88174019
RH		 328 tcg_gen_sub_tl(t, d, b);
329 tcg_gen_movcond_tl(TCG_COND_GEU, d, d, b, t, d);
330 tcg_temp_free(t);
aae6b32a
EI		 331}
332
40e9eddd
EI		 333static void t_gen_cris_mstep(TCGv d, TCGv a, TCGv b, TCGv ccs)
334{
7b5eff4d 335 TCGv t;
40e9eddd 336
7b5eff4d
EV		 337 /*
338 * d <<= 1
339 * if (n)
340 * d += s;
341 */
342 t = tcg_temp_new();
343 tcg_gen_shli_tl(d, a, 1);
344 tcg_gen_shli_tl(t, ccs, 31 - 3);
345 tcg_gen_sari_tl(t, t, 31);
346 tcg_gen_and_tl(t, t, b);
347 tcg_gen_add_tl(d, d, t);
348 tcg_temp_free(t);
40e9eddd
EI		 349}
350
3157a0a9
EI		 351/* Extended arithmetics on CRIS. */
352static inline void t_gen_add_flag(TCGv d, int flag)
353{
7b5eff4d 354 TCGv c;
3157a0a9 355
7b5eff4d
EV		 356 c = tcg_temp_new();
357 t_gen_mov_TN_preg(c, PR_CCS);
358 /* Propagate carry into d. */
359 tcg_gen_andi_tl(c, c, 1 << flag);
360 if (flag) {
361 tcg_gen_shri_tl(c, c, flag);
362 }
363 tcg_gen_add_tl(d, d, c);
364 tcg_temp_free(c);
3157a0a9
EI		 365}
366
30abcfc7 367static inline void t_gen_addx_carry(DisasContext *dc, TCGv d)
3157a0a9 368{
7b5eff4d
EV		 369 if (dc->flagx_known) {
370 if (dc->flags_x) {
371 TCGv c;
30abcfc7 372
7b5eff4d
EV		 373 c = tcg_temp_new();
374 t_gen_mov_TN_preg(c, PR_CCS);
375 /* C flag is already at bit 0. */
376 tcg_gen_andi_tl(c, c, C_FLAG);
377 tcg_gen_add_tl(d, d, c);
378 tcg_temp_free(c);
379 }
380 } else {
381 TCGv x, c;
382
383 x = tcg_temp_new();
384 c = tcg_temp_new();
385 t_gen_mov_TN_preg(x, PR_CCS);
386 tcg_gen_mov_tl(c, x);
387
388 /* Propagate carry into d if X is set. Branch free. */
389 tcg_gen_andi_tl(c, c, C_FLAG);
390 tcg_gen_andi_tl(x, x, X_FLAG);
391 tcg_gen_shri_tl(x, x, 4);
392
393 tcg_gen_and_tl(x, x, c);
394 tcg_gen_add_tl(d, d, x);
395 tcg_temp_free(x);
396 tcg_temp_free(c);
397 }
3157a0a9
EI		 398}
399
a39f8f3a 400static inline void t_gen_subx_carry(DisasContext *dc, TCGv d)
3157a0a9 401{
7b5eff4d
EV		 402 if (dc->flagx_known) {
403 if (dc->flags_x) {
404 TCGv c;
30abcfc7 405
7b5eff4d
EV		 406 c = tcg_temp_new();
407 t_gen_mov_TN_preg(c, PR_CCS);
408 /* C flag is already at bit 0. */
409 tcg_gen_andi_tl(c, c, C_FLAG);
410 tcg_gen_sub_tl(d, d, c);
411 tcg_temp_free(c);
412 }
413 } else {
414 TCGv x, c;
415
416 x = tcg_temp_new();
417 c = tcg_temp_new();
418 t_gen_mov_TN_preg(x, PR_CCS);
419 tcg_gen_mov_tl(c, x);
420
421 /* Propagate carry into d if X is set. Branch free. */
422 tcg_gen_andi_tl(c, c, C_FLAG);
423 tcg_gen_andi_tl(x, x, X_FLAG);
424 tcg_gen_shri_tl(x, x, 4);
425
426 tcg_gen_and_tl(x, x, c);
427 tcg_gen_sub_tl(d, d, x);
428 tcg_temp_free(x);
429 tcg_temp_free(c);
430 }
3157a0a9
EI		 431}
432
433/* Swap the two bytes within each half word of the s operand.
434 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
435static inline void t_gen_swapb(TCGv d, TCGv s)
436{
7b5eff4d 437 TCGv t, org_s;
3157a0a9 438
7b5eff4d
EV		 439 t = tcg_temp_new();
440 org_s = tcg_temp_new();
3157a0a9 441
7b5eff4d
EV		 442 /* d and s may refer to the same object. */
443 tcg_gen_mov_tl(org_s, s);
444 tcg_gen_shli_tl(t, org_s, 8);
445 tcg_gen_andi_tl(d, t, 0xff00ff00);
446 tcg_gen_shri_tl(t, org_s, 8);
447 tcg_gen_andi_tl(t, t, 0x00ff00ff);
448 tcg_gen_or_tl(d, d, t);
449 tcg_temp_free(t);
450 tcg_temp_free(org_s);
3157a0a9
EI		 451}
452
453/* Swap the halfwords of the s operand. */
454static inline void t_gen_swapw(TCGv d, TCGv s)
455{
7b5eff4d
EV		 456 TCGv t;
457 /* d and s refer the same object. */
458 t = tcg_temp_new();
459 tcg_gen_mov_tl(t, s);
460 tcg_gen_shli_tl(d, t, 16);
461 tcg_gen_shri_tl(t, t, 16);
462 tcg_gen_or_tl(d, d, t);
463 tcg_temp_free(t);
3157a0a9
EI		 464}
465
466/* Reverse the within each byte.
467 T0 = (((T0 << 7) & 0x80808080) |
468 ((T0 << 5) & 0x40404040) |
469 ((T0 << 3) & 0x20202020) |
470 ((T0 << 1) & 0x10101010) |
471 ((T0 >> 1) & 0x08080808) |
472 ((T0 >> 3) & 0x04040404) |
473 ((T0 >> 5) & 0x02020202) |
474 ((T0 >> 7) & 0x01010101));
475 */
476static inline void t_gen_swapr(TCGv d, TCGv s)
477{
7b5eff4d
EV		 478 struct {
479 int shift; /* LSL when positive, LSR when negative. */
480 uint32_t mask;
481 } bitrev[] = {
482 {7, 0x80808080},
483 {5, 0x40404040},
484 {3, 0x20202020},
485 {1, 0x10101010},
486 {-1, 0x08080808},
487 {-3, 0x04040404},
488 {-5, 0x02020202},
489 {-7, 0x01010101}
490 };
491 int i;
492 TCGv t, org_s;
493
494 /* d and s refer the same object. */
495 t = tcg_temp_new();
496 org_s = tcg_temp_new();
497 tcg_gen_mov_tl(org_s, s);
498
499 tcg_gen_shli_tl(t, org_s, bitrev[0].shift);
500 tcg_gen_andi_tl(d, t, bitrev[0].mask);
501 for (i = 1; i < ARRAY_SIZE(bitrev); i++) {
502 if (bitrev[i].shift >= 0) {
503 tcg_gen_shli_tl(t, org_s, bitrev[i].shift);
504 } else {
505 tcg_gen_shri_tl(t, org_s, -bitrev[i].shift);
506 }
507 tcg_gen_andi_tl(t, t, bitrev[i].mask);
508 tcg_gen_or_tl(d, d, t);
509 }
510 tcg_temp_free(t);
511 tcg_temp_free(org_s);
3157a0a9
EI		 512}
513
cf1d97f0 514static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false)
17ac9754 515{
42a268c2 516 TCGLabel *l1 = gen_new_label();
17ac9754 517
7b5eff4d
EV		 518 /* Conditional jmp. */
519 tcg_gen_mov_tl(env_pc, pc_false);
520 tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);
521 tcg_gen_mov_tl(env_pc, pc_true);
522 gen_set_label(l1);
17ac9754
EI		 523}
524
90aa39a1 525static inline bool use_goto_tb(DisasContext *dc, target_ulong dest)
8170028d 526{
90aa39a1
SF		 527#ifndef CONFIG_USER_ONLY
528 return (dc->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) ||
529 (dc->ppc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
530#else
531 return true;
532#endif
533}
5b053a4a 534
90aa39a1
SF		 535static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
536{
537 if (use_goto_tb(dc, dest)) {
7b5eff4d
EV		 538 tcg_gen_goto_tb(n);
539 tcg_gen_movi_tl(env_pc, dest);
07ea28b4 540 tcg_gen_exit_tb(dc->tb, n);
7b5eff4d
EV		 541 } else {
542 tcg_gen_movi_tl(env_pc, dest);
07ea28b4 543 tcg_gen_exit_tb(NULL, 0);
7b5eff4d 544 }
8170028d
TS		 545}
546
05ba7d5f
EI		 547static inline void cris_clear_x_flag(DisasContext *dc)
548{
7b5eff4d
EV		 549 if (dc->flagx_known && dc->flags_x) {
550 dc->flags_uptodate = 0;
551 }
2a44f7f1 552
7b5eff4d
EV		 553 dc->flagx_known = 1;
554 dc->flags_x = 0;
05ba7d5f
EI		 555}
556
30abcfc7 557static void cris_flush_cc_state(DisasContext *dc)
8170028d 558{
7b5eff4d
EV		 559 if (dc->cc_size_uptodate != dc->cc_size) {
560 tcg_gen_movi_tl(cc_size, dc->cc_size);
561 dc->cc_size_uptodate = dc->cc_size;
562 }
563 tcg_gen_movi_tl(cc_op, dc->cc_op);
564 tcg_gen_movi_tl(cc_mask, dc->cc_mask);
30abcfc7
EI		 565}
566
567static void cris_evaluate_flags(DisasContext *dc)
568{
7b5eff4d
EV		 569 if (dc->flags_uptodate) {
570 return;
571 }
572
573 cris_flush_cc_state(dc);
574
575 switch (dc->cc_op) {
576 case CC_OP_MCP:
577 gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS], cpu_env,
578 cpu_PR[PR_CCS], cc_src,
579 cc_dest, cc_result);
580 break;
581 case CC_OP_MULS:
582 gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS], cpu_env,
583 cpu_PR[PR_CCS], cc_result,
584 cpu_PR[PR_MOF]);
585 break;
586 case CC_OP_MULU:
587 gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS], cpu_env,
588 cpu_PR[PR_CCS], cc_result,
589 cpu_PR[PR_MOF]);
590 break;
591 case CC_OP_MOVE:
592 case CC_OP_AND:
593 case CC_OP_OR:
594 case CC_OP_XOR:
595 case CC_OP_ASR:
596 case CC_OP_LSR:
597 case CC_OP_LSL:
598 switch (dc->cc_size) {
599 case 4:
600 gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS],
601 cpu_env, cpu_PR[PR_CCS], cc_result);
602 break;
603 case 2:
604 gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS],
605 cpu_env, cpu_PR[PR_CCS], cc_result);
606 break;
607 default:
608 gen_helper_evaluate_flags(cpu_env);
609 break;
610 }
611 break;
612 case CC_OP_FLAGS:
613 /* live. */
614 break;
615 case CC_OP_SUB:
616 case CC_OP_CMP:
617 if (dc->cc_size == 4) {
618 gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS], cpu_env,
619 cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
620 } else {
621 gen_helper_evaluate_flags(cpu_env);
622 }
623
624 break;
625 default:
626 switch (dc->cc_size) {
627 case 4:
628 gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS], cpu_env,
629 cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
630 break;
631 default:
632 gen_helper_evaluate_flags(cpu_env);
633 break;
6231868b 634 }
7b5eff4d
EV		 635 break;
636 }
637
638 if (dc->flagx_known) {
639 if (dc->flags_x) {
640 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], X_FLAG);
641 } else if (dc->cc_op == CC_OP_FLAGS) {
642 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~X_FLAG);
643 }
644 }
645 dc->flags_uptodate = 1;
8170028d
TS		 646}
647
648static void cris_cc_mask(DisasContext *dc, unsigned int mask)
649{
7b5eff4d 650 uint32_t ovl;
8170028d 651
7b5eff4d
EV		 652 if (!mask) {
653 dc->update_cc = 0;
654 return;
655 }
2a44f7f1 656
7b5eff4d
EV		 657 /* Check if we need to evaluate the condition codes due to
658 CC overlaying. */
659 ovl = (dc->cc_mask ^ mask) & ~mask;
660 if (ovl) {
661 /* TODO: optimize this case. It trigs all the time. */
662 cris_evaluate_flags(dc);
663 }
664 dc->cc_mask = mask;
665 dc->update_cc = 1;
8170028d
TS		 666}
667
b41f7df0 668static void cris_update_cc_op(DisasContext *dc, int op, int size)
8170028d 669{
7b5eff4d
EV		 670 dc->cc_op = op;
671 dc->cc_size = size;
672 dc->flags_uptodate = 0;
8170028d
TS		 673}
674
30abcfc7
EI		 675static inline void cris_update_cc_x(DisasContext *dc)
676{
7b5eff4d
EV		 677 /* Save the x flag state at the time of the cc snapshot. */
678 if (dc->flagx_known) {
679 if (dc->cc_x_uptodate == (2 | dc->flags_x)) {
680 return;
681 }
682 tcg_gen_movi_tl(cc_x, dc->flags_x);
683 dc->cc_x_uptodate = 2 | dc->flags_x;
684 } else {
685 tcg_gen_andi_tl(cc_x, cpu_PR[PR_CCS], X_FLAG);
686 dc->cc_x_uptodate = 1;
687 }
30abcfc7
EI		 688}
689
690/* Update cc prior to executing ALU op. Needs source operands untouched. */
691static void cris_pre_alu_update_cc(DisasContext *dc, int op,
7b5eff4d
EV		 692 TCGv dst, TCGv src, int size)
693{
694 if (dc->update_cc) {
695 cris_update_cc_op(dc, op, size);
696 tcg_gen_mov_tl(cc_src, src);
697
698 if (op != CC_OP_MOVE
699 && op != CC_OP_AND
700 && op != CC_OP_OR
701 && op != CC_OP_XOR
702 && op != CC_OP_ASR
703 && op != CC_OP_LSR
704 && op != CC_OP_LSL) {
705 tcg_gen_mov_tl(cc_dest, dst);
706 }
30abcfc7 707
7b5eff4d
EV		 708 cris_update_cc_x(dc);
709 }
30abcfc7 710}
3157a0a9 711
30abcfc7
EI		 712/* Update cc after executing ALU op. needs the result. */
713static inline void cris_update_result(DisasContext *dc, TCGv res)
714{
7b5eff4d
EV		 715 if (dc->update_cc) {
716 tcg_gen_mov_tl(cc_result, res);
717 }
30abcfc7 718}
8170028d 719
30abcfc7
EI		 720/* Returns one if the write back stage should execute. */
721static void cris_alu_op_exec(DisasContext *dc, int op,
7b5eff4d
EV		 722 TCGv dst, TCGv a, TCGv b, int size)
723{
724 /* Emit the ALU insns. */
725 switch (op) {
726 case CC_OP_ADD:
727 tcg_gen_add_tl(dst, a, b);
728 /* Extended arithmetics. */
729 t_gen_addx_carry(dc, dst);
730 break;
731 case CC_OP_ADDC:
732 tcg_gen_add_tl(dst, a, b);
733 t_gen_add_flag(dst, 0); /* C_FLAG. */
734 break;
735 case CC_OP_MCP:
736 tcg_gen_add_tl(dst, a, b);
737 t_gen_add_flag(dst, 8); /* R_FLAG. */
738 break;
739 case CC_OP_SUB:
740 tcg_gen_sub_tl(dst, a, b);
741 /* Extended arithmetics. */
742 t_gen_subx_carry(dc, dst);
743 break;
744 case CC_OP_MOVE:
745 tcg_gen_mov_tl(dst, b);
746 break;
747 case CC_OP_OR:
748 tcg_gen_or_tl(dst, a, b);
749 break;
750 case CC_OP_AND:
751 tcg_gen_and_tl(dst, a, b);
752 break;
753 case CC_OP_XOR:
754 tcg_gen_xor_tl(dst, a, b);
755 break;
756 case CC_OP_LSL:
757 t_gen_lsl(dst, a, b);
758 break;
759 case CC_OP_LSR:
760 t_gen_lsr(dst, a, b);
761 break;
762 case CC_OP_ASR:
763 t_gen_asr(dst, a, b);
764 break;
765 case CC_OP_NEG:
766 tcg_gen_neg_tl(dst, b);
767 /* Extended arithmetics. */
768 t_gen_subx_carry(dc, dst);
769 break;
770 case CC_OP_LZ:
272694a2 771 tcg_gen_clzi_tl(dst, b, TARGET_LONG_BITS);
7b5eff4d
EV		 772 break;
773 case CC_OP_MULS:
bf45f971 774 tcg_gen_muls2_tl(dst, cpu_PR[PR_MOF], a, b);
7b5eff4d
EV		 775 break;
776 case CC_OP_MULU:
bf45f971 777 tcg_gen_mulu2_tl(dst, cpu_PR[PR_MOF], a, b);
7b5eff4d
EV		 778 break;
779 case CC_OP_DSTEP:
780 t_gen_cris_dstep(dst, a, b);
781 break;
782 case CC_OP_MSTEP:
783 t_gen_cris_mstep(dst, a, b, cpu_PR[PR_CCS]);
784 break;
785 case CC_OP_BOUND:
88174019 786 tcg_gen_movcond_tl(TCG_COND_LEU, dst, a, b, a, b);
7b5eff4d
EV		 787 break;
788 case CC_OP_CMP:
789 tcg_gen_sub_tl(dst, a, b);
790 /* Extended arithmetics. */
791 t_gen_subx_carry(dc, dst);
792 break;
793 default:
79e8ed35 794 qemu_log_mask(LOG_GUEST_ERROR, "illegal ALU op.\n");
7b5eff4d
EV		 795 BUG();
796 break;
797 }
798
799 if (size == 1) {
800 tcg_gen_andi_tl(dst, dst, 0xff);
801 } else if (size == 2) {
802 tcg_gen_andi_tl(dst, dst, 0xffff);
803 }
30abcfc7
EI		 804}
805
806static void cris_alu(DisasContext *dc, int op,
7b5eff4d 807 TCGv d, TCGv op_a, TCGv op_b, int size)
30abcfc7 808{
7b5eff4d
EV		 809 TCGv tmp;
810 int writeback;
30abcfc7 811
7b5eff4d 812 writeback = 1;
31c18d87 813
7b5eff4d
EV		 814 if (op == CC_OP_CMP) {
815 tmp = tcg_temp_new();
816 writeback = 0;
817 } else if (size == 4) {
818 tmp = d;
819 writeback = 0;
820 } else {
821 tmp = tcg_temp_new();
822 }
44696296 823
30abcfc7 824
7b5eff4d
EV		 825 cris_pre_alu_update_cc(dc, op, op_a, op_b, size);
826 cris_alu_op_exec(dc, op, tmp, op_a, op_b, size);
827 cris_update_result(dc, tmp);
05ba7d5f 828
7b5eff4d
EV		 829 /* Writeback. */
830 if (writeback) {
831 if (size == 1) {
832 tcg_gen_andi_tl(d, d, ~0xff);
833 } else {
834 tcg_gen_andi_tl(d, d, ~0xffff);
835 }
836 tcg_gen_or_tl(d, d, tmp);
837 }
11f4e8f8 838 if (tmp != d) {
7b5eff4d
EV		 839 tcg_temp_free(tmp);
840 }
8170028d
TS		 841}
842
843static int arith_cc(DisasContext *dc)
844{
7b5eff4d
EV		 845 if (dc->update_cc) {
846 switch (dc->cc_op) {
847 case CC_OP_ADDC: return 1;
848 case CC_OP_ADD: return 1;
849 case CC_OP_SUB: return 1;
850 case CC_OP_DSTEP: return 1;
851 case CC_OP_LSL: return 1;
852 case CC_OP_LSR: return 1;
853 case CC_OP_ASR: return 1;
854 case CC_OP_CMP: return 1;
855 case CC_OP_NEG: return 1;
856 case CC_OP_OR: return 1;
857 case CC_OP_AND: return 1;
858 case CC_OP_XOR: return 1;
859 case CC_OP_MULU: return 1;
860 case CC_OP_MULS: return 1;
861 default:
862 return 0;
863 }
864 }
865 return 0;
8170028d
TS		 866}
867
c5631f48 868static void gen_tst_cc (DisasContext *dc, TCGv cc, int cond)
8170028d 869{
7b5eff4d
EV		 870 int arith_opt, move_opt;
871
872 /* TODO: optimize more condition codes. */
873
874 /*
875 * If the flags are live, we've gotta look into the bits of CCS.
876 * Otherwise, if we just did an arithmetic operation we try to
877 * evaluate the condition code faster.
878 *
879 * When this function is done, T0 should be non-zero if the condition
880 * code is true.
881 */
882 arith_opt = arith_cc(dc) && !dc->flags_uptodate;
883 move_opt = (dc->cc_op == CC_OP_MOVE);
884 switch (cond) {
885 case CC_EQ:
886 if ((arith_opt || move_opt)
887 && dc->cc_x_uptodate != (2 | X_FLAG)) {
888 tcg_gen_setcond_tl(TCG_COND_EQ, cc,
889 cc_result, tcg_const_tl(0));
890 } else {
891 cris_evaluate_flags(dc);
892 tcg_gen_andi_tl(cc,
893 cpu_PR[PR_CCS], Z_FLAG);
894 }
895 break;
896 case CC_NE:
897 if ((arith_opt || move_opt)
898 && dc->cc_x_uptodate != (2 | X_FLAG)) {
899 tcg_gen_mov_tl(cc, cc_result);
900 } else {
901 cris_evaluate_flags(dc);
902 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
903 Z_FLAG);
904 tcg_gen_andi_tl(cc, cc, Z_FLAG);
905 }
906 break;
907 case CC_CS:
908 cris_evaluate_flags(dc);
909 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], C_FLAG);
910 break;
911 case CC_CC:
912 cris_evaluate_flags(dc);
913 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], C_FLAG);
914 tcg_gen_andi_tl(cc, cc, C_FLAG);
915 break;
916 case CC_VS:
917 cris_evaluate_flags(dc);
918 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], V_FLAG);
919 break;
920 case CC_VC:
921 cris_evaluate_flags(dc);
922 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
923 V_FLAG);
924 tcg_gen_andi_tl(cc, cc, V_FLAG);
925 break;
926 case CC_PL:
927 if (arith_opt || move_opt) {
928 int bits = 31;
929
930 if (dc->cc_size == 1) {
931 bits = 7;
932 } else if (dc->cc_size == 2) {
933 bits = 15;
934 }
935
936 tcg_gen_shri_tl(cc, cc_result, bits);
937 tcg_gen_xori_tl(cc, cc, 1);
938 } else {
939 cris_evaluate_flags(dc);
940 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
941 N_FLAG);
942 tcg_gen_andi_tl(cc, cc, N_FLAG);
943 }
944 break;
945 case CC_MI:
946 if (arith_opt || move_opt) {
947 int bits = 31;
948
949 if (dc->cc_size == 1) {
950 bits = 7;
951 } else if (dc->cc_size == 2) {
952 bits = 15;
953 }
954
955 tcg_gen_shri_tl(cc, cc_result, bits);
956 tcg_gen_andi_tl(cc, cc, 1);
957 } else {
958 cris_evaluate_flags(dc);
959 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
960 N_FLAG);
961 }
962 break;
963 case CC_LS:
964 cris_evaluate_flags(dc);
965 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
966 C_FLAG | Z_FLAG);
967 break;
968 case CC_HI:
969 cris_evaluate_flags(dc);
970 {
971 TCGv tmp;
972
973 tmp = tcg_temp_new();
974 tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS],
975 C_FLAG | Z_FLAG);
976 /* Overlay the C flag on top of the Z. */
977 tcg_gen_shli_tl(cc, tmp, 2);
978 tcg_gen_and_tl(cc, tmp, cc);
979 tcg_gen_andi_tl(cc, cc, Z_FLAG);
980
981 tcg_temp_free(tmp);
982 }
983 break;
984 case CC_GE:
985 cris_evaluate_flags(dc);
986 /* Overlay the V flag on top of the N. */
987 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
988 tcg_gen_xor_tl(cc,
989 cpu_PR[PR_CCS], cc);
990 tcg_gen_andi_tl(cc, cc, N_FLAG);
991 tcg_gen_xori_tl(cc, cc, N_FLAG);
992 break;
993 case CC_LT:
994 cris_evaluate_flags(dc);
995 /* Overlay the V flag on top of the N. */
996 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
997 tcg_gen_xor_tl(cc,
998 cpu_PR[PR_CCS], cc);
999 tcg_gen_andi_tl(cc, cc, N_FLAG);
1000 break;
1001 case CC_GT:
1002 cris_evaluate_flags(dc);
1003 {
1004 TCGv n, z;
1005
1006 n = tcg_temp_new();
1007 z = tcg_temp_new();
1008
1009 /* To avoid a shift we overlay everything on
1010 the V flag. */
1011 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1012 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1013 /* invert Z. */
1014 tcg_gen_xori_tl(z, z, 2);
1015
1016 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1017 tcg_gen_xori_tl(n, n, 2);
1018 tcg_gen_and_tl(cc, z, n);
1019 tcg_gen_andi_tl(cc, cc, 2);
1020
1021 tcg_temp_free(n);
1022 tcg_temp_free(z);
1023 }
1024 break;
1025 case CC_LE:
1026 cris_evaluate_flags(dc);
1027 {
1028 TCGv n, z;
1029
1030 n = tcg_temp_new();
1031 z = tcg_temp_new();
1032
1033 /* To avoid a shift we overlay everything on
1034 the V flag. */
1035 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1036 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1037
1038 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1039 tcg_gen_or_tl(cc, z, n);
1040 tcg_gen_andi_tl(cc, cc, 2);
1041
1042 tcg_temp_free(n);
1043 tcg_temp_free(z);
1044 }
1045 break;
1046 case CC_P:
1047 cris_evaluate_flags(dc);
1048 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], P_FLAG);
1049 break;
1050 case CC_A:
1051 tcg_gen_movi_tl(cc, 1);
1052 break;
1053 default:
1054 BUG();
1055 break;
1056 };
8170028d
TS		 1057}
1058
2a44f7f1
EI		 1059static void cris_store_direct_jmp(DisasContext *dc)
1060{
7b5eff4d
EV		 1061 /* Store the direct jmp state into the cpu-state. */
1062 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
1063 if (dc->jmp == JMP_DIRECT) {
1064 tcg_gen_movi_tl(env_btaken, 1);
1065 }
1066 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1067 dc->jmp = JMP_INDIRECT;
1068 }
2a44f7f1
EI		 1069}
1070
1071static void cris_prepare_cc_branch (DisasContext *dc,
7b5eff4d 1072 int offset, int cond)
8170028d 1073{
7b5eff4d
EV		 1074 /* This helps us re-schedule the micro-code to insns in delay-slots
1075 before the actual jump. */
1076 dc->delayed_branch = 2;
1077 dc->jmp = JMP_DIRECT_CC;
1078 dc->jmp_pc = dc->pc + offset;
2a44f7f1 1079
7b5eff4d
EV		 1080 gen_tst_cc(dc, env_btaken, cond);
1081 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
8170028d
TS		 1082}
1083
b41f7df0 1084
2a44f7f1
EI		 1085/* jumps, when the dest is in a live reg for example. Direct should be set
1086 when the dest addr is constant to allow tb chaining. */
1087static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type)
8170028d 1088{
7b5eff4d
EV		 1089 /* This helps us re-schedule the micro-code to insns in delay-slots
1090 before the actual jump. */
1091 dc->delayed_branch = 2;
1092 dc->jmp = type;
1093 if (type == JMP_INDIRECT) {
1094 tcg_gen_movi_tl(env_btaken, 1);
1095 }
8170028d
TS		 1096}
1097
a7812ae4
PB		 1098static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr)
1099{
97ed5ccd 1100 int mem_index = cpu_mmu_index(&dc->cpu->env, false);
a7812ae4 1101
7b5eff4d
EV		 1102 /* If we get a fault on a delayslot we must keep the jmp state in
1103 the cpu-state to be able to re-execute the jmp. */
1104 if (dc->delayed_branch == 1) {
1105 cris_store_direct_jmp(dc);
1106 }
a7812ae4 1107
a1d22a36 1108 tcg_gen_qemu_ld_i64(dst, addr, mem_index, MO_TEQ);
a7812ae4
PB		 1109}
1110
9b32fbf8 1111static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
7b5eff4d
EV		 1112 unsigned int size, int sign)
1113{
97ed5ccd 1114 int mem_index = cpu_mmu_index(&dc->cpu->env, false);
7b5eff4d
EV		 1115
1116 /* If we get a fault on a delayslot we must keep the jmp state in
1117 the cpu-state to be able to re-execute the jmp. */
1118 if (dc->delayed_branch == 1) {
1119 cris_store_direct_jmp(dc);
1120 }
1121
a1d22a36
RH		 1122 tcg_gen_qemu_ld_tl(dst, addr, mem_index,
1123 MO_TE + ctz32(size) + (sign ? MO_SIGN : 0));
8170028d
TS		 1124}
1125
9b32fbf8 1126static void gen_store (DisasContext *dc, TCGv addr, TCGv val,
7b5eff4d 1127 unsigned int size)
8170028d 1128{
97ed5ccd 1129 int mem_index = cpu_mmu_index(&dc->cpu->env, false);
b41f7df0 1130
7b5eff4d
EV		 1131 /* If we get a fault on a delayslot we must keep the jmp state in
1132 the cpu-state to be able to re-execute the jmp. */
1133 if (dc->delayed_branch == 1) {
1134 cris_store_direct_jmp(dc);
1135 }
2a44f7f1
EI		 1136
1137
7b5eff4d
EV		 1138 /* Conditional writes. We only support the kind were X and P are known
1139 at translation time. */
1140 if (dc->flagx_known && dc->flags_x && (dc->tb_flags & P_FLAG)) {
1141 dc->postinc = 0;
1142 cris_evaluate_flags(dc);
1143 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], C_FLAG);
1144 return;
1145 }
2a44f7f1 1146
a1d22a36 1147 tcg_gen_qemu_st_tl(val, addr, mem_index, MO_TE + ctz32(size));
2a44f7f1 1148
7b5eff4d
EV		 1149 if (dc->flagx_known && dc->flags_x) {
1150 cris_evaluate_flags(dc);
1151 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~C_FLAG);
1152 }
8170028d
TS		 1153}
1154
05ba7d5f 1155static inline void t_gen_sext(TCGv d, TCGv s, int size)
8170028d 1156{
7b5eff4d
EV		 1157 if (size == 1) {
1158 tcg_gen_ext8s_i32(d, s);
1159 } else if (size == 2) {
1160 tcg_gen_ext16s_i32(d, s);
11f4e8f8 1161 } else {
7b5eff4d
EV		 1162 tcg_gen_mov_tl(d, s);
1163 }
8170028d
TS		 1164}
1165
05ba7d5f 1166static inline void t_gen_zext(TCGv d, TCGv s, int size)
8170028d 1167{
7b5eff4d
EV		 1168 if (size == 1) {
1169 tcg_gen_ext8u_i32(d, s);
1170 } else if (size == 2) {
1171 tcg_gen_ext16u_i32(d, s);
11f4e8f8 1172 } else {
7b5eff4d
EV		 1173 tcg_gen_mov_tl(d, s);
1174 }
8170028d
TS		 1175}
1176
1177#if DISAS_CRIS
1178static char memsize_char(int size)
1179{
7b5eff4d
EV		 1180 switch (size) {
1181 case 1: return 'b'; break;
1182 case 2: return 'w'; break;
1183 case 4: return 'd'; break;
1184 default:
1185 return 'x';
1186 break;
1187 }
8170028d
TS		 1188}
1189#endif
1190
30abcfc7 1191static inline unsigned int memsize_z(DisasContext *dc)
8170028d 1192{
7b5eff4d 1193 return dc->zsize + 1;
8170028d
TS		 1194}
1195
30abcfc7 1196static inline unsigned int memsize_zz(DisasContext *dc)
8170028d 1197{
7b5eff4d
EV		 1198 switch (dc->zzsize) {
1199 case 0: return 1;
1200 case 1: return 2;
1201 default:
1202 return 4;
1203 }
8170028d
TS		 1204}
1205
c7d05695 1206static inline void do_postinc (DisasContext *dc, int size)
8170028d 1207{
7b5eff4d
EV		 1208 if (dc->postinc) {
1209 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);
1210 }
8170028d
TS		 1211}
1212
30abcfc7 1213static inline void dec_prep_move_r(DisasContext *dc, int rs, int rd,
7b5eff4d 1214 int size, int s_ext, TCGv dst)
8170028d 1215{
7b5eff4d
EV		 1216 if (s_ext) {
1217 t_gen_sext(dst, cpu_R[rs], size);
1218 } else {
1219 t_gen_zext(dst, cpu_R[rs], size);
1220 }
8170028d
TS		 1221}
1222
1223/* Prepare T0 and T1 for a register alu operation.
1224 s_ext decides if the operand1 should be sign-extended or zero-extended when
1225 needed. */
1226static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
7b5eff4d 1227 int size, int s_ext, TCGv dst, TCGv src)
8170028d 1228{
7b5eff4d 1229 dec_prep_move_r(dc, rs, rd, size, s_ext, src);
8170028d 1230
7b5eff4d
EV		 1231 if (s_ext) {
1232 t_gen_sext(dst, cpu_R[rd], size);
1233 } else {
1234 t_gen_zext(dst, cpu_R[rd], size);
1235 }
8170028d
TS		 1236}
1237
cf7e0c80
AJ		 1238static int dec_prep_move_m(CPUCRISState *env, DisasContext *dc,
1239 int s_ext, int memsize, TCGv dst)
8170028d 1240{
7b5eff4d
EV		 1241 unsigned int rs;
1242 uint32_t imm;
1243 int is_imm;
1244 int insn_len = 2;
1245
1246 rs = dc->op1;
1247 is_imm = rs == 15 && dc->postinc;
1248
1249 /* Load [$rs] onto T1. */
1250 if (is_imm) {
1251 insn_len = 2 + memsize;
1252 if (memsize == 1) {
1253 insn_len++;
1254 }
1255
1256 imm = cris_fetch(env, dc, dc->pc + 2, memsize, s_ext);
1257 tcg_gen_movi_tl(dst, imm);
1258 dc->postinc = 0;
1259 } else {
1260 cris_flush_cc_state(dc);
1261 gen_load(dc, dst, cpu_R[rs], memsize, 0);
1262 if (s_ext) {
1263 t_gen_sext(dst, dst, memsize);
1264 } else {
1265 t_gen_zext(dst, dst, memsize);
1266 }
1267 }
1268 return insn_len;
cf1d97f0
EI		 1269}
1270
1271/* Prepare T0 and T1 for a memory + alu operation.
1272 s_ext decides if the operand1 should be sign-extended or zero-extended when
1273 needed. */
cf7e0c80
AJ		 1274static int dec_prep_alu_m(CPUCRISState *env, DisasContext *dc,
1275 int s_ext, int memsize, TCGv dst, TCGv src)
cf1d97f0 1276{
7b5eff4d 1277 int insn_len;
cf1d97f0 1278
7b5eff4d
EV		 1279 insn_len = dec_prep_move_m(env, dc, s_ext, memsize, src);
1280 tcg_gen_mov_tl(dst, cpu_R[dc->op2]);
1281 return insn_len;
8170028d
TS		 1282}
1283
1284#if DISAS_CRIS
1285static const char *cc_name(int cc)
1286{
7b5eff4d
EV		 1287 static const char *cc_names[16] = {
1288 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1289 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1290 };
1291 assert(cc < 16);
1292 return cc_names[cc];
8170028d
TS		 1293}
1294#endif
1295
b41f7df0
EI		 1296/* Start of insn decoders. */
1297
cf7e0c80 1298static int dec_bccq(CPUCRISState *env, DisasContext *dc)
8170028d 1299{
7b5eff4d
EV		 1300 int32_t offset;
1301 int sign;
1302 uint32_t cond = dc->op2;
8170028d 1303
7b5eff4d
EV		 1304 offset = EXTRACT_FIELD(dc->ir, 1, 7);
1305 sign = EXTRACT_FIELD(dc->ir, 0, 0);
8170028d 1306
7b5eff4d
EV		 1307 offset *= 2;
1308 offset |= sign << 8;
1309 offset = sign_extend(offset, 8);
8170028d 1310
7b5eff4d 1311 LOG_DIS("b%s %x\n", cc_name(cond), dc->pc + offset);
2a44f7f1 1312
7b5eff4d
EV		 1313 /* op2 holds the condition-code. */
1314 cris_cc_mask(dc, 0);
1315 cris_prepare_cc_branch(dc, offset, cond);
1316 return 2;
8170028d 1317}
cf7e0c80 1318static int dec_addoq(CPUCRISState *env, DisasContext *dc)
8170028d 1319{
7b5eff4d 1320 int32_t imm;
8170028d 1321
7b5eff4d
EV		 1322 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);
1323 imm = sign_extend(dc->op1, 7);
8170028d 1324
7b5eff4d
EV		 1325 LOG_DIS("addoq %d, $r%u\n", imm, dc->op2);
1326 cris_cc_mask(dc, 0);
1327 /* Fetch register operand, */
1328 tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm);
fb48f71b 1329
7b5eff4d 1330 return 2;
8170028d 1331}
cf7e0c80 1332static int dec_addq(CPUCRISState *env, DisasContext *dc)
8170028d 1333{
7b5eff4d 1334 LOG_DIS("addq %u, $r%u\n", dc->op1, dc->op2);
8170028d 1335
7b5eff4d 1336 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
8170028d 1337
7b5eff4d 1338 cris_cc_mask(dc, CC_MASK_NZVC);
30abcfc7 1339
7b5eff4d
EV		 1340 cris_alu(dc, CC_OP_ADD,
1341 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1342 return 2;
8170028d 1343}
cf7e0c80 1344static int dec_moveq(CPUCRISState *env, DisasContext *dc)
8170028d 1345{
7b5eff4d 1346 uint32_t imm;
8170028d 1347
7b5eff4d
EV		 1348 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1349 imm = sign_extend(dc->op1, 5);
1350 LOG_DIS("moveq %d, $r%u\n", imm, dc->op2);
8170028d 1351
7b5eff4d
EV		 1352 tcg_gen_movi_tl(cpu_R[dc->op2], imm);
1353 return 2;
8170028d 1354}
cf7e0c80 1355static int dec_subq(CPUCRISState *env, DisasContext *dc)
8170028d 1356{
7b5eff4d 1357 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
8170028d 1358
7b5eff4d 1359 LOG_DIS("subq %u, $r%u\n", dc->op1, dc->op2);
8170028d 1360
7b5eff4d
EV		 1361 cris_cc_mask(dc, CC_MASK_NZVC);
1362 cris_alu(dc, CC_OP_SUB,
1363 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1364 return 2;
8170028d 1365}
cf7e0c80 1366static int dec_cmpq(CPUCRISState *env, DisasContext *dc)
8170028d 1367{
7b5eff4d
EV		 1368 uint32_t imm;
1369 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1370 imm = sign_extend(dc->op1, 5);
8170028d 1371
7b5eff4d
EV		 1372 LOG_DIS("cmpq %d, $r%d\n", imm, dc->op2);
1373 cris_cc_mask(dc, CC_MASK_NZVC);
30abcfc7 1374
7b5eff4d
EV		 1375 cris_alu(dc, CC_OP_CMP,
1376 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1377 return 2;
8170028d 1378}
cf7e0c80 1379static int dec_andq(CPUCRISState *env, DisasContext *dc)
8170028d 1380{
7b5eff4d
EV		 1381 uint32_t imm;
1382 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1383 imm = sign_extend(dc->op1, 5);
8170028d 1384
7b5eff4d
EV		 1385 LOG_DIS("andq %d, $r%d\n", imm, dc->op2);
1386 cris_cc_mask(dc, CC_MASK_NZ);
30abcfc7 1387
7b5eff4d
EV		 1388 cris_alu(dc, CC_OP_AND,
1389 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1390 return 2;
8170028d 1391}
cf7e0c80 1392static int dec_orq(CPUCRISState *env, DisasContext *dc)
8170028d 1393{
7b5eff4d
EV		 1394 uint32_t imm;
1395 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1396 imm = sign_extend(dc->op1, 5);
1397 LOG_DIS("orq %d, $r%d\n", imm, dc->op2);
1398 cris_cc_mask(dc, CC_MASK_NZ);
30abcfc7 1399
7b5eff4d
EV		 1400 cris_alu(dc, CC_OP_OR,
1401 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1402 return 2;
8170028d 1403}
cf7e0c80 1404static int dec_btstq(CPUCRISState *env, DisasContext *dc)
8170028d 1405{
7b5eff4d
EV		 1406 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1407 LOG_DIS("btstq %u, $r%d\n", dc->op1, dc->op2);
17ac9754 1408
7b5eff4d
EV		 1409 cris_cc_mask(dc, CC_MASK_NZ);
1410 cris_evaluate_flags(dc);
febc9920 1411 gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
7b5eff4d
EV		 1412 tcg_const_tl(dc->op1), cpu_PR[PR_CCS]);
1413 cris_alu(dc, CC_OP_MOVE,
1414 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1415 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1416 dc->flags_uptodate = 1;
1417 return 2;
8170028d 1418}
cf7e0c80 1419static int dec_asrq(CPUCRISState *env, DisasContext *dc)
8170028d 1420{
7b5eff4d
EV		 1421 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1422 LOG_DIS("asrq %u, $r%d\n", dc->op1, dc->op2);
1423 cris_cc_mask(dc, CC_MASK_NZ);
30abcfc7 1424
7b5eff4d
EV		 1425 tcg_gen_sari_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1426 cris_alu(dc, CC_OP_MOVE,
1427 cpu_R[dc->op2],
1428 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1429 return 2;
8170028d 1430}
cf7e0c80 1431static int dec_lslq(CPUCRISState *env, DisasContext *dc)
8170028d 1432{
7b5eff4d
EV		 1433 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1434 LOG_DIS("lslq %u, $r%d\n", dc->op1, dc->op2);
8170028d 1435
7b5eff4d 1436 cris_cc_mask(dc, CC_MASK_NZ);
30abcfc7 1437
7b5eff4d 1438 tcg_gen_shli_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
2a44f7f1 1439
7b5eff4d
EV		 1440 cris_alu(dc, CC_OP_MOVE,
1441 cpu_R[dc->op2],
1442 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1443 return 2;
8170028d 1444}
cf7e0c80 1445static int dec_lsrq(CPUCRISState *env, DisasContext *dc)
8170028d 1446{
7b5eff4d
EV		 1447 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1448 LOG_DIS("lsrq %u, $r%d\n", dc->op1, dc->op2);
8170028d 1449
7b5eff4d 1450 cris_cc_mask(dc, CC_MASK_NZ);
30abcfc7 1451
7b5eff4d
EV		 1452 tcg_gen_shri_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1453 cris_alu(dc, CC_OP_MOVE,
1454 cpu_R[dc->op2],
1455 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1456 return 2;
8170028d
TS		 1457}
1458
cf7e0c80 1459static int dec_move_r(CPUCRISState *env, DisasContext *dc)
8170028d 1460{
7b5eff4d
EV		 1461 int size = memsize_zz(dc);
1462
1463 LOG_DIS("move.%c $r%u, $r%u\n",
1464 memsize_char(size), dc->op1, dc->op2);
1465
1466 cris_cc_mask(dc, CC_MASK_NZ);
1467 if (size == 4) {
1468 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_R[dc->op2]);
1469 cris_cc_mask(dc, CC_MASK_NZ);
1470 cris_update_cc_op(dc, CC_OP_MOVE, 4);
1471 cris_update_cc_x(dc);
1472 cris_update_result(dc, cpu_R[dc->op2]);
1473 } else {
1474 TCGv t0;
1475
1476 t0 = tcg_temp_new();
1477 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1478 cris_alu(dc, CC_OP_MOVE,
1479 cpu_R[dc->op2],
1480 cpu_R[dc->op2], t0, size);
1481 tcg_temp_free(t0);
1482 }
1483 return 2;
8170028d
TS		 1484}
1485
cf7e0c80 1486static int dec_scc_r(CPUCRISState *env, DisasContext *dc)
8170028d 1487{
7b5eff4d 1488 int cond = dc->op2;
8170028d 1489
7b5eff4d
EV		 1490 LOG_DIS("s%s $r%u\n",
1491 cc_name(cond), dc->op1);
8170028d 1492
88174019
RH		 1493 gen_tst_cc(dc, cpu_R[dc->op1], cond);
1494 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_R[dc->op1], cpu_R[dc->op1], 0);
8170028d 1495
7b5eff4d
EV		 1496 cris_cc_mask(dc, 0);
1497 return 2;
8170028d
TS		 1498}
1499
fb48f71b
EI		 1500static inline void cris_alu_alloc_temps(DisasContext *dc, int size, TCGv *t)
1501{
7b5eff4d
EV		 1502 if (size == 4) {
1503 t[0] = cpu_R[dc->op2];
1504 t[1] = cpu_R[dc->op1];
1505 } else {
1506 t[0] = tcg_temp_new();
1507 t[1] = tcg_temp_new();
1508 }
fb48f71b
EI		 1509}
1510
1511static inline void cris_alu_free_temps(DisasContext *dc, int size, TCGv *t)
1512{
7b5eff4d
EV		 1513 if (size != 4) {
1514 tcg_temp_free(t[0]);
1515 tcg_temp_free(t[1]);
1516 }
fb48f71b
EI		 1517}
1518
cf7e0c80 1519static int dec_and_r(CPUCRISState *env, DisasContext *dc)
8170028d 1520{
7b5eff4d
EV		 1521 TCGv t[2];
1522 int size = memsize_zz(dc);
8170028d 1523
7b5eff4d
EV		 1524 LOG_DIS("and.%c $r%u, $r%u\n",
1525 memsize_char(size), dc->op1, dc->op2);
fb48f71b 1526
7b5eff4d 1527 cris_cc_mask(dc, CC_MASK_NZ);
30abcfc7 1528
7b5eff4d
EV		 1529 cris_alu_alloc_temps(dc, size, t);
1530 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1531 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], size);
1532 cris_alu_free_temps(dc, size, t);
1533 return 2;
8170028d
TS		 1534}
1535
cf7e0c80 1536static int dec_lz_r(CPUCRISState *env, DisasContext *dc)
8170028d 1537{
7b5eff4d
EV		 1538 TCGv t0;
1539 LOG_DIS("lz $r%u, $r%u\n",
1540 dc->op1, dc->op2);
1541 cris_cc_mask(dc, CC_MASK_NZ);
1542 t0 = tcg_temp_new();
1543 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0, cpu_R[dc->op2], t0);
1544 cris_alu(dc, CC_OP_LZ, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1545 tcg_temp_free(t0);
1546 return 2;
8170028d
TS		 1547}
1548
cf7e0c80 1549static int dec_lsl_r(CPUCRISState *env, DisasContext *dc)
8170028d 1550{
7b5eff4d
EV		 1551 TCGv t[2];
1552 int size = memsize_zz(dc);
8170028d 1553
7b5eff4d
EV		 1554 LOG_DIS("lsl.%c $r%u, $r%u\n",
1555 memsize_char(size), dc->op1, dc->op2);
30abcfc7 1556
7b5eff4d
EV		 1557 cris_cc_mask(dc, CC_MASK_NZ);
1558 cris_alu_alloc_temps(dc, size, t);
1559 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1560 tcg_gen_andi_tl(t[1], t[1], 63);
1561 cris_alu(dc, CC_OP_LSL, cpu_R[dc->op2], t[0], t[1], size);
1562 cris_alu_alloc_temps(dc, size, t);
1563 return 2;
8170028d
TS		 1564}
1565
cf7e0c80 1566static int dec_lsr_r(CPUCRISState *env, DisasContext *dc)
8170028d 1567{
7b5eff4d
EV		 1568 TCGv t[2];
1569 int size = memsize_zz(dc);
8170028d 1570
7b5eff4d
EV		 1571 LOG_DIS("lsr.%c $r%u, $r%u\n",
1572 memsize_char(size), dc->op1, dc->op2);
30abcfc7 1573
7b5eff4d
EV		 1574 cris_cc_mask(dc, CC_MASK_NZ);
1575 cris_alu_alloc_temps(dc, size, t);
1576 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1577 tcg_gen_andi_tl(t[1], t[1], 63);
1578 cris_alu(dc, CC_OP_LSR, cpu_R[dc->op2], t[0], t[1], size);
1579 cris_alu_free_temps(dc, size, t);
1580 return 2;
8170028d
TS		 1581}
1582
cf7e0c80 1583static int dec_asr_r(CPUCRISState *env, DisasContext *dc)
8170028d 1584{
7b5eff4d
EV		 1585 TCGv t[2];
1586 int size = memsize_zz(dc);
8170028d 1587
7b5eff4d
EV		 1588 LOG_DIS("asr.%c $r%u, $r%u\n",
1589 memsize_char(size), dc->op1, dc->op2);
30abcfc7 1590
7b5eff4d
EV		 1591 cris_cc_mask(dc, CC_MASK_NZ);
1592 cris_alu_alloc_temps(dc, size, t);
1593 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1594 tcg_gen_andi_tl(t[1], t[1], 63);
1595 cris_alu(dc, CC_OP_ASR, cpu_R[dc->op2], t[0], t[1], size);
1596 cris_alu_free_temps(dc, size, t);
1597 return 2;
8170028d
TS		 1598}
1599
cf7e0c80 1600static int dec_muls_r(CPUCRISState *env, DisasContext *dc)
8170028d 1601{
7b5eff4d
EV		 1602 TCGv t[2];
1603 int size = memsize_zz(dc);
8170028d 1604
7b5eff4d
EV		 1605 LOG_DIS("muls.%c $r%u, $r%u\n",
1606 memsize_char(size), dc->op1, dc->op2);
1607 cris_cc_mask(dc, CC_MASK_NZV);
1608 cris_alu_alloc_temps(dc, size, t);
1609 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
30abcfc7 1610
7b5eff4d
EV		 1611 cris_alu(dc, CC_OP_MULS, cpu_R[dc->op2], t[0], t[1], 4);
1612 cris_alu_free_temps(dc, size, t);
1613 return 2;
8170028d
TS		 1614}
1615
cf7e0c80 1616static int dec_mulu_r(CPUCRISState *env, DisasContext *dc)
8170028d 1617{
7b5eff4d
EV		 1618 TCGv t[2];
1619 int size = memsize_zz(dc);
8170028d 1620
7b5eff4d
EV		 1621 LOG_DIS("mulu.%c $r%u, $r%u\n",
1622 memsize_char(size), dc->op1, dc->op2);
1623 cris_cc_mask(dc, CC_MASK_NZV);
1624 cris_alu_alloc_temps(dc, size, t);
1625 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
30abcfc7 1626
7b5eff4d
EV		 1627 cris_alu(dc, CC_OP_MULU, cpu_R[dc->op2], t[0], t[1], 4);
1628 cris_alu_alloc_temps(dc, size, t);
1629 return 2;
8170028d
TS		 1630}
1631
1632
cf7e0c80 1633static int dec_dstep_r(CPUCRISState *env, DisasContext *dc)
8170028d 1634{
7b5eff4d
EV		 1635 LOG_DIS("dstep $r%u, $r%u\n", dc->op1, dc->op2);
1636 cris_cc_mask(dc, CC_MASK_NZ);
1637 cris_alu(dc, CC_OP_DSTEP,
1638 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1639 return 2;
8170028d
TS		 1640}
1641
cf7e0c80 1642static int dec_xor_r(CPUCRISState *env, DisasContext *dc)
8170028d 1643{
7b5eff4d
EV		 1644 TCGv t[2];
1645 int size = memsize_zz(dc);
1646 LOG_DIS("xor.%c $r%u, $r%u\n",
1647 memsize_char(size), dc->op1, dc->op2);
1648 BUG_ON(size != 4); /* xor is dword. */
1649 cris_cc_mask(dc, CC_MASK_NZ);
1650 cris_alu_alloc_temps(dc, size, t);
1651 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
30abcfc7 1652
7b5eff4d
EV		 1653 cris_alu(dc, CC_OP_XOR, cpu_R[dc->op2], t[0], t[1], 4);
1654 cris_alu_free_temps(dc, size, t);
1655 return 2;
8170028d
TS		 1656}
1657
cf7e0c80 1658static int dec_bound_r(CPUCRISState *env, DisasContext *dc)
8170028d 1659{
7b5eff4d
EV		 1660 TCGv l0;
1661 int size = memsize_zz(dc);
1662 LOG_DIS("bound.%c $r%u, $r%u\n",
1663 memsize_char(size), dc->op1, dc->op2);
1664 cris_cc_mask(dc, CC_MASK_NZ);
1665 l0 = tcg_temp_local_new();
1666 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, l0);
1667 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], cpu_R[dc->op2], l0, 4);
1668 tcg_temp_free(l0);
1669 return 2;
8170028d
TS		 1670}
1671
cf7e0c80 1672static int dec_cmp_r(CPUCRISState *env, DisasContext *dc)
8170028d 1673{
7b5eff4d
EV		 1674 TCGv t[2];
1675 int size = memsize_zz(dc);
1676 LOG_DIS("cmp.%c $r%u, $r%u\n",
1677 memsize_char(size), dc->op1, dc->op2);
1678 cris_cc_mask(dc, CC_MASK_NZVC);
1679 cris_alu_alloc_temps(dc, size, t);
1680 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
30abcfc7 1681
7b5eff4d
EV		 1682 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], t[0], t[1], size);
1683 cris_alu_free_temps(dc, size, t);
1684 return 2;
8170028d
TS		 1685}
1686
cf7e0c80 1687static int dec_abs_r(CPUCRISState *env, DisasContext *dc)
8170028d 1688{
7b5eff4d 1689 TCGv t0;
3157a0a9 1690
7b5eff4d
EV		 1691 LOG_DIS("abs $r%u, $r%u\n",
1692 dc->op1, dc->op2);
1693 cris_cc_mask(dc, CC_MASK_NZ);
3157a0a9 1694
7b5eff4d
EV		 1695 t0 = tcg_temp_new();
1696 tcg_gen_sari_tl(t0, cpu_R[dc->op1], 31);
1697 tcg_gen_xor_tl(cpu_R[dc->op2], cpu_R[dc->op1], t0);
1698 tcg_gen_sub_tl(cpu_R[dc->op2], cpu_R[dc->op2], t0);
1699 tcg_temp_free(t0);
7dcfb089 1700
7b5eff4d
EV		 1701 cris_alu(dc, CC_OP_MOVE,
1702 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1703 return 2;
8170028d
TS		 1704}
1705
cf7e0c80 1706static int dec_add_r(CPUCRISState *env, DisasContext *dc)
8170028d 1707{
7b5eff4d
EV		 1708 TCGv t[2];
1709 int size = memsize_zz(dc);
1710 LOG_DIS("add.%c $r%u, $r%u\n",
1711 memsize_char(size), dc->op1, dc->op2);
1712 cris_cc_mask(dc, CC_MASK_NZVC);
1713 cris_alu_alloc_temps(dc, size, t);
1714 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
30abcfc7 1715
7b5eff4d
EV		 1716 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], t[0], t[1], size);
1717 cris_alu_free_temps(dc, size, t);
1718 return 2;
8170028d
TS		 1719}
1720
cf7e0c80 1721static int dec_addc_r(CPUCRISState *env, DisasContext *dc)
8170028d 1722{
7b5eff4d
EV		 1723 LOG_DIS("addc $r%u, $r%u\n",
1724 dc->op1, dc->op2);
1725 cris_evaluate_flags(dc);
1726 /* Set for this insn. */
1727 dc->flagx_known = 1;
1728 dc->flags_x = X_FLAG;
a8cf66bb 1729
7b5eff4d
EV		 1730 cris_cc_mask(dc, CC_MASK_NZVC);
1731 cris_alu(dc, CC_OP_ADDC,
1732 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1733 return 2;
8170028d
TS		 1734}
1735
cf7e0c80 1736static int dec_mcp_r(CPUCRISState *env, DisasContext *dc)
8170028d 1737{
7b5eff4d
EV		 1738 LOG_DIS("mcp $p%u, $r%u\n",
1739 dc->op2, dc->op1);
1740 cris_evaluate_flags(dc);
1741 cris_cc_mask(dc, CC_MASK_RNZV);
1742 cris_alu(dc, CC_OP_MCP,
1743 cpu_R[dc->op1], cpu_R[dc->op1], cpu_PR[dc->op2], 4);
1744 return 2;
8170028d
TS		 1745}
1746
1747#if DISAS_CRIS
1748static char * swapmode_name(int mode, char *modename) {
7b5eff4d
EV		 1749 int i = 0;
1750 if (mode & 8) {
1751 modename[i++] = 'n';
1752 }
1753 if (mode & 4) {
1754 modename[i++] = 'w';
1755 }
1756 if (mode & 2) {
1757 modename[i++] = 'b';
1758 }
1759 if (mode & 1) {
1760 modename[i++] = 'r';
1761 }
1762 modename[i++] = 0;
1763 return modename;
8170028d
TS		 1764}
1765#endif
1766
cf7e0c80 1767static int dec_swap_r(CPUCRISState *env, DisasContext *dc)
8170028d 1768{
7b5eff4d 1769 TCGv t0;
cf1d97f0 1770#if DISAS_CRIS
7b5eff4d 1771 char modename[4];
cf1d97f0 1772#endif
7b5eff4d
EV		 1773 LOG_DIS("swap%s $r%u\n",
1774 swapmode_name(dc->op2, modename), dc->op1);
1775
1776 cris_cc_mask(dc, CC_MASK_NZ);
1777 t0 = tcg_temp_new();
08397c4b 1778 tcg_gen_mov_tl(t0, cpu_R[dc->op1]);
7b5eff4d
EV		 1779 if (dc->op2 & 8) {
1780 tcg_gen_not_tl(t0, t0);
1781 }
1782 if (dc->op2 & 4) {
1783 t_gen_swapw(t0, t0);
1784 }
1785 if (dc->op2 & 2) {
1786 t_gen_swapb(t0, t0);
1787 }
1788 if (dc->op2 & 1) {
1789 t_gen_swapr(t0, t0);
1790 }
1791 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op1], cpu_R[dc->op1], t0, 4);
1792 tcg_temp_free(t0);
1793 return 2;
8170028d
TS		 1794}
1795
cf7e0c80 1796static int dec_or_r(CPUCRISState *env, DisasContext *dc)
8170028d 1797{
7b5eff4d
EV		 1798 TCGv t[2];
1799 int size = memsize_zz(dc);
1800 LOG_DIS("or.%c $r%u, $r%u\n",
1801 memsize_char(size), dc->op1, dc->op2);
1802 cris_cc_mask(dc, CC_MASK_NZ);
1803 cris_alu_alloc_temps(dc, size, t);
1804 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1805 cris_alu(dc, CC_OP_OR, cpu_R[dc->op2], t[0], t[1], size);
1806 cris_alu_free_temps(dc, size, t);
1807 return 2;
8170028d
TS		 1808}
1809
cf7e0c80 1810static int dec_addi_r(CPUCRISState *env, DisasContext *dc)
8170028d 1811{
7b5eff4d
EV		 1812 TCGv t0;
1813 LOG_DIS("addi.%c $r%u, $r%u\n",
1814 memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
1815 cris_cc_mask(dc, 0);
1816 t0 = tcg_temp_new();
1817 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1818 tcg_gen_add_tl(cpu_R[dc->op1], cpu_R[dc->op1], t0);
1819 tcg_temp_free(t0);
1820 return 2;
8170028d
TS		 1821}
1822
cf7e0c80 1823static int dec_addi_acr(CPUCRISState *env, DisasContext *dc)
8170028d 1824{
7b5eff4d
EV		 1825 TCGv t0;
1826 LOG_DIS("addi.%c $r%u, $r%u, $acr\n",
1827 memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
1828 cris_cc_mask(dc, 0);
1829 t0 = tcg_temp_new();
1830 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1831 tcg_gen_add_tl(cpu_R[R_ACR], cpu_R[dc->op1], t0);
1832 tcg_temp_free(t0);
1833 return 2;
8170028d
TS		 1834}
1835
cf7e0c80 1836static int dec_neg_r(CPUCRISState *env, DisasContext *dc)
8170028d 1837{
7b5eff4d
EV		 1838 TCGv t[2];
1839 int size = memsize_zz(dc);
1840 LOG_DIS("neg.%c $r%u, $r%u\n",
1841 memsize_char(size), dc->op1, dc->op2);
1842 cris_cc_mask(dc, CC_MASK_NZVC);
1843 cris_alu_alloc_temps(dc, size, t);
1844 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
30abcfc7 1845
7b5eff4d
EV		 1846 cris_alu(dc, CC_OP_NEG, cpu_R[dc->op2], t[0], t[1], size);
1847 cris_alu_free_temps(dc, size, t);
1848 return 2;
8170028d
TS		 1849}
1850
cf7e0c80 1851static int dec_btst_r(CPUCRISState *env, DisasContext *dc)
8170028d 1852{
7b5eff4d
EV		 1853 LOG_DIS("btst $r%u, $r%u\n",
1854 dc->op1, dc->op2);
1855 cris_cc_mask(dc, CC_MASK_NZ);
1856 cris_evaluate_flags(dc);
febc9920 1857 gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
7b5eff4d
EV		 1858 cpu_R[dc->op1], cpu_PR[PR_CCS]);
1859 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2],
1860 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1861 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1862 dc->flags_uptodate = 1;
1863 return 2;
8170028d
TS		 1864}
1865
cf7e0c80 1866static int dec_sub_r(CPUCRISState *env, DisasContext *dc)
8170028d 1867{
7b5eff4d
EV		 1868 TCGv t[2];
1869 int size = memsize_zz(dc);
1870 LOG_DIS("sub.%c $r%u, $r%u\n",
1871 memsize_char(size), dc->op1, dc->op2);
1872 cris_cc_mask(dc, CC_MASK_NZVC);
1873 cris_alu_alloc_temps(dc, size, t);
1874 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1875 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], size);
1876 cris_alu_free_temps(dc, size, t);
1877 return 2;
8170028d
TS		 1878}
1879
1880/* Zero extension. From size to dword. */
cf7e0c80 1881static int dec_movu_r(CPUCRISState *env, DisasContext *dc)
8170028d 1882{
7b5eff4d
EV		 1883 TCGv t0;
1884 int size = memsize_z(dc);
1885 LOG_DIS("movu.%c $r%u, $r%u\n",
1886 memsize_char(size),
1887 dc->op1, dc->op2);
8170028d 1888
7b5eff4d
EV		 1889 cris_cc_mask(dc, CC_MASK_NZ);
1890 t0 = tcg_temp_new();
1891 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1892 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1893 tcg_temp_free(t0);
1894 return 2;
8170028d
TS		 1895}
1896
1897/* Sign extension. From size to dword. */
cf7e0c80 1898static int dec_movs_r(CPUCRISState *env, DisasContext *dc)
8170028d 1899{
7b5eff4d
EV		 1900 TCGv t0;
1901 int size = memsize_z(dc);
1902 LOG_DIS("movs.%c $r%u, $r%u\n",
1903 memsize_char(size),
1904 dc->op1, dc->op2);
8170028d 1905
7b5eff4d
EV		 1906 cris_cc_mask(dc, CC_MASK_NZ);
1907 t0 = tcg_temp_new();
1908 /* Size can only be qi or hi. */
1909 t_gen_sext(t0, cpu_R[dc->op1], size);
1910 cris_alu(dc, CC_OP_MOVE,
1911 cpu_R[dc->op2], cpu_R[dc->op1], t0, 4);
1912 tcg_temp_free(t0);
1913 return 2;
8170028d
TS		 1914}
1915
1916/* zero extension. From size to dword. */
cf7e0c80 1917static int dec_addu_r(CPUCRISState *env, DisasContext *dc)
8170028d 1918{
7b5eff4d
EV		 1919 TCGv t0;
1920 int size = memsize_z(dc);
1921 LOG_DIS("addu.%c $r%u, $r%u\n",
1922 memsize_char(size),
1923 dc->op1, dc->op2);
8170028d 1924
7b5eff4d
EV		 1925 cris_cc_mask(dc, CC_MASK_NZVC);
1926 t0 = tcg_temp_new();
1927 /* Size can only be qi or hi. */
1928 t_gen_zext(t0, cpu_R[dc->op1], size);
1929 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1930 tcg_temp_free(t0);
1931 return 2;
8170028d 1932}
05ba7d5f 1933
8170028d 1934/* Sign extension. From size to dword. */
cf7e0c80 1935static int dec_adds_r(CPUCRISState *env, DisasContext *dc)
8170028d 1936{
7b5eff4d
EV		 1937 TCGv t0;
1938 int size = memsize_z(dc);
1939 LOG_DIS("adds.%c $r%u, $r%u\n",
1940 memsize_char(size),
1941 dc->op1, dc->op2);
8170028d 1942
7b5eff4d
EV		 1943 cris_cc_mask(dc, CC_MASK_NZVC);
1944 t0 = tcg_temp_new();
1945 /* Size can only be qi or hi. */
1946 t_gen_sext(t0, cpu_R[dc->op1], size);
1947 cris_alu(dc, CC_OP_ADD,
1948 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1949 tcg_temp_free(t0);
1950 return 2;
8170028d
TS		 1951}
1952
1953/* Zero extension. From size to dword. */
cf7e0c80 1954static int dec_subu_r(CPUCRISState *env, DisasContext *dc)
8170028d 1955{
7b5eff4d
EV		 1956 TCGv t0;
1957 int size = memsize_z(dc);
1958 LOG_DIS("subu.%c $r%u, $r%u\n",
1959 memsize_char(size),
1960 dc->op1, dc->op2);
8170028d 1961
7b5eff4d
EV		 1962 cris_cc_mask(dc, CC_MASK_NZVC);
1963 t0 = tcg_temp_new();
1964 /* Size can only be qi or hi. */
1965 t_gen_zext(t0, cpu_R[dc->op1], size);
1966 cris_alu(dc, CC_OP_SUB,
1967 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1968 tcg_temp_free(t0);
1969 return 2;
8170028d
TS		 1970}
1971
1972/* Sign extension. From size to dword. */
cf7e0c80 1973static int dec_subs_r(CPUCRISState *env, DisasContext *dc)
8170028d 1974{
7b5eff4d
EV		 1975 TCGv t0;
1976 int size = memsize_z(dc);
1977 LOG_DIS("subs.%c $r%u, $r%u\n",
1978 memsize_char(size),
1979 dc->op1, dc->op2);
8170028d 1980
7b5eff4d
EV		 1981 cris_cc_mask(dc, CC_MASK_NZVC);
1982 t0 = tcg_temp_new();
1983 /* Size can only be qi or hi. */
1984 t_gen_sext(t0, cpu_R[dc->op1], size);
1985 cris_alu(dc, CC_OP_SUB,
1986 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1987 tcg_temp_free(t0);
1988 return 2;
8170028d
TS		 1989}
1990
cf7e0c80 1991static int dec_setclrf(CPUCRISState *env, DisasContext *dc)
8170028d 1992{
7b5eff4d
EV		 1993 uint32_t flags;
1994 int set = (~dc->opcode >> 2) & 1;
1995
1996
1997 flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
1998 | EXTRACT_FIELD(dc->ir, 0, 3);
1999 if (set && flags == 0) {
2000 LOG_DIS("nop\n");
2001 return 2;
2002 } else if (!set && (flags & 0x20)) {
2003 LOG_DIS("di\n");
2004 } else {
2005 LOG_DIS("%sf %x\n", set ? "set" : "clr", flags);
2006 }
2007
2008 /* User space is not allowed to touch these. Silently ignore. */
2009 if (dc->tb_flags & U_FLAG) {
2010 flags &= ~(S_FLAG | I_FLAG | U_FLAG);
2011 }
2012
2013 if (flags & X_FLAG) {
2014 dc->flagx_known = 1;
2015 if (set) {
2016 dc->flags_x = X_FLAG;
2017 } else {
2018 dc->flags_x = 0;
2019 }
2020 }
2021
2022 /* Break the TB if any of the SPI flag changes. */
2023 if (flags & (P_FLAG | S_FLAG)) {
2024 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2025 dc->is_jmp = DISAS_UPDATE;
2026 dc->cpustate_changed = 1;
2027 }
2028
2029 /* For the I flag, only act on posedge. */
2030 if ((flags & I_FLAG)) {
2031 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2032 dc->is_jmp = DISAS_UPDATE;
2033 dc->cpustate_changed = 1;
2034 }
2035
2036
2037 /* Simply decode the flags. */
2038 cris_evaluate_flags(dc);
2039 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2040 cris_update_cc_x(dc);
2041 tcg_gen_movi_tl(cc_op, dc->cc_op);
2042
2043 if (set) {
2044 if (!(dc->tb_flags & U_FLAG) && (flags & U_FLAG)) {
2045 /* Enter user mode. */
2046 t_gen_mov_env_TN(ksp, cpu_R[R_SP]);
2047 tcg_gen_mov_tl(cpu_R[R_SP], cpu_PR[PR_USP]);
2048 dc->cpustate_changed = 1;
2049 }
2050 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
2051 } else {
2052 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags);
2053 }
2054
2055 dc->flags_uptodate = 1;
2056 dc->clear_x = 0;
2057 return 2;
8170028d
TS		 2058}
2059
cf7e0c80 2060static int dec_move_rs(CPUCRISState *env, DisasContext *dc)
8170028d 2061{
7b5eff4d
EV		 2062 LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2);
2063 cris_cc_mask(dc, 0);
febc9920
AJ		 2064 gen_helper_movl_sreg_reg(cpu_env, tcg_const_tl(dc->op2),
2065 tcg_const_tl(dc->op1));
7b5eff4d 2066 return 2;
8170028d 2067}
cf7e0c80 2068static int dec_move_sr(CPUCRISState *env, DisasContext *dc)
8170028d 2069{
7b5eff4d
EV		 2070 LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1);
2071 cris_cc_mask(dc, 0);
febc9920
AJ		 2072 gen_helper_movl_reg_sreg(cpu_env, tcg_const_tl(dc->op1),
2073 tcg_const_tl(dc->op2));
7b5eff4d 2074 return 2;
8170028d 2075}
dceaf394 2076
cf7e0c80 2077static int dec_move_rp(CPUCRISState *env, DisasContext *dc)
8170028d 2078{
7b5eff4d
EV		 2079 TCGv t[2];
2080 LOG_DIS("move $r%u, $p%u\n", dc->op1, dc->op2);
2081 cris_cc_mask(dc, 0);
2082
2083 t[0] = tcg_temp_new();
2084 if (dc->op2 == PR_CCS) {
2085 cris_evaluate_flags(dc);
08397c4b 2086 tcg_gen_mov_tl(t[0], cpu_R[dc->op1]);
7b5eff4d
EV		 2087 if (dc->tb_flags & U_FLAG) {
2088 t[1] = tcg_temp_new();
2089 /* User space is not allowed to touch all flags. */
2090 tcg_gen_andi_tl(t[0], t[0], 0x39f);
2091 tcg_gen_andi_tl(t[1], cpu_PR[PR_CCS], ~0x39f);
2092 tcg_gen_or_tl(t[0], t[1], t[0]);
2093 tcg_temp_free(t[1]);
2094 }
2095 } else {
08397c4b 2096 tcg_gen_mov_tl(t[0], cpu_R[dc->op1]);
7b5eff4d
EV		 2097 }
2098
2099 t_gen_mov_preg_TN(dc, dc->op2, t[0]);
2100 if (dc->op2 == PR_CCS) {
2101 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2102 dc->flags_uptodate = 1;
2103 }
2104 tcg_temp_free(t[0]);
2105 return 2;
8170028d 2106}
cf7e0c80 2107static int dec_move_pr(CPUCRISState *env, DisasContext *dc)
8170028d 2108{
7b5eff4d
EV		 2109 TCGv t0;
2110 LOG_DIS("move $p%u, $r%u\n", dc->op2, dc->op1);
2111 cris_cc_mask(dc, 0);
2a44f7f1 2112
7b5eff4d
EV		 2113 if (dc->op2 == PR_CCS) {
2114 cris_evaluate_flags(dc);
2115 }
2a44f7f1 2116
7b5eff4d
EV		 2117 if (dc->op2 == PR_DZ) {
2118 tcg_gen_movi_tl(cpu_R[dc->op1], 0);
2119 } else {
2120 t0 = tcg_temp_new();
2121 t_gen_mov_TN_preg(t0, dc->op2);
2122 cris_alu(dc, CC_OP_MOVE,
2123 cpu_R[dc->op1], cpu_R[dc->op1], t0,
2124 preg_sizes[dc->op2]);
2125 tcg_temp_free(t0);
2126 }
2127 return 2;
8170028d
TS		 2128}
2129
cf7e0c80 2130static int dec_move_mr(CPUCRISState *env, DisasContext *dc)
8170028d 2131{
7b5eff4d
EV		 2132 int memsize = memsize_zz(dc);
2133 int insn_len;
2134 LOG_DIS("move.%c [$r%u%s, $r%u\n",
2135 memsize_char(memsize),
2136 dc->op1, dc->postinc ? "+]" : "]",
2137 dc->op2);
2138
2139 if (memsize == 4) {
2140 insn_len = dec_prep_move_m(env, dc, 0, 4, cpu_R[dc->op2]);
2141 cris_cc_mask(dc, CC_MASK_NZ);
2142 cris_update_cc_op(dc, CC_OP_MOVE, 4);
2143 cris_update_cc_x(dc);
2144 cris_update_result(dc, cpu_R[dc->op2]);
2145 } else {
2146 TCGv t0;
2147
2148 t0 = tcg_temp_new();
2149 insn_len = dec_prep_move_m(env, dc, 0, memsize, t0);
2150 cris_cc_mask(dc, CC_MASK_NZ);
2151 cris_alu(dc, CC_OP_MOVE,
2152 cpu_R[dc->op2], cpu_R[dc->op2], t0, memsize);
2153 tcg_temp_free(t0);
2154 }
2155 do_postinc(dc, memsize);
2156 return insn_len;
8170028d
TS		 2157}
2158
31c18d87
EI		 2159static inline void cris_alu_m_alloc_temps(TCGv *t)
2160{
7b5eff4d
EV		 2161 t[0] = tcg_temp_new();
2162 t[1] = tcg_temp_new();
31c18d87
EI		 2163}
2164
2165static inline void cris_alu_m_free_temps(TCGv *t)
2166{
7b5eff4d
EV		 2167 tcg_temp_free(t[0]);
2168 tcg_temp_free(t[1]);
31c18d87
EI		 2169}
2170
cf7e0c80 2171static int dec_movs_m(CPUCRISState *env, DisasContext *dc)
8170028d 2172{
7b5eff4d
EV		 2173 TCGv t[2];
2174 int memsize = memsize_z(dc);
2175 int insn_len;
2176 LOG_DIS("movs.%c [$r%u%s, $r%u\n",
2177 memsize_char(memsize),
2178 dc->op1, dc->postinc ? "+]" : "]",
2179 dc->op2);
8170028d 2180
7b5eff4d
EV		 2181 cris_alu_m_alloc_temps(t);
2182 /* sign extend. */
cf7e0c80 2183 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
7b5eff4d
EV		 2184 cris_cc_mask(dc, CC_MASK_NZ);
2185 cris_alu(dc, CC_OP_MOVE,
2186 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2187 do_postinc(dc, memsize);
2188 cris_alu_m_free_temps(t);
2189 return insn_len;
8170028d
TS		 2190}
2191
cf7e0c80 2192static int dec_addu_m(CPUCRISState *env, DisasContext *dc)
8170028d 2193{
7b5eff4d
EV		 2194 TCGv t[2];
2195 int memsize = memsize_z(dc);
2196 int insn_len;
2197 LOG_DIS("addu.%c [$r%u%s, $r%u\n",
2198 memsize_char(memsize),
2199 dc->op1, dc->postinc ? "+]" : "]",
2200 dc->op2);
8170028d 2201
7b5eff4d
EV		 2202 cris_alu_m_alloc_temps(t);
2203 /* sign extend. */
cf7e0c80 2204 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
7b5eff4d
EV		 2205 cris_cc_mask(dc, CC_MASK_NZVC);
2206 cris_alu(dc, CC_OP_ADD,
2207 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2208 do_postinc(dc, memsize);
2209 cris_alu_m_free_temps(t);
2210 return insn_len;
8170028d
TS		 2211}
2212
cf7e0c80 2213static int dec_adds_m(CPUCRISState *env, DisasContext *dc)
8170028d 2214{
7b5eff4d
EV		 2215 TCGv t[2];
2216 int memsize = memsize_z(dc);
2217 int insn_len;
2218 LOG_DIS("adds.%c [$r%u%s, $r%u\n",
2219 memsize_char(memsize),
2220 dc->op1, dc->postinc ? "+]" : "]",
2221 dc->op2);
8170028d 2222
7b5eff4d
EV		 2223 cris_alu_m_alloc_temps(t);
2224 /* sign extend. */
cf7e0c80 2225 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
7b5eff4d
EV		 2226 cris_cc_mask(dc, CC_MASK_NZVC);
2227 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2228 do_postinc(dc, memsize);
2229 cris_alu_m_free_temps(t);
2230 return insn_len;
8170028d
TS		 2231}
2232
cf7e0c80 2233static int dec_subu_m(CPUCRISState *env, DisasContext *dc)
8170028d 2234{
7b5eff4d
EV		 2235 TCGv t[2];
2236 int memsize = memsize_z(dc);
2237 int insn_len;
2238 LOG_DIS("subu.%c [$r%u%s, $r%u\n",
2239 memsize_char(memsize),
2240 dc->op1, dc->postinc ? "+]" : "]",
2241 dc->op2);
8170028d 2242
7b5eff4d
EV		 2243 cris_alu_m_alloc_temps(t);
2244 /* sign extend. */
cf7e0c80 2245 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
7b5eff4d
EV		 2246 cris_cc_mask(dc, CC_MASK_NZVC);
2247 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2248 do_postinc(dc, memsize);
2249 cris_alu_m_free_temps(t);
2250 return insn_len;
8170028d
TS		 2251}
2252
cf7e0c80 2253static int dec_subs_m(CPUCRISState *env, DisasContext *dc)
8170028d 2254{
7b5eff4d
EV		 2255 TCGv t[2];
2256 int memsize = memsize_z(dc);
2257 int insn_len;
2258 LOG_DIS("subs.%c [$r%u%s, $r%u\n",
2259 memsize_char(memsize),
2260 dc->op1, dc->postinc ? "+]" : "]",
2261 dc->op2);
8170028d 2262
7b5eff4d
EV		 2263 cris_alu_m_alloc_temps(t);
2264 /* sign extend. */
cf7e0c80 2265 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
7b5eff4d
EV		 2266 cris_cc_mask(dc, CC_MASK_NZVC);
2267 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2268 do_postinc(dc, memsize);
2269 cris_alu_m_free_temps(t);
2270 return insn_len;
8170028d
TS		 2271}
2272
cf7e0c80 2273static int dec_movu_m(CPUCRISState *env, DisasContext *dc)
8170028d 2274{
7b5eff4d
EV		 2275 TCGv t[2];
2276 int memsize = memsize_z(dc);
2277 int insn_len;
8170028d 2278
7b5eff4d
EV		 2279 LOG_DIS("movu.%c [$r%u%s, $r%u\n",
2280 memsize_char(memsize),
2281 dc->op1, dc->postinc ? "+]" : "]",
2282 dc->op2);
8170028d 2283
7b5eff4d 2284 cris_alu_m_alloc_temps(t);
cf7e0c80 2285 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
7b5eff4d
EV		 2286 cris_cc_mask(dc, CC_MASK_NZ);
2287 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2288 do_postinc(dc, memsize);
2289 cris_alu_m_free_temps(t);
2290 return insn_len;
8170028d
TS		 2291}
2292
cf7e0c80 2293static int dec_cmpu_m(CPUCRISState *env, DisasContext *dc)
8170028d 2294{
7b5eff4d
EV		 2295 TCGv t[2];
2296 int memsize = memsize_z(dc);
2297 int insn_len;
2298 LOG_DIS("cmpu.%c [$r%u%s, $r%u\n",
2299 memsize_char(memsize),
2300 dc->op1, dc->postinc ? "+]" : "]",
2301 dc->op2);
8170028d 2302
7b5eff4d 2303 cris_alu_m_alloc_temps(t);
cf7e0c80 2304 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
7b5eff4d
EV		 2305 cris_cc_mask(dc, CC_MASK_NZVC);
2306 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2307 do_postinc(dc, memsize);
2308 cris_alu_m_free_temps(t);
2309 return insn_len;
8170028d
TS		 2310}
2311
cf7e0c80 2312static int dec_cmps_m(CPUCRISState *env, DisasContext *dc)
8170028d 2313{
7b5eff4d
EV		 2314 TCGv t[2];
2315 int memsize = memsize_z(dc);
2316 int insn_len;
2317 LOG_DIS("cmps.%c [$r%u%s, $r%u\n",
2318 memsize_char(memsize),
2319 dc->op1, dc->postinc ? "+]" : "]",
2320 dc->op2);
8170028d 2321
7b5eff4d 2322 cris_alu_m_alloc_temps(t);
cf7e0c80 2323 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
7b5eff4d
EV		 2324 cris_cc_mask(dc, CC_MASK_NZVC);
2325 cris_alu(dc, CC_OP_CMP,
2326 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2327 memsize_zz(dc));
2328 do_postinc(dc, memsize);
2329 cris_alu_m_free_temps(t);
2330 return insn_len;
8170028d
TS		 2331}
2332
cf7e0c80 2333static int dec_cmp_m(CPUCRISState *env, DisasContext *dc)
8170028d 2334{
7b5eff4d
EV		 2335 TCGv t[2];
2336 int memsize = memsize_zz(dc);
2337 int insn_len;
2338 LOG_DIS("cmp.%c [$r%u%s, $r%u\n",
2339 memsize_char(memsize),
2340 dc->op1, dc->postinc ? "+]" : "]",
2341 dc->op2);
8170028d 2342
7b5eff4d 2343 cris_alu_m_alloc_temps(t);
cf7e0c80 2344 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
7b5eff4d
EV		 2345 cris_cc_mask(dc, CC_MASK_NZVC);
2346 cris_alu(dc, CC_OP_CMP,
2347 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2348 memsize_zz(dc));
2349 do_postinc(dc, memsize);
2350 cris_alu_m_free_temps(t);
2351 return insn_len;
8170028d
TS		 2352}
2353
cf7e0c80 2354static int dec_test_m(CPUCRISState *env, DisasContext *dc)
8170028d 2355{
7b5eff4d
EV		 2356 TCGv t[2];
2357 int memsize = memsize_zz(dc);
2358 int insn_len;
2359 LOG_DIS("test.%c [$r%u%s] op2=%x\n",
2360 memsize_char(memsize),
2361 dc->op1, dc->postinc ? "+]" : "]",
2362 dc->op2);
8170028d 2363
7b5eff4d 2364 cris_evaluate_flags(dc);
dceaf394 2365
7b5eff4d 2366 cris_alu_m_alloc_temps(t);
cf7e0c80 2367 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
7b5eff4d
EV		 2368 cris_cc_mask(dc, CC_MASK_NZ);
2369 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
b41f7df0 2370
7b5eff4d
EV		 2371 cris_alu(dc, CC_OP_CMP,
2372 cpu_R[dc->op2], t[1], tcg_const_tl(0), memsize_zz(dc));
2373 do_postinc(dc, memsize);
2374 cris_alu_m_free_temps(t);
2375 return insn_len;
8170028d
TS		 2376}
2377
cf7e0c80 2378static int dec_and_m(CPUCRISState *env, DisasContext *dc)
8170028d 2379{
7b5eff4d
EV		 2380 TCGv t[2];
2381 int memsize = memsize_zz(dc);
2382 int insn_len;
2383 LOG_DIS("and.%c [$r%u%s, $r%u\n",
2384 memsize_char(memsize),
2385 dc->op1, dc->postinc ? "+]" : "]",
2386 dc->op2);
8170028d 2387
7b5eff4d 2388 cris_alu_m_alloc_temps(t);
cf7e0c80 2389 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
7b5eff4d
EV		 2390 cris_cc_mask(dc, CC_MASK_NZ);
2391 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2392 do_postinc(dc, memsize);
2393 cris_alu_m_free_temps(t);
2394 return insn_len;
8170028d
TS		 2395}
2396
cf7e0c80 2397static int dec_add_m(CPUCRISState *env, DisasContext *dc)
8170028d 2398{
7b5eff4d
EV		 2399 TCGv t[2];
2400 int memsize = memsize_zz(dc);
2401 int insn_len;
2402 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2403 memsize_char(memsize),
2404 dc->op1, dc->postinc ? "+]" : "]",
2405 dc->op2);
8170028d 2406
7b5eff4d 2407 cris_alu_m_alloc_temps(t);
cf7e0c80 2408 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
7b5eff4d
EV		 2409 cris_cc_mask(dc, CC_MASK_NZVC);
2410 cris_alu(dc, CC_OP_ADD,
2411 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2412 do_postinc(dc, memsize);
2413 cris_alu_m_free_temps(t);
2414 return insn_len;
8170028d
TS		 2415}
2416
cf7e0c80 2417static int dec_addo_m(CPUCRISState *env, DisasContext *dc)
8170028d 2418{
7b5eff4d
EV		 2419 TCGv t[2];
2420 int memsize = memsize_zz(dc);
2421 int insn_len;
2422 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2423 memsize_char(memsize),
2424 dc->op1, dc->postinc ? "+]" : "]",
2425 dc->op2);
8170028d 2426
7b5eff4d 2427 cris_alu_m_alloc_temps(t);
cf7e0c80 2428 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
7b5eff4d
EV		 2429 cris_cc_mask(dc, 0);
2430 cris_alu(dc, CC_OP_ADD, cpu_R[R_ACR], t[0], t[1], 4);
2431 do_postinc(dc, memsize);
2432 cris_alu_m_free_temps(t);
2433 return insn_len;
8170028d
TS		 2434}
2435
cf7e0c80 2436static int dec_bound_m(CPUCRISState *env, DisasContext *dc)
8170028d 2437{
7b5eff4d
EV		 2438 TCGv l[2];
2439 int memsize = memsize_zz(dc);
2440 int insn_len;
2441 LOG_DIS("bound.%c [$r%u%s, $r%u\n",
2442 memsize_char(memsize),
2443 dc->op1, dc->postinc ? "+]" : "]",
2444 dc->op2);
8170028d 2445
7b5eff4d
EV		 2446 l[0] = tcg_temp_local_new();
2447 l[1] = tcg_temp_local_new();
cf7e0c80 2448 insn_len = dec_prep_alu_m(env, dc, 0, memsize, l[0], l[1]);
7b5eff4d
EV		 2449 cris_cc_mask(dc, CC_MASK_NZ);
2450 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], l[0], l[1], 4);
2451 do_postinc(dc, memsize);
2452 tcg_temp_free(l[0]);
2453 tcg_temp_free(l[1]);
2454 return insn_len;
8170028d
TS		 2455}
2456
cf7e0c80 2457static int dec_addc_mr(CPUCRISState *env, DisasContext *dc)
8170028d 2458{
7b5eff4d
EV		 2459 TCGv t[2];
2460 int insn_len = 2;
2461 LOG_DIS("addc [$r%u%s, $r%u\n",
2462 dc->op1, dc->postinc ? "+]" : "]",
2463 dc->op2);
8170028d 2464
7b5eff4d 2465 cris_evaluate_flags(dc);
a8cf66bb 2466
7b5eff4d
EV		 2467 /* Set for this insn. */
2468 dc->flagx_known = 1;
2469 dc->flags_x = X_FLAG;
a8cf66bb 2470
7b5eff4d 2471 cris_alu_m_alloc_temps(t);
cf7e0c80 2472 insn_len = dec_prep_alu_m(env, dc, 0, 4, t[0], t[1]);
7b5eff4d
EV		 2473 cris_cc_mask(dc, CC_MASK_NZVC);
2474 cris_alu(dc, CC_OP_ADDC, cpu_R[dc->op2], t[0], t[1], 4);
2475 do_postinc(dc, 4);
2476 cris_alu_m_free_temps(t);
2477 return insn_len;
8170028d
TS		 2478}
2479
cf7e0c80 2480static int dec_sub_m(CPUCRISState *env, DisasContext *dc)
8170028d 2481{
7b5eff4d
EV		 2482 TCGv t[2];
2483 int memsize = memsize_zz(dc);
2484 int insn_len;
2485 LOG_DIS("sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2486 memsize_char(memsize),
2487 dc->op1, dc->postinc ? "+]" : "]",
2488 dc->op2, dc->ir, dc->zzsize);
8170028d 2489
7b5eff4d 2490 cris_alu_m_alloc_temps(t);
cf7e0c80 2491 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
7b5eff4d
EV		 2492 cris_cc_mask(dc, CC_MASK_NZVC);
2493 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], memsize);
2494 do_postinc(dc, memsize);
2495 cris_alu_m_free_temps(t);
2496 return insn_len;
8170028d
TS		 2497}
2498
cf7e0c80 2499static int dec_or_m(CPUCRISState *env, DisasContext *dc)
8170028d 2500{
7b5eff4d
EV		 2501 TCGv t[2];
2502 int memsize = memsize_zz(dc);
2503 int insn_len;
2504 LOG_DIS("or.%c [$r%u%s, $r%u pc=%x\n",
2505 memsize_char(memsize),
2506 dc->op1, dc->postinc ? "+]" : "]",
2507 dc->op2, dc->pc);
8170028d 2508
7b5eff4d 2509 cris_alu_m_alloc_temps(t);
cf7e0c80 2510 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
7b5eff4d
EV		 2511 cris_cc_mask(dc, CC_MASK_NZ);
2512 cris_alu(dc, CC_OP_OR,
2513 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2514 do_postinc(dc, memsize);
2515 cris_alu_m_free_temps(t);
2516 return insn_len;
8170028d
TS		 2517}
2518
cf7e0c80 2519static int dec_move_mp(CPUCRISState *env, DisasContext *dc)
8170028d 2520{
7b5eff4d
EV		 2521 TCGv t[2];
2522 int memsize = memsize_zz(dc);
2523 int insn_len = 2;
8170028d 2524
7b5eff4d
EV		 2525 LOG_DIS("move.%c [$r%u%s, $p%u\n",
2526 memsize_char(memsize),
2527 dc->op1,
2528 dc->postinc ? "+]" : "]",
2529 dc->op2);
8170028d 2530
7b5eff4d 2531 cris_alu_m_alloc_temps(t);
cf7e0c80 2532 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
7b5eff4d
EV		 2533 cris_cc_mask(dc, 0);
2534 if (dc->op2 == PR_CCS) {
2535 cris_evaluate_flags(dc);
2536 if (dc->tb_flags & U_FLAG) {
2537 /* User space is not allowed to touch all flags. */
2538 tcg_gen_andi_tl(t[1], t[1], 0x39f);
2539 tcg_gen_andi_tl(t[0], cpu_PR[PR_CCS], ~0x39f);
2540 tcg_gen_or_tl(t[1], t[0], t[1]);
2541 }
2542 }
b41f7df0 2543
7b5eff4d 2544 t_gen_mov_preg_TN(dc, dc->op2, t[1]);
8170028d 2545
7b5eff4d
EV		 2546 do_postinc(dc, memsize);
2547 cris_alu_m_free_temps(t);
2548 return insn_len;
8170028d
TS		 2549}
2550
cf7e0c80 2551static int dec_move_pm(CPUCRISState *env, DisasContext *dc)
8170028d 2552{
7b5eff4d
EV		 2553 TCGv t0;
2554 int memsize;
8170028d 2555
7b5eff4d 2556 memsize = preg_sizes[dc->op2];
8170028d 2557
7b5eff4d
EV		 2558 LOG_DIS("move.%c $p%u, [$r%u%s\n",
2559 memsize_char(memsize),
2560 dc->op2, dc->op1, dc->postinc ? "+]" : "]");
8170028d 2561
7b5eff4d
EV		 2562 /* prepare store. Address in T0, value in T1. */
2563 if (dc->op2 == PR_CCS) {
2564 cris_evaluate_flags(dc);
2565 }
2566 t0 = tcg_temp_new();
2567 t_gen_mov_TN_preg(t0, dc->op2);
2568 cris_flush_cc_state(dc);
2569 gen_store(dc, cpu_R[dc->op1], t0, memsize);
2570 tcg_temp_free(t0);
2571
2572 cris_cc_mask(dc, 0);
2573 if (dc->postinc) {
2574 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2575 }
2576 return 2;
8170028d
TS		 2577}
2578
cf7e0c80 2579static int dec_movem_mr(CPUCRISState *env, DisasContext *dc)
8170028d 2580{
7b5eff4d
EV		 2581 TCGv_i64 tmp[16];
2582 TCGv tmp32;
2583 TCGv addr;
2584 int i;
2585 int nr = dc->op2 + 1;
2586
2587 LOG_DIS("movem [$r%u%s, $r%u\n", dc->op1,
2588 dc->postinc ? "+]" : "]", dc->op2);
2589
2590 addr = tcg_temp_new();
2591 /* There are probably better ways of doing this. */
2592 cris_flush_cc_state(dc);
2593 for (i = 0; i < (nr >> 1); i++) {
2594 tmp[i] = tcg_temp_new_i64();
2595 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2596 gen_load64(dc, tmp[i], addr);
2597 }
2598 if (nr & 1) {
2599 tmp32 = tcg_temp_new_i32();
2600 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2601 gen_load(dc, tmp32, addr, 4, 0);
2602 } else {
f764718d 2603 tmp32 = NULL;
7b5eff4d
EV		 2604 }
2605 tcg_temp_free(addr);
2606
2607 for (i = 0; i < (nr >> 1); i++) {
ecc7b3aa 2608 tcg_gen_extrl_i64_i32(cpu_R[i * 2], tmp[i]);
7b5eff4d 2609 tcg_gen_shri_i64(tmp[i], tmp[i], 32);
ecc7b3aa 2610 tcg_gen_extrl_i64_i32(cpu_R[i * 2 + 1], tmp[i]);
7b5eff4d
EV		 2611 tcg_temp_free_i64(tmp[i]);
2612 }
2613 if (nr & 1) {
2614 tcg_gen_mov_tl(cpu_R[dc->op2], tmp32);
2615 tcg_temp_free(tmp32);
2616 }
2617
2618 /* writeback the updated pointer value. */
2619 if (dc->postinc) {
2620 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], nr * 4);
2621 }
2622
2623 /* gen_load might want to evaluate the previous insns flags. */
2624 cris_cc_mask(dc, 0);
2625 return 2;
8170028d
TS		 2626}
2627
cf7e0c80 2628static int dec_movem_rm(CPUCRISState *env, DisasContext *dc)
8170028d 2629{
7b5eff4d
EV		 2630 TCGv tmp;
2631 TCGv addr;
2632 int i;
2633
2634 LOG_DIS("movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
2635 dc->postinc ? "+]" : "]");
2636
2637 cris_flush_cc_state(dc);
2638
2639 tmp = tcg_temp_new();
2640 addr = tcg_temp_new();
2641 tcg_gen_movi_tl(tmp, 4);
2642 tcg_gen_mov_tl(addr, cpu_R[dc->op1]);
2643 for (i = 0; i <= dc->op2; i++) {
2644 /* Displace addr. */
2645 /* Perform the store. */
2646 gen_store(dc, addr, cpu_R[i], 4);
2647 tcg_gen_add_tl(addr, addr, tmp);
2648 }
2649 if (dc->postinc) {
2650 tcg_gen_mov_tl(cpu_R[dc->op1], addr);
2651 }
2652 cris_cc_mask(dc, 0);
2653 tcg_temp_free(tmp);
2654 tcg_temp_free(addr);
2655 return 2;
8170028d
TS		 2656}
2657
cf7e0c80 2658static int dec_move_rm(CPUCRISState *env, DisasContext *dc)
8170028d 2659{
7b5eff4d 2660 int memsize;
8170028d 2661
7b5eff4d 2662 memsize = memsize_zz(dc);
8170028d 2663
7b5eff4d
EV		 2664 LOG_DIS("move.%c $r%u, [$r%u]\n",
2665 memsize_char(memsize), dc->op2, dc->op1);
8170028d 2666
7b5eff4d
EV		 2667 /* prepare store. */
2668 cris_flush_cc_state(dc);
2669 gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize);
17ac9754 2670
7b5eff4d
EV		 2671 if (dc->postinc) {
2672 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2673 }
2674 cris_cc_mask(dc, 0);
2675 return 2;
8170028d
TS		 2676}
2677
cf7e0c80 2678static int dec_lapcq(CPUCRISState *env, DisasContext *dc)
8170028d 2679{
7b5eff4d
EV		 2680 LOG_DIS("lapcq %x, $r%u\n",
2681 dc->pc + dc->op1*2, dc->op2);
2682 cris_cc_mask(dc, 0);
2683 tcg_gen_movi_tl(cpu_R[dc->op2], dc->pc + dc->op1 * 2);
2684 return 2;
8170028d
TS		 2685}
2686
cf7e0c80 2687static int dec_lapc_im(CPUCRISState *env, DisasContext *dc)
8170028d 2688{
7b5eff4d
EV		 2689 unsigned int rd;
2690 int32_t imm;
2691 int32_t pc;
8170028d 2692
7b5eff4d 2693 rd = dc->op2;
8170028d 2694
7b5eff4d
EV		 2695 cris_cc_mask(dc, 0);
2696 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2697 LOG_DIS("lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2);
b41f7df0 2698
7b5eff4d
EV		 2699 pc = dc->pc;
2700 pc += imm;
2701 tcg_gen_movi_tl(cpu_R[rd], pc);
2702 return 6;
8170028d
TS		 2703}
2704
2705/* Jump to special reg. */
cf7e0c80 2706static int dec_jump_p(CPUCRISState *env, DisasContext *dc)
8170028d 2707{
7b5eff4d 2708 LOG_DIS("jump $p%u\n", dc->op2);
b41f7df0 2709
7b5eff4d
EV		 2710 if (dc->op2 == PR_CCS) {
2711 cris_evaluate_flags(dc);
2712 }
2713 t_gen_mov_TN_preg(env_btarget, dc->op2);
2714 /* rete will often have low bit set to indicate delayslot. */
2715 tcg_gen_andi_tl(env_btarget, env_btarget, ~1);
2716 cris_cc_mask(dc, 0);
2717 cris_prepare_jmp(dc, JMP_INDIRECT);
2718 return 2;
8170028d
TS		 2719}
2720
2721/* Jump and save. */
cf7e0c80 2722static int dec_jas_r(CPUCRISState *env, DisasContext *dc)
8170028d 2723{
7b5eff4d
EV		 2724 LOG_DIS("jas $r%u, $p%u\n", dc->op1, dc->op2);
2725 cris_cc_mask(dc, 0);
2726 /* Store the return address in Pd. */
2727 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2728 if (dc->op2 > 15) {
2729 abort();
2730 }
2731 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4));
b41f7df0 2732
7b5eff4d
EV		 2733 cris_prepare_jmp(dc, JMP_INDIRECT);
2734 return 2;
8170028d
TS		 2735}
2736
cf7e0c80 2737static int dec_jas_im(CPUCRISState *env, DisasContext *dc)
8170028d 2738{
7b5eff4d 2739 uint32_t imm;
8170028d 2740
7b5eff4d 2741 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
8170028d 2742
7b5eff4d
EV		 2743 LOG_DIS("jas 0x%x\n", imm);
2744 cris_cc_mask(dc, 0);
2745 /* Store the return address in Pd. */
2746 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2a44f7f1 2747
7b5eff4d
EV		 2748 dc->jmp_pc = imm;
2749 cris_prepare_jmp(dc, JMP_DIRECT);
2750 return 6;
8170028d
TS		 2751}
2752
cf7e0c80 2753static int dec_jasc_im(CPUCRISState *env, DisasContext *dc)
8170028d 2754{
7b5eff4d 2755 uint32_t imm;
8170028d 2756
7b5eff4d 2757 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
8170028d 2758
7b5eff4d
EV		 2759 LOG_DIS("jasc 0x%x\n", imm);
2760 cris_cc_mask(dc, 0);
2761 /* Store the return address in Pd. */
2762 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8 + 4));
2a44f7f1 2763
7b5eff4d
EV		 2764 dc->jmp_pc = imm;
2765 cris_prepare_jmp(dc, JMP_DIRECT);
2766 return 6;
8170028d
TS		 2767}
2768
cf7e0c80 2769static int dec_jasc_r(CPUCRISState *env, DisasContext *dc)
8170028d 2770{
7b5eff4d
EV		 2771 LOG_DIS("jasc_r $r%u, $p%u\n", dc->op1, dc->op2);
2772 cris_cc_mask(dc, 0);
2773 /* Store the return address in Pd. */
2774 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2775 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4 + 4));
2776 cris_prepare_jmp(dc, JMP_INDIRECT);
2777 return 2;
8170028d
TS		 2778}
2779
cf7e0c80 2780static int dec_bcc_im(CPUCRISState *env, DisasContext *dc)
8170028d 2781{
7b5eff4d
EV		 2782 int32_t offset;
2783 uint32_t cond = dc->op2;
8170028d 2784
7b5eff4d 2785 offset = cris_fetch(env, dc, dc->pc + 2, 2, 1);
8170028d 2786
7b5eff4d
EV		 2787 LOG_DIS("b%s %d pc=%x dst=%x\n",
2788 cc_name(cond), offset,
2789 dc->pc, dc->pc + offset);
8170028d 2790
7b5eff4d
EV		 2791 cris_cc_mask(dc, 0);
2792 /* op2 holds the condition-code. */
2793 cris_prepare_cc_branch(dc, offset, cond);
2794 return 4;
8170028d
TS		 2795}
2796
cf7e0c80 2797static int dec_bas_im(CPUCRISState *env, DisasContext *dc)
8170028d 2798{
7b5eff4d 2799 int32_t simm;
8170028d 2800
7b5eff4d 2801 simm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
8170028d 2802
7b5eff4d
EV		 2803 LOG_DIS("bas 0x%x, $p%u\n", dc->pc + simm, dc->op2);
2804 cris_cc_mask(dc, 0);
2805 /* Store the return address in Pd. */
2806 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
8170028d 2807
7b5eff4d
EV		 2808 dc->jmp_pc = dc->pc + simm;
2809 cris_prepare_jmp(dc, JMP_DIRECT);
2810 return 6;
8170028d
TS		 2811}
2812
cf7e0c80 2813static int dec_basc_im(CPUCRISState *env, DisasContext *dc)
8170028d 2814{
7b5eff4d
EV		 2815 int32_t simm;
2816 simm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
8170028d 2817
7b5eff4d
EV		 2818 LOG_DIS("basc 0x%x, $p%u\n", dc->pc + simm, dc->op2);
2819 cris_cc_mask(dc, 0);
2820 /* Store the return address in Pd. */
2821 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 12));
2a44f7f1 2822
7b5eff4d
EV		 2823 dc->jmp_pc = dc->pc + simm;
2824 cris_prepare_jmp(dc, JMP_DIRECT);
2825 return 6;
8170028d
TS		 2826}
2827
cf7e0c80 2828static int dec_rfe_etc(CPUCRISState *env, DisasContext *dc)
8170028d 2829{
7b5eff4d
EV		 2830 cris_cc_mask(dc, 0);
2831
2832 if (dc->op2 == 15) {
259186a7
AF		 2833 tcg_gen_st_i32(tcg_const_i32(1), cpu_env,
2834 -offsetof(CRISCPU, env) + offsetof(CPUState, halted));
7b5eff4d
EV		 2835 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2836 t_gen_raise_exception(EXCP_HLT);
2837 return 2;
2838 }
2839
2840 switch (dc->op2 & 7) {
2841 case 2:
2842 /* rfe. */
2843 LOG_DIS("rfe\n");
2844 cris_evaluate_flags(dc);
2845 gen_helper_rfe(cpu_env);
2846 dc->is_jmp = DISAS_UPDATE;
2847 break;
2848 case 5:
2849 /* rfn. */
2850 LOG_DIS("rfn\n");
2851 cris_evaluate_flags(dc);
2852 gen_helper_rfn(cpu_env);
2853 dc->is_jmp = DISAS_UPDATE;
2854 break;
2855 case 6:
2856 LOG_DIS("break %d\n", dc->op1);
2857 cris_evaluate_flags(dc);
2858 /* break. */
2859 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2860
2861 /* Breaks start at 16 in the exception vector. */
2862 t_gen_mov_env_TN(trap_vector,
2863 tcg_const_tl(dc->op1 + 16));
2864 t_gen_raise_exception(EXCP_BREAK);
2865 dc->is_jmp = DISAS_UPDATE;
2866 break;
2867 default:
2868 printf("op2=%x\n", dc->op2);
2869 BUG();
2870 break;
2871
2872 }
2873 return 2;
8170028d
TS		 2874}
2875
cf7e0c80 2876static int dec_ftag_fidx_d_m(CPUCRISState *env, DisasContext *dc)
5d4a534d 2877{
7b5eff4d 2878 return 2;
5d4a534d
EI		 2879}
2880
cf7e0c80 2881static int dec_ftag_fidx_i_m(CPUCRISState *env, DisasContext *dc)
5d4a534d 2882{
7b5eff4d 2883 return 2;
5d4a534d
EI		 2884}
2885
cf7e0c80 2886static int dec_null(CPUCRISState *env, DisasContext *dc)
8170028d 2887{
7b5eff4d
EV		 2888 printf("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2889 dc->pc, dc->opcode, dc->op1, dc->op2);
2890 fflush(NULL);
2891 BUG();
2892 return 2;
8170028d
TS		 2893}
2894
9b32fbf8 2895static struct decoder_info {
7b5eff4d
EV		 2896 struct {
2897 uint32_t bits;
2898 uint32_t mask;
2899 };
2900 int (*dec)(CPUCRISState *env, DisasContext *dc);
8170028d 2901} decinfo[] = {
7b5eff4d
EV		 2902 /* Order matters here. */
2903 {DEC_MOVEQ, dec_moveq},
2904 {DEC_BTSTQ, dec_btstq},
2905 {DEC_CMPQ, dec_cmpq},
2906 {DEC_ADDOQ, dec_addoq},
2907 {DEC_ADDQ, dec_addq},
2908 {DEC_SUBQ, dec_subq},
2909 {DEC_ANDQ, dec_andq},
2910 {DEC_ORQ, dec_orq},
2911 {DEC_ASRQ, dec_asrq},
2912 {DEC_LSLQ, dec_lslq},
2913 {DEC_LSRQ, dec_lsrq},
2914 {DEC_BCCQ, dec_bccq},
2915
2916 {DEC_BCC_IM, dec_bcc_im},
2917 {DEC_JAS_IM, dec_jas_im},
2918 {DEC_JAS_R, dec_jas_r},
2919 {DEC_JASC_IM, dec_jasc_im},
2920 {DEC_JASC_R, dec_jasc_r},
2921 {DEC_BAS_IM, dec_bas_im},
2922 {DEC_BASC_IM, dec_basc_im},
2923 {DEC_JUMP_P, dec_jump_p},
2924 {DEC_LAPC_IM, dec_lapc_im},
2925 {DEC_LAPCQ, dec_lapcq},
2926
2927 {DEC_RFE_ETC, dec_rfe_etc},
2928 {DEC_ADDC_MR, dec_addc_mr},
2929
2930 {DEC_MOVE_MP, dec_move_mp},
2931 {DEC_MOVE_PM, dec_move_pm},
2932 {DEC_MOVEM_MR, dec_movem_mr},
2933 {DEC_MOVEM_RM, dec_movem_rm},
2934 {DEC_MOVE_PR, dec_move_pr},
2935 {DEC_SCC_R, dec_scc_r},
2936 {DEC_SETF, dec_setclrf},
2937 {DEC_CLEARF, dec_setclrf},
2938
2939 {DEC_MOVE_SR, dec_move_sr},
2940 {DEC_MOVE_RP, dec_move_rp},
2941 {DEC_SWAP_R, dec_swap_r},
2942 {DEC_ABS_R, dec_abs_r},
2943 {DEC_LZ_R, dec_lz_r},
2944 {DEC_MOVE_RS, dec_move_rs},
2945 {DEC_BTST_R, dec_btst_r},
2946 {DEC_ADDC_R, dec_addc_r},
2947
2948 {DEC_DSTEP_R, dec_dstep_r},
2949 {DEC_XOR_R, dec_xor_r},
2950 {DEC_MCP_R, dec_mcp_r},
2951 {DEC_CMP_R, dec_cmp_r},
2952
2953 {DEC_ADDI_R, dec_addi_r},
2954 {DEC_ADDI_ACR, dec_addi_acr},
2955
2956 {DEC_ADD_R, dec_add_r},
2957 {DEC_SUB_R, dec_sub_r},
2958
2959 {DEC_ADDU_R, dec_addu_r},
2960 {DEC_ADDS_R, dec_adds_r},
2961 {DEC_SUBU_R, dec_subu_r},
2962 {DEC_SUBS_R, dec_subs_r},
2963 {DEC_LSL_R, dec_lsl_r},
2964
2965 {DEC_AND_R, dec_and_r},
2966 {DEC_OR_R, dec_or_r},
2967 {DEC_BOUND_R, dec_bound_r},
2968 {DEC_ASR_R, dec_asr_r},
2969 {DEC_LSR_R, dec_lsr_r},
2970
2971 {DEC_MOVU_R, dec_movu_r},
2972 {DEC_MOVS_R, dec_movs_r},
2973 {DEC_NEG_R, dec_neg_r},
2974 {DEC_MOVE_R, dec_move_r},
2975
2976 {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m},
2977 {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m},
2978
2979 {DEC_MULS_R, dec_muls_r},
2980 {DEC_MULU_R, dec_mulu_r},
2981
2982 {DEC_ADDU_M, dec_addu_m},
2983 {DEC_ADDS_M, dec_adds_m},
2984 {DEC_SUBU_M, dec_subu_m},
2985 {DEC_SUBS_M, dec_subs_m},
2986
2987 {DEC_CMPU_M, dec_cmpu_m},
2988 {DEC_CMPS_M, dec_cmps_m},
2989 {DEC_MOVU_M, dec_movu_m},
2990 {DEC_MOVS_M, dec_movs_m},
2991
2992 {DEC_CMP_M, dec_cmp_m},
2993 {DEC_ADDO_M, dec_addo_m},
2994 {DEC_BOUND_M, dec_bound_m},
2995 {DEC_ADD_M, dec_add_m},
2996 {DEC_SUB_M, dec_sub_m},
2997 {DEC_AND_M, dec_and_m},
2998 {DEC_OR_M, dec_or_m},
2999 {DEC_MOVE_RM, dec_move_rm},
3000 {DEC_TEST_M, dec_test_m},
3001 {DEC_MOVE_MR, dec_move_mr},
3002
3003 {{0, 0}, dec_null}
8170028d
TS		 3004};
3005
cf7e0c80 3006static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc)
8170028d 3007{
7b5eff4d
EV		 3008 int insn_len = 2;
3009 int i;
8170028d 3010
7b5eff4d 3011 /* Load a halfword onto the instruction register. */
cf7e0c80 3012 dc->ir = cris_fetch(env, dc, dc->pc, 2, 0);
8170028d 3013
7b5eff4d
EV		 3014 /* Now decode it. */
3015 dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
3016 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3);
3017 dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15);
3018 dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4);
3019 dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5);
3020 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
3021
3022 /* Large switch for all insns. */
3023 for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
3024 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) {
3025 insn_len = decinfo[i].dec(env, dc);
3026 break;
3027 }
3028 }
8170028d 3029
dd20fcd0 3030#if !defined(CONFIG_USER_ONLY)
7b5eff4d
EV		 3031 /* Single-stepping ? */
3032 if (dc->tb_flags & S_FLAG) {
42a268c2 3033 TCGLabel *l1 = gen_new_label();
7b5eff4d
EV		 3034 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_PR[PR_SPC], dc->pc, l1);
3035 /* We treat SPC as a break with an odd trap vector. */
3036 cris_evaluate_flags(dc);
3037 t_gen_mov_env_TN(trap_vector, tcg_const_tl(3));
3038 tcg_gen_movi_tl(env_pc, dc->pc + insn_len);
3039 tcg_gen_movi_tl(cpu_PR[PR_SPC], dc->pc + insn_len);
3040 t_gen_raise_exception(EXCP_BREAK);
3041 gen_set_label(l1);
3042 }
a1aebcb8 3043#endif
7b5eff4d 3044 return insn_len;
8170028d
TS		 3045}
3046
5b27a92d 3047#include "translate_v10.inc.c"
cf1d97f0
EI		 3048
3049/*
3050 * Delay slots on QEMU/CRIS.
3051 *
3052 * If an exception hits on a delayslot, the core will let ERP (the Exception
3053 * Return Pointer) point to the branch (the previous) insn and set the lsb to
3054 * to give SW a hint that the exception actually hit on the dslot.
3055 *
3056 * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by
3057 * the core and any jmp to an odd addresses will mask off that lsb. It is
3058 * simply there to let sw know there was an exception on a dslot.
3059 *
3060 * When the software returns from an exception, the branch will re-execute.
3061 * On QEMU care needs to be taken when a branch+delayslot sequence is broken
cb8d4c8f 3062 * and the branch and delayslot don't share pages.
cf1d97f0
EI		 3063 *
3064 * The TB contaning the branch insn will set up env->btarget and evaluate
3065 * env->btaken. When the translation loop exits we will note that the branch
3066 * sequence is broken and let env->dslot be the size of the branch insn (those
3067 * vary in length).
3068 *
3069 * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
3070 * set). It will also expect to have env->dslot setup with the size of the
3071 * delay slot so that env->pc - env->dslot point to the branch insn. This TB
3072 * will execute the dslot and take the branch, either to btarget or just one
3073 * insn ahead.
3074 *
3075 * When exceptions occur, we check for env->dslot in do_interrupt to detect
3076 * broken branch sequences and setup $erp accordingly (i.e let it point to the
3077 * branch and set lsb). Then env->dslot gets cleared so that the exception
3078 * handler can enter. When returning from exceptions (jump $erp) the lsb gets
3079 * masked off and we will reexecute the branch insn.
3080 *
3081 */
3082
8170028d 3083/* generate intermediate code for basic block 'tb'. */
9c489ea6 3084void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
8170028d 3085{
9c489ea6 3086 CPUCRISState *env = cs->env_ptr;
7b5eff4d
EV		 3087 uint32_t pc_start;
3088 unsigned int insn_len;
7b5eff4d
EV		 3089 struct DisasContext ctx;
3090 struct DisasContext *dc = &ctx;
3ac5e413 3091 uint32_t page_start;
7b5eff4d
EV		 3092 target_ulong npc;
3093 int num_insns;
3094 int max_insns;
3095
7b5eff4d
EV		 3096 if (env->pregs[PR_VR] == 32) {
3097 dc->decoder = crisv32_decoder;
3098 dc->clear_locked_irq = 0;
3099 } else {
3100 dc->decoder = crisv10_decoder;
3101 dc->clear_locked_irq = 1;
3102 }
3103
3104 /* Odd PC indicates that branch is rexecuting due to exception in the
3105 * delayslot, like in real hw.
3106 */
3107 pc_start = tb->pc & ~1;
9c489ea6 3108 dc->cpu = cris_env_get_cpu(env);
7b5eff4d
EV		 3109 dc->tb = tb;
3110
7b5eff4d
EV		 3111 dc->is_jmp = DISAS_NEXT;
3112 dc->ppc = pc_start;
3113 dc->pc = pc_start;
ed2803da 3114 dc->singlestep_enabled = cs->singlestep_enabled;
7b5eff4d
EV		 3115 dc->flags_uptodate = 1;
3116 dc->flagx_known = 1;
3117 dc->flags_x = tb->flags & X_FLAG;
3118 dc->cc_x_uptodate = 0;
3119 dc->cc_mask = 0;
3120 dc->update_cc = 0;
3121 dc->clear_prefix = 0;
3122
3123 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
3124 dc->cc_size_uptodate = -1;
3125
3126 /* Decode TB flags. */
3127 dc->tb_flags = tb->flags & (S_FLAG | P_FLAG | U_FLAG \
3128 | X_FLAG | PFIX_FLAG);
3129 dc->delayed_branch = !!(tb->flags & 7);
3130 if (dc->delayed_branch) {
3131 dc->jmp = JMP_INDIRECT;
3132 } else {
3133 dc->jmp = JMP_NOJMP;
3134 }
3135
3136 dc->cpustate_changed = 0;
3137
3ac5e413 3138 page_start = pc_start & TARGET_PAGE_MASK;
7b5eff4d 3139 num_insns = 0;
c5a49c63 3140 max_insns = tb_cflags(tb) & CF_COUNT_MASK;
7b5eff4d
EV		 3141 if (max_insns == 0) {
3142 max_insns = CF_COUNT_MASK;
3143 }
190ce7fb
RH		 3144 if (max_insns > TCG_MAX_INSNS) {
3145 max_insns = TCG_MAX_INSNS;
3146 }
7b5eff4d 3147
cd42d5b2 3148 gen_tb_start(tb);
7b5eff4d 3149 do {
bd03c791
RH		 3150 tcg_gen_insn_start(dc->delayed_branch == 1
3151 ? dc->ppc | 1 : dc->pc);
959082fc 3152 num_insns++;
7b5eff4d 3153
b933066a
RH		 3154 if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
3155 cris_evaluate_flags(dc);
3156 tcg_gen_movi_tl(env_pc, dc->pc);
3157 t_gen_raise_exception(EXCP_DEBUG);
3158 dc->is_jmp = DISAS_UPDATE;
522a0d4e
RH		 3159 /* The address covered by the breakpoint must be included in
3160 [tb->pc, tb->pc + tb->size) in order to for it to be
3161 properly cleared -- thus we increment the PC here so that
3162 the logic setting tb->size below does the right thing. */
3163 dc->pc += 2;
b933066a
RH		 3164 break;
3165 }
3166
7b5eff4d
EV		 3167 /* Pretty disas. */
3168 LOG_DIS("%8.8x:\t", dc->pc);
3169
c5a49c63 3170 if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
7b5eff4d
EV		 3171 gen_io_start();
3172 }
3173 dc->clear_x = 1;
3174
3175 insn_len = dc->decoder(env, dc);
3176 dc->ppc = dc->pc;
3177 dc->pc += insn_len;
3178 if (dc->clear_x) {
3179 cris_clear_x_flag(dc);
3180 }
3181
7b5eff4d
EV		 3182 /* Check for delayed branches here. If we do it before
3183 actually generating any host code, the simulator will just
3184 loop doing nothing for on this program location. */
3185 if (dc->delayed_branch) {
3186 dc->delayed_branch--;
3187 if (dc->delayed_branch == 0) {
3188 if (tb->flags & 7) {
3189 t_gen_mov_env_TN(dslot, tcg_const_tl(0));
3190 }
3191 if (dc->cpustate_changed || !dc->flagx_known
3192 || (dc->flags_x != (tb->flags & X_FLAG))) {
3193 cris_store_direct_jmp(dc);
3194 }
3195
3196 if (dc->clear_locked_irq) {
3197 dc->clear_locked_irq = 0;
3198 t_gen_mov_env_TN(locked_irq, tcg_const_tl(0));
3199 }
3200
3201 if (dc->jmp == JMP_DIRECT_CC) {
42a268c2 3202 TCGLabel *l1 = gen_new_label();
7b5eff4d
EV		 3203 cris_evaluate_flags(dc);
3204
3205 /* Conditional jmp. */
3206 tcg_gen_brcondi_tl(TCG_COND_EQ,
3207 env_btaken, 0, l1);
3208 gen_goto_tb(dc, 1, dc->jmp_pc);
3209 gen_set_label(l1);
3210 gen_goto_tb(dc, 0, dc->pc);
3211 dc->is_jmp = DISAS_TB_JUMP;
3212 dc->jmp = JMP_NOJMP;
3213 } else if (dc->jmp == JMP_DIRECT) {
3214 cris_evaluate_flags(dc);
3215 gen_goto_tb(dc, 0, dc->jmp_pc);
3216 dc->is_jmp = DISAS_TB_JUMP;
3217 dc->jmp = JMP_NOJMP;
3218 } else {
3219 t_gen_cc_jmp(env_btarget, tcg_const_tl(dc->pc));
3220 dc->is_jmp = DISAS_JUMP;
3221 }
3222 break;
3223 }
3224 }
3225
3226 /* If we are rexecuting a branch due to exceptions on
cb8d4c8f 3227 delay slots don't break. */
ed2803da 3228 if (!(tb->pc & 1) && cs->singlestep_enabled) {
7b5eff4d
EV		 3229 break;
3230 }
3231 } while (!dc->is_jmp && !dc->cpustate_changed
fe700adb 3232 && !tcg_op_buf_full()
7b5eff4d 3233 && !singlestep
3ac5e413 3234 && (dc->pc - page_start < TARGET_PAGE_SIZE)
7b5eff4d
EV		 3235 && num_insns < max_insns);
3236
3237 if (dc->clear_locked_irq) {
3238 t_gen_mov_env_TN(locked_irq, tcg_const_tl(0));
3239 }
3240
3241 npc = dc->pc;
2a44f7f1 3242
c5a49c63 3243 if (tb_cflags(tb) & CF_LAST_IO)
2e70f6ef 3244 gen_io_end();
7b5eff4d
EV		 3245 /* Force an update if the per-tb cpu state has changed. */
3246 if (dc->is_jmp == DISAS_NEXT
3247 && (dc->cpustate_changed || !dc->flagx_known
3248 || (dc->flags_x != (tb->flags & X_FLAG)))) {
3249 dc->is_jmp = DISAS_UPDATE;
3250 tcg_gen_movi_tl(env_pc, npc);
3251 }
3252 /* Broken branch+delayslot sequence. */
3253 if (dc->delayed_branch == 1) {
3254 /* Set env->dslot to the size of the branch insn. */
3255 t_gen_mov_env_TN(dslot, tcg_const_tl(dc->pc - dc->ppc));
3256 cris_store_direct_jmp(dc);
3257 }
3258
3259 cris_evaluate_flags(dc);
3260
ed2803da 3261 if (unlikely(cs->singlestep_enabled)) {
7b5eff4d
EV		 3262 if (dc->is_jmp == DISAS_NEXT) {
3263 tcg_gen_movi_tl(env_pc, npc);
3264 }
3265 t_gen_raise_exception(EXCP_DEBUG);
3266 } else {
3267 switch (dc->is_jmp) {
3268 case DISAS_NEXT:
3269 gen_goto_tb(dc, 1, npc);
3270 break;
3271 default:
3272 case DISAS_JUMP:
3273 case DISAS_UPDATE:
3274 /* indicate that the hash table must be used
3275 to find the next TB */
07ea28b4 3276 tcg_gen_exit_tb(NULL, 0);
7b5eff4d
EV		 3277 break;
3278 case DISAS_SWI:
3279 case DISAS_TB_JUMP:
3280 /* nothing more to generate */
3281 break;
3282 }
3283 }
806f352d 3284 gen_tb_end(tb, num_insns);
0a7df5da 3285
4e5e1215
RH		 3286 tb->size = dc->pc - pc_start;
3287 tb->icount = num_insns;
8170028d
TS		 3288
3289#ifdef DEBUG_DISAS
a1aebcb8 3290#if !DISAS_CRIS
4910e6e4
RH		 3291 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
3292 && qemu_log_in_addr_range(pc_start)) {
1ee73216 3293 qemu_log_lock();
aab9eb2b
RH		 3294 qemu_log("--------------\n");
3295 qemu_log("IN: %s\n", lookup_symbol(pc_start));
1d48474d 3296 log_target_disas(cs, pc_start, dc->pc - pc_start);
1ee73216 3297 qemu_log_unlock();
7b5eff4d 3298 }
8170028d 3299#endif
a1aebcb8 3300#endif
8170028d
TS		 3301}
3302
90c84c56 3303void cris_cpu_dump_state(CPUState *cs, FILE *f, int flags)
8170028d 3304{
878096ee
AF		 3305 CRISCPU *cpu = CRIS_CPU(cs);
3306 CPUCRISState *env = &cpu->env;
17bc37b7
HPN		 3307 const char **regnames;
3308 const char **pregnames;
7b5eff4d 3309 int i;
7b5eff4d 3310
90c84c56 3311 if (!env) {
7b5eff4d
EV		 3312 return;
3313 }
17bc37b7
HPN		 3314 if (env->pregs[PR_VR] < 32) {
3315 pregnames = pregnames_v10;
3316 regnames = regnames_v10;
3317 } else {
3318 pregnames = pregnames_v32;
3319 regnames = regnames_v32;
3320 }
7b5eff4d 3321
90c84c56
MA		 3322 qemu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
3323 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n",
3324 env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
3325 env->cc_op,
3326 env->cc_src, env->cc_dest, env->cc_result, env->cc_mask);
7b5eff4d
EV		 3327
3328
3329 for (i = 0; i < 16; i++) {
90c84c56 3330 qemu_fprintf(f, "%s=%8.8x ", regnames[i], env->regs[i]);
7b5eff4d 3331 if ((i + 1) % 4 == 0) {
90c84c56 3332 qemu_fprintf(f, "\n");
7b5eff4d
EV		 3333 }
3334 }
90c84c56 3335 qemu_fprintf(f, "\nspecial regs:\n");
7b5eff4d 3336 for (i = 0; i < 16; i++) {
90c84c56 3337 qemu_fprintf(f, "%s=%8.8x ", pregnames[i], env->pregs[i]);
7b5eff4d 3338 if ((i + 1) % 4 == 0) {
90c84c56 3339 qemu_fprintf(f, "\n");
7b5eff4d
EV		 3340 }
3341 }
17bc37b7
HPN		 3342 if (env->pregs[PR_VR] >= 32) {
3343 uint32_t srs = env->pregs[PR_SRS];
90c84c56 3344 qemu_fprintf(f, "\nsupport function regs bank %x:\n", srs);
17bc37b7
HPN		 3345 if (srs < ARRAY_SIZE(env->sregs)) {
3346 for (i = 0; i < 16; i++) {
90c84c56
MA		 3347 qemu_fprintf(f, "s%2.2d=%8.8x ",
3348 i, env->sregs[srs][i]);
17bc37b7 3349 if ((i + 1) % 4 == 0) {
90c84c56 3350 qemu_fprintf(f, "\n");
17bc37b7 3351 }
7b5eff4d
EV		 3352 }
3353 }
3354 }
90c84c56 3355 qemu_fprintf(f, "\n\n");
8170028d
TS		 3356
3357}
3358
d1a94fec
AF		 3359void cris_initialize_tcg(void)
3360{
3361 int i;
05ba7d5f 3362
e1ccc054 3363 cc_x = tcg_global_mem_new(cpu_env,
dd10ce6d 3364 offsetof(CPUCRISState, cc_x), "cc_x");
e1ccc054 3365 cc_src = tcg_global_mem_new(cpu_env,
dd10ce6d 3366 offsetof(CPUCRISState, cc_src), "cc_src");
e1ccc054 3367 cc_dest = tcg_global_mem_new(cpu_env,
dd10ce6d
AF		 3368 offsetof(CPUCRISState, cc_dest),
3369 "cc_dest");
e1ccc054 3370 cc_result = tcg_global_mem_new(cpu_env,
dd10ce6d
AF		 3371 offsetof(CPUCRISState, cc_result),
3372 "cc_result");
e1ccc054 3373 cc_op = tcg_global_mem_new(cpu_env,
dd10ce6d 3374 offsetof(CPUCRISState, cc_op), "cc_op");
e1ccc054 3375 cc_size = tcg_global_mem_new(cpu_env,
dd10ce6d
AF		 3376 offsetof(CPUCRISState, cc_size),
3377 "cc_size");
e1ccc054 3378 cc_mask = tcg_global_mem_new(cpu_env,
dd10ce6d
AF		 3379 offsetof(CPUCRISState, cc_mask),
3380 "cc_mask");
3381
e1ccc054 3382 env_pc = tcg_global_mem_new(cpu_env,
dd10ce6d
AF		 3383 offsetof(CPUCRISState, pc),
3384 "pc");
e1ccc054 3385 env_btarget = tcg_global_mem_new(cpu_env,
dd10ce6d
AF		 3386 offsetof(CPUCRISState, btarget),
3387 "btarget");
e1ccc054 3388 env_btaken = tcg_global_mem_new(cpu_env,
dd10ce6d
AF		 3389 offsetof(CPUCRISState, btaken),
3390 "btaken");
3391 for (i = 0; i < 16; i++) {
e1ccc054 3392 cpu_R[i] = tcg_global_mem_new(cpu_env,
dd10ce6d 3393 offsetof(CPUCRISState, regs[i]),
17bc37b7 3394 regnames_v32[i]);
dd10ce6d
AF		 3395 }
3396 for (i = 0; i < 16; i++) {
e1ccc054 3397 cpu_PR[i] = tcg_global_mem_new(cpu_env,
dd10ce6d 3398 offsetof(CPUCRISState, pregs[i]),
17bc37b7 3399 pregnames_v32[i]);
dd10ce6d 3400 }
8170028d
TS		 3401}
3402
bad729e2
RH		 3403void restore_state_to_opc(CPUCRISState *env, TranslationBlock *tb,
3404 target_ulong *data)
d2856f1a 3405{
bad729e2 3406 env->pc = data[0];
d2856f1a 3407}
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