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Hexagon (target/hexagon) Move pkt_has_store_s1 to DisasContext
[mirror_qemu.git] / target / hexagon / translate.h
CommitLineData
8b453a2b 1/*
10849c26 2 * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
8b453a2b
TS		 3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef HEXAGON_TRANSLATE_H
19#define HEXAGON_TRANSLATE_H
20
21#include "qemu/bitmap.h"
cd617484 22#include "qemu/log.h"
8b453a2b
TS		 23#include "cpu.h"
24#include "exec/translator.h"
25#include "tcg/tcg-op.h"
1e536334 26#include "insn.h"
8b453a2b
TS		 27#include "internal.h"
28
29typedef struct DisasContext {
30 DisasContextBase base;
1e536334
TS		 31 Packet *pkt;
32 Insn *insn;
613653e5 33 uint32_t next_PC;
8b453a2b
TS		 34 uint32_t mem_idx;
35 uint32_t num_packets;
36 uint32_t num_insns;
a82dd548 37 uint32_t num_hvx_insns;
8b453a2b
TS		 38 int reg_log[REG_WRITES_MAX];
39 int reg_log_idx;
40 DECLARE_BITMAP(regs_written, TOTAL_PER_THREAD_REGS);
b9f0326b 41 DECLARE_BITMAP(regs_read, TOTAL_PER_THREAD_REGS);
10849c26 42 DECLARE_BITMAP(predicated_regs, TOTAL_PER_THREAD_REGS);
8b453a2b
TS		 43 int preg_log[PRED_WRITES_MAX];
44 int preg_log_idx;
6c677c60 45 DECLARE_BITMAP(pregs_written, NUM_PREGS);
b9f0326b 46 DECLARE_BITMAP(pregs_read, NUM_PREGS);
8b453a2b 47 uint8_t store_width[STORES_MAX];
92cfa25f 48 bool s1_store_processed;
a82dd548
TS		 49 int future_vregs_idx;
50 int future_vregs_num[VECTOR_TEMPS_MAX];
51 int tmp_vregs_idx;
52 int tmp_vregs_num[VECTOR_TEMPS_MAX];
53 int vreg_log[NUM_VREGS];
a82dd548
TS		 54 int vreg_log_idx;
55 DECLARE_BITMAP(vregs_updated_tmp, NUM_VREGS);
56 DECLARE_BITMAP(vregs_updated, NUM_VREGS);
57 DECLARE_BITMAP(vregs_select, NUM_VREGS);
4d6f8420
TS		 58 DECLARE_BITMAP(predicated_future_vregs, NUM_VREGS);
59 DECLARE_BITMAP(predicated_tmp_vregs, NUM_VREGS);
b9f0326b 60 DECLARE_BITMAP(vregs_read, NUM_VREGS);
a82dd548 61 int qreg_log[NUM_QREGS];
a82dd548 62 int qreg_log_idx;
b9f0326b 63 DECLARE_BITMAP(qregs_read, NUM_QREGS);
a82dd548 64 bool pre_commit;
d54c5615 65 bool need_commit;
1b9a7f2a
TS		 66 TCGCond branch_cond;
67 target_ulong branch_dest;
564b2040 68 bool is_tight_loop;
d54c5615 69 bool short_circuit;
d05d5eeb 70 bool has_hvx_helper;
4ff56764 71 TCGv new_value[TOTAL_PER_THREAD_REGS];
e22edc7c 72 TCGv new_pred_value[NUM_PREGS];
842b206f 73 TCGv pred_written;
8b453a2b
TS		 74} DisasContext;
75
10849c26 76static inline void ctx_log_pred_write(DisasContext *ctx, int pnum)
8b453a2b 77{
10849c26
TS		 78 if (!test_bit(pnum, ctx->pregs_written)) {
79 ctx->preg_log[ctx->preg_log_idx] = pnum;
80 ctx->preg_log_idx++;
81 set_bit(pnum, ctx->pregs_written);
8b453a2b 82 }
8b453a2b
TS		 83}
84
b9f0326b
TS		 85static inline void ctx_log_pred_read(DisasContext *ctx, int pnum)
86{
87 set_bit(pnum, ctx->pregs_read);
88}
89
10849c26
TS		 90static inline void ctx_log_reg_write(DisasContext *ctx, int rnum,
91 bool is_predicated)
8b453a2b 92{
10849c26
TS		 93 if (rnum == HEX_REG_P3_0_ALIASED) {
94 for (int i = 0; i < NUM_PREGS; i++) {
95 ctx_log_pred_write(ctx, i);
96 }
97 } else {
98 if (!test_bit(rnum, ctx->regs_written)) {
99 ctx->reg_log[ctx->reg_log_idx] = rnum;
100 ctx->reg_log_idx++;
101 set_bit(rnum, ctx->regs_written);
102 }
103 if (is_predicated) {
104 set_bit(rnum, ctx->predicated_regs);
105 }
106 }
8b453a2b
TS		 107}
108
10849c26
TS		 109static inline void ctx_log_reg_write_pair(DisasContext *ctx, int rnum,
110 bool is_predicated)
8b453a2b 111{
10849c26
TS		 112 ctx_log_reg_write(ctx, rnum, is_predicated);
113 ctx_log_reg_write(ctx, rnum + 1, is_predicated);
8b453a2b
TS		 114}
115
b9f0326b
TS		 116static inline void ctx_log_reg_read(DisasContext *ctx, int rnum)
117{
118 set_bit(rnum, ctx->regs_read);
119}
120
121static inline void ctx_log_reg_read_pair(DisasContext *ctx, int rnum)
122{
123 ctx_log_reg_read(ctx, rnum);
124 ctx_log_reg_read(ctx, rnum + 1);
125}
126
a82dd548
TS		 127intptr_t ctx_future_vreg_off(DisasContext *ctx, int regnum,
128 int num, bool alloc_ok);
129intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum,
130 int num, bool alloc_ok);
131
132static inline void ctx_log_vreg_write(DisasContext *ctx,
133 int rnum, VRegWriteType type,
134 bool is_predicated)
135{
136 if (type != EXT_TMP) {
c2b33d0b
TS		 137 if (!test_bit(rnum, ctx->vregs_updated)) {
138 ctx->vreg_log[ctx->vreg_log_idx] = rnum;
139 ctx->vreg_log_idx++;
140 set_bit(rnum, ctx->vregs_updated);
141 }
a82dd548
TS		 142
143 set_bit(rnum, ctx->vregs_updated);
4d6f8420
TS		 144 if (is_predicated) {
145 set_bit(rnum, ctx->predicated_future_vregs);
146 }
a82dd548
TS		 147 }
148 if (type == EXT_NEW) {
149 set_bit(rnum, ctx->vregs_select);
150 }
151 if (type == EXT_TMP) {
152 set_bit(rnum, ctx->vregs_updated_tmp);
4d6f8420
TS		 153 if (is_predicated) {
154 set_bit(rnum, ctx->predicated_tmp_vregs);
155 }
a82dd548
TS		 156 }
157}
158
159static inline void ctx_log_vreg_write_pair(DisasContext *ctx,
160 int rnum, VRegWriteType type,
161 bool is_predicated)
162{
163 ctx_log_vreg_write(ctx, rnum ^ 0, type, is_predicated);
164 ctx_log_vreg_write(ctx, rnum ^ 1, type, is_predicated);
165}
166
b9f0326b
TS		 167static inline void ctx_log_vreg_read(DisasContext *ctx, int rnum)
168{
169 set_bit(rnum, ctx->vregs_read);
170}
171
172static inline void ctx_log_vreg_read_pair(DisasContext *ctx, int rnum)
173{
174 ctx_log_vreg_read(ctx, rnum ^ 0);
175 ctx_log_vreg_read(ctx, rnum ^ 1);
176}
177
a82dd548 178static inline void ctx_log_qreg_write(DisasContext *ctx,
c2b33d0b 179 int rnum)
a82dd548
TS		 180{
181 ctx->qreg_log[ctx->qreg_log_idx] = rnum;
a82dd548
TS		 182 ctx->qreg_log_idx++;
183}
184
b9f0326b
TS		 185static inline void ctx_log_qreg_read(DisasContext *ctx, int qnum)
186{
187 set_bit(qnum, ctx->qregs_read);
188}
189
8b453a2b
TS		 190extern TCGv hex_gpr[TOTAL_PER_THREAD_REGS];
191extern TCGv hex_pred[NUM_PREGS];
8b453a2b
TS		 192extern TCGv hex_this_PC;
193extern TCGv hex_slot_cancelled;
194extern TCGv hex_branch_taken;
6aa4f1d1 195extern TCGv hex_new_value_usr;
8b453a2b 196extern TCGv hex_reg_written[TOTAL_PER_THREAD_REGS];
8b453a2b
TS		 197extern TCGv hex_store_addr[STORES_MAX];
198extern TCGv hex_store_width[STORES_MAX];
199extern TCGv hex_store_val32[STORES_MAX];
200extern TCGv_i64 hex_store_val64[STORES_MAX];
201extern TCGv hex_dczero_addr;
202extern TCGv hex_llsc_addr;
203extern TCGv hex_llsc_val;
204extern TCGv_i64 hex_llsc_val_i64;
a82dd548
TS		 205extern TCGv hex_vstore_addr[VSTORES_MAX];
206extern TCGv hex_vstore_size[VSTORES_MAX];
207extern TCGv hex_vstore_pending[VSTORES_MAX];
8b453a2b 208
1e536334
TS		 209bool is_gather_store_insn(DisasContext *ctx);
210void process_store(DisasContext *ctx, int slot_num);
7b84fd04
TS		 211
212FIELD(PROBE_PKT_SCALAR_STORE_S0, MMU_IDX, 0, 2)
213FIELD(PROBE_PKT_SCALAR_STORE_S0, IS_PREDICATED, 2, 1)
214
215FIELD(PROBE_PKT_SCALAR_HVX_STORES, HAS_ST0, 0, 1)
216FIELD(PROBE_PKT_SCALAR_HVX_STORES, HAS_ST1, 1, 1)
217FIELD(PROBE_PKT_SCALAR_HVX_STORES, HAS_HVX_STORES, 2, 1)
218FIELD(PROBE_PKT_SCALAR_HVX_STORES, S0_IS_PRED, 3, 1)
219FIELD(PROBE_PKT_SCALAR_HVX_STORES, S1_IS_PRED, 4, 1)
2bda44e8 220FIELD(PROBE_PKT_SCALAR_HVX_STORES, MMU_IDX, 5, 2)
7b84fd04 221
8b453a2b 222#endif
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