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61766fe9 RH |
1 | /* |
2 | * HPPA emulation cpu translation for qemu. | |
3 | * | |
4 | * Copyright (c) 2016 Richard Henderson <rth@twiddle.net> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
d6ea4236 | 9 | * version 2.1 of the License, or (at your option) any later version. |
61766fe9 RH |
10 | * |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
21 | #include "cpu.h" | |
22 | #include "disas/disas.h" | |
23 | #include "qemu/host-utils.h" | |
24 | #include "exec/exec-all.h" | |
dcb32f1d | 25 | #include "tcg/tcg-op.h" |
61766fe9 | 26 | #include "exec/cpu_ldst.h" |
61766fe9 RH |
27 | #include "exec/helper-proto.h" |
28 | #include "exec/helper-gen.h" | |
869051ea | 29 | #include "exec/translator.h" |
61766fe9 RH |
30 | #include "exec/log.h" |
31 | ||
eaa3783b RH |
32 | /* Since we have a distinction between register size and address size, |
33 | we need to redefine all of these. */ | |
34 | ||
35 | #undef TCGv | |
36 | #undef tcg_temp_new | |
eaa3783b | 37 | #undef tcg_global_mem_new |
eaa3783b RH |
38 | |
39 | #if TARGET_LONG_BITS == 64 | |
40 | #define TCGv_tl TCGv_i64 | |
41 | #define tcg_temp_new_tl tcg_temp_new_i64 | |
eaa3783b RH |
42 | #if TARGET_REGISTER_BITS == 64 |
43 | #define tcg_gen_extu_reg_tl tcg_gen_mov_i64 | |
44 | #else | |
45 | #define tcg_gen_extu_reg_tl tcg_gen_extu_i32_i64 | |
46 | #endif | |
47 | #else | |
48 | #define TCGv_tl TCGv_i32 | |
49 | #define tcg_temp_new_tl tcg_temp_new_i32 | |
eaa3783b RH |
50 | #define tcg_gen_extu_reg_tl tcg_gen_mov_i32 |
51 | #endif | |
52 | ||
53 | #if TARGET_REGISTER_BITS == 64 | |
54 | #define TCGv_reg TCGv_i64 | |
55 | ||
56 | #define tcg_temp_new tcg_temp_new_i64 | |
eaa3783b | 57 | #define tcg_global_mem_new tcg_global_mem_new_i64 |
eaa3783b RH |
58 | |
59 | #define tcg_gen_movi_reg tcg_gen_movi_i64 | |
60 | #define tcg_gen_mov_reg tcg_gen_mov_i64 | |
61 | #define tcg_gen_ld8u_reg tcg_gen_ld8u_i64 | |
62 | #define tcg_gen_ld8s_reg tcg_gen_ld8s_i64 | |
63 | #define tcg_gen_ld16u_reg tcg_gen_ld16u_i64 | |
64 | #define tcg_gen_ld16s_reg tcg_gen_ld16s_i64 | |
65 | #define tcg_gen_ld32u_reg tcg_gen_ld32u_i64 | |
66 | #define tcg_gen_ld32s_reg tcg_gen_ld32s_i64 | |
67 | #define tcg_gen_ld_reg tcg_gen_ld_i64 | |
68 | #define tcg_gen_st8_reg tcg_gen_st8_i64 | |
69 | #define tcg_gen_st16_reg tcg_gen_st16_i64 | |
70 | #define tcg_gen_st32_reg tcg_gen_st32_i64 | |
71 | #define tcg_gen_st_reg tcg_gen_st_i64 | |
72 | #define tcg_gen_add_reg tcg_gen_add_i64 | |
73 | #define tcg_gen_addi_reg tcg_gen_addi_i64 | |
74 | #define tcg_gen_sub_reg tcg_gen_sub_i64 | |
75 | #define tcg_gen_neg_reg tcg_gen_neg_i64 | |
76 | #define tcg_gen_subfi_reg tcg_gen_subfi_i64 | |
77 | #define tcg_gen_subi_reg tcg_gen_subi_i64 | |
78 | #define tcg_gen_and_reg tcg_gen_and_i64 | |
79 | #define tcg_gen_andi_reg tcg_gen_andi_i64 | |
80 | #define tcg_gen_or_reg tcg_gen_or_i64 | |
81 | #define tcg_gen_ori_reg tcg_gen_ori_i64 | |
82 | #define tcg_gen_xor_reg tcg_gen_xor_i64 | |
83 | #define tcg_gen_xori_reg tcg_gen_xori_i64 | |
84 | #define tcg_gen_not_reg tcg_gen_not_i64 | |
85 | #define tcg_gen_shl_reg tcg_gen_shl_i64 | |
86 | #define tcg_gen_shli_reg tcg_gen_shli_i64 | |
87 | #define tcg_gen_shr_reg tcg_gen_shr_i64 | |
88 | #define tcg_gen_shri_reg tcg_gen_shri_i64 | |
89 | #define tcg_gen_sar_reg tcg_gen_sar_i64 | |
90 | #define tcg_gen_sari_reg tcg_gen_sari_i64 | |
91 | #define tcg_gen_brcond_reg tcg_gen_brcond_i64 | |
92 | #define tcg_gen_brcondi_reg tcg_gen_brcondi_i64 | |
93 | #define tcg_gen_setcond_reg tcg_gen_setcond_i64 | |
94 | #define tcg_gen_setcondi_reg tcg_gen_setcondi_i64 | |
95 | #define tcg_gen_mul_reg tcg_gen_mul_i64 | |
96 | #define tcg_gen_muli_reg tcg_gen_muli_i64 | |
97 | #define tcg_gen_div_reg tcg_gen_div_i64 | |
98 | #define tcg_gen_rem_reg tcg_gen_rem_i64 | |
99 | #define tcg_gen_divu_reg tcg_gen_divu_i64 | |
100 | #define tcg_gen_remu_reg tcg_gen_remu_i64 | |
101 | #define tcg_gen_discard_reg tcg_gen_discard_i64 | |
102 | #define tcg_gen_trunc_reg_i32 tcg_gen_extrl_i64_i32 | |
103 | #define tcg_gen_trunc_i64_reg tcg_gen_mov_i64 | |
104 | #define tcg_gen_extu_i32_reg tcg_gen_extu_i32_i64 | |
105 | #define tcg_gen_ext_i32_reg tcg_gen_ext_i32_i64 | |
106 | #define tcg_gen_extu_reg_i64 tcg_gen_mov_i64 | |
107 | #define tcg_gen_ext_reg_i64 tcg_gen_mov_i64 | |
108 | #define tcg_gen_ext8u_reg tcg_gen_ext8u_i64 | |
109 | #define tcg_gen_ext8s_reg tcg_gen_ext8s_i64 | |
110 | #define tcg_gen_ext16u_reg tcg_gen_ext16u_i64 | |
111 | #define tcg_gen_ext16s_reg tcg_gen_ext16s_i64 | |
112 | #define tcg_gen_ext32u_reg tcg_gen_ext32u_i64 | |
113 | #define tcg_gen_ext32s_reg tcg_gen_ext32s_i64 | |
114 | #define tcg_gen_bswap16_reg tcg_gen_bswap16_i64 | |
115 | #define tcg_gen_bswap32_reg tcg_gen_bswap32_i64 | |
116 | #define tcg_gen_bswap64_reg tcg_gen_bswap64_i64 | |
117 | #define tcg_gen_concat_reg_i64 tcg_gen_concat32_i64 | |
118 | #define tcg_gen_andc_reg tcg_gen_andc_i64 | |
119 | #define tcg_gen_eqv_reg tcg_gen_eqv_i64 | |
120 | #define tcg_gen_nand_reg tcg_gen_nand_i64 | |
121 | #define tcg_gen_nor_reg tcg_gen_nor_i64 | |
122 | #define tcg_gen_orc_reg tcg_gen_orc_i64 | |
123 | #define tcg_gen_clz_reg tcg_gen_clz_i64 | |
124 | #define tcg_gen_ctz_reg tcg_gen_ctz_i64 | |
125 | #define tcg_gen_clzi_reg tcg_gen_clzi_i64 | |
126 | #define tcg_gen_ctzi_reg tcg_gen_ctzi_i64 | |
127 | #define tcg_gen_clrsb_reg tcg_gen_clrsb_i64 | |
128 | #define tcg_gen_ctpop_reg tcg_gen_ctpop_i64 | |
129 | #define tcg_gen_rotl_reg tcg_gen_rotl_i64 | |
130 | #define tcg_gen_rotli_reg tcg_gen_rotli_i64 | |
131 | #define tcg_gen_rotr_reg tcg_gen_rotr_i64 | |
132 | #define tcg_gen_rotri_reg tcg_gen_rotri_i64 | |
133 | #define tcg_gen_deposit_reg tcg_gen_deposit_i64 | |
134 | #define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i64 | |
135 | #define tcg_gen_extract_reg tcg_gen_extract_i64 | |
136 | #define tcg_gen_sextract_reg tcg_gen_sextract_i64 | |
05bfd4db | 137 | #define tcg_gen_extract2_reg tcg_gen_extract2_i64 |
29dd6f64 | 138 | #define tcg_constant_reg tcg_constant_i64 |
eaa3783b RH |
139 | #define tcg_gen_movcond_reg tcg_gen_movcond_i64 |
140 | #define tcg_gen_add2_reg tcg_gen_add2_i64 | |
141 | #define tcg_gen_sub2_reg tcg_gen_sub2_i64 | |
142 | #define tcg_gen_qemu_ld_reg tcg_gen_qemu_ld_i64 | |
143 | #define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i64 | |
144 | #define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i64 | |
5bfa8034 | 145 | #define tcg_gen_trunc_reg_ptr tcg_gen_trunc_i64_ptr |
eaa3783b RH |
146 | #else |
147 | #define TCGv_reg TCGv_i32 | |
148 | #define tcg_temp_new tcg_temp_new_i32 | |
eaa3783b | 149 | #define tcg_global_mem_new tcg_global_mem_new_i32 |
eaa3783b RH |
150 | |
151 | #define tcg_gen_movi_reg tcg_gen_movi_i32 | |
152 | #define tcg_gen_mov_reg tcg_gen_mov_i32 | |
153 | #define tcg_gen_ld8u_reg tcg_gen_ld8u_i32 | |
154 | #define tcg_gen_ld8s_reg tcg_gen_ld8s_i32 | |
155 | #define tcg_gen_ld16u_reg tcg_gen_ld16u_i32 | |
156 | #define tcg_gen_ld16s_reg tcg_gen_ld16s_i32 | |
157 | #define tcg_gen_ld32u_reg tcg_gen_ld_i32 | |
158 | #define tcg_gen_ld32s_reg tcg_gen_ld_i32 | |
159 | #define tcg_gen_ld_reg tcg_gen_ld_i32 | |
160 | #define tcg_gen_st8_reg tcg_gen_st8_i32 | |
161 | #define tcg_gen_st16_reg tcg_gen_st16_i32 | |
162 | #define tcg_gen_st32_reg tcg_gen_st32_i32 | |
163 | #define tcg_gen_st_reg tcg_gen_st_i32 | |
164 | #define tcg_gen_add_reg tcg_gen_add_i32 | |
165 | #define tcg_gen_addi_reg tcg_gen_addi_i32 | |
166 | #define tcg_gen_sub_reg tcg_gen_sub_i32 | |
167 | #define tcg_gen_neg_reg tcg_gen_neg_i32 | |
168 | #define tcg_gen_subfi_reg tcg_gen_subfi_i32 | |
169 | #define tcg_gen_subi_reg tcg_gen_subi_i32 | |
170 | #define tcg_gen_and_reg tcg_gen_and_i32 | |
171 | #define tcg_gen_andi_reg tcg_gen_andi_i32 | |
172 | #define tcg_gen_or_reg tcg_gen_or_i32 | |
173 | #define tcg_gen_ori_reg tcg_gen_ori_i32 | |
174 | #define tcg_gen_xor_reg tcg_gen_xor_i32 | |
175 | #define tcg_gen_xori_reg tcg_gen_xori_i32 | |
176 | #define tcg_gen_not_reg tcg_gen_not_i32 | |
177 | #define tcg_gen_shl_reg tcg_gen_shl_i32 | |
178 | #define tcg_gen_shli_reg tcg_gen_shli_i32 | |
179 | #define tcg_gen_shr_reg tcg_gen_shr_i32 | |
180 | #define tcg_gen_shri_reg tcg_gen_shri_i32 | |
181 | #define tcg_gen_sar_reg tcg_gen_sar_i32 | |
182 | #define tcg_gen_sari_reg tcg_gen_sari_i32 | |
183 | #define tcg_gen_brcond_reg tcg_gen_brcond_i32 | |
184 | #define tcg_gen_brcondi_reg tcg_gen_brcondi_i32 | |
185 | #define tcg_gen_setcond_reg tcg_gen_setcond_i32 | |
186 | #define tcg_gen_setcondi_reg tcg_gen_setcondi_i32 | |
187 | #define tcg_gen_mul_reg tcg_gen_mul_i32 | |
188 | #define tcg_gen_muli_reg tcg_gen_muli_i32 | |
189 | #define tcg_gen_div_reg tcg_gen_div_i32 | |
190 | #define tcg_gen_rem_reg tcg_gen_rem_i32 | |
191 | #define tcg_gen_divu_reg tcg_gen_divu_i32 | |
192 | #define tcg_gen_remu_reg tcg_gen_remu_i32 | |
193 | #define tcg_gen_discard_reg tcg_gen_discard_i32 | |
194 | #define tcg_gen_trunc_reg_i32 tcg_gen_mov_i32 | |
195 | #define tcg_gen_trunc_i64_reg tcg_gen_extrl_i64_i32 | |
196 | #define tcg_gen_extu_i32_reg tcg_gen_mov_i32 | |
197 | #define tcg_gen_ext_i32_reg tcg_gen_mov_i32 | |
198 | #define tcg_gen_extu_reg_i64 tcg_gen_extu_i32_i64 | |
199 | #define tcg_gen_ext_reg_i64 tcg_gen_ext_i32_i64 | |
200 | #define tcg_gen_ext8u_reg tcg_gen_ext8u_i32 | |
201 | #define tcg_gen_ext8s_reg tcg_gen_ext8s_i32 | |
202 | #define tcg_gen_ext16u_reg tcg_gen_ext16u_i32 | |
203 | #define tcg_gen_ext16s_reg tcg_gen_ext16s_i32 | |
204 | #define tcg_gen_ext32u_reg tcg_gen_mov_i32 | |
205 | #define tcg_gen_ext32s_reg tcg_gen_mov_i32 | |
206 | #define tcg_gen_bswap16_reg tcg_gen_bswap16_i32 | |
207 | #define tcg_gen_bswap32_reg tcg_gen_bswap32_i32 | |
208 | #define tcg_gen_concat_reg_i64 tcg_gen_concat_i32_i64 | |
209 | #define tcg_gen_andc_reg tcg_gen_andc_i32 | |
210 | #define tcg_gen_eqv_reg tcg_gen_eqv_i32 | |
211 | #define tcg_gen_nand_reg tcg_gen_nand_i32 | |
212 | #define tcg_gen_nor_reg tcg_gen_nor_i32 | |
213 | #define tcg_gen_orc_reg tcg_gen_orc_i32 | |
214 | #define tcg_gen_clz_reg tcg_gen_clz_i32 | |
215 | #define tcg_gen_ctz_reg tcg_gen_ctz_i32 | |
216 | #define tcg_gen_clzi_reg tcg_gen_clzi_i32 | |
217 | #define tcg_gen_ctzi_reg tcg_gen_ctzi_i32 | |
218 | #define tcg_gen_clrsb_reg tcg_gen_clrsb_i32 | |
219 | #define tcg_gen_ctpop_reg tcg_gen_ctpop_i32 | |
220 | #define tcg_gen_rotl_reg tcg_gen_rotl_i32 | |
221 | #define tcg_gen_rotli_reg tcg_gen_rotli_i32 | |
222 | #define tcg_gen_rotr_reg tcg_gen_rotr_i32 | |
223 | #define tcg_gen_rotri_reg tcg_gen_rotri_i32 | |
224 | #define tcg_gen_deposit_reg tcg_gen_deposit_i32 | |
225 | #define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i32 | |
226 | #define tcg_gen_extract_reg tcg_gen_extract_i32 | |
227 | #define tcg_gen_sextract_reg tcg_gen_sextract_i32 | |
05bfd4db | 228 | #define tcg_gen_extract2_reg tcg_gen_extract2_i32 |
29dd6f64 | 229 | #define tcg_constant_reg tcg_constant_i32 |
eaa3783b RH |
230 | #define tcg_gen_movcond_reg tcg_gen_movcond_i32 |
231 | #define tcg_gen_add2_reg tcg_gen_add2_i32 | |
232 | #define tcg_gen_sub2_reg tcg_gen_sub2_i32 | |
233 | #define tcg_gen_qemu_ld_reg tcg_gen_qemu_ld_i32 | |
234 | #define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i32 | |
235 | #define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i32 | |
5bfa8034 | 236 | #define tcg_gen_trunc_reg_ptr tcg_gen_ext_i32_ptr |
eaa3783b RH |
237 | #endif /* TARGET_REGISTER_BITS */ |
238 | ||
61766fe9 RH |
239 | typedef struct DisasCond { |
240 | TCGCond c; | |
eaa3783b | 241 | TCGv_reg a0, a1; |
61766fe9 RH |
242 | } DisasCond; |
243 | ||
244 | typedef struct DisasContext { | |
d01a3625 | 245 | DisasContextBase base; |
61766fe9 RH |
246 | CPUState *cs; |
247 | ||
eaa3783b RH |
248 | target_ureg iaoq_f; |
249 | target_ureg iaoq_b; | |
250 | target_ureg iaoq_n; | |
251 | TCGv_reg iaoq_n_var; | |
61766fe9 | 252 | |
86f8d05f | 253 | int ntempr, ntempl; |
5eecd37a | 254 | TCGv_reg tempr[8]; |
86f8d05f | 255 | TCGv_tl templ[4]; |
61766fe9 RH |
256 | |
257 | DisasCond null_cond; | |
258 | TCGLabel *null_lab; | |
259 | ||
1a19da0d | 260 | uint32_t insn; |
494737b7 | 261 | uint32_t tb_flags; |
3d68ee7b RH |
262 | int mmu_idx; |
263 | int privilege; | |
61766fe9 | 264 | bool psw_n_nonzero; |
217d1a5e RH |
265 | |
266 | #ifdef CONFIG_USER_ONLY | |
267 | MemOp unalign; | |
268 | #endif | |
61766fe9 RH |
269 | } DisasContext; |
270 | ||
217d1a5e RH |
271 | #ifdef CONFIG_USER_ONLY |
272 | #define UNALIGN(C) (C)->unalign | |
273 | #else | |
2d4afb03 | 274 | #define UNALIGN(C) MO_ALIGN |
217d1a5e RH |
275 | #endif |
276 | ||
e36f27ef | 277 | /* Note that ssm/rsm instructions number PSW_W and PSW_E differently. */ |
451e4ffd | 278 | static int expand_sm_imm(DisasContext *ctx, int val) |
e36f27ef RH |
279 | { |
280 | if (val & PSW_SM_E) { | |
281 | val = (val & ~PSW_SM_E) | PSW_E; | |
282 | } | |
283 | if (val & PSW_SM_W) { | |
284 | val = (val & ~PSW_SM_W) | PSW_W; | |
285 | } | |
286 | return val; | |
287 | } | |
288 | ||
deee69a1 | 289 | /* Inverted space register indicates 0 means sr0 not inferred from base. */ |
451e4ffd | 290 | static int expand_sr3x(DisasContext *ctx, int val) |
deee69a1 RH |
291 | { |
292 | return ~val; | |
293 | } | |
294 | ||
1cd012a5 RH |
295 | /* Convert the M:A bits within a memory insn to the tri-state value |
296 | we use for the final M. */ | |
451e4ffd | 297 | static int ma_to_m(DisasContext *ctx, int val) |
1cd012a5 RH |
298 | { |
299 | return val & 2 ? (val & 1 ? -1 : 1) : 0; | |
300 | } | |
301 | ||
740038d7 | 302 | /* Convert the sign of the displacement to a pre or post-modify. */ |
451e4ffd | 303 | static int pos_to_m(DisasContext *ctx, int val) |
740038d7 RH |
304 | { |
305 | return val ? 1 : -1; | |
306 | } | |
307 | ||
451e4ffd | 308 | static int neg_to_m(DisasContext *ctx, int val) |
740038d7 RH |
309 | { |
310 | return val ? -1 : 1; | |
311 | } | |
312 | ||
313 | /* Used for branch targets and fp memory ops. */ | |
451e4ffd | 314 | static int expand_shl2(DisasContext *ctx, int val) |
01afb7be RH |
315 | { |
316 | return val << 2; | |
317 | } | |
318 | ||
740038d7 | 319 | /* Used for fp memory ops. */ |
451e4ffd | 320 | static int expand_shl3(DisasContext *ctx, int val) |
740038d7 RH |
321 | { |
322 | return val << 3; | |
323 | } | |
324 | ||
0588e061 | 325 | /* Used for assemble_21. */ |
451e4ffd | 326 | static int expand_shl11(DisasContext *ctx, int val) |
0588e061 RH |
327 | { |
328 | return val << 11; | |
329 | } | |
330 | ||
01afb7be | 331 | |
40f9f908 | 332 | /* Include the auto-generated decoder. */ |
abff1abf | 333 | #include "decode-insns.c.inc" |
40f9f908 | 334 | |
869051ea RH |
335 | /* We are not using a goto_tb (for whatever reason), but have updated |
336 | the iaq (for whatever reason), so don't do it again on exit. */ | |
337 | #define DISAS_IAQ_N_UPDATED DISAS_TARGET_0 | |
61766fe9 | 338 | |
869051ea RH |
339 | /* We are exiting the TB, but have neither emitted a goto_tb, nor |
340 | updated the iaq for the next instruction to be executed. */ | |
341 | #define DISAS_IAQ_N_STALE DISAS_TARGET_1 | |
61766fe9 | 342 | |
e1b5a5ed RH |
343 | /* Similarly, but we want to return to the main loop immediately |
344 | to recognize unmasked interrupts. */ | |
345 | #define DISAS_IAQ_N_STALE_EXIT DISAS_TARGET_2 | |
c5d0aec2 | 346 | #define DISAS_EXIT DISAS_TARGET_3 |
e1b5a5ed | 347 | |
61766fe9 | 348 | /* global register indexes */ |
eaa3783b | 349 | static TCGv_reg cpu_gr[32]; |
33423472 | 350 | static TCGv_i64 cpu_sr[4]; |
494737b7 | 351 | static TCGv_i64 cpu_srH; |
eaa3783b RH |
352 | static TCGv_reg cpu_iaoq_f; |
353 | static TCGv_reg cpu_iaoq_b; | |
c301f34e RH |
354 | static TCGv_i64 cpu_iasq_f; |
355 | static TCGv_i64 cpu_iasq_b; | |
eaa3783b RH |
356 | static TCGv_reg cpu_sar; |
357 | static TCGv_reg cpu_psw_n; | |
358 | static TCGv_reg cpu_psw_v; | |
359 | static TCGv_reg cpu_psw_cb; | |
360 | static TCGv_reg cpu_psw_cb_msb; | |
61766fe9 RH |
361 | |
362 | #include "exec/gen-icount.h" | |
363 | ||
364 | void hppa_translate_init(void) | |
365 | { | |
366 | #define DEF_VAR(V) { &cpu_##V, #V, offsetof(CPUHPPAState, V) } | |
367 | ||
eaa3783b | 368 | typedef struct { TCGv_reg *var; const char *name; int ofs; } GlobalVar; |
61766fe9 | 369 | static const GlobalVar vars[] = { |
35136a77 | 370 | { &cpu_sar, "sar", offsetof(CPUHPPAState, cr[CR_SAR]) }, |
61766fe9 RH |
371 | DEF_VAR(psw_n), |
372 | DEF_VAR(psw_v), | |
373 | DEF_VAR(psw_cb), | |
374 | DEF_VAR(psw_cb_msb), | |
375 | DEF_VAR(iaoq_f), | |
376 | DEF_VAR(iaoq_b), | |
377 | }; | |
378 | ||
379 | #undef DEF_VAR | |
380 | ||
381 | /* Use the symbolic register names that match the disassembler. */ | |
382 | static const char gr_names[32][4] = { | |
383 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
384 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
385 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
386 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | |
387 | }; | |
33423472 | 388 | /* SR[4-7] are not global registers so that we can index them. */ |
494737b7 RH |
389 | static const char sr_names[5][4] = { |
390 | "sr0", "sr1", "sr2", "sr3", "srH" | |
33423472 | 391 | }; |
61766fe9 | 392 | |
61766fe9 RH |
393 | int i; |
394 | ||
f764718d | 395 | cpu_gr[0] = NULL; |
61766fe9 RH |
396 | for (i = 1; i < 32; i++) { |
397 | cpu_gr[i] = tcg_global_mem_new(cpu_env, | |
398 | offsetof(CPUHPPAState, gr[i]), | |
399 | gr_names[i]); | |
400 | } | |
33423472 RH |
401 | for (i = 0; i < 4; i++) { |
402 | cpu_sr[i] = tcg_global_mem_new_i64(cpu_env, | |
403 | offsetof(CPUHPPAState, sr[i]), | |
404 | sr_names[i]); | |
405 | } | |
494737b7 RH |
406 | cpu_srH = tcg_global_mem_new_i64(cpu_env, |
407 | offsetof(CPUHPPAState, sr[4]), | |
408 | sr_names[4]); | |
61766fe9 RH |
409 | |
410 | for (i = 0; i < ARRAY_SIZE(vars); ++i) { | |
411 | const GlobalVar *v = &vars[i]; | |
412 | *v->var = tcg_global_mem_new(cpu_env, v->ofs, v->name); | |
413 | } | |
c301f34e RH |
414 | |
415 | cpu_iasq_f = tcg_global_mem_new_i64(cpu_env, | |
416 | offsetof(CPUHPPAState, iasq_f), | |
417 | "iasq_f"); | |
418 | cpu_iasq_b = tcg_global_mem_new_i64(cpu_env, | |
419 | offsetof(CPUHPPAState, iasq_b), | |
420 | "iasq_b"); | |
61766fe9 RH |
421 | } |
422 | ||
129e9cc3 RH |
423 | static DisasCond cond_make_f(void) |
424 | { | |
f764718d RH |
425 | return (DisasCond){ |
426 | .c = TCG_COND_NEVER, | |
427 | .a0 = NULL, | |
428 | .a1 = NULL, | |
429 | }; | |
129e9cc3 RH |
430 | } |
431 | ||
df0232fe RH |
432 | static DisasCond cond_make_t(void) |
433 | { | |
434 | return (DisasCond){ | |
435 | .c = TCG_COND_ALWAYS, | |
436 | .a0 = NULL, | |
437 | .a1 = NULL, | |
438 | }; | |
439 | } | |
440 | ||
129e9cc3 RH |
441 | static DisasCond cond_make_n(void) |
442 | { | |
f764718d RH |
443 | return (DisasCond){ |
444 | .c = TCG_COND_NE, | |
445 | .a0 = cpu_psw_n, | |
6e94937a | 446 | .a1 = tcg_constant_reg(0) |
f764718d | 447 | }; |
129e9cc3 RH |
448 | } |
449 | ||
b47a4a02 | 450 | static DisasCond cond_make_0_tmp(TCGCond c, TCGv_reg a0) |
129e9cc3 | 451 | { |
129e9cc3 | 452 | assert (c != TCG_COND_NEVER && c != TCG_COND_ALWAYS); |
b47a4a02 | 453 | return (DisasCond){ |
6e94937a | 454 | .c = c, .a0 = a0, .a1 = tcg_constant_reg(0) |
b47a4a02 SS |
455 | }; |
456 | } | |
129e9cc3 | 457 | |
b47a4a02 SS |
458 | static DisasCond cond_make_0(TCGCond c, TCGv_reg a0) |
459 | { | |
460 | TCGv_reg tmp = tcg_temp_new(); | |
461 | tcg_gen_mov_reg(tmp, a0); | |
462 | return cond_make_0_tmp(c, tmp); | |
129e9cc3 RH |
463 | } |
464 | ||
eaa3783b | 465 | static DisasCond cond_make(TCGCond c, TCGv_reg a0, TCGv_reg a1) |
129e9cc3 RH |
466 | { |
467 | DisasCond r = { .c = c }; | |
468 | ||
469 | assert (c != TCG_COND_NEVER && c != TCG_COND_ALWAYS); | |
470 | r.a0 = tcg_temp_new(); | |
eaa3783b | 471 | tcg_gen_mov_reg(r.a0, a0); |
129e9cc3 | 472 | r.a1 = tcg_temp_new(); |
eaa3783b | 473 | tcg_gen_mov_reg(r.a1, a1); |
129e9cc3 RH |
474 | |
475 | return r; | |
476 | } | |
477 | ||
129e9cc3 RH |
478 | static void cond_free(DisasCond *cond) |
479 | { | |
480 | switch (cond->c) { | |
481 | default: | |
f764718d RH |
482 | cond->a0 = NULL; |
483 | cond->a1 = NULL; | |
129e9cc3 RH |
484 | /* fallthru */ |
485 | case TCG_COND_ALWAYS: | |
486 | cond->c = TCG_COND_NEVER; | |
487 | break; | |
488 | case TCG_COND_NEVER: | |
489 | break; | |
490 | } | |
491 | } | |
492 | ||
eaa3783b | 493 | static TCGv_reg get_temp(DisasContext *ctx) |
61766fe9 | 494 | { |
86f8d05f RH |
495 | unsigned i = ctx->ntempr++; |
496 | g_assert(i < ARRAY_SIZE(ctx->tempr)); | |
497 | return ctx->tempr[i] = tcg_temp_new(); | |
61766fe9 RH |
498 | } |
499 | ||
86f8d05f RH |
500 | #ifndef CONFIG_USER_ONLY |
501 | static TCGv_tl get_temp_tl(DisasContext *ctx) | |
502 | { | |
503 | unsigned i = ctx->ntempl++; | |
504 | g_assert(i < ARRAY_SIZE(ctx->templ)); | |
505 | return ctx->templ[i] = tcg_temp_new_tl(); | |
506 | } | |
507 | #endif | |
508 | ||
eaa3783b | 509 | static TCGv_reg load_const(DisasContext *ctx, target_sreg v) |
61766fe9 | 510 | { |
eaa3783b RH |
511 | TCGv_reg t = get_temp(ctx); |
512 | tcg_gen_movi_reg(t, v); | |
61766fe9 RH |
513 | return t; |
514 | } | |
515 | ||
eaa3783b | 516 | static TCGv_reg load_gpr(DisasContext *ctx, unsigned reg) |
61766fe9 RH |
517 | { |
518 | if (reg == 0) { | |
eaa3783b RH |
519 | TCGv_reg t = get_temp(ctx); |
520 | tcg_gen_movi_reg(t, 0); | |
61766fe9 RH |
521 | return t; |
522 | } else { | |
523 | return cpu_gr[reg]; | |
524 | } | |
525 | } | |
526 | ||
eaa3783b | 527 | static TCGv_reg dest_gpr(DisasContext *ctx, unsigned reg) |
61766fe9 | 528 | { |
129e9cc3 | 529 | if (reg == 0 || ctx->null_cond.c != TCG_COND_NEVER) { |
61766fe9 RH |
530 | return get_temp(ctx); |
531 | } else { | |
532 | return cpu_gr[reg]; | |
533 | } | |
534 | } | |
535 | ||
eaa3783b | 536 | static void save_or_nullify(DisasContext *ctx, TCGv_reg dest, TCGv_reg t) |
129e9cc3 RH |
537 | { |
538 | if (ctx->null_cond.c != TCG_COND_NEVER) { | |
eaa3783b | 539 | tcg_gen_movcond_reg(ctx->null_cond.c, dest, ctx->null_cond.a0, |
6e94937a | 540 | ctx->null_cond.a1, dest, t); |
129e9cc3 | 541 | } else { |
eaa3783b | 542 | tcg_gen_mov_reg(dest, t); |
129e9cc3 RH |
543 | } |
544 | } | |
545 | ||
eaa3783b | 546 | static void save_gpr(DisasContext *ctx, unsigned reg, TCGv_reg t) |
129e9cc3 RH |
547 | { |
548 | if (reg != 0) { | |
549 | save_or_nullify(ctx, cpu_gr[reg], t); | |
550 | } | |
551 | } | |
552 | ||
e03b5686 | 553 | #if HOST_BIG_ENDIAN |
96d6407f RH |
554 | # define HI_OFS 0 |
555 | # define LO_OFS 4 | |
556 | #else | |
557 | # define HI_OFS 4 | |
558 | # define LO_OFS 0 | |
559 | #endif | |
560 | ||
561 | static TCGv_i32 load_frw_i32(unsigned rt) | |
562 | { | |
563 | TCGv_i32 ret = tcg_temp_new_i32(); | |
564 | tcg_gen_ld_i32(ret, cpu_env, | |
565 | offsetof(CPUHPPAState, fr[rt & 31]) | |
566 | + (rt & 32 ? LO_OFS : HI_OFS)); | |
567 | return ret; | |
568 | } | |
569 | ||
ebe9383c RH |
570 | static TCGv_i32 load_frw0_i32(unsigned rt) |
571 | { | |
572 | if (rt == 0) { | |
0992a930 RH |
573 | TCGv_i32 ret = tcg_temp_new_i32(); |
574 | tcg_gen_movi_i32(ret, 0); | |
575 | return ret; | |
ebe9383c RH |
576 | } else { |
577 | return load_frw_i32(rt); | |
578 | } | |
579 | } | |
580 | ||
581 | static TCGv_i64 load_frw0_i64(unsigned rt) | |
582 | { | |
0992a930 | 583 | TCGv_i64 ret = tcg_temp_new_i64(); |
ebe9383c | 584 | if (rt == 0) { |
0992a930 | 585 | tcg_gen_movi_i64(ret, 0); |
ebe9383c | 586 | } else { |
ebe9383c RH |
587 | tcg_gen_ld32u_i64(ret, cpu_env, |
588 | offsetof(CPUHPPAState, fr[rt & 31]) | |
589 | + (rt & 32 ? LO_OFS : HI_OFS)); | |
ebe9383c | 590 | } |
0992a930 | 591 | return ret; |
ebe9383c RH |
592 | } |
593 | ||
96d6407f RH |
594 | static void save_frw_i32(unsigned rt, TCGv_i32 val) |
595 | { | |
596 | tcg_gen_st_i32(val, cpu_env, | |
597 | offsetof(CPUHPPAState, fr[rt & 31]) | |
598 | + (rt & 32 ? LO_OFS : HI_OFS)); | |
599 | } | |
600 | ||
601 | #undef HI_OFS | |
602 | #undef LO_OFS | |
603 | ||
604 | static TCGv_i64 load_frd(unsigned rt) | |
605 | { | |
606 | TCGv_i64 ret = tcg_temp_new_i64(); | |
607 | tcg_gen_ld_i64(ret, cpu_env, offsetof(CPUHPPAState, fr[rt])); | |
608 | return ret; | |
609 | } | |
610 | ||
ebe9383c RH |
611 | static TCGv_i64 load_frd0(unsigned rt) |
612 | { | |
613 | if (rt == 0) { | |
0992a930 RH |
614 | TCGv_i64 ret = tcg_temp_new_i64(); |
615 | tcg_gen_movi_i64(ret, 0); | |
616 | return ret; | |
ebe9383c RH |
617 | } else { |
618 | return load_frd(rt); | |
619 | } | |
620 | } | |
621 | ||
96d6407f RH |
622 | static void save_frd(unsigned rt, TCGv_i64 val) |
623 | { | |
624 | tcg_gen_st_i64(val, cpu_env, offsetof(CPUHPPAState, fr[rt])); | |
625 | } | |
626 | ||
33423472 RH |
627 | static void load_spr(DisasContext *ctx, TCGv_i64 dest, unsigned reg) |
628 | { | |
629 | #ifdef CONFIG_USER_ONLY | |
630 | tcg_gen_movi_i64(dest, 0); | |
631 | #else | |
632 | if (reg < 4) { | |
633 | tcg_gen_mov_i64(dest, cpu_sr[reg]); | |
494737b7 RH |
634 | } else if (ctx->tb_flags & TB_FLAG_SR_SAME) { |
635 | tcg_gen_mov_i64(dest, cpu_srH); | |
33423472 RH |
636 | } else { |
637 | tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUHPPAState, sr[reg])); | |
638 | } | |
639 | #endif | |
640 | } | |
641 | ||
129e9cc3 RH |
642 | /* Skip over the implementation of an insn that has been nullified. |
643 | Use this when the insn is too complex for a conditional move. */ | |
644 | static void nullify_over(DisasContext *ctx) | |
645 | { | |
646 | if (ctx->null_cond.c != TCG_COND_NEVER) { | |
647 | /* The always condition should have been handled in the main loop. */ | |
648 | assert(ctx->null_cond.c != TCG_COND_ALWAYS); | |
649 | ||
650 | ctx->null_lab = gen_new_label(); | |
129e9cc3 RH |
651 | |
652 | /* If we're using PSW[N], copy it to a temp because... */ | |
6e94937a | 653 | if (ctx->null_cond.a0 == cpu_psw_n) { |
129e9cc3 | 654 | ctx->null_cond.a0 = tcg_temp_new(); |
eaa3783b | 655 | tcg_gen_mov_reg(ctx->null_cond.a0, cpu_psw_n); |
129e9cc3 RH |
656 | } |
657 | /* ... we clear it before branching over the implementation, | |
658 | so that (1) it's clear after nullifying this insn and | |
659 | (2) if this insn nullifies the next, PSW[N] is valid. */ | |
660 | if (ctx->psw_n_nonzero) { | |
661 | ctx->psw_n_nonzero = false; | |
eaa3783b | 662 | tcg_gen_movi_reg(cpu_psw_n, 0); |
129e9cc3 RH |
663 | } |
664 | ||
eaa3783b | 665 | tcg_gen_brcond_reg(ctx->null_cond.c, ctx->null_cond.a0, |
6e94937a | 666 | ctx->null_cond.a1, ctx->null_lab); |
129e9cc3 RH |
667 | cond_free(&ctx->null_cond); |
668 | } | |
669 | } | |
670 | ||
671 | /* Save the current nullification state to PSW[N]. */ | |
672 | static void nullify_save(DisasContext *ctx) | |
673 | { | |
674 | if (ctx->null_cond.c == TCG_COND_NEVER) { | |
675 | if (ctx->psw_n_nonzero) { | |
eaa3783b | 676 | tcg_gen_movi_reg(cpu_psw_n, 0); |
129e9cc3 RH |
677 | } |
678 | return; | |
679 | } | |
6e94937a | 680 | if (ctx->null_cond.a0 != cpu_psw_n) { |
eaa3783b | 681 | tcg_gen_setcond_reg(ctx->null_cond.c, cpu_psw_n, |
6e94937a | 682 | ctx->null_cond.a0, ctx->null_cond.a1); |
129e9cc3 RH |
683 | ctx->psw_n_nonzero = true; |
684 | } | |
685 | cond_free(&ctx->null_cond); | |
686 | } | |
687 | ||
688 | /* Set a PSW[N] to X. The intention is that this is used immediately | |
689 | before a goto_tb/exit_tb, so that there is no fallthru path to other | |
690 | code within the TB. Therefore we do not update psw_n_nonzero. */ | |
691 | static void nullify_set(DisasContext *ctx, bool x) | |
692 | { | |
693 | if (ctx->psw_n_nonzero || x) { | |
eaa3783b | 694 | tcg_gen_movi_reg(cpu_psw_n, x); |
129e9cc3 RH |
695 | } |
696 | } | |
697 | ||
698 | /* Mark the end of an instruction that may have been nullified. | |
40f9f908 RH |
699 | This is the pair to nullify_over. Always returns true so that |
700 | it may be tail-called from a translate function. */ | |
31234768 | 701 | static bool nullify_end(DisasContext *ctx) |
129e9cc3 RH |
702 | { |
703 | TCGLabel *null_lab = ctx->null_lab; | |
31234768 | 704 | DisasJumpType status = ctx->base.is_jmp; |
129e9cc3 | 705 | |
f49b3537 RH |
706 | /* For NEXT, NORETURN, STALE, we can easily continue (or exit). |
707 | For UPDATED, we cannot update on the nullified path. */ | |
708 | assert(status != DISAS_IAQ_N_UPDATED); | |
709 | ||
129e9cc3 RH |
710 | if (likely(null_lab == NULL)) { |
711 | /* The current insn wasn't conditional or handled the condition | |
712 | applied to it without a branch, so the (new) setting of | |
713 | NULL_COND can be applied directly to the next insn. */ | |
31234768 | 714 | return true; |
129e9cc3 RH |
715 | } |
716 | ctx->null_lab = NULL; | |
717 | ||
718 | if (likely(ctx->null_cond.c == TCG_COND_NEVER)) { | |
719 | /* The next instruction will be unconditional, | |
720 | and NULL_COND already reflects that. */ | |
721 | gen_set_label(null_lab); | |
722 | } else { | |
723 | /* The insn that we just executed is itself nullifying the next | |
724 | instruction. Store the condition in the PSW[N] global. | |
725 | We asserted PSW[N] = 0 in nullify_over, so that after the | |
726 | label we have the proper value in place. */ | |
727 | nullify_save(ctx); | |
728 | gen_set_label(null_lab); | |
729 | ctx->null_cond = cond_make_n(); | |
730 | } | |
869051ea | 731 | if (status == DISAS_NORETURN) { |
31234768 | 732 | ctx->base.is_jmp = DISAS_NEXT; |
129e9cc3 | 733 | } |
31234768 | 734 | return true; |
129e9cc3 RH |
735 | } |
736 | ||
eaa3783b | 737 | static void copy_iaoq_entry(TCGv_reg dest, target_ureg ival, TCGv_reg vval) |
61766fe9 RH |
738 | { |
739 | if (unlikely(ival == -1)) { | |
eaa3783b | 740 | tcg_gen_mov_reg(dest, vval); |
61766fe9 | 741 | } else { |
eaa3783b | 742 | tcg_gen_movi_reg(dest, ival); |
61766fe9 RH |
743 | } |
744 | } | |
745 | ||
eaa3783b | 746 | static inline target_ureg iaoq_dest(DisasContext *ctx, target_sreg disp) |
61766fe9 RH |
747 | { |
748 | return ctx->iaoq_f + disp + 8; | |
749 | } | |
750 | ||
751 | static void gen_excp_1(int exception) | |
752 | { | |
29dd6f64 | 753 | gen_helper_excp(cpu_env, tcg_constant_i32(exception)); |
61766fe9 RH |
754 | } |
755 | ||
31234768 | 756 | static void gen_excp(DisasContext *ctx, int exception) |
61766fe9 RH |
757 | { |
758 | copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_f, cpu_iaoq_f); | |
759 | copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_b, cpu_iaoq_b); | |
129e9cc3 | 760 | nullify_save(ctx); |
61766fe9 | 761 | gen_excp_1(exception); |
31234768 | 762 | ctx->base.is_jmp = DISAS_NORETURN; |
61766fe9 RH |
763 | } |
764 | ||
31234768 | 765 | static bool gen_excp_iir(DisasContext *ctx, int exc) |
1a19da0d | 766 | { |
31234768 | 767 | nullify_over(ctx); |
29dd6f64 RH |
768 | tcg_gen_st_reg(tcg_constant_reg(ctx->insn), |
769 | cpu_env, offsetof(CPUHPPAState, cr[CR_IIR])); | |
31234768 RH |
770 | gen_excp(ctx, exc); |
771 | return nullify_end(ctx); | |
1a19da0d RH |
772 | } |
773 | ||
31234768 | 774 | static bool gen_illegal(DisasContext *ctx) |
61766fe9 | 775 | { |
31234768 | 776 | return gen_excp_iir(ctx, EXCP_ILL); |
61766fe9 RH |
777 | } |
778 | ||
40f9f908 RH |
779 | #ifdef CONFIG_USER_ONLY |
780 | #define CHECK_MOST_PRIVILEGED(EXCP) \ | |
781 | return gen_excp_iir(ctx, EXCP) | |
782 | #else | |
783 | #define CHECK_MOST_PRIVILEGED(EXCP) \ | |
31234768 RH |
784 | do { \ |
785 | if (ctx->privilege != 0) { \ | |
786 | return gen_excp_iir(ctx, EXCP); \ | |
787 | } \ | |
e1b5a5ed | 788 | } while (0) |
40f9f908 | 789 | #endif |
e1b5a5ed | 790 | |
eaa3783b | 791 | static bool use_goto_tb(DisasContext *ctx, target_ureg dest) |
61766fe9 | 792 | { |
57f91498 | 793 | return translator_use_goto_tb(&ctx->base, dest); |
61766fe9 RH |
794 | } |
795 | ||
129e9cc3 RH |
796 | /* If the next insn is to be nullified, and it's on the same page, |
797 | and we're not attempting to set a breakpoint on it, then we can | |
798 | totally skip the nullified insn. This avoids creating and | |
799 | executing a TB that merely branches to the next TB. */ | |
800 | static bool use_nullify_skip(DisasContext *ctx) | |
801 | { | |
802 | return (((ctx->iaoq_b ^ ctx->iaoq_f) & TARGET_PAGE_MASK) == 0 | |
803 | && !cpu_breakpoint_test(ctx->cs, ctx->iaoq_b, BP_ANY)); | |
804 | } | |
805 | ||
61766fe9 | 806 | static void gen_goto_tb(DisasContext *ctx, int which, |
eaa3783b | 807 | target_ureg f, target_ureg b) |
61766fe9 RH |
808 | { |
809 | if (f != -1 && b != -1 && use_goto_tb(ctx, f)) { | |
810 | tcg_gen_goto_tb(which); | |
eaa3783b RH |
811 | tcg_gen_movi_reg(cpu_iaoq_f, f); |
812 | tcg_gen_movi_reg(cpu_iaoq_b, b); | |
07ea28b4 | 813 | tcg_gen_exit_tb(ctx->base.tb, which); |
61766fe9 RH |
814 | } else { |
815 | copy_iaoq_entry(cpu_iaoq_f, f, cpu_iaoq_b); | |
816 | copy_iaoq_entry(cpu_iaoq_b, b, ctx->iaoq_n_var); | |
8532a14e | 817 | tcg_gen_lookup_and_goto_ptr(); |
61766fe9 RH |
818 | } |
819 | } | |
820 | ||
b47a4a02 SS |
821 | static bool cond_need_sv(int c) |
822 | { | |
823 | return c == 2 || c == 3 || c == 6; | |
824 | } | |
825 | ||
826 | static bool cond_need_cb(int c) | |
827 | { | |
828 | return c == 4 || c == 5; | |
829 | } | |
830 | ||
831 | /* | |
832 | * Compute conditional for arithmetic. See Page 5-3, Table 5-1, of | |
833 | * the Parisc 1.1 Architecture Reference Manual for details. | |
834 | */ | |
b2167459 | 835 | |
eaa3783b RH |
836 | static DisasCond do_cond(unsigned cf, TCGv_reg res, |
837 | TCGv_reg cb_msb, TCGv_reg sv) | |
b2167459 RH |
838 | { |
839 | DisasCond cond; | |
eaa3783b | 840 | TCGv_reg tmp; |
b2167459 RH |
841 | |
842 | switch (cf >> 1) { | |
b47a4a02 | 843 | case 0: /* Never / TR (0 / 1) */ |
b2167459 RH |
844 | cond = cond_make_f(); |
845 | break; | |
846 | case 1: /* = / <> (Z / !Z) */ | |
847 | cond = cond_make_0(TCG_COND_EQ, res); | |
848 | break; | |
b47a4a02 SS |
849 | case 2: /* < / >= (N ^ V / !(N ^ V) */ |
850 | tmp = tcg_temp_new(); | |
851 | tcg_gen_xor_reg(tmp, res, sv); | |
852 | cond = cond_make_0_tmp(TCG_COND_LT, tmp); | |
b2167459 | 853 | break; |
b47a4a02 SS |
854 | case 3: /* <= / > (N ^ V) | Z / !((N ^ V) | Z) */ |
855 | /* | |
856 | * Simplify: | |
857 | * (N ^ V) | Z | |
858 | * ((res < 0) ^ (sv < 0)) | !res | |
859 | * ((res ^ sv) < 0) | !res | |
860 | * (~(res ^ sv) >= 0) | !res | |
861 | * !(~(res ^ sv) >> 31) | !res | |
862 | * !(~(res ^ sv) >> 31 & res) | |
863 | */ | |
864 | tmp = tcg_temp_new(); | |
865 | tcg_gen_eqv_reg(tmp, res, sv); | |
866 | tcg_gen_sari_reg(tmp, tmp, TARGET_REGISTER_BITS - 1); | |
867 | tcg_gen_and_reg(tmp, tmp, res); | |
868 | cond = cond_make_0_tmp(TCG_COND_EQ, tmp); | |
b2167459 RH |
869 | break; |
870 | case 4: /* NUV / UV (!C / C) */ | |
871 | cond = cond_make_0(TCG_COND_EQ, cb_msb); | |
872 | break; | |
873 | case 5: /* ZNV / VNZ (!C | Z / C & !Z) */ | |
874 | tmp = tcg_temp_new(); | |
eaa3783b RH |
875 | tcg_gen_neg_reg(tmp, cb_msb); |
876 | tcg_gen_and_reg(tmp, tmp, res); | |
b47a4a02 | 877 | cond = cond_make_0_tmp(TCG_COND_EQ, tmp); |
b2167459 RH |
878 | break; |
879 | case 6: /* SV / NSV (V / !V) */ | |
880 | cond = cond_make_0(TCG_COND_LT, sv); | |
881 | break; | |
882 | case 7: /* OD / EV */ | |
883 | tmp = tcg_temp_new(); | |
eaa3783b | 884 | tcg_gen_andi_reg(tmp, res, 1); |
b47a4a02 | 885 | cond = cond_make_0_tmp(TCG_COND_NE, tmp); |
b2167459 RH |
886 | break; |
887 | default: | |
888 | g_assert_not_reached(); | |
889 | } | |
890 | if (cf & 1) { | |
891 | cond.c = tcg_invert_cond(cond.c); | |
892 | } | |
893 | ||
894 | return cond; | |
895 | } | |
896 | ||
897 | /* Similar, but for the special case of subtraction without borrow, we | |
898 | can use the inputs directly. This can allow other computation to be | |
899 | deleted as unused. */ | |
900 | ||
eaa3783b RH |
901 | static DisasCond do_sub_cond(unsigned cf, TCGv_reg res, |
902 | TCGv_reg in1, TCGv_reg in2, TCGv_reg sv) | |
b2167459 RH |
903 | { |
904 | DisasCond cond; | |
905 | ||
906 | switch (cf >> 1) { | |
907 | case 1: /* = / <> */ | |
908 | cond = cond_make(TCG_COND_EQ, in1, in2); | |
909 | break; | |
910 | case 2: /* < / >= */ | |
911 | cond = cond_make(TCG_COND_LT, in1, in2); | |
912 | break; | |
913 | case 3: /* <= / > */ | |
914 | cond = cond_make(TCG_COND_LE, in1, in2); | |
915 | break; | |
916 | case 4: /* << / >>= */ | |
917 | cond = cond_make(TCG_COND_LTU, in1, in2); | |
918 | break; | |
919 | case 5: /* <<= / >> */ | |
920 | cond = cond_make(TCG_COND_LEU, in1, in2); | |
921 | break; | |
922 | default: | |
b47a4a02 | 923 | return do_cond(cf, res, NULL, sv); |
b2167459 RH |
924 | } |
925 | if (cf & 1) { | |
926 | cond.c = tcg_invert_cond(cond.c); | |
927 | } | |
928 | ||
929 | return cond; | |
930 | } | |
931 | ||
df0232fe RH |
932 | /* |
933 | * Similar, but for logicals, where the carry and overflow bits are not | |
934 | * computed, and use of them is undefined. | |
935 | * | |
936 | * Undefined or not, hardware does not trap. It seems reasonable to | |
937 | * assume hardware treats cases c={4,5,6} as if C=0 & V=0, since that's | |
938 | * how cases c={2,3} are treated. | |
939 | */ | |
b2167459 | 940 | |
eaa3783b | 941 | static DisasCond do_log_cond(unsigned cf, TCGv_reg res) |
b2167459 | 942 | { |
df0232fe RH |
943 | switch (cf) { |
944 | case 0: /* never */ | |
945 | case 9: /* undef, C */ | |
946 | case 11: /* undef, C & !Z */ | |
947 | case 12: /* undef, V */ | |
948 | return cond_make_f(); | |
949 | ||
950 | case 1: /* true */ | |
951 | case 8: /* undef, !C */ | |
952 | case 10: /* undef, !C | Z */ | |
953 | case 13: /* undef, !V */ | |
954 | return cond_make_t(); | |
955 | ||
956 | case 2: /* == */ | |
957 | return cond_make_0(TCG_COND_EQ, res); | |
958 | case 3: /* <> */ | |
959 | return cond_make_0(TCG_COND_NE, res); | |
960 | case 4: /* < */ | |
961 | return cond_make_0(TCG_COND_LT, res); | |
962 | case 5: /* >= */ | |
963 | return cond_make_0(TCG_COND_GE, res); | |
964 | case 6: /* <= */ | |
965 | return cond_make_0(TCG_COND_LE, res); | |
966 | case 7: /* > */ | |
967 | return cond_make_0(TCG_COND_GT, res); | |
968 | ||
969 | case 14: /* OD */ | |
970 | case 15: /* EV */ | |
971 | return do_cond(cf, res, NULL, NULL); | |
972 | ||
973 | default: | |
974 | g_assert_not_reached(); | |
b2167459 | 975 | } |
b2167459 RH |
976 | } |
977 | ||
98cd9ca7 RH |
978 | /* Similar, but for shift/extract/deposit conditions. */ |
979 | ||
eaa3783b | 980 | static DisasCond do_sed_cond(unsigned orig, TCGv_reg res) |
98cd9ca7 RH |
981 | { |
982 | unsigned c, f; | |
983 | ||
984 | /* Convert the compressed condition codes to standard. | |
985 | 0-2 are the same as logicals (nv,<,<=), while 3 is OD. | |
986 | 4-7 are the reverse of 0-3. */ | |
987 | c = orig & 3; | |
988 | if (c == 3) { | |
989 | c = 7; | |
990 | } | |
991 | f = (orig & 4) / 4; | |
992 | ||
993 | return do_log_cond(c * 2 + f, res); | |
994 | } | |
995 | ||
b2167459 RH |
996 | /* Similar, but for unit conditions. */ |
997 | ||
eaa3783b RH |
998 | static DisasCond do_unit_cond(unsigned cf, TCGv_reg res, |
999 | TCGv_reg in1, TCGv_reg in2) | |
b2167459 RH |
1000 | { |
1001 | DisasCond cond; | |
eaa3783b | 1002 | TCGv_reg tmp, cb = NULL; |
b2167459 | 1003 | |
b2167459 RH |
1004 | if (cf & 8) { |
1005 | /* Since we want to test lots of carry-out bits all at once, do not | |
1006 | * do our normal thing and compute carry-in of bit B+1 since that | |
1007 | * leaves us with carry bits spread across two words. | |
1008 | */ | |
1009 | cb = tcg_temp_new(); | |
1010 | tmp = tcg_temp_new(); | |
eaa3783b RH |
1011 | tcg_gen_or_reg(cb, in1, in2); |
1012 | tcg_gen_and_reg(tmp, in1, in2); | |
1013 | tcg_gen_andc_reg(cb, cb, res); | |
1014 | tcg_gen_or_reg(cb, cb, tmp); | |
b2167459 RH |
1015 | } |
1016 | ||
1017 | switch (cf >> 1) { | |
1018 | case 0: /* never / TR */ | |
1019 | case 1: /* undefined */ | |
1020 | case 5: /* undefined */ | |
1021 | cond = cond_make_f(); | |
1022 | break; | |
1023 | ||
1024 | case 2: /* SBZ / NBZ */ | |
1025 | /* See hasless(v,1) from | |
1026 | * https://graphics.stanford.edu/~seander/bithacks.html#ZeroInWord | |
1027 | */ | |
1028 | tmp = tcg_temp_new(); | |
eaa3783b RH |
1029 | tcg_gen_subi_reg(tmp, res, 0x01010101u); |
1030 | tcg_gen_andc_reg(tmp, tmp, res); | |
1031 | tcg_gen_andi_reg(tmp, tmp, 0x80808080u); | |
b2167459 | 1032 | cond = cond_make_0(TCG_COND_NE, tmp); |
b2167459 RH |
1033 | break; |
1034 | ||
1035 | case 3: /* SHZ / NHZ */ | |
1036 | tmp = tcg_temp_new(); | |
eaa3783b RH |
1037 | tcg_gen_subi_reg(tmp, res, 0x00010001u); |
1038 | tcg_gen_andc_reg(tmp, tmp, res); | |
1039 | tcg_gen_andi_reg(tmp, tmp, 0x80008000u); | |
b2167459 | 1040 | cond = cond_make_0(TCG_COND_NE, tmp); |
b2167459 RH |
1041 | break; |
1042 | ||
1043 | case 4: /* SDC / NDC */ | |
eaa3783b | 1044 | tcg_gen_andi_reg(cb, cb, 0x88888888u); |
b2167459 RH |
1045 | cond = cond_make_0(TCG_COND_NE, cb); |
1046 | break; | |
1047 | ||
1048 | case 6: /* SBC / NBC */ | |
eaa3783b | 1049 | tcg_gen_andi_reg(cb, cb, 0x80808080u); |
b2167459 RH |
1050 | cond = cond_make_0(TCG_COND_NE, cb); |
1051 | break; | |
1052 | ||
1053 | case 7: /* SHC / NHC */ | |
eaa3783b | 1054 | tcg_gen_andi_reg(cb, cb, 0x80008000u); |
b2167459 RH |
1055 | cond = cond_make_0(TCG_COND_NE, cb); |
1056 | break; | |
1057 | ||
1058 | default: | |
1059 | g_assert_not_reached(); | |
1060 | } | |
b2167459 RH |
1061 | if (cf & 1) { |
1062 | cond.c = tcg_invert_cond(cond.c); | |
1063 | } | |
1064 | ||
1065 | return cond; | |
1066 | } | |
1067 | ||
1068 | /* Compute signed overflow for addition. */ | |
eaa3783b RH |
1069 | static TCGv_reg do_add_sv(DisasContext *ctx, TCGv_reg res, |
1070 | TCGv_reg in1, TCGv_reg in2) | |
b2167459 | 1071 | { |
eaa3783b RH |
1072 | TCGv_reg sv = get_temp(ctx); |
1073 | TCGv_reg tmp = tcg_temp_new(); | |
b2167459 | 1074 | |
eaa3783b RH |
1075 | tcg_gen_xor_reg(sv, res, in1); |
1076 | tcg_gen_xor_reg(tmp, in1, in2); | |
1077 | tcg_gen_andc_reg(sv, sv, tmp); | |
b2167459 RH |
1078 | |
1079 | return sv; | |
1080 | } | |
1081 | ||
1082 | /* Compute signed overflow for subtraction. */ | |
eaa3783b RH |
1083 | static TCGv_reg do_sub_sv(DisasContext *ctx, TCGv_reg res, |
1084 | TCGv_reg in1, TCGv_reg in2) | |
b2167459 | 1085 | { |
eaa3783b RH |
1086 | TCGv_reg sv = get_temp(ctx); |
1087 | TCGv_reg tmp = tcg_temp_new(); | |
b2167459 | 1088 | |
eaa3783b RH |
1089 | tcg_gen_xor_reg(sv, res, in1); |
1090 | tcg_gen_xor_reg(tmp, in1, in2); | |
1091 | tcg_gen_and_reg(sv, sv, tmp); | |
b2167459 RH |
1092 | |
1093 | return sv; | |
1094 | } | |
1095 | ||
31234768 RH |
1096 | static void do_add(DisasContext *ctx, unsigned rt, TCGv_reg in1, |
1097 | TCGv_reg in2, unsigned shift, bool is_l, | |
1098 | bool is_tsv, bool is_tc, bool is_c, unsigned cf) | |
b2167459 | 1099 | { |
eaa3783b | 1100 | TCGv_reg dest, cb, cb_msb, sv, tmp; |
b2167459 RH |
1101 | unsigned c = cf >> 1; |
1102 | DisasCond cond; | |
1103 | ||
1104 | dest = tcg_temp_new(); | |
f764718d RH |
1105 | cb = NULL; |
1106 | cb_msb = NULL; | |
b2167459 RH |
1107 | |
1108 | if (shift) { | |
1109 | tmp = get_temp(ctx); | |
eaa3783b | 1110 | tcg_gen_shli_reg(tmp, in1, shift); |
b2167459 RH |
1111 | in1 = tmp; |
1112 | } | |
1113 | ||
b47a4a02 | 1114 | if (!is_l || cond_need_cb(c)) { |
29dd6f64 | 1115 | TCGv_reg zero = tcg_constant_reg(0); |
b2167459 | 1116 | cb_msb = get_temp(ctx); |
eaa3783b | 1117 | tcg_gen_add2_reg(dest, cb_msb, in1, zero, in2, zero); |
b2167459 | 1118 | if (is_c) { |
eaa3783b | 1119 | tcg_gen_add2_reg(dest, cb_msb, dest, cb_msb, cpu_psw_cb_msb, zero); |
b2167459 | 1120 | } |
b2167459 RH |
1121 | if (!is_l) { |
1122 | cb = get_temp(ctx); | |
eaa3783b RH |
1123 | tcg_gen_xor_reg(cb, in1, in2); |
1124 | tcg_gen_xor_reg(cb, cb, dest); | |
b2167459 RH |
1125 | } |
1126 | } else { | |
eaa3783b | 1127 | tcg_gen_add_reg(dest, in1, in2); |
b2167459 | 1128 | if (is_c) { |
eaa3783b | 1129 | tcg_gen_add_reg(dest, dest, cpu_psw_cb_msb); |
b2167459 RH |
1130 | } |
1131 | } | |
1132 | ||
1133 | /* Compute signed overflow if required. */ | |
f764718d | 1134 | sv = NULL; |
b47a4a02 | 1135 | if (is_tsv || cond_need_sv(c)) { |
b2167459 RH |
1136 | sv = do_add_sv(ctx, dest, in1, in2); |
1137 | if (is_tsv) { | |
1138 | /* ??? Need to include overflow from shift. */ | |
1139 | gen_helper_tsv(cpu_env, sv); | |
1140 | } | |
1141 | } | |
1142 | ||
1143 | /* Emit any conditional trap before any writeback. */ | |
1144 | cond = do_cond(cf, dest, cb_msb, sv); | |
1145 | if (is_tc) { | |
b2167459 | 1146 | tmp = tcg_temp_new(); |
eaa3783b | 1147 | tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); |
b2167459 | 1148 | gen_helper_tcond(cpu_env, tmp); |
b2167459 RH |
1149 | } |
1150 | ||
1151 | /* Write back the result. */ | |
1152 | if (!is_l) { | |
1153 | save_or_nullify(ctx, cpu_psw_cb, cb); | |
1154 | save_or_nullify(ctx, cpu_psw_cb_msb, cb_msb); | |
1155 | } | |
1156 | save_gpr(ctx, rt, dest); | |
b2167459 RH |
1157 | |
1158 | /* Install the new nullification. */ | |
1159 | cond_free(&ctx->null_cond); | |
1160 | ctx->null_cond = cond; | |
b2167459 RH |
1161 | } |
1162 | ||
0c982a28 RH |
1163 | static bool do_add_reg(DisasContext *ctx, arg_rrr_cf_sh *a, |
1164 | bool is_l, bool is_tsv, bool is_tc, bool is_c) | |
1165 | { | |
1166 | TCGv_reg tcg_r1, tcg_r2; | |
1167 | ||
1168 | if (a->cf) { | |
1169 | nullify_over(ctx); | |
1170 | } | |
1171 | tcg_r1 = load_gpr(ctx, a->r1); | |
1172 | tcg_r2 = load_gpr(ctx, a->r2); | |
1173 | do_add(ctx, a->t, tcg_r1, tcg_r2, a->sh, is_l, is_tsv, is_tc, is_c, a->cf); | |
1174 | return nullify_end(ctx); | |
1175 | } | |
1176 | ||
0588e061 RH |
1177 | static bool do_add_imm(DisasContext *ctx, arg_rri_cf *a, |
1178 | bool is_tsv, bool is_tc) | |
1179 | { | |
1180 | TCGv_reg tcg_im, tcg_r2; | |
1181 | ||
1182 | if (a->cf) { | |
1183 | nullify_over(ctx); | |
1184 | } | |
1185 | tcg_im = load_const(ctx, a->i); | |
1186 | tcg_r2 = load_gpr(ctx, a->r); | |
1187 | do_add(ctx, a->t, tcg_im, tcg_r2, 0, 0, is_tsv, is_tc, 0, a->cf); | |
1188 | return nullify_end(ctx); | |
1189 | } | |
1190 | ||
31234768 RH |
1191 | static void do_sub(DisasContext *ctx, unsigned rt, TCGv_reg in1, |
1192 | TCGv_reg in2, bool is_tsv, bool is_b, | |
1193 | bool is_tc, unsigned cf) | |
b2167459 | 1194 | { |
eaa3783b | 1195 | TCGv_reg dest, sv, cb, cb_msb, zero, tmp; |
b2167459 RH |
1196 | unsigned c = cf >> 1; |
1197 | DisasCond cond; | |
1198 | ||
1199 | dest = tcg_temp_new(); | |
1200 | cb = tcg_temp_new(); | |
1201 | cb_msb = tcg_temp_new(); | |
1202 | ||
29dd6f64 | 1203 | zero = tcg_constant_reg(0); |
b2167459 RH |
1204 | if (is_b) { |
1205 | /* DEST,C = IN1 + ~IN2 + C. */ | |
eaa3783b RH |
1206 | tcg_gen_not_reg(cb, in2); |
1207 | tcg_gen_add2_reg(dest, cb_msb, in1, zero, cpu_psw_cb_msb, zero); | |
1208 | tcg_gen_add2_reg(dest, cb_msb, dest, cb_msb, cb, zero); | |
1209 | tcg_gen_xor_reg(cb, cb, in1); | |
1210 | tcg_gen_xor_reg(cb, cb, dest); | |
b2167459 RH |
1211 | } else { |
1212 | /* DEST,C = IN1 + ~IN2 + 1. We can produce the same result in fewer | |
1213 | operations by seeding the high word with 1 and subtracting. */ | |
eaa3783b RH |
1214 | tcg_gen_movi_reg(cb_msb, 1); |
1215 | tcg_gen_sub2_reg(dest, cb_msb, in1, cb_msb, in2, zero); | |
1216 | tcg_gen_eqv_reg(cb, in1, in2); | |
1217 | tcg_gen_xor_reg(cb, cb, dest); | |
b2167459 | 1218 | } |
b2167459 RH |
1219 | |
1220 | /* Compute signed overflow if required. */ | |
f764718d | 1221 | sv = NULL; |
b47a4a02 | 1222 | if (is_tsv || cond_need_sv(c)) { |
b2167459 RH |
1223 | sv = do_sub_sv(ctx, dest, in1, in2); |
1224 | if (is_tsv) { | |
1225 | gen_helper_tsv(cpu_env, sv); | |
1226 | } | |
1227 | } | |
1228 | ||
1229 | /* Compute the condition. We cannot use the special case for borrow. */ | |
1230 | if (!is_b) { | |
1231 | cond = do_sub_cond(cf, dest, in1, in2, sv); | |
1232 | } else { | |
1233 | cond = do_cond(cf, dest, cb_msb, sv); | |
1234 | } | |
1235 | ||
1236 | /* Emit any conditional trap before any writeback. */ | |
1237 | if (is_tc) { | |
b2167459 | 1238 | tmp = tcg_temp_new(); |
eaa3783b | 1239 | tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); |
b2167459 | 1240 | gen_helper_tcond(cpu_env, tmp); |
b2167459 RH |
1241 | } |
1242 | ||
1243 | /* Write back the result. */ | |
1244 | save_or_nullify(ctx, cpu_psw_cb, cb); | |
1245 | save_or_nullify(ctx, cpu_psw_cb_msb, cb_msb); | |
1246 | save_gpr(ctx, rt, dest); | |
b2167459 RH |
1247 | |
1248 | /* Install the new nullification. */ | |
1249 | cond_free(&ctx->null_cond); | |
1250 | ctx->null_cond = cond; | |
b2167459 RH |
1251 | } |
1252 | ||
0c982a28 RH |
1253 | static bool do_sub_reg(DisasContext *ctx, arg_rrr_cf *a, |
1254 | bool is_tsv, bool is_b, bool is_tc) | |
1255 | { | |
1256 | TCGv_reg tcg_r1, tcg_r2; | |
1257 | ||
1258 | if (a->cf) { | |
1259 | nullify_over(ctx); | |
1260 | } | |
1261 | tcg_r1 = load_gpr(ctx, a->r1); | |
1262 | tcg_r2 = load_gpr(ctx, a->r2); | |
1263 | do_sub(ctx, a->t, tcg_r1, tcg_r2, is_tsv, is_b, is_tc, a->cf); | |
1264 | return nullify_end(ctx); | |
1265 | } | |
1266 | ||
0588e061 RH |
1267 | static bool do_sub_imm(DisasContext *ctx, arg_rri_cf *a, bool is_tsv) |
1268 | { | |
1269 | TCGv_reg tcg_im, tcg_r2; | |
1270 | ||
1271 | if (a->cf) { | |
1272 | nullify_over(ctx); | |
1273 | } | |
1274 | tcg_im = load_const(ctx, a->i); | |
1275 | tcg_r2 = load_gpr(ctx, a->r); | |
1276 | do_sub(ctx, a->t, tcg_im, tcg_r2, is_tsv, 0, 0, a->cf); | |
1277 | return nullify_end(ctx); | |
1278 | } | |
1279 | ||
31234768 RH |
1280 | static void do_cmpclr(DisasContext *ctx, unsigned rt, TCGv_reg in1, |
1281 | TCGv_reg in2, unsigned cf) | |
b2167459 | 1282 | { |
eaa3783b | 1283 | TCGv_reg dest, sv; |
b2167459 RH |
1284 | DisasCond cond; |
1285 | ||
1286 | dest = tcg_temp_new(); | |
eaa3783b | 1287 | tcg_gen_sub_reg(dest, in1, in2); |
b2167459 RH |
1288 | |
1289 | /* Compute signed overflow if required. */ | |
f764718d | 1290 | sv = NULL; |
b47a4a02 | 1291 | if (cond_need_sv(cf >> 1)) { |
b2167459 RH |
1292 | sv = do_sub_sv(ctx, dest, in1, in2); |
1293 | } | |
1294 | ||
1295 | /* Form the condition for the compare. */ | |
1296 | cond = do_sub_cond(cf, dest, in1, in2, sv); | |
1297 | ||
1298 | /* Clear. */ | |
eaa3783b | 1299 | tcg_gen_movi_reg(dest, 0); |
b2167459 | 1300 | save_gpr(ctx, rt, dest); |
b2167459 RH |
1301 | |
1302 | /* Install the new nullification. */ | |
1303 | cond_free(&ctx->null_cond); | |
1304 | ctx->null_cond = cond; | |
b2167459 RH |
1305 | } |
1306 | ||
31234768 RH |
1307 | static void do_log(DisasContext *ctx, unsigned rt, TCGv_reg in1, |
1308 | TCGv_reg in2, unsigned cf, | |
1309 | void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) | |
b2167459 | 1310 | { |
eaa3783b | 1311 | TCGv_reg dest = dest_gpr(ctx, rt); |
b2167459 RH |
1312 | |
1313 | /* Perform the operation, and writeback. */ | |
1314 | fn(dest, in1, in2); | |
1315 | save_gpr(ctx, rt, dest); | |
1316 | ||
1317 | /* Install the new nullification. */ | |
1318 | cond_free(&ctx->null_cond); | |
1319 | if (cf) { | |
1320 | ctx->null_cond = do_log_cond(cf, dest); | |
1321 | } | |
b2167459 RH |
1322 | } |
1323 | ||
0c982a28 RH |
1324 | static bool do_log_reg(DisasContext *ctx, arg_rrr_cf *a, |
1325 | void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) | |
1326 | { | |
1327 | TCGv_reg tcg_r1, tcg_r2; | |
1328 | ||
1329 | if (a->cf) { | |
1330 | nullify_over(ctx); | |
1331 | } | |
1332 | tcg_r1 = load_gpr(ctx, a->r1); | |
1333 | tcg_r2 = load_gpr(ctx, a->r2); | |
1334 | do_log(ctx, a->t, tcg_r1, tcg_r2, a->cf, fn); | |
1335 | return nullify_end(ctx); | |
1336 | } | |
1337 | ||
31234768 RH |
1338 | static void do_unit(DisasContext *ctx, unsigned rt, TCGv_reg in1, |
1339 | TCGv_reg in2, unsigned cf, bool is_tc, | |
1340 | void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) | |
b2167459 | 1341 | { |
eaa3783b | 1342 | TCGv_reg dest; |
b2167459 RH |
1343 | DisasCond cond; |
1344 | ||
1345 | if (cf == 0) { | |
1346 | dest = dest_gpr(ctx, rt); | |
1347 | fn(dest, in1, in2); | |
1348 | save_gpr(ctx, rt, dest); | |
1349 | cond_free(&ctx->null_cond); | |
1350 | } else { | |
1351 | dest = tcg_temp_new(); | |
1352 | fn(dest, in1, in2); | |
1353 | ||
1354 | cond = do_unit_cond(cf, dest, in1, in2); | |
1355 | ||
1356 | if (is_tc) { | |
eaa3783b | 1357 | TCGv_reg tmp = tcg_temp_new(); |
eaa3783b | 1358 | tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); |
b2167459 | 1359 | gen_helper_tcond(cpu_env, tmp); |
b2167459 RH |
1360 | } |
1361 | save_gpr(ctx, rt, dest); | |
1362 | ||
1363 | cond_free(&ctx->null_cond); | |
1364 | ctx->null_cond = cond; | |
1365 | } | |
b2167459 RH |
1366 | } |
1367 | ||
86f8d05f | 1368 | #ifndef CONFIG_USER_ONLY |
8d6ae7fb RH |
1369 | /* The "normal" usage is SP >= 0, wherein SP == 0 selects the space |
1370 | from the top 2 bits of the base register. There are a few system | |
1371 | instructions that have a 3-bit space specifier, for which SR0 is | |
1372 | not special. To handle this, pass ~SP. */ | |
86f8d05f RH |
1373 | static TCGv_i64 space_select(DisasContext *ctx, int sp, TCGv_reg base) |
1374 | { | |
1375 | TCGv_ptr ptr; | |
1376 | TCGv_reg tmp; | |
1377 | TCGv_i64 spc; | |
1378 | ||
1379 | if (sp != 0) { | |
8d6ae7fb RH |
1380 | if (sp < 0) { |
1381 | sp = ~sp; | |
1382 | } | |
1383 | spc = get_temp_tl(ctx); | |
1384 | load_spr(ctx, spc, sp); | |
1385 | return spc; | |
86f8d05f | 1386 | } |
494737b7 RH |
1387 | if (ctx->tb_flags & TB_FLAG_SR_SAME) { |
1388 | return cpu_srH; | |
1389 | } | |
86f8d05f RH |
1390 | |
1391 | ptr = tcg_temp_new_ptr(); | |
1392 | tmp = tcg_temp_new(); | |
1393 | spc = get_temp_tl(ctx); | |
1394 | ||
1395 | tcg_gen_shri_reg(tmp, base, TARGET_REGISTER_BITS - 5); | |
1396 | tcg_gen_andi_reg(tmp, tmp, 030); | |
1397 | tcg_gen_trunc_reg_ptr(ptr, tmp); | |
86f8d05f RH |
1398 | |
1399 | tcg_gen_add_ptr(ptr, ptr, cpu_env); | |
1400 | tcg_gen_ld_i64(spc, ptr, offsetof(CPUHPPAState, sr[4])); | |
86f8d05f RH |
1401 | |
1402 | return spc; | |
1403 | } | |
1404 | #endif | |
1405 | ||
1406 | static void form_gva(DisasContext *ctx, TCGv_tl *pgva, TCGv_reg *pofs, | |
1407 | unsigned rb, unsigned rx, int scale, target_sreg disp, | |
1408 | unsigned sp, int modify, bool is_phys) | |
1409 | { | |
1410 | TCGv_reg base = load_gpr(ctx, rb); | |
1411 | TCGv_reg ofs; | |
1412 | ||
1413 | /* Note that RX is mutually exclusive with DISP. */ | |
1414 | if (rx) { | |
1415 | ofs = get_temp(ctx); | |
1416 | tcg_gen_shli_reg(ofs, cpu_gr[rx], scale); | |
1417 | tcg_gen_add_reg(ofs, ofs, base); | |
1418 | } else if (disp || modify) { | |
1419 | ofs = get_temp(ctx); | |
1420 | tcg_gen_addi_reg(ofs, base, disp); | |
1421 | } else { | |
1422 | ofs = base; | |
1423 | } | |
1424 | ||
1425 | *pofs = ofs; | |
1426 | #ifdef CONFIG_USER_ONLY | |
1427 | *pgva = (modify <= 0 ? ofs : base); | |
1428 | #else | |
1429 | TCGv_tl addr = get_temp_tl(ctx); | |
1430 | tcg_gen_extu_reg_tl(addr, modify <= 0 ? ofs : base); | |
494737b7 | 1431 | if (ctx->tb_flags & PSW_W) { |
86f8d05f RH |
1432 | tcg_gen_andi_tl(addr, addr, 0x3fffffffffffffffull); |
1433 | } | |
1434 | if (!is_phys) { | |
1435 | tcg_gen_or_tl(addr, addr, space_select(ctx, sp, base)); | |
1436 | } | |
1437 | *pgva = addr; | |
1438 | #endif | |
1439 | } | |
1440 | ||
96d6407f RH |
1441 | /* Emit a memory load. The modify parameter should be |
1442 | * < 0 for pre-modify, | |
1443 | * > 0 for post-modify, | |
1444 | * = 0 for no base register update. | |
1445 | */ | |
1446 | static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb, | |
eaa3783b | 1447 | unsigned rx, int scale, target_sreg disp, |
14776ab5 | 1448 | unsigned sp, int modify, MemOp mop) |
96d6407f | 1449 | { |
86f8d05f RH |
1450 | TCGv_reg ofs; |
1451 | TCGv_tl addr; | |
96d6407f RH |
1452 | |
1453 | /* Caller uses nullify_over/nullify_end. */ | |
1454 | assert(ctx->null_cond.c == TCG_COND_NEVER); | |
1455 | ||
86f8d05f RH |
1456 | form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, |
1457 | ctx->mmu_idx == MMU_PHYS_IDX); | |
217d1a5e | 1458 | tcg_gen_qemu_ld_reg(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); |
86f8d05f RH |
1459 | if (modify) { |
1460 | save_gpr(ctx, rb, ofs); | |
96d6407f | 1461 | } |
96d6407f RH |
1462 | } |
1463 | ||
1464 | static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb, | |
eaa3783b | 1465 | unsigned rx, int scale, target_sreg disp, |
14776ab5 | 1466 | unsigned sp, int modify, MemOp mop) |
96d6407f | 1467 | { |
86f8d05f RH |
1468 | TCGv_reg ofs; |
1469 | TCGv_tl addr; | |
96d6407f RH |
1470 | |
1471 | /* Caller uses nullify_over/nullify_end. */ | |
1472 | assert(ctx->null_cond.c == TCG_COND_NEVER); | |
1473 | ||
86f8d05f RH |
1474 | form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, |
1475 | ctx->mmu_idx == MMU_PHYS_IDX); | |
217d1a5e | 1476 | tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); |
86f8d05f RH |
1477 | if (modify) { |
1478 | save_gpr(ctx, rb, ofs); | |
96d6407f | 1479 | } |
96d6407f RH |
1480 | } |
1481 | ||
1482 | static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb, | |
eaa3783b | 1483 | unsigned rx, int scale, target_sreg disp, |
14776ab5 | 1484 | unsigned sp, int modify, MemOp mop) |
96d6407f | 1485 | { |
86f8d05f RH |
1486 | TCGv_reg ofs; |
1487 | TCGv_tl addr; | |
96d6407f RH |
1488 | |
1489 | /* Caller uses nullify_over/nullify_end. */ | |
1490 | assert(ctx->null_cond.c == TCG_COND_NEVER); | |
1491 | ||
86f8d05f RH |
1492 | form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, |
1493 | ctx->mmu_idx == MMU_PHYS_IDX); | |
217d1a5e | 1494 | tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); |
86f8d05f RH |
1495 | if (modify) { |
1496 | save_gpr(ctx, rb, ofs); | |
96d6407f | 1497 | } |
96d6407f RH |
1498 | } |
1499 | ||
1500 | static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb, | |
eaa3783b | 1501 | unsigned rx, int scale, target_sreg disp, |
14776ab5 | 1502 | unsigned sp, int modify, MemOp mop) |
96d6407f | 1503 | { |
86f8d05f RH |
1504 | TCGv_reg ofs; |
1505 | TCGv_tl addr; | |
96d6407f RH |
1506 | |
1507 | /* Caller uses nullify_over/nullify_end. */ | |
1508 | assert(ctx->null_cond.c == TCG_COND_NEVER); | |
1509 | ||
86f8d05f RH |
1510 | form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, |
1511 | ctx->mmu_idx == MMU_PHYS_IDX); | |
217d1a5e | 1512 | tcg_gen_qemu_st_i64(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); |
86f8d05f RH |
1513 | if (modify) { |
1514 | save_gpr(ctx, rb, ofs); | |
96d6407f | 1515 | } |
96d6407f RH |
1516 | } |
1517 | ||
eaa3783b RH |
1518 | #if TARGET_REGISTER_BITS == 64 |
1519 | #define do_load_reg do_load_64 | |
1520 | #define do_store_reg do_store_64 | |
96d6407f | 1521 | #else |
eaa3783b RH |
1522 | #define do_load_reg do_load_32 |
1523 | #define do_store_reg do_store_32 | |
96d6407f RH |
1524 | #endif |
1525 | ||
1cd012a5 | 1526 | static bool do_load(DisasContext *ctx, unsigned rt, unsigned rb, |
31234768 | 1527 | unsigned rx, int scale, target_sreg disp, |
14776ab5 | 1528 | unsigned sp, int modify, MemOp mop) |
96d6407f | 1529 | { |
eaa3783b | 1530 | TCGv_reg dest; |
96d6407f RH |
1531 | |
1532 | nullify_over(ctx); | |
1533 | ||
1534 | if (modify == 0) { | |
1535 | /* No base register update. */ | |
1536 | dest = dest_gpr(ctx, rt); | |
1537 | } else { | |
1538 | /* Make sure if RT == RB, we see the result of the load. */ | |
1539 | dest = get_temp(ctx); | |
1540 | } | |
86f8d05f | 1541 | do_load_reg(ctx, dest, rb, rx, scale, disp, sp, modify, mop); |
96d6407f RH |
1542 | save_gpr(ctx, rt, dest); |
1543 | ||
1cd012a5 | 1544 | return nullify_end(ctx); |
96d6407f RH |
1545 | } |
1546 | ||
740038d7 | 1547 | static bool do_floadw(DisasContext *ctx, unsigned rt, unsigned rb, |
31234768 RH |
1548 | unsigned rx, int scale, target_sreg disp, |
1549 | unsigned sp, int modify) | |
96d6407f RH |
1550 | { |
1551 | TCGv_i32 tmp; | |
1552 | ||
1553 | nullify_over(ctx); | |
1554 | ||
1555 | tmp = tcg_temp_new_i32(); | |
86f8d05f | 1556 | do_load_32(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEUL); |
96d6407f | 1557 | save_frw_i32(rt, tmp); |
96d6407f RH |
1558 | |
1559 | if (rt == 0) { | |
1560 | gen_helper_loaded_fr0(cpu_env); | |
1561 | } | |
1562 | ||
740038d7 RH |
1563 | return nullify_end(ctx); |
1564 | } | |
1565 | ||
1566 | static bool trans_fldw(DisasContext *ctx, arg_ldst *a) | |
1567 | { | |
1568 | return do_floadw(ctx, a->t, a->b, a->x, a->scale ? 2 : 0, | |
1569 | a->disp, a->sp, a->m); | |
96d6407f RH |
1570 | } |
1571 | ||
740038d7 | 1572 | static bool do_floadd(DisasContext *ctx, unsigned rt, unsigned rb, |
31234768 RH |
1573 | unsigned rx, int scale, target_sreg disp, |
1574 | unsigned sp, int modify) | |
96d6407f RH |
1575 | { |
1576 | TCGv_i64 tmp; | |
1577 | ||
1578 | nullify_over(ctx); | |
1579 | ||
1580 | tmp = tcg_temp_new_i64(); | |
fc313c64 | 1581 | do_load_64(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEUQ); |
96d6407f | 1582 | save_frd(rt, tmp); |
96d6407f RH |
1583 | |
1584 | if (rt == 0) { | |
1585 | gen_helper_loaded_fr0(cpu_env); | |
1586 | } | |
1587 | ||
740038d7 RH |
1588 | return nullify_end(ctx); |
1589 | } | |
1590 | ||
1591 | static bool trans_fldd(DisasContext *ctx, arg_ldst *a) | |
1592 | { | |
1593 | return do_floadd(ctx, a->t, a->b, a->x, a->scale ? 3 : 0, | |
1594 | a->disp, a->sp, a->m); | |
96d6407f RH |
1595 | } |
1596 | ||
1cd012a5 | 1597 | static bool do_store(DisasContext *ctx, unsigned rt, unsigned rb, |
31234768 | 1598 | target_sreg disp, unsigned sp, |
14776ab5 | 1599 | int modify, MemOp mop) |
96d6407f RH |
1600 | { |
1601 | nullify_over(ctx); | |
86f8d05f | 1602 | do_store_reg(ctx, load_gpr(ctx, rt), rb, 0, 0, disp, sp, modify, mop); |
1cd012a5 | 1603 | return nullify_end(ctx); |
96d6407f RH |
1604 | } |
1605 | ||
740038d7 | 1606 | static bool do_fstorew(DisasContext *ctx, unsigned rt, unsigned rb, |
31234768 RH |
1607 | unsigned rx, int scale, target_sreg disp, |
1608 | unsigned sp, int modify) | |
96d6407f RH |
1609 | { |
1610 | TCGv_i32 tmp; | |
1611 | ||
1612 | nullify_over(ctx); | |
1613 | ||
1614 | tmp = load_frw_i32(rt); | |
86f8d05f | 1615 | do_store_32(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEUL); |
96d6407f | 1616 | |
740038d7 RH |
1617 | return nullify_end(ctx); |
1618 | } | |
1619 | ||
1620 | static bool trans_fstw(DisasContext *ctx, arg_ldst *a) | |
1621 | { | |
1622 | return do_fstorew(ctx, a->t, a->b, a->x, a->scale ? 2 : 0, | |
1623 | a->disp, a->sp, a->m); | |
96d6407f RH |
1624 | } |
1625 | ||
740038d7 | 1626 | static bool do_fstored(DisasContext *ctx, unsigned rt, unsigned rb, |
31234768 RH |
1627 | unsigned rx, int scale, target_sreg disp, |
1628 | unsigned sp, int modify) | |
96d6407f RH |
1629 | { |
1630 | TCGv_i64 tmp; | |
1631 | ||
1632 | nullify_over(ctx); | |
1633 | ||
1634 | tmp = load_frd(rt); | |
fc313c64 | 1635 | do_store_64(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEUQ); |
96d6407f | 1636 | |
740038d7 RH |
1637 | return nullify_end(ctx); |
1638 | } | |
1639 | ||
1640 | static bool trans_fstd(DisasContext *ctx, arg_ldst *a) | |
1641 | { | |
1642 | return do_fstored(ctx, a->t, a->b, a->x, a->scale ? 3 : 0, | |
1643 | a->disp, a->sp, a->m); | |
96d6407f RH |
1644 | } |
1645 | ||
1ca74648 | 1646 | static bool do_fop_wew(DisasContext *ctx, unsigned rt, unsigned ra, |
31234768 | 1647 | void (*func)(TCGv_i32, TCGv_env, TCGv_i32)) |
ebe9383c RH |
1648 | { |
1649 | TCGv_i32 tmp; | |
1650 | ||
1651 | nullify_over(ctx); | |
1652 | tmp = load_frw0_i32(ra); | |
1653 | ||
1654 | func(tmp, cpu_env, tmp); | |
1655 | ||
1656 | save_frw_i32(rt, tmp); | |
1ca74648 | 1657 | return nullify_end(ctx); |
ebe9383c RH |
1658 | } |
1659 | ||
1ca74648 | 1660 | static bool do_fop_wed(DisasContext *ctx, unsigned rt, unsigned ra, |
31234768 | 1661 | void (*func)(TCGv_i32, TCGv_env, TCGv_i64)) |
ebe9383c RH |
1662 | { |
1663 | TCGv_i32 dst; | |
1664 | TCGv_i64 src; | |
1665 | ||
1666 | nullify_over(ctx); | |
1667 | src = load_frd(ra); | |
1668 | dst = tcg_temp_new_i32(); | |
1669 | ||
1670 | func(dst, cpu_env, src); | |
1671 | ||
ebe9383c | 1672 | save_frw_i32(rt, dst); |
1ca74648 | 1673 | return nullify_end(ctx); |
ebe9383c RH |
1674 | } |
1675 | ||
1ca74648 | 1676 | static bool do_fop_ded(DisasContext *ctx, unsigned rt, unsigned ra, |
31234768 | 1677 | void (*func)(TCGv_i64, TCGv_env, TCGv_i64)) |
ebe9383c RH |
1678 | { |
1679 | TCGv_i64 tmp; | |
1680 | ||
1681 | nullify_over(ctx); | |
1682 | tmp = load_frd0(ra); | |
1683 | ||
1684 | func(tmp, cpu_env, tmp); | |
1685 | ||
1686 | save_frd(rt, tmp); | |
1ca74648 | 1687 | return nullify_end(ctx); |
ebe9383c RH |
1688 | } |
1689 | ||
1ca74648 | 1690 | static bool do_fop_dew(DisasContext *ctx, unsigned rt, unsigned ra, |
31234768 | 1691 | void (*func)(TCGv_i64, TCGv_env, TCGv_i32)) |
ebe9383c RH |
1692 | { |
1693 | TCGv_i32 src; | |
1694 | TCGv_i64 dst; | |
1695 | ||
1696 | nullify_over(ctx); | |
1697 | src = load_frw0_i32(ra); | |
1698 | dst = tcg_temp_new_i64(); | |
1699 | ||
1700 | func(dst, cpu_env, src); | |
1701 | ||
ebe9383c | 1702 | save_frd(rt, dst); |
1ca74648 | 1703 | return nullify_end(ctx); |
ebe9383c RH |
1704 | } |
1705 | ||
1ca74648 | 1706 | static bool do_fop_weww(DisasContext *ctx, unsigned rt, |
31234768 RH |
1707 | unsigned ra, unsigned rb, |
1708 | void (*func)(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32)) | |
ebe9383c RH |
1709 | { |
1710 | TCGv_i32 a, b; | |
1711 | ||
1712 | nullify_over(ctx); | |
1713 | a = load_frw0_i32(ra); | |
1714 | b = load_frw0_i32(rb); | |
1715 | ||
1716 | func(a, cpu_env, a, b); | |
1717 | ||
ebe9383c | 1718 | save_frw_i32(rt, a); |
1ca74648 | 1719 | return nullify_end(ctx); |
ebe9383c RH |
1720 | } |
1721 | ||
1ca74648 | 1722 | static bool do_fop_dedd(DisasContext *ctx, unsigned rt, |
31234768 RH |
1723 | unsigned ra, unsigned rb, |
1724 | void (*func)(TCGv_i64, TCGv_env, TCGv_i64, TCGv_i64)) | |
ebe9383c RH |
1725 | { |
1726 | TCGv_i64 a, b; | |
1727 | ||
1728 | nullify_over(ctx); | |
1729 | a = load_frd0(ra); | |
1730 | b = load_frd0(rb); | |
1731 | ||
1732 | func(a, cpu_env, a, b); | |
1733 | ||
ebe9383c | 1734 | save_frd(rt, a); |
1ca74648 | 1735 | return nullify_end(ctx); |
ebe9383c RH |
1736 | } |
1737 | ||
98cd9ca7 RH |
1738 | /* Emit an unconditional branch to a direct target, which may or may not |
1739 | have already had nullification handled. */ | |
01afb7be | 1740 | static bool do_dbranch(DisasContext *ctx, target_ureg dest, |
31234768 | 1741 | unsigned link, bool is_n) |
98cd9ca7 RH |
1742 | { |
1743 | if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) { | |
1744 | if (link != 0) { | |
1745 | copy_iaoq_entry(cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); | |
1746 | } | |
1747 | ctx->iaoq_n = dest; | |
1748 | if (is_n) { | |
1749 | ctx->null_cond.c = TCG_COND_ALWAYS; | |
1750 | } | |
98cd9ca7 RH |
1751 | } else { |
1752 | nullify_over(ctx); | |
1753 | ||
1754 | if (link != 0) { | |
1755 | copy_iaoq_entry(cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); | |
1756 | } | |
1757 | ||
1758 | if (is_n && use_nullify_skip(ctx)) { | |
1759 | nullify_set(ctx, 0); | |
1760 | gen_goto_tb(ctx, 0, dest, dest + 4); | |
1761 | } else { | |
1762 | nullify_set(ctx, is_n); | |
1763 | gen_goto_tb(ctx, 0, ctx->iaoq_b, dest); | |
1764 | } | |
1765 | ||
31234768 | 1766 | nullify_end(ctx); |
98cd9ca7 RH |
1767 | |
1768 | nullify_set(ctx, 0); | |
1769 | gen_goto_tb(ctx, 1, ctx->iaoq_b, ctx->iaoq_n); | |
31234768 | 1770 | ctx->base.is_jmp = DISAS_NORETURN; |
98cd9ca7 | 1771 | } |
01afb7be | 1772 | return true; |
98cd9ca7 RH |
1773 | } |
1774 | ||
1775 | /* Emit a conditional branch to a direct target. If the branch itself | |
1776 | is nullified, we should have already used nullify_over. */ | |
01afb7be | 1777 | static bool do_cbranch(DisasContext *ctx, target_sreg disp, bool is_n, |
31234768 | 1778 | DisasCond *cond) |
98cd9ca7 | 1779 | { |
eaa3783b | 1780 | target_ureg dest = iaoq_dest(ctx, disp); |
98cd9ca7 RH |
1781 | TCGLabel *taken = NULL; |
1782 | TCGCond c = cond->c; | |
98cd9ca7 RH |
1783 | bool n; |
1784 | ||
1785 | assert(ctx->null_cond.c == TCG_COND_NEVER); | |
1786 | ||
1787 | /* Handle TRUE and NEVER as direct branches. */ | |
1788 | if (c == TCG_COND_ALWAYS) { | |
01afb7be | 1789 | return do_dbranch(ctx, dest, 0, is_n && disp >= 0); |
98cd9ca7 RH |
1790 | } |
1791 | if (c == TCG_COND_NEVER) { | |
01afb7be | 1792 | return do_dbranch(ctx, ctx->iaoq_n, 0, is_n && disp < 0); |
98cd9ca7 RH |
1793 | } |
1794 | ||
1795 | taken = gen_new_label(); | |
eaa3783b | 1796 | tcg_gen_brcond_reg(c, cond->a0, cond->a1, taken); |
98cd9ca7 RH |
1797 | cond_free(cond); |
1798 | ||
1799 | /* Not taken: Condition not satisfied; nullify on backward branches. */ | |
1800 | n = is_n && disp < 0; | |
1801 | if (n && use_nullify_skip(ctx)) { | |
1802 | nullify_set(ctx, 0); | |
a881c8e7 | 1803 | gen_goto_tb(ctx, 0, ctx->iaoq_n, ctx->iaoq_n + 4); |
98cd9ca7 RH |
1804 | } else { |
1805 | if (!n && ctx->null_lab) { | |
1806 | gen_set_label(ctx->null_lab); | |
1807 | ctx->null_lab = NULL; | |
1808 | } | |
1809 | nullify_set(ctx, n); | |
c301f34e RH |
1810 | if (ctx->iaoq_n == -1) { |
1811 | /* The temporary iaoq_n_var died at the branch above. | |
1812 | Regenerate it here instead of saving it. */ | |
1813 | tcg_gen_addi_reg(ctx->iaoq_n_var, cpu_iaoq_b, 4); | |
1814 | } | |
a881c8e7 | 1815 | gen_goto_tb(ctx, 0, ctx->iaoq_b, ctx->iaoq_n); |
98cd9ca7 RH |
1816 | } |
1817 | ||
1818 | gen_set_label(taken); | |
1819 | ||
1820 | /* Taken: Condition satisfied; nullify on forward branches. */ | |
1821 | n = is_n && disp >= 0; | |
1822 | if (n && use_nullify_skip(ctx)) { | |
1823 | nullify_set(ctx, 0); | |
a881c8e7 | 1824 | gen_goto_tb(ctx, 1, dest, dest + 4); |
98cd9ca7 RH |
1825 | } else { |
1826 | nullify_set(ctx, n); | |
a881c8e7 | 1827 | gen_goto_tb(ctx, 1, ctx->iaoq_b, dest); |
98cd9ca7 RH |
1828 | } |
1829 | ||
1830 | /* Not taken: the branch itself was nullified. */ | |
1831 | if (ctx->null_lab) { | |
1832 | gen_set_label(ctx->null_lab); | |
1833 | ctx->null_lab = NULL; | |
31234768 | 1834 | ctx->base.is_jmp = DISAS_IAQ_N_STALE; |
98cd9ca7 | 1835 | } else { |
31234768 | 1836 | ctx->base.is_jmp = DISAS_NORETURN; |
98cd9ca7 | 1837 | } |
01afb7be | 1838 | return true; |
98cd9ca7 RH |
1839 | } |
1840 | ||
1841 | /* Emit an unconditional branch to an indirect target. This handles | |
1842 | nullification of the branch itself. */ | |
01afb7be | 1843 | static bool do_ibranch(DisasContext *ctx, TCGv_reg dest, |
31234768 | 1844 | unsigned link, bool is_n) |
98cd9ca7 | 1845 | { |
eaa3783b | 1846 | TCGv_reg a0, a1, next, tmp; |
98cd9ca7 RH |
1847 | TCGCond c; |
1848 | ||
1849 | assert(ctx->null_lab == NULL); | |
1850 | ||
1851 | if (ctx->null_cond.c == TCG_COND_NEVER) { | |
1852 | if (link != 0) { | |
1853 | copy_iaoq_entry(cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); | |
1854 | } | |
1855 | next = get_temp(ctx); | |
eaa3783b | 1856 | tcg_gen_mov_reg(next, dest); |
98cd9ca7 | 1857 | if (is_n) { |
c301f34e RH |
1858 | if (use_nullify_skip(ctx)) { |
1859 | tcg_gen_mov_reg(cpu_iaoq_f, next); | |
1860 | tcg_gen_addi_reg(cpu_iaoq_b, next, 4); | |
1861 | nullify_set(ctx, 0); | |
31234768 | 1862 | ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; |
01afb7be | 1863 | return true; |
c301f34e | 1864 | } |
98cd9ca7 RH |
1865 | ctx->null_cond.c = TCG_COND_ALWAYS; |
1866 | } | |
c301f34e RH |
1867 | ctx->iaoq_n = -1; |
1868 | ctx->iaoq_n_var = next; | |
98cd9ca7 RH |
1869 | } else if (is_n && use_nullify_skip(ctx)) { |
1870 | /* The (conditional) branch, B, nullifies the next insn, N, | |
1871 | and we're allowed to skip execution N (no single-step or | |
4137cb83 | 1872 | tracepoint in effect). Since the goto_ptr that we must use |
98cd9ca7 RH |
1873 | for the indirect branch consumes no special resources, we |
1874 | can (conditionally) skip B and continue execution. */ | |
1875 | /* The use_nullify_skip test implies we have a known control path. */ | |
1876 | tcg_debug_assert(ctx->iaoq_b != -1); | |
1877 | tcg_debug_assert(ctx->iaoq_n != -1); | |
1878 | ||
1879 | /* We do have to handle the non-local temporary, DEST, before | |
1880 | branching. Since IOAQ_F is not really live at this point, we | |
1881 | can simply store DEST optimistically. Similarly with IAOQ_B. */ | |
eaa3783b RH |
1882 | tcg_gen_mov_reg(cpu_iaoq_f, dest); |
1883 | tcg_gen_addi_reg(cpu_iaoq_b, dest, 4); | |
98cd9ca7 RH |
1884 | |
1885 | nullify_over(ctx); | |
1886 | if (link != 0) { | |
eaa3783b | 1887 | tcg_gen_movi_reg(cpu_gr[link], ctx->iaoq_n); |
98cd9ca7 | 1888 | } |
7f11636d | 1889 | tcg_gen_lookup_and_goto_ptr(); |
01afb7be | 1890 | return nullify_end(ctx); |
98cd9ca7 | 1891 | } else { |
98cd9ca7 RH |
1892 | c = ctx->null_cond.c; |
1893 | a0 = ctx->null_cond.a0; | |
1894 | a1 = ctx->null_cond.a1; | |
1895 | ||
1896 | tmp = tcg_temp_new(); | |
1897 | next = get_temp(ctx); | |
1898 | ||
1899 | copy_iaoq_entry(tmp, ctx->iaoq_n, ctx->iaoq_n_var); | |
eaa3783b | 1900 | tcg_gen_movcond_reg(c, next, a0, a1, tmp, dest); |
98cd9ca7 RH |
1901 | ctx->iaoq_n = -1; |
1902 | ctx->iaoq_n_var = next; | |
1903 | ||
1904 | if (link != 0) { | |
eaa3783b | 1905 | tcg_gen_movcond_reg(c, cpu_gr[link], a0, a1, cpu_gr[link], tmp); |
98cd9ca7 RH |
1906 | } |
1907 | ||
1908 | if (is_n) { | |
1909 | /* The branch nullifies the next insn, which means the state of N | |
1910 | after the branch is the inverse of the state of N that applied | |
1911 | to the branch. */ | |
eaa3783b | 1912 | tcg_gen_setcond_reg(tcg_invert_cond(c), cpu_psw_n, a0, a1); |
98cd9ca7 RH |
1913 | cond_free(&ctx->null_cond); |
1914 | ctx->null_cond = cond_make_n(); | |
1915 | ctx->psw_n_nonzero = true; | |
1916 | } else { | |
1917 | cond_free(&ctx->null_cond); | |
1918 | } | |
1919 | } | |
01afb7be | 1920 | return true; |
98cd9ca7 RH |
1921 | } |
1922 | ||
660eefe1 RH |
1923 | /* Implement |
1924 | * if (IAOQ_Front{30..31} < GR[b]{30..31}) | |
1925 | * IAOQ_Next{30..31} ← GR[b]{30..31}; | |
1926 | * else | |
1927 | * IAOQ_Next{30..31} ← IAOQ_Front{30..31}; | |
1928 | * which keeps the privilege level from being increased. | |
1929 | */ | |
1930 | static TCGv_reg do_ibranch_priv(DisasContext *ctx, TCGv_reg offset) | |
1931 | { | |
660eefe1 RH |
1932 | TCGv_reg dest; |
1933 | switch (ctx->privilege) { | |
1934 | case 0: | |
1935 | /* Privilege 0 is maximum and is allowed to decrease. */ | |
1936 | return offset; | |
1937 | case 3: | |
993119fe | 1938 | /* Privilege 3 is minimum and is never allowed to increase. */ |
660eefe1 RH |
1939 | dest = get_temp(ctx); |
1940 | tcg_gen_ori_reg(dest, offset, 3); | |
1941 | break; | |
1942 | default: | |
993119fe | 1943 | dest = get_temp(ctx); |
660eefe1 RH |
1944 | tcg_gen_andi_reg(dest, offset, -4); |
1945 | tcg_gen_ori_reg(dest, dest, ctx->privilege); | |
1946 | tcg_gen_movcond_reg(TCG_COND_GTU, dest, dest, offset, dest, offset); | |
660eefe1 RH |
1947 | break; |
1948 | } | |
1949 | return dest; | |
660eefe1 RH |
1950 | } |
1951 | ||
ba1d0b44 | 1952 | #ifdef CONFIG_USER_ONLY |
7ad439df RH |
1953 | /* On Linux, page zero is normally marked execute only + gateway. |
1954 | Therefore normal read or write is supposed to fail, but specific | |
1955 | offsets have kernel code mapped to raise permissions to implement | |
1956 | system calls. Handling this via an explicit check here, rather | |
1957 | in than the "be disp(sr2,r0)" instruction that probably sent us | |
1958 | here, is the easiest way to handle the branch delay slot on the | |
1959 | aforementioned BE. */ | |
31234768 | 1960 | static void do_page_zero(DisasContext *ctx) |
7ad439df RH |
1961 | { |
1962 | /* If by some means we get here with PSW[N]=1, that implies that | |
1963 | the B,GATE instruction would be skipped, and we'd fault on the | |
1964 | next insn within the privilaged page. */ | |
1965 | switch (ctx->null_cond.c) { | |
1966 | case TCG_COND_NEVER: | |
1967 | break; | |
1968 | case TCG_COND_ALWAYS: | |
eaa3783b | 1969 | tcg_gen_movi_reg(cpu_psw_n, 0); |
7ad439df RH |
1970 | goto do_sigill; |
1971 | default: | |
1972 | /* Since this is always the first (and only) insn within the | |
1973 | TB, we should know the state of PSW[N] from TB->FLAGS. */ | |
1974 | g_assert_not_reached(); | |
1975 | } | |
1976 | ||
1977 | /* Check that we didn't arrive here via some means that allowed | |
1978 | non-sequential instruction execution. Normally the PSW[B] bit | |
1979 | detects this by disallowing the B,GATE instruction to execute | |
1980 | under such conditions. */ | |
1981 | if (ctx->iaoq_b != ctx->iaoq_f + 4) { | |
1982 | goto do_sigill; | |
1983 | } | |
1984 | ||
ebd0e151 | 1985 | switch (ctx->iaoq_f & -4) { |
7ad439df | 1986 | case 0x00: /* Null pointer call */ |
2986721d | 1987 | gen_excp_1(EXCP_IMP); |
31234768 RH |
1988 | ctx->base.is_jmp = DISAS_NORETURN; |
1989 | break; | |
7ad439df RH |
1990 | |
1991 | case 0xb0: /* LWS */ | |
1992 | gen_excp_1(EXCP_SYSCALL_LWS); | |
31234768 RH |
1993 | ctx->base.is_jmp = DISAS_NORETURN; |
1994 | break; | |
7ad439df RH |
1995 | |
1996 | case 0xe0: /* SET_THREAD_POINTER */ | |
35136a77 | 1997 | tcg_gen_st_reg(cpu_gr[26], cpu_env, offsetof(CPUHPPAState, cr[27])); |
ebd0e151 | 1998 | tcg_gen_ori_reg(cpu_iaoq_f, cpu_gr[31], 3); |
eaa3783b | 1999 | tcg_gen_addi_reg(cpu_iaoq_b, cpu_iaoq_f, 4); |
31234768 RH |
2000 | ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; |
2001 | break; | |
7ad439df RH |
2002 | |
2003 | case 0x100: /* SYSCALL */ | |
2004 | gen_excp_1(EXCP_SYSCALL); | |
31234768 RH |
2005 | ctx->base.is_jmp = DISAS_NORETURN; |
2006 | break; | |
7ad439df RH |
2007 | |
2008 | default: | |
2009 | do_sigill: | |
2986721d | 2010 | gen_excp_1(EXCP_ILL); |
31234768 RH |
2011 | ctx->base.is_jmp = DISAS_NORETURN; |
2012 | break; | |
7ad439df RH |
2013 | } |
2014 | } | |
ba1d0b44 | 2015 | #endif |
7ad439df | 2016 | |
deee69a1 | 2017 | static bool trans_nop(DisasContext *ctx, arg_nop *a) |
b2167459 RH |
2018 | { |
2019 | cond_free(&ctx->null_cond); | |
31234768 | 2020 | return true; |
b2167459 RH |
2021 | } |
2022 | ||
40f9f908 | 2023 | static bool trans_break(DisasContext *ctx, arg_break *a) |
98a9cb79 | 2024 | { |
31234768 | 2025 | return gen_excp_iir(ctx, EXCP_BREAK); |
98a9cb79 RH |
2026 | } |
2027 | ||
e36f27ef | 2028 | static bool trans_sync(DisasContext *ctx, arg_sync *a) |
98a9cb79 RH |
2029 | { |
2030 | /* No point in nullifying the memory barrier. */ | |
2031 | tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); | |
2032 | ||
2033 | cond_free(&ctx->null_cond); | |
31234768 | 2034 | return true; |
98a9cb79 RH |
2035 | } |
2036 | ||
c603e14a | 2037 | static bool trans_mfia(DisasContext *ctx, arg_mfia *a) |
98a9cb79 | 2038 | { |
c603e14a | 2039 | unsigned rt = a->t; |
eaa3783b RH |
2040 | TCGv_reg tmp = dest_gpr(ctx, rt); |
2041 | tcg_gen_movi_reg(tmp, ctx->iaoq_f); | |
98a9cb79 RH |
2042 | save_gpr(ctx, rt, tmp); |
2043 | ||
2044 | cond_free(&ctx->null_cond); | |
31234768 | 2045 | return true; |
98a9cb79 RH |
2046 | } |
2047 | ||
c603e14a | 2048 | static bool trans_mfsp(DisasContext *ctx, arg_mfsp *a) |
98a9cb79 | 2049 | { |
c603e14a RH |
2050 | unsigned rt = a->t; |
2051 | unsigned rs = a->sp; | |
33423472 RH |
2052 | TCGv_i64 t0 = tcg_temp_new_i64(); |
2053 | TCGv_reg t1 = tcg_temp_new(); | |
98a9cb79 | 2054 | |
33423472 RH |
2055 | load_spr(ctx, t0, rs); |
2056 | tcg_gen_shri_i64(t0, t0, 32); | |
2057 | tcg_gen_trunc_i64_reg(t1, t0); | |
2058 | ||
2059 | save_gpr(ctx, rt, t1); | |
98a9cb79 RH |
2060 | |
2061 | cond_free(&ctx->null_cond); | |
31234768 | 2062 | return true; |
98a9cb79 RH |
2063 | } |
2064 | ||
c603e14a | 2065 | static bool trans_mfctl(DisasContext *ctx, arg_mfctl *a) |
98a9cb79 | 2066 | { |
c603e14a RH |
2067 | unsigned rt = a->t; |
2068 | unsigned ctl = a->r; | |
eaa3783b | 2069 | TCGv_reg tmp; |
98a9cb79 RH |
2070 | |
2071 | switch (ctl) { | |
35136a77 | 2072 | case CR_SAR: |
98a9cb79 | 2073 | #ifdef TARGET_HPPA64 |
c603e14a | 2074 | if (a->e == 0) { |
98a9cb79 RH |
2075 | /* MFSAR without ,W masks low 5 bits. */ |
2076 | tmp = dest_gpr(ctx, rt); | |
eaa3783b | 2077 | tcg_gen_andi_reg(tmp, cpu_sar, 31); |
98a9cb79 | 2078 | save_gpr(ctx, rt, tmp); |
35136a77 | 2079 | goto done; |
98a9cb79 RH |
2080 | } |
2081 | #endif | |
2082 | save_gpr(ctx, rt, cpu_sar); | |
35136a77 RH |
2083 | goto done; |
2084 | case CR_IT: /* Interval Timer */ | |
2085 | /* FIXME: Respect PSW_S bit. */ | |
2086 | nullify_over(ctx); | |
98a9cb79 | 2087 | tmp = dest_gpr(ctx, rt); |
84b41e65 | 2088 | if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { |
49c29d6c RH |
2089 | gen_io_start(); |
2090 | gen_helper_read_interval_timer(tmp); | |
31234768 | 2091 | ctx->base.is_jmp = DISAS_IAQ_N_STALE; |
49c29d6c RH |
2092 | } else { |
2093 | gen_helper_read_interval_timer(tmp); | |
49c29d6c | 2094 | } |
98a9cb79 | 2095 | save_gpr(ctx, rt, tmp); |
31234768 | 2096 | return nullify_end(ctx); |
98a9cb79 | 2097 | case 26: |
98a9cb79 | 2098 | case 27: |
98a9cb79 RH |
2099 | break; |
2100 | default: | |
2101 | /* All other control registers are privileged. */ | |
35136a77 RH |
2102 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG); |
2103 | break; | |
98a9cb79 RH |
2104 | } |
2105 | ||
35136a77 RH |
2106 | tmp = get_temp(ctx); |
2107 | tcg_gen_ld_reg(tmp, cpu_env, offsetof(CPUHPPAState, cr[ctl])); | |
2108 | save_gpr(ctx, rt, tmp); | |
2109 | ||
2110 | done: | |
98a9cb79 | 2111 | cond_free(&ctx->null_cond); |
31234768 | 2112 | return true; |
98a9cb79 RH |
2113 | } |
2114 | ||
c603e14a | 2115 | static bool trans_mtsp(DisasContext *ctx, arg_mtsp *a) |
33423472 | 2116 | { |
c603e14a RH |
2117 | unsigned rr = a->r; |
2118 | unsigned rs = a->sp; | |
33423472 RH |
2119 | TCGv_i64 t64; |
2120 | ||
2121 | if (rs >= 5) { | |
2122 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG); | |
2123 | } | |
2124 | nullify_over(ctx); | |
2125 | ||
2126 | t64 = tcg_temp_new_i64(); | |
2127 | tcg_gen_extu_reg_i64(t64, load_gpr(ctx, rr)); | |
2128 | tcg_gen_shli_i64(t64, t64, 32); | |
2129 | ||
2130 | if (rs >= 4) { | |
2131 | tcg_gen_st_i64(t64, cpu_env, offsetof(CPUHPPAState, sr[rs])); | |
494737b7 | 2132 | ctx->tb_flags &= ~TB_FLAG_SR_SAME; |
33423472 RH |
2133 | } else { |
2134 | tcg_gen_mov_i64(cpu_sr[rs], t64); | |
2135 | } | |
33423472 | 2136 | |
31234768 | 2137 | return nullify_end(ctx); |
33423472 RH |
2138 | } |
2139 | ||
c603e14a | 2140 | static bool trans_mtctl(DisasContext *ctx, arg_mtctl *a) |
98a9cb79 | 2141 | { |
c603e14a | 2142 | unsigned ctl = a->t; |
4845f015 | 2143 | TCGv_reg reg; |
eaa3783b | 2144 | TCGv_reg tmp; |
98a9cb79 | 2145 | |
35136a77 | 2146 | if (ctl == CR_SAR) { |
4845f015 | 2147 | reg = load_gpr(ctx, a->r); |
98a9cb79 | 2148 | tmp = tcg_temp_new(); |
35136a77 | 2149 | tcg_gen_andi_reg(tmp, reg, TARGET_REGISTER_BITS - 1); |
98a9cb79 | 2150 | save_or_nullify(ctx, cpu_sar, tmp); |
35136a77 RH |
2151 | |
2152 | cond_free(&ctx->null_cond); | |
31234768 | 2153 | return true; |
98a9cb79 RH |
2154 | } |
2155 | ||
35136a77 RH |
2156 | /* All other control registers are privileged or read-only. */ |
2157 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG); | |
2158 | ||
c603e14a | 2159 | #ifndef CONFIG_USER_ONLY |
35136a77 | 2160 | nullify_over(ctx); |
4845f015 SS |
2161 | reg = load_gpr(ctx, a->r); |
2162 | ||
35136a77 RH |
2163 | switch (ctl) { |
2164 | case CR_IT: | |
49c29d6c | 2165 | gen_helper_write_interval_timer(cpu_env, reg); |
35136a77 | 2166 | break; |
4f5f2548 RH |
2167 | case CR_EIRR: |
2168 | gen_helper_write_eirr(cpu_env, reg); | |
2169 | break; | |
2170 | case CR_EIEM: | |
2171 | gen_helper_write_eiem(cpu_env, reg); | |
31234768 | 2172 | ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; |
4f5f2548 RH |
2173 | break; |
2174 | ||
35136a77 RH |
2175 | case CR_IIASQ: |
2176 | case CR_IIAOQ: | |
2177 | /* FIXME: Respect PSW_Q bit */ | |
2178 | /* The write advances the queue and stores to the back element. */ | |
2179 | tmp = get_temp(ctx); | |
2180 | tcg_gen_ld_reg(tmp, cpu_env, | |
2181 | offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ])); | |
2182 | tcg_gen_st_reg(tmp, cpu_env, offsetof(CPUHPPAState, cr[ctl])); | |
2183 | tcg_gen_st_reg(reg, cpu_env, | |
2184 | offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ])); | |
2185 | break; | |
2186 | ||
d5de20bd SS |
2187 | case CR_PID1: |
2188 | case CR_PID2: | |
2189 | case CR_PID3: | |
2190 | case CR_PID4: | |
2191 | tcg_gen_st_reg(reg, cpu_env, offsetof(CPUHPPAState, cr[ctl])); | |
2192 | #ifndef CONFIG_USER_ONLY | |
2193 | gen_helper_change_prot_id(cpu_env); | |
2194 | #endif | |
2195 | break; | |
2196 | ||
35136a77 RH |
2197 | default: |
2198 | tcg_gen_st_reg(reg, cpu_env, offsetof(CPUHPPAState, cr[ctl])); | |
2199 | break; | |
2200 | } | |
31234768 | 2201 | return nullify_end(ctx); |
4f5f2548 | 2202 | #endif |
98a9cb79 RH |
2203 | } |
2204 | ||
c603e14a | 2205 | static bool trans_mtsarcm(DisasContext *ctx, arg_mtsarcm *a) |
98a9cb79 | 2206 | { |
eaa3783b | 2207 | TCGv_reg tmp = tcg_temp_new(); |
98a9cb79 | 2208 | |
c603e14a | 2209 | tcg_gen_not_reg(tmp, load_gpr(ctx, a->r)); |
eaa3783b | 2210 | tcg_gen_andi_reg(tmp, tmp, TARGET_REGISTER_BITS - 1); |
98a9cb79 | 2211 | save_or_nullify(ctx, cpu_sar, tmp); |
98a9cb79 RH |
2212 | |
2213 | cond_free(&ctx->null_cond); | |
31234768 | 2214 | return true; |
98a9cb79 RH |
2215 | } |
2216 | ||
e36f27ef | 2217 | static bool trans_ldsid(DisasContext *ctx, arg_ldsid *a) |
98a9cb79 | 2218 | { |
e36f27ef | 2219 | TCGv_reg dest = dest_gpr(ctx, a->t); |
98a9cb79 | 2220 | |
2330504c HD |
2221 | #ifdef CONFIG_USER_ONLY |
2222 | /* We don't implement space registers in user mode. */ | |
eaa3783b | 2223 | tcg_gen_movi_reg(dest, 0); |
2330504c | 2224 | #else |
2330504c HD |
2225 | TCGv_i64 t0 = tcg_temp_new_i64(); |
2226 | ||
e36f27ef | 2227 | tcg_gen_mov_i64(t0, space_select(ctx, a->sp, load_gpr(ctx, a->b))); |
2330504c HD |
2228 | tcg_gen_shri_i64(t0, t0, 32); |
2229 | tcg_gen_trunc_i64_reg(dest, t0); | |
2330504c | 2230 | #endif |
e36f27ef | 2231 | save_gpr(ctx, a->t, dest); |
98a9cb79 RH |
2232 | |
2233 | cond_free(&ctx->null_cond); | |
31234768 | 2234 | return true; |
98a9cb79 RH |
2235 | } |
2236 | ||
e36f27ef | 2237 | static bool trans_rsm(DisasContext *ctx, arg_rsm *a) |
e1b5a5ed | 2238 | { |
e36f27ef RH |
2239 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); |
2240 | #ifndef CONFIG_USER_ONLY | |
e1b5a5ed RH |
2241 | TCGv_reg tmp; |
2242 | ||
e1b5a5ed RH |
2243 | nullify_over(ctx); |
2244 | ||
2245 | tmp = get_temp(ctx); | |
2246 | tcg_gen_ld_reg(tmp, cpu_env, offsetof(CPUHPPAState, psw)); | |
e36f27ef | 2247 | tcg_gen_andi_reg(tmp, tmp, ~a->i); |
e1b5a5ed | 2248 | gen_helper_swap_system_mask(tmp, cpu_env, tmp); |
e36f27ef | 2249 | save_gpr(ctx, a->t, tmp); |
e1b5a5ed RH |
2250 | |
2251 | /* Exit the TB to recognize new interrupts, e.g. PSW_M. */ | |
31234768 RH |
2252 | ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; |
2253 | return nullify_end(ctx); | |
e36f27ef | 2254 | #endif |
e1b5a5ed RH |
2255 | } |
2256 | ||
e36f27ef | 2257 | static bool trans_ssm(DisasContext *ctx, arg_ssm *a) |
e1b5a5ed | 2258 | { |
e36f27ef RH |
2259 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); |
2260 | #ifndef CONFIG_USER_ONLY | |
e1b5a5ed RH |
2261 | TCGv_reg tmp; |
2262 | ||
e1b5a5ed RH |
2263 | nullify_over(ctx); |
2264 | ||
2265 | tmp = get_temp(ctx); | |
2266 | tcg_gen_ld_reg(tmp, cpu_env, offsetof(CPUHPPAState, psw)); | |
e36f27ef | 2267 | tcg_gen_ori_reg(tmp, tmp, a->i); |
e1b5a5ed | 2268 | gen_helper_swap_system_mask(tmp, cpu_env, tmp); |
e36f27ef | 2269 | save_gpr(ctx, a->t, tmp); |
e1b5a5ed RH |
2270 | |
2271 | /* Exit the TB to recognize new interrupts, e.g. PSW_I. */ | |
31234768 RH |
2272 | ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; |
2273 | return nullify_end(ctx); | |
e36f27ef | 2274 | #endif |
e1b5a5ed RH |
2275 | } |
2276 | ||
c603e14a | 2277 | static bool trans_mtsm(DisasContext *ctx, arg_mtsm *a) |
e1b5a5ed | 2278 | { |
e1b5a5ed | 2279 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); |
c603e14a RH |
2280 | #ifndef CONFIG_USER_ONLY |
2281 | TCGv_reg tmp, reg; | |
e1b5a5ed RH |
2282 | nullify_over(ctx); |
2283 | ||
c603e14a | 2284 | reg = load_gpr(ctx, a->r); |
e1b5a5ed RH |
2285 | tmp = get_temp(ctx); |
2286 | gen_helper_swap_system_mask(tmp, cpu_env, reg); | |
2287 | ||
2288 | /* Exit the TB to recognize new interrupts. */ | |
31234768 RH |
2289 | ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; |
2290 | return nullify_end(ctx); | |
c603e14a | 2291 | #endif |
e1b5a5ed | 2292 | } |
f49b3537 | 2293 | |
e36f27ef | 2294 | static bool do_rfi(DisasContext *ctx, bool rfi_r) |
f49b3537 | 2295 | { |
f49b3537 | 2296 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); |
e36f27ef | 2297 | #ifndef CONFIG_USER_ONLY |
f49b3537 RH |
2298 | nullify_over(ctx); |
2299 | ||
e36f27ef | 2300 | if (rfi_r) { |
f49b3537 RH |
2301 | gen_helper_rfi_r(cpu_env); |
2302 | } else { | |
2303 | gen_helper_rfi(cpu_env); | |
2304 | } | |
31234768 | 2305 | /* Exit the TB to recognize new interrupts. */ |
8532a14e | 2306 | tcg_gen_exit_tb(NULL, 0); |
31234768 | 2307 | ctx->base.is_jmp = DISAS_NORETURN; |
f49b3537 | 2308 | |
31234768 | 2309 | return nullify_end(ctx); |
e36f27ef RH |
2310 | #endif |
2311 | } | |
2312 | ||
2313 | static bool trans_rfi(DisasContext *ctx, arg_rfi *a) | |
2314 | { | |
2315 | return do_rfi(ctx, false); | |
2316 | } | |
2317 | ||
2318 | static bool trans_rfi_r(DisasContext *ctx, arg_rfi_r *a) | |
2319 | { | |
2320 | return do_rfi(ctx, true); | |
f49b3537 | 2321 | } |
6210db05 | 2322 | |
96927adb RH |
2323 | static bool trans_halt(DisasContext *ctx, arg_halt *a) |
2324 | { | |
2325 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); | |
e36f27ef | 2326 | #ifndef CONFIG_USER_ONLY |
96927adb RH |
2327 | nullify_over(ctx); |
2328 | gen_helper_halt(cpu_env); | |
2329 | ctx->base.is_jmp = DISAS_NORETURN; | |
2330 | return nullify_end(ctx); | |
2331 | #endif | |
2332 | } | |
2333 | ||
2334 | static bool trans_reset(DisasContext *ctx, arg_reset *a) | |
6210db05 HD |
2335 | { |
2336 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); | |
96927adb | 2337 | #ifndef CONFIG_USER_ONLY |
6210db05 | 2338 | nullify_over(ctx); |
96927adb | 2339 | gen_helper_reset(cpu_env); |
31234768 RH |
2340 | ctx->base.is_jmp = DISAS_NORETURN; |
2341 | return nullify_end(ctx); | |
96927adb | 2342 | #endif |
6210db05 | 2343 | } |
e1b5a5ed | 2344 | |
4a4554c6 HD |
2345 | static bool trans_getshadowregs(DisasContext *ctx, arg_getshadowregs *a) |
2346 | { | |
2347 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); | |
2348 | #ifndef CONFIG_USER_ONLY | |
2349 | nullify_over(ctx); | |
2350 | gen_helper_getshadowregs(cpu_env); | |
2351 | return nullify_end(ctx); | |
2352 | #endif | |
2353 | } | |
2354 | ||
deee69a1 | 2355 | static bool trans_nop_addrx(DisasContext *ctx, arg_ldst *a) |
98a9cb79 | 2356 | { |
deee69a1 RH |
2357 | if (a->m) { |
2358 | TCGv_reg dest = dest_gpr(ctx, a->b); | |
2359 | TCGv_reg src1 = load_gpr(ctx, a->b); | |
2360 | TCGv_reg src2 = load_gpr(ctx, a->x); | |
98a9cb79 | 2361 | |
deee69a1 RH |
2362 | /* The only thing we need to do is the base register modification. */ |
2363 | tcg_gen_add_reg(dest, src1, src2); | |
2364 | save_gpr(ctx, a->b, dest); | |
2365 | } | |
98a9cb79 | 2366 | cond_free(&ctx->null_cond); |
31234768 | 2367 | return true; |
98a9cb79 RH |
2368 | } |
2369 | ||
deee69a1 | 2370 | static bool trans_probe(DisasContext *ctx, arg_probe *a) |
98a9cb79 | 2371 | { |
86f8d05f | 2372 | TCGv_reg dest, ofs; |
eed14219 | 2373 | TCGv_i32 level, want; |
86f8d05f | 2374 | TCGv_tl addr; |
98a9cb79 RH |
2375 | |
2376 | nullify_over(ctx); | |
2377 | ||
deee69a1 RH |
2378 | dest = dest_gpr(ctx, a->t); |
2379 | form_gva(ctx, &addr, &ofs, a->b, 0, 0, 0, a->sp, 0, false); | |
eed14219 | 2380 | |
deee69a1 | 2381 | if (a->imm) { |
29dd6f64 | 2382 | level = tcg_constant_i32(a->ri); |
98a9cb79 | 2383 | } else { |
eed14219 | 2384 | level = tcg_temp_new_i32(); |
deee69a1 | 2385 | tcg_gen_trunc_reg_i32(level, load_gpr(ctx, a->ri)); |
eed14219 | 2386 | tcg_gen_andi_i32(level, level, 3); |
98a9cb79 | 2387 | } |
29dd6f64 | 2388 | want = tcg_constant_i32(a->write ? PAGE_WRITE : PAGE_READ); |
eed14219 RH |
2389 | |
2390 | gen_helper_probe(dest, cpu_env, addr, level, want); | |
2391 | ||
deee69a1 | 2392 | save_gpr(ctx, a->t, dest); |
31234768 | 2393 | return nullify_end(ctx); |
98a9cb79 RH |
2394 | } |
2395 | ||
deee69a1 | 2396 | static bool trans_ixtlbx(DisasContext *ctx, arg_ixtlbx *a) |
8d6ae7fb | 2397 | { |
deee69a1 RH |
2398 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); |
2399 | #ifndef CONFIG_USER_ONLY | |
8d6ae7fb RH |
2400 | TCGv_tl addr; |
2401 | TCGv_reg ofs, reg; | |
2402 | ||
8d6ae7fb RH |
2403 | nullify_over(ctx); |
2404 | ||
deee69a1 RH |
2405 | form_gva(ctx, &addr, &ofs, a->b, 0, 0, 0, a->sp, 0, false); |
2406 | reg = load_gpr(ctx, a->r); | |
2407 | if (a->addr) { | |
8d6ae7fb RH |
2408 | gen_helper_itlba(cpu_env, addr, reg); |
2409 | } else { | |
2410 | gen_helper_itlbp(cpu_env, addr, reg); | |
2411 | } | |
2412 | ||
32dc7569 SS |
2413 | /* Exit TB for TLB change if mmu is enabled. */ |
2414 | if (ctx->tb_flags & PSW_C) { | |
31234768 RH |
2415 | ctx->base.is_jmp = DISAS_IAQ_N_STALE; |
2416 | } | |
2417 | return nullify_end(ctx); | |
deee69a1 | 2418 | #endif |
8d6ae7fb | 2419 | } |
63300a00 | 2420 | |
deee69a1 | 2421 | static bool trans_pxtlbx(DisasContext *ctx, arg_pxtlbx *a) |
63300a00 | 2422 | { |
deee69a1 RH |
2423 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); |
2424 | #ifndef CONFIG_USER_ONLY | |
63300a00 RH |
2425 | TCGv_tl addr; |
2426 | TCGv_reg ofs; | |
2427 | ||
63300a00 RH |
2428 | nullify_over(ctx); |
2429 | ||
deee69a1 RH |
2430 | form_gva(ctx, &addr, &ofs, a->b, a->x, 0, 0, a->sp, a->m, false); |
2431 | if (a->m) { | |
2432 | save_gpr(ctx, a->b, ofs); | |
63300a00 | 2433 | } |
deee69a1 | 2434 | if (a->local) { |
63300a00 RH |
2435 | gen_helper_ptlbe(cpu_env); |
2436 | } else { | |
2437 | gen_helper_ptlb(cpu_env, addr); | |
2438 | } | |
2439 | ||
2440 | /* Exit TB for TLB change if mmu is enabled. */ | |
6797c315 NH |
2441 | if (ctx->tb_flags & PSW_C) { |
2442 | ctx->base.is_jmp = DISAS_IAQ_N_STALE; | |
2443 | } | |
2444 | return nullify_end(ctx); | |
2445 | #endif | |
2446 | } | |
2447 | ||
2448 | /* | |
2449 | * Implement the pcxl and pcxl2 Fast TLB Insert instructions. | |
2450 | * See | |
2451 | * https://parisc.wiki.kernel.org/images-parisc/a/a9/Pcxl2_ers.pdf | |
2452 | * page 13-9 (195/206) | |
2453 | */ | |
2454 | static bool trans_ixtlbxf(DisasContext *ctx, arg_ixtlbxf *a) | |
2455 | { | |
2456 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); | |
2457 | #ifndef CONFIG_USER_ONLY | |
2458 | TCGv_tl addr, atl, stl; | |
2459 | TCGv_reg reg; | |
2460 | ||
2461 | nullify_over(ctx); | |
2462 | ||
2463 | /* | |
2464 | * FIXME: | |
2465 | * if (not (pcxl or pcxl2)) | |
2466 | * return gen_illegal(ctx); | |
2467 | * | |
2468 | * Note for future: these are 32-bit systems; no hppa64. | |
2469 | */ | |
2470 | ||
2471 | atl = tcg_temp_new_tl(); | |
2472 | stl = tcg_temp_new_tl(); | |
2473 | addr = tcg_temp_new_tl(); | |
2474 | ||
2475 | tcg_gen_ld32u_i64(stl, cpu_env, | |
2476 | a->data ? offsetof(CPUHPPAState, cr[CR_ISR]) | |
2477 | : offsetof(CPUHPPAState, cr[CR_IIASQ])); | |
2478 | tcg_gen_ld32u_i64(atl, cpu_env, | |
2479 | a->data ? offsetof(CPUHPPAState, cr[CR_IOR]) | |
2480 | : offsetof(CPUHPPAState, cr[CR_IIAOQ])); | |
2481 | tcg_gen_shli_i64(stl, stl, 32); | |
2482 | tcg_gen_or_tl(addr, atl, stl); | |
6797c315 NH |
2483 | |
2484 | reg = load_gpr(ctx, a->r); | |
2485 | if (a->addr) { | |
2486 | gen_helper_itlba(cpu_env, addr, reg); | |
2487 | } else { | |
2488 | gen_helper_itlbp(cpu_env, addr, reg); | |
2489 | } | |
6797c315 NH |
2490 | |
2491 | /* Exit TB for TLB change if mmu is enabled. */ | |
32dc7569 | 2492 | if (ctx->tb_flags & PSW_C) { |
31234768 RH |
2493 | ctx->base.is_jmp = DISAS_IAQ_N_STALE; |
2494 | } | |
2495 | return nullify_end(ctx); | |
deee69a1 | 2496 | #endif |
63300a00 | 2497 | } |
2dfcca9f | 2498 | |
deee69a1 | 2499 | static bool trans_lpa(DisasContext *ctx, arg_ldst *a) |
2dfcca9f | 2500 | { |
deee69a1 RH |
2501 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); |
2502 | #ifndef CONFIG_USER_ONLY | |
2dfcca9f RH |
2503 | TCGv_tl vaddr; |
2504 | TCGv_reg ofs, paddr; | |
2505 | ||
2dfcca9f RH |
2506 | nullify_over(ctx); |
2507 | ||
deee69a1 | 2508 | form_gva(ctx, &vaddr, &ofs, a->b, a->x, 0, 0, a->sp, a->m, false); |
2dfcca9f RH |
2509 | |
2510 | paddr = tcg_temp_new(); | |
2511 | gen_helper_lpa(paddr, cpu_env, vaddr); | |
2512 | ||
2513 | /* Note that physical address result overrides base modification. */ | |
deee69a1 RH |
2514 | if (a->m) { |
2515 | save_gpr(ctx, a->b, ofs); | |
2dfcca9f | 2516 | } |
deee69a1 | 2517 | save_gpr(ctx, a->t, paddr); |
2dfcca9f | 2518 | |
31234768 | 2519 | return nullify_end(ctx); |
deee69a1 | 2520 | #endif |
2dfcca9f | 2521 | } |
43a97b81 | 2522 | |
deee69a1 | 2523 | static bool trans_lci(DisasContext *ctx, arg_lci *a) |
43a97b81 | 2524 | { |
43a97b81 RH |
2525 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); |
2526 | ||
2527 | /* The Coherence Index is an implementation-defined function of the | |
2528 | physical address. Two addresses with the same CI have a coherent | |
2529 | view of the cache. Our implementation is to return 0 for all, | |
2530 | since the entire address space is coherent. */ | |
29dd6f64 | 2531 | save_gpr(ctx, a->t, tcg_constant_reg(0)); |
43a97b81 | 2532 | |
31234768 RH |
2533 | cond_free(&ctx->null_cond); |
2534 | return true; | |
43a97b81 | 2535 | } |
98a9cb79 | 2536 | |
0c982a28 | 2537 | static bool trans_add(DisasContext *ctx, arg_rrr_cf_sh *a) |
b2167459 | 2538 | { |
0c982a28 RH |
2539 | return do_add_reg(ctx, a, false, false, false, false); |
2540 | } | |
b2167459 | 2541 | |
0c982a28 RH |
2542 | static bool trans_add_l(DisasContext *ctx, arg_rrr_cf_sh *a) |
2543 | { | |
2544 | return do_add_reg(ctx, a, true, false, false, false); | |
2545 | } | |
b2167459 | 2546 | |
0c982a28 RH |
2547 | static bool trans_add_tsv(DisasContext *ctx, arg_rrr_cf_sh *a) |
2548 | { | |
2549 | return do_add_reg(ctx, a, false, true, false, false); | |
b2167459 RH |
2550 | } |
2551 | ||
0c982a28 | 2552 | static bool trans_add_c(DisasContext *ctx, arg_rrr_cf_sh *a) |
b2167459 | 2553 | { |
0c982a28 RH |
2554 | return do_add_reg(ctx, a, false, false, false, true); |
2555 | } | |
b2167459 | 2556 | |
0c982a28 RH |
2557 | static bool trans_add_c_tsv(DisasContext *ctx, arg_rrr_cf_sh *a) |
2558 | { | |
2559 | return do_add_reg(ctx, a, false, true, false, true); | |
2560 | } | |
b2167459 | 2561 | |
0c982a28 RH |
2562 | static bool trans_sub(DisasContext *ctx, arg_rrr_cf *a) |
2563 | { | |
2564 | return do_sub_reg(ctx, a, false, false, false); | |
b2167459 RH |
2565 | } |
2566 | ||
0c982a28 | 2567 | static bool trans_sub_tsv(DisasContext *ctx, arg_rrr_cf *a) |
b2167459 | 2568 | { |
0c982a28 RH |
2569 | return do_sub_reg(ctx, a, true, false, false); |
2570 | } | |
b2167459 | 2571 | |
0c982a28 RH |
2572 | static bool trans_sub_tc(DisasContext *ctx, arg_rrr_cf *a) |
2573 | { | |
2574 | return do_sub_reg(ctx, a, false, false, true); | |
b2167459 RH |
2575 | } |
2576 | ||
0c982a28 | 2577 | static bool trans_sub_tsv_tc(DisasContext *ctx, arg_rrr_cf *a) |
b2167459 | 2578 | { |
0c982a28 RH |
2579 | return do_sub_reg(ctx, a, true, false, true); |
2580 | } | |
2581 | ||
2582 | static bool trans_sub_b(DisasContext *ctx, arg_rrr_cf *a) | |
2583 | { | |
2584 | return do_sub_reg(ctx, a, false, true, false); | |
2585 | } | |
2586 | ||
2587 | static bool trans_sub_b_tsv(DisasContext *ctx, arg_rrr_cf *a) | |
2588 | { | |
2589 | return do_sub_reg(ctx, a, true, true, false); | |
2590 | } | |
2591 | ||
2592 | static bool trans_andcm(DisasContext *ctx, arg_rrr_cf *a) | |
2593 | { | |
2594 | return do_log_reg(ctx, a, tcg_gen_andc_reg); | |
2595 | } | |
2596 | ||
2597 | static bool trans_and(DisasContext *ctx, arg_rrr_cf *a) | |
2598 | { | |
2599 | return do_log_reg(ctx, a, tcg_gen_and_reg); | |
2600 | } | |
2601 | ||
2602 | static bool trans_or(DisasContext *ctx, arg_rrr_cf *a) | |
2603 | { | |
2604 | if (a->cf == 0) { | |
2605 | unsigned r2 = a->r2; | |
2606 | unsigned r1 = a->r1; | |
2607 | unsigned rt = a->t; | |
b2167459 | 2608 | |
7aee8189 RH |
2609 | if (rt == 0) { /* NOP */ |
2610 | cond_free(&ctx->null_cond); | |
2611 | return true; | |
2612 | } | |
2613 | if (r2 == 0) { /* COPY */ | |
2614 | if (r1 == 0) { | |
2615 | TCGv_reg dest = dest_gpr(ctx, rt); | |
2616 | tcg_gen_movi_reg(dest, 0); | |
2617 | save_gpr(ctx, rt, dest); | |
2618 | } else { | |
2619 | save_gpr(ctx, rt, cpu_gr[r1]); | |
2620 | } | |
2621 | cond_free(&ctx->null_cond); | |
2622 | return true; | |
2623 | } | |
2624 | #ifndef CONFIG_USER_ONLY | |
2625 | /* These are QEMU extensions and are nops in the real architecture: | |
2626 | * | |
2627 | * or %r10,%r10,%r10 -- idle loop; wait for interrupt | |
2628 | * or %r31,%r31,%r31 -- death loop; offline cpu | |
2629 | * currently implemented as idle. | |
2630 | */ | |
2631 | if ((rt == 10 || rt == 31) && r1 == rt && r2 == rt) { /* PAUSE */ | |
7aee8189 RH |
2632 | /* No need to check for supervisor, as userland can only pause |
2633 | until the next timer interrupt. */ | |
2634 | nullify_over(ctx); | |
2635 | ||
2636 | /* Advance the instruction queue. */ | |
2637 | copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); | |
2638 | copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var); | |
2639 | nullify_set(ctx, 0); | |
2640 | ||
2641 | /* Tell the qemu main loop to halt until this cpu has work. */ | |
29dd6f64 RH |
2642 | tcg_gen_st_i32(tcg_constant_i32(1), cpu_env, |
2643 | offsetof(CPUState, halted) - offsetof(HPPACPU, env)); | |
7aee8189 RH |
2644 | gen_excp_1(EXCP_HALTED); |
2645 | ctx->base.is_jmp = DISAS_NORETURN; | |
2646 | ||
2647 | return nullify_end(ctx); | |
2648 | } | |
2649 | #endif | |
b2167459 | 2650 | } |
0c982a28 RH |
2651 | return do_log_reg(ctx, a, tcg_gen_or_reg); |
2652 | } | |
7aee8189 | 2653 | |
0c982a28 RH |
2654 | static bool trans_xor(DisasContext *ctx, arg_rrr_cf *a) |
2655 | { | |
2656 | return do_log_reg(ctx, a, tcg_gen_xor_reg); | |
b2167459 RH |
2657 | } |
2658 | ||
0c982a28 | 2659 | static bool trans_cmpclr(DisasContext *ctx, arg_rrr_cf *a) |
b2167459 | 2660 | { |
eaa3783b | 2661 | TCGv_reg tcg_r1, tcg_r2; |
b2167459 | 2662 | |
0c982a28 | 2663 | if (a->cf) { |
b2167459 RH |
2664 | nullify_over(ctx); |
2665 | } | |
0c982a28 RH |
2666 | tcg_r1 = load_gpr(ctx, a->r1); |
2667 | tcg_r2 = load_gpr(ctx, a->r2); | |
2668 | do_cmpclr(ctx, a->t, tcg_r1, tcg_r2, a->cf); | |
31234768 | 2669 | return nullify_end(ctx); |
b2167459 RH |
2670 | } |
2671 | ||
0c982a28 | 2672 | static bool trans_uxor(DisasContext *ctx, arg_rrr_cf *a) |
b2167459 | 2673 | { |
eaa3783b | 2674 | TCGv_reg tcg_r1, tcg_r2; |
b2167459 | 2675 | |
0c982a28 | 2676 | if (a->cf) { |
b2167459 RH |
2677 | nullify_over(ctx); |
2678 | } | |
0c982a28 RH |
2679 | tcg_r1 = load_gpr(ctx, a->r1); |
2680 | tcg_r2 = load_gpr(ctx, a->r2); | |
2681 | do_unit(ctx, a->t, tcg_r1, tcg_r2, a->cf, false, tcg_gen_xor_reg); | |
31234768 | 2682 | return nullify_end(ctx); |
b2167459 RH |
2683 | } |
2684 | ||
0c982a28 | 2685 | static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf *a, bool is_tc) |
b2167459 | 2686 | { |
eaa3783b | 2687 | TCGv_reg tcg_r1, tcg_r2, tmp; |
b2167459 | 2688 | |
0c982a28 | 2689 | if (a->cf) { |
b2167459 RH |
2690 | nullify_over(ctx); |
2691 | } | |
0c982a28 RH |
2692 | tcg_r1 = load_gpr(ctx, a->r1); |
2693 | tcg_r2 = load_gpr(ctx, a->r2); | |
b2167459 | 2694 | tmp = get_temp(ctx); |
eaa3783b | 2695 | tcg_gen_not_reg(tmp, tcg_r2); |
0c982a28 | 2696 | do_unit(ctx, a->t, tcg_r1, tmp, a->cf, is_tc, tcg_gen_add_reg); |
31234768 | 2697 | return nullify_end(ctx); |
b2167459 RH |
2698 | } |
2699 | ||
0c982a28 RH |
2700 | static bool trans_uaddcm(DisasContext *ctx, arg_rrr_cf *a) |
2701 | { | |
2702 | return do_uaddcm(ctx, a, false); | |
2703 | } | |
2704 | ||
2705 | static bool trans_uaddcm_tc(DisasContext *ctx, arg_rrr_cf *a) | |
2706 | { | |
2707 | return do_uaddcm(ctx, a, true); | |
2708 | } | |
2709 | ||
2710 | static bool do_dcor(DisasContext *ctx, arg_rr_cf *a, bool is_i) | |
b2167459 | 2711 | { |
eaa3783b | 2712 | TCGv_reg tmp; |
b2167459 RH |
2713 | |
2714 | nullify_over(ctx); | |
2715 | ||
2716 | tmp = get_temp(ctx); | |
eaa3783b | 2717 | tcg_gen_shri_reg(tmp, cpu_psw_cb, 3); |
b2167459 | 2718 | if (!is_i) { |
eaa3783b | 2719 | tcg_gen_not_reg(tmp, tmp); |
b2167459 | 2720 | } |
eaa3783b RH |
2721 | tcg_gen_andi_reg(tmp, tmp, 0x11111111); |
2722 | tcg_gen_muli_reg(tmp, tmp, 6); | |
60e29463 | 2723 | do_unit(ctx, a->t, load_gpr(ctx, a->r), tmp, a->cf, false, |
31234768 | 2724 | is_i ? tcg_gen_add_reg : tcg_gen_sub_reg); |
31234768 | 2725 | return nullify_end(ctx); |
b2167459 RH |
2726 | } |
2727 | ||
0c982a28 RH |
2728 | static bool trans_dcor(DisasContext *ctx, arg_rr_cf *a) |
2729 | { | |
2730 | return do_dcor(ctx, a, false); | |
2731 | } | |
2732 | ||
2733 | static bool trans_dcor_i(DisasContext *ctx, arg_rr_cf *a) | |
2734 | { | |
2735 | return do_dcor(ctx, a, true); | |
2736 | } | |
2737 | ||
2738 | static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a) | |
b2167459 | 2739 | { |
eaa3783b | 2740 | TCGv_reg dest, add1, add2, addc, zero, in1, in2; |
b2167459 RH |
2741 | |
2742 | nullify_over(ctx); | |
2743 | ||
0c982a28 RH |
2744 | in1 = load_gpr(ctx, a->r1); |
2745 | in2 = load_gpr(ctx, a->r2); | |
b2167459 RH |
2746 | |
2747 | add1 = tcg_temp_new(); | |
2748 | add2 = tcg_temp_new(); | |
2749 | addc = tcg_temp_new(); | |
2750 | dest = tcg_temp_new(); | |
29dd6f64 | 2751 | zero = tcg_constant_reg(0); |
b2167459 RH |
2752 | |
2753 | /* Form R1 << 1 | PSW[CB]{8}. */ | |
eaa3783b RH |
2754 | tcg_gen_add_reg(add1, in1, in1); |
2755 | tcg_gen_add_reg(add1, add1, cpu_psw_cb_msb); | |
b2167459 RH |
2756 | |
2757 | /* Add or subtract R2, depending on PSW[V]. Proper computation of | |
2758 | carry{8} requires that we subtract via + ~R2 + 1, as described in | |
2759 | the manual. By extracting and masking V, we can produce the | |
2760 | proper inputs to the addition without movcond. */ | |
eaa3783b RH |
2761 | tcg_gen_sari_reg(addc, cpu_psw_v, TARGET_REGISTER_BITS - 1); |
2762 | tcg_gen_xor_reg(add2, in2, addc); | |
2763 | tcg_gen_andi_reg(addc, addc, 1); | |
b2167459 RH |
2764 | /* ??? This is only correct for 32-bit. */ |
2765 | tcg_gen_add2_i32(dest, cpu_psw_cb_msb, add1, zero, add2, zero); | |
2766 | tcg_gen_add2_i32(dest, cpu_psw_cb_msb, dest, cpu_psw_cb_msb, addc, zero); | |
2767 | ||
b2167459 | 2768 | /* Write back the result register. */ |
0c982a28 | 2769 | save_gpr(ctx, a->t, dest); |
b2167459 RH |
2770 | |
2771 | /* Write back PSW[CB]. */ | |
eaa3783b RH |
2772 | tcg_gen_xor_reg(cpu_psw_cb, add1, add2); |
2773 | tcg_gen_xor_reg(cpu_psw_cb, cpu_psw_cb, dest); | |
b2167459 RH |
2774 | |
2775 | /* Write back PSW[V] for the division step. */ | |
eaa3783b RH |
2776 | tcg_gen_neg_reg(cpu_psw_v, cpu_psw_cb_msb); |
2777 | tcg_gen_xor_reg(cpu_psw_v, cpu_psw_v, in2); | |
b2167459 RH |
2778 | |
2779 | /* Install the new nullification. */ | |
0c982a28 | 2780 | if (a->cf) { |
eaa3783b | 2781 | TCGv_reg sv = NULL; |
b47a4a02 | 2782 | if (cond_need_sv(a->cf >> 1)) { |
b2167459 RH |
2783 | /* ??? The lshift is supposed to contribute to overflow. */ |
2784 | sv = do_add_sv(ctx, dest, add1, add2); | |
2785 | } | |
0c982a28 | 2786 | ctx->null_cond = do_cond(a->cf, dest, cpu_psw_cb_msb, sv); |
b2167459 RH |
2787 | } |
2788 | ||
31234768 | 2789 | return nullify_end(ctx); |
b2167459 RH |
2790 | } |
2791 | ||
0588e061 | 2792 | static bool trans_addi(DisasContext *ctx, arg_rri_cf *a) |
b2167459 | 2793 | { |
0588e061 RH |
2794 | return do_add_imm(ctx, a, false, false); |
2795 | } | |
b2167459 | 2796 | |
0588e061 RH |
2797 | static bool trans_addi_tsv(DisasContext *ctx, arg_rri_cf *a) |
2798 | { | |
2799 | return do_add_imm(ctx, a, true, false); | |
b2167459 RH |
2800 | } |
2801 | ||
0588e061 | 2802 | static bool trans_addi_tc(DisasContext *ctx, arg_rri_cf *a) |
b2167459 | 2803 | { |
0588e061 RH |
2804 | return do_add_imm(ctx, a, false, true); |
2805 | } | |
b2167459 | 2806 | |
0588e061 RH |
2807 | static bool trans_addi_tc_tsv(DisasContext *ctx, arg_rri_cf *a) |
2808 | { | |
2809 | return do_add_imm(ctx, a, true, true); | |
2810 | } | |
b2167459 | 2811 | |
0588e061 RH |
2812 | static bool trans_subi(DisasContext *ctx, arg_rri_cf *a) |
2813 | { | |
2814 | return do_sub_imm(ctx, a, false); | |
2815 | } | |
b2167459 | 2816 | |
0588e061 RH |
2817 | static bool trans_subi_tsv(DisasContext *ctx, arg_rri_cf *a) |
2818 | { | |
2819 | return do_sub_imm(ctx, a, true); | |
b2167459 RH |
2820 | } |
2821 | ||
0588e061 | 2822 | static bool trans_cmpiclr(DisasContext *ctx, arg_rri_cf *a) |
b2167459 | 2823 | { |
eaa3783b | 2824 | TCGv_reg tcg_im, tcg_r2; |
b2167459 | 2825 | |
0588e061 | 2826 | if (a->cf) { |
b2167459 RH |
2827 | nullify_over(ctx); |
2828 | } | |
2829 | ||
0588e061 RH |
2830 | tcg_im = load_const(ctx, a->i); |
2831 | tcg_r2 = load_gpr(ctx, a->r); | |
2832 | do_cmpclr(ctx, a->t, tcg_im, tcg_r2, a->cf); | |
b2167459 | 2833 | |
31234768 | 2834 | return nullify_end(ctx); |
b2167459 RH |
2835 | } |
2836 | ||
1cd012a5 | 2837 | static bool trans_ld(DisasContext *ctx, arg_ldst *a) |
96d6407f | 2838 | { |
0786a3b6 HD |
2839 | if (unlikely(TARGET_REGISTER_BITS == 32 && a->size > MO_32)) { |
2840 | return gen_illegal(ctx); | |
2841 | } else { | |
2842 | return do_load(ctx, a->t, a->b, a->x, a->scale ? a->size : 0, | |
1cd012a5 | 2843 | a->disp, a->sp, a->m, a->size | MO_TE); |
0786a3b6 | 2844 | } |
96d6407f RH |
2845 | } |
2846 | ||
1cd012a5 | 2847 | static bool trans_st(DisasContext *ctx, arg_ldst *a) |
96d6407f | 2848 | { |
1cd012a5 | 2849 | assert(a->x == 0 && a->scale == 0); |
0786a3b6 HD |
2850 | if (unlikely(TARGET_REGISTER_BITS == 32 && a->size > MO_32)) { |
2851 | return gen_illegal(ctx); | |
2852 | } else { | |
2853 | return do_store(ctx, a->t, a->b, a->disp, a->sp, a->m, a->size | MO_TE); | |
2854 | } | |
96d6407f RH |
2855 | } |
2856 | ||
1cd012a5 | 2857 | static bool trans_ldc(DisasContext *ctx, arg_ldst *a) |
96d6407f | 2858 | { |
b1af755c | 2859 | MemOp mop = MO_TE | MO_ALIGN | a->size; |
86f8d05f RH |
2860 | TCGv_reg zero, dest, ofs; |
2861 | TCGv_tl addr; | |
96d6407f RH |
2862 | |
2863 | nullify_over(ctx); | |
2864 | ||
1cd012a5 | 2865 | if (a->m) { |
86f8d05f RH |
2866 | /* Base register modification. Make sure if RT == RB, |
2867 | we see the result of the load. */ | |
96d6407f RH |
2868 | dest = get_temp(ctx); |
2869 | } else { | |
1cd012a5 | 2870 | dest = dest_gpr(ctx, a->t); |
96d6407f RH |
2871 | } |
2872 | ||
1cd012a5 RH |
2873 | form_gva(ctx, &addr, &ofs, a->b, a->x, a->scale ? a->size : 0, |
2874 | a->disp, a->sp, a->m, ctx->mmu_idx == MMU_PHYS_IDX); | |
b1af755c RH |
2875 | |
2876 | /* | |
2877 | * For hppa1.1, LDCW is undefined unless aligned mod 16. | |
2878 | * However actual hardware succeeds with aligned mod 4. | |
2879 | * Detect this case and log a GUEST_ERROR. | |
2880 | * | |
2881 | * TODO: HPPA64 relaxes the over-alignment requirement | |
2882 | * with the ,co completer. | |
2883 | */ | |
2884 | gen_helper_ldc_check(addr); | |
2885 | ||
29dd6f64 | 2886 | zero = tcg_constant_reg(0); |
86f8d05f | 2887 | tcg_gen_atomic_xchg_reg(dest, addr, zero, ctx->mmu_idx, mop); |
b1af755c | 2888 | |
1cd012a5 RH |
2889 | if (a->m) { |
2890 | save_gpr(ctx, a->b, ofs); | |
96d6407f | 2891 | } |
1cd012a5 | 2892 | save_gpr(ctx, a->t, dest); |
96d6407f | 2893 | |
31234768 | 2894 | return nullify_end(ctx); |
96d6407f RH |
2895 | } |
2896 | ||
1cd012a5 | 2897 | static bool trans_stby(DisasContext *ctx, arg_stby *a) |
96d6407f | 2898 | { |
86f8d05f RH |
2899 | TCGv_reg ofs, val; |
2900 | TCGv_tl addr; | |
96d6407f RH |
2901 | |
2902 | nullify_over(ctx); | |
2903 | ||
1cd012a5 | 2904 | form_gva(ctx, &addr, &ofs, a->b, 0, 0, a->disp, a->sp, a->m, |
86f8d05f | 2905 | ctx->mmu_idx == MMU_PHYS_IDX); |
1cd012a5 RH |
2906 | val = load_gpr(ctx, a->r); |
2907 | if (a->a) { | |
f9f46db4 EC |
2908 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { |
2909 | gen_helper_stby_e_parallel(cpu_env, addr, val); | |
2910 | } else { | |
2911 | gen_helper_stby_e(cpu_env, addr, val); | |
2912 | } | |
96d6407f | 2913 | } else { |
f9f46db4 EC |
2914 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { |
2915 | gen_helper_stby_b_parallel(cpu_env, addr, val); | |
2916 | } else { | |
2917 | gen_helper_stby_b(cpu_env, addr, val); | |
2918 | } | |
96d6407f | 2919 | } |
1cd012a5 | 2920 | if (a->m) { |
86f8d05f | 2921 | tcg_gen_andi_reg(ofs, ofs, ~3); |
1cd012a5 | 2922 | save_gpr(ctx, a->b, ofs); |
96d6407f | 2923 | } |
96d6407f | 2924 | |
31234768 | 2925 | return nullify_end(ctx); |
96d6407f RH |
2926 | } |
2927 | ||
1cd012a5 | 2928 | static bool trans_lda(DisasContext *ctx, arg_ldst *a) |
d0a851cc RH |
2929 | { |
2930 | int hold_mmu_idx = ctx->mmu_idx; | |
d0a851cc RH |
2931 | |
2932 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); | |
d0a851cc | 2933 | ctx->mmu_idx = MMU_PHYS_IDX; |
1cd012a5 | 2934 | trans_ld(ctx, a); |
d0a851cc | 2935 | ctx->mmu_idx = hold_mmu_idx; |
31234768 | 2936 | return true; |
d0a851cc RH |
2937 | } |
2938 | ||
1cd012a5 | 2939 | static bool trans_sta(DisasContext *ctx, arg_ldst *a) |
d0a851cc RH |
2940 | { |
2941 | int hold_mmu_idx = ctx->mmu_idx; | |
d0a851cc RH |
2942 | |
2943 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); | |
d0a851cc | 2944 | ctx->mmu_idx = MMU_PHYS_IDX; |
1cd012a5 | 2945 | trans_st(ctx, a); |
d0a851cc | 2946 | ctx->mmu_idx = hold_mmu_idx; |
31234768 | 2947 | return true; |
d0a851cc | 2948 | } |
95412a61 | 2949 | |
0588e061 | 2950 | static bool trans_ldil(DisasContext *ctx, arg_ldil *a) |
b2167459 | 2951 | { |
0588e061 | 2952 | TCGv_reg tcg_rt = dest_gpr(ctx, a->t); |
b2167459 | 2953 | |
0588e061 RH |
2954 | tcg_gen_movi_reg(tcg_rt, a->i); |
2955 | save_gpr(ctx, a->t, tcg_rt); | |
b2167459 | 2956 | cond_free(&ctx->null_cond); |
31234768 | 2957 | return true; |
b2167459 RH |
2958 | } |
2959 | ||
0588e061 | 2960 | static bool trans_addil(DisasContext *ctx, arg_addil *a) |
b2167459 | 2961 | { |
0588e061 | 2962 | TCGv_reg tcg_rt = load_gpr(ctx, a->r); |
eaa3783b | 2963 | TCGv_reg tcg_r1 = dest_gpr(ctx, 1); |
b2167459 | 2964 | |
0588e061 | 2965 | tcg_gen_addi_reg(tcg_r1, tcg_rt, a->i); |
b2167459 RH |
2966 | save_gpr(ctx, 1, tcg_r1); |
2967 | cond_free(&ctx->null_cond); | |
31234768 | 2968 | return true; |
b2167459 RH |
2969 | } |
2970 | ||
0588e061 | 2971 | static bool trans_ldo(DisasContext *ctx, arg_ldo *a) |
b2167459 | 2972 | { |
0588e061 | 2973 | TCGv_reg tcg_rt = dest_gpr(ctx, a->t); |
b2167459 RH |
2974 | |
2975 | /* Special case rb == 0, for the LDI pseudo-op. | |
2976 | The COPY pseudo-op is handled for free within tcg_gen_addi_tl. */ | |
0588e061 RH |
2977 | if (a->b == 0) { |
2978 | tcg_gen_movi_reg(tcg_rt, a->i); | |
b2167459 | 2979 | } else { |
0588e061 | 2980 | tcg_gen_addi_reg(tcg_rt, cpu_gr[a->b], a->i); |
b2167459 | 2981 | } |
0588e061 | 2982 | save_gpr(ctx, a->t, tcg_rt); |
b2167459 | 2983 | cond_free(&ctx->null_cond); |
31234768 | 2984 | return true; |
b2167459 RH |
2985 | } |
2986 | ||
01afb7be RH |
2987 | static bool do_cmpb(DisasContext *ctx, unsigned r, TCGv_reg in1, |
2988 | unsigned c, unsigned f, unsigned n, int disp) | |
98cd9ca7 | 2989 | { |
01afb7be | 2990 | TCGv_reg dest, in2, sv; |
98cd9ca7 RH |
2991 | DisasCond cond; |
2992 | ||
98cd9ca7 RH |
2993 | in2 = load_gpr(ctx, r); |
2994 | dest = get_temp(ctx); | |
2995 | ||
eaa3783b | 2996 | tcg_gen_sub_reg(dest, in1, in2); |
98cd9ca7 | 2997 | |
f764718d | 2998 | sv = NULL; |
b47a4a02 | 2999 | if (cond_need_sv(c)) { |
98cd9ca7 RH |
3000 | sv = do_sub_sv(ctx, dest, in1, in2); |
3001 | } | |
3002 | ||
01afb7be RH |
3003 | cond = do_sub_cond(c * 2 + f, dest, in1, in2, sv); |
3004 | return do_cbranch(ctx, disp, n, &cond); | |
98cd9ca7 RH |
3005 | } |
3006 | ||
01afb7be | 3007 | static bool trans_cmpb(DisasContext *ctx, arg_cmpb *a) |
98cd9ca7 | 3008 | { |
01afb7be RH |
3009 | nullify_over(ctx); |
3010 | return do_cmpb(ctx, a->r2, load_gpr(ctx, a->r1), a->c, a->f, a->n, a->disp); | |
3011 | } | |
98cd9ca7 | 3012 | |
01afb7be RH |
3013 | static bool trans_cmpbi(DisasContext *ctx, arg_cmpbi *a) |
3014 | { | |
98cd9ca7 | 3015 | nullify_over(ctx); |
01afb7be RH |
3016 | return do_cmpb(ctx, a->r, load_const(ctx, a->i), a->c, a->f, a->n, a->disp); |
3017 | } | |
3018 | ||
3019 | static bool do_addb(DisasContext *ctx, unsigned r, TCGv_reg in1, | |
3020 | unsigned c, unsigned f, unsigned n, int disp) | |
3021 | { | |
3022 | TCGv_reg dest, in2, sv, cb_msb; | |
3023 | DisasCond cond; | |
98cd9ca7 | 3024 | |
98cd9ca7 | 3025 | in2 = load_gpr(ctx, r); |
43675d20 | 3026 | dest = tcg_temp_new(); |
f764718d RH |
3027 | sv = NULL; |
3028 | cb_msb = NULL; | |
98cd9ca7 | 3029 | |
b47a4a02 | 3030 | if (cond_need_cb(c)) { |
98cd9ca7 | 3031 | cb_msb = get_temp(ctx); |
eaa3783b RH |
3032 | tcg_gen_movi_reg(cb_msb, 0); |
3033 | tcg_gen_add2_reg(dest, cb_msb, in1, cb_msb, in2, cb_msb); | |
b47a4a02 | 3034 | } else { |
eaa3783b | 3035 | tcg_gen_add_reg(dest, in1, in2); |
b47a4a02 SS |
3036 | } |
3037 | if (cond_need_sv(c)) { | |
98cd9ca7 | 3038 | sv = do_add_sv(ctx, dest, in1, in2); |
98cd9ca7 RH |
3039 | } |
3040 | ||
01afb7be | 3041 | cond = do_cond(c * 2 + f, dest, cb_msb, sv); |
43675d20 | 3042 | save_gpr(ctx, r, dest); |
01afb7be | 3043 | return do_cbranch(ctx, disp, n, &cond); |
98cd9ca7 RH |
3044 | } |
3045 | ||
01afb7be RH |
3046 | static bool trans_addb(DisasContext *ctx, arg_addb *a) |
3047 | { | |
3048 | nullify_over(ctx); | |
3049 | return do_addb(ctx, a->r2, load_gpr(ctx, a->r1), a->c, a->f, a->n, a->disp); | |
3050 | } | |
3051 | ||
3052 | static bool trans_addbi(DisasContext *ctx, arg_addbi *a) | |
3053 | { | |
3054 | nullify_over(ctx); | |
3055 | return do_addb(ctx, a->r, load_const(ctx, a->i), a->c, a->f, a->n, a->disp); | |
3056 | } | |
3057 | ||
3058 | static bool trans_bb_sar(DisasContext *ctx, arg_bb_sar *a) | |
98cd9ca7 | 3059 | { |
eaa3783b | 3060 | TCGv_reg tmp, tcg_r; |
98cd9ca7 RH |
3061 | DisasCond cond; |
3062 | ||
3063 | nullify_over(ctx); | |
3064 | ||
3065 | tmp = tcg_temp_new(); | |
01afb7be RH |
3066 | tcg_r = load_gpr(ctx, a->r); |
3067 | tcg_gen_shl_reg(tmp, tcg_r, cpu_sar); | |
98cd9ca7 | 3068 | |
01afb7be | 3069 | cond = cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp); |
01afb7be | 3070 | return do_cbranch(ctx, a->disp, a->n, &cond); |
98cd9ca7 RH |
3071 | } |
3072 | ||
01afb7be RH |
3073 | static bool trans_bb_imm(DisasContext *ctx, arg_bb_imm *a) |
3074 | { | |
3075 | TCGv_reg tmp, tcg_r; | |
3076 | DisasCond cond; | |
3077 | ||
3078 | nullify_over(ctx); | |
3079 | ||
3080 | tmp = tcg_temp_new(); | |
3081 | tcg_r = load_gpr(ctx, a->r); | |
3082 | tcg_gen_shli_reg(tmp, tcg_r, a->p); | |
3083 | ||
3084 | cond = cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp); | |
01afb7be RH |
3085 | return do_cbranch(ctx, a->disp, a->n, &cond); |
3086 | } | |
3087 | ||
3088 | static bool trans_movb(DisasContext *ctx, arg_movb *a) | |
98cd9ca7 | 3089 | { |
eaa3783b | 3090 | TCGv_reg dest; |
98cd9ca7 RH |
3091 | DisasCond cond; |
3092 | ||
3093 | nullify_over(ctx); | |
3094 | ||
01afb7be RH |
3095 | dest = dest_gpr(ctx, a->r2); |
3096 | if (a->r1 == 0) { | |
eaa3783b | 3097 | tcg_gen_movi_reg(dest, 0); |
98cd9ca7 | 3098 | } else { |
01afb7be | 3099 | tcg_gen_mov_reg(dest, cpu_gr[a->r1]); |
98cd9ca7 RH |
3100 | } |
3101 | ||
01afb7be RH |
3102 | cond = do_sed_cond(a->c, dest); |
3103 | return do_cbranch(ctx, a->disp, a->n, &cond); | |
3104 | } | |
3105 | ||
3106 | static bool trans_movbi(DisasContext *ctx, arg_movbi *a) | |
3107 | { | |
3108 | TCGv_reg dest; | |
3109 | DisasCond cond; | |
3110 | ||
3111 | nullify_over(ctx); | |
3112 | ||
3113 | dest = dest_gpr(ctx, a->r); | |
3114 | tcg_gen_movi_reg(dest, a->i); | |
3115 | ||
3116 | cond = do_sed_cond(a->c, dest); | |
3117 | return do_cbranch(ctx, a->disp, a->n, &cond); | |
98cd9ca7 RH |
3118 | } |
3119 | ||
30878590 | 3120 | static bool trans_shrpw_sar(DisasContext *ctx, arg_shrpw_sar *a) |
0b1347d2 | 3121 | { |
eaa3783b | 3122 | TCGv_reg dest; |
0b1347d2 | 3123 | |
30878590 | 3124 | if (a->c) { |
0b1347d2 RH |
3125 | nullify_over(ctx); |
3126 | } | |
3127 | ||
30878590 RH |
3128 | dest = dest_gpr(ctx, a->t); |
3129 | if (a->r1 == 0) { | |
3130 | tcg_gen_ext32u_reg(dest, load_gpr(ctx, a->r2)); | |
eaa3783b | 3131 | tcg_gen_shr_reg(dest, dest, cpu_sar); |
30878590 | 3132 | } else if (a->r1 == a->r2) { |
0b1347d2 | 3133 | TCGv_i32 t32 = tcg_temp_new_i32(); |
30878590 | 3134 | tcg_gen_trunc_reg_i32(t32, load_gpr(ctx, a->r2)); |
0b1347d2 | 3135 | tcg_gen_rotr_i32(t32, t32, cpu_sar); |
eaa3783b | 3136 | tcg_gen_extu_i32_reg(dest, t32); |
0b1347d2 RH |
3137 | } else { |
3138 | TCGv_i64 t = tcg_temp_new_i64(); | |
3139 | TCGv_i64 s = tcg_temp_new_i64(); | |
3140 | ||
30878590 | 3141 | tcg_gen_concat_reg_i64(t, load_gpr(ctx, a->r2), load_gpr(ctx, a->r1)); |
eaa3783b | 3142 | tcg_gen_extu_reg_i64(s, cpu_sar); |
0b1347d2 | 3143 | tcg_gen_shr_i64(t, t, s); |
eaa3783b | 3144 | tcg_gen_trunc_i64_reg(dest, t); |
0b1347d2 | 3145 | } |
30878590 | 3146 | save_gpr(ctx, a->t, dest); |
0b1347d2 RH |
3147 | |
3148 | /* Install the new nullification. */ | |
3149 | cond_free(&ctx->null_cond); | |
30878590 RH |
3150 | if (a->c) { |
3151 | ctx->null_cond = do_sed_cond(a->c, dest); | |
0b1347d2 | 3152 | } |
31234768 | 3153 | return nullify_end(ctx); |
0b1347d2 RH |
3154 | } |
3155 | ||
30878590 | 3156 | static bool trans_shrpw_imm(DisasContext *ctx, arg_shrpw_imm *a) |
0b1347d2 | 3157 | { |
30878590 | 3158 | unsigned sa = 31 - a->cpos; |
eaa3783b | 3159 | TCGv_reg dest, t2; |
0b1347d2 | 3160 | |
30878590 | 3161 | if (a->c) { |
0b1347d2 RH |
3162 | nullify_over(ctx); |
3163 | } | |
3164 | ||
30878590 RH |
3165 | dest = dest_gpr(ctx, a->t); |
3166 | t2 = load_gpr(ctx, a->r2); | |
05bfd4db RH |
3167 | if (a->r1 == 0) { |
3168 | tcg_gen_extract_reg(dest, t2, sa, 32 - sa); | |
3169 | } else if (TARGET_REGISTER_BITS == 32) { | |
3170 | tcg_gen_extract2_reg(dest, t2, cpu_gr[a->r1], sa); | |
3171 | } else if (a->r1 == a->r2) { | |
0b1347d2 | 3172 | TCGv_i32 t32 = tcg_temp_new_i32(); |
eaa3783b | 3173 | tcg_gen_trunc_reg_i32(t32, t2); |
0b1347d2 | 3174 | tcg_gen_rotri_i32(t32, t32, sa); |
eaa3783b | 3175 | tcg_gen_extu_i32_reg(dest, t32); |
0b1347d2 | 3176 | } else { |
05bfd4db RH |
3177 | TCGv_i64 t64 = tcg_temp_new_i64(); |
3178 | tcg_gen_concat_reg_i64(t64, t2, cpu_gr[a->r1]); | |
3179 | tcg_gen_shri_i64(t64, t64, sa); | |
3180 | tcg_gen_trunc_i64_reg(dest, t64); | |
0b1347d2 | 3181 | } |
30878590 | 3182 | save_gpr(ctx, a->t, dest); |
0b1347d2 RH |
3183 | |
3184 | /* Install the new nullification. */ | |
3185 | cond_free(&ctx->null_cond); | |
30878590 RH |
3186 | if (a->c) { |
3187 | ctx->null_cond = do_sed_cond(a->c, dest); | |
0b1347d2 | 3188 | } |
31234768 | 3189 | return nullify_end(ctx); |
0b1347d2 RH |
3190 | } |
3191 | ||
30878590 | 3192 | static bool trans_extrw_sar(DisasContext *ctx, arg_extrw_sar *a) |
0b1347d2 | 3193 | { |
30878590 | 3194 | unsigned len = 32 - a->clen; |
eaa3783b | 3195 | TCGv_reg dest, src, tmp; |
0b1347d2 | 3196 | |
30878590 | 3197 | if (a->c) { |
0b1347d2 RH |
3198 | nullify_over(ctx); |
3199 | } | |
3200 | ||
30878590 RH |
3201 | dest = dest_gpr(ctx, a->t); |
3202 | src = load_gpr(ctx, a->r); | |
0b1347d2 RH |
3203 | tmp = tcg_temp_new(); |
3204 | ||
3205 | /* Recall that SAR is using big-endian bit numbering. */ | |
eaa3783b | 3206 | tcg_gen_xori_reg(tmp, cpu_sar, TARGET_REGISTER_BITS - 1); |
30878590 | 3207 | if (a->se) { |
eaa3783b RH |
3208 | tcg_gen_sar_reg(dest, src, tmp); |
3209 | tcg_gen_sextract_reg(dest, dest, 0, len); | |
0b1347d2 | 3210 | } else { |
eaa3783b RH |
3211 | tcg_gen_shr_reg(dest, src, tmp); |
3212 | tcg_gen_extract_reg(dest, dest, 0, len); | |
0b1347d2 | 3213 | } |
30878590 | 3214 | save_gpr(ctx, a->t, dest); |
0b1347d2 RH |
3215 | |
3216 | /* Install the new nullification. */ | |
3217 | cond_free(&ctx->null_cond); | |
30878590 RH |
3218 | if (a->c) { |
3219 | ctx->null_cond = do_sed_cond(a->c, dest); | |
0b1347d2 | 3220 | } |
31234768 | 3221 | return nullify_end(ctx); |
0b1347d2 RH |
3222 | } |
3223 | ||
30878590 | 3224 | static bool trans_extrw_imm(DisasContext *ctx, arg_extrw_imm *a) |
0b1347d2 | 3225 | { |
30878590 RH |
3226 | unsigned len = 32 - a->clen; |
3227 | unsigned cpos = 31 - a->pos; | |
eaa3783b | 3228 | TCGv_reg dest, src; |
0b1347d2 | 3229 | |
30878590 | 3230 | if (a->c) { |
0b1347d2 RH |
3231 | nullify_over(ctx); |
3232 | } | |
3233 | ||
30878590 RH |
3234 | dest = dest_gpr(ctx, a->t); |
3235 | src = load_gpr(ctx, a->r); | |
3236 | if (a->se) { | |
eaa3783b | 3237 | tcg_gen_sextract_reg(dest, src, cpos, len); |
0b1347d2 | 3238 | } else { |
eaa3783b | 3239 | tcg_gen_extract_reg(dest, src, cpos, len); |
0b1347d2 | 3240 | } |
30878590 | 3241 | save_gpr(ctx, a->t, dest); |
0b1347d2 RH |
3242 | |
3243 | /* Install the new nullification. */ | |
3244 | cond_free(&ctx->null_cond); | |
30878590 RH |
3245 | if (a->c) { |
3246 | ctx->null_cond = do_sed_cond(a->c, dest); | |
0b1347d2 | 3247 | } |
31234768 | 3248 | return nullify_end(ctx); |
0b1347d2 RH |
3249 | } |
3250 | ||
30878590 | 3251 | static bool trans_depwi_imm(DisasContext *ctx, arg_depwi_imm *a) |
0b1347d2 | 3252 | { |
30878590 | 3253 | unsigned len = 32 - a->clen; |
eaa3783b RH |
3254 | target_sreg mask0, mask1; |
3255 | TCGv_reg dest; | |
0b1347d2 | 3256 | |
30878590 | 3257 | if (a->c) { |
0b1347d2 RH |
3258 | nullify_over(ctx); |
3259 | } | |
30878590 RH |
3260 | if (a->cpos + len > 32) { |
3261 | len = 32 - a->cpos; | |
0b1347d2 RH |
3262 | } |
3263 | ||
30878590 RH |
3264 | dest = dest_gpr(ctx, a->t); |
3265 | mask0 = deposit64(0, a->cpos, len, a->i); | |
3266 | mask1 = deposit64(-1, a->cpos, len, a->i); | |
0b1347d2 | 3267 | |
30878590 RH |
3268 | if (a->nz) { |
3269 | TCGv_reg src = load_gpr(ctx, a->t); | |
0b1347d2 | 3270 | if (mask1 != -1) { |
eaa3783b | 3271 | tcg_gen_andi_reg(dest, src, mask1); |
0b1347d2 RH |
3272 | src = dest; |
3273 | } | |
eaa3783b | 3274 | tcg_gen_ori_reg(dest, src, mask0); |
0b1347d2 | 3275 | } else { |
eaa3783b | 3276 | tcg_gen_movi_reg(dest, mask0); |
0b1347d2 | 3277 | } |
30878590 | 3278 | save_gpr(ctx, a->t, dest); |
0b1347d2 RH |
3279 | |
3280 | /* Install the new nullification. */ | |
3281 | cond_free(&ctx->null_cond); | |
30878590 RH |
3282 | if (a->c) { |
3283 | ctx->null_cond = do_sed_cond(a->c, dest); | |
0b1347d2 | 3284 | } |
31234768 | 3285 | return nullify_end(ctx); |
0b1347d2 RH |
3286 | } |
3287 | ||
30878590 | 3288 | static bool trans_depw_imm(DisasContext *ctx, arg_depw_imm *a) |
0b1347d2 | 3289 | { |
30878590 RH |
3290 | unsigned rs = a->nz ? a->t : 0; |
3291 | unsigned len = 32 - a->clen; | |
eaa3783b | 3292 | TCGv_reg dest, val; |
0b1347d2 | 3293 | |
30878590 | 3294 | if (a->c) { |
0b1347d2 RH |
3295 | nullify_over(ctx); |
3296 | } | |
30878590 RH |
3297 | if (a->cpos + len > 32) { |
3298 | len = 32 - a->cpos; | |
0b1347d2 RH |
3299 | } |
3300 | ||
30878590 RH |
3301 | dest = dest_gpr(ctx, a->t); |
3302 | val = load_gpr(ctx, a->r); | |
0b1347d2 | 3303 | if (rs == 0) { |
30878590 | 3304 | tcg_gen_deposit_z_reg(dest, val, a->cpos, len); |
0b1347d2 | 3305 | } else { |
30878590 | 3306 | tcg_gen_deposit_reg(dest, cpu_gr[rs], val, a->cpos, len); |
0b1347d2 | 3307 | } |
30878590 | 3308 | save_gpr(ctx, a->t, dest); |
0b1347d2 RH |
3309 | |
3310 | /* Install the new nullification. */ | |
3311 | cond_free(&ctx->null_cond); | |
30878590 RH |
3312 | if (a->c) { |
3313 | ctx->null_cond = do_sed_cond(a->c, dest); | |
0b1347d2 | 3314 | } |
31234768 | 3315 | return nullify_end(ctx); |
0b1347d2 RH |
3316 | } |
3317 | ||
30878590 RH |
3318 | static bool do_depw_sar(DisasContext *ctx, unsigned rt, unsigned c, |
3319 | unsigned nz, unsigned clen, TCGv_reg val) | |
0b1347d2 | 3320 | { |
0b1347d2 RH |
3321 | unsigned rs = nz ? rt : 0; |
3322 | unsigned len = 32 - clen; | |
30878590 | 3323 | TCGv_reg mask, tmp, shift, dest; |
0b1347d2 RH |
3324 | unsigned msb = 1U << (len - 1); |
3325 | ||
0b1347d2 RH |
3326 | dest = dest_gpr(ctx, rt); |
3327 | shift = tcg_temp_new(); | |
3328 | tmp = tcg_temp_new(); | |
3329 | ||
3330 | /* Convert big-endian bit numbering in SAR to left-shift. */ | |
eaa3783b | 3331 | tcg_gen_xori_reg(shift, cpu_sar, TARGET_REGISTER_BITS - 1); |
0b1347d2 | 3332 | |
0992a930 RH |
3333 | mask = tcg_temp_new(); |
3334 | tcg_gen_movi_reg(mask, msb + (msb - 1)); | |
eaa3783b | 3335 | tcg_gen_and_reg(tmp, val, mask); |
0b1347d2 | 3336 | if (rs) { |
eaa3783b RH |
3337 | tcg_gen_shl_reg(mask, mask, shift); |
3338 | tcg_gen_shl_reg(tmp, tmp, shift); | |
3339 | tcg_gen_andc_reg(dest, cpu_gr[rs], mask); | |
3340 | tcg_gen_or_reg(dest, dest, tmp); | |
0b1347d2 | 3341 | } else { |
eaa3783b | 3342 | tcg_gen_shl_reg(dest, tmp, shift); |
0b1347d2 | 3343 | } |
0b1347d2 RH |
3344 | save_gpr(ctx, rt, dest); |
3345 | ||
3346 | /* Install the new nullification. */ | |
3347 | cond_free(&ctx->null_cond); | |
3348 | if (c) { | |
3349 | ctx->null_cond = do_sed_cond(c, dest); | |
3350 | } | |
31234768 | 3351 | return nullify_end(ctx); |
0b1347d2 RH |
3352 | } |
3353 | ||
30878590 RH |
3354 | static bool trans_depw_sar(DisasContext *ctx, arg_depw_sar *a) |
3355 | { | |
a6deecce SS |
3356 | if (a->c) { |
3357 | nullify_over(ctx); | |
3358 | } | |
30878590 RH |
3359 | return do_depw_sar(ctx, a->t, a->c, a->nz, a->clen, load_gpr(ctx, a->r)); |
3360 | } | |
3361 | ||
3362 | static bool trans_depwi_sar(DisasContext *ctx, arg_depwi_sar *a) | |
3363 | { | |
a6deecce SS |
3364 | if (a->c) { |
3365 | nullify_over(ctx); | |
3366 | } | |
30878590 RH |
3367 | return do_depw_sar(ctx, a->t, a->c, a->nz, a->clen, load_const(ctx, a->i)); |
3368 | } | |
0b1347d2 | 3369 | |
8340f534 | 3370 | static bool trans_be(DisasContext *ctx, arg_be *a) |
98cd9ca7 | 3371 | { |
660eefe1 | 3372 | TCGv_reg tmp; |
98cd9ca7 | 3373 | |
c301f34e | 3374 | #ifdef CONFIG_USER_ONLY |
98cd9ca7 RH |
3375 | /* ??? It seems like there should be a good way of using |
3376 | "be disp(sr2, r0)", the canonical gateway entry mechanism | |
3377 | to our advantage. But that appears to be inconvenient to | |
3378 | manage along side branch delay slots. Therefore we handle | |
3379 | entry into the gateway page via absolute address. */ | |
98cd9ca7 RH |
3380 | /* Since we don't implement spaces, just branch. Do notice the special |
3381 | case of "be disp(*,r0)" using a direct branch to disp, so that we can | |
3382 | goto_tb to the TB containing the syscall. */ | |
8340f534 RH |
3383 | if (a->b == 0) { |
3384 | return do_dbranch(ctx, a->disp, a->l, a->n); | |
98cd9ca7 | 3385 | } |
c301f34e | 3386 | #else |
c301f34e | 3387 | nullify_over(ctx); |
660eefe1 RH |
3388 | #endif |
3389 | ||
3390 | tmp = get_temp(ctx); | |
8340f534 | 3391 | tcg_gen_addi_reg(tmp, load_gpr(ctx, a->b), a->disp); |
660eefe1 | 3392 | tmp = do_ibranch_priv(ctx, tmp); |
c301f34e RH |
3393 | |
3394 | #ifdef CONFIG_USER_ONLY | |
8340f534 | 3395 | return do_ibranch(ctx, tmp, a->l, a->n); |
c301f34e RH |
3396 | #else |
3397 | TCGv_i64 new_spc = tcg_temp_new_i64(); | |
3398 | ||
8340f534 RH |
3399 | load_spr(ctx, new_spc, a->sp); |
3400 | if (a->l) { | |
c301f34e RH |
3401 | copy_iaoq_entry(cpu_gr[31], ctx->iaoq_n, ctx->iaoq_n_var); |
3402 | tcg_gen_mov_i64(cpu_sr[0], cpu_iasq_f); | |
3403 | } | |
8340f534 | 3404 | if (a->n && use_nullify_skip(ctx)) { |
c301f34e RH |
3405 | tcg_gen_mov_reg(cpu_iaoq_f, tmp); |
3406 | tcg_gen_addi_reg(cpu_iaoq_b, cpu_iaoq_f, 4); | |
3407 | tcg_gen_mov_i64(cpu_iasq_f, new_spc); | |
3408 | tcg_gen_mov_i64(cpu_iasq_b, cpu_iasq_f); | |
3409 | } else { | |
3410 | copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); | |
3411 | if (ctx->iaoq_b == -1) { | |
3412 | tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); | |
3413 | } | |
3414 | tcg_gen_mov_reg(cpu_iaoq_b, tmp); | |
3415 | tcg_gen_mov_i64(cpu_iasq_b, new_spc); | |
8340f534 | 3416 | nullify_set(ctx, a->n); |
c301f34e | 3417 | } |
c301f34e | 3418 | tcg_gen_lookup_and_goto_ptr(); |
31234768 RH |
3419 | ctx->base.is_jmp = DISAS_NORETURN; |
3420 | return nullify_end(ctx); | |
c301f34e | 3421 | #endif |
98cd9ca7 RH |
3422 | } |
3423 | ||
8340f534 | 3424 | static bool trans_bl(DisasContext *ctx, arg_bl *a) |
98cd9ca7 | 3425 | { |
8340f534 | 3426 | return do_dbranch(ctx, iaoq_dest(ctx, a->disp), a->l, a->n); |
98cd9ca7 RH |
3427 | } |
3428 | ||
8340f534 | 3429 | static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) |
43e05652 | 3430 | { |
8340f534 | 3431 | target_ureg dest = iaoq_dest(ctx, a->disp); |
43e05652 | 3432 | |
6e5f5300 SS |
3433 | nullify_over(ctx); |
3434 | ||
43e05652 RH |
3435 | /* Make sure the caller hasn't done something weird with the queue. |
3436 | * ??? This is not quite the same as the PSW[B] bit, which would be | |
3437 | * expensive to track. Real hardware will trap for | |
3438 | * b gateway | |
3439 | * b gateway+4 (in delay slot of first branch) | |
3440 | * However, checking for a non-sequential instruction queue *will* | |
3441 | * diagnose the security hole | |
3442 | * b gateway | |
3443 | * b evil | |
3444 | * in which instructions at evil would run with increased privs. | |
3445 | */ | |
3446 | if (ctx->iaoq_b == -1 || ctx->iaoq_b != ctx->iaoq_f + 4) { | |
3447 | return gen_illegal(ctx); | |
3448 | } | |
3449 | ||
3450 | #ifndef CONFIG_USER_ONLY | |
3451 | if (ctx->tb_flags & PSW_C) { | |
3452 | CPUHPPAState *env = ctx->cs->env_ptr; | |
3453 | int type = hppa_artype_for_page(env, ctx->base.pc_next); | |
3454 | /* If we could not find a TLB entry, then we need to generate an | |
3455 | ITLB miss exception so the kernel will provide it. | |
3456 | The resulting TLB fill operation will invalidate this TB and | |
3457 | we will re-translate, at which point we *will* be able to find | |
3458 | the TLB entry and determine if this is in fact a gateway page. */ | |
3459 | if (type < 0) { | |
31234768 RH |
3460 | gen_excp(ctx, EXCP_ITLB_MISS); |
3461 | return true; | |
43e05652 RH |
3462 | } |
3463 | /* No change for non-gateway pages or for priv decrease. */ | |
3464 | if (type >= 4 && type - 4 < ctx->privilege) { | |
3465 | dest = deposit32(dest, 0, 2, type - 4); | |
3466 | } | |
3467 | } else { | |
3468 | dest &= -4; /* priv = 0 */ | |
3469 | } | |
3470 | #endif | |
3471 | ||
6e5f5300 SS |
3472 | if (a->l) { |
3473 | TCGv_reg tmp = dest_gpr(ctx, a->l); | |
3474 | if (ctx->privilege < 3) { | |
3475 | tcg_gen_andi_reg(tmp, tmp, -4); | |
3476 | } | |
3477 | tcg_gen_ori_reg(tmp, tmp, ctx->privilege); | |
3478 | save_gpr(ctx, a->l, tmp); | |
3479 | } | |
3480 | ||
3481 | return do_dbranch(ctx, dest, 0, a->n); | |
43e05652 RH |
3482 | } |
3483 | ||
8340f534 | 3484 | static bool trans_blr(DisasContext *ctx, arg_blr *a) |
98cd9ca7 | 3485 | { |
b35aec85 RH |
3486 | if (a->x) { |
3487 | TCGv_reg tmp = get_temp(ctx); | |
3488 | tcg_gen_shli_reg(tmp, load_gpr(ctx, a->x), 3); | |
3489 | tcg_gen_addi_reg(tmp, tmp, ctx->iaoq_f + 8); | |
3490 | /* The computation here never changes privilege level. */ | |
3491 | return do_ibranch(ctx, tmp, a->l, a->n); | |
3492 | } else { | |
3493 | /* BLR R0,RX is a good way to load PC+8 into RX. */ | |
3494 | return do_dbranch(ctx, ctx->iaoq_f + 8, a->l, a->n); | |
3495 | } | |
98cd9ca7 RH |
3496 | } |
3497 | ||
8340f534 | 3498 | static bool trans_bv(DisasContext *ctx, arg_bv *a) |
98cd9ca7 | 3499 | { |
eaa3783b | 3500 | TCGv_reg dest; |
98cd9ca7 | 3501 | |
8340f534 RH |
3502 | if (a->x == 0) { |
3503 | dest = load_gpr(ctx, a->b); | |
98cd9ca7 RH |
3504 | } else { |
3505 | dest = get_temp(ctx); | |
8340f534 RH |
3506 | tcg_gen_shli_reg(dest, load_gpr(ctx, a->x), 3); |
3507 | tcg_gen_add_reg(dest, dest, load_gpr(ctx, a->b)); | |
98cd9ca7 | 3508 | } |
660eefe1 | 3509 | dest = do_ibranch_priv(ctx, dest); |
8340f534 | 3510 | return do_ibranch(ctx, dest, 0, a->n); |
98cd9ca7 RH |
3511 | } |
3512 | ||
8340f534 | 3513 | static bool trans_bve(DisasContext *ctx, arg_bve *a) |
98cd9ca7 | 3514 | { |
660eefe1 | 3515 | TCGv_reg dest; |
98cd9ca7 | 3516 | |
c301f34e | 3517 | #ifdef CONFIG_USER_ONLY |
8340f534 RH |
3518 | dest = do_ibranch_priv(ctx, load_gpr(ctx, a->b)); |
3519 | return do_ibranch(ctx, dest, a->l, a->n); | |
c301f34e RH |
3520 | #else |
3521 | nullify_over(ctx); | |
8340f534 | 3522 | dest = do_ibranch_priv(ctx, load_gpr(ctx, a->b)); |
c301f34e RH |
3523 | |
3524 | copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); | |
3525 | if (ctx->iaoq_b == -1) { | |
3526 | tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); | |
3527 | } | |
3528 | copy_iaoq_entry(cpu_iaoq_b, -1, dest); | |
3529 | tcg_gen_mov_i64(cpu_iasq_b, space_select(ctx, 0, dest)); | |
8340f534 RH |
3530 | if (a->l) { |
3531 | copy_iaoq_entry(cpu_gr[a->l], ctx->iaoq_n, ctx->iaoq_n_var); | |
c301f34e | 3532 | } |
8340f534 | 3533 | nullify_set(ctx, a->n); |
c301f34e | 3534 | tcg_gen_lookup_and_goto_ptr(); |
31234768 RH |
3535 | ctx->base.is_jmp = DISAS_NORETURN; |
3536 | return nullify_end(ctx); | |
c301f34e | 3537 | #endif |
98cd9ca7 RH |
3538 | } |
3539 | ||
1ca74648 RH |
3540 | /* |
3541 | * Float class 0 | |
3542 | */ | |
ebe9383c | 3543 | |
1ca74648 | 3544 | static void gen_fcpy_f(TCGv_i32 dst, TCGv_env unused, TCGv_i32 src) |
ebe9383c | 3545 | { |
1ca74648 | 3546 | tcg_gen_mov_i32(dst, src); |
ebe9383c RH |
3547 | } |
3548 | ||
59f8c04b HD |
3549 | static bool trans_fid_f(DisasContext *ctx, arg_fid_f *a) |
3550 | { | |
a300dad3 RH |
3551 | uint64_t ret; |
3552 | ||
3553 | if (TARGET_REGISTER_BITS == 64) { | |
3554 | ret = 0x13080000000000ULL; /* PA8700 (PCX-W2) */ | |
3555 | } else { | |
3556 | ret = 0x0f080000000000ULL; /* PA7300LC (PCX-L2) */ | |
3557 | } | |
3558 | ||
59f8c04b | 3559 | nullify_over(ctx); |
a300dad3 | 3560 | save_frd(0, tcg_constant_i64(ret)); |
59f8c04b HD |
3561 | return nullify_end(ctx); |
3562 | } | |
3563 | ||
1ca74648 | 3564 | static bool trans_fcpy_f(DisasContext *ctx, arg_fclass01 *a) |
ebe9383c | 3565 | { |
1ca74648 | 3566 | return do_fop_wew(ctx, a->t, a->r, gen_fcpy_f); |
ebe9383c RH |
3567 | } |
3568 | ||
1ca74648 | 3569 | static void gen_fcpy_d(TCGv_i64 dst, TCGv_env unused, TCGv_i64 src) |
ebe9383c | 3570 | { |
1ca74648 | 3571 | tcg_gen_mov_i64(dst, src); |
ebe9383c RH |
3572 | } |
3573 | ||
1ca74648 | 3574 | static bool trans_fcpy_d(DisasContext *ctx, arg_fclass01 *a) |
ebe9383c | 3575 | { |
1ca74648 | 3576 | return do_fop_ded(ctx, a->t, a->r, gen_fcpy_d); |
ebe9383c RH |
3577 | } |
3578 | ||
1ca74648 | 3579 | static void gen_fabs_f(TCGv_i32 dst, TCGv_env unused, TCGv_i32 src) |
ebe9383c | 3580 | { |
1ca74648 | 3581 | tcg_gen_andi_i32(dst, src, INT32_MAX); |
ebe9383c RH |
3582 | } |
3583 | ||
1ca74648 | 3584 | static bool trans_fabs_f(DisasContext *ctx, arg_fclass01 *a) |
ebe9383c | 3585 | { |
1ca74648 | 3586 | return do_fop_wew(ctx, a->t, a->r, gen_fabs_f); |
ebe9383c RH |
3587 | } |
3588 | ||
1ca74648 | 3589 | static void gen_fabs_d(TCGv_i64 dst, TCGv_env unused, TCGv_i64 src) |
ebe9383c | 3590 | { |
1ca74648 | 3591 | tcg_gen_andi_i64(dst, src, INT64_MAX); |
ebe9383c RH |
3592 | } |
3593 | ||
1ca74648 | 3594 | static bool trans_fabs_d(DisasContext *ctx, arg_fclass01 *a) |
ebe9383c | 3595 | { |
1ca74648 | 3596 | return do_fop_ded(ctx, a->t, a->r, gen_fabs_d); |
ebe9383c RH |
3597 | } |
3598 | ||
1ca74648 | 3599 | static bool trans_fsqrt_f(DisasContext *ctx, arg_fclass01 *a) |
ebe9383c | 3600 | { |
1ca74648 | 3601 | return do_fop_wew(ctx, a->t, a->r, gen_helper_fsqrt_s); |
ebe9383c RH |
3602 | } |
3603 | ||
1ca74648 | 3604 | static bool trans_fsqrt_d(DisasContext *ctx, arg_fclass01 *a) |
ebe9383c | 3605 | { |
1ca74648 | 3606 | return do_fop_ded(ctx, a->t, a->r, gen_helper_fsqrt_d); |
ebe9383c RH |
3607 | } |
3608 | ||
1ca74648 | 3609 | static bool trans_frnd_f(DisasContext *ctx, arg_fclass01 *a) |
ebe9383c | 3610 | { |
1ca74648 | 3611 | return do_fop_wew(ctx, a->t, a->r, gen_helper_frnd_s); |
ebe9383c RH |
3612 | } |
3613 | ||
1ca74648 | 3614 | static bool trans_frnd_d(DisasContext *ctx, arg_fclass01 *a) |
ebe9383c | 3615 | { |
1ca74648 | 3616 | return do_fop_ded(ctx, a->t, a->r, gen_helper_frnd_d); |
ebe9383c RH |
3617 | } |
3618 | ||
1ca74648 | 3619 | static void gen_fneg_f(TCGv_i32 dst, TCGv_env unused, TCGv_i32 src) |
ebe9383c | 3620 | { |
1ca74648 | 3621 | tcg_gen_xori_i32(dst, src, INT32_MIN); |
ebe9383c RH |
3622 | } |
3623 | ||
1ca74648 | 3624 | static bool trans_fneg_f(DisasContext *ctx, arg_fclass01 *a) |
ebe9383c | 3625 | { |
1ca74648 | 3626 | return do_fop_wew(ctx, a->t, a->r, gen_fneg_f); |
ebe9383c RH |
3627 | } |
3628 | ||
3629 | static void gen_fneg_d(TCGv_i64 dst, TCGv_env unused, TCGv_i64 src) | |
3630 | { | |
3631 | tcg_gen_xori_i64(dst, src, INT64_MIN); | |
3632 | } | |
3633 | ||
1ca74648 RH |
3634 | static bool trans_fneg_d(DisasContext *ctx, arg_fclass01 *a) |
3635 | { | |
3636 | return do_fop_ded(ctx, a->t, a->r, gen_fneg_d); | |
3637 | } | |
3638 | ||
3639 | static void gen_fnegabs_f(TCGv_i32 dst, TCGv_env unused, TCGv_i32 src) | |
ebe9383c RH |
3640 | { |
3641 | tcg_gen_ori_i32(dst, src, INT32_MIN); | |
3642 | } | |
3643 | ||
1ca74648 RH |
3644 | static bool trans_fnegabs_f(DisasContext *ctx, arg_fclass01 *a) |
3645 | { | |
3646 | return do_fop_wew(ctx, a->t, a->r, gen_fnegabs_f); | |
3647 | } | |
3648 | ||
ebe9383c RH |
3649 | static void gen_fnegabs_d(TCGv_i64 dst, TCGv_env unused, TCGv_i64 src) |
3650 | { | |
3651 | tcg_gen_ori_i64(dst, src, INT64_MIN); | |
3652 | } | |
3653 | ||
1ca74648 RH |
3654 | static bool trans_fnegabs_d(DisasContext *ctx, arg_fclass01 *a) |
3655 | { | |
3656 | return do_fop_ded(ctx, a->t, a->r, gen_fnegabs_d); | |
3657 | } | |
3658 | ||
3659 | /* | |
3660 | * Float class 1 | |
3661 | */ | |
3662 | ||
3663 | static bool trans_fcnv_d_f(DisasContext *ctx, arg_fclass01 *a) | |
3664 | { | |
3665 | return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_d_s); | |
3666 | } | |
3667 | ||
3668 | static bool trans_fcnv_f_d(DisasContext *ctx, arg_fclass01 *a) | |
3669 | { | |
3670 | return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_s_d); | |
3671 | } | |
3672 | ||
3673 | static bool trans_fcnv_w_f(DisasContext *ctx, arg_fclass01 *a) | |
3674 | { | |
3675 | return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_w_s); | |
3676 | } | |
3677 | ||
3678 | static bool trans_fcnv_q_f(DisasContext *ctx, arg_fclass01 *a) | |
3679 | { | |
3680 | return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_dw_s); | |
3681 | } | |
3682 | ||
3683 | static bool trans_fcnv_w_d(DisasContext *ctx, arg_fclass01 *a) | |
3684 | { | |
3685 | return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_w_d); | |
3686 | } | |
3687 | ||
3688 | static bool trans_fcnv_q_d(DisasContext *ctx, arg_fclass01 *a) | |
3689 | { | |
3690 | return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_dw_d); | |
3691 | } | |
3692 | ||
3693 | static bool trans_fcnv_f_w(DisasContext *ctx, arg_fclass01 *a) | |
3694 | { | |
3695 | return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_s_w); | |
3696 | } | |
3697 | ||
3698 | static bool trans_fcnv_d_w(DisasContext *ctx, arg_fclass01 *a) | |
3699 | { | |
3700 | return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_d_w); | |
3701 | } | |
3702 | ||
3703 | static bool trans_fcnv_f_q(DisasContext *ctx, arg_fclass01 *a) | |
3704 | { | |
3705 | return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_s_dw); | |
3706 | } | |
3707 | ||
3708 | static bool trans_fcnv_d_q(DisasContext *ctx, arg_fclass01 *a) | |
3709 | { | |
3710 | return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_d_dw); | |
3711 | } | |
3712 | ||
3713 | static bool trans_fcnv_t_f_w(DisasContext *ctx, arg_fclass01 *a) | |
3714 | { | |
3715 | return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_t_s_w); | |
3716 | } | |
3717 | ||
3718 | static bool trans_fcnv_t_d_w(DisasContext *ctx, arg_fclass01 *a) | |
3719 | { | |
3720 | return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_t_d_w); | |
3721 | } | |
3722 | ||
3723 | static bool trans_fcnv_t_f_q(DisasContext *ctx, arg_fclass01 *a) | |
3724 | { | |
3725 | return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_t_s_dw); | |
3726 | } | |
3727 | ||
3728 | static bool trans_fcnv_t_d_q(DisasContext *ctx, arg_fclass01 *a) | |
3729 | { | |
3730 | return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_t_d_dw); | |
3731 | } | |
3732 | ||
3733 | static bool trans_fcnv_uw_f(DisasContext *ctx, arg_fclass01 *a) | |
3734 | { | |
3735 | return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_uw_s); | |
3736 | } | |
3737 | ||
3738 | static bool trans_fcnv_uq_f(DisasContext *ctx, arg_fclass01 *a) | |
3739 | { | |
3740 | return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_udw_s); | |
3741 | } | |
3742 | ||
3743 | static bool trans_fcnv_uw_d(DisasContext *ctx, arg_fclass01 *a) | |
3744 | { | |
3745 | return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_uw_d); | |
3746 | } | |
3747 | ||
3748 | static bool trans_fcnv_uq_d(DisasContext *ctx, arg_fclass01 *a) | |
3749 | { | |
3750 | return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_udw_d); | |
3751 | } | |
3752 | ||
3753 | static bool trans_fcnv_f_uw(DisasContext *ctx, arg_fclass01 *a) | |
3754 | { | |
3755 | return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_s_uw); | |
3756 | } | |
3757 | ||
3758 | static bool trans_fcnv_d_uw(DisasContext *ctx, arg_fclass01 *a) | |
3759 | { | |
3760 | return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_d_uw); | |
3761 | } | |
3762 | ||
3763 | static bool trans_fcnv_f_uq(DisasContext *ctx, arg_fclass01 *a) | |
3764 | { | |
3765 | return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_s_udw); | |
3766 | } | |
3767 | ||
3768 | static bool trans_fcnv_d_uq(DisasContext *ctx, arg_fclass01 *a) | |
3769 | { | |
3770 | return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_d_udw); | |
3771 | } | |
3772 | ||
3773 | static bool trans_fcnv_t_f_uw(DisasContext *ctx, arg_fclass01 *a) | |
3774 | { | |
3775 | return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_t_s_uw); | |
3776 | } | |
3777 | ||
3778 | static bool trans_fcnv_t_d_uw(DisasContext *ctx, arg_fclass01 *a) | |
3779 | { | |
3780 | return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_t_d_uw); | |
3781 | } | |
3782 | ||
3783 | static bool trans_fcnv_t_f_uq(DisasContext *ctx, arg_fclass01 *a) | |
3784 | { | |
3785 | return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_t_s_udw); | |
3786 | } | |
3787 | ||
3788 | static bool trans_fcnv_t_d_uq(DisasContext *ctx, arg_fclass01 *a) | |
3789 | { | |
3790 | return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_t_d_udw); | |
3791 | } | |
3792 | ||
3793 | /* | |
3794 | * Float class 2 | |
3795 | */ | |
3796 | ||
3797 | static bool trans_fcmp_f(DisasContext *ctx, arg_fclass2 *a) | |
ebe9383c RH |
3798 | { |
3799 | TCGv_i32 ta, tb, tc, ty; | |
3800 | ||
3801 | nullify_over(ctx); | |
3802 | ||
1ca74648 RH |
3803 | ta = load_frw0_i32(a->r1); |
3804 | tb = load_frw0_i32(a->r2); | |
29dd6f64 RH |
3805 | ty = tcg_constant_i32(a->y); |
3806 | tc = tcg_constant_i32(a->c); | |
ebe9383c RH |
3807 | |
3808 | gen_helper_fcmp_s(cpu_env, ta, tb, ty, tc); | |
3809 | ||
1ca74648 | 3810 | return nullify_end(ctx); |
ebe9383c RH |
3811 | } |
3812 | ||
1ca74648 | 3813 | static bool trans_fcmp_d(DisasContext *ctx, arg_fclass2 *a) |
ebe9383c | 3814 | { |
ebe9383c RH |
3815 | TCGv_i64 ta, tb; |
3816 | TCGv_i32 tc, ty; | |
3817 | ||
3818 | nullify_over(ctx); | |
3819 | ||
1ca74648 RH |
3820 | ta = load_frd0(a->r1); |
3821 | tb = load_frd0(a->r2); | |
29dd6f64 RH |
3822 | ty = tcg_constant_i32(a->y); |
3823 | tc = tcg_constant_i32(a->c); | |
ebe9383c RH |
3824 | |
3825 | gen_helper_fcmp_d(cpu_env, ta, tb, ty, tc); | |
3826 | ||
31234768 | 3827 | return nullify_end(ctx); |
ebe9383c RH |
3828 | } |
3829 | ||
1ca74648 | 3830 | static bool trans_ftest(DisasContext *ctx, arg_ftest *a) |
ebe9383c | 3831 | { |
eaa3783b | 3832 | TCGv_reg t; |
ebe9383c RH |
3833 | |
3834 | nullify_over(ctx); | |
3835 | ||
1ca74648 | 3836 | t = get_temp(ctx); |
eaa3783b | 3837 | tcg_gen_ld32u_reg(t, cpu_env, offsetof(CPUHPPAState, fr0_shadow)); |
ebe9383c | 3838 | |
1ca74648 RH |
3839 | if (a->y == 1) { |
3840 | int mask; | |
3841 | bool inv = false; | |
3842 | ||
3843 | switch (a->c) { | |
3844 | case 0: /* simple */ | |
3845 | tcg_gen_andi_reg(t, t, 0x4000000); | |
3846 | ctx->null_cond = cond_make_0(TCG_COND_NE, t); | |
3847 | goto done; | |
3848 | case 2: /* rej */ | |
3849 | inv = true; | |
3850 | /* fallthru */ | |
3851 | case 1: /* acc */ | |
3852 | mask = 0x43ff800; | |
3853 | break; | |
3854 | case 6: /* rej8 */ | |
3855 | inv = true; | |
3856 | /* fallthru */ | |
3857 | case 5: /* acc8 */ | |
3858 | mask = 0x43f8000; | |
3859 | break; | |
3860 | case 9: /* acc6 */ | |
3861 | mask = 0x43e0000; | |
3862 | break; | |
3863 | case 13: /* acc4 */ | |
3864 | mask = 0x4380000; | |
3865 | break; | |
3866 | case 17: /* acc2 */ | |
3867 | mask = 0x4200000; | |
3868 | break; | |
3869 | default: | |
3870 | gen_illegal(ctx); | |
3871 | return true; | |
3872 | } | |
3873 | if (inv) { | |
3874 | TCGv_reg c = load_const(ctx, mask); | |
3875 | tcg_gen_or_reg(t, t, c); | |
3876 | ctx->null_cond = cond_make(TCG_COND_EQ, t, c); | |
3877 | } else { | |
3878 | tcg_gen_andi_reg(t, t, mask); | |
3879 | ctx->null_cond = cond_make_0(TCG_COND_EQ, t); | |
3880 | } | |
3881 | } else { | |
3882 | unsigned cbit = (a->y ^ 1) - 1; | |
3883 | ||
3884 | tcg_gen_extract_reg(t, t, 21 - cbit, 1); | |
3885 | ctx->null_cond = cond_make_0(TCG_COND_NE, t); | |
1ca74648 RH |
3886 | } |
3887 | ||
3888 | done: | |
31234768 | 3889 | return nullify_end(ctx); |
ebe9383c RH |
3890 | } |
3891 | ||
1ca74648 RH |
3892 | /* |
3893 | * Float class 2 | |
3894 | */ | |
3895 | ||
3896 | static bool trans_fadd_f(DisasContext *ctx, arg_fclass3 *a) | |
ebe9383c | 3897 | { |
1ca74648 RH |
3898 | return do_fop_weww(ctx, a->t, a->r1, a->r2, gen_helper_fadd_s); |
3899 | } | |
ebe9383c | 3900 | |
1ca74648 RH |
3901 | static bool trans_fadd_d(DisasContext *ctx, arg_fclass3 *a) |
3902 | { | |
3903 | return do_fop_dedd(ctx, a->t, a->r1, a->r2, gen_helper_fadd_d); | |
3904 | } | |
ebe9383c | 3905 | |
1ca74648 RH |
3906 | static bool trans_fsub_f(DisasContext *ctx, arg_fclass3 *a) |
3907 | { | |
3908 | return do_fop_weww(ctx, a->t, a->r1, a->r2, gen_helper_fsub_s); | |
3909 | } | |
ebe9383c | 3910 | |
1ca74648 RH |
3911 | static bool trans_fsub_d(DisasContext *ctx, arg_fclass3 *a) |
3912 | { | |
3913 | return do_fop_dedd(ctx, a->t, a->r1, a->r2, gen_helper_fsub_d); | |
ebe9383c RH |
3914 | } |
3915 | ||
1ca74648 | 3916 | static bool trans_fmpy_f(DisasContext *ctx, arg_fclass3 *a) |
ebe9383c | 3917 | { |
1ca74648 RH |
3918 | return do_fop_weww(ctx, a->t, a->r1, a->r2, gen_helper_fmpy_s); |
3919 | } | |
3920 | ||
3921 | static bool trans_fmpy_d(DisasContext *ctx, arg_fclass3 *a) | |
3922 | { | |
3923 | return do_fop_dedd(ctx, a->t, a->r1, a->r2, gen_helper_fmpy_d); | |
3924 | } | |
3925 | ||
3926 | static bool trans_fdiv_f(DisasContext *ctx, arg_fclass3 *a) | |
3927 | { | |
3928 | return do_fop_weww(ctx, a->t, a->r1, a->r2, gen_helper_fdiv_s); | |
3929 | } | |
3930 | ||
3931 | static bool trans_fdiv_d(DisasContext *ctx, arg_fclass3 *a) | |
3932 | { | |
3933 | return do_fop_dedd(ctx, a->t, a->r1, a->r2, gen_helper_fdiv_d); | |
3934 | } | |
3935 | ||
3936 | static bool trans_xmpyu(DisasContext *ctx, arg_xmpyu *a) | |
3937 | { | |
3938 | TCGv_i64 x, y; | |
ebe9383c RH |
3939 | |
3940 | nullify_over(ctx); | |
3941 | ||
1ca74648 RH |
3942 | x = load_frw0_i64(a->r1); |
3943 | y = load_frw0_i64(a->r2); | |
3944 | tcg_gen_mul_i64(x, x, y); | |
3945 | save_frd(a->t, x); | |
ebe9383c | 3946 | |
31234768 | 3947 | return nullify_end(ctx); |
ebe9383c RH |
3948 | } |
3949 | ||
ebe9383c RH |
3950 | /* Convert the fmpyadd single-precision register encodings to standard. */ |
3951 | static inline int fmpyadd_s_reg(unsigned r) | |
3952 | { | |
3953 | return (r & 16) * 2 + 16 + (r & 15); | |
3954 | } | |
3955 | ||
b1e2af57 | 3956 | static bool do_fmpyadd_s(DisasContext *ctx, arg_mpyadd *a, bool is_sub) |
ebe9383c | 3957 | { |
b1e2af57 RH |
3958 | int tm = fmpyadd_s_reg(a->tm); |
3959 | int ra = fmpyadd_s_reg(a->ra); | |
3960 | int ta = fmpyadd_s_reg(a->ta); | |
3961 | int rm2 = fmpyadd_s_reg(a->rm2); | |
3962 | int rm1 = fmpyadd_s_reg(a->rm1); | |
ebe9383c RH |
3963 | |
3964 | nullify_over(ctx); | |
3965 | ||
b1e2af57 RH |
3966 | do_fop_weww(ctx, tm, rm1, rm2, gen_helper_fmpy_s); |
3967 | do_fop_weww(ctx, ta, ta, ra, | |
3968 | is_sub ? gen_helper_fsub_s : gen_helper_fadd_s); | |
ebe9383c | 3969 | |
31234768 | 3970 | return nullify_end(ctx); |
ebe9383c RH |
3971 | } |
3972 | ||
b1e2af57 RH |
3973 | static bool trans_fmpyadd_f(DisasContext *ctx, arg_mpyadd *a) |
3974 | { | |
3975 | return do_fmpyadd_s(ctx, a, false); | |
3976 | } | |
3977 | ||
3978 | static bool trans_fmpysub_f(DisasContext *ctx, arg_mpyadd *a) | |
3979 | { | |
3980 | return do_fmpyadd_s(ctx, a, true); | |
3981 | } | |
3982 | ||
3983 | static bool do_fmpyadd_d(DisasContext *ctx, arg_mpyadd *a, bool is_sub) | |
3984 | { | |
3985 | nullify_over(ctx); | |
3986 | ||
3987 | do_fop_dedd(ctx, a->tm, a->rm1, a->rm2, gen_helper_fmpy_d); | |
3988 | do_fop_dedd(ctx, a->ta, a->ta, a->ra, | |
3989 | is_sub ? gen_helper_fsub_d : gen_helper_fadd_d); | |
3990 | ||
3991 | return nullify_end(ctx); | |
3992 | } | |
3993 | ||
3994 | static bool trans_fmpyadd_d(DisasContext *ctx, arg_mpyadd *a) | |
3995 | { | |
3996 | return do_fmpyadd_d(ctx, a, false); | |
3997 | } | |
3998 | ||
3999 | static bool trans_fmpysub_d(DisasContext *ctx, arg_mpyadd *a) | |
4000 | { | |
4001 | return do_fmpyadd_d(ctx, a, true); | |
4002 | } | |
4003 | ||
c3bad4f8 | 4004 | static bool trans_fmpyfadd_f(DisasContext *ctx, arg_fmpyfadd_f *a) |
ebe9383c | 4005 | { |
c3bad4f8 | 4006 | TCGv_i32 x, y, z; |
ebe9383c RH |
4007 | |
4008 | nullify_over(ctx); | |
c3bad4f8 RH |
4009 | x = load_frw0_i32(a->rm1); |
4010 | y = load_frw0_i32(a->rm2); | |
4011 | z = load_frw0_i32(a->ra3); | |
ebe9383c | 4012 | |
c3bad4f8 RH |
4013 | if (a->neg) { |
4014 | gen_helper_fmpynfadd_s(x, cpu_env, x, y, z); | |
ebe9383c | 4015 | } else { |
c3bad4f8 | 4016 | gen_helper_fmpyfadd_s(x, cpu_env, x, y, z); |
ebe9383c RH |
4017 | } |
4018 | ||
c3bad4f8 | 4019 | save_frw_i32(a->t, x); |
31234768 | 4020 | return nullify_end(ctx); |
ebe9383c RH |
4021 | } |
4022 | ||
c3bad4f8 | 4023 | static bool trans_fmpyfadd_d(DisasContext *ctx, arg_fmpyfadd_d *a) |
ebe9383c | 4024 | { |
c3bad4f8 | 4025 | TCGv_i64 x, y, z; |
ebe9383c RH |
4026 | |
4027 | nullify_over(ctx); | |
c3bad4f8 RH |
4028 | x = load_frd0(a->rm1); |
4029 | y = load_frd0(a->rm2); | |
4030 | z = load_frd0(a->ra3); | |
ebe9383c | 4031 | |
c3bad4f8 RH |
4032 | if (a->neg) { |
4033 | gen_helper_fmpynfadd_d(x, cpu_env, x, y, z); | |
ebe9383c | 4034 | } else { |
c3bad4f8 | 4035 | gen_helper_fmpyfadd_d(x, cpu_env, x, y, z); |
ebe9383c RH |
4036 | } |
4037 | ||
c3bad4f8 | 4038 | save_frd(a->t, x); |
31234768 | 4039 | return nullify_end(ctx); |
ebe9383c RH |
4040 | } |
4041 | ||
15da177b SS |
4042 | static bool trans_diag(DisasContext *ctx, arg_diag *a) |
4043 | { | |
4044 | qemu_log_mask(LOG_UNIMP, "DIAG opcode ignored\n"); | |
4045 | cond_free(&ctx->null_cond); | |
4046 | return true; | |
4047 | } | |
4048 | ||
b542683d | 4049 | static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) |
61766fe9 | 4050 | { |
51b061fb | 4051 | DisasContext *ctx = container_of(dcbase, DisasContext, base); |
f764718d | 4052 | int bound; |
61766fe9 | 4053 | |
51b061fb | 4054 | ctx->cs = cs; |
494737b7 | 4055 | ctx->tb_flags = ctx->base.tb->flags; |
3d68ee7b RH |
4056 | |
4057 | #ifdef CONFIG_USER_ONLY | |
4058 | ctx->privilege = MMU_USER_IDX; | |
4059 | ctx->mmu_idx = MMU_USER_IDX; | |
ebd0e151 RH |
4060 | ctx->iaoq_f = ctx->base.pc_first | MMU_USER_IDX; |
4061 | ctx->iaoq_b = ctx->base.tb->cs_base | MMU_USER_IDX; | |
217d1a5e | 4062 | ctx->unalign = (ctx->tb_flags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN); |
3d68ee7b | 4063 | #else |
494737b7 RH |
4064 | ctx->privilege = (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3; |
4065 | ctx->mmu_idx = (ctx->tb_flags & PSW_D ? ctx->privilege : MMU_PHYS_IDX); | |
3d68ee7b | 4066 | |
c301f34e RH |
4067 | /* Recover the IAOQ values from the GVA + PRIV. */ |
4068 | uint64_t cs_base = ctx->base.tb->cs_base; | |
4069 | uint64_t iasq_f = cs_base & ~0xffffffffull; | |
4070 | int32_t diff = cs_base; | |
4071 | ||
4072 | ctx->iaoq_f = (ctx->base.pc_first & ~iasq_f) + ctx->privilege; | |
4073 | ctx->iaoq_b = (diff ? ctx->iaoq_f + diff : -1); | |
4074 | #endif | |
51b061fb | 4075 | ctx->iaoq_n = -1; |
f764718d | 4076 | ctx->iaoq_n_var = NULL; |
61766fe9 | 4077 | |
3d68ee7b RH |
4078 | /* Bound the number of instructions by those left on the page. */ |
4079 | bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; | |
b542683d | 4080 | ctx->base.max_insns = MIN(ctx->base.max_insns, bound); |
3d68ee7b | 4081 | |
86f8d05f RH |
4082 | ctx->ntempr = 0; |
4083 | ctx->ntempl = 0; | |
4084 | memset(ctx->tempr, 0, sizeof(ctx->tempr)); | |
4085 | memset(ctx->templ, 0, sizeof(ctx->templ)); | |
51b061fb | 4086 | } |
61766fe9 | 4087 | |
51b061fb RH |
4088 | static void hppa_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) |
4089 | { | |
4090 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
61766fe9 | 4091 | |
3d68ee7b | 4092 | /* Seed the nullification status from PSW[N], as saved in TB->FLAGS. */ |
51b061fb RH |
4093 | ctx->null_cond = cond_make_f(); |
4094 | ctx->psw_n_nonzero = false; | |
494737b7 | 4095 | if (ctx->tb_flags & PSW_N) { |
51b061fb RH |
4096 | ctx->null_cond.c = TCG_COND_ALWAYS; |
4097 | ctx->psw_n_nonzero = true; | |
129e9cc3 | 4098 | } |
51b061fb RH |
4099 | ctx->null_lab = NULL; |
4100 | } | |
129e9cc3 | 4101 | |
51b061fb RH |
4102 | static void hppa_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) |
4103 | { | |
4104 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
61766fe9 | 4105 | |
51b061fb RH |
4106 | tcg_gen_insn_start(ctx->iaoq_f, ctx->iaoq_b); |
4107 | } | |
4108 | ||
51b061fb RH |
4109 | static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) |
4110 | { | |
4111 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
4112 | CPUHPPAState *env = cs->env_ptr; | |
4113 | DisasJumpType ret; | |
4114 | int i, n; | |
4115 | ||
4116 | /* Execute one insn. */ | |
ba1d0b44 | 4117 | #ifdef CONFIG_USER_ONLY |
c301f34e | 4118 | if (ctx->base.pc_next < TARGET_PAGE_SIZE) { |
31234768 RH |
4119 | do_page_zero(ctx); |
4120 | ret = ctx->base.is_jmp; | |
51b061fb | 4121 | assert(ret != DISAS_NEXT); |
ba1d0b44 RH |
4122 | } else |
4123 | #endif | |
4124 | { | |
51b061fb RH |
4125 | /* Always fetch the insn, even if nullified, so that we check |
4126 | the page permissions for execute. */ | |
4e116893 | 4127 | uint32_t insn = translator_ldl(env, &ctx->base, ctx->base.pc_next); |
51b061fb RH |
4128 | |
4129 | /* Set up the IA queue for the next insn. | |
4130 | This will be overwritten by a branch. */ | |
4131 | if (ctx->iaoq_b == -1) { | |
4132 | ctx->iaoq_n = -1; | |
4133 | ctx->iaoq_n_var = get_temp(ctx); | |
eaa3783b | 4134 | tcg_gen_addi_reg(ctx->iaoq_n_var, cpu_iaoq_b, 4); |
7ad439df | 4135 | } else { |
51b061fb | 4136 | ctx->iaoq_n = ctx->iaoq_b + 4; |
f764718d | 4137 | ctx->iaoq_n_var = NULL; |
61766fe9 RH |
4138 | } |
4139 | ||
51b061fb RH |
4140 | if (unlikely(ctx->null_cond.c == TCG_COND_ALWAYS)) { |
4141 | ctx->null_cond.c = TCG_COND_NEVER; | |
4142 | ret = DISAS_NEXT; | |
4143 | } else { | |
1a19da0d | 4144 | ctx->insn = insn; |
31274b46 RH |
4145 | if (!decode(ctx, insn)) { |
4146 | gen_illegal(ctx); | |
4147 | } | |
31234768 | 4148 | ret = ctx->base.is_jmp; |
51b061fb | 4149 | assert(ctx->null_lab == NULL); |
61766fe9 | 4150 | } |
51b061fb | 4151 | } |
61766fe9 | 4152 | |
af187238 | 4153 | /* Forget any temporaries allocated. */ |
86f8d05f | 4154 | for (i = 0, n = ctx->ntempr; i < n; ++i) { |
86f8d05f RH |
4155 | ctx->tempr[i] = NULL; |
4156 | } | |
4157 | for (i = 0, n = ctx->ntempl; i < n; ++i) { | |
86f8d05f | 4158 | ctx->templ[i] = NULL; |
51b061fb | 4159 | } |
86f8d05f RH |
4160 | ctx->ntempr = 0; |
4161 | ctx->ntempl = 0; | |
61766fe9 | 4162 | |
3d68ee7b RH |
4163 | /* Advance the insn queue. Note that this check also detects |
4164 | a priority change within the instruction queue. */ | |
51b061fb | 4165 | if (ret == DISAS_NEXT && ctx->iaoq_b != ctx->iaoq_f + 4) { |
c301f34e RH |
4166 | if (ctx->iaoq_b != -1 && ctx->iaoq_n != -1 |
4167 | && use_goto_tb(ctx, ctx->iaoq_b) | |
4168 | && (ctx->null_cond.c == TCG_COND_NEVER | |
4169 | || ctx->null_cond.c == TCG_COND_ALWAYS)) { | |
51b061fb RH |
4170 | nullify_set(ctx, ctx->null_cond.c == TCG_COND_ALWAYS); |
4171 | gen_goto_tb(ctx, 0, ctx->iaoq_b, ctx->iaoq_n); | |
31234768 | 4172 | ctx->base.is_jmp = ret = DISAS_NORETURN; |
51b061fb | 4173 | } else { |
31234768 | 4174 | ctx->base.is_jmp = ret = DISAS_IAQ_N_STALE; |
c301f34e | 4175 | } |
61766fe9 | 4176 | } |
51b061fb RH |
4177 | ctx->iaoq_f = ctx->iaoq_b; |
4178 | ctx->iaoq_b = ctx->iaoq_n; | |
c301f34e | 4179 | ctx->base.pc_next += 4; |
51b061fb | 4180 | |
c5d0aec2 RH |
4181 | switch (ret) { |
4182 | case DISAS_NORETURN: | |
4183 | case DISAS_IAQ_N_UPDATED: | |
4184 | break; | |
4185 | ||
4186 | case DISAS_NEXT: | |
4187 | case DISAS_IAQ_N_STALE: | |
4188 | case DISAS_IAQ_N_STALE_EXIT: | |
4189 | if (ctx->iaoq_f == -1) { | |
4190 | tcg_gen_mov_reg(cpu_iaoq_f, cpu_iaoq_b); | |
4191 | copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var); | |
c301f34e | 4192 | #ifndef CONFIG_USER_ONLY |
c5d0aec2 | 4193 | tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); |
c301f34e | 4194 | #endif |
c5d0aec2 RH |
4195 | nullify_save(ctx); |
4196 | ctx->base.is_jmp = (ret == DISAS_IAQ_N_STALE_EXIT | |
4197 | ? DISAS_EXIT | |
4198 | : DISAS_IAQ_N_UPDATED); | |
4199 | } else if (ctx->iaoq_b == -1) { | |
4200 | tcg_gen_mov_reg(cpu_iaoq_b, ctx->iaoq_n_var); | |
4201 | } | |
4202 | break; | |
4203 | ||
4204 | default: | |
4205 | g_assert_not_reached(); | |
51b061fb RH |
4206 | } |
4207 | } | |
4208 | ||
4209 | static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) | |
4210 | { | |
4211 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
e1b5a5ed | 4212 | DisasJumpType is_jmp = ctx->base.is_jmp; |
61766fe9 | 4213 | |
e1b5a5ed | 4214 | switch (is_jmp) { |
869051ea | 4215 | case DISAS_NORETURN: |
61766fe9 | 4216 | break; |
51b061fb | 4217 | case DISAS_TOO_MANY: |
869051ea | 4218 | case DISAS_IAQ_N_STALE: |
e1b5a5ed | 4219 | case DISAS_IAQ_N_STALE_EXIT: |
51b061fb RH |
4220 | copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_f, cpu_iaoq_f); |
4221 | copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_b, cpu_iaoq_b); | |
4222 | nullify_save(ctx); | |
61766fe9 | 4223 | /* FALLTHRU */ |
869051ea | 4224 | case DISAS_IAQ_N_UPDATED: |
8532a14e | 4225 | if (is_jmp != DISAS_IAQ_N_STALE_EXIT) { |
7f11636d | 4226 | tcg_gen_lookup_and_goto_ptr(); |
8532a14e | 4227 | break; |
61766fe9 | 4228 | } |
c5d0aec2 RH |
4229 | /* FALLTHRU */ |
4230 | case DISAS_EXIT: | |
4231 | tcg_gen_exit_tb(NULL, 0); | |
61766fe9 RH |
4232 | break; |
4233 | default: | |
51b061fb | 4234 | g_assert_not_reached(); |
61766fe9 | 4235 | } |
51b061fb | 4236 | } |
61766fe9 | 4237 | |
8eb806a7 RH |
4238 | static void hppa_tr_disas_log(const DisasContextBase *dcbase, |
4239 | CPUState *cs, FILE *logfile) | |
51b061fb | 4240 | { |
c301f34e | 4241 | target_ulong pc = dcbase->pc_first; |
61766fe9 | 4242 | |
ba1d0b44 RH |
4243 | #ifdef CONFIG_USER_ONLY |
4244 | switch (pc) { | |
51b061fb | 4245 | case 0x00: |
8eb806a7 | 4246 | fprintf(logfile, "IN:\n0x00000000: (null)\n"); |
ba1d0b44 | 4247 | return; |
51b061fb | 4248 | case 0xb0: |
8eb806a7 | 4249 | fprintf(logfile, "IN:\n0x000000b0: light-weight-syscall\n"); |
ba1d0b44 | 4250 | return; |
51b061fb | 4251 | case 0xe0: |
8eb806a7 | 4252 | fprintf(logfile, "IN:\n0x000000e0: set-thread-pointer-syscall\n"); |
ba1d0b44 | 4253 | return; |
51b061fb | 4254 | case 0x100: |
8eb806a7 | 4255 | fprintf(logfile, "IN:\n0x00000100: syscall\n"); |
ba1d0b44 | 4256 | return; |
61766fe9 | 4257 | } |
ba1d0b44 RH |
4258 | #endif |
4259 | ||
8eb806a7 RH |
4260 | fprintf(logfile, "IN: %s\n", lookup_symbol(pc)); |
4261 | target_disas(logfile, cs, pc, dcbase->tb->size); | |
51b061fb RH |
4262 | } |
4263 | ||
4264 | static const TranslatorOps hppa_tr_ops = { | |
4265 | .init_disas_context = hppa_tr_init_disas_context, | |
4266 | .tb_start = hppa_tr_tb_start, | |
4267 | .insn_start = hppa_tr_insn_start, | |
51b061fb RH |
4268 | .translate_insn = hppa_tr_translate_insn, |
4269 | .tb_stop = hppa_tr_tb_stop, | |
4270 | .disas_log = hppa_tr_disas_log, | |
4271 | }; | |
4272 | ||
597f9b2d | 4273 | void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, |
306c8721 | 4274 | target_ulong pc, void *host_pc) |
51b061fb RH |
4275 | { |
4276 | DisasContext ctx; | |
306c8721 | 4277 | translator_loop(cs, tb, max_insns, pc, host_pc, &hppa_tr_ops, &ctx.base); |
61766fe9 | 4278 | } |