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61766fe9 RH |
1 | /* |
2 | * HPPA emulation cpu translation for qemu. | |
3 | * | |
4 | * Copyright (c) 2016 Richard Henderson <rth@twiddle.net> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
d6ea4236 | 9 | * version 2.1 of the License, or (at your option) any later version. |
61766fe9 RH |
10 | * |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
21 | #include "cpu.h" | |
22 | #include "disas/disas.h" | |
23 | #include "qemu/host-utils.h" | |
24 | #include "exec/exec-all.h" | |
dcb32f1d | 25 | #include "tcg/tcg-op.h" |
61766fe9 RH |
26 | #include "exec/helper-proto.h" |
27 | #include "exec/helper-gen.h" | |
869051ea | 28 | #include "exec/translator.h" |
61766fe9 RH |
29 | #include "exec/log.h" |
30 | ||
d53106c9 RH |
31 | #define HELPER_H "helper.h" |
32 | #include "exec/helper-info.c.inc" | |
33 | #undef HELPER_H | |
34 | ||
35 | ||
eaa3783b RH |
36 | /* Since we have a distinction between register size and address size, |
37 | we need to redefine all of these. */ | |
38 | ||
39 | #undef TCGv | |
40 | #undef tcg_temp_new | |
eaa3783b | 41 | #undef tcg_global_mem_new |
eaa3783b RH |
42 | |
43 | #if TARGET_LONG_BITS == 64 | |
44 | #define TCGv_tl TCGv_i64 | |
45 | #define tcg_temp_new_tl tcg_temp_new_i64 | |
eaa3783b RH |
46 | #if TARGET_REGISTER_BITS == 64 |
47 | #define tcg_gen_extu_reg_tl tcg_gen_mov_i64 | |
48 | #else | |
49 | #define tcg_gen_extu_reg_tl tcg_gen_extu_i32_i64 | |
50 | #endif | |
51 | #else | |
52 | #define TCGv_tl TCGv_i32 | |
53 | #define tcg_temp_new_tl tcg_temp_new_i32 | |
eaa3783b RH |
54 | #define tcg_gen_extu_reg_tl tcg_gen_mov_i32 |
55 | #endif | |
56 | ||
57 | #if TARGET_REGISTER_BITS == 64 | |
58 | #define TCGv_reg TCGv_i64 | |
59 | ||
60 | #define tcg_temp_new tcg_temp_new_i64 | |
eaa3783b | 61 | #define tcg_global_mem_new tcg_global_mem_new_i64 |
eaa3783b RH |
62 | |
63 | #define tcg_gen_movi_reg tcg_gen_movi_i64 | |
64 | #define tcg_gen_mov_reg tcg_gen_mov_i64 | |
65 | #define tcg_gen_ld8u_reg tcg_gen_ld8u_i64 | |
66 | #define tcg_gen_ld8s_reg tcg_gen_ld8s_i64 | |
67 | #define tcg_gen_ld16u_reg tcg_gen_ld16u_i64 | |
68 | #define tcg_gen_ld16s_reg tcg_gen_ld16s_i64 | |
69 | #define tcg_gen_ld32u_reg tcg_gen_ld32u_i64 | |
70 | #define tcg_gen_ld32s_reg tcg_gen_ld32s_i64 | |
71 | #define tcg_gen_ld_reg tcg_gen_ld_i64 | |
72 | #define tcg_gen_st8_reg tcg_gen_st8_i64 | |
73 | #define tcg_gen_st16_reg tcg_gen_st16_i64 | |
74 | #define tcg_gen_st32_reg tcg_gen_st32_i64 | |
75 | #define tcg_gen_st_reg tcg_gen_st_i64 | |
76 | #define tcg_gen_add_reg tcg_gen_add_i64 | |
77 | #define tcg_gen_addi_reg tcg_gen_addi_i64 | |
78 | #define tcg_gen_sub_reg tcg_gen_sub_i64 | |
79 | #define tcg_gen_neg_reg tcg_gen_neg_i64 | |
80 | #define tcg_gen_subfi_reg tcg_gen_subfi_i64 | |
81 | #define tcg_gen_subi_reg tcg_gen_subi_i64 | |
82 | #define tcg_gen_and_reg tcg_gen_and_i64 | |
83 | #define tcg_gen_andi_reg tcg_gen_andi_i64 | |
84 | #define tcg_gen_or_reg tcg_gen_or_i64 | |
85 | #define tcg_gen_ori_reg tcg_gen_ori_i64 | |
86 | #define tcg_gen_xor_reg tcg_gen_xor_i64 | |
87 | #define tcg_gen_xori_reg tcg_gen_xori_i64 | |
88 | #define tcg_gen_not_reg tcg_gen_not_i64 | |
89 | #define tcg_gen_shl_reg tcg_gen_shl_i64 | |
90 | #define tcg_gen_shli_reg tcg_gen_shli_i64 | |
91 | #define tcg_gen_shr_reg tcg_gen_shr_i64 | |
92 | #define tcg_gen_shri_reg tcg_gen_shri_i64 | |
93 | #define tcg_gen_sar_reg tcg_gen_sar_i64 | |
94 | #define tcg_gen_sari_reg tcg_gen_sari_i64 | |
95 | #define tcg_gen_brcond_reg tcg_gen_brcond_i64 | |
96 | #define tcg_gen_brcondi_reg tcg_gen_brcondi_i64 | |
97 | #define tcg_gen_setcond_reg tcg_gen_setcond_i64 | |
98 | #define tcg_gen_setcondi_reg tcg_gen_setcondi_i64 | |
99 | #define tcg_gen_mul_reg tcg_gen_mul_i64 | |
100 | #define tcg_gen_muli_reg tcg_gen_muli_i64 | |
101 | #define tcg_gen_div_reg tcg_gen_div_i64 | |
102 | #define tcg_gen_rem_reg tcg_gen_rem_i64 | |
103 | #define tcg_gen_divu_reg tcg_gen_divu_i64 | |
104 | #define tcg_gen_remu_reg tcg_gen_remu_i64 | |
105 | #define tcg_gen_discard_reg tcg_gen_discard_i64 | |
106 | #define tcg_gen_trunc_reg_i32 tcg_gen_extrl_i64_i32 | |
107 | #define tcg_gen_trunc_i64_reg tcg_gen_mov_i64 | |
108 | #define tcg_gen_extu_i32_reg tcg_gen_extu_i32_i64 | |
109 | #define tcg_gen_ext_i32_reg tcg_gen_ext_i32_i64 | |
110 | #define tcg_gen_extu_reg_i64 tcg_gen_mov_i64 | |
111 | #define tcg_gen_ext_reg_i64 tcg_gen_mov_i64 | |
112 | #define tcg_gen_ext8u_reg tcg_gen_ext8u_i64 | |
113 | #define tcg_gen_ext8s_reg tcg_gen_ext8s_i64 | |
114 | #define tcg_gen_ext16u_reg tcg_gen_ext16u_i64 | |
115 | #define tcg_gen_ext16s_reg tcg_gen_ext16s_i64 | |
116 | #define tcg_gen_ext32u_reg tcg_gen_ext32u_i64 | |
117 | #define tcg_gen_ext32s_reg tcg_gen_ext32s_i64 | |
118 | #define tcg_gen_bswap16_reg tcg_gen_bswap16_i64 | |
119 | #define tcg_gen_bswap32_reg tcg_gen_bswap32_i64 | |
120 | #define tcg_gen_bswap64_reg tcg_gen_bswap64_i64 | |
121 | #define tcg_gen_concat_reg_i64 tcg_gen_concat32_i64 | |
122 | #define tcg_gen_andc_reg tcg_gen_andc_i64 | |
123 | #define tcg_gen_eqv_reg tcg_gen_eqv_i64 | |
124 | #define tcg_gen_nand_reg tcg_gen_nand_i64 | |
125 | #define tcg_gen_nor_reg tcg_gen_nor_i64 | |
126 | #define tcg_gen_orc_reg tcg_gen_orc_i64 | |
127 | #define tcg_gen_clz_reg tcg_gen_clz_i64 | |
128 | #define tcg_gen_ctz_reg tcg_gen_ctz_i64 | |
129 | #define tcg_gen_clzi_reg tcg_gen_clzi_i64 | |
130 | #define tcg_gen_ctzi_reg tcg_gen_ctzi_i64 | |
131 | #define tcg_gen_clrsb_reg tcg_gen_clrsb_i64 | |
132 | #define tcg_gen_ctpop_reg tcg_gen_ctpop_i64 | |
133 | #define tcg_gen_rotl_reg tcg_gen_rotl_i64 | |
134 | #define tcg_gen_rotli_reg tcg_gen_rotli_i64 | |
135 | #define tcg_gen_rotr_reg tcg_gen_rotr_i64 | |
136 | #define tcg_gen_rotri_reg tcg_gen_rotri_i64 | |
137 | #define tcg_gen_deposit_reg tcg_gen_deposit_i64 | |
138 | #define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i64 | |
139 | #define tcg_gen_extract_reg tcg_gen_extract_i64 | |
140 | #define tcg_gen_sextract_reg tcg_gen_sextract_i64 | |
05bfd4db | 141 | #define tcg_gen_extract2_reg tcg_gen_extract2_i64 |
29dd6f64 | 142 | #define tcg_constant_reg tcg_constant_i64 |
eaa3783b RH |
143 | #define tcg_gen_movcond_reg tcg_gen_movcond_i64 |
144 | #define tcg_gen_add2_reg tcg_gen_add2_i64 | |
145 | #define tcg_gen_sub2_reg tcg_gen_sub2_i64 | |
146 | #define tcg_gen_qemu_ld_reg tcg_gen_qemu_ld_i64 | |
147 | #define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i64 | |
148 | #define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i64 | |
5bfa8034 | 149 | #define tcg_gen_trunc_reg_ptr tcg_gen_trunc_i64_ptr |
eaa3783b RH |
150 | #else |
151 | #define TCGv_reg TCGv_i32 | |
152 | #define tcg_temp_new tcg_temp_new_i32 | |
eaa3783b | 153 | #define tcg_global_mem_new tcg_global_mem_new_i32 |
eaa3783b RH |
154 | |
155 | #define tcg_gen_movi_reg tcg_gen_movi_i32 | |
156 | #define tcg_gen_mov_reg tcg_gen_mov_i32 | |
157 | #define tcg_gen_ld8u_reg tcg_gen_ld8u_i32 | |
158 | #define tcg_gen_ld8s_reg tcg_gen_ld8s_i32 | |
159 | #define tcg_gen_ld16u_reg tcg_gen_ld16u_i32 | |
160 | #define tcg_gen_ld16s_reg tcg_gen_ld16s_i32 | |
161 | #define tcg_gen_ld32u_reg tcg_gen_ld_i32 | |
162 | #define tcg_gen_ld32s_reg tcg_gen_ld_i32 | |
163 | #define tcg_gen_ld_reg tcg_gen_ld_i32 | |
164 | #define tcg_gen_st8_reg tcg_gen_st8_i32 | |
165 | #define tcg_gen_st16_reg tcg_gen_st16_i32 | |
166 | #define tcg_gen_st32_reg tcg_gen_st32_i32 | |
167 | #define tcg_gen_st_reg tcg_gen_st_i32 | |
168 | #define tcg_gen_add_reg tcg_gen_add_i32 | |
169 | #define tcg_gen_addi_reg tcg_gen_addi_i32 | |
170 | #define tcg_gen_sub_reg tcg_gen_sub_i32 | |
171 | #define tcg_gen_neg_reg tcg_gen_neg_i32 | |
172 | #define tcg_gen_subfi_reg tcg_gen_subfi_i32 | |
173 | #define tcg_gen_subi_reg tcg_gen_subi_i32 | |
174 | #define tcg_gen_and_reg tcg_gen_and_i32 | |
175 | #define tcg_gen_andi_reg tcg_gen_andi_i32 | |
176 | #define tcg_gen_or_reg tcg_gen_or_i32 | |
177 | #define tcg_gen_ori_reg tcg_gen_ori_i32 | |
178 | #define tcg_gen_xor_reg tcg_gen_xor_i32 | |
179 | #define tcg_gen_xori_reg tcg_gen_xori_i32 | |
180 | #define tcg_gen_not_reg tcg_gen_not_i32 | |
181 | #define tcg_gen_shl_reg tcg_gen_shl_i32 | |
182 | #define tcg_gen_shli_reg tcg_gen_shli_i32 | |
183 | #define tcg_gen_shr_reg tcg_gen_shr_i32 | |
184 | #define tcg_gen_shri_reg tcg_gen_shri_i32 | |
185 | #define tcg_gen_sar_reg tcg_gen_sar_i32 | |
186 | #define tcg_gen_sari_reg tcg_gen_sari_i32 | |
187 | #define tcg_gen_brcond_reg tcg_gen_brcond_i32 | |
188 | #define tcg_gen_brcondi_reg tcg_gen_brcondi_i32 | |
189 | #define tcg_gen_setcond_reg tcg_gen_setcond_i32 | |
190 | #define tcg_gen_setcondi_reg tcg_gen_setcondi_i32 | |
191 | #define tcg_gen_mul_reg tcg_gen_mul_i32 | |
192 | #define tcg_gen_muli_reg tcg_gen_muli_i32 | |
193 | #define tcg_gen_div_reg tcg_gen_div_i32 | |
194 | #define tcg_gen_rem_reg tcg_gen_rem_i32 | |
195 | #define tcg_gen_divu_reg tcg_gen_divu_i32 | |
196 | #define tcg_gen_remu_reg tcg_gen_remu_i32 | |
197 | #define tcg_gen_discard_reg tcg_gen_discard_i32 | |
198 | #define tcg_gen_trunc_reg_i32 tcg_gen_mov_i32 | |
199 | #define tcg_gen_trunc_i64_reg tcg_gen_extrl_i64_i32 | |
200 | #define tcg_gen_extu_i32_reg tcg_gen_mov_i32 | |
201 | #define tcg_gen_ext_i32_reg tcg_gen_mov_i32 | |
202 | #define tcg_gen_extu_reg_i64 tcg_gen_extu_i32_i64 | |
203 | #define tcg_gen_ext_reg_i64 tcg_gen_ext_i32_i64 | |
204 | #define tcg_gen_ext8u_reg tcg_gen_ext8u_i32 | |
205 | #define tcg_gen_ext8s_reg tcg_gen_ext8s_i32 | |
206 | #define tcg_gen_ext16u_reg tcg_gen_ext16u_i32 | |
207 | #define tcg_gen_ext16s_reg tcg_gen_ext16s_i32 | |
208 | #define tcg_gen_ext32u_reg tcg_gen_mov_i32 | |
209 | #define tcg_gen_ext32s_reg tcg_gen_mov_i32 | |
210 | #define tcg_gen_bswap16_reg tcg_gen_bswap16_i32 | |
211 | #define tcg_gen_bswap32_reg tcg_gen_bswap32_i32 | |
212 | #define tcg_gen_concat_reg_i64 tcg_gen_concat_i32_i64 | |
213 | #define tcg_gen_andc_reg tcg_gen_andc_i32 | |
214 | #define tcg_gen_eqv_reg tcg_gen_eqv_i32 | |
215 | #define tcg_gen_nand_reg tcg_gen_nand_i32 | |
216 | #define tcg_gen_nor_reg tcg_gen_nor_i32 | |
217 | #define tcg_gen_orc_reg tcg_gen_orc_i32 | |
218 | #define tcg_gen_clz_reg tcg_gen_clz_i32 | |
219 | #define tcg_gen_ctz_reg tcg_gen_ctz_i32 | |
220 | #define tcg_gen_clzi_reg tcg_gen_clzi_i32 | |
221 | #define tcg_gen_ctzi_reg tcg_gen_ctzi_i32 | |
222 | #define tcg_gen_clrsb_reg tcg_gen_clrsb_i32 | |
223 | #define tcg_gen_ctpop_reg tcg_gen_ctpop_i32 | |
224 | #define tcg_gen_rotl_reg tcg_gen_rotl_i32 | |
225 | #define tcg_gen_rotli_reg tcg_gen_rotli_i32 | |
226 | #define tcg_gen_rotr_reg tcg_gen_rotr_i32 | |
227 | #define tcg_gen_rotri_reg tcg_gen_rotri_i32 | |
228 | #define tcg_gen_deposit_reg tcg_gen_deposit_i32 | |
229 | #define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i32 | |
230 | #define tcg_gen_extract_reg tcg_gen_extract_i32 | |
231 | #define tcg_gen_sextract_reg tcg_gen_sextract_i32 | |
05bfd4db | 232 | #define tcg_gen_extract2_reg tcg_gen_extract2_i32 |
29dd6f64 | 233 | #define tcg_constant_reg tcg_constant_i32 |
eaa3783b RH |
234 | #define tcg_gen_movcond_reg tcg_gen_movcond_i32 |
235 | #define tcg_gen_add2_reg tcg_gen_add2_i32 | |
236 | #define tcg_gen_sub2_reg tcg_gen_sub2_i32 | |
237 | #define tcg_gen_qemu_ld_reg tcg_gen_qemu_ld_i32 | |
238 | #define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i32 | |
239 | #define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i32 | |
5bfa8034 | 240 | #define tcg_gen_trunc_reg_ptr tcg_gen_ext_i32_ptr |
eaa3783b RH |
241 | #endif /* TARGET_REGISTER_BITS */ |
242 | ||
61766fe9 RH |
243 | typedef struct DisasCond { |
244 | TCGCond c; | |
eaa3783b | 245 | TCGv_reg a0, a1; |
61766fe9 RH |
246 | } DisasCond; |
247 | ||
248 | typedef struct DisasContext { | |
d01a3625 | 249 | DisasContextBase base; |
61766fe9 RH |
250 | CPUState *cs; |
251 | ||
eaa3783b RH |
252 | target_ureg iaoq_f; |
253 | target_ureg iaoq_b; | |
254 | target_ureg iaoq_n; | |
255 | TCGv_reg iaoq_n_var; | |
61766fe9 | 256 | |
61766fe9 RH |
257 | DisasCond null_cond; |
258 | TCGLabel *null_lab; | |
259 | ||
1a19da0d | 260 | uint32_t insn; |
494737b7 | 261 | uint32_t tb_flags; |
3d68ee7b RH |
262 | int mmu_idx; |
263 | int privilege; | |
61766fe9 | 264 | bool psw_n_nonzero; |
bd6243a3 | 265 | bool is_pa20; |
217d1a5e RH |
266 | |
267 | #ifdef CONFIG_USER_ONLY | |
268 | MemOp unalign; | |
269 | #endif | |
61766fe9 RH |
270 | } DisasContext; |
271 | ||
217d1a5e RH |
272 | #ifdef CONFIG_USER_ONLY |
273 | #define UNALIGN(C) (C)->unalign | |
274 | #else | |
2d4afb03 | 275 | #define UNALIGN(C) MO_ALIGN |
217d1a5e RH |
276 | #endif |
277 | ||
e36f27ef | 278 | /* Note that ssm/rsm instructions number PSW_W and PSW_E differently. */ |
451e4ffd | 279 | static int expand_sm_imm(DisasContext *ctx, int val) |
e36f27ef RH |
280 | { |
281 | if (val & PSW_SM_E) { | |
282 | val = (val & ~PSW_SM_E) | PSW_E; | |
283 | } | |
284 | if (val & PSW_SM_W) { | |
285 | val = (val & ~PSW_SM_W) | PSW_W; | |
286 | } | |
287 | return val; | |
288 | } | |
289 | ||
deee69a1 | 290 | /* Inverted space register indicates 0 means sr0 not inferred from base. */ |
451e4ffd | 291 | static int expand_sr3x(DisasContext *ctx, int val) |
deee69a1 RH |
292 | { |
293 | return ~val; | |
294 | } | |
295 | ||
1cd012a5 RH |
296 | /* Convert the M:A bits within a memory insn to the tri-state value |
297 | we use for the final M. */ | |
451e4ffd | 298 | static int ma_to_m(DisasContext *ctx, int val) |
1cd012a5 RH |
299 | { |
300 | return val & 2 ? (val & 1 ? -1 : 1) : 0; | |
301 | } | |
302 | ||
740038d7 | 303 | /* Convert the sign of the displacement to a pre or post-modify. */ |
451e4ffd | 304 | static int pos_to_m(DisasContext *ctx, int val) |
740038d7 RH |
305 | { |
306 | return val ? 1 : -1; | |
307 | } | |
308 | ||
451e4ffd | 309 | static int neg_to_m(DisasContext *ctx, int val) |
740038d7 RH |
310 | { |
311 | return val ? -1 : 1; | |
312 | } | |
313 | ||
314 | /* Used for branch targets and fp memory ops. */ | |
451e4ffd | 315 | static int expand_shl2(DisasContext *ctx, int val) |
01afb7be RH |
316 | { |
317 | return val << 2; | |
318 | } | |
319 | ||
740038d7 | 320 | /* Used for fp memory ops. */ |
451e4ffd | 321 | static int expand_shl3(DisasContext *ctx, int val) |
740038d7 RH |
322 | { |
323 | return val << 3; | |
324 | } | |
325 | ||
0588e061 | 326 | /* Used for assemble_21. */ |
451e4ffd | 327 | static int expand_shl11(DisasContext *ctx, int val) |
0588e061 RH |
328 | { |
329 | return val << 11; | |
330 | } | |
331 | ||
72ae4f2b RH |
332 | static int assemble_6(DisasContext *ctx, int val) |
333 | { | |
334 | /* | |
335 | * Officially, 32 * x + 32 - y. | |
336 | * Here, x is already in bit 5, and y is [4:0]. | |
337 | * Since -y = ~y + 1, in 5 bits 32 - y => y ^ 31 + 1, | |
338 | * with the overflow from bit 4 summing with x. | |
339 | */ | |
340 | return (val ^ 31) + 1; | |
341 | } | |
342 | ||
c65c3ee1 RH |
343 | /* Translate CMPI doubleword conditions to standard. */ |
344 | static int cmpbid_c(DisasContext *ctx, int val) | |
345 | { | |
346 | return val ? val : 4; /* 0 == "*<<" */ | |
347 | } | |
348 | ||
01afb7be | 349 | |
40f9f908 | 350 | /* Include the auto-generated decoder. */ |
abff1abf | 351 | #include "decode-insns.c.inc" |
40f9f908 | 352 | |
869051ea RH |
353 | /* We are not using a goto_tb (for whatever reason), but have updated |
354 | the iaq (for whatever reason), so don't do it again on exit. */ | |
355 | #define DISAS_IAQ_N_UPDATED DISAS_TARGET_0 | |
61766fe9 | 356 | |
869051ea RH |
357 | /* We are exiting the TB, but have neither emitted a goto_tb, nor |
358 | updated the iaq for the next instruction to be executed. */ | |
359 | #define DISAS_IAQ_N_STALE DISAS_TARGET_1 | |
61766fe9 | 360 | |
e1b5a5ed RH |
361 | /* Similarly, but we want to return to the main loop immediately |
362 | to recognize unmasked interrupts. */ | |
363 | #define DISAS_IAQ_N_STALE_EXIT DISAS_TARGET_2 | |
c5d0aec2 | 364 | #define DISAS_EXIT DISAS_TARGET_3 |
e1b5a5ed | 365 | |
61766fe9 | 366 | /* global register indexes */ |
eaa3783b | 367 | static TCGv_reg cpu_gr[32]; |
33423472 | 368 | static TCGv_i64 cpu_sr[4]; |
494737b7 | 369 | static TCGv_i64 cpu_srH; |
eaa3783b RH |
370 | static TCGv_reg cpu_iaoq_f; |
371 | static TCGv_reg cpu_iaoq_b; | |
c301f34e RH |
372 | static TCGv_i64 cpu_iasq_f; |
373 | static TCGv_i64 cpu_iasq_b; | |
eaa3783b RH |
374 | static TCGv_reg cpu_sar; |
375 | static TCGv_reg cpu_psw_n; | |
376 | static TCGv_reg cpu_psw_v; | |
377 | static TCGv_reg cpu_psw_cb; | |
378 | static TCGv_reg cpu_psw_cb_msb; | |
61766fe9 | 379 | |
61766fe9 RH |
380 | void hppa_translate_init(void) |
381 | { | |
382 | #define DEF_VAR(V) { &cpu_##V, #V, offsetof(CPUHPPAState, V) } | |
383 | ||
eaa3783b | 384 | typedef struct { TCGv_reg *var; const char *name; int ofs; } GlobalVar; |
61766fe9 | 385 | static const GlobalVar vars[] = { |
35136a77 | 386 | { &cpu_sar, "sar", offsetof(CPUHPPAState, cr[CR_SAR]) }, |
61766fe9 RH |
387 | DEF_VAR(psw_n), |
388 | DEF_VAR(psw_v), | |
389 | DEF_VAR(psw_cb), | |
390 | DEF_VAR(psw_cb_msb), | |
391 | DEF_VAR(iaoq_f), | |
392 | DEF_VAR(iaoq_b), | |
393 | }; | |
394 | ||
395 | #undef DEF_VAR | |
396 | ||
397 | /* Use the symbolic register names that match the disassembler. */ | |
398 | static const char gr_names[32][4] = { | |
399 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
400 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
401 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
402 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | |
403 | }; | |
33423472 | 404 | /* SR[4-7] are not global registers so that we can index them. */ |
494737b7 RH |
405 | static const char sr_names[5][4] = { |
406 | "sr0", "sr1", "sr2", "sr3", "srH" | |
33423472 | 407 | }; |
61766fe9 | 408 | |
61766fe9 RH |
409 | int i; |
410 | ||
f764718d | 411 | cpu_gr[0] = NULL; |
61766fe9 | 412 | for (i = 1; i < 32; i++) { |
ad75a51e | 413 | cpu_gr[i] = tcg_global_mem_new(tcg_env, |
61766fe9 RH |
414 | offsetof(CPUHPPAState, gr[i]), |
415 | gr_names[i]); | |
416 | } | |
33423472 | 417 | for (i = 0; i < 4; i++) { |
ad75a51e | 418 | cpu_sr[i] = tcg_global_mem_new_i64(tcg_env, |
33423472 RH |
419 | offsetof(CPUHPPAState, sr[i]), |
420 | sr_names[i]); | |
421 | } | |
ad75a51e | 422 | cpu_srH = tcg_global_mem_new_i64(tcg_env, |
494737b7 RH |
423 | offsetof(CPUHPPAState, sr[4]), |
424 | sr_names[4]); | |
61766fe9 RH |
425 | |
426 | for (i = 0; i < ARRAY_SIZE(vars); ++i) { | |
427 | const GlobalVar *v = &vars[i]; | |
ad75a51e | 428 | *v->var = tcg_global_mem_new(tcg_env, v->ofs, v->name); |
61766fe9 | 429 | } |
c301f34e | 430 | |
ad75a51e | 431 | cpu_iasq_f = tcg_global_mem_new_i64(tcg_env, |
c301f34e RH |
432 | offsetof(CPUHPPAState, iasq_f), |
433 | "iasq_f"); | |
ad75a51e | 434 | cpu_iasq_b = tcg_global_mem_new_i64(tcg_env, |
c301f34e RH |
435 | offsetof(CPUHPPAState, iasq_b), |
436 | "iasq_b"); | |
61766fe9 RH |
437 | } |
438 | ||
129e9cc3 RH |
439 | static DisasCond cond_make_f(void) |
440 | { | |
f764718d RH |
441 | return (DisasCond){ |
442 | .c = TCG_COND_NEVER, | |
443 | .a0 = NULL, | |
444 | .a1 = NULL, | |
445 | }; | |
129e9cc3 RH |
446 | } |
447 | ||
df0232fe RH |
448 | static DisasCond cond_make_t(void) |
449 | { | |
450 | return (DisasCond){ | |
451 | .c = TCG_COND_ALWAYS, | |
452 | .a0 = NULL, | |
453 | .a1 = NULL, | |
454 | }; | |
455 | } | |
456 | ||
129e9cc3 RH |
457 | static DisasCond cond_make_n(void) |
458 | { | |
f764718d RH |
459 | return (DisasCond){ |
460 | .c = TCG_COND_NE, | |
461 | .a0 = cpu_psw_n, | |
6e94937a | 462 | .a1 = tcg_constant_reg(0) |
f764718d | 463 | }; |
129e9cc3 RH |
464 | } |
465 | ||
4fe9533a | 466 | static DisasCond cond_make_tmp(TCGCond c, TCGv_reg a0, TCGv_reg a1) |
129e9cc3 | 467 | { |
129e9cc3 | 468 | assert (c != TCG_COND_NEVER && c != TCG_COND_ALWAYS); |
4fe9533a RH |
469 | return (DisasCond){ .c = c, .a0 = a0, .a1 = a1 }; |
470 | } | |
471 | ||
472 | static DisasCond cond_make_0_tmp(TCGCond c, TCGv_reg a0) | |
473 | { | |
474 | return cond_make_tmp(c, a0, tcg_constant_reg(0)); | |
b47a4a02 | 475 | } |
129e9cc3 | 476 | |
b47a4a02 SS |
477 | static DisasCond cond_make_0(TCGCond c, TCGv_reg a0) |
478 | { | |
479 | TCGv_reg tmp = tcg_temp_new(); | |
480 | tcg_gen_mov_reg(tmp, a0); | |
481 | return cond_make_0_tmp(c, tmp); | |
129e9cc3 RH |
482 | } |
483 | ||
eaa3783b | 484 | static DisasCond cond_make(TCGCond c, TCGv_reg a0, TCGv_reg a1) |
129e9cc3 | 485 | { |
4fe9533a RH |
486 | TCGv_reg t0 = tcg_temp_new(); |
487 | TCGv_reg t1 = tcg_temp_new(); | |
129e9cc3 | 488 | |
4fe9533a RH |
489 | tcg_gen_mov_reg(t0, a0); |
490 | tcg_gen_mov_reg(t1, a1); | |
491 | return cond_make_tmp(c, t0, t1); | |
129e9cc3 RH |
492 | } |
493 | ||
129e9cc3 RH |
494 | static void cond_free(DisasCond *cond) |
495 | { | |
496 | switch (cond->c) { | |
497 | default: | |
f764718d RH |
498 | cond->a0 = NULL; |
499 | cond->a1 = NULL; | |
129e9cc3 RH |
500 | /* fallthru */ |
501 | case TCG_COND_ALWAYS: | |
502 | cond->c = TCG_COND_NEVER; | |
503 | break; | |
504 | case TCG_COND_NEVER: | |
505 | break; | |
506 | } | |
507 | } | |
508 | ||
eaa3783b | 509 | static TCGv_reg load_gpr(DisasContext *ctx, unsigned reg) |
61766fe9 RH |
510 | { |
511 | if (reg == 0) { | |
e12c6309 | 512 | TCGv_reg t = tcg_temp_new(); |
eaa3783b | 513 | tcg_gen_movi_reg(t, 0); |
61766fe9 RH |
514 | return t; |
515 | } else { | |
516 | return cpu_gr[reg]; | |
517 | } | |
518 | } | |
519 | ||
eaa3783b | 520 | static TCGv_reg dest_gpr(DisasContext *ctx, unsigned reg) |
61766fe9 | 521 | { |
129e9cc3 | 522 | if (reg == 0 || ctx->null_cond.c != TCG_COND_NEVER) { |
e12c6309 | 523 | return tcg_temp_new(); |
61766fe9 RH |
524 | } else { |
525 | return cpu_gr[reg]; | |
526 | } | |
527 | } | |
528 | ||
eaa3783b | 529 | static void save_or_nullify(DisasContext *ctx, TCGv_reg dest, TCGv_reg t) |
129e9cc3 RH |
530 | { |
531 | if (ctx->null_cond.c != TCG_COND_NEVER) { | |
eaa3783b | 532 | tcg_gen_movcond_reg(ctx->null_cond.c, dest, ctx->null_cond.a0, |
6e94937a | 533 | ctx->null_cond.a1, dest, t); |
129e9cc3 | 534 | } else { |
eaa3783b | 535 | tcg_gen_mov_reg(dest, t); |
129e9cc3 RH |
536 | } |
537 | } | |
538 | ||
eaa3783b | 539 | static void save_gpr(DisasContext *ctx, unsigned reg, TCGv_reg t) |
129e9cc3 RH |
540 | { |
541 | if (reg != 0) { | |
542 | save_or_nullify(ctx, cpu_gr[reg], t); | |
543 | } | |
544 | } | |
545 | ||
e03b5686 | 546 | #if HOST_BIG_ENDIAN |
96d6407f RH |
547 | # define HI_OFS 0 |
548 | # define LO_OFS 4 | |
549 | #else | |
550 | # define HI_OFS 4 | |
551 | # define LO_OFS 0 | |
552 | #endif | |
553 | ||
554 | static TCGv_i32 load_frw_i32(unsigned rt) | |
555 | { | |
556 | TCGv_i32 ret = tcg_temp_new_i32(); | |
ad75a51e | 557 | tcg_gen_ld_i32(ret, tcg_env, |
96d6407f RH |
558 | offsetof(CPUHPPAState, fr[rt & 31]) |
559 | + (rt & 32 ? LO_OFS : HI_OFS)); | |
560 | return ret; | |
561 | } | |
562 | ||
ebe9383c RH |
563 | static TCGv_i32 load_frw0_i32(unsigned rt) |
564 | { | |
565 | if (rt == 0) { | |
0992a930 RH |
566 | TCGv_i32 ret = tcg_temp_new_i32(); |
567 | tcg_gen_movi_i32(ret, 0); | |
568 | return ret; | |
ebe9383c RH |
569 | } else { |
570 | return load_frw_i32(rt); | |
571 | } | |
572 | } | |
573 | ||
574 | static TCGv_i64 load_frw0_i64(unsigned rt) | |
575 | { | |
0992a930 | 576 | TCGv_i64 ret = tcg_temp_new_i64(); |
ebe9383c | 577 | if (rt == 0) { |
0992a930 | 578 | tcg_gen_movi_i64(ret, 0); |
ebe9383c | 579 | } else { |
ad75a51e | 580 | tcg_gen_ld32u_i64(ret, tcg_env, |
ebe9383c RH |
581 | offsetof(CPUHPPAState, fr[rt & 31]) |
582 | + (rt & 32 ? LO_OFS : HI_OFS)); | |
ebe9383c | 583 | } |
0992a930 | 584 | return ret; |
ebe9383c RH |
585 | } |
586 | ||
96d6407f RH |
587 | static void save_frw_i32(unsigned rt, TCGv_i32 val) |
588 | { | |
ad75a51e | 589 | tcg_gen_st_i32(val, tcg_env, |
96d6407f RH |
590 | offsetof(CPUHPPAState, fr[rt & 31]) |
591 | + (rt & 32 ? LO_OFS : HI_OFS)); | |
592 | } | |
593 | ||
594 | #undef HI_OFS | |
595 | #undef LO_OFS | |
596 | ||
597 | static TCGv_i64 load_frd(unsigned rt) | |
598 | { | |
599 | TCGv_i64 ret = tcg_temp_new_i64(); | |
ad75a51e | 600 | tcg_gen_ld_i64(ret, tcg_env, offsetof(CPUHPPAState, fr[rt])); |
96d6407f RH |
601 | return ret; |
602 | } | |
603 | ||
ebe9383c RH |
604 | static TCGv_i64 load_frd0(unsigned rt) |
605 | { | |
606 | if (rt == 0) { | |
0992a930 RH |
607 | TCGv_i64 ret = tcg_temp_new_i64(); |
608 | tcg_gen_movi_i64(ret, 0); | |
609 | return ret; | |
ebe9383c RH |
610 | } else { |
611 | return load_frd(rt); | |
612 | } | |
613 | } | |
614 | ||
96d6407f RH |
615 | static void save_frd(unsigned rt, TCGv_i64 val) |
616 | { | |
ad75a51e | 617 | tcg_gen_st_i64(val, tcg_env, offsetof(CPUHPPAState, fr[rt])); |
96d6407f RH |
618 | } |
619 | ||
33423472 RH |
620 | static void load_spr(DisasContext *ctx, TCGv_i64 dest, unsigned reg) |
621 | { | |
622 | #ifdef CONFIG_USER_ONLY | |
623 | tcg_gen_movi_i64(dest, 0); | |
624 | #else | |
625 | if (reg < 4) { | |
626 | tcg_gen_mov_i64(dest, cpu_sr[reg]); | |
494737b7 RH |
627 | } else if (ctx->tb_flags & TB_FLAG_SR_SAME) { |
628 | tcg_gen_mov_i64(dest, cpu_srH); | |
33423472 | 629 | } else { |
ad75a51e | 630 | tcg_gen_ld_i64(dest, tcg_env, offsetof(CPUHPPAState, sr[reg])); |
33423472 RH |
631 | } |
632 | #endif | |
633 | } | |
634 | ||
129e9cc3 RH |
635 | /* Skip over the implementation of an insn that has been nullified. |
636 | Use this when the insn is too complex for a conditional move. */ | |
637 | static void nullify_over(DisasContext *ctx) | |
638 | { | |
639 | if (ctx->null_cond.c != TCG_COND_NEVER) { | |
640 | /* The always condition should have been handled in the main loop. */ | |
641 | assert(ctx->null_cond.c != TCG_COND_ALWAYS); | |
642 | ||
643 | ctx->null_lab = gen_new_label(); | |
129e9cc3 RH |
644 | |
645 | /* If we're using PSW[N], copy it to a temp because... */ | |
6e94937a | 646 | if (ctx->null_cond.a0 == cpu_psw_n) { |
129e9cc3 | 647 | ctx->null_cond.a0 = tcg_temp_new(); |
eaa3783b | 648 | tcg_gen_mov_reg(ctx->null_cond.a0, cpu_psw_n); |
129e9cc3 RH |
649 | } |
650 | /* ... we clear it before branching over the implementation, | |
651 | so that (1) it's clear after nullifying this insn and | |
652 | (2) if this insn nullifies the next, PSW[N] is valid. */ | |
653 | if (ctx->psw_n_nonzero) { | |
654 | ctx->psw_n_nonzero = false; | |
eaa3783b | 655 | tcg_gen_movi_reg(cpu_psw_n, 0); |
129e9cc3 RH |
656 | } |
657 | ||
eaa3783b | 658 | tcg_gen_brcond_reg(ctx->null_cond.c, ctx->null_cond.a0, |
6e94937a | 659 | ctx->null_cond.a1, ctx->null_lab); |
129e9cc3 RH |
660 | cond_free(&ctx->null_cond); |
661 | } | |
662 | } | |
663 | ||
664 | /* Save the current nullification state to PSW[N]. */ | |
665 | static void nullify_save(DisasContext *ctx) | |
666 | { | |
667 | if (ctx->null_cond.c == TCG_COND_NEVER) { | |
668 | if (ctx->psw_n_nonzero) { | |
eaa3783b | 669 | tcg_gen_movi_reg(cpu_psw_n, 0); |
129e9cc3 RH |
670 | } |
671 | return; | |
672 | } | |
6e94937a | 673 | if (ctx->null_cond.a0 != cpu_psw_n) { |
eaa3783b | 674 | tcg_gen_setcond_reg(ctx->null_cond.c, cpu_psw_n, |
6e94937a | 675 | ctx->null_cond.a0, ctx->null_cond.a1); |
129e9cc3 RH |
676 | ctx->psw_n_nonzero = true; |
677 | } | |
678 | cond_free(&ctx->null_cond); | |
679 | } | |
680 | ||
681 | /* Set a PSW[N] to X. The intention is that this is used immediately | |
682 | before a goto_tb/exit_tb, so that there is no fallthru path to other | |
683 | code within the TB. Therefore we do not update psw_n_nonzero. */ | |
684 | static void nullify_set(DisasContext *ctx, bool x) | |
685 | { | |
686 | if (ctx->psw_n_nonzero || x) { | |
eaa3783b | 687 | tcg_gen_movi_reg(cpu_psw_n, x); |
129e9cc3 RH |
688 | } |
689 | } | |
690 | ||
691 | /* Mark the end of an instruction that may have been nullified. | |
40f9f908 RH |
692 | This is the pair to nullify_over. Always returns true so that |
693 | it may be tail-called from a translate function. */ | |
31234768 | 694 | static bool nullify_end(DisasContext *ctx) |
129e9cc3 RH |
695 | { |
696 | TCGLabel *null_lab = ctx->null_lab; | |
31234768 | 697 | DisasJumpType status = ctx->base.is_jmp; |
129e9cc3 | 698 | |
f49b3537 RH |
699 | /* For NEXT, NORETURN, STALE, we can easily continue (or exit). |
700 | For UPDATED, we cannot update on the nullified path. */ | |
701 | assert(status != DISAS_IAQ_N_UPDATED); | |
702 | ||
129e9cc3 RH |
703 | if (likely(null_lab == NULL)) { |
704 | /* The current insn wasn't conditional or handled the condition | |
705 | applied to it without a branch, so the (new) setting of | |
706 | NULL_COND can be applied directly to the next insn. */ | |
31234768 | 707 | return true; |
129e9cc3 RH |
708 | } |
709 | ctx->null_lab = NULL; | |
710 | ||
711 | if (likely(ctx->null_cond.c == TCG_COND_NEVER)) { | |
712 | /* The next instruction will be unconditional, | |
713 | and NULL_COND already reflects that. */ | |
714 | gen_set_label(null_lab); | |
715 | } else { | |
716 | /* The insn that we just executed is itself nullifying the next | |
717 | instruction. Store the condition in the PSW[N] global. | |
718 | We asserted PSW[N] = 0 in nullify_over, so that after the | |
719 | label we have the proper value in place. */ | |
720 | nullify_save(ctx); | |
721 | gen_set_label(null_lab); | |
722 | ctx->null_cond = cond_make_n(); | |
723 | } | |
869051ea | 724 | if (status == DISAS_NORETURN) { |
31234768 | 725 | ctx->base.is_jmp = DISAS_NEXT; |
129e9cc3 | 726 | } |
31234768 | 727 | return true; |
129e9cc3 RH |
728 | } |
729 | ||
698240d1 RH |
730 | static target_ureg gva_offset_mask(DisasContext *ctx) |
731 | { | |
732 | return (ctx->tb_flags & PSW_W | |
733 | ? MAKE_64BIT_MASK(0, 62) | |
734 | : MAKE_64BIT_MASK(0, 32)); | |
735 | } | |
736 | ||
741322f4 RH |
737 | static void copy_iaoq_entry(DisasContext *ctx, TCGv_reg dest, |
738 | target_ureg ival, TCGv_reg vval) | |
61766fe9 | 739 | { |
f13bf343 RH |
740 | target_ureg mask = gva_offset_mask(ctx); |
741 | ||
742 | if (ival != -1) { | |
743 | tcg_gen_movi_reg(dest, ival & mask); | |
744 | return; | |
745 | } | |
746 | tcg_debug_assert(vval != NULL); | |
747 | ||
748 | /* | |
749 | * We know that the IAOQ is already properly masked. | |
750 | * This optimization is primarily for "iaoq_f = iaoq_b". | |
751 | */ | |
752 | if (vval == cpu_iaoq_f || vval == cpu_iaoq_b) { | |
eaa3783b | 753 | tcg_gen_mov_reg(dest, vval); |
61766fe9 | 754 | } else { |
f13bf343 | 755 | tcg_gen_andi_reg(dest, vval, mask); |
61766fe9 RH |
756 | } |
757 | } | |
758 | ||
eaa3783b | 759 | static inline target_ureg iaoq_dest(DisasContext *ctx, target_sreg disp) |
61766fe9 RH |
760 | { |
761 | return ctx->iaoq_f + disp + 8; | |
762 | } | |
763 | ||
764 | static void gen_excp_1(int exception) | |
765 | { | |
ad75a51e | 766 | gen_helper_excp(tcg_env, tcg_constant_i32(exception)); |
61766fe9 RH |
767 | } |
768 | ||
31234768 | 769 | static void gen_excp(DisasContext *ctx, int exception) |
61766fe9 | 770 | { |
741322f4 RH |
771 | copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_f, cpu_iaoq_f); |
772 | copy_iaoq_entry(ctx, cpu_iaoq_b, ctx->iaoq_b, cpu_iaoq_b); | |
129e9cc3 | 773 | nullify_save(ctx); |
61766fe9 | 774 | gen_excp_1(exception); |
31234768 | 775 | ctx->base.is_jmp = DISAS_NORETURN; |
61766fe9 RH |
776 | } |
777 | ||
31234768 | 778 | static bool gen_excp_iir(DisasContext *ctx, int exc) |
1a19da0d | 779 | { |
31234768 | 780 | nullify_over(ctx); |
29dd6f64 | 781 | tcg_gen_st_reg(tcg_constant_reg(ctx->insn), |
ad75a51e | 782 | tcg_env, offsetof(CPUHPPAState, cr[CR_IIR])); |
31234768 RH |
783 | gen_excp(ctx, exc); |
784 | return nullify_end(ctx); | |
1a19da0d RH |
785 | } |
786 | ||
31234768 | 787 | static bool gen_illegal(DisasContext *ctx) |
61766fe9 | 788 | { |
31234768 | 789 | return gen_excp_iir(ctx, EXCP_ILL); |
61766fe9 RH |
790 | } |
791 | ||
40f9f908 RH |
792 | #ifdef CONFIG_USER_ONLY |
793 | #define CHECK_MOST_PRIVILEGED(EXCP) \ | |
794 | return gen_excp_iir(ctx, EXCP) | |
795 | #else | |
796 | #define CHECK_MOST_PRIVILEGED(EXCP) \ | |
31234768 RH |
797 | do { \ |
798 | if (ctx->privilege != 0) { \ | |
799 | return gen_excp_iir(ctx, EXCP); \ | |
800 | } \ | |
e1b5a5ed | 801 | } while (0) |
40f9f908 | 802 | #endif |
e1b5a5ed | 803 | |
eaa3783b | 804 | static bool use_goto_tb(DisasContext *ctx, target_ureg dest) |
61766fe9 | 805 | { |
57f91498 | 806 | return translator_use_goto_tb(&ctx->base, dest); |
61766fe9 RH |
807 | } |
808 | ||
129e9cc3 RH |
809 | /* If the next insn is to be nullified, and it's on the same page, |
810 | and we're not attempting to set a breakpoint on it, then we can | |
811 | totally skip the nullified insn. This avoids creating and | |
812 | executing a TB that merely branches to the next TB. */ | |
813 | static bool use_nullify_skip(DisasContext *ctx) | |
814 | { | |
815 | return (((ctx->iaoq_b ^ ctx->iaoq_f) & TARGET_PAGE_MASK) == 0 | |
816 | && !cpu_breakpoint_test(ctx->cs, ctx->iaoq_b, BP_ANY)); | |
817 | } | |
818 | ||
61766fe9 | 819 | static void gen_goto_tb(DisasContext *ctx, int which, |
eaa3783b | 820 | target_ureg f, target_ureg b) |
61766fe9 RH |
821 | { |
822 | if (f != -1 && b != -1 && use_goto_tb(ctx, f)) { | |
823 | tcg_gen_goto_tb(which); | |
a0180973 RH |
824 | copy_iaoq_entry(ctx, cpu_iaoq_f, f, NULL); |
825 | copy_iaoq_entry(ctx, cpu_iaoq_b, b, NULL); | |
07ea28b4 | 826 | tcg_gen_exit_tb(ctx->base.tb, which); |
61766fe9 | 827 | } else { |
741322f4 RH |
828 | copy_iaoq_entry(ctx, cpu_iaoq_f, f, cpu_iaoq_b); |
829 | copy_iaoq_entry(ctx, cpu_iaoq_b, b, ctx->iaoq_n_var); | |
8532a14e | 830 | tcg_gen_lookup_and_goto_ptr(); |
61766fe9 RH |
831 | } |
832 | } | |
833 | ||
b47a4a02 SS |
834 | static bool cond_need_sv(int c) |
835 | { | |
836 | return c == 2 || c == 3 || c == 6; | |
837 | } | |
838 | ||
839 | static bool cond_need_cb(int c) | |
840 | { | |
841 | return c == 4 || c == 5; | |
842 | } | |
843 | ||
72ca8753 RH |
844 | /* Need extensions from TCGv_i32 to TCGv_reg. */ |
845 | static bool cond_need_ext(DisasContext *ctx, bool d) | |
846 | { | |
a751eb31 | 847 | return TARGET_REGISTER_BITS == 64 && !(ctx->is_pa20 && d); |
72ca8753 RH |
848 | } |
849 | ||
b47a4a02 SS |
850 | /* |
851 | * Compute conditional for arithmetic. See Page 5-3, Table 5-1, of | |
852 | * the Parisc 1.1 Architecture Reference Manual for details. | |
853 | */ | |
b2167459 | 854 | |
a751eb31 RH |
855 | static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, |
856 | TCGv_reg res, TCGv_reg cb_msb, TCGv_reg sv) | |
b2167459 RH |
857 | { |
858 | DisasCond cond; | |
eaa3783b | 859 | TCGv_reg tmp; |
b2167459 RH |
860 | |
861 | switch (cf >> 1) { | |
b47a4a02 | 862 | case 0: /* Never / TR (0 / 1) */ |
b2167459 RH |
863 | cond = cond_make_f(); |
864 | break; | |
865 | case 1: /* = / <> (Z / !Z) */ | |
a751eb31 RH |
866 | if (cond_need_ext(ctx, d)) { |
867 | tmp = tcg_temp_new(); | |
868 | tcg_gen_ext32u_reg(tmp, res); | |
869 | res = tmp; | |
870 | } | |
b2167459 RH |
871 | cond = cond_make_0(TCG_COND_EQ, res); |
872 | break; | |
b47a4a02 SS |
873 | case 2: /* < / >= (N ^ V / !(N ^ V) */ |
874 | tmp = tcg_temp_new(); | |
875 | tcg_gen_xor_reg(tmp, res, sv); | |
a751eb31 RH |
876 | if (cond_need_ext(ctx, d)) { |
877 | tcg_gen_ext32s_reg(tmp, tmp); | |
878 | } | |
b47a4a02 | 879 | cond = cond_make_0_tmp(TCG_COND_LT, tmp); |
b2167459 | 880 | break; |
b47a4a02 SS |
881 | case 3: /* <= / > (N ^ V) | Z / !((N ^ V) | Z) */ |
882 | /* | |
883 | * Simplify: | |
884 | * (N ^ V) | Z | |
885 | * ((res < 0) ^ (sv < 0)) | !res | |
886 | * ((res ^ sv) < 0) | !res | |
887 | * (~(res ^ sv) >= 0) | !res | |
888 | * !(~(res ^ sv) >> 31) | !res | |
889 | * !(~(res ^ sv) >> 31 & res) | |
890 | */ | |
891 | tmp = tcg_temp_new(); | |
892 | tcg_gen_eqv_reg(tmp, res, sv); | |
a751eb31 RH |
893 | if (cond_need_ext(ctx, d)) { |
894 | tcg_gen_sextract_reg(tmp, tmp, 31, 1); | |
895 | tcg_gen_and_reg(tmp, tmp, res); | |
896 | tcg_gen_ext32u_reg(tmp, tmp); | |
897 | } else { | |
898 | tcg_gen_sari_reg(tmp, tmp, TARGET_REGISTER_BITS - 1); | |
899 | tcg_gen_and_reg(tmp, tmp, res); | |
900 | } | |
b47a4a02 | 901 | cond = cond_make_0_tmp(TCG_COND_EQ, tmp); |
b2167459 RH |
902 | break; |
903 | case 4: /* NUV / UV (!C / C) */ | |
a751eb31 | 904 | /* Only bit 0 of cb_msb is ever set. */ |
b2167459 RH |
905 | cond = cond_make_0(TCG_COND_EQ, cb_msb); |
906 | break; | |
907 | case 5: /* ZNV / VNZ (!C | Z / C & !Z) */ | |
908 | tmp = tcg_temp_new(); | |
eaa3783b RH |
909 | tcg_gen_neg_reg(tmp, cb_msb); |
910 | tcg_gen_and_reg(tmp, tmp, res); | |
a751eb31 RH |
911 | if (cond_need_ext(ctx, d)) { |
912 | tcg_gen_ext32u_reg(tmp, tmp); | |
913 | } | |
b47a4a02 | 914 | cond = cond_make_0_tmp(TCG_COND_EQ, tmp); |
b2167459 RH |
915 | break; |
916 | case 6: /* SV / NSV (V / !V) */ | |
a751eb31 RH |
917 | if (cond_need_ext(ctx, d)) { |
918 | tmp = tcg_temp_new(); | |
919 | tcg_gen_ext32s_reg(tmp, sv); | |
920 | sv = tmp; | |
921 | } | |
b2167459 RH |
922 | cond = cond_make_0(TCG_COND_LT, sv); |
923 | break; | |
924 | case 7: /* OD / EV */ | |
925 | tmp = tcg_temp_new(); | |
eaa3783b | 926 | tcg_gen_andi_reg(tmp, res, 1); |
b47a4a02 | 927 | cond = cond_make_0_tmp(TCG_COND_NE, tmp); |
b2167459 RH |
928 | break; |
929 | default: | |
930 | g_assert_not_reached(); | |
931 | } | |
932 | if (cf & 1) { | |
933 | cond.c = tcg_invert_cond(cond.c); | |
934 | } | |
935 | ||
936 | return cond; | |
937 | } | |
938 | ||
939 | /* Similar, but for the special case of subtraction without borrow, we | |
940 | can use the inputs directly. This can allow other computation to be | |
941 | deleted as unused. */ | |
942 | ||
4fe9533a RH |
943 | static DisasCond do_sub_cond(DisasContext *ctx, unsigned cf, bool d, |
944 | TCGv_reg res, TCGv_reg in1, | |
945 | TCGv_reg in2, TCGv_reg sv) | |
b2167459 | 946 | { |
4fe9533a RH |
947 | TCGCond tc; |
948 | bool ext_uns; | |
b2167459 RH |
949 | |
950 | switch (cf >> 1) { | |
951 | case 1: /* = / <> */ | |
4fe9533a RH |
952 | tc = TCG_COND_EQ; |
953 | ext_uns = true; | |
b2167459 RH |
954 | break; |
955 | case 2: /* < / >= */ | |
4fe9533a RH |
956 | tc = TCG_COND_LT; |
957 | ext_uns = false; | |
b2167459 RH |
958 | break; |
959 | case 3: /* <= / > */ | |
4fe9533a RH |
960 | tc = TCG_COND_LE; |
961 | ext_uns = false; | |
b2167459 RH |
962 | break; |
963 | case 4: /* << / >>= */ | |
4fe9533a RH |
964 | tc = TCG_COND_LTU; |
965 | ext_uns = true; | |
b2167459 RH |
966 | break; |
967 | case 5: /* <<= / >> */ | |
4fe9533a RH |
968 | tc = TCG_COND_LEU; |
969 | ext_uns = true; | |
b2167459 RH |
970 | break; |
971 | default: | |
a751eb31 | 972 | return do_cond(ctx, cf, d, res, NULL, sv); |
b2167459 | 973 | } |
4fe9533a | 974 | |
b2167459 | 975 | if (cf & 1) { |
4fe9533a | 976 | tc = tcg_invert_cond(tc); |
b2167459 | 977 | } |
4fe9533a RH |
978 | if (cond_need_ext(ctx, d)) { |
979 | TCGv_reg t1 = tcg_temp_new(); | |
980 | TCGv_reg t2 = tcg_temp_new(); | |
b2167459 | 981 | |
4fe9533a RH |
982 | if (ext_uns) { |
983 | tcg_gen_ext32u_reg(t1, in1); | |
984 | tcg_gen_ext32u_reg(t2, in2); | |
985 | } else { | |
986 | tcg_gen_ext32s_reg(t1, in1); | |
987 | tcg_gen_ext32s_reg(t2, in2); | |
988 | } | |
989 | return cond_make_tmp(tc, t1, t2); | |
990 | } | |
991 | return cond_make(tc, in1, in2); | |
b2167459 RH |
992 | } |
993 | ||
df0232fe RH |
994 | /* |
995 | * Similar, but for logicals, where the carry and overflow bits are not | |
996 | * computed, and use of them is undefined. | |
997 | * | |
998 | * Undefined or not, hardware does not trap. It seems reasonable to | |
999 | * assume hardware treats cases c={4,5,6} as if C=0 & V=0, since that's | |
1000 | * how cases c={2,3} are treated. | |
1001 | */ | |
b2167459 | 1002 | |
b5af8423 RH |
1003 | static DisasCond do_log_cond(DisasContext *ctx, unsigned cf, bool d, |
1004 | TCGv_reg res) | |
b2167459 | 1005 | { |
b5af8423 RH |
1006 | TCGCond tc; |
1007 | bool ext_uns; | |
a751eb31 | 1008 | |
df0232fe RH |
1009 | switch (cf) { |
1010 | case 0: /* never */ | |
1011 | case 9: /* undef, C */ | |
1012 | case 11: /* undef, C & !Z */ | |
1013 | case 12: /* undef, V */ | |
1014 | return cond_make_f(); | |
1015 | ||
1016 | case 1: /* true */ | |
1017 | case 8: /* undef, !C */ | |
1018 | case 10: /* undef, !C | Z */ | |
1019 | case 13: /* undef, !V */ | |
1020 | return cond_make_t(); | |
1021 | ||
1022 | case 2: /* == */ | |
b5af8423 RH |
1023 | tc = TCG_COND_EQ; |
1024 | ext_uns = true; | |
1025 | break; | |
df0232fe | 1026 | case 3: /* <> */ |
b5af8423 RH |
1027 | tc = TCG_COND_NE; |
1028 | ext_uns = true; | |
1029 | break; | |
df0232fe | 1030 | case 4: /* < */ |
b5af8423 RH |
1031 | tc = TCG_COND_LT; |
1032 | ext_uns = false; | |
1033 | break; | |
df0232fe | 1034 | case 5: /* >= */ |
b5af8423 RH |
1035 | tc = TCG_COND_GE; |
1036 | ext_uns = false; | |
1037 | break; | |
df0232fe | 1038 | case 6: /* <= */ |
b5af8423 RH |
1039 | tc = TCG_COND_LE; |
1040 | ext_uns = false; | |
1041 | break; | |
df0232fe | 1042 | case 7: /* > */ |
b5af8423 RH |
1043 | tc = TCG_COND_GT; |
1044 | ext_uns = false; | |
1045 | break; | |
df0232fe RH |
1046 | |
1047 | case 14: /* OD */ | |
1048 | case 15: /* EV */ | |
a751eb31 | 1049 | return do_cond(ctx, cf, d, res, NULL, NULL); |
df0232fe RH |
1050 | |
1051 | default: | |
1052 | g_assert_not_reached(); | |
b2167459 | 1053 | } |
b5af8423 RH |
1054 | |
1055 | if (cond_need_ext(ctx, d)) { | |
1056 | TCGv_reg tmp = tcg_temp_new(); | |
1057 | ||
1058 | if (ext_uns) { | |
1059 | tcg_gen_ext32u_reg(tmp, res); | |
1060 | } else { | |
1061 | tcg_gen_ext32s_reg(tmp, res); | |
1062 | } | |
1063 | return cond_make_0_tmp(tc, tmp); | |
1064 | } | |
1065 | return cond_make_0(tc, res); | |
b2167459 RH |
1066 | } |
1067 | ||
98cd9ca7 RH |
1068 | /* Similar, but for shift/extract/deposit conditions. */ |
1069 | ||
4fa52edf RH |
1070 | static DisasCond do_sed_cond(DisasContext *ctx, unsigned orig, bool d, |
1071 | TCGv_reg res) | |
98cd9ca7 RH |
1072 | { |
1073 | unsigned c, f; | |
1074 | ||
1075 | /* Convert the compressed condition codes to standard. | |
1076 | 0-2 are the same as logicals (nv,<,<=), while 3 is OD. | |
1077 | 4-7 are the reverse of 0-3. */ | |
1078 | c = orig & 3; | |
1079 | if (c == 3) { | |
1080 | c = 7; | |
1081 | } | |
1082 | f = (orig & 4) / 4; | |
1083 | ||
b5af8423 | 1084 | return do_log_cond(ctx, c * 2 + f, d, res); |
98cd9ca7 RH |
1085 | } |
1086 | ||
b2167459 RH |
1087 | /* Similar, but for unit conditions. */ |
1088 | ||
59963d8f | 1089 | static DisasCond do_unit_cond(unsigned cf, bool d, TCGv_reg res, |
eaa3783b | 1090 | TCGv_reg in1, TCGv_reg in2) |
b2167459 RH |
1091 | { |
1092 | DisasCond cond; | |
eaa3783b | 1093 | TCGv_reg tmp, cb = NULL; |
59963d8f | 1094 | target_ureg d_repl = d ? 0x0000000100000001ull : 1; |
b2167459 | 1095 | |
b2167459 RH |
1096 | if (cf & 8) { |
1097 | /* Since we want to test lots of carry-out bits all at once, do not | |
1098 | * do our normal thing and compute carry-in of bit B+1 since that | |
1099 | * leaves us with carry bits spread across two words. | |
1100 | */ | |
1101 | cb = tcg_temp_new(); | |
1102 | tmp = tcg_temp_new(); | |
eaa3783b RH |
1103 | tcg_gen_or_reg(cb, in1, in2); |
1104 | tcg_gen_and_reg(tmp, in1, in2); | |
1105 | tcg_gen_andc_reg(cb, cb, res); | |
1106 | tcg_gen_or_reg(cb, cb, tmp); | |
b2167459 RH |
1107 | } |
1108 | ||
1109 | switch (cf >> 1) { | |
1110 | case 0: /* never / TR */ | |
1111 | case 1: /* undefined */ | |
1112 | case 5: /* undefined */ | |
1113 | cond = cond_make_f(); | |
1114 | break; | |
1115 | ||
1116 | case 2: /* SBZ / NBZ */ | |
1117 | /* See hasless(v,1) from | |
1118 | * https://graphics.stanford.edu/~seander/bithacks.html#ZeroInWord | |
1119 | */ | |
1120 | tmp = tcg_temp_new(); | |
59963d8f | 1121 | tcg_gen_subi_reg(tmp, res, d_repl * 0x01010101u); |
eaa3783b | 1122 | tcg_gen_andc_reg(tmp, tmp, res); |
59963d8f | 1123 | tcg_gen_andi_reg(tmp, tmp, d_repl * 0x80808080u); |
b2167459 | 1124 | cond = cond_make_0(TCG_COND_NE, tmp); |
b2167459 RH |
1125 | break; |
1126 | ||
1127 | case 3: /* SHZ / NHZ */ | |
1128 | tmp = tcg_temp_new(); | |
59963d8f | 1129 | tcg_gen_subi_reg(tmp, res, d_repl * 0x00010001u); |
eaa3783b | 1130 | tcg_gen_andc_reg(tmp, tmp, res); |
59963d8f | 1131 | tcg_gen_andi_reg(tmp, tmp, d_repl * 0x80008000u); |
b2167459 | 1132 | cond = cond_make_0(TCG_COND_NE, tmp); |
b2167459 RH |
1133 | break; |
1134 | ||
1135 | case 4: /* SDC / NDC */ | |
59963d8f | 1136 | tcg_gen_andi_reg(cb, cb, d_repl * 0x88888888u); |
b2167459 RH |
1137 | cond = cond_make_0(TCG_COND_NE, cb); |
1138 | break; | |
1139 | ||
1140 | case 6: /* SBC / NBC */ | |
59963d8f | 1141 | tcg_gen_andi_reg(cb, cb, d_repl * 0x80808080u); |
b2167459 RH |
1142 | cond = cond_make_0(TCG_COND_NE, cb); |
1143 | break; | |
1144 | ||
1145 | case 7: /* SHC / NHC */ | |
59963d8f | 1146 | tcg_gen_andi_reg(cb, cb, d_repl * 0x80008000u); |
b2167459 RH |
1147 | cond = cond_make_0(TCG_COND_NE, cb); |
1148 | break; | |
1149 | ||
1150 | default: | |
1151 | g_assert_not_reached(); | |
1152 | } | |
b2167459 RH |
1153 | if (cf & 1) { |
1154 | cond.c = tcg_invert_cond(cond.c); | |
1155 | } | |
1156 | ||
1157 | return cond; | |
1158 | } | |
1159 | ||
72ca8753 RH |
1160 | static TCGv_reg get_carry(DisasContext *ctx, bool d, |
1161 | TCGv_reg cb, TCGv_reg cb_msb) | |
1162 | { | |
1163 | if (cond_need_ext(ctx, d)) { | |
1164 | TCGv_reg t = tcg_temp_new(); | |
1165 | tcg_gen_extract_reg(t, cb, 32, 1); | |
1166 | return t; | |
1167 | } | |
1168 | return cb_msb; | |
1169 | } | |
1170 | ||
1171 | static TCGv_reg get_psw_carry(DisasContext *ctx, bool d) | |
1172 | { | |
1173 | return get_carry(ctx, d, cpu_psw_cb, cpu_psw_cb_msb); | |
1174 | } | |
1175 | ||
b2167459 | 1176 | /* Compute signed overflow for addition. */ |
eaa3783b RH |
1177 | static TCGv_reg do_add_sv(DisasContext *ctx, TCGv_reg res, |
1178 | TCGv_reg in1, TCGv_reg in2) | |
b2167459 | 1179 | { |
e12c6309 | 1180 | TCGv_reg sv = tcg_temp_new(); |
eaa3783b | 1181 | TCGv_reg tmp = tcg_temp_new(); |
b2167459 | 1182 | |
eaa3783b RH |
1183 | tcg_gen_xor_reg(sv, res, in1); |
1184 | tcg_gen_xor_reg(tmp, in1, in2); | |
1185 | tcg_gen_andc_reg(sv, sv, tmp); | |
b2167459 RH |
1186 | |
1187 | return sv; | |
1188 | } | |
1189 | ||
1190 | /* Compute signed overflow for subtraction. */ | |
eaa3783b RH |
1191 | static TCGv_reg do_sub_sv(DisasContext *ctx, TCGv_reg res, |
1192 | TCGv_reg in1, TCGv_reg in2) | |
b2167459 | 1193 | { |
e12c6309 | 1194 | TCGv_reg sv = tcg_temp_new(); |
eaa3783b | 1195 | TCGv_reg tmp = tcg_temp_new(); |
b2167459 | 1196 | |
eaa3783b RH |
1197 | tcg_gen_xor_reg(sv, res, in1); |
1198 | tcg_gen_xor_reg(tmp, in1, in2); | |
1199 | tcg_gen_and_reg(sv, sv, tmp); | |
b2167459 RH |
1200 | |
1201 | return sv; | |
1202 | } | |
1203 | ||
31234768 RH |
1204 | static void do_add(DisasContext *ctx, unsigned rt, TCGv_reg in1, |
1205 | TCGv_reg in2, unsigned shift, bool is_l, | |
faf97ba1 | 1206 | bool is_tsv, bool is_tc, bool is_c, unsigned cf, bool d) |
b2167459 | 1207 | { |
bdcccc17 | 1208 | TCGv_reg dest, cb, cb_msb, cb_cond, sv, tmp; |
b2167459 RH |
1209 | unsigned c = cf >> 1; |
1210 | DisasCond cond; | |
1211 | ||
1212 | dest = tcg_temp_new(); | |
f764718d RH |
1213 | cb = NULL; |
1214 | cb_msb = NULL; | |
bdcccc17 | 1215 | cb_cond = NULL; |
b2167459 RH |
1216 | |
1217 | if (shift) { | |
e12c6309 | 1218 | tmp = tcg_temp_new(); |
eaa3783b | 1219 | tcg_gen_shli_reg(tmp, in1, shift); |
b2167459 RH |
1220 | in1 = tmp; |
1221 | } | |
1222 | ||
b47a4a02 | 1223 | if (!is_l || cond_need_cb(c)) { |
29dd6f64 | 1224 | TCGv_reg zero = tcg_constant_reg(0); |
e12c6309 | 1225 | cb_msb = tcg_temp_new(); |
bdcccc17 RH |
1226 | cb = tcg_temp_new(); |
1227 | ||
eaa3783b | 1228 | tcg_gen_add2_reg(dest, cb_msb, in1, zero, in2, zero); |
b2167459 | 1229 | if (is_c) { |
bdcccc17 RH |
1230 | tcg_gen_add2_reg(dest, cb_msb, dest, cb_msb, |
1231 | get_psw_carry(ctx, d), zero); | |
b2167459 | 1232 | } |
bdcccc17 RH |
1233 | tcg_gen_xor_reg(cb, in1, in2); |
1234 | tcg_gen_xor_reg(cb, cb, dest); | |
1235 | if (cond_need_cb(c)) { | |
1236 | cb_cond = get_carry(ctx, d, cb, cb_msb); | |
b2167459 RH |
1237 | } |
1238 | } else { | |
eaa3783b | 1239 | tcg_gen_add_reg(dest, in1, in2); |
b2167459 | 1240 | if (is_c) { |
bdcccc17 | 1241 | tcg_gen_add_reg(dest, dest, get_psw_carry(ctx, d)); |
b2167459 RH |
1242 | } |
1243 | } | |
1244 | ||
1245 | /* Compute signed overflow if required. */ | |
f764718d | 1246 | sv = NULL; |
b47a4a02 | 1247 | if (is_tsv || cond_need_sv(c)) { |
b2167459 RH |
1248 | sv = do_add_sv(ctx, dest, in1, in2); |
1249 | if (is_tsv) { | |
1250 | /* ??? Need to include overflow from shift. */ | |
ad75a51e | 1251 | gen_helper_tsv(tcg_env, sv); |
b2167459 RH |
1252 | } |
1253 | } | |
1254 | ||
1255 | /* Emit any conditional trap before any writeback. */ | |
a751eb31 | 1256 | cond = do_cond(ctx, cf, d, dest, cb_cond, sv); |
b2167459 | 1257 | if (is_tc) { |
b2167459 | 1258 | tmp = tcg_temp_new(); |
eaa3783b | 1259 | tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); |
ad75a51e | 1260 | gen_helper_tcond(tcg_env, tmp); |
b2167459 RH |
1261 | } |
1262 | ||
1263 | /* Write back the result. */ | |
1264 | if (!is_l) { | |
1265 | save_or_nullify(ctx, cpu_psw_cb, cb); | |
1266 | save_or_nullify(ctx, cpu_psw_cb_msb, cb_msb); | |
1267 | } | |
1268 | save_gpr(ctx, rt, dest); | |
b2167459 RH |
1269 | |
1270 | /* Install the new nullification. */ | |
1271 | cond_free(&ctx->null_cond); | |
1272 | ctx->null_cond = cond; | |
b2167459 RH |
1273 | } |
1274 | ||
faf97ba1 | 1275 | static bool do_add_reg(DisasContext *ctx, arg_rrr_cf_d_sh *a, |
0c982a28 RH |
1276 | bool is_l, bool is_tsv, bool is_tc, bool is_c) |
1277 | { | |
1278 | TCGv_reg tcg_r1, tcg_r2; | |
1279 | ||
1280 | if (a->cf) { | |
1281 | nullify_over(ctx); | |
1282 | } | |
1283 | tcg_r1 = load_gpr(ctx, a->r1); | |
1284 | tcg_r2 = load_gpr(ctx, a->r2); | |
faf97ba1 RH |
1285 | do_add(ctx, a->t, tcg_r1, tcg_r2, a->sh, is_l, |
1286 | is_tsv, is_tc, is_c, a->cf, a->d); | |
0c982a28 RH |
1287 | return nullify_end(ctx); |
1288 | } | |
1289 | ||
0588e061 RH |
1290 | static bool do_add_imm(DisasContext *ctx, arg_rri_cf *a, |
1291 | bool is_tsv, bool is_tc) | |
1292 | { | |
1293 | TCGv_reg tcg_im, tcg_r2; | |
1294 | ||
1295 | if (a->cf) { | |
1296 | nullify_over(ctx); | |
1297 | } | |
d4e58033 | 1298 | tcg_im = tcg_constant_reg(a->i); |
0588e061 | 1299 | tcg_r2 = load_gpr(ctx, a->r); |
faf97ba1 RH |
1300 | /* All ADDI conditions are 32-bit. */ |
1301 | do_add(ctx, a->t, tcg_im, tcg_r2, 0, 0, is_tsv, is_tc, 0, a->cf, false); | |
0588e061 RH |
1302 | return nullify_end(ctx); |
1303 | } | |
1304 | ||
31234768 RH |
1305 | static void do_sub(DisasContext *ctx, unsigned rt, TCGv_reg in1, |
1306 | TCGv_reg in2, bool is_tsv, bool is_b, | |
63c427c6 | 1307 | bool is_tc, unsigned cf, bool d) |
b2167459 | 1308 | { |
eaa3783b | 1309 | TCGv_reg dest, sv, cb, cb_msb, zero, tmp; |
b2167459 RH |
1310 | unsigned c = cf >> 1; |
1311 | DisasCond cond; | |
1312 | ||
1313 | dest = tcg_temp_new(); | |
1314 | cb = tcg_temp_new(); | |
1315 | cb_msb = tcg_temp_new(); | |
1316 | ||
29dd6f64 | 1317 | zero = tcg_constant_reg(0); |
b2167459 RH |
1318 | if (is_b) { |
1319 | /* DEST,C = IN1 + ~IN2 + C. */ | |
eaa3783b | 1320 | tcg_gen_not_reg(cb, in2); |
bdcccc17 | 1321 | tcg_gen_add2_reg(dest, cb_msb, in1, zero, get_psw_carry(ctx, d), zero); |
eaa3783b RH |
1322 | tcg_gen_add2_reg(dest, cb_msb, dest, cb_msb, cb, zero); |
1323 | tcg_gen_xor_reg(cb, cb, in1); | |
1324 | tcg_gen_xor_reg(cb, cb, dest); | |
b2167459 | 1325 | } else { |
bdcccc17 RH |
1326 | /* |
1327 | * DEST,C = IN1 + ~IN2 + 1. We can produce the same result in fewer | |
1328 | * operations by seeding the high word with 1 and subtracting. | |
1329 | */ | |
1330 | TCGv_reg one = tcg_constant_reg(1); | |
1331 | tcg_gen_sub2_reg(dest, cb_msb, in1, one, in2, zero); | |
eaa3783b RH |
1332 | tcg_gen_eqv_reg(cb, in1, in2); |
1333 | tcg_gen_xor_reg(cb, cb, dest); | |
b2167459 | 1334 | } |
b2167459 RH |
1335 | |
1336 | /* Compute signed overflow if required. */ | |
f764718d | 1337 | sv = NULL; |
b47a4a02 | 1338 | if (is_tsv || cond_need_sv(c)) { |
b2167459 RH |
1339 | sv = do_sub_sv(ctx, dest, in1, in2); |
1340 | if (is_tsv) { | |
ad75a51e | 1341 | gen_helper_tsv(tcg_env, sv); |
b2167459 RH |
1342 | } |
1343 | } | |
1344 | ||
1345 | /* Compute the condition. We cannot use the special case for borrow. */ | |
1346 | if (!is_b) { | |
4fe9533a | 1347 | cond = do_sub_cond(ctx, cf, d, dest, in1, in2, sv); |
b2167459 | 1348 | } else { |
a751eb31 | 1349 | cond = do_cond(ctx, cf, d, dest, get_carry(ctx, d, cb, cb_msb), sv); |
b2167459 RH |
1350 | } |
1351 | ||
1352 | /* Emit any conditional trap before any writeback. */ | |
1353 | if (is_tc) { | |
b2167459 | 1354 | tmp = tcg_temp_new(); |
eaa3783b | 1355 | tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); |
ad75a51e | 1356 | gen_helper_tcond(tcg_env, tmp); |
b2167459 RH |
1357 | } |
1358 | ||
1359 | /* Write back the result. */ | |
1360 | save_or_nullify(ctx, cpu_psw_cb, cb); | |
1361 | save_or_nullify(ctx, cpu_psw_cb_msb, cb_msb); | |
1362 | save_gpr(ctx, rt, dest); | |
b2167459 RH |
1363 | |
1364 | /* Install the new nullification. */ | |
1365 | cond_free(&ctx->null_cond); | |
1366 | ctx->null_cond = cond; | |
b2167459 RH |
1367 | } |
1368 | ||
63c427c6 | 1369 | static bool do_sub_reg(DisasContext *ctx, arg_rrr_cf_d *a, |
0c982a28 RH |
1370 | bool is_tsv, bool is_b, bool is_tc) |
1371 | { | |
1372 | TCGv_reg tcg_r1, tcg_r2; | |
1373 | ||
1374 | if (a->cf) { | |
1375 | nullify_over(ctx); | |
1376 | } | |
1377 | tcg_r1 = load_gpr(ctx, a->r1); | |
1378 | tcg_r2 = load_gpr(ctx, a->r2); | |
63c427c6 | 1379 | do_sub(ctx, a->t, tcg_r1, tcg_r2, is_tsv, is_b, is_tc, a->cf, a->d); |
0c982a28 RH |
1380 | return nullify_end(ctx); |
1381 | } | |
1382 | ||
0588e061 RH |
1383 | static bool do_sub_imm(DisasContext *ctx, arg_rri_cf *a, bool is_tsv) |
1384 | { | |
1385 | TCGv_reg tcg_im, tcg_r2; | |
1386 | ||
1387 | if (a->cf) { | |
1388 | nullify_over(ctx); | |
1389 | } | |
d4e58033 | 1390 | tcg_im = tcg_constant_reg(a->i); |
0588e061 | 1391 | tcg_r2 = load_gpr(ctx, a->r); |
63c427c6 RH |
1392 | /* All SUBI conditions are 32-bit. */ |
1393 | do_sub(ctx, a->t, tcg_im, tcg_r2, is_tsv, 0, 0, a->cf, false); | |
0588e061 RH |
1394 | return nullify_end(ctx); |
1395 | } | |
1396 | ||
31234768 | 1397 | static void do_cmpclr(DisasContext *ctx, unsigned rt, TCGv_reg in1, |
345aa35f | 1398 | TCGv_reg in2, unsigned cf, bool d) |
b2167459 | 1399 | { |
eaa3783b | 1400 | TCGv_reg dest, sv; |
b2167459 RH |
1401 | DisasCond cond; |
1402 | ||
1403 | dest = tcg_temp_new(); | |
eaa3783b | 1404 | tcg_gen_sub_reg(dest, in1, in2); |
b2167459 RH |
1405 | |
1406 | /* Compute signed overflow if required. */ | |
f764718d | 1407 | sv = NULL; |
b47a4a02 | 1408 | if (cond_need_sv(cf >> 1)) { |
b2167459 RH |
1409 | sv = do_sub_sv(ctx, dest, in1, in2); |
1410 | } | |
1411 | ||
1412 | /* Form the condition for the compare. */ | |
4fe9533a | 1413 | cond = do_sub_cond(ctx, cf, d, dest, in1, in2, sv); |
b2167459 RH |
1414 | |
1415 | /* Clear. */ | |
eaa3783b | 1416 | tcg_gen_movi_reg(dest, 0); |
b2167459 | 1417 | save_gpr(ctx, rt, dest); |
b2167459 RH |
1418 | |
1419 | /* Install the new nullification. */ | |
1420 | cond_free(&ctx->null_cond); | |
1421 | ctx->null_cond = cond; | |
b2167459 RH |
1422 | } |
1423 | ||
31234768 | 1424 | static void do_log(DisasContext *ctx, unsigned rt, TCGv_reg in1, |
fa8e3bed | 1425 | TCGv_reg in2, unsigned cf, bool d, |
31234768 | 1426 | void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) |
b2167459 | 1427 | { |
eaa3783b | 1428 | TCGv_reg dest = dest_gpr(ctx, rt); |
b2167459 RH |
1429 | |
1430 | /* Perform the operation, and writeback. */ | |
1431 | fn(dest, in1, in2); | |
1432 | save_gpr(ctx, rt, dest); | |
1433 | ||
1434 | /* Install the new nullification. */ | |
1435 | cond_free(&ctx->null_cond); | |
1436 | if (cf) { | |
b5af8423 | 1437 | ctx->null_cond = do_log_cond(ctx, cf, d, dest); |
b2167459 | 1438 | } |
b2167459 RH |
1439 | } |
1440 | ||
fa8e3bed | 1441 | static bool do_log_reg(DisasContext *ctx, arg_rrr_cf_d *a, |
0c982a28 RH |
1442 | void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) |
1443 | { | |
1444 | TCGv_reg tcg_r1, tcg_r2; | |
1445 | ||
1446 | if (a->cf) { | |
1447 | nullify_over(ctx); | |
1448 | } | |
1449 | tcg_r1 = load_gpr(ctx, a->r1); | |
1450 | tcg_r2 = load_gpr(ctx, a->r2); | |
fa8e3bed | 1451 | do_log(ctx, a->t, tcg_r1, tcg_r2, a->cf, a->d, fn); |
0c982a28 RH |
1452 | return nullify_end(ctx); |
1453 | } | |
1454 | ||
31234768 | 1455 | static void do_unit(DisasContext *ctx, unsigned rt, TCGv_reg in1, |
af240753 | 1456 | TCGv_reg in2, unsigned cf, bool d, bool is_tc, |
31234768 | 1457 | void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) |
b2167459 | 1458 | { |
eaa3783b | 1459 | TCGv_reg dest; |
b2167459 RH |
1460 | DisasCond cond; |
1461 | ||
1462 | if (cf == 0) { | |
1463 | dest = dest_gpr(ctx, rt); | |
1464 | fn(dest, in1, in2); | |
1465 | save_gpr(ctx, rt, dest); | |
1466 | cond_free(&ctx->null_cond); | |
1467 | } else { | |
1468 | dest = tcg_temp_new(); | |
1469 | fn(dest, in1, in2); | |
1470 | ||
59963d8f | 1471 | cond = do_unit_cond(cf, d, dest, in1, in2); |
b2167459 RH |
1472 | |
1473 | if (is_tc) { | |
eaa3783b | 1474 | TCGv_reg tmp = tcg_temp_new(); |
eaa3783b | 1475 | tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); |
ad75a51e | 1476 | gen_helper_tcond(tcg_env, tmp); |
b2167459 RH |
1477 | } |
1478 | save_gpr(ctx, rt, dest); | |
1479 | ||
1480 | cond_free(&ctx->null_cond); | |
1481 | ctx->null_cond = cond; | |
1482 | } | |
b2167459 RH |
1483 | } |
1484 | ||
86f8d05f | 1485 | #ifndef CONFIG_USER_ONLY |
8d6ae7fb RH |
1486 | /* The "normal" usage is SP >= 0, wherein SP == 0 selects the space |
1487 | from the top 2 bits of the base register. There are a few system | |
1488 | instructions that have a 3-bit space specifier, for which SR0 is | |
1489 | not special. To handle this, pass ~SP. */ | |
86f8d05f RH |
1490 | static TCGv_i64 space_select(DisasContext *ctx, int sp, TCGv_reg base) |
1491 | { | |
1492 | TCGv_ptr ptr; | |
1493 | TCGv_reg tmp; | |
1494 | TCGv_i64 spc; | |
1495 | ||
1496 | if (sp != 0) { | |
8d6ae7fb RH |
1497 | if (sp < 0) { |
1498 | sp = ~sp; | |
1499 | } | |
a6779861 | 1500 | spc = tcg_temp_new_tl(); |
8d6ae7fb RH |
1501 | load_spr(ctx, spc, sp); |
1502 | return spc; | |
86f8d05f | 1503 | } |
494737b7 RH |
1504 | if (ctx->tb_flags & TB_FLAG_SR_SAME) { |
1505 | return cpu_srH; | |
1506 | } | |
86f8d05f RH |
1507 | |
1508 | ptr = tcg_temp_new_ptr(); | |
1509 | tmp = tcg_temp_new(); | |
a6779861 | 1510 | spc = tcg_temp_new_tl(); |
86f8d05f | 1511 | |
698240d1 RH |
1512 | /* Extract top 2 bits of the address, shift left 3 for uint64_t index. */ |
1513 | tcg_gen_shri_reg(tmp, base, (ctx->tb_flags & PSW_W ? 64 : 32) - 5); | |
86f8d05f RH |
1514 | tcg_gen_andi_reg(tmp, tmp, 030); |
1515 | tcg_gen_trunc_reg_ptr(ptr, tmp); | |
86f8d05f | 1516 | |
ad75a51e | 1517 | tcg_gen_add_ptr(ptr, ptr, tcg_env); |
86f8d05f | 1518 | tcg_gen_ld_i64(spc, ptr, offsetof(CPUHPPAState, sr[4])); |
86f8d05f RH |
1519 | |
1520 | return spc; | |
1521 | } | |
1522 | #endif | |
1523 | ||
1524 | static void form_gva(DisasContext *ctx, TCGv_tl *pgva, TCGv_reg *pofs, | |
1525 | unsigned rb, unsigned rx, int scale, target_sreg disp, | |
1526 | unsigned sp, int modify, bool is_phys) | |
1527 | { | |
1528 | TCGv_reg base = load_gpr(ctx, rb); | |
1529 | TCGv_reg ofs; | |
698240d1 | 1530 | TCGv_tl addr; |
86f8d05f RH |
1531 | |
1532 | /* Note that RX is mutually exclusive with DISP. */ | |
1533 | if (rx) { | |
e12c6309 | 1534 | ofs = tcg_temp_new(); |
86f8d05f RH |
1535 | tcg_gen_shli_reg(ofs, cpu_gr[rx], scale); |
1536 | tcg_gen_add_reg(ofs, ofs, base); | |
1537 | } else if (disp || modify) { | |
e12c6309 | 1538 | ofs = tcg_temp_new(); |
86f8d05f RH |
1539 | tcg_gen_addi_reg(ofs, base, disp); |
1540 | } else { | |
1541 | ofs = base; | |
1542 | } | |
1543 | ||
1544 | *pofs = ofs; | |
698240d1 | 1545 | *pgva = addr = tcg_temp_new_tl(); |
86f8d05f | 1546 | tcg_gen_extu_reg_tl(addr, modify <= 0 ? ofs : base); |
698240d1 RH |
1547 | tcg_gen_andi_tl(addr, addr, gva_offset_mask(ctx)); |
1548 | #ifndef CONFIG_USER_ONLY | |
86f8d05f RH |
1549 | if (!is_phys) { |
1550 | tcg_gen_or_tl(addr, addr, space_select(ctx, sp, base)); | |
1551 | } | |
86f8d05f RH |
1552 | #endif |
1553 | } | |
1554 | ||
96d6407f RH |
1555 | /* Emit a memory load. The modify parameter should be |
1556 | * < 0 for pre-modify, | |
1557 | * > 0 for post-modify, | |
1558 | * = 0 for no base register update. | |
1559 | */ | |
1560 | static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb, | |
eaa3783b | 1561 | unsigned rx, int scale, target_sreg disp, |
14776ab5 | 1562 | unsigned sp, int modify, MemOp mop) |
96d6407f | 1563 | { |
86f8d05f RH |
1564 | TCGv_reg ofs; |
1565 | TCGv_tl addr; | |
96d6407f RH |
1566 | |
1567 | /* Caller uses nullify_over/nullify_end. */ | |
1568 | assert(ctx->null_cond.c == TCG_COND_NEVER); | |
1569 | ||
86f8d05f RH |
1570 | form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, |
1571 | ctx->mmu_idx == MMU_PHYS_IDX); | |
c1f55d97 | 1572 | tcg_gen_qemu_ld_i32(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); |
86f8d05f RH |
1573 | if (modify) { |
1574 | save_gpr(ctx, rb, ofs); | |
96d6407f | 1575 | } |
96d6407f RH |
1576 | } |
1577 | ||
1578 | static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb, | |
eaa3783b | 1579 | unsigned rx, int scale, target_sreg disp, |
14776ab5 | 1580 | unsigned sp, int modify, MemOp mop) |
96d6407f | 1581 | { |
86f8d05f RH |
1582 | TCGv_reg ofs; |
1583 | TCGv_tl addr; | |
96d6407f RH |
1584 | |
1585 | /* Caller uses nullify_over/nullify_end. */ | |
1586 | assert(ctx->null_cond.c == TCG_COND_NEVER); | |
1587 | ||
86f8d05f RH |
1588 | form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, |
1589 | ctx->mmu_idx == MMU_PHYS_IDX); | |
217d1a5e | 1590 | tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); |
86f8d05f RH |
1591 | if (modify) { |
1592 | save_gpr(ctx, rb, ofs); | |
96d6407f | 1593 | } |
96d6407f RH |
1594 | } |
1595 | ||
1596 | static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb, | |
eaa3783b | 1597 | unsigned rx, int scale, target_sreg disp, |
14776ab5 | 1598 | unsigned sp, int modify, MemOp mop) |
96d6407f | 1599 | { |
86f8d05f RH |
1600 | TCGv_reg ofs; |
1601 | TCGv_tl addr; | |
96d6407f RH |
1602 | |
1603 | /* Caller uses nullify_over/nullify_end. */ | |
1604 | assert(ctx->null_cond.c == TCG_COND_NEVER); | |
1605 | ||
86f8d05f RH |
1606 | form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, |
1607 | ctx->mmu_idx == MMU_PHYS_IDX); | |
217d1a5e | 1608 | tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); |
86f8d05f RH |
1609 | if (modify) { |
1610 | save_gpr(ctx, rb, ofs); | |
96d6407f | 1611 | } |
96d6407f RH |
1612 | } |
1613 | ||
1614 | static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb, | |
eaa3783b | 1615 | unsigned rx, int scale, target_sreg disp, |
14776ab5 | 1616 | unsigned sp, int modify, MemOp mop) |
96d6407f | 1617 | { |
86f8d05f RH |
1618 | TCGv_reg ofs; |
1619 | TCGv_tl addr; | |
96d6407f RH |
1620 | |
1621 | /* Caller uses nullify_over/nullify_end. */ | |
1622 | assert(ctx->null_cond.c == TCG_COND_NEVER); | |
1623 | ||
86f8d05f RH |
1624 | form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, |
1625 | ctx->mmu_idx == MMU_PHYS_IDX); | |
217d1a5e | 1626 | tcg_gen_qemu_st_i64(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); |
86f8d05f RH |
1627 | if (modify) { |
1628 | save_gpr(ctx, rb, ofs); | |
96d6407f | 1629 | } |
96d6407f RH |
1630 | } |
1631 | ||
eaa3783b RH |
1632 | #if TARGET_REGISTER_BITS == 64 |
1633 | #define do_load_reg do_load_64 | |
1634 | #define do_store_reg do_store_64 | |
96d6407f | 1635 | #else |
eaa3783b RH |
1636 | #define do_load_reg do_load_32 |
1637 | #define do_store_reg do_store_32 | |
96d6407f RH |
1638 | #endif |
1639 | ||
1cd012a5 | 1640 | static bool do_load(DisasContext *ctx, unsigned rt, unsigned rb, |
31234768 | 1641 | unsigned rx, int scale, target_sreg disp, |
14776ab5 | 1642 | unsigned sp, int modify, MemOp mop) |
96d6407f | 1643 | { |
eaa3783b | 1644 | TCGv_reg dest; |
96d6407f RH |
1645 | |
1646 | nullify_over(ctx); | |
1647 | ||
1648 | if (modify == 0) { | |
1649 | /* No base register update. */ | |
1650 | dest = dest_gpr(ctx, rt); | |
1651 | } else { | |
1652 | /* Make sure if RT == RB, we see the result of the load. */ | |
e12c6309 | 1653 | dest = tcg_temp_new(); |
96d6407f | 1654 | } |
86f8d05f | 1655 | do_load_reg(ctx, dest, rb, rx, scale, disp, sp, modify, mop); |
96d6407f RH |
1656 | save_gpr(ctx, rt, dest); |
1657 | ||
1cd012a5 | 1658 | return nullify_end(ctx); |
96d6407f RH |
1659 | } |
1660 | ||
740038d7 | 1661 | static bool do_floadw(DisasContext *ctx, unsigned rt, unsigned rb, |
31234768 RH |
1662 | unsigned rx, int scale, target_sreg disp, |
1663 | unsigned sp, int modify) | |
96d6407f RH |
1664 | { |
1665 | TCGv_i32 tmp; | |
1666 | ||
1667 | nullify_over(ctx); | |
1668 | ||
1669 | tmp = tcg_temp_new_i32(); | |
86f8d05f | 1670 | do_load_32(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEUL); |
96d6407f | 1671 | save_frw_i32(rt, tmp); |
96d6407f RH |
1672 | |
1673 | if (rt == 0) { | |
ad75a51e | 1674 | gen_helper_loaded_fr0(tcg_env); |
96d6407f RH |
1675 | } |
1676 | ||
740038d7 RH |
1677 | return nullify_end(ctx); |
1678 | } | |
1679 | ||
1680 | static bool trans_fldw(DisasContext *ctx, arg_ldst *a) | |
1681 | { | |
1682 | return do_floadw(ctx, a->t, a->b, a->x, a->scale ? 2 : 0, | |
1683 | a->disp, a->sp, a->m); | |
96d6407f RH |
1684 | } |
1685 | ||
740038d7 | 1686 | static bool do_floadd(DisasContext *ctx, unsigned rt, unsigned rb, |
31234768 RH |
1687 | unsigned rx, int scale, target_sreg disp, |
1688 | unsigned sp, int modify) | |
96d6407f RH |
1689 | { |
1690 | TCGv_i64 tmp; | |
1691 | ||
1692 | nullify_over(ctx); | |
1693 | ||
1694 | tmp = tcg_temp_new_i64(); | |
fc313c64 | 1695 | do_load_64(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEUQ); |
96d6407f | 1696 | save_frd(rt, tmp); |
96d6407f RH |
1697 | |
1698 | if (rt == 0) { | |
ad75a51e | 1699 | gen_helper_loaded_fr0(tcg_env); |
96d6407f RH |
1700 | } |
1701 | ||
740038d7 RH |
1702 | return nullify_end(ctx); |
1703 | } | |
1704 | ||
1705 | static bool trans_fldd(DisasContext *ctx, arg_ldst *a) | |
1706 | { | |
1707 | return do_floadd(ctx, a->t, a->b, a->x, a->scale ? 3 : 0, | |
1708 | a->disp, a->sp, a->m); | |
96d6407f RH |
1709 | } |
1710 | ||
1cd012a5 | 1711 | static bool do_store(DisasContext *ctx, unsigned rt, unsigned rb, |
31234768 | 1712 | target_sreg disp, unsigned sp, |
14776ab5 | 1713 | int modify, MemOp mop) |
96d6407f RH |
1714 | { |
1715 | nullify_over(ctx); | |
86f8d05f | 1716 | do_store_reg(ctx, load_gpr(ctx, rt), rb, 0, 0, disp, sp, modify, mop); |
1cd012a5 | 1717 | return nullify_end(ctx); |
96d6407f RH |
1718 | } |
1719 | ||
740038d7 | 1720 | static bool do_fstorew(DisasContext *ctx, unsigned rt, unsigned rb, |
31234768 RH |
1721 | unsigned rx, int scale, target_sreg disp, |
1722 | unsigned sp, int modify) | |
96d6407f RH |
1723 | { |
1724 | TCGv_i32 tmp; | |
1725 | ||
1726 | nullify_over(ctx); | |
1727 | ||
1728 | tmp = load_frw_i32(rt); | |
86f8d05f | 1729 | do_store_32(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEUL); |
96d6407f | 1730 | |
740038d7 RH |
1731 | return nullify_end(ctx); |
1732 | } | |
1733 | ||
1734 | static bool trans_fstw(DisasContext *ctx, arg_ldst *a) | |
1735 | { | |
1736 | return do_fstorew(ctx, a->t, a->b, a->x, a->scale ? 2 : 0, | |
1737 | a->disp, a->sp, a->m); | |
96d6407f RH |
1738 | } |
1739 | ||
740038d7 | 1740 | static bool do_fstored(DisasContext *ctx, unsigned rt, unsigned rb, |
31234768 RH |
1741 | unsigned rx, int scale, target_sreg disp, |
1742 | unsigned sp, int modify) | |
96d6407f RH |
1743 | { |
1744 | TCGv_i64 tmp; | |
1745 | ||
1746 | nullify_over(ctx); | |
1747 | ||
1748 | tmp = load_frd(rt); | |
fc313c64 | 1749 | do_store_64(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEUQ); |
96d6407f | 1750 | |
740038d7 RH |
1751 | return nullify_end(ctx); |
1752 | } | |
1753 | ||
1754 | static bool trans_fstd(DisasContext *ctx, arg_ldst *a) | |
1755 | { | |
1756 | return do_fstored(ctx, a->t, a->b, a->x, a->scale ? 3 : 0, | |
1757 | a->disp, a->sp, a->m); | |
96d6407f RH |
1758 | } |
1759 | ||
1ca74648 | 1760 | static bool do_fop_wew(DisasContext *ctx, unsigned rt, unsigned ra, |
31234768 | 1761 | void (*func)(TCGv_i32, TCGv_env, TCGv_i32)) |
ebe9383c RH |
1762 | { |
1763 | TCGv_i32 tmp; | |
1764 | ||
1765 | nullify_over(ctx); | |
1766 | tmp = load_frw0_i32(ra); | |
1767 | ||
ad75a51e | 1768 | func(tmp, tcg_env, tmp); |
ebe9383c RH |
1769 | |
1770 | save_frw_i32(rt, tmp); | |
1ca74648 | 1771 | return nullify_end(ctx); |
ebe9383c RH |
1772 | } |
1773 | ||
1ca74648 | 1774 | static bool do_fop_wed(DisasContext *ctx, unsigned rt, unsigned ra, |
31234768 | 1775 | void (*func)(TCGv_i32, TCGv_env, TCGv_i64)) |
ebe9383c RH |
1776 | { |
1777 | TCGv_i32 dst; | |
1778 | TCGv_i64 src; | |
1779 | ||
1780 | nullify_over(ctx); | |
1781 | src = load_frd(ra); | |
1782 | dst = tcg_temp_new_i32(); | |
1783 | ||
ad75a51e | 1784 | func(dst, tcg_env, src); |
ebe9383c | 1785 | |
ebe9383c | 1786 | save_frw_i32(rt, dst); |
1ca74648 | 1787 | return nullify_end(ctx); |
ebe9383c RH |
1788 | } |
1789 | ||
1ca74648 | 1790 | static bool do_fop_ded(DisasContext *ctx, unsigned rt, unsigned ra, |
31234768 | 1791 | void (*func)(TCGv_i64, TCGv_env, TCGv_i64)) |
ebe9383c RH |
1792 | { |
1793 | TCGv_i64 tmp; | |
1794 | ||
1795 | nullify_over(ctx); | |
1796 | tmp = load_frd0(ra); | |
1797 | ||
ad75a51e | 1798 | func(tmp, tcg_env, tmp); |
ebe9383c RH |
1799 | |
1800 | save_frd(rt, tmp); | |
1ca74648 | 1801 | return nullify_end(ctx); |
ebe9383c RH |
1802 | } |
1803 | ||
1ca74648 | 1804 | static bool do_fop_dew(DisasContext *ctx, unsigned rt, unsigned ra, |
31234768 | 1805 | void (*func)(TCGv_i64, TCGv_env, TCGv_i32)) |
ebe9383c RH |
1806 | { |
1807 | TCGv_i32 src; | |
1808 | TCGv_i64 dst; | |
1809 | ||
1810 | nullify_over(ctx); | |
1811 | src = load_frw0_i32(ra); | |
1812 | dst = tcg_temp_new_i64(); | |
1813 | ||
ad75a51e | 1814 | func(dst, tcg_env, src); |
ebe9383c | 1815 | |
ebe9383c | 1816 | save_frd(rt, dst); |
1ca74648 | 1817 | return nullify_end(ctx); |
ebe9383c RH |
1818 | } |
1819 | ||
1ca74648 | 1820 | static bool do_fop_weww(DisasContext *ctx, unsigned rt, |
31234768 RH |
1821 | unsigned ra, unsigned rb, |
1822 | void (*func)(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32)) | |
ebe9383c RH |
1823 | { |
1824 | TCGv_i32 a, b; | |
1825 | ||
1826 | nullify_over(ctx); | |
1827 | a = load_frw0_i32(ra); | |
1828 | b = load_frw0_i32(rb); | |
1829 | ||
ad75a51e | 1830 | func(a, tcg_env, a, b); |
ebe9383c | 1831 | |
ebe9383c | 1832 | save_frw_i32(rt, a); |
1ca74648 | 1833 | return nullify_end(ctx); |
ebe9383c RH |
1834 | } |
1835 | ||
1ca74648 | 1836 | static bool do_fop_dedd(DisasContext *ctx, unsigned rt, |
31234768 RH |
1837 | unsigned ra, unsigned rb, |
1838 | void (*func)(TCGv_i64, TCGv_env, TCGv_i64, TCGv_i64)) | |
ebe9383c RH |
1839 | { |
1840 | TCGv_i64 a, b; | |
1841 | ||
1842 | nullify_over(ctx); | |
1843 | a = load_frd0(ra); | |
1844 | b = load_frd0(rb); | |
1845 | ||
ad75a51e | 1846 | func(a, tcg_env, a, b); |
ebe9383c | 1847 | |
ebe9383c | 1848 | save_frd(rt, a); |
1ca74648 | 1849 | return nullify_end(ctx); |
ebe9383c RH |
1850 | } |
1851 | ||
98cd9ca7 RH |
1852 | /* Emit an unconditional branch to a direct target, which may or may not |
1853 | have already had nullification handled. */ | |
01afb7be | 1854 | static bool do_dbranch(DisasContext *ctx, target_ureg dest, |
31234768 | 1855 | unsigned link, bool is_n) |
98cd9ca7 RH |
1856 | { |
1857 | if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) { | |
1858 | if (link != 0) { | |
741322f4 | 1859 | copy_iaoq_entry(ctx, cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); |
98cd9ca7 RH |
1860 | } |
1861 | ctx->iaoq_n = dest; | |
1862 | if (is_n) { | |
1863 | ctx->null_cond.c = TCG_COND_ALWAYS; | |
1864 | } | |
98cd9ca7 RH |
1865 | } else { |
1866 | nullify_over(ctx); | |
1867 | ||
1868 | if (link != 0) { | |
741322f4 | 1869 | copy_iaoq_entry(ctx, cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); |
98cd9ca7 RH |
1870 | } |
1871 | ||
1872 | if (is_n && use_nullify_skip(ctx)) { | |
1873 | nullify_set(ctx, 0); | |
1874 | gen_goto_tb(ctx, 0, dest, dest + 4); | |
1875 | } else { | |
1876 | nullify_set(ctx, is_n); | |
1877 | gen_goto_tb(ctx, 0, ctx->iaoq_b, dest); | |
1878 | } | |
1879 | ||
31234768 | 1880 | nullify_end(ctx); |
98cd9ca7 RH |
1881 | |
1882 | nullify_set(ctx, 0); | |
1883 | gen_goto_tb(ctx, 1, ctx->iaoq_b, ctx->iaoq_n); | |
31234768 | 1884 | ctx->base.is_jmp = DISAS_NORETURN; |
98cd9ca7 | 1885 | } |
01afb7be | 1886 | return true; |
98cd9ca7 RH |
1887 | } |
1888 | ||
1889 | /* Emit a conditional branch to a direct target. If the branch itself | |
1890 | is nullified, we should have already used nullify_over. */ | |
01afb7be | 1891 | static bool do_cbranch(DisasContext *ctx, target_sreg disp, bool is_n, |
31234768 | 1892 | DisasCond *cond) |
98cd9ca7 | 1893 | { |
eaa3783b | 1894 | target_ureg dest = iaoq_dest(ctx, disp); |
98cd9ca7 RH |
1895 | TCGLabel *taken = NULL; |
1896 | TCGCond c = cond->c; | |
98cd9ca7 RH |
1897 | bool n; |
1898 | ||
1899 | assert(ctx->null_cond.c == TCG_COND_NEVER); | |
1900 | ||
1901 | /* Handle TRUE and NEVER as direct branches. */ | |
1902 | if (c == TCG_COND_ALWAYS) { | |
01afb7be | 1903 | return do_dbranch(ctx, dest, 0, is_n && disp >= 0); |
98cd9ca7 RH |
1904 | } |
1905 | if (c == TCG_COND_NEVER) { | |
01afb7be | 1906 | return do_dbranch(ctx, ctx->iaoq_n, 0, is_n && disp < 0); |
98cd9ca7 RH |
1907 | } |
1908 | ||
1909 | taken = gen_new_label(); | |
eaa3783b | 1910 | tcg_gen_brcond_reg(c, cond->a0, cond->a1, taken); |
98cd9ca7 RH |
1911 | cond_free(cond); |
1912 | ||
1913 | /* Not taken: Condition not satisfied; nullify on backward branches. */ | |
1914 | n = is_n && disp < 0; | |
1915 | if (n && use_nullify_skip(ctx)) { | |
1916 | nullify_set(ctx, 0); | |
a881c8e7 | 1917 | gen_goto_tb(ctx, 0, ctx->iaoq_n, ctx->iaoq_n + 4); |
98cd9ca7 RH |
1918 | } else { |
1919 | if (!n && ctx->null_lab) { | |
1920 | gen_set_label(ctx->null_lab); | |
1921 | ctx->null_lab = NULL; | |
1922 | } | |
1923 | nullify_set(ctx, n); | |
c301f34e RH |
1924 | if (ctx->iaoq_n == -1) { |
1925 | /* The temporary iaoq_n_var died at the branch above. | |
1926 | Regenerate it here instead of saving it. */ | |
1927 | tcg_gen_addi_reg(ctx->iaoq_n_var, cpu_iaoq_b, 4); | |
1928 | } | |
a881c8e7 | 1929 | gen_goto_tb(ctx, 0, ctx->iaoq_b, ctx->iaoq_n); |
98cd9ca7 RH |
1930 | } |
1931 | ||
1932 | gen_set_label(taken); | |
1933 | ||
1934 | /* Taken: Condition satisfied; nullify on forward branches. */ | |
1935 | n = is_n && disp >= 0; | |
1936 | if (n && use_nullify_skip(ctx)) { | |
1937 | nullify_set(ctx, 0); | |
a881c8e7 | 1938 | gen_goto_tb(ctx, 1, dest, dest + 4); |
98cd9ca7 RH |
1939 | } else { |
1940 | nullify_set(ctx, n); | |
a881c8e7 | 1941 | gen_goto_tb(ctx, 1, ctx->iaoq_b, dest); |
98cd9ca7 RH |
1942 | } |
1943 | ||
1944 | /* Not taken: the branch itself was nullified. */ | |
1945 | if (ctx->null_lab) { | |
1946 | gen_set_label(ctx->null_lab); | |
1947 | ctx->null_lab = NULL; | |
31234768 | 1948 | ctx->base.is_jmp = DISAS_IAQ_N_STALE; |
98cd9ca7 | 1949 | } else { |
31234768 | 1950 | ctx->base.is_jmp = DISAS_NORETURN; |
98cd9ca7 | 1951 | } |
01afb7be | 1952 | return true; |
98cd9ca7 RH |
1953 | } |
1954 | ||
1955 | /* Emit an unconditional branch to an indirect target. This handles | |
1956 | nullification of the branch itself. */ | |
01afb7be | 1957 | static bool do_ibranch(DisasContext *ctx, TCGv_reg dest, |
31234768 | 1958 | unsigned link, bool is_n) |
98cd9ca7 | 1959 | { |
eaa3783b | 1960 | TCGv_reg a0, a1, next, tmp; |
98cd9ca7 RH |
1961 | TCGCond c; |
1962 | ||
1963 | assert(ctx->null_lab == NULL); | |
1964 | ||
1965 | if (ctx->null_cond.c == TCG_COND_NEVER) { | |
1966 | if (link != 0) { | |
741322f4 | 1967 | copy_iaoq_entry(ctx, cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); |
98cd9ca7 | 1968 | } |
e12c6309 | 1969 | next = tcg_temp_new(); |
eaa3783b | 1970 | tcg_gen_mov_reg(next, dest); |
98cd9ca7 | 1971 | if (is_n) { |
c301f34e | 1972 | if (use_nullify_skip(ctx)) { |
a0180973 RH |
1973 | copy_iaoq_entry(ctx, cpu_iaoq_f, -1, next); |
1974 | tcg_gen_addi_reg(next, next, 4); | |
1975 | copy_iaoq_entry(ctx, cpu_iaoq_b, -1, next); | |
c301f34e | 1976 | nullify_set(ctx, 0); |
31234768 | 1977 | ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; |
01afb7be | 1978 | return true; |
c301f34e | 1979 | } |
98cd9ca7 RH |
1980 | ctx->null_cond.c = TCG_COND_ALWAYS; |
1981 | } | |
c301f34e RH |
1982 | ctx->iaoq_n = -1; |
1983 | ctx->iaoq_n_var = next; | |
98cd9ca7 RH |
1984 | } else if (is_n && use_nullify_skip(ctx)) { |
1985 | /* The (conditional) branch, B, nullifies the next insn, N, | |
1986 | and we're allowed to skip execution N (no single-step or | |
4137cb83 | 1987 | tracepoint in effect). Since the goto_ptr that we must use |
98cd9ca7 RH |
1988 | for the indirect branch consumes no special resources, we |
1989 | can (conditionally) skip B and continue execution. */ | |
1990 | /* The use_nullify_skip test implies we have a known control path. */ | |
1991 | tcg_debug_assert(ctx->iaoq_b != -1); | |
1992 | tcg_debug_assert(ctx->iaoq_n != -1); | |
1993 | ||
1994 | /* We do have to handle the non-local temporary, DEST, before | |
1995 | branching. Since IOAQ_F is not really live at this point, we | |
1996 | can simply store DEST optimistically. Similarly with IAOQ_B. */ | |
a0180973 RH |
1997 | copy_iaoq_entry(ctx, cpu_iaoq_f, -1, dest); |
1998 | next = tcg_temp_new(); | |
1999 | tcg_gen_addi_reg(next, dest, 4); | |
2000 | copy_iaoq_entry(ctx, cpu_iaoq_b, -1, next); | |
98cd9ca7 RH |
2001 | |
2002 | nullify_over(ctx); | |
2003 | if (link != 0) { | |
9a91dd84 | 2004 | copy_iaoq_entry(ctx, cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); |
98cd9ca7 | 2005 | } |
7f11636d | 2006 | tcg_gen_lookup_and_goto_ptr(); |
01afb7be | 2007 | return nullify_end(ctx); |
98cd9ca7 | 2008 | } else { |
98cd9ca7 RH |
2009 | c = ctx->null_cond.c; |
2010 | a0 = ctx->null_cond.a0; | |
2011 | a1 = ctx->null_cond.a1; | |
2012 | ||
2013 | tmp = tcg_temp_new(); | |
e12c6309 | 2014 | next = tcg_temp_new(); |
98cd9ca7 | 2015 | |
741322f4 | 2016 | copy_iaoq_entry(ctx, tmp, ctx->iaoq_n, ctx->iaoq_n_var); |
eaa3783b | 2017 | tcg_gen_movcond_reg(c, next, a0, a1, tmp, dest); |
98cd9ca7 RH |
2018 | ctx->iaoq_n = -1; |
2019 | ctx->iaoq_n_var = next; | |
2020 | ||
2021 | if (link != 0) { | |
eaa3783b | 2022 | tcg_gen_movcond_reg(c, cpu_gr[link], a0, a1, cpu_gr[link], tmp); |
98cd9ca7 RH |
2023 | } |
2024 | ||
2025 | if (is_n) { | |
2026 | /* The branch nullifies the next insn, which means the state of N | |
2027 | after the branch is the inverse of the state of N that applied | |
2028 | to the branch. */ | |
eaa3783b | 2029 | tcg_gen_setcond_reg(tcg_invert_cond(c), cpu_psw_n, a0, a1); |
98cd9ca7 RH |
2030 | cond_free(&ctx->null_cond); |
2031 | ctx->null_cond = cond_make_n(); | |
2032 | ctx->psw_n_nonzero = true; | |
2033 | } else { | |
2034 | cond_free(&ctx->null_cond); | |
2035 | } | |
2036 | } | |
01afb7be | 2037 | return true; |
98cd9ca7 RH |
2038 | } |
2039 | ||
660eefe1 RH |
2040 | /* Implement |
2041 | * if (IAOQ_Front{30..31} < GR[b]{30..31}) | |
2042 | * IAOQ_Next{30..31} ← GR[b]{30..31}; | |
2043 | * else | |
2044 | * IAOQ_Next{30..31} ← IAOQ_Front{30..31}; | |
2045 | * which keeps the privilege level from being increased. | |
2046 | */ | |
2047 | static TCGv_reg do_ibranch_priv(DisasContext *ctx, TCGv_reg offset) | |
2048 | { | |
660eefe1 RH |
2049 | TCGv_reg dest; |
2050 | switch (ctx->privilege) { | |
2051 | case 0: | |
2052 | /* Privilege 0 is maximum and is allowed to decrease. */ | |
2053 | return offset; | |
2054 | case 3: | |
993119fe | 2055 | /* Privilege 3 is minimum and is never allowed to increase. */ |
e12c6309 | 2056 | dest = tcg_temp_new(); |
660eefe1 RH |
2057 | tcg_gen_ori_reg(dest, offset, 3); |
2058 | break; | |
2059 | default: | |
e12c6309 | 2060 | dest = tcg_temp_new(); |
660eefe1 RH |
2061 | tcg_gen_andi_reg(dest, offset, -4); |
2062 | tcg_gen_ori_reg(dest, dest, ctx->privilege); | |
2063 | tcg_gen_movcond_reg(TCG_COND_GTU, dest, dest, offset, dest, offset); | |
660eefe1 RH |
2064 | break; |
2065 | } | |
2066 | return dest; | |
660eefe1 RH |
2067 | } |
2068 | ||
ba1d0b44 | 2069 | #ifdef CONFIG_USER_ONLY |
7ad439df RH |
2070 | /* On Linux, page zero is normally marked execute only + gateway. |
2071 | Therefore normal read or write is supposed to fail, but specific | |
2072 | offsets have kernel code mapped to raise permissions to implement | |
2073 | system calls. Handling this via an explicit check here, rather | |
2074 | in than the "be disp(sr2,r0)" instruction that probably sent us | |
2075 | here, is the easiest way to handle the branch delay slot on the | |
2076 | aforementioned BE. */ | |
31234768 | 2077 | static void do_page_zero(DisasContext *ctx) |
7ad439df | 2078 | { |
a0180973 RH |
2079 | TCGv_reg tmp; |
2080 | ||
7ad439df RH |
2081 | /* If by some means we get here with PSW[N]=1, that implies that |
2082 | the B,GATE instruction would be skipped, and we'd fault on the | |
8b81968c | 2083 | next insn within the privileged page. */ |
7ad439df RH |
2084 | switch (ctx->null_cond.c) { |
2085 | case TCG_COND_NEVER: | |
2086 | break; | |
2087 | case TCG_COND_ALWAYS: | |
eaa3783b | 2088 | tcg_gen_movi_reg(cpu_psw_n, 0); |
7ad439df RH |
2089 | goto do_sigill; |
2090 | default: | |
2091 | /* Since this is always the first (and only) insn within the | |
2092 | TB, we should know the state of PSW[N] from TB->FLAGS. */ | |
2093 | g_assert_not_reached(); | |
2094 | } | |
2095 | ||
2096 | /* Check that we didn't arrive here via some means that allowed | |
2097 | non-sequential instruction execution. Normally the PSW[B] bit | |
2098 | detects this by disallowing the B,GATE instruction to execute | |
2099 | under such conditions. */ | |
2100 | if (ctx->iaoq_b != ctx->iaoq_f + 4) { | |
2101 | goto do_sigill; | |
2102 | } | |
2103 | ||
ebd0e151 | 2104 | switch (ctx->iaoq_f & -4) { |
7ad439df | 2105 | case 0x00: /* Null pointer call */ |
2986721d | 2106 | gen_excp_1(EXCP_IMP); |
31234768 RH |
2107 | ctx->base.is_jmp = DISAS_NORETURN; |
2108 | break; | |
7ad439df RH |
2109 | |
2110 | case 0xb0: /* LWS */ | |
2111 | gen_excp_1(EXCP_SYSCALL_LWS); | |
31234768 RH |
2112 | ctx->base.is_jmp = DISAS_NORETURN; |
2113 | break; | |
7ad439df RH |
2114 | |
2115 | case 0xe0: /* SET_THREAD_POINTER */ | |
ad75a51e | 2116 | tcg_gen_st_reg(cpu_gr[26], tcg_env, offsetof(CPUHPPAState, cr[27])); |
a0180973 RH |
2117 | tmp = tcg_temp_new(); |
2118 | tcg_gen_ori_reg(tmp, cpu_gr[31], 3); | |
2119 | copy_iaoq_entry(ctx, cpu_iaoq_f, -1, tmp); | |
2120 | tcg_gen_addi_reg(tmp, tmp, 4); | |
2121 | copy_iaoq_entry(ctx, cpu_iaoq_b, -1, tmp); | |
31234768 RH |
2122 | ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; |
2123 | break; | |
7ad439df RH |
2124 | |
2125 | case 0x100: /* SYSCALL */ | |
2126 | gen_excp_1(EXCP_SYSCALL); | |
31234768 RH |
2127 | ctx->base.is_jmp = DISAS_NORETURN; |
2128 | break; | |
7ad439df RH |
2129 | |
2130 | default: | |
2131 | do_sigill: | |
2986721d | 2132 | gen_excp_1(EXCP_ILL); |
31234768 RH |
2133 | ctx->base.is_jmp = DISAS_NORETURN; |
2134 | break; | |
7ad439df RH |
2135 | } |
2136 | } | |
ba1d0b44 | 2137 | #endif |
7ad439df | 2138 | |
deee69a1 | 2139 | static bool trans_nop(DisasContext *ctx, arg_nop *a) |
b2167459 RH |
2140 | { |
2141 | cond_free(&ctx->null_cond); | |
31234768 | 2142 | return true; |
b2167459 RH |
2143 | } |
2144 | ||
40f9f908 | 2145 | static bool trans_break(DisasContext *ctx, arg_break *a) |
98a9cb79 | 2146 | { |
31234768 | 2147 | return gen_excp_iir(ctx, EXCP_BREAK); |
98a9cb79 RH |
2148 | } |
2149 | ||
e36f27ef | 2150 | static bool trans_sync(DisasContext *ctx, arg_sync *a) |
98a9cb79 RH |
2151 | { |
2152 | /* No point in nullifying the memory barrier. */ | |
2153 | tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); | |
2154 | ||
2155 | cond_free(&ctx->null_cond); | |
31234768 | 2156 | return true; |
98a9cb79 RH |
2157 | } |
2158 | ||
c603e14a | 2159 | static bool trans_mfia(DisasContext *ctx, arg_mfia *a) |
98a9cb79 | 2160 | { |
c603e14a | 2161 | unsigned rt = a->t; |
eaa3783b RH |
2162 | TCGv_reg tmp = dest_gpr(ctx, rt); |
2163 | tcg_gen_movi_reg(tmp, ctx->iaoq_f); | |
98a9cb79 RH |
2164 | save_gpr(ctx, rt, tmp); |
2165 | ||
2166 | cond_free(&ctx->null_cond); | |
31234768 | 2167 | return true; |
98a9cb79 RH |
2168 | } |
2169 | ||
c603e14a | 2170 | static bool trans_mfsp(DisasContext *ctx, arg_mfsp *a) |
98a9cb79 | 2171 | { |
c603e14a RH |
2172 | unsigned rt = a->t; |
2173 | unsigned rs = a->sp; | |
33423472 RH |
2174 | TCGv_i64 t0 = tcg_temp_new_i64(); |
2175 | TCGv_reg t1 = tcg_temp_new(); | |
98a9cb79 | 2176 | |
33423472 RH |
2177 | load_spr(ctx, t0, rs); |
2178 | tcg_gen_shri_i64(t0, t0, 32); | |
2179 | tcg_gen_trunc_i64_reg(t1, t0); | |
2180 | ||
2181 | save_gpr(ctx, rt, t1); | |
98a9cb79 RH |
2182 | |
2183 | cond_free(&ctx->null_cond); | |
31234768 | 2184 | return true; |
98a9cb79 RH |
2185 | } |
2186 | ||
c603e14a | 2187 | static bool trans_mfctl(DisasContext *ctx, arg_mfctl *a) |
98a9cb79 | 2188 | { |
c603e14a RH |
2189 | unsigned rt = a->t; |
2190 | unsigned ctl = a->r; | |
eaa3783b | 2191 | TCGv_reg tmp; |
98a9cb79 RH |
2192 | |
2193 | switch (ctl) { | |
35136a77 | 2194 | case CR_SAR: |
c603e14a | 2195 | if (a->e == 0) { |
98a9cb79 RH |
2196 | /* MFSAR without ,W masks low 5 bits. */ |
2197 | tmp = dest_gpr(ctx, rt); | |
eaa3783b | 2198 | tcg_gen_andi_reg(tmp, cpu_sar, 31); |
98a9cb79 | 2199 | save_gpr(ctx, rt, tmp); |
35136a77 | 2200 | goto done; |
98a9cb79 | 2201 | } |
98a9cb79 | 2202 | save_gpr(ctx, rt, cpu_sar); |
35136a77 RH |
2203 | goto done; |
2204 | case CR_IT: /* Interval Timer */ | |
2205 | /* FIXME: Respect PSW_S bit. */ | |
2206 | nullify_over(ctx); | |
98a9cb79 | 2207 | tmp = dest_gpr(ctx, rt); |
dfd1b812 | 2208 | if (translator_io_start(&ctx->base)) { |
49c29d6c | 2209 | gen_helper_read_interval_timer(tmp); |
31234768 | 2210 | ctx->base.is_jmp = DISAS_IAQ_N_STALE; |
49c29d6c RH |
2211 | } else { |
2212 | gen_helper_read_interval_timer(tmp); | |
49c29d6c | 2213 | } |
98a9cb79 | 2214 | save_gpr(ctx, rt, tmp); |
31234768 | 2215 | return nullify_end(ctx); |
98a9cb79 | 2216 | case 26: |
98a9cb79 | 2217 | case 27: |
98a9cb79 RH |
2218 | break; |
2219 | default: | |
2220 | /* All other control registers are privileged. */ | |
35136a77 RH |
2221 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG); |
2222 | break; | |
98a9cb79 RH |
2223 | } |
2224 | ||
e12c6309 | 2225 | tmp = tcg_temp_new(); |
ad75a51e | 2226 | tcg_gen_ld_reg(tmp, tcg_env, offsetof(CPUHPPAState, cr[ctl])); |
35136a77 RH |
2227 | save_gpr(ctx, rt, tmp); |
2228 | ||
2229 | done: | |
98a9cb79 | 2230 | cond_free(&ctx->null_cond); |
31234768 | 2231 | return true; |
98a9cb79 RH |
2232 | } |
2233 | ||
c603e14a | 2234 | static bool trans_mtsp(DisasContext *ctx, arg_mtsp *a) |
33423472 | 2235 | { |
c603e14a RH |
2236 | unsigned rr = a->r; |
2237 | unsigned rs = a->sp; | |
33423472 RH |
2238 | TCGv_i64 t64; |
2239 | ||
2240 | if (rs >= 5) { | |
2241 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG); | |
2242 | } | |
2243 | nullify_over(ctx); | |
2244 | ||
2245 | t64 = tcg_temp_new_i64(); | |
2246 | tcg_gen_extu_reg_i64(t64, load_gpr(ctx, rr)); | |
2247 | tcg_gen_shli_i64(t64, t64, 32); | |
2248 | ||
2249 | if (rs >= 4) { | |
ad75a51e | 2250 | tcg_gen_st_i64(t64, tcg_env, offsetof(CPUHPPAState, sr[rs])); |
494737b7 | 2251 | ctx->tb_flags &= ~TB_FLAG_SR_SAME; |
33423472 RH |
2252 | } else { |
2253 | tcg_gen_mov_i64(cpu_sr[rs], t64); | |
2254 | } | |
33423472 | 2255 | |
31234768 | 2256 | return nullify_end(ctx); |
33423472 RH |
2257 | } |
2258 | ||
c603e14a | 2259 | static bool trans_mtctl(DisasContext *ctx, arg_mtctl *a) |
98a9cb79 | 2260 | { |
c603e14a | 2261 | unsigned ctl = a->t; |
4845f015 | 2262 | TCGv_reg reg; |
eaa3783b | 2263 | TCGv_reg tmp; |
98a9cb79 | 2264 | |
35136a77 | 2265 | if (ctl == CR_SAR) { |
4845f015 | 2266 | reg = load_gpr(ctx, a->r); |
98a9cb79 | 2267 | tmp = tcg_temp_new(); |
f3618f59 | 2268 | tcg_gen_andi_reg(tmp, reg, ctx->is_pa20 ? 63 : 31); |
98a9cb79 | 2269 | save_or_nullify(ctx, cpu_sar, tmp); |
35136a77 RH |
2270 | |
2271 | cond_free(&ctx->null_cond); | |
31234768 | 2272 | return true; |
98a9cb79 RH |
2273 | } |
2274 | ||
35136a77 RH |
2275 | /* All other control registers are privileged or read-only. */ |
2276 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG); | |
2277 | ||
c603e14a | 2278 | #ifndef CONFIG_USER_ONLY |
35136a77 | 2279 | nullify_over(ctx); |
4845f015 SS |
2280 | reg = load_gpr(ctx, a->r); |
2281 | ||
35136a77 RH |
2282 | switch (ctl) { |
2283 | case CR_IT: | |
ad75a51e | 2284 | gen_helper_write_interval_timer(tcg_env, reg); |
35136a77 | 2285 | break; |
4f5f2548 | 2286 | case CR_EIRR: |
ad75a51e | 2287 | gen_helper_write_eirr(tcg_env, reg); |
4f5f2548 RH |
2288 | break; |
2289 | case CR_EIEM: | |
ad75a51e | 2290 | gen_helper_write_eiem(tcg_env, reg); |
31234768 | 2291 | ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; |
4f5f2548 RH |
2292 | break; |
2293 | ||
35136a77 RH |
2294 | case CR_IIASQ: |
2295 | case CR_IIAOQ: | |
2296 | /* FIXME: Respect PSW_Q bit */ | |
2297 | /* The write advances the queue and stores to the back element. */ | |
e12c6309 | 2298 | tmp = tcg_temp_new(); |
ad75a51e | 2299 | tcg_gen_ld_reg(tmp, tcg_env, |
35136a77 | 2300 | offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ])); |
ad75a51e RH |
2301 | tcg_gen_st_reg(tmp, tcg_env, offsetof(CPUHPPAState, cr[ctl])); |
2302 | tcg_gen_st_reg(reg, tcg_env, | |
35136a77 RH |
2303 | offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ])); |
2304 | break; | |
2305 | ||
d5de20bd SS |
2306 | case CR_PID1: |
2307 | case CR_PID2: | |
2308 | case CR_PID3: | |
2309 | case CR_PID4: | |
ad75a51e | 2310 | tcg_gen_st_reg(reg, tcg_env, offsetof(CPUHPPAState, cr[ctl])); |
d5de20bd | 2311 | #ifndef CONFIG_USER_ONLY |
ad75a51e | 2312 | gen_helper_change_prot_id(tcg_env); |
d5de20bd SS |
2313 | #endif |
2314 | break; | |
2315 | ||
35136a77 | 2316 | default: |
ad75a51e | 2317 | tcg_gen_st_reg(reg, tcg_env, offsetof(CPUHPPAState, cr[ctl])); |
35136a77 RH |
2318 | break; |
2319 | } | |
31234768 | 2320 | return nullify_end(ctx); |
4f5f2548 | 2321 | #endif |
98a9cb79 RH |
2322 | } |
2323 | ||
c603e14a | 2324 | static bool trans_mtsarcm(DisasContext *ctx, arg_mtsarcm *a) |
98a9cb79 | 2325 | { |
eaa3783b | 2326 | TCGv_reg tmp = tcg_temp_new(); |
98a9cb79 | 2327 | |
c603e14a | 2328 | tcg_gen_not_reg(tmp, load_gpr(ctx, a->r)); |
f3618f59 | 2329 | tcg_gen_andi_reg(tmp, tmp, ctx->is_pa20 ? 63 : 31); |
98a9cb79 | 2330 | save_or_nullify(ctx, cpu_sar, tmp); |
98a9cb79 RH |
2331 | |
2332 | cond_free(&ctx->null_cond); | |
31234768 | 2333 | return true; |
98a9cb79 RH |
2334 | } |
2335 | ||
e36f27ef | 2336 | static bool trans_ldsid(DisasContext *ctx, arg_ldsid *a) |
98a9cb79 | 2337 | { |
e36f27ef | 2338 | TCGv_reg dest = dest_gpr(ctx, a->t); |
98a9cb79 | 2339 | |
2330504c HD |
2340 | #ifdef CONFIG_USER_ONLY |
2341 | /* We don't implement space registers in user mode. */ | |
eaa3783b | 2342 | tcg_gen_movi_reg(dest, 0); |
2330504c | 2343 | #else |
2330504c HD |
2344 | TCGv_i64 t0 = tcg_temp_new_i64(); |
2345 | ||
e36f27ef | 2346 | tcg_gen_mov_i64(t0, space_select(ctx, a->sp, load_gpr(ctx, a->b))); |
2330504c HD |
2347 | tcg_gen_shri_i64(t0, t0, 32); |
2348 | tcg_gen_trunc_i64_reg(dest, t0); | |
2330504c | 2349 | #endif |
e36f27ef | 2350 | save_gpr(ctx, a->t, dest); |
98a9cb79 RH |
2351 | |
2352 | cond_free(&ctx->null_cond); | |
31234768 | 2353 | return true; |
98a9cb79 RH |
2354 | } |
2355 | ||
e36f27ef | 2356 | static bool trans_rsm(DisasContext *ctx, arg_rsm *a) |
e1b5a5ed | 2357 | { |
e36f27ef RH |
2358 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); |
2359 | #ifndef CONFIG_USER_ONLY | |
e1b5a5ed RH |
2360 | TCGv_reg tmp; |
2361 | ||
e1b5a5ed RH |
2362 | nullify_over(ctx); |
2363 | ||
e12c6309 | 2364 | tmp = tcg_temp_new(); |
ad75a51e | 2365 | tcg_gen_ld_reg(tmp, tcg_env, offsetof(CPUHPPAState, psw)); |
e36f27ef | 2366 | tcg_gen_andi_reg(tmp, tmp, ~a->i); |
ad75a51e | 2367 | gen_helper_swap_system_mask(tmp, tcg_env, tmp); |
e36f27ef | 2368 | save_gpr(ctx, a->t, tmp); |
e1b5a5ed RH |
2369 | |
2370 | /* Exit the TB to recognize new interrupts, e.g. PSW_M. */ | |
31234768 RH |
2371 | ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; |
2372 | return nullify_end(ctx); | |
e36f27ef | 2373 | #endif |
e1b5a5ed RH |
2374 | } |
2375 | ||
e36f27ef | 2376 | static bool trans_ssm(DisasContext *ctx, arg_ssm *a) |
e1b5a5ed | 2377 | { |
e36f27ef RH |
2378 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); |
2379 | #ifndef CONFIG_USER_ONLY | |
e1b5a5ed RH |
2380 | TCGv_reg tmp; |
2381 | ||
e1b5a5ed RH |
2382 | nullify_over(ctx); |
2383 | ||
e12c6309 | 2384 | tmp = tcg_temp_new(); |
ad75a51e | 2385 | tcg_gen_ld_reg(tmp, tcg_env, offsetof(CPUHPPAState, psw)); |
e36f27ef | 2386 | tcg_gen_ori_reg(tmp, tmp, a->i); |
ad75a51e | 2387 | gen_helper_swap_system_mask(tmp, tcg_env, tmp); |
e36f27ef | 2388 | save_gpr(ctx, a->t, tmp); |
e1b5a5ed RH |
2389 | |
2390 | /* Exit the TB to recognize new interrupts, e.g. PSW_I. */ | |
31234768 RH |
2391 | ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; |
2392 | return nullify_end(ctx); | |
e36f27ef | 2393 | #endif |
e1b5a5ed RH |
2394 | } |
2395 | ||
c603e14a | 2396 | static bool trans_mtsm(DisasContext *ctx, arg_mtsm *a) |
e1b5a5ed | 2397 | { |
e1b5a5ed | 2398 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); |
c603e14a RH |
2399 | #ifndef CONFIG_USER_ONLY |
2400 | TCGv_reg tmp, reg; | |
e1b5a5ed RH |
2401 | nullify_over(ctx); |
2402 | ||
c603e14a | 2403 | reg = load_gpr(ctx, a->r); |
e12c6309 | 2404 | tmp = tcg_temp_new(); |
ad75a51e | 2405 | gen_helper_swap_system_mask(tmp, tcg_env, reg); |
e1b5a5ed RH |
2406 | |
2407 | /* Exit the TB to recognize new interrupts. */ | |
31234768 RH |
2408 | ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; |
2409 | return nullify_end(ctx); | |
c603e14a | 2410 | #endif |
e1b5a5ed | 2411 | } |
f49b3537 | 2412 | |
e36f27ef | 2413 | static bool do_rfi(DisasContext *ctx, bool rfi_r) |
f49b3537 | 2414 | { |
f49b3537 | 2415 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); |
e36f27ef | 2416 | #ifndef CONFIG_USER_ONLY |
f49b3537 RH |
2417 | nullify_over(ctx); |
2418 | ||
e36f27ef | 2419 | if (rfi_r) { |
ad75a51e | 2420 | gen_helper_rfi_r(tcg_env); |
f49b3537 | 2421 | } else { |
ad75a51e | 2422 | gen_helper_rfi(tcg_env); |
f49b3537 | 2423 | } |
31234768 | 2424 | /* Exit the TB to recognize new interrupts. */ |
8532a14e | 2425 | tcg_gen_exit_tb(NULL, 0); |
31234768 | 2426 | ctx->base.is_jmp = DISAS_NORETURN; |
f49b3537 | 2427 | |
31234768 | 2428 | return nullify_end(ctx); |
e36f27ef RH |
2429 | #endif |
2430 | } | |
2431 | ||
2432 | static bool trans_rfi(DisasContext *ctx, arg_rfi *a) | |
2433 | { | |
2434 | return do_rfi(ctx, false); | |
2435 | } | |
2436 | ||
2437 | static bool trans_rfi_r(DisasContext *ctx, arg_rfi_r *a) | |
2438 | { | |
2439 | return do_rfi(ctx, true); | |
f49b3537 | 2440 | } |
6210db05 | 2441 | |
96927adb RH |
2442 | static bool trans_halt(DisasContext *ctx, arg_halt *a) |
2443 | { | |
2444 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); | |
e36f27ef | 2445 | #ifndef CONFIG_USER_ONLY |
96927adb | 2446 | nullify_over(ctx); |
ad75a51e | 2447 | gen_helper_halt(tcg_env); |
96927adb RH |
2448 | ctx->base.is_jmp = DISAS_NORETURN; |
2449 | return nullify_end(ctx); | |
2450 | #endif | |
2451 | } | |
2452 | ||
2453 | static bool trans_reset(DisasContext *ctx, arg_reset *a) | |
6210db05 HD |
2454 | { |
2455 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); | |
96927adb | 2456 | #ifndef CONFIG_USER_ONLY |
6210db05 | 2457 | nullify_over(ctx); |
ad75a51e | 2458 | gen_helper_reset(tcg_env); |
31234768 RH |
2459 | ctx->base.is_jmp = DISAS_NORETURN; |
2460 | return nullify_end(ctx); | |
96927adb | 2461 | #endif |
6210db05 | 2462 | } |
e1b5a5ed | 2463 | |
4a4554c6 HD |
2464 | static bool trans_getshadowregs(DisasContext *ctx, arg_getshadowregs *a) |
2465 | { | |
2466 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); | |
2467 | #ifndef CONFIG_USER_ONLY | |
2468 | nullify_over(ctx); | |
ad75a51e | 2469 | gen_helper_getshadowregs(tcg_env); |
4a4554c6 HD |
2470 | return nullify_end(ctx); |
2471 | #endif | |
2472 | } | |
2473 | ||
deee69a1 | 2474 | static bool trans_nop_addrx(DisasContext *ctx, arg_ldst *a) |
98a9cb79 | 2475 | { |
deee69a1 RH |
2476 | if (a->m) { |
2477 | TCGv_reg dest = dest_gpr(ctx, a->b); | |
2478 | TCGv_reg src1 = load_gpr(ctx, a->b); | |
2479 | TCGv_reg src2 = load_gpr(ctx, a->x); | |
98a9cb79 | 2480 | |
deee69a1 RH |
2481 | /* The only thing we need to do is the base register modification. */ |
2482 | tcg_gen_add_reg(dest, src1, src2); | |
2483 | save_gpr(ctx, a->b, dest); | |
2484 | } | |
98a9cb79 | 2485 | cond_free(&ctx->null_cond); |
31234768 | 2486 | return true; |
98a9cb79 RH |
2487 | } |
2488 | ||
deee69a1 | 2489 | static bool trans_probe(DisasContext *ctx, arg_probe *a) |
98a9cb79 | 2490 | { |
86f8d05f | 2491 | TCGv_reg dest, ofs; |
eed14219 | 2492 | TCGv_i32 level, want; |
86f8d05f | 2493 | TCGv_tl addr; |
98a9cb79 RH |
2494 | |
2495 | nullify_over(ctx); | |
2496 | ||
deee69a1 RH |
2497 | dest = dest_gpr(ctx, a->t); |
2498 | form_gva(ctx, &addr, &ofs, a->b, 0, 0, 0, a->sp, 0, false); | |
eed14219 | 2499 | |
deee69a1 | 2500 | if (a->imm) { |
29dd6f64 | 2501 | level = tcg_constant_i32(a->ri); |
98a9cb79 | 2502 | } else { |
eed14219 | 2503 | level = tcg_temp_new_i32(); |
deee69a1 | 2504 | tcg_gen_trunc_reg_i32(level, load_gpr(ctx, a->ri)); |
eed14219 | 2505 | tcg_gen_andi_i32(level, level, 3); |
98a9cb79 | 2506 | } |
29dd6f64 | 2507 | want = tcg_constant_i32(a->write ? PAGE_WRITE : PAGE_READ); |
eed14219 | 2508 | |
ad75a51e | 2509 | gen_helper_probe(dest, tcg_env, addr, level, want); |
eed14219 | 2510 | |
deee69a1 | 2511 | save_gpr(ctx, a->t, dest); |
31234768 | 2512 | return nullify_end(ctx); |
98a9cb79 RH |
2513 | } |
2514 | ||
deee69a1 | 2515 | static bool trans_ixtlbx(DisasContext *ctx, arg_ixtlbx *a) |
8d6ae7fb | 2516 | { |
deee69a1 RH |
2517 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); |
2518 | #ifndef CONFIG_USER_ONLY | |
8d6ae7fb RH |
2519 | TCGv_tl addr; |
2520 | TCGv_reg ofs, reg; | |
2521 | ||
8d6ae7fb RH |
2522 | nullify_over(ctx); |
2523 | ||
deee69a1 RH |
2524 | form_gva(ctx, &addr, &ofs, a->b, 0, 0, 0, a->sp, 0, false); |
2525 | reg = load_gpr(ctx, a->r); | |
2526 | if (a->addr) { | |
ad75a51e | 2527 | gen_helper_itlba(tcg_env, addr, reg); |
8d6ae7fb | 2528 | } else { |
ad75a51e | 2529 | gen_helper_itlbp(tcg_env, addr, reg); |
8d6ae7fb RH |
2530 | } |
2531 | ||
32dc7569 SS |
2532 | /* Exit TB for TLB change if mmu is enabled. */ |
2533 | if (ctx->tb_flags & PSW_C) { | |
31234768 RH |
2534 | ctx->base.is_jmp = DISAS_IAQ_N_STALE; |
2535 | } | |
2536 | return nullify_end(ctx); | |
deee69a1 | 2537 | #endif |
8d6ae7fb | 2538 | } |
63300a00 | 2539 | |
deee69a1 | 2540 | static bool trans_pxtlbx(DisasContext *ctx, arg_pxtlbx *a) |
63300a00 | 2541 | { |
deee69a1 RH |
2542 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); |
2543 | #ifndef CONFIG_USER_ONLY | |
63300a00 RH |
2544 | TCGv_tl addr; |
2545 | TCGv_reg ofs; | |
2546 | ||
63300a00 RH |
2547 | nullify_over(ctx); |
2548 | ||
deee69a1 RH |
2549 | form_gva(ctx, &addr, &ofs, a->b, a->x, 0, 0, a->sp, a->m, false); |
2550 | if (a->m) { | |
2551 | save_gpr(ctx, a->b, ofs); | |
63300a00 | 2552 | } |
deee69a1 | 2553 | if (a->local) { |
ad75a51e | 2554 | gen_helper_ptlbe(tcg_env); |
63300a00 | 2555 | } else { |
ad75a51e | 2556 | gen_helper_ptlb(tcg_env, addr); |
63300a00 RH |
2557 | } |
2558 | ||
2559 | /* Exit TB for TLB change if mmu is enabled. */ | |
6797c315 NH |
2560 | if (ctx->tb_flags & PSW_C) { |
2561 | ctx->base.is_jmp = DISAS_IAQ_N_STALE; | |
2562 | } | |
2563 | return nullify_end(ctx); | |
2564 | #endif | |
2565 | } | |
2566 | ||
2567 | /* | |
2568 | * Implement the pcxl and pcxl2 Fast TLB Insert instructions. | |
2569 | * See | |
2570 | * https://parisc.wiki.kernel.org/images-parisc/a/a9/Pcxl2_ers.pdf | |
2571 | * page 13-9 (195/206) | |
2572 | */ | |
2573 | static bool trans_ixtlbxf(DisasContext *ctx, arg_ixtlbxf *a) | |
2574 | { | |
2575 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); | |
2576 | #ifndef CONFIG_USER_ONLY | |
2577 | TCGv_tl addr, atl, stl; | |
2578 | TCGv_reg reg; | |
2579 | ||
2580 | nullify_over(ctx); | |
2581 | ||
2582 | /* | |
2583 | * FIXME: | |
2584 | * if (not (pcxl or pcxl2)) | |
2585 | * return gen_illegal(ctx); | |
2586 | * | |
2587 | * Note for future: these are 32-bit systems; no hppa64. | |
2588 | */ | |
2589 | ||
2590 | atl = tcg_temp_new_tl(); | |
2591 | stl = tcg_temp_new_tl(); | |
2592 | addr = tcg_temp_new_tl(); | |
2593 | ||
ad75a51e | 2594 | tcg_gen_ld32u_i64(stl, tcg_env, |
6797c315 NH |
2595 | a->data ? offsetof(CPUHPPAState, cr[CR_ISR]) |
2596 | : offsetof(CPUHPPAState, cr[CR_IIASQ])); | |
ad75a51e | 2597 | tcg_gen_ld32u_i64(atl, tcg_env, |
6797c315 NH |
2598 | a->data ? offsetof(CPUHPPAState, cr[CR_IOR]) |
2599 | : offsetof(CPUHPPAState, cr[CR_IIAOQ])); | |
2600 | tcg_gen_shli_i64(stl, stl, 32); | |
2601 | tcg_gen_or_tl(addr, atl, stl); | |
6797c315 NH |
2602 | |
2603 | reg = load_gpr(ctx, a->r); | |
2604 | if (a->addr) { | |
ad75a51e | 2605 | gen_helper_itlba(tcg_env, addr, reg); |
6797c315 | 2606 | } else { |
ad75a51e | 2607 | gen_helper_itlbp(tcg_env, addr, reg); |
6797c315 | 2608 | } |
6797c315 NH |
2609 | |
2610 | /* Exit TB for TLB change if mmu is enabled. */ | |
32dc7569 | 2611 | if (ctx->tb_flags & PSW_C) { |
31234768 RH |
2612 | ctx->base.is_jmp = DISAS_IAQ_N_STALE; |
2613 | } | |
2614 | return nullify_end(ctx); | |
deee69a1 | 2615 | #endif |
63300a00 | 2616 | } |
2dfcca9f | 2617 | |
deee69a1 | 2618 | static bool trans_lpa(DisasContext *ctx, arg_ldst *a) |
2dfcca9f | 2619 | { |
deee69a1 RH |
2620 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); |
2621 | #ifndef CONFIG_USER_ONLY | |
2dfcca9f RH |
2622 | TCGv_tl vaddr; |
2623 | TCGv_reg ofs, paddr; | |
2624 | ||
2dfcca9f RH |
2625 | nullify_over(ctx); |
2626 | ||
deee69a1 | 2627 | form_gva(ctx, &vaddr, &ofs, a->b, a->x, 0, 0, a->sp, a->m, false); |
2dfcca9f RH |
2628 | |
2629 | paddr = tcg_temp_new(); | |
ad75a51e | 2630 | gen_helper_lpa(paddr, tcg_env, vaddr); |
2dfcca9f RH |
2631 | |
2632 | /* Note that physical address result overrides base modification. */ | |
deee69a1 RH |
2633 | if (a->m) { |
2634 | save_gpr(ctx, a->b, ofs); | |
2dfcca9f | 2635 | } |
deee69a1 | 2636 | save_gpr(ctx, a->t, paddr); |
2dfcca9f | 2637 | |
31234768 | 2638 | return nullify_end(ctx); |
deee69a1 | 2639 | #endif |
2dfcca9f | 2640 | } |
43a97b81 | 2641 | |
deee69a1 | 2642 | static bool trans_lci(DisasContext *ctx, arg_lci *a) |
43a97b81 | 2643 | { |
43a97b81 RH |
2644 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); |
2645 | ||
2646 | /* The Coherence Index is an implementation-defined function of the | |
2647 | physical address. Two addresses with the same CI have a coherent | |
2648 | view of the cache. Our implementation is to return 0 for all, | |
2649 | since the entire address space is coherent. */ | |
29dd6f64 | 2650 | save_gpr(ctx, a->t, tcg_constant_reg(0)); |
43a97b81 | 2651 | |
31234768 RH |
2652 | cond_free(&ctx->null_cond); |
2653 | return true; | |
43a97b81 | 2654 | } |
98a9cb79 | 2655 | |
faf97ba1 | 2656 | static bool trans_add(DisasContext *ctx, arg_rrr_cf_d_sh *a) |
b2167459 | 2657 | { |
0c982a28 RH |
2658 | return do_add_reg(ctx, a, false, false, false, false); |
2659 | } | |
b2167459 | 2660 | |
faf97ba1 | 2661 | static bool trans_add_l(DisasContext *ctx, arg_rrr_cf_d_sh *a) |
0c982a28 RH |
2662 | { |
2663 | return do_add_reg(ctx, a, true, false, false, false); | |
2664 | } | |
b2167459 | 2665 | |
faf97ba1 | 2666 | static bool trans_add_tsv(DisasContext *ctx, arg_rrr_cf_d_sh *a) |
0c982a28 RH |
2667 | { |
2668 | return do_add_reg(ctx, a, false, true, false, false); | |
b2167459 RH |
2669 | } |
2670 | ||
faf97ba1 | 2671 | static bool trans_add_c(DisasContext *ctx, arg_rrr_cf_d_sh *a) |
b2167459 | 2672 | { |
0c982a28 RH |
2673 | return do_add_reg(ctx, a, false, false, false, true); |
2674 | } | |
b2167459 | 2675 | |
faf97ba1 | 2676 | static bool trans_add_c_tsv(DisasContext *ctx, arg_rrr_cf_d_sh *a) |
0c982a28 RH |
2677 | { |
2678 | return do_add_reg(ctx, a, false, true, false, true); | |
2679 | } | |
b2167459 | 2680 | |
63c427c6 | 2681 | static bool trans_sub(DisasContext *ctx, arg_rrr_cf_d *a) |
0c982a28 RH |
2682 | { |
2683 | return do_sub_reg(ctx, a, false, false, false); | |
b2167459 RH |
2684 | } |
2685 | ||
63c427c6 | 2686 | static bool trans_sub_tsv(DisasContext *ctx, arg_rrr_cf_d *a) |
b2167459 | 2687 | { |
0c982a28 RH |
2688 | return do_sub_reg(ctx, a, true, false, false); |
2689 | } | |
b2167459 | 2690 | |
63c427c6 | 2691 | static bool trans_sub_tc(DisasContext *ctx, arg_rrr_cf_d *a) |
0c982a28 RH |
2692 | { |
2693 | return do_sub_reg(ctx, a, false, false, true); | |
b2167459 RH |
2694 | } |
2695 | ||
63c427c6 | 2696 | static bool trans_sub_tsv_tc(DisasContext *ctx, arg_rrr_cf_d *a) |
b2167459 | 2697 | { |
0c982a28 RH |
2698 | return do_sub_reg(ctx, a, true, false, true); |
2699 | } | |
2700 | ||
63c427c6 | 2701 | static bool trans_sub_b(DisasContext *ctx, arg_rrr_cf_d *a) |
0c982a28 RH |
2702 | { |
2703 | return do_sub_reg(ctx, a, false, true, false); | |
2704 | } | |
2705 | ||
63c427c6 | 2706 | static bool trans_sub_b_tsv(DisasContext *ctx, arg_rrr_cf_d *a) |
0c982a28 RH |
2707 | { |
2708 | return do_sub_reg(ctx, a, true, true, false); | |
2709 | } | |
2710 | ||
fa8e3bed | 2711 | static bool trans_andcm(DisasContext *ctx, arg_rrr_cf_d *a) |
0c982a28 RH |
2712 | { |
2713 | return do_log_reg(ctx, a, tcg_gen_andc_reg); | |
2714 | } | |
2715 | ||
fa8e3bed | 2716 | static bool trans_and(DisasContext *ctx, arg_rrr_cf_d *a) |
0c982a28 RH |
2717 | { |
2718 | return do_log_reg(ctx, a, tcg_gen_and_reg); | |
2719 | } | |
2720 | ||
fa8e3bed | 2721 | static bool trans_or(DisasContext *ctx, arg_rrr_cf_d *a) |
0c982a28 RH |
2722 | { |
2723 | if (a->cf == 0) { | |
2724 | unsigned r2 = a->r2; | |
2725 | unsigned r1 = a->r1; | |
2726 | unsigned rt = a->t; | |
b2167459 | 2727 | |
7aee8189 RH |
2728 | if (rt == 0) { /* NOP */ |
2729 | cond_free(&ctx->null_cond); | |
2730 | return true; | |
2731 | } | |
2732 | if (r2 == 0) { /* COPY */ | |
2733 | if (r1 == 0) { | |
2734 | TCGv_reg dest = dest_gpr(ctx, rt); | |
2735 | tcg_gen_movi_reg(dest, 0); | |
2736 | save_gpr(ctx, rt, dest); | |
2737 | } else { | |
2738 | save_gpr(ctx, rt, cpu_gr[r1]); | |
2739 | } | |
2740 | cond_free(&ctx->null_cond); | |
2741 | return true; | |
2742 | } | |
2743 | #ifndef CONFIG_USER_ONLY | |
2744 | /* These are QEMU extensions and are nops in the real architecture: | |
2745 | * | |
2746 | * or %r10,%r10,%r10 -- idle loop; wait for interrupt | |
2747 | * or %r31,%r31,%r31 -- death loop; offline cpu | |
2748 | * currently implemented as idle. | |
2749 | */ | |
2750 | if ((rt == 10 || rt == 31) && r1 == rt && r2 == rt) { /* PAUSE */ | |
7aee8189 RH |
2751 | /* No need to check for supervisor, as userland can only pause |
2752 | until the next timer interrupt. */ | |
2753 | nullify_over(ctx); | |
2754 | ||
2755 | /* Advance the instruction queue. */ | |
741322f4 RH |
2756 | copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); |
2757 | copy_iaoq_entry(ctx, cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var); | |
7aee8189 RH |
2758 | nullify_set(ctx, 0); |
2759 | ||
2760 | /* Tell the qemu main loop to halt until this cpu has work. */ | |
ad75a51e | 2761 | tcg_gen_st_i32(tcg_constant_i32(1), tcg_env, |
29dd6f64 | 2762 | offsetof(CPUState, halted) - offsetof(HPPACPU, env)); |
7aee8189 RH |
2763 | gen_excp_1(EXCP_HALTED); |
2764 | ctx->base.is_jmp = DISAS_NORETURN; | |
2765 | ||
2766 | return nullify_end(ctx); | |
2767 | } | |
2768 | #endif | |
b2167459 | 2769 | } |
0c982a28 RH |
2770 | return do_log_reg(ctx, a, tcg_gen_or_reg); |
2771 | } | |
7aee8189 | 2772 | |
fa8e3bed | 2773 | static bool trans_xor(DisasContext *ctx, arg_rrr_cf_d *a) |
0c982a28 RH |
2774 | { |
2775 | return do_log_reg(ctx, a, tcg_gen_xor_reg); | |
b2167459 RH |
2776 | } |
2777 | ||
345aa35f | 2778 | static bool trans_cmpclr(DisasContext *ctx, arg_rrr_cf_d *a) |
b2167459 | 2779 | { |
eaa3783b | 2780 | TCGv_reg tcg_r1, tcg_r2; |
b2167459 | 2781 | |
0c982a28 | 2782 | if (a->cf) { |
b2167459 RH |
2783 | nullify_over(ctx); |
2784 | } | |
0c982a28 RH |
2785 | tcg_r1 = load_gpr(ctx, a->r1); |
2786 | tcg_r2 = load_gpr(ctx, a->r2); | |
345aa35f | 2787 | do_cmpclr(ctx, a->t, tcg_r1, tcg_r2, a->cf, a->d); |
31234768 | 2788 | return nullify_end(ctx); |
b2167459 RH |
2789 | } |
2790 | ||
af240753 | 2791 | static bool trans_uxor(DisasContext *ctx, arg_rrr_cf_d *a) |
b2167459 | 2792 | { |
eaa3783b | 2793 | TCGv_reg tcg_r1, tcg_r2; |
b2167459 | 2794 | |
0c982a28 | 2795 | if (a->cf) { |
b2167459 RH |
2796 | nullify_over(ctx); |
2797 | } | |
0c982a28 RH |
2798 | tcg_r1 = load_gpr(ctx, a->r1); |
2799 | tcg_r2 = load_gpr(ctx, a->r2); | |
af240753 | 2800 | do_unit(ctx, a->t, tcg_r1, tcg_r2, a->cf, a->d, false, tcg_gen_xor_reg); |
31234768 | 2801 | return nullify_end(ctx); |
b2167459 RH |
2802 | } |
2803 | ||
af240753 | 2804 | static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf_d *a, bool is_tc) |
b2167459 | 2805 | { |
eaa3783b | 2806 | TCGv_reg tcg_r1, tcg_r2, tmp; |
b2167459 | 2807 | |
0c982a28 | 2808 | if (a->cf) { |
b2167459 RH |
2809 | nullify_over(ctx); |
2810 | } | |
0c982a28 RH |
2811 | tcg_r1 = load_gpr(ctx, a->r1); |
2812 | tcg_r2 = load_gpr(ctx, a->r2); | |
e12c6309 | 2813 | tmp = tcg_temp_new(); |
eaa3783b | 2814 | tcg_gen_not_reg(tmp, tcg_r2); |
af240753 | 2815 | do_unit(ctx, a->t, tcg_r1, tmp, a->cf, a->d, is_tc, tcg_gen_add_reg); |
31234768 | 2816 | return nullify_end(ctx); |
b2167459 RH |
2817 | } |
2818 | ||
af240753 | 2819 | static bool trans_uaddcm(DisasContext *ctx, arg_rrr_cf_d *a) |
0c982a28 RH |
2820 | { |
2821 | return do_uaddcm(ctx, a, false); | |
2822 | } | |
2823 | ||
af240753 | 2824 | static bool trans_uaddcm_tc(DisasContext *ctx, arg_rrr_cf_d *a) |
0c982a28 RH |
2825 | { |
2826 | return do_uaddcm(ctx, a, true); | |
2827 | } | |
2828 | ||
af240753 | 2829 | static bool do_dcor(DisasContext *ctx, arg_rr_cf_d *a, bool is_i) |
b2167459 | 2830 | { |
eaa3783b | 2831 | TCGv_reg tmp; |
b2167459 RH |
2832 | |
2833 | nullify_over(ctx); | |
2834 | ||
e12c6309 | 2835 | tmp = tcg_temp_new(); |
eaa3783b | 2836 | tcg_gen_shri_reg(tmp, cpu_psw_cb, 3); |
b2167459 | 2837 | if (!is_i) { |
eaa3783b | 2838 | tcg_gen_not_reg(tmp, tmp); |
b2167459 | 2839 | } |
af240753 | 2840 | tcg_gen_andi_reg(tmp, tmp, (target_ureg)0x1111111111111111ull); |
eaa3783b | 2841 | tcg_gen_muli_reg(tmp, tmp, 6); |
af240753 | 2842 | do_unit(ctx, a->t, load_gpr(ctx, a->r), tmp, a->cf, a->d, false, |
31234768 | 2843 | is_i ? tcg_gen_add_reg : tcg_gen_sub_reg); |
31234768 | 2844 | return nullify_end(ctx); |
b2167459 RH |
2845 | } |
2846 | ||
af240753 | 2847 | static bool trans_dcor(DisasContext *ctx, arg_rr_cf_d *a) |
0c982a28 RH |
2848 | { |
2849 | return do_dcor(ctx, a, false); | |
2850 | } | |
2851 | ||
af240753 | 2852 | static bool trans_dcor_i(DisasContext *ctx, arg_rr_cf_d *a) |
0c982a28 RH |
2853 | { |
2854 | return do_dcor(ctx, a, true); | |
2855 | } | |
2856 | ||
2857 | static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a) | |
b2167459 | 2858 | { |
eaa3783b | 2859 | TCGv_reg dest, add1, add2, addc, zero, in1, in2; |
72ca8753 | 2860 | TCGv_reg cout; |
b2167459 RH |
2861 | |
2862 | nullify_over(ctx); | |
2863 | ||
0c982a28 RH |
2864 | in1 = load_gpr(ctx, a->r1); |
2865 | in2 = load_gpr(ctx, a->r2); | |
b2167459 RH |
2866 | |
2867 | add1 = tcg_temp_new(); | |
2868 | add2 = tcg_temp_new(); | |
2869 | addc = tcg_temp_new(); | |
2870 | dest = tcg_temp_new(); | |
29dd6f64 | 2871 | zero = tcg_constant_reg(0); |
b2167459 RH |
2872 | |
2873 | /* Form R1 << 1 | PSW[CB]{8}. */ | |
eaa3783b | 2874 | tcg_gen_add_reg(add1, in1, in1); |
72ca8753 | 2875 | tcg_gen_add_reg(add1, add1, get_psw_carry(ctx, false)); |
b2167459 | 2876 | |
72ca8753 RH |
2877 | /* |
2878 | * Add or subtract R2, depending on PSW[V]. Proper computation of | |
2879 | * carry requires that we subtract via + ~R2 + 1, as described in | |
2880 | * the manual. By extracting and masking V, we can produce the | |
2881 | * proper inputs to the addition without movcond. | |
2882 | */ | |
2883 | tcg_gen_sextract_reg(addc, cpu_psw_v, 31, 1); | |
eaa3783b RH |
2884 | tcg_gen_xor_reg(add2, in2, addc); |
2885 | tcg_gen_andi_reg(addc, addc, 1); | |
72ca8753 RH |
2886 | |
2887 | tcg_gen_add2_reg(dest, cpu_psw_cb_msb, add1, zero, add2, zero); | |
2888 | tcg_gen_add2_reg(dest, cpu_psw_cb_msb, dest, cpu_psw_cb_msb, addc, zero); | |
b2167459 | 2889 | |
b2167459 | 2890 | /* Write back the result register. */ |
0c982a28 | 2891 | save_gpr(ctx, a->t, dest); |
b2167459 RH |
2892 | |
2893 | /* Write back PSW[CB]. */ | |
eaa3783b RH |
2894 | tcg_gen_xor_reg(cpu_psw_cb, add1, add2); |
2895 | tcg_gen_xor_reg(cpu_psw_cb, cpu_psw_cb, dest); | |
b2167459 RH |
2896 | |
2897 | /* Write back PSW[V] for the division step. */ | |
72ca8753 RH |
2898 | cout = get_psw_carry(ctx, false); |
2899 | tcg_gen_neg_reg(cpu_psw_v, cout); | |
eaa3783b | 2900 | tcg_gen_xor_reg(cpu_psw_v, cpu_psw_v, in2); |
b2167459 RH |
2901 | |
2902 | /* Install the new nullification. */ | |
0c982a28 | 2903 | if (a->cf) { |
eaa3783b | 2904 | TCGv_reg sv = NULL; |
b47a4a02 | 2905 | if (cond_need_sv(a->cf >> 1)) { |
b2167459 RH |
2906 | /* ??? The lshift is supposed to contribute to overflow. */ |
2907 | sv = do_add_sv(ctx, dest, add1, add2); | |
2908 | } | |
a751eb31 | 2909 | ctx->null_cond = do_cond(ctx, a->cf, false, dest, cout, sv); |
b2167459 RH |
2910 | } |
2911 | ||
31234768 | 2912 | return nullify_end(ctx); |
b2167459 RH |
2913 | } |
2914 | ||
0588e061 | 2915 | static bool trans_addi(DisasContext *ctx, arg_rri_cf *a) |
b2167459 | 2916 | { |
0588e061 RH |
2917 | return do_add_imm(ctx, a, false, false); |
2918 | } | |
b2167459 | 2919 | |
0588e061 RH |
2920 | static bool trans_addi_tsv(DisasContext *ctx, arg_rri_cf *a) |
2921 | { | |
2922 | return do_add_imm(ctx, a, true, false); | |
b2167459 RH |
2923 | } |
2924 | ||
0588e061 | 2925 | static bool trans_addi_tc(DisasContext *ctx, arg_rri_cf *a) |
b2167459 | 2926 | { |
0588e061 RH |
2927 | return do_add_imm(ctx, a, false, true); |
2928 | } | |
b2167459 | 2929 | |
0588e061 RH |
2930 | static bool trans_addi_tc_tsv(DisasContext *ctx, arg_rri_cf *a) |
2931 | { | |
2932 | return do_add_imm(ctx, a, true, true); | |
2933 | } | |
b2167459 | 2934 | |
0588e061 RH |
2935 | static bool trans_subi(DisasContext *ctx, arg_rri_cf *a) |
2936 | { | |
2937 | return do_sub_imm(ctx, a, false); | |
2938 | } | |
b2167459 | 2939 | |
0588e061 RH |
2940 | static bool trans_subi_tsv(DisasContext *ctx, arg_rri_cf *a) |
2941 | { | |
2942 | return do_sub_imm(ctx, a, true); | |
b2167459 RH |
2943 | } |
2944 | ||
345aa35f | 2945 | static bool trans_cmpiclr(DisasContext *ctx, arg_rri_cf_d *a) |
b2167459 | 2946 | { |
eaa3783b | 2947 | TCGv_reg tcg_im, tcg_r2; |
b2167459 | 2948 | |
0588e061 | 2949 | if (a->cf) { |
b2167459 RH |
2950 | nullify_over(ctx); |
2951 | } | |
2952 | ||
d4e58033 | 2953 | tcg_im = tcg_constant_reg(a->i); |
0588e061 | 2954 | tcg_r2 = load_gpr(ctx, a->r); |
345aa35f | 2955 | do_cmpclr(ctx, a->t, tcg_im, tcg_r2, a->cf, a->d); |
b2167459 | 2956 | |
31234768 | 2957 | return nullify_end(ctx); |
b2167459 RH |
2958 | } |
2959 | ||
1cd012a5 | 2960 | static bool trans_ld(DisasContext *ctx, arg_ldst *a) |
96d6407f | 2961 | { |
0786a3b6 HD |
2962 | if (unlikely(TARGET_REGISTER_BITS == 32 && a->size > MO_32)) { |
2963 | return gen_illegal(ctx); | |
2964 | } else { | |
2965 | return do_load(ctx, a->t, a->b, a->x, a->scale ? a->size : 0, | |
1cd012a5 | 2966 | a->disp, a->sp, a->m, a->size | MO_TE); |
0786a3b6 | 2967 | } |
96d6407f RH |
2968 | } |
2969 | ||
1cd012a5 | 2970 | static bool trans_st(DisasContext *ctx, arg_ldst *a) |
96d6407f | 2971 | { |
1cd012a5 | 2972 | assert(a->x == 0 && a->scale == 0); |
0786a3b6 HD |
2973 | if (unlikely(TARGET_REGISTER_BITS == 32 && a->size > MO_32)) { |
2974 | return gen_illegal(ctx); | |
2975 | } else { | |
2976 | return do_store(ctx, a->t, a->b, a->disp, a->sp, a->m, a->size | MO_TE); | |
2977 | } | |
96d6407f RH |
2978 | } |
2979 | ||
1cd012a5 | 2980 | static bool trans_ldc(DisasContext *ctx, arg_ldst *a) |
96d6407f | 2981 | { |
b1af755c | 2982 | MemOp mop = MO_TE | MO_ALIGN | a->size; |
86f8d05f RH |
2983 | TCGv_reg zero, dest, ofs; |
2984 | TCGv_tl addr; | |
96d6407f | 2985 | |
51416c4e RH |
2986 | if (unlikely(TARGET_REGISTER_BITS == 32 && a->size > MO_32)) { |
2987 | return gen_illegal(ctx); | |
2988 | } | |
2989 | ||
96d6407f RH |
2990 | nullify_over(ctx); |
2991 | ||
1cd012a5 | 2992 | if (a->m) { |
86f8d05f RH |
2993 | /* Base register modification. Make sure if RT == RB, |
2994 | we see the result of the load. */ | |
e12c6309 | 2995 | dest = tcg_temp_new(); |
96d6407f | 2996 | } else { |
1cd012a5 | 2997 | dest = dest_gpr(ctx, a->t); |
96d6407f RH |
2998 | } |
2999 | ||
1cd012a5 RH |
3000 | form_gva(ctx, &addr, &ofs, a->b, a->x, a->scale ? a->size : 0, |
3001 | a->disp, a->sp, a->m, ctx->mmu_idx == MMU_PHYS_IDX); | |
b1af755c RH |
3002 | |
3003 | /* | |
3004 | * For hppa1.1, LDCW is undefined unless aligned mod 16. | |
3005 | * However actual hardware succeeds with aligned mod 4. | |
3006 | * Detect this case and log a GUEST_ERROR. | |
3007 | * | |
3008 | * TODO: HPPA64 relaxes the over-alignment requirement | |
3009 | * with the ,co completer. | |
3010 | */ | |
3011 | gen_helper_ldc_check(addr); | |
3012 | ||
29dd6f64 | 3013 | zero = tcg_constant_reg(0); |
86f8d05f | 3014 | tcg_gen_atomic_xchg_reg(dest, addr, zero, ctx->mmu_idx, mop); |
b1af755c | 3015 | |
1cd012a5 RH |
3016 | if (a->m) { |
3017 | save_gpr(ctx, a->b, ofs); | |
96d6407f | 3018 | } |
1cd012a5 | 3019 | save_gpr(ctx, a->t, dest); |
96d6407f | 3020 | |
31234768 | 3021 | return nullify_end(ctx); |
96d6407f RH |
3022 | } |
3023 | ||
1cd012a5 | 3024 | static bool trans_stby(DisasContext *ctx, arg_stby *a) |
96d6407f | 3025 | { |
86f8d05f RH |
3026 | TCGv_reg ofs, val; |
3027 | TCGv_tl addr; | |
96d6407f RH |
3028 | |
3029 | nullify_over(ctx); | |
3030 | ||
1cd012a5 | 3031 | form_gva(ctx, &addr, &ofs, a->b, 0, 0, a->disp, a->sp, a->m, |
86f8d05f | 3032 | ctx->mmu_idx == MMU_PHYS_IDX); |
1cd012a5 RH |
3033 | val = load_gpr(ctx, a->r); |
3034 | if (a->a) { | |
f9f46db4 | 3035 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { |
ad75a51e | 3036 | gen_helper_stby_e_parallel(tcg_env, addr, val); |
f9f46db4 | 3037 | } else { |
ad75a51e | 3038 | gen_helper_stby_e(tcg_env, addr, val); |
f9f46db4 | 3039 | } |
96d6407f | 3040 | } else { |
f9f46db4 | 3041 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { |
ad75a51e | 3042 | gen_helper_stby_b_parallel(tcg_env, addr, val); |
f9f46db4 | 3043 | } else { |
ad75a51e | 3044 | gen_helper_stby_b(tcg_env, addr, val); |
f9f46db4 | 3045 | } |
96d6407f | 3046 | } |
1cd012a5 | 3047 | if (a->m) { |
86f8d05f | 3048 | tcg_gen_andi_reg(ofs, ofs, ~3); |
1cd012a5 | 3049 | save_gpr(ctx, a->b, ofs); |
96d6407f | 3050 | } |
96d6407f | 3051 | |
31234768 | 3052 | return nullify_end(ctx); |
96d6407f RH |
3053 | } |
3054 | ||
1cd012a5 | 3055 | static bool trans_lda(DisasContext *ctx, arg_ldst *a) |
d0a851cc RH |
3056 | { |
3057 | int hold_mmu_idx = ctx->mmu_idx; | |
d0a851cc RH |
3058 | |
3059 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); | |
d0a851cc | 3060 | ctx->mmu_idx = MMU_PHYS_IDX; |
1cd012a5 | 3061 | trans_ld(ctx, a); |
d0a851cc | 3062 | ctx->mmu_idx = hold_mmu_idx; |
31234768 | 3063 | return true; |
d0a851cc RH |
3064 | } |
3065 | ||
1cd012a5 | 3066 | static bool trans_sta(DisasContext *ctx, arg_ldst *a) |
d0a851cc RH |
3067 | { |
3068 | int hold_mmu_idx = ctx->mmu_idx; | |
d0a851cc RH |
3069 | |
3070 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); | |
d0a851cc | 3071 | ctx->mmu_idx = MMU_PHYS_IDX; |
1cd012a5 | 3072 | trans_st(ctx, a); |
d0a851cc | 3073 | ctx->mmu_idx = hold_mmu_idx; |
31234768 | 3074 | return true; |
d0a851cc | 3075 | } |
95412a61 | 3076 | |
0588e061 | 3077 | static bool trans_ldil(DisasContext *ctx, arg_ldil *a) |
b2167459 | 3078 | { |
0588e061 | 3079 | TCGv_reg tcg_rt = dest_gpr(ctx, a->t); |
b2167459 | 3080 | |
0588e061 RH |
3081 | tcg_gen_movi_reg(tcg_rt, a->i); |
3082 | save_gpr(ctx, a->t, tcg_rt); | |
b2167459 | 3083 | cond_free(&ctx->null_cond); |
31234768 | 3084 | return true; |
b2167459 RH |
3085 | } |
3086 | ||
0588e061 | 3087 | static bool trans_addil(DisasContext *ctx, arg_addil *a) |
b2167459 | 3088 | { |
0588e061 | 3089 | TCGv_reg tcg_rt = load_gpr(ctx, a->r); |
eaa3783b | 3090 | TCGv_reg tcg_r1 = dest_gpr(ctx, 1); |
b2167459 | 3091 | |
0588e061 | 3092 | tcg_gen_addi_reg(tcg_r1, tcg_rt, a->i); |
b2167459 RH |
3093 | save_gpr(ctx, 1, tcg_r1); |
3094 | cond_free(&ctx->null_cond); | |
31234768 | 3095 | return true; |
b2167459 RH |
3096 | } |
3097 | ||
0588e061 | 3098 | static bool trans_ldo(DisasContext *ctx, arg_ldo *a) |
b2167459 | 3099 | { |
0588e061 | 3100 | TCGv_reg tcg_rt = dest_gpr(ctx, a->t); |
b2167459 RH |
3101 | |
3102 | /* Special case rb == 0, for the LDI pseudo-op. | |
3103 | The COPY pseudo-op is handled for free within tcg_gen_addi_tl. */ | |
0588e061 RH |
3104 | if (a->b == 0) { |
3105 | tcg_gen_movi_reg(tcg_rt, a->i); | |
b2167459 | 3106 | } else { |
0588e061 | 3107 | tcg_gen_addi_reg(tcg_rt, cpu_gr[a->b], a->i); |
b2167459 | 3108 | } |
0588e061 | 3109 | save_gpr(ctx, a->t, tcg_rt); |
b2167459 | 3110 | cond_free(&ctx->null_cond); |
31234768 | 3111 | return true; |
b2167459 RH |
3112 | } |
3113 | ||
01afb7be | 3114 | static bool do_cmpb(DisasContext *ctx, unsigned r, TCGv_reg in1, |
e9efd4bc | 3115 | unsigned c, unsigned f, bool d, unsigned n, int disp) |
98cd9ca7 | 3116 | { |
01afb7be | 3117 | TCGv_reg dest, in2, sv; |
98cd9ca7 RH |
3118 | DisasCond cond; |
3119 | ||
98cd9ca7 | 3120 | in2 = load_gpr(ctx, r); |
e12c6309 | 3121 | dest = tcg_temp_new(); |
98cd9ca7 | 3122 | |
eaa3783b | 3123 | tcg_gen_sub_reg(dest, in1, in2); |
98cd9ca7 | 3124 | |
f764718d | 3125 | sv = NULL; |
b47a4a02 | 3126 | if (cond_need_sv(c)) { |
98cd9ca7 RH |
3127 | sv = do_sub_sv(ctx, dest, in1, in2); |
3128 | } | |
3129 | ||
4fe9533a | 3130 | cond = do_sub_cond(ctx, c * 2 + f, d, dest, in1, in2, sv); |
01afb7be | 3131 | return do_cbranch(ctx, disp, n, &cond); |
98cd9ca7 RH |
3132 | } |
3133 | ||
01afb7be | 3134 | static bool trans_cmpb(DisasContext *ctx, arg_cmpb *a) |
98cd9ca7 | 3135 | { |
e9efd4bc RH |
3136 | if (!ctx->is_pa20 && a->d) { |
3137 | return false; | |
3138 | } | |
01afb7be | 3139 | nullify_over(ctx); |
e9efd4bc RH |
3140 | return do_cmpb(ctx, a->r2, load_gpr(ctx, a->r1), |
3141 | a->c, a->f, a->d, a->n, a->disp); | |
01afb7be | 3142 | } |
98cd9ca7 | 3143 | |
01afb7be RH |
3144 | static bool trans_cmpbi(DisasContext *ctx, arg_cmpbi *a) |
3145 | { | |
c65c3ee1 RH |
3146 | if (!ctx->is_pa20 && a->d) { |
3147 | return false; | |
3148 | } | |
98cd9ca7 | 3149 | nullify_over(ctx); |
e9efd4bc | 3150 | return do_cmpb(ctx, a->r, tcg_constant_reg(a->i), |
c65c3ee1 | 3151 | a->c, a->f, a->d, a->n, a->disp); |
01afb7be RH |
3152 | } |
3153 | ||
3154 | static bool do_addb(DisasContext *ctx, unsigned r, TCGv_reg in1, | |
3155 | unsigned c, unsigned f, unsigned n, int disp) | |
3156 | { | |
bdcccc17 | 3157 | TCGv_reg dest, in2, sv, cb_cond; |
01afb7be | 3158 | DisasCond cond; |
bdcccc17 | 3159 | bool d = false; |
98cd9ca7 | 3160 | |
f25d3160 RH |
3161 | /* |
3162 | * For hppa64, the ADDB conditions change with PSW.W, | |
3163 | * dropping ZNV, SV, OD in favor of double-word EQ, LT, LE. | |
3164 | */ | |
3165 | if (ctx->tb_flags & PSW_W) { | |
3166 | d = c >= 5; | |
3167 | if (d) { | |
3168 | c &= 3; | |
3169 | } | |
3170 | } | |
3171 | ||
98cd9ca7 | 3172 | in2 = load_gpr(ctx, r); |
43675d20 | 3173 | dest = tcg_temp_new(); |
f764718d | 3174 | sv = NULL; |
bdcccc17 | 3175 | cb_cond = NULL; |
98cd9ca7 | 3176 | |
b47a4a02 | 3177 | if (cond_need_cb(c)) { |
bdcccc17 RH |
3178 | TCGv_reg cb = tcg_temp_new(); |
3179 | TCGv_reg cb_msb = tcg_temp_new(); | |
3180 | ||
eaa3783b RH |
3181 | tcg_gen_movi_reg(cb_msb, 0); |
3182 | tcg_gen_add2_reg(dest, cb_msb, in1, cb_msb, in2, cb_msb); | |
bdcccc17 RH |
3183 | tcg_gen_xor_reg(cb, in1, in2); |
3184 | tcg_gen_xor_reg(cb, cb, dest); | |
3185 | cb_cond = get_carry(ctx, d, cb, cb_msb); | |
b47a4a02 | 3186 | } else { |
eaa3783b | 3187 | tcg_gen_add_reg(dest, in1, in2); |
b47a4a02 SS |
3188 | } |
3189 | if (cond_need_sv(c)) { | |
98cd9ca7 | 3190 | sv = do_add_sv(ctx, dest, in1, in2); |
98cd9ca7 RH |
3191 | } |
3192 | ||
a751eb31 | 3193 | cond = do_cond(ctx, c * 2 + f, d, dest, cb_cond, sv); |
43675d20 | 3194 | save_gpr(ctx, r, dest); |
01afb7be | 3195 | return do_cbranch(ctx, disp, n, &cond); |
98cd9ca7 RH |
3196 | } |
3197 | ||
01afb7be RH |
3198 | static bool trans_addb(DisasContext *ctx, arg_addb *a) |
3199 | { | |
3200 | nullify_over(ctx); | |
3201 | return do_addb(ctx, a->r2, load_gpr(ctx, a->r1), a->c, a->f, a->n, a->disp); | |
3202 | } | |
3203 | ||
3204 | static bool trans_addbi(DisasContext *ctx, arg_addbi *a) | |
3205 | { | |
3206 | nullify_over(ctx); | |
d4e58033 | 3207 | return do_addb(ctx, a->r, tcg_constant_reg(a->i), a->c, a->f, a->n, a->disp); |
01afb7be RH |
3208 | } |
3209 | ||
3210 | static bool trans_bb_sar(DisasContext *ctx, arg_bb_sar *a) | |
98cd9ca7 | 3211 | { |
eaa3783b | 3212 | TCGv_reg tmp, tcg_r; |
98cd9ca7 RH |
3213 | DisasCond cond; |
3214 | ||
3215 | nullify_over(ctx); | |
3216 | ||
3217 | tmp = tcg_temp_new(); | |
01afb7be | 3218 | tcg_r = load_gpr(ctx, a->r); |
84e224d4 | 3219 | if (cond_need_ext(ctx, a->d)) { |
1e9ab9fb RH |
3220 | /* Force shift into [32,63] */ |
3221 | tcg_gen_ori_reg(tmp, cpu_sar, 32); | |
3222 | tcg_gen_shl_reg(tmp, tcg_r, tmp); | |
3223 | } else { | |
3224 | tcg_gen_shl_reg(tmp, tcg_r, cpu_sar); | |
3225 | } | |
98cd9ca7 | 3226 | |
1e9ab9fb | 3227 | cond = cond_make_0_tmp(a->c ? TCG_COND_GE : TCG_COND_LT, tmp); |
01afb7be | 3228 | return do_cbranch(ctx, a->disp, a->n, &cond); |
98cd9ca7 RH |
3229 | } |
3230 | ||
01afb7be RH |
3231 | static bool trans_bb_imm(DisasContext *ctx, arg_bb_imm *a) |
3232 | { | |
3233 | TCGv_reg tmp, tcg_r; | |
3234 | DisasCond cond; | |
1e9ab9fb | 3235 | int p; |
01afb7be RH |
3236 | |
3237 | nullify_over(ctx); | |
3238 | ||
3239 | tmp = tcg_temp_new(); | |
3240 | tcg_r = load_gpr(ctx, a->r); | |
84e224d4 | 3241 | p = a->p | (cond_need_ext(ctx, a->d) ? 32 : 0); |
1e9ab9fb | 3242 | tcg_gen_shli_reg(tmp, tcg_r, p); |
01afb7be RH |
3243 | |
3244 | cond = cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp); | |
01afb7be RH |
3245 | return do_cbranch(ctx, a->disp, a->n, &cond); |
3246 | } | |
3247 | ||
3248 | static bool trans_movb(DisasContext *ctx, arg_movb *a) | |
98cd9ca7 | 3249 | { |
eaa3783b | 3250 | TCGv_reg dest; |
98cd9ca7 RH |
3251 | DisasCond cond; |
3252 | ||
3253 | nullify_over(ctx); | |
3254 | ||
01afb7be RH |
3255 | dest = dest_gpr(ctx, a->r2); |
3256 | if (a->r1 == 0) { | |
eaa3783b | 3257 | tcg_gen_movi_reg(dest, 0); |
98cd9ca7 | 3258 | } else { |
01afb7be | 3259 | tcg_gen_mov_reg(dest, cpu_gr[a->r1]); |
98cd9ca7 RH |
3260 | } |
3261 | ||
4fa52edf RH |
3262 | /* All MOVB conditions are 32-bit. */ |
3263 | cond = do_sed_cond(ctx, a->c, false, dest); | |
01afb7be RH |
3264 | return do_cbranch(ctx, a->disp, a->n, &cond); |
3265 | } | |
3266 | ||
3267 | static bool trans_movbi(DisasContext *ctx, arg_movbi *a) | |
3268 | { | |
3269 | TCGv_reg dest; | |
3270 | DisasCond cond; | |
3271 | ||
3272 | nullify_over(ctx); | |
3273 | ||
3274 | dest = dest_gpr(ctx, a->r); | |
3275 | tcg_gen_movi_reg(dest, a->i); | |
3276 | ||
4fa52edf RH |
3277 | /* All MOVBI conditions are 32-bit. */ |
3278 | cond = do_sed_cond(ctx, a->c, false, dest); | |
01afb7be | 3279 | return do_cbranch(ctx, a->disp, a->n, &cond); |
98cd9ca7 RH |
3280 | } |
3281 | ||
30878590 | 3282 | static bool trans_shrpw_sar(DisasContext *ctx, arg_shrpw_sar *a) |
0b1347d2 | 3283 | { |
eaa3783b | 3284 | TCGv_reg dest; |
0b1347d2 | 3285 | |
30878590 | 3286 | if (a->c) { |
0b1347d2 RH |
3287 | nullify_over(ctx); |
3288 | } | |
3289 | ||
30878590 RH |
3290 | dest = dest_gpr(ctx, a->t); |
3291 | if (a->r1 == 0) { | |
3292 | tcg_gen_ext32u_reg(dest, load_gpr(ctx, a->r2)); | |
eaa3783b | 3293 | tcg_gen_shr_reg(dest, dest, cpu_sar); |
30878590 | 3294 | } else if (a->r1 == a->r2) { |
0b1347d2 | 3295 | TCGv_i32 t32 = tcg_temp_new_i32(); |
e1d635e8 RH |
3296 | TCGv_i32 s32 = tcg_temp_new_i32(); |
3297 | ||
30878590 | 3298 | tcg_gen_trunc_reg_i32(t32, load_gpr(ctx, a->r2)); |
e1d635e8 RH |
3299 | tcg_gen_trunc_reg_i32(s32, cpu_sar); |
3300 | tcg_gen_rotr_i32(t32, t32, s32); | |
eaa3783b | 3301 | tcg_gen_extu_i32_reg(dest, t32); |
0b1347d2 RH |
3302 | } else { |
3303 | TCGv_i64 t = tcg_temp_new_i64(); | |
3304 | TCGv_i64 s = tcg_temp_new_i64(); | |
3305 | ||
30878590 | 3306 | tcg_gen_concat_reg_i64(t, load_gpr(ctx, a->r2), load_gpr(ctx, a->r1)); |
eaa3783b | 3307 | tcg_gen_extu_reg_i64(s, cpu_sar); |
0b1347d2 | 3308 | tcg_gen_shr_i64(t, t, s); |
eaa3783b | 3309 | tcg_gen_trunc_i64_reg(dest, t); |
0b1347d2 | 3310 | } |
30878590 | 3311 | save_gpr(ctx, a->t, dest); |
0b1347d2 RH |
3312 | |
3313 | /* Install the new nullification. */ | |
3314 | cond_free(&ctx->null_cond); | |
30878590 | 3315 | if (a->c) { |
4fa52edf | 3316 | ctx->null_cond = do_sed_cond(ctx, a->c, false, dest); |
0b1347d2 | 3317 | } |
31234768 | 3318 | return nullify_end(ctx); |
0b1347d2 RH |
3319 | } |
3320 | ||
30878590 | 3321 | static bool trans_shrpw_imm(DisasContext *ctx, arg_shrpw_imm *a) |
0b1347d2 | 3322 | { |
30878590 | 3323 | unsigned sa = 31 - a->cpos; |
eaa3783b | 3324 | TCGv_reg dest, t2; |
0b1347d2 | 3325 | |
30878590 | 3326 | if (a->c) { |
0b1347d2 RH |
3327 | nullify_over(ctx); |
3328 | } | |
3329 | ||
30878590 RH |
3330 | dest = dest_gpr(ctx, a->t); |
3331 | t2 = load_gpr(ctx, a->r2); | |
05bfd4db RH |
3332 | if (a->r1 == 0) { |
3333 | tcg_gen_extract_reg(dest, t2, sa, 32 - sa); | |
3334 | } else if (TARGET_REGISTER_BITS == 32) { | |
3335 | tcg_gen_extract2_reg(dest, t2, cpu_gr[a->r1], sa); | |
3336 | } else if (a->r1 == a->r2) { | |
0b1347d2 | 3337 | TCGv_i32 t32 = tcg_temp_new_i32(); |
eaa3783b | 3338 | tcg_gen_trunc_reg_i32(t32, t2); |
0b1347d2 | 3339 | tcg_gen_rotri_i32(t32, t32, sa); |
eaa3783b | 3340 | tcg_gen_extu_i32_reg(dest, t32); |
0b1347d2 | 3341 | } else { |
05bfd4db RH |
3342 | TCGv_i64 t64 = tcg_temp_new_i64(); |
3343 | tcg_gen_concat_reg_i64(t64, t2, cpu_gr[a->r1]); | |
3344 | tcg_gen_shri_i64(t64, t64, sa); | |
3345 | tcg_gen_trunc_i64_reg(dest, t64); | |
0b1347d2 | 3346 | } |
30878590 | 3347 | save_gpr(ctx, a->t, dest); |
0b1347d2 RH |
3348 | |
3349 | /* Install the new nullification. */ | |
3350 | cond_free(&ctx->null_cond); | |
30878590 | 3351 | if (a->c) { |
4fa52edf | 3352 | ctx->null_cond = do_sed_cond(ctx, a->c, false, dest); |
0b1347d2 | 3353 | } |
31234768 | 3354 | return nullify_end(ctx); |
0b1347d2 RH |
3355 | } |
3356 | ||
30878590 | 3357 | static bool trans_extrw_sar(DisasContext *ctx, arg_extrw_sar *a) |
0b1347d2 | 3358 | { |
30878590 | 3359 | unsigned len = 32 - a->clen; |
eaa3783b | 3360 | TCGv_reg dest, src, tmp; |
0b1347d2 | 3361 | |
30878590 | 3362 | if (a->c) { |
0b1347d2 RH |
3363 | nullify_over(ctx); |
3364 | } | |
3365 | ||
30878590 RH |
3366 | dest = dest_gpr(ctx, a->t); |
3367 | src = load_gpr(ctx, a->r); | |
0b1347d2 RH |
3368 | tmp = tcg_temp_new(); |
3369 | ||
3370 | /* Recall that SAR is using big-endian bit numbering. */ | |
d781cb77 RH |
3371 | tcg_gen_andi_reg(tmp, cpu_sar, 31); |
3372 | tcg_gen_xori_reg(tmp, tmp, 31); | |
3373 | ||
30878590 | 3374 | if (a->se) { |
eaa3783b RH |
3375 | tcg_gen_sar_reg(dest, src, tmp); |
3376 | tcg_gen_sextract_reg(dest, dest, 0, len); | |
0b1347d2 | 3377 | } else { |
eaa3783b RH |
3378 | tcg_gen_shr_reg(dest, src, tmp); |
3379 | tcg_gen_extract_reg(dest, dest, 0, len); | |
0b1347d2 | 3380 | } |
30878590 | 3381 | save_gpr(ctx, a->t, dest); |
0b1347d2 RH |
3382 | |
3383 | /* Install the new nullification. */ | |
3384 | cond_free(&ctx->null_cond); | |
30878590 | 3385 | if (a->c) { |
4fa52edf | 3386 | ctx->null_cond = do_sed_cond(ctx, a->c, false, dest); |
0b1347d2 | 3387 | } |
31234768 | 3388 | return nullify_end(ctx); |
0b1347d2 RH |
3389 | } |
3390 | ||
30878590 | 3391 | static bool trans_extrw_imm(DisasContext *ctx, arg_extrw_imm *a) |
0b1347d2 | 3392 | { |
30878590 RH |
3393 | unsigned len = 32 - a->clen; |
3394 | unsigned cpos = 31 - a->pos; | |
eaa3783b | 3395 | TCGv_reg dest, src; |
0b1347d2 | 3396 | |
30878590 | 3397 | if (a->c) { |
0b1347d2 RH |
3398 | nullify_over(ctx); |
3399 | } | |
3400 | ||
30878590 RH |
3401 | dest = dest_gpr(ctx, a->t); |
3402 | src = load_gpr(ctx, a->r); | |
3403 | if (a->se) { | |
eaa3783b | 3404 | tcg_gen_sextract_reg(dest, src, cpos, len); |
0b1347d2 | 3405 | } else { |
eaa3783b | 3406 | tcg_gen_extract_reg(dest, src, cpos, len); |
0b1347d2 | 3407 | } |
30878590 | 3408 | save_gpr(ctx, a->t, dest); |
0b1347d2 RH |
3409 | |
3410 | /* Install the new nullification. */ | |
3411 | cond_free(&ctx->null_cond); | |
30878590 | 3412 | if (a->c) { |
4fa52edf | 3413 | ctx->null_cond = do_sed_cond(ctx, a->c, false, dest); |
0b1347d2 | 3414 | } |
31234768 | 3415 | return nullify_end(ctx); |
0b1347d2 RH |
3416 | } |
3417 | ||
72ae4f2b | 3418 | static bool trans_depi_imm(DisasContext *ctx, arg_depi_imm *a) |
0b1347d2 | 3419 | { |
72ae4f2b | 3420 | unsigned len, width; |
eaa3783b RH |
3421 | target_sreg mask0, mask1; |
3422 | TCGv_reg dest; | |
0b1347d2 | 3423 | |
72ae4f2b RH |
3424 | if (!ctx->is_pa20 && a->d) { |
3425 | return false; | |
3426 | } | |
30878590 | 3427 | if (a->c) { |
0b1347d2 RH |
3428 | nullify_over(ctx); |
3429 | } | |
72ae4f2b RH |
3430 | |
3431 | len = a->len; | |
3432 | width = a->d ? 64 : 32; | |
3433 | if (a->cpos + len > width) { | |
3434 | len = width - a->cpos; | |
0b1347d2 RH |
3435 | } |
3436 | ||
30878590 RH |
3437 | dest = dest_gpr(ctx, a->t); |
3438 | mask0 = deposit64(0, a->cpos, len, a->i); | |
3439 | mask1 = deposit64(-1, a->cpos, len, a->i); | |
0b1347d2 | 3440 | |
30878590 RH |
3441 | if (a->nz) { |
3442 | TCGv_reg src = load_gpr(ctx, a->t); | |
72ae4f2b RH |
3443 | tcg_gen_andi_reg(dest, src, mask1); |
3444 | tcg_gen_ori_reg(dest, dest, mask0); | |
0b1347d2 | 3445 | } else { |
eaa3783b | 3446 | tcg_gen_movi_reg(dest, mask0); |
0b1347d2 | 3447 | } |
30878590 | 3448 | save_gpr(ctx, a->t, dest); |
0b1347d2 RH |
3449 | |
3450 | /* Install the new nullification. */ | |
3451 | cond_free(&ctx->null_cond); | |
30878590 | 3452 | if (a->c) { |
72ae4f2b | 3453 | ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); |
0b1347d2 | 3454 | } |
31234768 | 3455 | return nullify_end(ctx); |
0b1347d2 RH |
3456 | } |
3457 | ||
72ae4f2b | 3458 | static bool trans_dep_imm(DisasContext *ctx, arg_dep_imm *a) |
0b1347d2 | 3459 | { |
30878590 | 3460 | unsigned rs = a->nz ? a->t : 0; |
72ae4f2b | 3461 | unsigned len, width; |
eaa3783b | 3462 | TCGv_reg dest, val; |
0b1347d2 | 3463 | |
72ae4f2b RH |
3464 | if (!ctx->is_pa20 && a->d) { |
3465 | return false; | |
3466 | } | |
30878590 | 3467 | if (a->c) { |
0b1347d2 RH |
3468 | nullify_over(ctx); |
3469 | } | |
72ae4f2b RH |
3470 | |
3471 | len = a->len; | |
3472 | width = a->d ? 64 : 32; | |
3473 | if (a->cpos + len > width) { | |
3474 | len = width - a->cpos; | |
0b1347d2 RH |
3475 | } |
3476 | ||
30878590 RH |
3477 | dest = dest_gpr(ctx, a->t); |
3478 | val = load_gpr(ctx, a->r); | |
0b1347d2 | 3479 | if (rs == 0) { |
30878590 | 3480 | tcg_gen_deposit_z_reg(dest, val, a->cpos, len); |
0b1347d2 | 3481 | } else { |
30878590 | 3482 | tcg_gen_deposit_reg(dest, cpu_gr[rs], val, a->cpos, len); |
0b1347d2 | 3483 | } |
30878590 | 3484 | save_gpr(ctx, a->t, dest); |
0b1347d2 RH |
3485 | |
3486 | /* Install the new nullification. */ | |
3487 | cond_free(&ctx->null_cond); | |
30878590 | 3488 | if (a->c) { |
72ae4f2b | 3489 | ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); |
0b1347d2 | 3490 | } |
31234768 | 3491 | return nullify_end(ctx); |
0b1347d2 RH |
3492 | } |
3493 | ||
72ae4f2b RH |
3494 | static bool do_dep_sar(DisasContext *ctx, unsigned rt, unsigned c, |
3495 | bool d, bool nz, unsigned len, TCGv_reg val) | |
0b1347d2 | 3496 | { |
0b1347d2 | 3497 | unsigned rs = nz ? rt : 0; |
72ae4f2b | 3498 | unsigned widthm1 = d ? 63 : 31; |
30878590 | 3499 | TCGv_reg mask, tmp, shift, dest; |
72ae4f2b | 3500 | target_ureg msb = 1ULL << (len - 1); |
0b1347d2 | 3501 | |
0b1347d2 RH |
3502 | dest = dest_gpr(ctx, rt); |
3503 | shift = tcg_temp_new(); | |
3504 | tmp = tcg_temp_new(); | |
3505 | ||
3506 | /* Convert big-endian bit numbering in SAR to left-shift. */ | |
72ae4f2b RH |
3507 | tcg_gen_andi_reg(shift, cpu_sar, widthm1); |
3508 | tcg_gen_xori_reg(shift, shift, widthm1); | |
0b1347d2 | 3509 | |
0992a930 RH |
3510 | mask = tcg_temp_new(); |
3511 | tcg_gen_movi_reg(mask, msb + (msb - 1)); | |
eaa3783b | 3512 | tcg_gen_and_reg(tmp, val, mask); |
0b1347d2 | 3513 | if (rs) { |
eaa3783b RH |
3514 | tcg_gen_shl_reg(mask, mask, shift); |
3515 | tcg_gen_shl_reg(tmp, tmp, shift); | |
3516 | tcg_gen_andc_reg(dest, cpu_gr[rs], mask); | |
3517 | tcg_gen_or_reg(dest, dest, tmp); | |
0b1347d2 | 3518 | } else { |
eaa3783b | 3519 | tcg_gen_shl_reg(dest, tmp, shift); |
0b1347d2 | 3520 | } |
0b1347d2 RH |
3521 | save_gpr(ctx, rt, dest); |
3522 | ||
3523 | /* Install the new nullification. */ | |
3524 | cond_free(&ctx->null_cond); | |
3525 | if (c) { | |
72ae4f2b | 3526 | ctx->null_cond = do_sed_cond(ctx, c, d, dest); |
0b1347d2 | 3527 | } |
31234768 | 3528 | return nullify_end(ctx); |
0b1347d2 RH |
3529 | } |
3530 | ||
72ae4f2b | 3531 | static bool trans_dep_sar(DisasContext *ctx, arg_dep_sar *a) |
30878590 | 3532 | { |
72ae4f2b RH |
3533 | if (!ctx->is_pa20 && a->d) { |
3534 | return false; | |
3535 | } | |
a6deecce SS |
3536 | if (a->c) { |
3537 | nullify_over(ctx); | |
3538 | } | |
72ae4f2b RH |
3539 | return do_dep_sar(ctx, a->t, a->c, a->d, a->nz, a->len, |
3540 | load_gpr(ctx, a->r)); | |
30878590 RH |
3541 | } |
3542 | ||
72ae4f2b | 3543 | static bool trans_depi_sar(DisasContext *ctx, arg_depi_sar *a) |
30878590 | 3544 | { |
72ae4f2b RH |
3545 | if (!ctx->is_pa20 && a->d) { |
3546 | return false; | |
3547 | } | |
a6deecce SS |
3548 | if (a->c) { |
3549 | nullify_over(ctx); | |
3550 | } | |
72ae4f2b RH |
3551 | return do_dep_sar(ctx, a->t, a->c, a->d, a->nz, a->len, |
3552 | tcg_constant_reg(a->i)); | |
30878590 | 3553 | } |
0b1347d2 | 3554 | |
8340f534 | 3555 | static bool trans_be(DisasContext *ctx, arg_be *a) |
98cd9ca7 | 3556 | { |
660eefe1 | 3557 | TCGv_reg tmp; |
98cd9ca7 | 3558 | |
c301f34e | 3559 | #ifdef CONFIG_USER_ONLY |
98cd9ca7 RH |
3560 | /* ??? It seems like there should be a good way of using |
3561 | "be disp(sr2, r0)", the canonical gateway entry mechanism | |
3562 | to our advantage. But that appears to be inconvenient to | |
3563 | manage along side branch delay slots. Therefore we handle | |
3564 | entry into the gateway page via absolute address. */ | |
98cd9ca7 RH |
3565 | /* Since we don't implement spaces, just branch. Do notice the special |
3566 | case of "be disp(*,r0)" using a direct branch to disp, so that we can | |
3567 | goto_tb to the TB containing the syscall. */ | |
8340f534 RH |
3568 | if (a->b == 0) { |
3569 | return do_dbranch(ctx, a->disp, a->l, a->n); | |
98cd9ca7 | 3570 | } |
c301f34e | 3571 | #else |
c301f34e | 3572 | nullify_over(ctx); |
660eefe1 RH |
3573 | #endif |
3574 | ||
e12c6309 | 3575 | tmp = tcg_temp_new(); |
8340f534 | 3576 | tcg_gen_addi_reg(tmp, load_gpr(ctx, a->b), a->disp); |
660eefe1 | 3577 | tmp = do_ibranch_priv(ctx, tmp); |
c301f34e RH |
3578 | |
3579 | #ifdef CONFIG_USER_ONLY | |
8340f534 | 3580 | return do_ibranch(ctx, tmp, a->l, a->n); |
c301f34e RH |
3581 | #else |
3582 | TCGv_i64 new_spc = tcg_temp_new_i64(); | |
3583 | ||
8340f534 RH |
3584 | load_spr(ctx, new_spc, a->sp); |
3585 | if (a->l) { | |
741322f4 | 3586 | copy_iaoq_entry(ctx, cpu_gr[31], ctx->iaoq_n, ctx->iaoq_n_var); |
c301f34e RH |
3587 | tcg_gen_mov_i64(cpu_sr[0], cpu_iasq_f); |
3588 | } | |
8340f534 | 3589 | if (a->n && use_nullify_skip(ctx)) { |
a0180973 RH |
3590 | copy_iaoq_entry(ctx, cpu_iaoq_f, -1, tmp); |
3591 | tcg_gen_addi_reg(tmp, tmp, 4); | |
3592 | copy_iaoq_entry(ctx, cpu_iaoq_b, -1, tmp); | |
c301f34e RH |
3593 | tcg_gen_mov_i64(cpu_iasq_f, new_spc); |
3594 | tcg_gen_mov_i64(cpu_iasq_b, cpu_iasq_f); | |
3595 | } else { | |
741322f4 | 3596 | copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); |
c301f34e RH |
3597 | if (ctx->iaoq_b == -1) { |
3598 | tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); | |
3599 | } | |
a0180973 | 3600 | copy_iaoq_entry(ctx, cpu_iaoq_b, -1, tmp); |
c301f34e | 3601 | tcg_gen_mov_i64(cpu_iasq_b, new_spc); |
8340f534 | 3602 | nullify_set(ctx, a->n); |
c301f34e | 3603 | } |
c301f34e | 3604 | tcg_gen_lookup_and_goto_ptr(); |
31234768 RH |
3605 | ctx->base.is_jmp = DISAS_NORETURN; |
3606 | return nullify_end(ctx); | |
c301f34e | 3607 | #endif |
98cd9ca7 RH |
3608 | } |
3609 | ||
8340f534 | 3610 | static bool trans_bl(DisasContext *ctx, arg_bl *a) |
98cd9ca7 | 3611 | { |
8340f534 | 3612 | return do_dbranch(ctx, iaoq_dest(ctx, a->disp), a->l, a->n); |
98cd9ca7 RH |
3613 | } |
3614 | ||
8340f534 | 3615 | static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) |
43e05652 | 3616 | { |
8340f534 | 3617 | target_ureg dest = iaoq_dest(ctx, a->disp); |
43e05652 | 3618 | |
6e5f5300 SS |
3619 | nullify_over(ctx); |
3620 | ||
43e05652 RH |
3621 | /* Make sure the caller hasn't done something weird with the queue. |
3622 | * ??? This is not quite the same as the PSW[B] bit, which would be | |
3623 | * expensive to track. Real hardware will trap for | |
3624 | * b gateway | |
3625 | * b gateway+4 (in delay slot of first branch) | |
3626 | * However, checking for a non-sequential instruction queue *will* | |
3627 | * diagnose the security hole | |
3628 | * b gateway | |
3629 | * b evil | |
3630 | * in which instructions at evil would run with increased privs. | |
3631 | */ | |
3632 | if (ctx->iaoq_b == -1 || ctx->iaoq_b != ctx->iaoq_f + 4) { | |
3633 | return gen_illegal(ctx); | |
3634 | } | |
3635 | ||
3636 | #ifndef CONFIG_USER_ONLY | |
3637 | if (ctx->tb_flags & PSW_C) { | |
b77af26e | 3638 | CPUHPPAState *env = cpu_env(ctx->cs); |
43e05652 RH |
3639 | int type = hppa_artype_for_page(env, ctx->base.pc_next); |
3640 | /* If we could not find a TLB entry, then we need to generate an | |
3641 | ITLB miss exception so the kernel will provide it. | |
3642 | The resulting TLB fill operation will invalidate this TB and | |
3643 | we will re-translate, at which point we *will* be able to find | |
3644 | the TLB entry and determine if this is in fact a gateway page. */ | |
3645 | if (type < 0) { | |
31234768 RH |
3646 | gen_excp(ctx, EXCP_ITLB_MISS); |
3647 | return true; | |
43e05652 RH |
3648 | } |
3649 | /* No change for non-gateway pages or for priv decrease. */ | |
3650 | if (type >= 4 && type - 4 < ctx->privilege) { | |
3651 | dest = deposit32(dest, 0, 2, type - 4); | |
3652 | } | |
3653 | } else { | |
3654 | dest &= -4; /* priv = 0 */ | |
3655 | } | |
3656 | #endif | |
3657 | ||
6e5f5300 SS |
3658 | if (a->l) { |
3659 | TCGv_reg tmp = dest_gpr(ctx, a->l); | |
3660 | if (ctx->privilege < 3) { | |
3661 | tcg_gen_andi_reg(tmp, tmp, -4); | |
3662 | } | |
3663 | tcg_gen_ori_reg(tmp, tmp, ctx->privilege); | |
3664 | save_gpr(ctx, a->l, tmp); | |
3665 | } | |
3666 | ||
3667 | return do_dbranch(ctx, dest, 0, a->n); | |
43e05652 RH |
3668 | } |
3669 | ||
8340f534 | 3670 | static bool trans_blr(DisasContext *ctx, arg_blr *a) |
98cd9ca7 | 3671 | { |
b35aec85 | 3672 | if (a->x) { |
e12c6309 | 3673 | TCGv_reg tmp = tcg_temp_new(); |
b35aec85 RH |
3674 | tcg_gen_shli_reg(tmp, load_gpr(ctx, a->x), 3); |
3675 | tcg_gen_addi_reg(tmp, tmp, ctx->iaoq_f + 8); | |
3676 | /* The computation here never changes privilege level. */ | |
3677 | return do_ibranch(ctx, tmp, a->l, a->n); | |
3678 | } else { | |
3679 | /* BLR R0,RX is a good way to load PC+8 into RX. */ | |
3680 | return do_dbranch(ctx, ctx->iaoq_f + 8, a->l, a->n); | |
3681 | } | |
98cd9ca7 RH |
3682 | } |
3683 | ||
8340f534 | 3684 | static bool trans_bv(DisasContext *ctx, arg_bv *a) |
98cd9ca7 | 3685 | { |
eaa3783b | 3686 | TCGv_reg dest; |
98cd9ca7 | 3687 | |
8340f534 RH |
3688 | if (a->x == 0) { |
3689 | dest = load_gpr(ctx, a->b); | |
98cd9ca7 | 3690 | } else { |
e12c6309 | 3691 | dest = tcg_temp_new(); |
8340f534 RH |
3692 | tcg_gen_shli_reg(dest, load_gpr(ctx, a->x), 3); |
3693 | tcg_gen_add_reg(dest, dest, load_gpr(ctx, a->b)); | |
98cd9ca7 | 3694 | } |
660eefe1 | 3695 | dest = do_ibranch_priv(ctx, dest); |
8340f534 | 3696 | return do_ibranch(ctx, dest, 0, a->n); |
98cd9ca7 RH |
3697 | } |
3698 | ||
8340f534 | 3699 | static bool trans_bve(DisasContext *ctx, arg_bve *a) |
98cd9ca7 | 3700 | { |
660eefe1 | 3701 | TCGv_reg dest; |
98cd9ca7 | 3702 | |
c301f34e | 3703 | #ifdef CONFIG_USER_ONLY |
8340f534 RH |
3704 | dest = do_ibranch_priv(ctx, load_gpr(ctx, a->b)); |
3705 | return do_ibranch(ctx, dest, a->l, a->n); | |
c301f34e RH |
3706 | #else |
3707 | nullify_over(ctx); | |
8340f534 | 3708 | dest = do_ibranch_priv(ctx, load_gpr(ctx, a->b)); |
c301f34e | 3709 | |
741322f4 | 3710 | copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); |
c301f34e RH |
3711 | if (ctx->iaoq_b == -1) { |
3712 | tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); | |
3713 | } | |
741322f4 | 3714 | copy_iaoq_entry(ctx, cpu_iaoq_b, -1, dest); |
c301f34e | 3715 | tcg_gen_mov_i64(cpu_iasq_b, space_select(ctx, 0, dest)); |
8340f534 | 3716 | if (a->l) { |
741322f4 | 3717 | copy_iaoq_entry(ctx, cpu_gr[a->l], ctx->iaoq_n, ctx->iaoq_n_var); |
c301f34e | 3718 | } |
8340f534 | 3719 | nullify_set(ctx, a->n); |
c301f34e | 3720 | tcg_gen_lookup_and_goto_ptr(); |
31234768 RH |
3721 | ctx->base.is_jmp = DISAS_NORETURN; |
3722 | return nullify_end(ctx); | |
c301f34e | 3723 | #endif |
98cd9ca7 RH |
3724 | } |
3725 | ||
1ca74648 RH |
3726 | /* |
3727 | * Float class 0 | |
3728 | */ | |
ebe9383c | 3729 | |
1ca74648 | 3730 | static void gen_fcpy_f(TCGv_i32 dst, TCGv_env unused, TCGv_i32 src) |
ebe9383c | 3731 | { |
1ca74648 | 3732 | tcg_gen_mov_i32(dst, src); |
ebe9383c RH |
3733 | } |
3734 | ||
59f8c04b HD |
3735 | static bool trans_fid_f(DisasContext *ctx, arg_fid_f *a) |
3736 | { | |
a300dad3 RH |
3737 | uint64_t ret; |
3738 | ||
3739 | if (TARGET_REGISTER_BITS == 64) { | |
3740 | ret = 0x13080000000000ULL; /* PA8700 (PCX-W2) */ | |
3741 | } else { | |
3742 | ret = 0x0f080000000000ULL; /* PA7300LC (PCX-L2) */ | |
3743 | } | |
3744 | ||
59f8c04b | 3745 | nullify_over(ctx); |
a300dad3 | 3746 | save_frd(0, tcg_constant_i64(ret)); |
59f8c04b HD |
3747 | return nullify_end(ctx); |
3748 | } | |
3749 | ||
1ca74648 | 3750 | static bool trans_fcpy_f(DisasContext *ctx, arg_fclass01 *a) |
ebe9383c | 3751 | { |
1ca74648 | 3752 | return do_fop_wew(ctx, a->t, a->r, gen_fcpy_f); |
ebe9383c RH |
3753 | } |
3754 | ||
1ca74648 | 3755 | static void gen_fcpy_d(TCGv_i64 dst, TCGv_env unused, TCGv_i64 src) |
ebe9383c | 3756 | { |
1ca74648 | 3757 | tcg_gen_mov_i64(dst, src); |
ebe9383c RH |
3758 | } |
3759 | ||
1ca74648 | 3760 | static bool trans_fcpy_d(DisasContext *ctx, arg_fclass01 *a) |
ebe9383c | 3761 | { |
1ca74648 | 3762 | return do_fop_ded(ctx, a->t, a->r, gen_fcpy_d); |
ebe9383c RH |
3763 | } |
3764 | ||
1ca74648 | 3765 | static void gen_fabs_f(TCGv_i32 dst, TCGv_env unused, TCGv_i32 src) |
ebe9383c | 3766 | { |
1ca74648 | 3767 | tcg_gen_andi_i32(dst, src, INT32_MAX); |
ebe9383c RH |
3768 | } |
3769 | ||
1ca74648 | 3770 | static bool trans_fabs_f(DisasContext *ctx, arg_fclass01 *a) |
ebe9383c | 3771 | { |
1ca74648 | 3772 | return do_fop_wew(ctx, a->t, a->r, gen_fabs_f); |
ebe9383c RH |
3773 | } |
3774 | ||
1ca74648 | 3775 | static void gen_fabs_d(TCGv_i64 dst, TCGv_env unused, TCGv_i64 src) |
ebe9383c | 3776 | { |
1ca74648 | 3777 | tcg_gen_andi_i64(dst, src, INT64_MAX); |
ebe9383c RH |
3778 | } |
3779 | ||
1ca74648 | 3780 | static bool trans_fabs_d(DisasContext *ctx, arg_fclass01 *a) |
ebe9383c | 3781 | { |
1ca74648 | 3782 | return do_fop_ded(ctx, a->t, a->r, gen_fabs_d); |
ebe9383c RH |
3783 | } |
3784 | ||
1ca74648 | 3785 | static bool trans_fsqrt_f(DisasContext *ctx, arg_fclass01 *a) |
ebe9383c | 3786 | { |
1ca74648 | 3787 | return do_fop_wew(ctx, a->t, a->r, gen_helper_fsqrt_s); |
ebe9383c RH |
3788 | } |
3789 | ||
1ca74648 | 3790 | static bool trans_fsqrt_d(DisasContext *ctx, arg_fclass01 *a) |
ebe9383c | 3791 | { |
1ca74648 | 3792 | return do_fop_ded(ctx, a->t, a->r, gen_helper_fsqrt_d); |
ebe9383c RH |
3793 | } |
3794 | ||
1ca74648 | 3795 | static bool trans_frnd_f(DisasContext *ctx, arg_fclass01 *a) |
ebe9383c | 3796 | { |
1ca74648 | 3797 | return do_fop_wew(ctx, a->t, a->r, gen_helper_frnd_s); |
ebe9383c RH |
3798 | } |
3799 | ||
1ca74648 | 3800 | static bool trans_frnd_d(DisasContext *ctx, arg_fclass01 *a) |
ebe9383c | 3801 | { |
1ca74648 | 3802 | return do_fop_ded(ctx, a->t, a->r, gen_helper_frnd_d); |
ebe9383c RH |
3803 | } |
3804 | ||
1ca74648 | 3805 | static void gen_fneg_f(TCGv_i32 dst, TCGv_env unused, TCGv_i32 src) |
ebe9383c | 3806 | { |
1ca74648 | 3807 | tcg_gen_xori_i32(dst, src, INT32_MIN); |
ebe9383c RH |
3808 | } |
3809 | ||
1ca74648 | 3810 | static bool trans_fneg_f(DisasContext *ctx, arg_fclass01 *a) |
ebe9383c | 3811 | { |
1ca74648 | 3812 | return do_fop_wew(ctx, a->t, a->r, gen_fneg_f); |
ebe9383c RH |
3813 | } |
3814 | ||
3815 | static void gen_fneg_d(TCGv_i64 dst, TCGv_env unused, TCGv_i64 src) | |
3816 | { | |
3817 | tcg_gen_xori_i64(dst, src, INT64_MIN); | |
3818 | } | |
3819 | ||
1ca74648 RH |
3820 | static bool trans_fneg_d(DisasContext *ctx, arg_fclass01 *a) |
3821 | { | |
3822 | return do_fop_ded(ctx, a->t, a->r, gen_fneg_d); | |
3823 | } | |
3824 | ||
3825 | static void gen_fnegabs_f(TCGv_i32 dst, TCGv_env unused, TCGv_i32 src) | |
ebe9383c RH |
3826 | { |
3827 | tcg_gen_ori_i32(dst, src, INT32_MIN); | |
3828 | } | |
3829 | ||
1ca74648 RH |
3830 | static bool trans_fnegabs_f(DisasContext *ctx, arg_fclass01 *a) |
3831 | { | |
3832 | return do_fop_wew(ctx, a->t, a->r, gen_fnegabs_f); | |
3833 | } | |
3834 | ||
ebe9383c RH |
3835 | static void gen_fnegabs_d(TCGv_i64 dst, TCGv_env unused, TCGv_i64 src) |
3836 | { | |
3837 | tcg_gen_ori_i64(dst, src, INT64_MIN); | |
3838 | } | |
3839 | ||
1ca74648 RH |
3840 | static bool trans_fnegabs_d(DisasContext *ctx, arg_fclass01 *a) |
3841 | { | |
3842 | return do_fop_ded(ctx, a->t, a->r, gen_fnegabs_d); | |
3843 | } | |
3844 | ||
3845 | /* | |
3846 | * Float class 1 | |
3847 | */ | |
3848 | ||
3849 | static bool trans_fcnv_d_f(DisasContext *ctx, arg_fclass01 *a) | |
3850 | { | |
3851 | return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_d_s); | |
3852 | } | |
3853 | ||
3854 | static bool trans_fcnv_f_d(DisasContext *ctx, arg_fclass01 *a) | |
3855 | { | |
3856 | return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_s_d); | |
3857 | } | |
3858 | ||
3859 | static bool trans_fcnv_w_f(DisasContext *ctx, arg_fclass01 *a) | |
3860 | { | |
3861 | return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_w_s); | |
3862 | } | |
3863 | ||
3864 | static bool trans_fcnv_q_f(DisasContext *ctx, arg_fclass01 *a) | |
3865 | { | |
3866 | return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_dw_s); | |
3867 | } | |
3868 | ||
3869 | static bool trans_fcnv_w_d(DisasContext *ctx, arg_fclass01 *a) | |
3870 | { | |
3871 | return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_w_d); | |
3872 | } | |
3873 | ||
3874 | static bool trans_fcnv_q_d(DisasContext *ctx, arg_fclass01 *a) | |
3875 | { | |
3876 | return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_dw_d); | |
3877 | } | |
3878 | ||
3879 | static bool trans_fcnv_f_w(DisasContext *ctx, arg_fclass01 *a) | |
3880 | { | |
3881 | return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_s_w); | |
3882 | } | |
3883 | ||
3884 | static bool trans_fcnv_d_w(DisasContext *ctx, arg_fclass01 *a) | |
3885 | { | |
3886 | return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_d_w); | |
3887 | } | |
3888 | ||
3889 | static bool trans_fcnv_f_q(DisasContext *ctx, arg_fclass01 *a) | |
3890 | { | |
3891 | return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_s_dw); | |
3892 | } | |
3893 | ||
3894 | static bool trans_fcnv_d_q(DisasContext *ctx, arg_fclass01 *a) | |
3895 | { | |
3896 | return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_d_dw); | |
3897 | } | |
3898 | ||
3899 | static bool trans_fcnv_t_f_w(DisasContext *ctx, arg_fclass01 *a) | |
3900 | { | |
3901 | return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_t_s_w); | |
3902 | } | |
3903 | ||
3904 | static bool trans_fcnv_t_d_w(DisasContext *ctx, arg_fclass01 *a) | |
3905 | { | |
3906 | return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_t_d_w); | |
3907 | } | |
3908 | ||
3909 | static bool trans_fcnv_t_f_q(DisasContext *ctx, arg_fclass01 *a) | |
3910 | { | |
3911 | return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_t_s_dw); | |
3912 | } | |
3913 | ||
3914 | static bool trans_fcnv_t_d_q(DisasContext *ctx, arg_fclass01 *a) | |
3915 | { | |
3916 | return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_t_d_dw); | |
3917 | } | |
3918 | ||
3919 | static bool trans_fcnv_uw_f(DisasContext *ctx, arg_fclass01 *a) | |
3920 | { | |
3921 | return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_uw_s); | |
3922 | } | |
3923 | ||
3924 | static bool trans_fcnv_uq_f(DisasContext *ctx, arg_fclass01 *a) | |
3925 | { | |
3926 | return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_udw_s); | |
3927 | } | |
3928 | ||
3929 | static bool trans_fcnv_uw_d(DisasContext *ctx, arg_fclass01 *a) | |
3930 | { | |
3931 | return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_uw_d); | |
3932 | } | |
3933 | ||
3934 | static bool trans_fcnv_uq_d(DisasContext *ctx, arg_fclass01 *a) | |
3935 | { | |
3936 | return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_udw_d); | |
3937 | } | |
3938 | ||
3939 | static bool trans_fcnv_f_uw(DisasContext *ctx, arg_fclass01 *a) | |
3940 | { | |
3941 | return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_s_uw); | |
3942 | } | |
3943 | ||
3944 | static bool trans_fcnv_d_uw(DisasContext *ctx, arg_fclass01 *a) | |
3945 | { | |
3946 | return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_d_uw); | |
3947 | } | |
3948 | ||
3949 | static bool trans_fcnv_f_uq(DisasContext *ctx, arg_fclass01 *a) | |
3950 | { | |
3951 | return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_s_udw); | |
3952 | } | |
3953 | ||
3954 | static bool trans_fcnv_d_uq(DisasContext *ctx, arg_fclass01 *a) | |
3955 | { | |
3956 | return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_d_udw); | |
3957 | } | |
3958 | ||
3959 | static bool trans_fcnv_t_f_uw(DisasContext *ctx, arg_fclass01 *a) | |
3960 | { | |
3961 | return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_t_s_uw); | |
3962 | } | |
3963 | ||
3964 | static bool trans_fcnv_t_d_uw(DisasContext *ctx, arg_fclass01 *a) | |
3965 | { | |
3966 | return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_t_d_uw); | |
3967 | } | |
3968 | ||
3969 | static bool trans_fcnv_t_f_uq(DisasContext *ctx, arg_fclass01 *a) | |
3970 | { | |
3971 | return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_t_s_udw); | |
3972 | } | |
3973 | ||
3974 | static bool trans_fcnv_t_d_uq(DisasContext *ctx, arg_fclass01 *a) | |
3975 | { | |
3976 | return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_t_d_udw); | |
3977 | } | |
3978 | ||
3979 | /* | |
3980 | * Float class 2 | |
3981 | */ | |
3982 | ||
3983 | static bool trans_fcmp_f(DisasContext *ctx, arg_fclass2 *a) | |
ebe9383c RH |
3984 | { |
3985 | TCGv_i32 ta, tb, tc, ty; | |
3986 | ||
3987 | nullify_over(ctx); | |
3988 | ||
1ca74648 RH |
3989 | ta = load_frw0_i32(a->r1); |
3990 | tb = load_frw0_i32(a->r2); | |
29dd6f64 RH |
3991 | ty = tcg_constant_i32(a->y); |
3992 | tc = tcg_constant_i32(a->c); | |
ebe9383c | 3993 | |
ad75a51e | 3994 | gen_helper_fcmp_s(tcg_env, ta, tb, ty, tc); |
ebe9383c | 3995 | |
1ca74648 | 3996 | return nullify_end(ctx); |
ebe9383c RH |
3997 | } |
3998 | ||
1ca74648 | 3999 | static bool trans_fcmp_d(DisasContext *ctx, arg_fclass2 *a) |
ebe9383c | 4000 | { |
ebe9383c RH |
4001 | TCGv_i64 ta, tb; |
4002 | TCGv_i32 tc, ty; | |
4003 | ||
4004 | nullify_over(ctx); | |
4005 | ||
1ca74648 RH |
4006 | ta = load_frd0(a->r1); |
4007 | tb = load_frd0(a->r2); | |
29dd6f64 RH |
4008 | ty = tcg_constant_i32(a->y); |
4009 | tc = tcg_constant_i32(a->c); | |
ebe9383c | 4010 | |
ad75a51e | 4011 | gen_helper_fcmp_d(tcg_env, ta, tb, ty, tc); |
ebe9383c | 4012 | |
31234768 | 4013 | return nullify_end(ctx); |
ebe9383c RH |
4014 | } |
4015 | ||
1ca74648 | 4016 | static bool trans_ftest(DisasContext *ctx, arg_ftest *a) |
ebe9383c | 4017 | { |
eaa3783b | 4018 | TCGv_reg t; |
ebe9383c RH |
4019 | |
4020 | nullify_over(ctx); | |
4021 | ||
e12c6309 | 4022 | t = tcg_temp_new(); |
ad75a51e | 4023 | tcg_gen_ld32u_reg(t, tcg_env, offsetof(CPUHPPAState, fr0_shadow)); |
ebe9383c | 4024 | |
1ca74648 RH |
4025 | if (a->y == 1) { |
4026 | int mask; | |
4027 | bool inv = false; | |
4028 | ||
4029 | switch (a->c) { | |
4030 | case 0: /* simple */ | |
4031 | tcg_gen_andi_reg(t, t, 0x4000000); | |
4032 | ctx->null_cond = cond_make_0(TCG_COND_NE, t); | |
4033 | goto done; | |
4034 | case 2: /* rej */ | |
4035 | inv = true; | |
4036 | /* fallthru */ | |
4037 | case 1: /* acc */ | |
4038 | mask = 0x43ff800; | |
4039 | break; | |
4040 | case 6: /* rej8 */ | |
4041 | inv = true; | |
4042 | /* fallthru */ | |
4043 | case 5: /* acc8 */ | |
4044 | mask = 0x43f8000; | |
4045 | break; | |
4046 | case 9: /* acc6 */ | |
4047 | mask = 0x43e0000; | |
4048 | break; | |
4049 | case 13: /* acc4 */ | |
4050 | mask = 0x4380000; | |
4051 | break; | |
4052 | case 17: /* acc2 */ | |
4053 | mask = 0x4200000; | |
4054 | break; | |
4055 | default: | |
4056 | gen_illegal(ctx); | |
4057 | return true; | |
4058 | } | |
4059 | if (inv) { | |
d4e58033 | 4060 | TCGv_reg c = tcg_constant_reg(mask); |
1ca74648 RH |
4061 | tcg_gen_or_reg(t, t, c); |
4062 | ctx->null_cond = cond_make(TCG_COND_EQ, t, c); | |
4063 | } else { | |
4064 | tcg_gen_andi_reg(t, t, mask); | |
4065 | ctx->null_cond = cond_make_0(TCG_COND_EQ, t); | |
4066 | } | |
4067 | } else { | |
4068 | unsigned cbit = (a->y ^ 1) - 1; | |
4069 | ||
4070 | tcg_gen_extract_reg(t, t, 21 - cbit, 1); | |
4071 | ctx->null_cond = cond_make_0(TCG_COND_NE, t); | |
1ca74648 RH |
4072 | } |
4073 | ||
4074 | done: | |
31234768 | 4075 | return nullify_end(ctx); |
ebe9383c RH |
4076 | } |
4077 | ||
1ca74648 RH |
4078 | /* |
4079 | * Float class 2 | |
4080 | */ | |
4081 | ||
4082 | static bool trans_fadd_f(DisasContext *ctx, arg_fclass3 *a) | |
ebe9383c | 4083 | { |
1ca74648 RH |
4084 | return do_fop_weww(ctx, a->t, a->r1, a->r2, gen_helper_fadd_s); |
4085 | } | |
ebe9383c | 4086 | |
1ca74648 RH |
4087 | static bool trans_fadd_d(DisasContext *ctx, arg_fclass3 *a) |
4088 | { | |
4089 | return do_fop_dedd(ctx, a->t, a->r1, a->r2, gen_helper_fadd_d); | |
4090 | } | |
ebe9383c | 4091 | |
1ca74648 RH |
4092 | static bool trans_fsub_f(DisasContext *ctx, arg_fclass3 *a) |
4093 | { | |
4094 | return do_fop_weww(ctx, a->t, a->r1, a->r2, gen_helper_fsub_s); | |
4095 | } | |
ebe9383c | 4096 | |
1ca74648 RH |
4097 | static bool trans_fsub_d(DisasContext *ctx, arg_fclass3 *a) |
4098 | { | |
4099 | return do_fop_dedd(ctx, a->t, a->r1, a->r2, gen_helper_fsub_d); | |
ebe9383c RH |
4100 | } |
4101 | ||
1ca74648 | 4102 | static bool trans_fmpy_f(DisasContext *ctx, arg_fclass3 *a) |
ebe9383c | 4103 | { |
1ca74648 RH |
4104 | return do_fop_weww(ctx, a->t, a->r1, a->r2, gen_helper_fmpy_s); |
4105 | } | |
4106 | ||
4107 | static bool trans_fmpy_d(DisasContext *ctx, arg_fclass3 *a) | |
4108 | { | |
4109 | return do_fop_dedd(ctx, a->t, a->r1, a->r2, gen_helper_fmpy_d); | |
4110 | } | |
4111 | ||
4112 | static bool trans_fdiv_f(DisasContext *ctx, arg_fclass3 *a) | |
4113 | { | |
4114 | return do_fop_weww(ctx, a->t, a->r1, a->r2, gen_helper_fdiv_s); | |
4115 | } | |
4116 | ||
4117 | static bool trans_fdiv_d(DisasContext *ctx, arg_fclass3 *a) | |
4118 | { | |
4119 | return do_fop_dedd(ctx, a->t, a->r1, a->r2, gen_helper_fdiv_d); | |
4120 | } | |
4121 | ||
4122 | static bool trans_xmpyu(DisasContext *ctx, arg_xmpyu *a) | |
4123 | { | |
4124 | TCGv_i64 x, y; | |
ebe9383c RH |
4125 | |
4126 | nullify_over(ctx); | |
4127 | ||
1ca74648 RH |
4128 | x = load_frw0_i64(a->r1); |
4129 | y = load_frw0_i64(a->r2); | |
4130 | tcg_gen_mul_i64(x, x, y); | |
4131 | save_frd(a->t, x); | |
ebe9383c | 4132 | |
31234768 | 4133 | return nullify_end(ctx); |
ebe9383c RH |
4134 | } |
4135 | ||
ebe9383c RH |
4136 | /* Convert the fmpyadd single-precision register encodings to standard. */ |
4137 | static inline int fmpyadd_s_reg(unsigned r) | |
4138 | { | |
4139 | return (r & 16) * 2 + 16 + (r & 15); | |
4140 | } | |
4141 | ||
b1e2af57 | 4142 | static bool do_fmpyadd_s(DisasContext *ctx, arg_mpyadd *a, bool is_sub) |
ebe9383c | 4143 | { |
b1e2af57 RH |
4144 | int tm = fmpyadd_s_reg(a->tm); |
4145 | int ra = fmpyadd_s_reg(a->ra); | |
4146 | int ta = fmpyadd_s_reg(a->ta); | |
4147 | int rm2 = fmpyadd_s_reg(a->rm2); | |
4148 | int rm1 = fmpyadd_s_reg(a->rm1); | |
ebe9383c RH |
4149 | |
4150 | nullify_over(ctx); | |
4151 | ||
b1e2af57 RH |
4152 | do_fop_weww(ctx, tm, rm1, rm2, gen_helper_fmpy_s); |
4153 | do_fop_weww(ctx, ta, ta, ra, | |
4154 | is_sub ? gen_helper_fsub_s : gen_helper_fadd_s); | |
ebe9383c | 4155 | |
31234768 | 4156 | return nullify_end(ctx); |
ebe9383c RH |
4157 | } |
4158 | ||
b1e2af57 RH |
4159 | static bool trans_fmpyadd_f(DisasContext *ctx, arg_mpyadd *a) |
4160 | { | |
4161 | return do_fmpyadd_s(ctx, a, false); | |
4162 | } | |
4163 | ||
4164 | static bool trans_fmpysub_f(DisasContext *ctx, arg_mpyadd *a) | |
4165 | { | |
4166 | return do_fmpyadd_s(ctx, a, true); | |
4167 | } | |
4168 | ||
4169 | static bool do_fmpyadd_d(DisasContext *ctx, arg_mpyadd *a, bool is_sub) | |
4170 | { | |
4171 | nullify_over(ctx); | |
4172 | ||
4173 | do_fop_dedd(ctx, a->tm, a->rm1, a->rm2, gen_helper_fmpy_d); | |
4174 | do_fop_dedd(ctx, a->ta, a->ta, a->ra, | |
4175 | is_sub ? gen_helper_fsub_d : gen_helper_fadd_d); | |
4176 | ||
4177 | return nullify_end(ctx); | |
4178 | } | |
4179 | ||
4180 | static bool trans_fmpyadd_d(DisasContext *ctx, arg_mpyadd *a) | |
4181 | { | |
4182 | return do_fmpyadd_d(ctx, a, false); | |
4183 | } | |
4184 | ||
4185 | static bool trans_fmpysub_d(DisasContext *ctx, arg_mpyadd *a) | |
4186 | { | |
4187 | return do_fmpyadd_d(ctx, a, true); | |
4188 | } | |
4189 | ||
c3bad4f8 | 4190 | static bool trans_fmpyfadd_f(DisasContext *ctx, arg_fmpyfadd_f *a) |
ebe9383c | 4191 | { |
c3bad4f8 | 4192 | TCGv_i32 x, y, z; |
ebe9383c RH |
4193 | |
4194 | nullify_over(ctx); | |
c3bad4f8 RH |
4195 | x = load_frw0_i32(a->rm1); |
4196 | y = load_frw0_i32(a->rm2); | |
4197 | z = load_frw0_i32(a->ra3); | |
ebe9383c | 4198 | |
c3bad4f8 | 4199 | if (a->neg) { |
ad75a51e | 4200 | gen_helper_fmpynfadd_s(x, tcg_env, x, y, z); |
ebe9383c | 4201 | } else { |
ad75a51e | 4202 | gen_helper_fmpyfadd_s(x, tcg_env, x, y, z); |
ebe9383c RH |
4203 | } |
4204 | ||
c3bad4f8 | 4205 | save_frw_i32(a->t, x); |
31234768 | 4206 | return nullify_end(ctx); |
ebe9383c RH |
4207 | } |
4208 | ||
c3bad4f8 | 4209 | static bool trans_fmpyfadd_d(DisasContext *ctx, arg_fmpyfadd_d *a) |
ebe9383c | 4210 | { |
c3bad4f8 | 4211 | TCGv_i64 x, y, z; |
ebe9383c RH |
4212 | |
4213 | nullify_over(ctx); | |
c3bad4f8 RH |
4214 | x = load_frd0(a->rm1); |
4215 | y = load_frd0(a->rm2); | |
4216 | z = load_frd0(a->ra3); | |
ebe9383c | 4217 | |
c3bad4f8 | 4218 | if (a->neg) { |
ad75a51e | 4219 | gen_helper_fmpynfadd_d(x, tcg_env, x, y, z); |
ebe9383c | 4220 | } else { |
ad75a51e | 4221 | gen_helper_fmpyfadd_d(x, tcg_env, x, y, z); |
ebe9383c RH |
4222 | } |
4223 | ||
c3bad4f8 | 4224 | save_frd(a->t, x); |
31234768 | 4225 | return nullify_end(ctx); |
ebe9383c RH |
4226 | } |
4227 | ||
15da177b SS |
4228 | static bool trans_diag(DisasContext *ctx, arg_diag *a) |
4229 | { | |
cf6b28d4 HD |
4230 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); |
4231 | #ifndef CONFIG_USER_ONLY | |
4232 | if (a->i == 0x100) { | |
4233 | /* emulate PDC BTLB, called by SeaBIOS-hppa */ | |
ad75a51e RH |
4234 | nullify_over(ctx); |
4235 | gen_helper_diag_btlb(tcg_env); | |
4236 | return nullify_end(ctx); | |
cf6b28d4 | 4237 | } |
ad75a51e RH |
4238 | #endif |
4239 | qemu_log_mask(LOG_UNIMP, "DIAG opcode 0x%04x ignored\n", a->i); | |
4240 | return true; | |
15da177b SS |
4241 | } |
4242 | ||
b542683d | 4243 | static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) |
61766fe9 | 4244 | { |
51b061fb | 4245 | DisasContext *ctx = container_of(dcbase, DisasContext, base); |
f764718d | 4246 | int bound; |
61766fe9 | 4247 | |
51b061fb | 4248 | ctx->cs = cs; |
494737b7 | 4249 | ctx->tb_flags = ctx->base.tb->flags; |
bd6243a3 | 4250 | ctx->is_pa20 = hppa_is_pa20(cpu_env(cs)); |
3d68ee7b RH |
4251 | |
4252 | #ifdef CONFIG_USER_ONLY | |
c01e5dfb | 4253 | ctx->privilege = MMU_IDX_TO_PRIV(MMU_USER_IDX); |
3d68ee7b | 4254 | ctx->mmu_idx = MMU_USER_IDX; |
c01e5dfb HD |
4255 | ctx->iaoq_f = ctx->base.pc_first | ctx->privilege; |
4256 | ctx->iaoq_b = ctx->base.tb->cs_base | ctx->privilege; | |
217d1a5e | 4257 | ctx->unalign = (ctx->tb_flags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN); |
3d68ee7b | 4258 | #else |
494737b7 | 4259 | ctx->privilege = (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3; |
bb67ec32 RH |
4260 | ctx->mmu_idx = (ctx->tb_flags & PSW_D |
4261 | ? PRIV_P_TO_MMU_IDX(ctx->privilege, ctx->tb_flags & PSW_P) | |
4262 | : MMU_PHYS_IDX); | |
3d68ee7b | 4263 | |
c301f34e RH |
4264 | /* Recover the IAOQ values from the GVA + PRIV. */ |
4265 | uint64_t cs_base = ctx->base.tb->cs_base; | |
4266 | uint64_t iasq_f = cs_base & ~0xffffffffull; | |
4267 | int32_t diff = cs_base; | |
4268 | ||
4269 | ctx->iaoq_f = (ctx->base.pc_first & ~iasq_f) + ctx->privilege; | |
4270 | ctx->iaoq_b = (diff ? ctx->iaoq_f + diff : -1); | |
4271 | #endif | |
51b061fb | 4272 | ctx->iaoq_n = -1; |
f764718d | 4273 | ctx->iaoq_n_var = NULL; |
61766fe9 | 4274 | |
3d68ee7b RH |
4275 | /* Bound the number of instructions by those left on the page. */ |
4276 | bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; | |
b542683d | 4277 | ctx->base.max_insns = MIN(ctx->base.max_insns, bound); |
51b061fb | 4278 | } |
61766fe9 | 4279 | |
51b061fb RH |
4280 | static void hppa_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) |
4281 | { | |
4282 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
61766fe9 | 4283 | |
3d68ee7b | 4284 | /* Seed the nullification status from PSW[N], as saved in TB->FLAGS. */ |
51b061fb RH |
4285 | ctx->null_cond = cond_make_f(); |
4286 | ctx->psw_n_nonzero = false; | |
494737b7 | 4287 | if (ctx->tb_flags & PSW_N) { |
51b061fb RH |
4288 | ctx->null_cond.c = TCG_COND_ALWAYS; |
4289 | ctx->psw_n_nonzero = true; | |
129e9cc3 | 4290 | } |
51b061fb RH |
4291 | ctx->null_lab = NULL; |
4292 | } | |
129e9cc3 | 4293 | |
51b061fb RH |
4294 | static void hppa_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) |
4295 | { | |
4296 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
61766fe9 | 4297 | |
51b061fb RH |
4298 | tcg_gen_insn_start(ctx->iaoq_f, ctx->iaoq_b); |
4299 | } | |
4300 | ||
51b061fb RH |
4301 | static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) |
4302 | { | |
4303 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
b77af26e | 4304 | CPUHPPAState *env = cpu_env(cs); |
51b061fb | 4305 | DisasJumpType ret; |
51b061fb RH |
4306 | |
4307 | /* Execute one insn. */ | |
ba1d0b44 | 4308 | #ifdef CONFIG_USER_ONLY |
c301f34e | 4309 | if (ctx->base.pc_next < TARGET_PAGE_SIZE) { |
31234768 RH |
4310 | do_page_zero(ctx); |
4311 | ret = ctx->base.is_jmp; | |
51b061fb | 4312 | assert(ret != DISAS_NEXT); |
ba1d0b44 RH |
4313 | } else |
4314 | #endif | |
4315 | { | |
51b061fb RH |
4316 | /* Always fetch the insn, even if nullified, so that we check |
4317 | the page permissions for execute. */ | |
4e116893 | 4318 | uint32_t insn = translator_ldl(env, &ctx->base, ctx->base.pc_next); |
51b061fb RH |
4319 | |
4320 | /* Set up the IA queue for the next insn. | |
4321 | This will be overwritten by a branch. */ | |
4322 | if (ctx->iaoq_b == -1) { | |
4323 | ctx->iaoq_n = -1; | |
e12c6309 | 4324 | ctx->iaoq_n_var = tcg_temp_new(); |
eaa3783b | 4325 | tcg_gen_addi_reg(ctx->iaoq_n_var, cpu_iaoq_b, 4); |
7ad439df | 4326 | } else { |
51b061fb | 4327 | ctx->iaoq_n = ctx->iaoq_b + 4; |
f764718d | 4328 | ctx->iaoq_n_var = NULL; |
61766fe9 RH |
4329 | } |
4330 | ||
51b061fb RH |
4331 | if (unlikely(ctx->null_cond.c == TCG_COND_ALWAYS)) { |
4332 | ctx->null_cond.c = TCG_COND_NEVER; | |
4333 | ret = DISAS_NEXT; | |
4334 | } else { | |
1a19da0d | 4335 | ctx->insn = insn; |
31274b46 RH |
4336 | if (!decode(ctx, insn)) { |
4337 | gen_illegal(ctx); | |
4338 | } | |
31234768 | 4339 | ret = ctx->base.is_jmp; |
51b061fb | 4340 | assert(ctx->null_lab == NULL); |
61766fe9 | 4341 | } |
51b061fb | 4342 | } |
61766fe9 | 4343 | |
3d68ee7b RH |
4344 | /* Advance the insn queue. Note that this check also detects |
4345 | a priority change within the instruction queue. */ | |
51b061fb | 4346 | if (ret == DISAS_NEXT && ctx->iaoq_b != ctx->iaoq_f + 4) { |
c301f34e RH |
4347 | if (ctx->iaoq_b != -1 && ctx->iaoq_n != -1 |
4348 | && use_goto_tb(ctx, ctx->iaoq_b) | |
4349 | && (ctx->null_cond.c == TCG_COND_NEVER | |
4350 | || ctx->null_cond.c == TCG_COND_ALWAYS)) { | |
51b061fb RH |
4351 | nullify_set(ctx, ctx->null_cond.c == TCG_COND_ALWAYS); |
4352 | gen_goto_tb(ctx, 0, ctx->iaoq_b, ctx->iaoq_n); | |
31234768 | 4353 | ctx->base.is_jmp = ret = DISAS_NORETURN; |
51b061fb | 4354 | } else { |
31234768 | 4355 | ctx->base.is_jmp = ret = DISAS_IAQ_N_STALE; |
c301f34e | 4356 | } |
61766fe9 | 4357 | } |
51b061fb RH |
4358 | ctx->iaoq_f = ctx->iaoq_b; |
4359 | ctx->iaoq_b = ctx->iaoq_n; | |
c301f34e | 4360 | ctx->base.pc_next += 4; |
51b061fb | 4361 | |
c5d0aec2 RH |
4362 | switch (ret) { |
4363 | case DISAS_NORETURN: | |
4364 | case DISAS_IAQ_N_UPDATED: | |
4365 | break; | |
4366 | ||
4367 | case DISAS_NEXT: | |
4368 | case DISAS_IAQ_N_STALE: | |
4369 | case DISAS_IAQ_N_STALE_EXIT: | |
4370 | if (ctx->iaoq_f == -1) { | |
a0180973 | 4371 | copy_iaoq_entry(ctx, cpu_iaoq_f, -1, cpu_iaoq_b); |
741322f4 | 4372 | copy_iaoq_entry(ctx, cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var); |
c301f34e | 4373 | #ifndef CONFIG_USER_ONLY |
c5d0aec2 | 4374 | tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); |
c301f34e | 4375 | #endif |
c5d0aec2 RH |
4376 | nullify_save(ctx); |
4377 | ctx->base.is_jmp = (ret == DISAS_IAQ_N_STALE_EXIT | |
4378 | ? DISAS_EXIT | |
4379 | : DISAS_IAQ_N_UPDATED); | |
4380 | } else if (ctx->iaoq_b == -1) { | |
a0180973 | 4381 | copy_iaoq_entry(ctx, cpu_iaoq_b, -1, ctx->iaoq_n_var); |
c5d0aec2 RH |
4382 | } |
4383 | break; | |
4384 | ||
4385 | default: | |
4386 | g_assert_not_reached(); | |
51b061fb RH |
4387 | } |
4388 | } | |
4389 | ||
4390 | static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) | |
4391 | { | |
4392 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
e1b5a5ed | 4393 | DisasJumpType is_jmp = ctx->base.is_jmp; |
61766fe9 | 4394 | |
e1b5a5ed | 4395 | switch (is_jmp) { |
869051ea | 4396 | case DISAS_NORETURN: |
61766fe9 | 4397 | break; |
51b061fb | 4398 | case DISAS_TOO_MANY: |
869051ea | 4399 | case DISAS_IAQ_N_STALE: |
e1b5a5ed | 4400 | case DISAS_IAQ_N_STALE_EXIT: |
741322f4 RH |
4401 | copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_f, cpu_iaoq_f); |
4402 | copy_iaoq_entry(ctx, cpu_iaoq_b, ctx->iaoq_b, cpu_iaoq_b); | |
51b061fb | 4403 | nullify_save(ctx); |
61766fe9 | 4404 | /* FALLTHRU */ |
869051ea | 4405 | case DISAS_IAQ_N_UPDATED: |
8532a14e | 4406 | if (is_jmp != DISAS_IAQ_N_STALE_EXIT) { |
7f11636d | 4407 | tcg_gen_lookup_and_goto_ptr(); |
8532a14e | 4408 | break; |
61766fe9 | 4409 | } |
c5d0aec2 RH |
4410 | /* FALLTHRU */ |
4411 | case DISAS_EXIT: | |
4412 | tcg_gen_exit_tb(NULL, 0); | |
61766fe9 RH |
4413 | break; |
4414 | default: | |
51b061fb | 4415 | g_assert_not_reached(); |
61766fe9 | 4416 | } |
51b061fb | 4417 | } |
61766fe9 | 4418 | |
8eb806a7 RH |
4419 | static void hppa_tr_disas_log(const DisasContextBase *dcbase, |
4420 | CPUState *cs, FILE *logfile) | |
51b061fb | 4421 | { |
c301f34e | 4422 | target_ulong pc = dcbase->pc_first; |
61766fe9 | 4423 | |
ba1d0b44 RH |
4424 | #ifdef CONFIG_USER_ONLY |
4425 | switch (pc) { | |
51b061fb | 4426 | case 0x00: |
8eb806a7 | 4427 | fprintf(logfile, "IN:\n0x00000000: (null)\n"); |
ba1d0b44 | 4428 | return; |
51b061fb | 4429 | case 0xb0: |
8eb806a7 | 4430 | fprintf(logfile, "IN:\n0x000000b0: light-weight-syscall\n"); |
ba1d0b44 | 4431 | return; |
51b061fb | 4432 | case 0xe0: |
8eb806a7 | 4433 | fprintf(logfile, "IN:\n0x000000e0: set-thread-pointer-syscall\n"); |
ba1d0b44 | 4434 | return; |
51b061fb | 4435 | case 0x100: |
8eb806a7 | 4436 | fprintf(logfile, "IN:\n0x00000100: syscall\n"); |
ba1d0b44 | 4437 | return; |
61766fe9 | 4438 | } |
ba1d0b44 RH |
4439 | #endif |
4440 | ||
8eb806a7 RH |
4441 | fprintf(logfile, "IN: %s\n", lookup_symbol(pc)); |
4442 | target_disas(logfile, cs, pc, dcbase->tb->size); | |
51b061fb RH |
4443 | } |
4444 | ||
4445 | static const TranslatorOps hppa_tr_ops = { | |
4446 | .init_disas_context = hppa_tr_init_disas_context, | |
4447 | .tb_start = hppa_tr_tb_start, | |
4448 | .insn_start = hppa_tr_insn_start, | |
51b061fb RH |
4449 | .translate_insn = hppa_tr_translate_insn, |
4450 | .tb_stop = hppa_tr_tb_stop, | |
4451 | .disas_log = hppa_tr_disas_log, | |
4452 | }; | |
4453 | ||
597f9b2d | 4454 | void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, |
306c8721 | 4455 | target_ulong pc, void *host_pc) |
51b061fb RH |
4456 | { |
4457 | DisasContext ctx; | |
306c8721 | 4458 | translator_loop(cs, tb, max_insns, pc, host_pc, &hppa_tr_ops, &ctx.base); |
61766fe9 | 4459 | } |