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61766fe9 RH |
1 | /* |
2 | * HPPA emulation cpu translation for qemu. | |
3 | * | |
4 | * Copyright (c) 2016 Richard Henderson <rth@twiddle.net> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
d6ea4236 | 9 | * version 2.1 of the License, or (at your option) any later version. |
61766fe9 RH |
10 | * |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
21 | #include "cpu.h" | |
22 | #include "disas/disas.h" | |
23 | #include "qemu/host-utils.h" | |
24 | #include "exec/exec-all.h" | |
dcb32f1d | 25 | #include "tcg/tcg-op.h" |
61766fe9 RH |
26 | #include "exec/helper-proto.h" |
27 | #include "exec/helper-gen.h" | |
869051ea | 28 | #include "exec/translator.h" |
61766fe9 RH |
29 | #include "exec/log.h" |
30 | ||
d53106c9 RH |
31 | #define HELPER_H "helper.h" |
32 | #include "exec/helper-info.c.inc" | |
33 | #undef HELPER_H | |
34 | ||
35 | ||
eaa3783b RH |
36 | /* Since we have a distinction between register size and address size, |
37 | we need to redefine all of these. */ | |
38 | ||
39 | #undef TCGv | |
40 | #undef tcg_temp_new | |
eaa3783b | 41 | #undef tcg_global_mem_new |
eaa3783b RH |
42 | |
43 | #if TARGET_LONG_BITS == 64 | |
44 | #define TCGv_tl TCGv_i64 | |
45 | #define tcg_temp_new_tl tcg_temp_new_i64 | |
eaa3783b RH |
46 | #if TARGET_REGISTER_BITS == 64 |
47 | #define tcg_gen_extu_reg_tl tcg_gen_mov_i64 | |
48 | #else | |
49 | #define tcg_gen_extu_reg_tl tcg_gen_extu_i32_i64 | |
50 | #endif | |
51 | #else | |
52 | #define TCGv_tl TCGv_i32 | |
53 | #define tcg_temp_new_tl tcg_temp_new_i32 | |
eaa3783b RH |
54 | #define tcg_gen_extu_reg_tl tcg_gen_mov_i32 |
55 | #endif | |
56 | ||
57 | #if TARGET_REGISTER_BITS == 64 | |
58 | #define TCGv_reg TCGv_i64 | |
59 | ||
60 | #define tcg_temp_new tcg_temp_new_i64 | |
eaa3783b | 61 | #define tcg_global_mem_new tcg_global_mem_new_i64 |
eaa3783b RH |
62 | |
63 | #define tcg_gen_movi_reg tcg_gen_movi_i64 | |
64 | #define tcg_gen_mov_reg tcg_gen_mov_i64 | |
65 | #define tcg_gen_ld8u_reg tcg_gen_ld8u_i64 | |
66 | #define tcg_gen_ld8s_reg tcg_gen_ld8s_i64 | |
67 | #define tcg_gen_ld16u_reg tcg_gen_ld16u_i64 | |
68 | #define tcg_gen_ld16s_reg tcg_gen_ld16s_i64 | |
69 | #define tcg_gen_ld32u_reg tcg_gen_ld32u_i64 | |
70 | #define tcg_gen_ld32s_reg tcg_gen_ld32s_i64 | |
71 | #define tcg_gen_ld_reg tcg_gen_ld_i64 | |
72 | #define tcg_gen_st8_reg tcg_gen_st8_i64 | |
73 | #define tcg_gen_st16_reg tcg_gen_st16_i64 | |
74 | #define tcg_gen_st32_reg tcg_gen_st32_i64 | |
75 | #define tcg_gen_st_reg tcg_gen_st_i64 | |
76 | #define tcg_gen_add_reg tcg_gen_add_i64 | |
77 | #define tcg_gen_addi_reg tcg_gen_addi_i64 | |
78 | #define tcg_gen_sub_reg tcg_gen_sub_i64 | |
79 | #define tcg_gen_neg_reg tcg_gen_neg_i64 | |
80 | #define tcg_gen_subfi_reg tcg_gen_subfi_i64 | |
81 | #define tcg_gen_subi_reg tcg_gen_subi_i64 | |
82 | #define tcg_gen_and_reg tcg_gen_and_i64 | |
83 | #define tcg_gen_andi_reg tcg_gen_andi_i64 | |
84 | #define tcg_gen_or_reg tcg_gen_or_i64 | |
85 | #define tcg_gen_ori_reg tcg_gen_ori_i64 | |
86 | #define tcg_gen_xor_reg tcg_gen_xor_i64 | |
87 | #define tcg_gen_xori_reg tcg_gen_xori_i64 | |
88 | #define tcg_gen_not_reg tcg_gen_not_i64 | |
89 | #define tcg_gen_shl_reg tcg_gen_shl_i64 | |
90 | #define tcg_gen_shli_reg tcg_gen_shli_i64 | |
91 | #define tcg_gen_shr_reg tcg_gen_shr_i64 | |
92 | #define tcg_gen_shri_reg tcg_gen_shri_i64 | |
93 | #define tcg_gen_sar_reg tcg_gen_sar_i64 | |
94 | #define tcg_gen_sari_reg tcg_gen_sari_i64 | |
95 | #define tcg_gen_brcond_reg tcg_gen_brcond_i64 | |
96 | #define tcg_gen_brcondi_reg tcg_gen_brcondi_i64 | |
97 | #define tcg_gen_setcond_reg tcg_gen_setcond_i64 | |
98 | #define tcg_gen_setcondi_reg tcg_gen_setcondi_i64 | |
99 | #define tcg_gen_mul_reg tcg_gen_mul_i64 | |
100 | #define tcg_gen_muli_reg tcg_gen_muli_i64 | |
101 | #define tcg_gen_div_reg tcg_gen_div_i64 | |
102 | #define tcg_gen_rem_reg tcg_gen_rem_i64 | |
103 | #define tcg_gen_divu_reg tcg_gen_divu_i64 | |
104 | #define tcg_gen_remu_reg tcg_gen_remu_i64 | |
105 | #define tcg_gen_discard_reg tcg_gen_discard_i64 | |
106 | #define tcg_gen_trunc_reg_i32 tcg_gen_extrl_i64_i32 | |
107 | #define tcg_gen_trunc_i64_reg tcg_gen_mov_i64 | |
108 | #define tcg_gen_extu_i32_reg tcg_gen_extu_i32_i64 | |
109 | #define tcg_gen_ext_i32_reg tcg_gen_ext_i32_i64 | |
110 | #define tcg_gen_extu_reg_i64 tcg_gen_mov_i64 | |
111 | #define tcg_gen_ext_reg_i64 tcg_gen_mov_i64 | |
112 | #define tcg_gen_ext8u_reg tcg_gen_ext8u_i64 | |
113 | #define tcg_gen_ext8s_reg tcg_gen_ext8s_i64 | |
114 | #define tcg_gen_ext16u_reg tcg_gen_ext16u_i64 | |
115 | #define tcg_gen_ext16s_reg tcg_gen_ext16s_i64 | |
116 | #define tcg_gen_ext32u_reg tcg_gen_ext32u_i64 | |
117 | #define tcg_gen_ext32s_reg tcg_gen_ext32s_i64 | |
118 | #define tcg_gen_bswap16_reg tcg_gen_bswap16_i64 | |
119 | #define tcg_gen_bswap32_reg tcg_gen_bswap32_i64 | |
120 | #define tcg_gen_bswap64_reg tcg_gen_bswap64_i64 | |
121 | #define tcg_gen_concat_reg_i64 tcg_gen_concat32_i64 | |
122 | #define tcg_gen_andc_reg tcg_gen_andc_i64 | |
123 | #define tcg_gen_eqv_reg tcg_gen_eqv_i64 | |
124 | #define tcg_gen_nand_reg tcg_gen_nand_i64 | |
125 | #define tcg_gen_nor_reg tcg_gen_nor_i64 | |
126 | #define tcg_gen_orc_reg tcg_gen_orc_i64 | |
127 | #define tcg_gen_clz_reg tcg_gen_clz_i64 | |
128 | #define tcg_gen_ctz_reg tcg_gen_ctz_i64 | |
129 | #define tcg_gen_clzi_reg tcg_gen_clzi_i64 | |
130 | #define tcg_gen_ctzi_reg tcg_gen_ctzi_i64 | |
131 | #define tcg_gen_clrsb_reg tcg_gen_clrsb_i64 | |
132 | #define tcg_gen_ctpop_reg tcg_gen_ctpop_i64 | |
133 | #define tcg_gen_rotl_reg tcg_gen_rotl_i64 | |
134 | #define tcg_gen_rotli_reg tcg_gen_rotli_i64 | |
135 | #define tcg_gen_rotr_reg tcg_gen_rotr_i64 | |
136 | #define tcg_gen_rotri_reg tcg_gen_rotri_i64 | |
137 | #define tcg_gen_deposit_reg tcg_gen_deposit_i64 | |
138 | #define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i64 | |
139 | #define tcg_gen_extract_reg tcg_gen_extract_i64 | |
140 | #define tcg_gen_sextract_reg tcg_gen_sextract_i64 | |
05bfd4db | 141 | #define tcg_gen_extract2_reg tcg_gen_extract2_i64 |
29dd6f64 | 142 | #define tcg_constant_reg tcg_constant_i64 |
eaa3783b RH |
143 | #define tcg_gen_movcond_reg tcg_gen_movcond_i64 |
144 | #define tcg_gen_add2_reg tcg_gen_add2_i64 | |
145 | #define tcg_gen_sub2_reg tcg_gen_sub2_i64 | |
146 | #define tcg_gen_qemu_ld_reg tcg_gen_qemu_ld_i64 | |
147 | #define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i64 | |
148 | #define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i64 | |
5bfa8034 | 149 | #define tcg_gen_trunc_reg_ptr tcg_gen_trunc_i64_ptr |
eaa3783b RH |
150 | #else |
151 | #define TCGv_reg TCGv_i32 | |
152 | #define tcg_temp_new tcg_temp_new_i32 | |
eaa3783b | 153 | #define tcg_global_mem_new tcg_global_mem_new_i32 |
eaa3783b RH |
154 | |
155 | #define tcg_gen_movi_reg tcg_gen_movi_i32 | |
156 | #define tcg_gen_mov_reg tcg_gen_mov_i32 | |
157 | #define tcg_gen_ld8u_reg tcg_gen_ld8u_i32 | |
158 | #define tcg_gen_ld8s_reg tcg_gen_ld8s_i32 | |
159 | #define tcg_gen_ld16u_reg tcg_gen_ld16u_i32 | |
160 | #define tcg_gen_ld16s_reg tcg_gen_ld16s_i32 | |
161 | #define tcg_gen_ld32u_reg tcg_gen_ld_i32 | |
162 | #define tcg_gen_ld32s_reg tcg_gen_ld_i32 | |
163 | #define tcg_gen_ld_reg tcg_gen_ld_i32 | |
164 | #define tcg_gen_st8_reg tcg_gen_st8_i32 | |
165 | #define tcg_gen_st16_reg tcg_gen_st16_i32 | |
166 | #define tcg_gen_st32_reg tcg_gen_st32_i32 | |
167 | #define tcg_gen_st_reg tcg_gen_st_i32 | |
168 | #define tcg_gen_add_reg tcg_gen_add_i32 | |
169 | #define tcg_gen_addi_reg tcg_gen_addi_i32 | |
170 | #define tcg_gen_sub_reg tcg_gen_sub_i32 | |
171 | #define tcg_gen_neg_reg tcg_gen_neg_i32 | |
172 | #define tcg_gen_subfi_reg tcg_gen_subfi_i32 | |
173 | #define tcg_gen_subi_reg tcg_gen_subi_i32 | |
174 | #define tcg_gen_and_reg tcg_gen_and_i32 | |
175 | #define tcg_gen_andi_reg tcg_gen_andi_i32 | |
176 | #define tcg_gen_or_reg tcg_gen_or_i32 | |
177 | #define tcg_gen_ori_reg tcg_gen_ori_i32 | |
178 | #define tcg_gen_xor_reg tcg_gen_xor_i32 | |
179 | #define tcg_gen_xori_reg tcg_gen_xori_i32 | |
180 | #define tcg_gen_not_reg tcg_gen_not_i32 | |
181 | #define tcg_gen_shl_reg tcg_gen_shl_i32 | |
182 | #define tcg_gen_shli_reg tcg_gen_shli_i32 | |
183 | #define tcg_gen_shr_reg tcg_gen_shr_i32 | |
184 | #define tcg_gen_shri_reg tcg_gen_shri_i32 | |
185 | #define tcg_gen_sar_reg tcg_gen_sar_i32 | |
186 | #define tcg_gen_sari_reg tcg_gen_sari_i32 | |
187 | #define tcg_gen_brcond_reg tcg_gen_brcond_i32 | |
188 | #define tcg_gen_brcondi_reg tcg_gen_brcondi_i32 | |
189 | #define tcg_gen_setcond_reg tcg_gen_setcond_i32 | |
190 | #define tcg_gen_setcondi_reg tcg_gen_setcondi_i32 | |
191 | #define tcg_gen_mul_reg tcg_gen_mul_i32 | |
192 | #define tcg_gen_muli_reg tcg_gen_muli_i32 | |
193 | #define tcg_gen_div_reg tcg_gen_div_i32 | |
194 | #define tcg_gen_rem_reg tcg_gen_rem_i32 | |
195 | #define tcg_gen_divu_reg tcg_gen_divu_i32 | |
196 | #define tcg_gen_remu_reg tcg_gen_remu_i32 | |
197 | #define tcg_gen_discard_reg tcg_gen_discard_i32 | |
198 | #define tcg_gen_trunc_reg_i32 tcg_gen_mov_i32 | |
199 | #define tcg_gen_trunc_i64_reg tcg_gen_extrl_i64_i32 | |
200 | #define tcg_gen_extu_i32_reg tcg_gen_mov_i32 | |
201 | #define tcg_gen_ext_i32_reg tcg_gen_mov_i32 | |
202 | #define tcg_gen_extu_reg_i64 tcg_gen_extu_i32_i64 | |
203 | #define tcg_gen_ext_reg_i64 tcg_gen_ext_i32_i64 | |
204 | #define tcg_gen_ext8u_reg tcg_gen_ext8u_i32 | |
205 | #define tcg_gen_ext8s_reg tcg_gen_ext8s_i32 | |
206 | #define tcg_gen_ext16u_reg tcg_gen_ext16u_i32 | |
207 | #define tcg_gen_ext16s_reg tcg_gen_ext16s_i32 | |
208 | #define tcg_gen_ext32u_reg tcg_gen_mov_i32 | |
209 | #define tcg_gen_ext32s_reg tcg_gen_mov_i32 | |
210 | #define tcg_gen_bswap16_reg tcg_gen_bswap16_i32 | |
211 | #define tcg_gen_bswap32_reg tcg_gen_bswap32_i32 | |
212 | #define tcg_gen_concat_reg_i64 tcg_gen_concat_i32_i64 | |
213 | #define tcg_gen_andc_reg tcg_gen_andc_i32 | |
214 | #define tcg_gen_eqv_reg tcg_gen_eqv_i32 | |
215 | #define tcg_gen_nand_reg tcg_gen_nand_i32 | |
216 | #define tcg_gen_nor_reg tcg_gen_nor_i32 | |
217 | #define tcg_gen_orc_reg tcg_gen_orc_i32 | |
218 | #define tcg_gen_clz_reg tcg_gen_clz_i32 | |
219 | #define tcg_gen_ctz_reg tcg_gen_ctz_i32 | |
220 | #define tcg_gen_clzi_reg tcg_gen_clzi_i32 | |
221 | #define tcg_gen_ctzi_reg tcg_gen_ctzi_i32 | |
222 | #define tcg_gen_clrsb_reg tcg_gen_clrsb_i32 | |
223 | #define tcg_gen_ctpop_reg tcg_gen_ctpop_i32 | |
224 | #define tcg_gen_rotl_reg tcg_gen_rotl_i32 | |
225 | #define tcg_gen_rotli_reg tcg_gen_rotli_i32 | |
226 | #define tcg_gen_rotr_reg tcg_gen_rotr_i32 | |
227 | #define tcg_gen_rotri_reg tcg_gen_rotri_i32 | |
228 | #define tcg_gen_deposit_reg tcg_gen_deposit_i32 | |
229 | #define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i32 | |
230 | #define tcg_gen_extract_reg tcg_gen_extract_i32 | |
231 | #define tcg_gen_sextract_reg tcg_gen_sextract_i32 | |
05bfd4db | 232 | #define tcg_gen_extract2_reg tcg_gen_extract2_i32 |
29dd6f64 | 233 | #define tcg_constant_reg tcg_constant_i32 |
eaa3783b RH |
234 | #define tcg_gen_movcond_reg tcg_gen_movcond_i32 |
235 | #define tcg_gen_add2_reg tcg_gen_add2_i32 | |
236 | #define tcg_gen_sub2_reg tcg_gen_sub2_i32 | |
237 | #define tcg_gen_qemu_ld_reg tcg_gen_qemu_ld_i32 | |
238 | #define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i32 | |
239 | #define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i32 | |
5bfa8034 | 240 | #define tcg_gen_trunc_reg_ptr tcg_gen_ext_i32_ptr |
eaa3783b RH |
241 | #endif /* TARGET_REGISTER_BITS */ |
242 | ||
61766fe9 RH |
243 | typedef struct DisasCond { |
244 | TCGCond c; | |
eaa3783b | 245 | TCGv_reg a0, a1; |
61766fe9 RH |
246 | } DisasCond; |
247 | ||
248 | typedef struct DisasContext { | |
d01a3625 | 249 | DisasContextBase base; |
61766fe9 RH |
250 | CPUState *cs; |
251 | ||
eaa3783b RH |
252 | target_ureg iaoq_f; |
253 | target_ureg iaoq_b; | |
254 | target_ureg iaoq_n; | |
255 | TCGv_reg iaoq_n_var; | |
61766fe9 | 256 | |
61766fe9 RH |
257 | DisasCond null_cond; |
258 | TCGLabel *null_lab; | |
259 | ||
1a19da0d | 260 | uint32_t insn; |
494737b7 | 261 | uint32_t tb_flags; |
3d68ee7b RH |
262 | int mmu_idx; |
263 | int privilege; | |
61766fe9 | 264 | bool psw_n_nonzero; |
bd6243a3 | 265 | bool is_pa20; |
217d1a5e RH |
266 | |
267 | #ifdef CONFIG_USER_ONLY | |
268 | MemOp unalign; | |
269 | #endif | |
61766fe9 RH |
270 | } DisasContext; |
271 | ||
217d1a5e RH |
272 | #ifdef CONFIG_USER_ONLY |
273 | #define UNALIGN(C) (C)->unalign | |
274 | #else | |
2d4afb03 | 275 | #define UNALIGN(C) MO_ALIGN |
217d1a5e RH |
276 | #endif |
277 | ||
e36f27ef | 278 | /* Note that ssm/rsm instructions number PSW_W and PSW_E differently. */ |
451e4ffd | 279 | static int expand_sm_imm(DisasContext *ctx, int val) |
e36f27ef RH |
280 | { |
281 | if (val & PSW_SM_E) { | |
282 | val = (val & ~PSW_SM_E) | PSW_E; | |
283 | } | |
284 | if (val & PSW_SM_W) { | |
285 | val = (val & ~PSW_SM_W) | PSW_W; | |
286 | } | |
287 | return val; | |
288 | } | |
289 | ||
deee69a1 | 290 | /* Inverted space register indicates 0 means sr0 not inferred from base. */ |
451e4ffd | 291 | static int expand_sr3x(DisasContext *ctx, int val) |
deee69a1 RH |
292 | { |
293 | return ~val; | |
294 | } | |
295 | ||
1cd012a5 RH |
296 | /* Convert the M:A bits within a memory insn to the tri-state value |
297 | we use for the final M. */ | |
451e4ffd | 298 | static int ma_to_m(DisasContext *ctx, int val) |
1cd012a5 RH |
299 | { |
300 | return val & 2 ? (val & 1 ? -1 : 1) : 0; | |
301 | } | |
302 | ||
740038d7 | 303 | /* Convert the sign of the displacement to a pre or post-modify. */ |
451e4ffd | 304 | static int pos_to_m(DisasContext *ctx, int val) |
740038d7 RH |
305 | { |
306 | return val ? 1 : -1; | |
307 | } | |
308 | ||
451e4ffd | 309 | static int neg_to_m(DisasContext *ctx, int val) |
740038d7 RH |
310 | { |
311 | return val ? -1 : 1; | |
312 | } | |
313 | ||
314 | /* Used for branch targets and fp memory ops. */ | |
451e4ffd | 315 | static int expand_shl2(DisasContext *ctx, int val) |
01afb7be RH |
316 | { |
317 | return val << 2; | |
318 | } | |
319 | ||
740038d7 | 320 | /* Used for fp memory ops. */ |
451e4ffd | 321 | static int expand_shl3(DisasContext *ctx, int val) |
740038d7 RH |
322 | { |
323 | return val << 3; | |
324 | } | |
325 | ||
0588e061 | 326 | /* Used for assemble_21. */ |
451e4ffd | 327 | static int expand_shl11(DisasContext *ctx, int val) |
0588e061 RH |
328 | { |
329 | return val << 11; | |
330 | } | |
331 | ||
01afb7be | 332 | |
40f9f908 | 333 | /* Include the auto-generated decoder. */ |
abff1abf | 334 | #include "decode-insns.c.inc" |
40f9f908 | 335 | |
869051ea RH |
336 | /* We are not using a goto_tb (for whatever reason), but have updated |
337 | the iaq (for whatever reason), so don't do it again on exit. */ | |
338 | #define DISAS_IAQ_N_UPDATED DISAS_TARGET_0 | |
61766fe9 | 339 | |
869051ea RH |
340 | /* We are exiting the TB, but have neither emitted a goto_tb, nor |
341 | updated the iaq for the next instruction to be executed. */ | |
342 | #define DISAS_IAQ_N_STALE DISAS_TARGET_1 | |
61766fe9 | 343 | |
e1b5a5ed RH |
344 | /* Similarly, but we want to return to the main loop immediately |
345 | to recognize unmasked interrupts. */ | |
346 | #define DISAS_IAQ_N_STALE_EXIT DISAS_TARGET_2 | |
c5d0aec2 | 347 | #define DISAS_EXIT DISAS_TARGET_3 |
e1b5a5ed | 348 | |
61766fe9 | 349 | /* global register indexes */ |
eaa3783b | 350 | static TCGv_reg cpu_gr[32]; |
33423472 | 351 | static TCGv_i64 cpu_sr[4]; |
494737b7 | 352 | static TCGv_i64 cpu_srH; |
eaa3783b RH |
353 | static TCGv_reg cpu_iaoq_f; |
354 | static TCGv_reg cpu_iaoq_b; | |
c301f34e RH |
355 | static TCGv_i64 cpu_iasq_f; |
356 | static TCGv_i64 cpu_iasq_b; | |
eaa3783b RH |
357 | static TCGv_reg cpu_sar; |
358 | static TCGv_reg cpu_psw_n; | |
359 | static TCGv_reg cpu_psw_v; | |
360 | static TCGv_reg cpu_psw_cb; | |
361 | static TCGv_reg cpu_psw_cb_msb; | |
61766fe9 | 362 | |
61766fe9 RH |
363 | void hppa_translate_init(void) |
364 | { | |
365 | #define DEF_VAR(V) { &cpu_##V, #V, offsetof(CPUHPPAState, V) } | |
366 | ||
eaa3783b | 367 | typedef struct { TCGv_reg *var; const char *name; int ofs; } GlobalVar; |
61766fe9 | 368 | static const GlobalVar vars[] = { |
35136a77 | 369 | { &cpu_sar, "sar", offsetof(CPUHPPAState, cr[CR_SAR]) }, |
61766fe9 RH |
370 | DEF_VAR(psw_n), |
371 | DEF_VAR(psw_v), | |
372 | DEF_VAR(psw_cb), | |
373 | DEF_VAR(psw_cb_msb), | |
374 | DEF_VAR(iaoq_f), | |
375 | DEF_VAR(iaoq_b), | |
376 | }; | |
377 | ||
378 | #undef DEF_VAR | |
379 | ||
380 | /* Use the symbolic register names that match the disassembler. */ | |
381 | static const char gr_names[32][4] = { | |
382 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
383 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
384 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
385 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | |
386 | }; | |
33423472 | 387 | /* SR[4-7] are not global registers so that we can index them. */ |
494737b7 RH |
388 | static const char sr_names[5][4] = { |
389 | "sr0", "sr1", "sr2", "sr3", "srH" | |
33423472 | 390 | }; |
61766fe9 | 391 | |
61766fe9 RH |
392 | int i; |
393 | ||
f764718d | 394 | cpu_gr[0] = NULL; |
61766fe9 | 395 | for (i = 1; i < 32; i++) { |
ad75a51e | 396 | cpu_gr[i] = tcg_global_mem_new(tcg_env, |
61766fe9 RH |
397 | offsetof(CPUHPPAState, gr[i]), |
398 | gr_names[i]); | |
399 | } | |
33423472 | 400 | for (i = 0; i < 4; i++) { |
ad75a51e | 401 | cpu_sr[i] = tcg_global_mem_new_i64(tcg_env, |
33423472 RH |
402 | offsetof(CPUHPPAState, sr[i]), |
403 | sr_names[i]); | |
404 | } | |
ad75a51e | 405 | cpu_srH = tcg_global_mem_new_i64(tcg_env, |
494737b7 RH |
406 | offsetof(CPUHPPAState, sr[4]), |
407 | sr_names[4]); | |
61766fe9 RH |
408 | |
409 | for (i = 0; i < ARRAY_SIZE(vars); ++i) { | |
410 | const GlobalVar *v = &vars[i]; | |
ad75a51e | 411 | *v->var = tcg_global_mem_new(tcg_env, v->ofs, v->name); |
61766fe9 | 412 | } |
c301f34e | 413 | |
ad75a51e | 414 | cpu_iasq_f = tcg_global_mem_new_i64(tcg_env, |
c301f34e RH |
415 | offsetof(CPUHPPAState, iasq_f), |
416 | "iasq_f"); | |
ad75a51e | 417 | cpu_iasq_b = tcg_global_mem_new_i64(tcg_env, |
c301f34e RH |
418 | offsetof(CPUHPPAState, iasq_b), |
419 | "iasq_b"); | |
61766fe9 RH |
420 | } |
421 | ||
129e9cc3 RH |
422 | static DisasCond cond_make_f(void) |
423 | { | |
f764718d RH |
424 | return (DisasCond){ |
425 | .c = TCG_COND_NEVER, | |
426 | .a0 = NULL, | |
427 | .a1 = NULL, | |
428 | }; | |
129e9cc3 RH |
429 | } |
430 | ||
df0232fe RH |
431 | static DisasCond cond_make_t(void) |
432 | { | |
433 | return (DisasCond){ | |
434 | .c = TCG_COND_ALWAYS, | |
435 | .a0 = NULL, | |
436 | .a1 = NULL, | |
437 | }; | |
438 | } | |
439 | ||
129e9cc3 RH |
440 | static DisasCond cond_make_n(void) |
441 | { | |
f764718d RH |
442 | return (DisasCond){ |
443 | .c = TCG_COND_NE, | |
444 | .a0 = cpu_psw_n, | |
6e94937a | 445 | .a1 = tcg_constant_reg(0) |
f764718d | 446 | }; |
129e9cc3 RH |
447 | } |
448 | ||
4fe9533a | 449 | static DisasCond cond_make_tmp(TCGCond c, TCGv_reg a0, TCGv_reg a1) |
129e9cc3 | 450 | { |
129e9cc3 | 451 | assert (c != TCG_COND_NEVER && c != TCG_COND_ALWAYS); |
4fe9533a RH |
452 | return (DisasCond){ .c = c, .a0 = a0, .a1 = a1 }; |
453 | } | |
454 | ||
455 | static DisasCond cond_make_0_tmp(TCGCond c, TCGv_reg a0) | |
456 | { | |
457 | return cond_make_tmp(c, a0, tcg_constant_reg(0)); | |
b47a4a02 | 458 | } |
129e9cc3 | 459 | |
b47a4a02 SS |
460 | static DisasCond cond_make_0(TCGCond c, TCGv_reg a0) |
461 | { | |
462 | TCGv_reg tmp = tcg_temp_new(); | |
463 | tcg_gen_mov_reg(tmp, a0); | |
464 | return cond_make_0_tmp(c, tmp); | |
129e9cc3 RH |
465 | } |
466 | ||
eaa3783b | 467 | static DisasCond cond_make(TCGCond c, TCGv_reg a0, TCGv_reg a1) |
129e9cc3 | 468 | { |
4fe9533a RH |
469 | TCGv_reg t0 = tcg_temp_new(); |
470 | TCGv_reg t1 = tcg_temp_new(); | |
129e9cc3 | 471 | |
4fe9533a RH |
472 | tcg_gen_mov_reg(t0, a0); |
473 | tcg_gen_mov_reg(t1, a1); | |
474 | return cond_make_tmp(c, t0, t1); | |
129e9cc3 RH |
475 | } |
476 | ||
129e9cc3 RH |
477 | static void cond_free(DisasCond *cond) |
478 | { | |
479 | switch (cond->c) { | |
480 | default: | |
f764718d RH |
481 | cond->a0 = NULL; |
482 | cond->a1 = NULL; | |
129e9cc3 RH |
483 | /* fallthru */ |
484 | case TCG_COND_ALWAYS: | |
485 | cond->c = TCG_COND_NEVER; | |
486 | break; | |
487 | case TCG_COND_NEVER: | |
488 | break; | |
489 | } | |
490 | } | |
491 | ||
eaa3783b | 492 | static TCGv_reg load_gpr(DisasContext *ctx, unsigned reg) |
61766fe9 RH |
493 | { |
494 | if (reg == 0) { | |
e12c6309 | 495 | TCGv_reg t = tcg_temp_new(); |
eaa3783b | 496 | tcg_gen_movi_reg(t, 0); |
61766fe9 RH |
497 | return t; |
498 | } else { | |
499 | return cpu_gr[reg]; | |
500 | } | |
501 | } | |
502 | ||
eaa3783b | 503 | static TCGv_reg dest_gpr(DisasContext *ctx, unsigned reg) |
61766fe9 | 504 | { |
129e9cc3 | 505 | if (reg == 0 || ctx->null_cond.c != TCG_COND_NEVER) { |
e12c6309 | 506 | return tcg_temp_new(); |
61766fe9 RH |
507 | } else { |
508 | return cpu_gr[reg]; | |
509 | } | |
510 | } | |
511 | ||
eaa3783b | 512 | static void save_or_nullify(DisasContext *ctx, TCGv_reg dest, TCGv_reg t) |
129e9cc3 RH |
513 | { |
514 | if (ctx->null_cond.c != TCG_COND_NEVER) { | |
eaa3783b | 515 | tcg_gen_movcond_reg(ctx->null_cond.c, dest, ctx->null_cond.a0, |
6e94937a | 516 | ctx->null_cond.a1, dest, t); |
129e9cc3 | 517 | } else { |
eaa3783b | 518 | tcg_gen_mov_reg(dest, t); |
129e9cc3 RH |
519 | } |
520 | } | |
521 | ||
eaa3783b | 522 | static void save_gpr(DisasContext *ctx, unsigned reg, TCGv_reg t) |
129e9cc3 RH |
523 | { |
524 | if (reg != 0) { | |
525 | save_or_nullify(ctx, cpu_gr[reg], t); | |
526 | } | |
527 | } | |
528 | ||
e03b5686 | 529 | #if HOST_BIG_ENDIAN |
96d6407f RH |
530 | # define HI_OFS 0 |
531 | # define LO_OFS 4 | |
532 | #else | |
533 | # define HI_OFS 4 | |
534 | # define LO_OFS 0 | |
535 | #endif | |
536 | ||
537 | static TCGv_i32 load_frw_i32(unsigned rt) | |
538 | { | |
539 | TCGv_i32 ret = tcg_temp_new_i32(); | |
ad75a51e | 540 | tcg_gen_ld_i32(ret, tcg_env, |
96d6407f RH |
541 | offsetof(CPUHPPAState, fr[rt & 31]) |
542 | + (rt & 32 ? LO_OFS : HI_OFS)); | |
543 | return ret; | |
544 | } | |
545 | ||
ebe9383c RH |
546 | static TCGv_i32 load_frw0_i32(unsigned rt) |
547 | { | |
548 | if (rt == 0) { | |
0992a930 RH |
549 | TCGv_i32 ret = tcg_temp_new_i32(); |
550 | tcg_gen_movi_i32(ret, 0); | |
551 | return ret; | |
ebe9383c RH |
552 | } else { |
553 | return load_frw_i32(rt); | |
554 | } | |
555 | } | |
556 | ||
557 | static TCGv_i64 load_frw0_i64(unsigned rt) | |
558 | { | |
0992a930 | 559 | TCGv_i64 ret = tcg_temp_new_i64(); |
ebe9383c | 560 | if (rt == 0) { |
0992a930 | 561 | tcg_gen_movi_i64(ret, 0); |
ebe9383c | 562 | } else { |
ad75a51e | 563 | tcg_gen_ld32u_i64(ret, tcg_env, |
ebe9383c RH |
564 | offsetof(CPUHPPAState, fr[rt & 31]) |
565 | + (rt & 32 ? LO_OFS : HI_OFS)); | |
ebe9383c | 566 | } |
0992a930 | 567 | return ret; |
ebe9383c RH |
568 | } |
569 | ||
96d6407f RH |
570 | static void save_frw_i32(unsigned rt, TCGv_i32 val) |
571 | { | |
ad75a51e | 572 | tcg_gen_st_i32(val, tcg_env, |
96d6407f RH |
573 | offsetof(CPUHPPAState, fr[rt & 31]) |
574 | + (rt & 32 ? LO_OFS : HI_OFS)); | |
575 | } | |
576 | ||
577 | #undef HI_OFS | |
578 | #undef LO_OFS | |
579 | ||
580 | static TCGv_i64 load_frd(unsigned rt) | |
581 | { | |
582 | TCGv_i64 ret = tcg_temp_new_i64(); | |
ad75a51e | 583 | tcg_gen_ld_i64(ret, tcg_env, offsetof(CPUHPPAState, fr[rt])); |
96d6407f RH |
584 | return ret; |
585 | } | |
586 | ||
ebe9383c RH |
587 | static TCGv_i64 load_frd0(unsigned rt) |
588 | { | |
589 | if (rt == 0) { | |
0992a930 RH |
590 | TCGv_i64 ret = tcg_temp_new_i64(); |
591 | tcg_gen_movi_i64(ret, 0); | |
592 | return ret; | |
ebe9383c RH |
593 | } else { |
594 | return load_frd(rt); | |
595 | } | |
596 | } | |
597 | ||
96d6407f RH |
598 | static void save_frd(unsigned rt, TCGv_i64 val) |
599 | { | |
ad75a51e | 600 | tcg_gen_st_i64(val, tcg_env, offsetof(CPUHPPAState, fr[rt])); |
96d6407f RH |
601 | } |
602 | ||
33423472 RH |
603 | static void load_spr(DisasContext *ctx, TCGv_i64 dest, unsigned reg) |
604 | { | |
605 | #ifdef CONFIG_USER_ONLY | |
606 | tcg_gen_movi_i64(dest, 0); | |
607 | #else | |
608 | if (reg < 4) { | |
609 | tcg_gen_mov_i64(dest, cpu_sr[reg]); | |
494737b7 RH |
610 | } else if (ctx->tb_flags & TB_FLAG_SR_SAME) { |
611 | tcg_gen_mov_i64(dest, cpu_srH); | |
33423472 | 612 | } else { |
ad75a51e | 613 | tcg_gen_ld_i64(dest, tcg_env, offsetof(CPUHPPAState, sr[reg])); |
33423472 RH |
614 | } |
615 | #endif | |
616 | } | |
617 | ||
129e9cc3 RH |
618 | /* Skip over the implementation of an insn that has been nullified. |
619 | Use this when the insn is too complex for a conditional move. */ | |
620 | static void nullify_over(DisasContext *ctx) | |
621 | { | |
622 | if (ctx->null_cond.c != TCG_COND_NEVER) { | |
623 | /* The always condition should have been handled in the main loop. */ | |
624 | assert(ctx->null_cond.c != TCG_COND_ALWAYS); | |
625 | ||
626 | ctx->null_lab = gen_new_label(); | |
129e9cc3 RH |
627 | |
628 | /* If we're using PSW[N], copy it to a temp because... */ | |
6e94937a | 629 | if (ctx->null_cond.a0 == cpu_psw_n) { |
129e9cc3 | 630 | ctx->null_cond.a0 = tcg_temp_new(); |
eaa3783b | 631 | tcg_gen_mov_reg(ctx->null_cond.a0, cpu_psw_n); |
129e9cc3 RH |
632 | } |
633 | /* ... we clear it before branching over the implementation, | |
634 | so that (1) it's clear after nullifying this insn and | |
635 | (2) if this insn nullifies the next, PSW[N] is valid. */ | |
636 | if (ctx->psw_n_nonzero) { | |
637 | ctx->psw_n_nonzero = false; | |
eaa3783b | 638 | tcg_gen_movi_reg(cpu_psw_n, 0); |
129e9cc3 RH |
639 | } |
640 | ||
eaa3783b | 641 | tcg_gen_brcond_reg(ctx->null_cond.c, ctx->null_cond.a0, |
6e94937a | 642 | ctx->null_cond.a1, ctx->null_lab); |
129e9cc3 RH |
643 | cond_free(&ctx->null_cond); |
644 | } | |
645 | } | |
646 | ||
647 | /* Save the current nullification state to PSW[N]. */ | |
648 | static void nullify_save(DisasContext *ctx) | |
649 | { | |
650 | if (ctx->null_cond.c == TCG_COND_NEVER) { | |
651 | if (ctx->psw_n_nonzero) { | |
eaa3783b | 652 | tcg_gen_movi_reg(cpu_psw_n, 0); |
129e9cc3 RH |
653 | } |
654 | return; | |
655 | } | |
6e94937a | 656 | if (ctx->null_cond.a0 != cpu_psw_n) { |
eaa3783b | 657 | tcg_gen_setcond_reg(ctx->null_cond.c, cpu_psw_n, |
6e94937a | 658 | ctx->null_cond.a0, ctx->null_cond.a1); |
129e9cc3 RH |
659 | ctx->psw_n_nonzero = true; |
660 | } | |
661 | cond_free(&ctx->null_cond); | |
662 | } | |
663 | ||
664 | /* Set a PSW[N] to X. The intention is that this is used immediately | |
665 | before a goto_tb/exit_tb, so that there is no fallthru path to other | |
666 | code within the TB. Therefore we do not update psw_n_nonzero. */ | |
667 | static void nullify_set(DisasContext *ctx, bool x) | |
668 | { | |
669 | if (ctx->psw_n_nonzero || x) { | |
eaa3783b | 670 | tcg_gen_movi_reg(cpu_psw_n, x); |
129e9cc3 RH |
671 | } |
672 | } | |
673 | ||
674 | /* Mark the end of an instruction that may have been nullified. | |
40f9f908 RH |
675 | This is the pair to nullify_over. Always returns true so that |
676 | it may be tail-called from a translate function. */ | |
31234768 | 677 | static bool nullify_end(DisasContext *ctx) |
129e9cc3 RH |
678 | { |
679 | TCGLabel *null_lab = ctx->null_lab; | |
31234768 | 680 | DisasJumpType status = ctx->base.is_jmp; |
129e9cc3 | 681 | |
f49b3537 RH |
682 | /* For NEXT, NORETURN, STALE, we can easily continue (or exit). |
683 | For UPDATED, we cannot update on the nullified path. */ | |
684 | assert(status != DISAS_IAQ_N_UPDATED); | |
685 | ||
129e9cc3 RH |
686 | if (likely(null_lab == NULL)) { |
687 | /* The current insn wasn't conditional or handled the condition | |
688 | applied to it without a branch, so the (new) setting of | |
689 | NULL_COND can be applied directly to the next insn. */ | |
31234768 | 690 | return true; |
129e9cc3 RH |
691 | } |
692 | ctx->null_lab = NULL; | |
693 | ||
694 | if (likely(ctx->null_cond.c == TCG_COND_NEVER)) { | |
695 | /* The next instruction will be unconditional, | |
696 | and NULL_COND already reflects that. */ | |
697 | gen_set_label(null_lab); | |
698 | } else { | |
699 | /* The insn that we just executed is itself nullifying the next | |
700 | instruction. Store the condition in the PSW[N] global. | |
701 | We asserted PSW[N] = 0 in nullify_over, so that after the | |
702 | label we have the proper value in place. */ | |
703 | nullify_save(ctx); | |
704 | gen_set_label(null_lab); | |
705 | ctx->null_cond = cond_make_n(); | |
706 | } | |
869051ea | 707 | if (status == DISAS_NORETURN) { |
31234768 | 708 | ctx->base.is_jmp = DISAS_NEXT; |
129e9cc3 | 709 | } |
31234768 | 710 | return true; |
129e9cc3 RH |
711 | } |
712 | ||
698240d1 RH |
713 | static target_ureg gva_offset_mask(DisasContext *ctx) |
714 | { | |
715 | return (ctx->tb_flags & PSW_W | |
716 | ? MAKE_64BIT_MASK(0, 62) | |
717 | : MAKE_64BIT_MASK(0, 32)); | |
718 | } | |
719 | ||
741322f4 RH |
720 | static void copy_iaoq_entry(DisasContext *ctx, TCGv_reg dest, |
721 | target_ureg ival, TCGv_reg vval) | |
61766fe9 | 722 | { |
f13bf343 RH |
723 | target_ureg mask = gva_offset_mask(ctx); |
724 | ||
725 | if (ival != -1) { | |
726 | tcg_gen_movi_reg(dest, ival & mask); | |
727 | return; | |
728 | } | |
729 | tcg_debug_assert(vval != NULL); | |
730 | ||
731 | /* | |
732 | * We know that the IAOQ is already properly masked. | |
733 | * This optimization is primarily for "iaoq_f = iaoq_b". | |
734 | */ | |
735 | if (vval == cpu_iaoq_f || vval == cpu_iaoq_b) { | |
eaa3783b | 736 | tcg_gen_mov_reg(dest, vval); |
61766fe9 | 737 | } else { |
f13bf343 | 738 | tcg_gen_andi_reg(dest, vval, mask); |
61766fe9 RH |
739 | } |
740 | } | |
741 | ||
eaa3783b | 742 | static inline target_ureg iaoq_dest(DisasContext *ctx, target_sreg disp) |
61766fe9 RH |
743 | { |
744 | return ctx->iaoq_f + disp + 8; | |
745 | } | |
746 | ||
747 | static void gen_excp_1(int exception) | |
748 | { | |
ad75a51e | 749 | gen_helper_excp(tcg_env, tcg_constant_i32(exception)); |
61766fe9 RH |
750 | } |
751 | ||
31234768 | 752 | static void gen_excp(DisasContext *ctx, int exception) |
61766fe9 | 753 | { |
741322f4 RH |
754 | copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_f, cpu_iaoq_f); |
755 | copy_iaoq_entry(ctx, cpu_iaoq_b, ctx->iaoq_b, cpu_iaoq_b); | |
129e9cc3 | 756 | nullify_save(ctx); |
61766fe9 | 757 | gen_excp_1(exception); |
31234768 | 758 | ctx->base.is_jmp = DISAS_NORETURN; |
61766fe9 RH |
759 | } |
760 | ||
31234768 | 761 | static bool gen_excp_iir(DisasContext *ctx, int exc) |
1a19da0d | 762 | { |
31234768 | 763 | nullify_over(ctx); |
29dd6f64 | 764 | tcg_gen_st_reg(tcg_constant_reg(ctx->insn), |
ad75a51e | 765 | tcg_env, offsetof(CPUHPPAState, cr[CR_IIR])); |
31234768 RH |
766 | gen_excp(ctx, exc); |
767 | return nullify_end(ctx); | |
1a19da0d RH |
768 | } |
769 | ||
31234768 | 770 | static bool gen_illegal(DisasContext *ctx) |
61766fe9 | 771 | { |
31234768 | 772 | return gen_excp_iir(ctx, EXCP_ILL); |
61766fe9 RH |
773 | } |
774 | ||
40f9f908 RH |
775 | #ifdef CONFIG_USER_ONLY |
776 | #define CHECK_MOST_PRIVILEGED(EXCP) \ | |
777 | return gen_excp_iir(ctx, EXCP) | |
778 | #else | |
779 | #define CHECK_MOST_PRIVILEGED(EXCP) \ | |
31234768 RH |
780 | do { \ |
781 | if (ctx->privilege != 0) { \ | |
782 | return gen_excp_iir(ctx, EXCP); \ | |
783 | } \ | |
e1b5a5ed | 784 | } while (0) |
40f9f908 | 785 | #endif |
e1b5a5ed | 786 | |
eaa3783b | 787 | static bool use_goto_tb(DisasContext *ctx, target_ureg dest) |
61766fe9 | 788 | { |
57f91498 | 789 | return translator_use_goto_tb(&ctx->base, dest); |
61766fe9 RH |
790 | } |
791 | ||
129e9cc3 RH |
792 | /* If the next insn is to be nullified, and it's on the same page, |
793 | and we're not attempting to set a breakpoint on it, then we can | |
794 | totally skip the nullified insn. This avoids creating and | |
795 | executing a TB that merely branches to the next TB. */ | |
796 | static bool use_nullify_skip(DisasContext *ctx) | |
797 | { | |
798 | return (((ctx->iaoq_b ^ ctx->iaoq_f) & TARGET_PAGE_MASK) == 0 | |
799 | && !cpu_breakpoint_test(ctx->cs, ctx->iaoq_b, BP_ANY)); | |
800 | } | |
801 | ||
61766fe9 | 802 | static void gen_goto_tb(DisasContext *ctx, int which, |
eaa3783b | 803 | target_ureg f, target_ureg b) |
61766fe9 RH |
804 | { |
805 | if (f != -1 && b != -1 && use_goto_tb(ctx, f)) { | |
806 | tcg_gen_goto_tb(which); | |
a0180973 RH |
807 | copy_iaoq_entry(ctx, cpu_iaoq_f, f, NULL); |
808 | copy_iaoq_entry(ctx, cpu_iaoq_b, b, NULL); | |
07ea28b4 | 809 | tcg_gen_exit_tb(ctx->base.tb, which); |
61766fe9 | 810 | } else { |
741322f4 RH |
811 | copy_iaoq_entry(ctx, cpu_iaoq_f, f, cpu_iaoq_b); |
812 | copy_iaoq_entry(ctx, cpu_iaoq_b, b, ctx->iaoq_n_var); | |
8532a14e | 813 | tcg_gen_lookup_and_goto_ptr(); |
61766fe9 RH |
814 | } |
815 | } | |
816 | ||
b47a4a02 SS |
817 | static bool cond_need_sv(int c) |
818 | { | |
819 | return c == 2 || c == 3 || c == 6; | |
820 | } | |
821 | ||
822 | static bool cond_need_cb(int c) | |
823 | { | |
824 | return c == 4 || c == 5; | |
825 | } | |
826 | ||
72ca8753 RH |
827 | /* Need extensions from TCGv_i32 to TCGv_reg. */ |
828 | static bool cond_need_ext(DisasContext *ctx, bool d) | |
829 | { | |
a751eb31 | 830 | return TARGET_REGISTER_BITS == 64 && !(ctx->is_pa20 && d); |
72ca8753 RH |
831 | } |
832 | ||
b47a4a02 SS |
833 | /* |
834 | * Compute conditional for arithmetic. See Page 5-3, Table 5-1, of | |
835 | * the Parisc 1.1 Architecture Reference Manual for details. | |
836 | */ | |
b2167459 | 837 | |
a751eb31 RH |
838 | static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, |
839 | TCGv_reg res, TCGv_reg cb_msb, TCGv_reg sv) | |
b2167459 RH |
840 | { |
841 | DisasCond cond; | |
eaa3783b | 842 | TCGv_reg tmp; |
b2167459 RH |
843 | |
844 | switch (cf >> 1) { | |
b47a4a02 | 845 | case 0: /* Never / TR (0 / 1) */ |
b2167459 RH |
846 | cond = cond_make_f(); |
847 | break; | |
848 | case 1: /* = / <> (Z / !Z) */ | |
a751eb31 RH |
849 | if (cond_need_ext(ctx, d)) { |
850 | tmp = tcg_temp_new(); | |
851 | tcg_gen_ext32u_reg(tmp, res); | |
852 | res = tmp; | |
853 | } | |
b2167459 RH |
854 | cond = cond_make_0(TCG_COND_EQ, res); |
855 | break; | |
b47a4a02 SS |
856 | case 2: /* < / >= (N ^ V / !(N ^ V) */ |
857 | tmp = tcg_temp_new(); | |
858 | tcg_gen_xor_reg(tmp, res, sv); | |
a751eb31 RH |
859 | if (cond_need_ext(ctx, d)) { |
860 | tcg_gen_ext32s_reg(tmp, tmp); | |
861 | } | |
b47a4a02 | 862 | cond = cond_make_0_tmp(TCG_COND_LT, tmp); |
b2167459 | 863 | break; |
b47a4a02 SS |
864 | case 3: /* <= / > (N ^ V) | Z / !((N ^ V) | Z) */ |
865 | /* | |
866 | * Simplify: | |
867 | * (N ^ V) | Z | |
868 | * ((res < 0) ^ (sv < 0)) | !res | |
869 | * ((res ^ sv) < 0) | !res | |
870 | * (~(res ^ sv) >= 0) | !res | |
871 | * !(~(res ^ sv) >> 31) | !res | |
872 | * !(~(res ^ sv) >> 31 & res) | |
873 | */ | |
874 | tmp = tcg_temp_new(); | |
875 | tcg_gen_eqv_reg(tmp, res, sv); | |
a751eb31 RH |
876 | if (cond_need_ext(ctx, d)) { |
877 | tcg_gen_sextract_reg(tmp, tmp, 31, 1); | |
878 | tcg_gen_and_reg(tmp, tmp, res); | |
879 | tcg_gen_ext32u_reg(tmp, tmp); | |
880 | } else { | |
881 | tcg_gen_sari_reg(tmp, tmp, TARGET_REGISTER_BITS - 1); | |
882 | tcg_gen_and_reg(tmp, tmp, res); | |
883 | } | |
b47a4a02 | 884 | cond = cond_make_0_tmp(TCG_COND_EQ, tmp); |
b2167459 RH |
885 | break; |
886 | case 4: /* NUV / UV (!C / C) */ | |
a751eb31 | 887 | /* Only bit 0 of cb_msb is ever set. */ |
b2167459 RH |
888 | cond = cond_make_0(TCG_COND_EQ, cb_msb); |
889 | break; | |
890 | case 5: /* ZNV / VNZ (!C | Z / C & !Z) */ | |
891 | tmp = tcg_temp_new(); | |
eaa3783b RH |
892 | tcg_gen_neg_reg(tmp, cb_msb); |
893 | tcg_gen_and_reg(tmp, tmp, res); | |
a751eb31 RH |
894 | if (cond_need_ext(ctx, d)) { |
895 | tcg_gen_ext32u_reg(tmp, tmp); | |
896 | } | |
b47a4a02 | 897 | cond = cond_make_0_tmp(TCG_COND_EQ, tmp); |
b2167459 RH |
898 | break; |
899 | case 6: /* SV / NSV (V / !V) */ | |
a751eb31 RH |
900 | if (cond_need_ext(ctx, d)) { |
901 | tmp = tcg_temp_new(); | |
902 | tcg_gen_ext32s_reg(tmp, sv); | |
903 | sv = tmp; | |
904 | } | |
b2167459 RH |
905 | cond = cond_make_0(TCG_COND_LT, sv); |
906 | break; | |
907 | case 7: /* OD / EV */ | |
908 | tmp = tcg_temp_new(); | |
eaa3783b | 909 | tcg_gen_andi_reg(tmp, res, 1); |
b47a4a02 | 910 | cond = cond_make_0_tmp(TCG_COND_NE, tmp); |
b2167459 RH |
911 | break; |
912 | default: | |
913 | g_assert_not_reached(); | |
914 | } | |
915 | if (cf & 1) { | |
916 | cond.c = tcg_invert_cond(cond.c); | |
917 | } | |
918 | ||
919 | return cond; | |
920 | } | |
921 | ||
922 | /* Similar, but for the special case of subtraction without borrow, we | |
923 | can use the inputs directly. This can allow other computation to be | |
924 | deleted as unused. */ | |
925 | ||
4fe9533a RH |
926 | static DisasCond do_sub_cond(DisasContext *ctx, unsigned cf, bool d, |
927 | TCGv_reg res, TCGv_reg in1, | |
928 | TCGv_reg in2, TCGv_reg sv) | |
b2167459 | 929 | { |
4fe9533a RH |
930 | TCGCond tc; |
931 | bool ext_uns; | |
b2167459 RH |
932 | |
933 | switch (cf >> 1) { | |
934 | case 1: /* = / <> */ | |
4fe9533a RH |
935 | tc = TCG_COND_EQ; |
936 | ext_uns = true; | |
b2167459 RH |
937 | break; |
938 | case 2: /* < / >= */ | |
4fe9533a RH |
939 | tc = TCG_COND_LT; |
940 | ext_uns = false; | |
b2167459 RH |
941 | break; |
942 | case 3: /* <= / > */ | |
4fe9533a RH |
943 | tc = TCG_COND_LE; |
944 | ext_uns = false; | |
b2167459 RH |
945 | break; |
946 | case 4: /* << / >>= */ | |
4fe9533a RH |
947 | tc = TCG_COND_LTU; |
948 | ext_uns = true; | |
b2167459 RH |
949 | break; |
950 | case 5: /* <<= / >> */ | |
4fe9533a RH |
951 | tc = TCG_COND_LEU; |
952 | ext_uns = true; | |
b2167459 RH |
953 | break; |
954 | default: | |
a751eb31 | 955 | return do_cond(ctx, cf, d, res, NULL, sv); |
b2167459 | 956 | } |
4fe9533a | 957 | |
b2167459 | 958 | if (cf & 1) { |
4fe9533a | 959 | tc = tcg_invert_cond(tc); |
b2167459 | 960 | } |
4fe9533a RH |
961 | if (cond_need_ext(ctx, d)) { |
962 | TCGv_reg t1 = tcg_temp_new(); | |
963 | TCGv_reg t2 = tcg_temp_new(); | |
b2167459 | 964 | |
4fe9533a RH |
965 | if (ext_uns) { |
966 | tcg_gen_ext32u_reg(t1, in1); | |
967 | tcg_gen_ext32u_reg(t2, in2); | |
968 | } else { | |
969 | tcg_gen_ext32s_reg(t1, in1); | |
970 | tcg_gen_ext32s_reg(t2, in2); | |
971 | } | |
972 | return cond_make_tmp(tc, t1, t2); | |
973 | } | |
974 | return cond_make(tc, in1, in2); | |
b2167459 RH |
975 | } |
976 | ||
df0232fe RH |
977 | /* |
978 | * Similar, but for logicals, where the carry and overflow bits are not | |
979 | * computed, and use of them is undefined. | |
980 | * | |
981 | * Undefined or not, hardware does not trap. It seems reasonable to | |
982 | * assume hardware treats cases c={4,5,6} as if C=0 & V=0, since that's | |
983 | * how cases c={2,3} are treated. | |
984 | */ | |
b2167459 | 985 | |
b5af8423 RH |
986 | static DisasCond do_log_cond(DisasContext *ctx, unsigned cf, bool d, |
987 | TCGv_reg res) | |
b2167459 | 988 | { |
b5af8423 RH |
989 | TCGCond tc; |
990 | bool ext_uns; | |
a751eb31 | 991 | |
df0232fe RH |
992 | switch (cf) { |
993 | case 0: /* never */ | |
994 | case 9: /* undef, C */ | |
995 | case 11: /* undef, C & !Z */ | |
996 | case 12: /* undef, V */ | |
997 | return cond_make_f(); | |
998 | ||
999 | case 1: /* true */ | |
1000 | case 8: /* undef, !C */ | |
1001 | case 10: /* undef, !C | Z */ | |
1002 | case 13: /* undef, !V */ | |
1003 | return cond_make_t(); | |
1004 | ||
1005 | case 2: /* == */ | |
b5af8423 RH |
1006 | tc = TCG_COND_EQ; |
1007 | ext_uns = true; | |
1008 | break; | |
df0232fe | 1009 | case 3: /* <> */ |
b5af8423 RH |
1010 | tc = TCG_COND_NE; |
1011 | ext_uns = true; | |
1012 | break; | |
df0232fe | 1013 | case 4: /* < */ |
b5af8423 RH |
1014 | tc = TCG_COND_LT; |
1015 | ext_uns = false; | |
1016 | break; | |
df0232fe | 1017 | case 5: /* >= */ |
b5af8423 RH |
1018 | tc = TCG_COND_GE; |
1019 | ext_uns = false; | |
1020 | break; | |
df0232fe | 1021 | case 6: /* <= */ |
b5af8423 RH |
1022 | tc = TCG_COND_LE; |
1023 | ext_uns = false; | |
1024 | break; | |
df0232fe | 1025 | case 7: /* > */ |
b5af8423 RH |
1026 | tc = TCG_COND_GT; |
1027 | ext_uns = false; | |
1028 | break; | |
df0232fe RH |
1029 | |
1030 | case 14: /* OD */ | |
1031 | case 15: /* EV */ | |
a751eb31 | 1032 | return do_cond(ctx, cf, d, res, NULL, NULL); |
df0232fe RH |
1033 | |
1034 | default: | |
1035 | g_assert_not_reached(); | |
b2167459 | 1036 | } |
b5af8423 RH |
1037 | |
1038 | if (cond_need_ext(ctx, d)) { | |
1039 | TCGv_reg tmp = tcg_temp_new(); | |
1040 | ||
1041 | if (ext_uns) { | |
1042 | tcg_gen_ext32u_reg(tmp, res); | |
1043 | } else { | |
1044 | tcg_gen_ext32s_reg(tmp, res); | |
1045 | } | |
1046 | return cond_make_0_tmp(tc, tmp); | |
1047 | } | |
1048 | return cond_make_0(tc, res); | |
b2167459 RH |
1049 | } |
1050 | ||
98cd9ca7 RH |
1051 | /* Similar, but for shift/extract/deposit conditions. */ |
1052 | ||
4fa52edf RH |
1053 | static DisasCond do_sed_cond(DisasContext *ctx, unsigned orig, bool d, |
1054 | TCGv_reg res) | |
98cd9ca7 RH |
1055 | { |
1056 | unsigned c, f; | |
1057 | ||
1058 | /* Convert the compressed condition codes to standard. | |
1059 | 0-2 are the same as logicals (nv,<,<=), while 3 is OD. | |
1060 | 4-7 are the reverse of 0-3. */ | |
1061 | c = orig & 3; | |
1062 | if (c == 3) { | |
1063 | c = 7; | |
1064 | } | |
1065 | f = (orig & 4) / 4; | |
1066 | ||
b5af8423 | 1067 | return do_log_cond(ctx, c * 2 + f, d, res); |
98cd9ca7 RH |
1068 | } |
1069 | ||
b2167459 RH |
1070 | /* Similar, but for unit conditions. */ |
1071 | ||
59963d8f | 1072 | static DisasCond do_unit_cond(unsigned cf, bool d, TCGv_reg res, |
eaa3783b | 1073 | TCGv_reg in1, TCGv_reg in2) |
b2167459 RH |
1074 | { |
1075 | DisasCond cond; | |
eaa3783b | 1076 | TCGv_reg tmp, cb = NULL; |
59963d8f | 1077 | target_ureg d_repl = d ? 0x0000000100000001ull : 1; |
b2167459 | 1078 | |
b2167459 RH |
1079 | if (cf & 8) { |
1080 | /* Since we want to test lots of carry-out bits all at once, do not | |
1081 | * do our normal thing and compute carry-in of bit B+1 since that | |
1082 | * leaves us with carry bits spread across two words. | |
1083 | */ | |
1084 | cb = tcg_temp_new(); | |
1085 | tmp = tcg_temp_new(); | |
eaa3783b RH |
1086 | tcg_gen_or_reg(cb, in1, in2); |
1087 | tcg_gen_and_reg(tmp, in1, in2); | |
1088 | tcg_gen_andc_reg(cb, cb, res); | |
1089 | tcg_gen_or_reg(cb, cb, tmp); | |
b2167459 RH |
1090 | } |
1091 | ||
1092 | switch (cf >> 1) { | |
1093 | case 0: /* never / TR */ | |
1094 | case 1: /* undefined */ | |
1095 | case 5: /* undefined */ | |
1096 | cond = cond_make_f(); | |
1097 | break; | |
1098 | ||
1099 | case 2: /* SBZ / NBZ */ | |
1100 | /* See hasless(v,1) from | |
1101 | * https://graphics.stanford.edu/~seander/bithacks.html#ZeroInWord | |
1102 | */ | |
1103 | tmp = tcg_temp_new(); | |
59963d8f | 1104 | tcg_gen_subi_reg(tmp, res, d_repl * 0x01010101u); |
eaa3783b | 1105 | tcg_gen_andc_reg(tmp, tmp, res); |
59963d8f | 1106 | tcg_gen_andi_reg(tmp, tmp, d_repl * 0x80808080u); |
b2167459 | 1107 | cond = cond_make_0(TCG_COND_NE, tmp); |
b2167459 RH |
1108 | break; |
1109 | ||
1110 | case 3: /* SHZ / NHZ */ | |
1111 | tmp = tcg_temp_new(); | |
59963d8f | 1112 | tcg_gen_subi_reg(tmp, res, d_repl * 0x00010001u); |
eaa3783b | 1113 | tcg_gen_andc_reg(tmp, tmp, res); |
59963d8f | 1114 | tcg_gen_andi_reg(tmp, tmp, d_repl * 0x80008000u); |
b2167459 | 1115 | cond = cond_make_0(TCG_COND_NE, tmp); |
b2167459 RH |
1116 | break; |
1117 | ||
1118 | case 4: /* SDC / NDC */ | |
59963d8f | 1119 | tcg_gen_andi_reg(cb, cb, d_repl * 0x88888888u); |
b2167459 RH |
1120 | cond = cond_make_0(TCG_COND_NE, cb); |
1121 | break; | |
1122 | ||
1123 | case 6: /* SBC / NBC */ | |
59963d8f | 1124 | tcg_gen_andi_reg(cb, cb, d_repl * 0x80808080u); |
b2167459 RH |
1125 | cond = cond_make_0(TCG_COND_NE, cb); |
1126 | break; | |
1127 | ||
1128 | case 7: /* SHC / NHC */ | |
59963d8f | 1129 | tcg_gen_andi_reg(cb, cb, d_repl * 0x80008000u); |
b2167459 RH |
1130 | cond = cond_make_0(TCG_COND_NE, cb); |
1131 | break; | |
1132 | ||
1133 | default: | |
1134 | g_assert_not_reached(); | |
1135 | } | |
b2167459 RH |
1136 | if (cf & 1) { |
1137 | cond.c = tcg_invert_cond(cond.c); | |
1138 | } | |
1139 | ||
1140 | return cond; | |
1141 | } | |
1142 | ||
72ca8753 RH |
1143 | static TCGv_reg get_carry(DisasContext *ctx, bool d, |
1144 | TCGv_reg cb, TCGv_reg cb_msb) | |
1145 | { | |
1146 | if (cond_need_ext(ctx, d)) { | |
1147 | TCGv_reg t = tcg_temp_new(); | |
1148 | tcg_gen_extract_reg(t, cb, 32, 1); | |
1149 | return t; | |
1150 | } | |
1151 | return cb_msb; | |
1152 | } | |
1153 | ||
1154 | static TCGv_reg get_psw_carry(DisasContext *ctx, bool d) | |
1155 | { | |
1156 | return get_carry(ctx, d, cpu_psw_cb, cpu_psw_cb_msb); | |
1157 | } | |
1158 | ||
b2167459 | 1159 | /* Compute signed overflow for addition. */ |
eaa3783b RH |
1160 | static TCGv_reg do_add_sv(DisasContext *ctx, TCGv_reg res, |
1161 | TCGv_reg in1, TCGv_reg in2) | |
b2167459 | 1162 | { |
e12c6309 | 1163 | TCGv_reg sv = tcg_temp_new(); |
eaa3783b | 1164 | TCGv_reg tmp = tcg_temp_new(); |
b2167459 | 1165 | |
eaa3783b RH |
1166 | tcg_gen_xor_reg(sv, res, in1); |
1167 | tcg_gen_xor_reg(tmp, in1, in2); | |
1168 | tcg_gen_andc_reg(sv, sv, tmp); | |
b2167459 RH |
1169 | |
1170 | return sv; | |
1171 | } | |
1172 | ||
1173 | /* Compute signed overflow for subtraction. */ | |
eaa3783b RH |
1174 | static TCGv_reg do_sub_sv(DisasContext *ctx, TCGv_reg res, |
1175 | TCGv_reg in1, TCGv_reg in2) | |
b2167459 | 1176 | { |
e12c6309 | 1177 | TCGv_reg sv = tcg_temp_new(); |
eaa3783b | 1178 | TCGv_reg tmp = tcg_temp_new(); |
b2167459 | 1179 | |
eaa3783b RH |
1180 | tcg_gen_xor_reg(sv, res, in1); |
1181 | tcg_gen_xor_reg(tmp, in1, in2); | |
1182 | tcg_gen_and_reg(sv, sv, tmp); | |
b2167459 RH |
1183 | |
1184 | return sv; | |
1185 | } | |
1186 | ||
31234768 RH |
1187 | static void do_add(DisasContext *ctx, unsigned rt, TCGv_reg in1, |
1188 | TCGv_reg in2, unsigned shift, bool is_l, | |
1189 | bool is_tsv, bool is_tc, bool is_c, unsigned cf) | |
b2167459 | 1190 | { |
bdcccc17 | 1191 | TCGv_reg dest, cb, cb_msb, cb_cond, sv, tmp; |
b2167459 RH |
1192 | unsigned c = cf >> 1; |
1193 | DisasCond cond; | |
bdcccc17 | 1194 | bool d = false; |
b2167459 RH |
1195 | |
1196 | dest = tcg_temp_new(); | |
f764718d RH |
1197 | cb = NULL; |
1198 | cb_msb = NULL; | |
bdcccc17 | 1199 | cb_cond = NULL; |
b2167459 RH |
1200 | |
1201 | if (shift) { | |
e12c6309 | 1202 | tmp = tcg_temp_new(); |
eaa3783b | 1203 | tcg_gen_shli_reg(tmp, in1, shift); |
b2167459 RH |
1204 | in1 = tmp; |
1205 | } | |
1206 | ||
b47a4a02 | 1207 | if (!is_l || cond_need_cb(c)) { |
29dd6f64 | 1208 | TCGv_reg zero = tcg_constant_reg(0); |
e12c6309 | 1209 | cb_msb = tcg_temp_new(); |
bdcccc17 RH |
1210 | cb = tcg_temp_new(); |
1211 | ||
eaa3783b | 1212 | tcg_gen_add2_reg(dest, cb_msb, in1, zero, in2, zero); |
b2167459 | 1213 | if (is_c) { |
bdcccc17 RH |
1214 | tcg_gen_add2_reg(dest, cb_msb, dest, cb_msb, |
1215 | get_psw_carry(ctx, d), zero); | |
b2167459 | 1216 | } |
bdcccc17 RH |
1217 | tcg_gen_xor_reg(cb, in1, in2); |
1218 | tcg_gen_xor_reg(cb, cb, dest); | |
1219 | if (cond_need_cb(c)) { | |
1220 | cb_cond = get_carry(ctx, d, cb, cb_msb); | |
b2167459 RH |
1221 | } |
1222 | } else { | |
eaa3783b | 1223 | tcg_gen_add_reg(dest, in1, in2); |
b2167459 | 1224 | if (is_c) { |
bdcccc17 | 1225 | tcg_gen_add_reg(dest, dest, get_psw_carry(ctx, d)); |
b2167459 RH |
1226 | } |
1227 | } | |
1228 | ||
1229 | /* Compute signed overflow if required. */ | |
f764718d | 1230 | sv = NULL; |
b47a4a02 | 1231 | if (is_tsv || cond_need_sv(c)) { |
b2167459 RH |
1232 | sv = do_add_sv(ctx, dest, in1, in2); |
1233 | if (is_tsv) { | |
1234 | /* ??? Need to include overflow from shift. */ | |
ad75a51e | 1235 | gen_helper_tsv(tcg_env, sv); |
b2167459 RH |
1236 | } |
1237 | } | |
1238 | ||
1239 | /* Emit any conditional trap before any writeback. */ | |
a751eb31 | 1240 | cond = do_cond(ctx, cf, d, dest, cb_cond, sv); |
b2167459 | 1241 | if (is_tc) { |
b2167459 | 1242 | tmp = tcg_temp_new(); |
eaa3783b | 1243 | tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); |
ad75a51e | 1244 | gen_helper_tcond(tcg_env, tmp); |
b2167459 RH |
1245 | } |
1246 | ||
1247 | /* Write back the result. */ | |
1248 | if (!is_l) { | |
1249 | save_or_nullify(ctx, cpu_psw_cb, cb); | |
1250 | save_or_nullify(ctx, cpu_psw_cb_msb, cb_msb); | |
1251 | } | |
1252 | save_gpr(ctx, rt, dest); | |
b2167459 RH |
1253 | |
1254 | /* Install the new nullification. */ | |
1255 | cond_free(&ctx->null_cond); | |
1256 | ctx->null_cond = cond; | |
b2167459 RH |
1257 | } |
1258 | ||
0c982a28 RH |
1259 | static bool do_add_reg(DisasContext *ctx, arg_rrr_cf_sh *a, |
1260 | bool is_l, bool is_tsv, bool is_tc, bool is_c) | |
1261 | { | |
1262 | TCGv_reg tcg_r1, tcg_r2; | |
1263 | ||
1264 | if (a->cf) { | |
1265 | nullify_over(ctx); | |
1266 | } | |
1267 | tcg_r1 = load_gpr(ctx, a->r1); | |
1268 | tcg_r2 = load_gpr(ctx, a->r2); | |
1269 | do_add(ctx, a->t, tcg_r1, tcg_r2, a->sh, is_l, is_tsv, is_tc, is_c, a->cf); | |
1270 | return nullify_end(ctx); | |
1271 | } | |
1272 | ||
0588e061 RH |
1273 | static bool do_add_imm(DisasContext *ctx, arg_rri_cf *a, |
1274 | bool is_tsv, bool is_tc) | |
1275 | { | |
1276 | TCGv_reg tcg_im, tcg_r2; | |
1277 | ||
1278 | if (a->cf) { | |
1279 | nullify_over(ctx); | |
1280 | } | |
d4e58033 | 1281 | tcg_im = tcg_constant_reg(a->i); |
0588e061 RH |
1282 | tcg_r2 = load_gpr(ctx, a->r); |
1283 | do_add(ctx, a->t, tcg_im, tcg_r2, 0, 0, is_tsv, is_tc, 0, a->cf); | |
1284 | return nullify_end(ctx); | |
1285 | } | |
1286 | ||
31234768 RH |
1287 | static void do_sub(DisasContext *ctx, unsigned rt, TCGv_reg in1, |
1288 | TCGv_reg in2, bool is_tsv, bool is_b, | |
1289 | bool is_tc, unsigned cf) | |
b2167459 | 1290 | { |
eaa3783b | 1291 | TCGv_reg dest, sv, cb, cb_msb, zero, tmp; |
b2167459 RH |
1292 | unsigned c = cf >> 1; |
1293 | DisasCond cond; | |
bdcccc17 | 1294 | bool d = false; |
b2167459 RH |
1295 | |
1296 | dest = tcg_temp_new(); | |
1297 | cb = tcg_temp_new(); | |
1298 | cb_msb = tcg_temp_new(); | |
1299 | ||
29dd6f64 | 1300 | zero = tcg_constant_reg(0); |
b2167459 RH |
1301 | if (is_b) { |
1302 | /* DEST,C = IN1 + ~IN2 + C. */ | |
eaa3783b | 1303 | tcg_gen_not_reg(cb, in2); |
bdcccc17 | 1304 | tcg_gen_add2_reg(dest, cb_msb, in1, zero, get_psw_carry(ctx, d), zero); |
eaa3783b RH |
1305 | tcg_gen_add2_reg(dest, cb_msb, dest, cb_msb, cb, zero); |
1306 | tcg_gen_xor_reg(cb, cb, in1); | |
1307 | tcg_gen_xor_reg(cb, cb, dest); | |
b2167459 | 1308 | } else { |
bdcccc17 RH |
1309 | /* |
1310 | * DEST,C = IN1 + ~IN2 + 1. We can produce the same result in fewer | |
1311 | * operations by seeding the high word with 1 and subtracting. | |
1312 | */ | |
1313 | TCGv_reg one = tcg_constant_reg(1); | |
1314 | tcg_gen_sub2_reg(dest, cb_msb, in1, one, in2, zero); | |
eaa3783b RH |
1315 | tcg_gen_eqv_reg(cb, in1, in2); |
1316 | tcg_gen_xor_reg(cb, cb, dest); | |
b2167459 | 1317 | } |
b2167459 RH |
1318 | |
1319 | /* Compute signed overflow if required. */ | |
f764718d | 1320 | sv = NULL; |
b47a4a02 | 1321 | if (is_tsv || cond_need_sv(c)) { |
b2167459 RH |
1322 | sv = do_sub_sv(ctx, dest, in1, in2); |
1323 | if (is_tsv) { | |
ad75a51e | 1324 | gen_helper_tsv(tcg_env, sv); |
b2167459 RH |
1325 | } |
1326 | } | |
1327 | ||
1328 | /* Compute the condition. We cannot use the special case for borrow. */ | |
1329 | if (!is_b) { | |
4fe9533a | 1330 | cond = do_sub_cond(ctx, cf, d, dest, in1, in2, sv); |
b2167459 | 1331 | } else { |
a751eb31 | 1332 | cond = do_cond(ctx, cf, d, dest, get_carry(ctx, d, cb, cb_msb), sv); |
b2167459 RH |
1333 | } |
1334 | ||
1335 | /* Emit any conditional trap before any writeback. */ | |
1336 | if (is_tc) { | |
b2167459 | 1337 | tmp = tcg_temp_new(); |
eaa3783b | 1338 | tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); |
ad75a51e | 1339 | gen_helper_tcond(tcg_env, tmp); |
b2167459 RH |
1340 | } |
1341 | ||
1342 | /* Write back the result. */ | |
1343 | save_or_nullify(ctx, cpu_psw_cb, cb); | |
1344 | save_or_nullify(ctx, cpu_psw_cb_msb, cb_msb); | |
1345 | save_gpr(ctx, rt, dest); | |
b2167459 RH |
1346 | |
1347 | /* Install the new nullification. */ | |
1348 | cond_free(&ctx->null_cond); | |
1349 | ctx->null_cond = cond; | |
b2167459 RH |
1350 | } |
1351 | ||
0c982a28 RH |
1352 | static bool do_sub_reg(DisasContext *ctx, arg_rrr_cf *a, |
1353 | bool is_tsv, bool is_b, bool is_tc) | |
1354 | { | |
1355 | TCGv_reg tcg_r1, tcg_r2; | |
1356 | ||
1357 | if (a->cf) { | |
1358 | nullify_over(ctx); | |
1359 | } | |
1360 | tcg_r1 = load_gpr(ctx, a->r1); | |
1361 | tcg_r2 = load_gpr(ctx, a->r2); | |
1362 | do_sub(ctx, a->t, tcg_r1, tcg_r2, is_tsv, is_b, is_tc, a->cf); | |
1363 | return nullify_end(ctx); | |
1364 | } | |
1365 | ||
0588e061 RH |
1366 | static bool do_sub_imm(DisasContext *ctx, arg_rri_cf *a, bool is_tsv) |
1367 | { | |
1368 | TCGv_reg tcg_im, tcg_r2; | |
1369 | ||
1370 | if (a->cf) { | |
1371 | nullify_over(ctx); | |
1372 | } | |
d4e58033 | 1373 | tcg_im = tcg_constant_reg(a->i); |
0588e061 RH |
1374 | tcg_r2 = load_gpr(ctx, a->r); |
1375 | do_sub(ctx, a->t, tcg_im, tcg_r2, is_tsv, 0, 0, a->cf); | |
1376 | return nullify_end(ctx); | |
1377 | } | |
1378 | ||
31234768 RH |
1379 | static void do_cmpclr(DisasContext *ctx, unsigned rt, TCGv_reg in1, |
1380 | TCGv_reg in2, unsigned cf) | |
b2167459 | 1381 | { |
eaa3783b | 1382 | TCGv_reg dest, sv; |
b2167459 | 1383 | DisasCond cond; |
4fe9533a | 1384 | bool d = false; |
b2167459 RH |
1385 | |
1386 | dest = tcg_temp_new(); | |
eaa3783b | 1387 | tcg_gen_sub_reg(dest, in1, in2); |
b2167459 RH |
1388 | |
1389 | /* Compute signed overflow if required. */ | |
f764718d | 1390 | sv = NULL; |
b47a4a02 | 1391 | if (cond_need_sv(cf >> 1)) { |
b2167459 RH |
1392 | sv = do_sub_sv(ctx, dest, in1, in2); |
1393 | } | |
1394 | ||
1395 | /* Form the condition for the compare. */ | |
4fe9533a | 1396 | cond = do_sub_cond(ctx, cf, d, dest, in1, in2, sv); |
b2167459 RH |
1397 | |
1398 | /* Clear. */ | |
eaa3783b | 1399 | tcg_gen_movi_reg(dest, 0); |
b2167459 | 1400 | save_gpr(ctx, rt, dest); |
b2167459 RH |
1401 | |
1402 | /* Install the new nullification. */ | |
1403 | cond_free(&ctx->null_cond); | |
1404 | ctx->null_cond = cond; | |
b2167459 RH |
1405 | } |
1406 | ||
31234768 | 1407 | static void do_log(DisasContext *ctx, unsigned rt, TCGv_reg in1, |
fa8e3bed | 1408 | TCGv_reg in2, unsigned cf, bool d, |
31234768 | 1409 | void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) |
b2167459 | 1410 | { |
eaa3783b | 1411 | TCGv_reg dest = dest_gpr(ctx, rt); |
b2167459 RH |
1412 | |
1413 | /* Perform the operation, and writeback. */ | |
1414 | fn(dest, in1, in2); | |
1415 | save_gpr(ctx, rt, dest); | |
1416 | ||
1417 | /* Install the new nullification. */ | |
1418 | cond_free(&ctx->null_cond); | |
1419 | if (cf) { | |
b5af8423 | 1420 | ctx->null_cond = do_log_cond(ctx, cf, d, dest); |
b2167459 | 1421 | } |
b2167459 RH |
1422 | } |
1423 | ||
fa8e3bed | 1424 | static bool do_log_reg(DisasContext *ctx, arg_rrr_cf_d *a, |
0c982a28 RH |
1425 | void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) |
1426 | { | |
1427 | TCGv_reg tcg_r1, tcg_r2; | |
1428 | ||
1429 | if (a->cf) { | |
1430 | nullify_over(ctx); | |
1431 | } | |
1432 | tcg_r1 = load_gpr(ctx, a->r1); | |
1433 | tcg_r2 = load_gpr(ctx, a->r2); | |
fa8e3bed | 1434 | do_log(ctx, a->t, tcg_r1, tcg_r2, a->cf, a->d, fn); |
0c982a28 RH |
1435 | return nullify_end(ctx); |
1436 | } | |
1437 | ||
31234768 | 1438 | static void do_unit(DisasContext *ctx, unsigned rt, TCGv_reg in1, |
af240753 | 1439 | TCGv_reg in2, unsigned cf, bool d, bool is_tc, |
31234768 | 1440 | void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) |
b2167459 | 1441 | { |
eaa3783b | 1442 | TCGv_reg dest; |
b2167459 RH |
1443 | DisasCond cond; |
1444 | ||
1445 | if (cf == 0) { | |
1446 | dest = dest_gpr(ctx, rt); | |
1447 | fn(dest, in1, in2); | |
1448 | save_gpr(ctx, rt, dest); | |
1449 | cond_free(&ctx->null_cond); | |
1450 | } else { | |
1451 | dest = tcg_temp_new(); | |
1452 | fn(dest, in1, in2); | |
1453 | ||
59963d8f | 1454 | cond = do_unit_cond(cf, d, dest, in1, in2); |
b2167459 RH |
1455 | |
1456 | if (is_tc) { | |
eaa3783b | 1457 | TCGv_reg tmp = tcg_temp_new(); |
eaa3783b | 1458 | tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); |
ad75a51e | 1459 | gen_helper_tcond(tcg_env, tmp); |
b2167459 RH |
1460 | } |
1461 | save_gpr(ctx, rt, dest); | |
1462 | ||
1463 | cond_free(&ctx->null_cond); | |
1464 | ctx->null_cond = cond; | |
1465 | } | |
b2167459 RH |
1466 | } |
1467 | ||
86f8d05f | 1468 | #ifndef CONFIG_USER_ONLY |
8d6ae7fb RH |
1469 | /* The "normal" usage is SP >= 0, wherein SP == 0 selects the space |
1470 | from the top 2 bits of the base register. There are a few system | |
1471 | instructions that have a 3-bit space specifier, for which SR0 is | |
1472 | not special. To handle this, pass ~SP. */ | |
86f8d05f RH |
1473 | static TCGv_i64 space_select(DisasContext *ctx, int sp, TCGv_reg base) |
1474 | { | |
1475 | TCGv_ptr ptr; | |
1476 | TCGv_reg tmp; | |
1477 | TCGv_i64 spc; | |
1478 | ||
1479 | if (sp != 0) { | |
8d6ae7fb RH |
1480 | if (sp < 0) { |
1481 | sp = ~sp; | |
1482 | } | |
a6779861 | 1483 | spc = tcg_temp_new_tl(); |
8d6ae7fb RH |
1484 | load_spr(ctx, spc, sp); |
1485 | return spc; | |
86f8d05f | 1486 | } |
494737b7 RH |
1487 | if (ctx->tb_flags & TB_FLAG_SR_SAME) { |
1488 | return cpu_srH; | |
1489 | } | |
86f8d05f RH |
1490 | |
1491 | ptr = tcg_temp_new_ptr(); | |
1492 | tmp = tcg_temp_new(); | |
a6779861 | 1493 | spc = tcg_temp_new_tl(); |
86f8d05f | 1494 | |
698240d1 RH |
1495 | /* Extract top 2 bits of the address, shift left 3 for uint64_t index. */ |
1496 | tcg_gen_shri_reg(tmp, base, (ctx->tb_flags & PSW_W ? 64 : 32) - 5); | |
86f8d05f RH |
1497 | tcg_gen_andi_reg(tmp, tmp, 030); |
1498 | tcg_gen_trunc_reg_ptr(ptr, tmp); | |
86f8d05f | 1499 | |
ad75a51e | 1500 | tcg_gen_add_ptr(ptr, ptr, tcg_env); |
86f8d05f | 1501 | tcg_gen_ld_i64(spc, ptr, offsetof(CPUHPPAState, sr[4])); |
86f8d05f RH |
1502 | |
1503 | return spc; | |
1504 | } | |
1505 | #endif | |
1506 | ||
1507 | static void form_gva(DisasContext *ctx, TCGv_tl *pgva, TCGv_reg *pofs, | |
1508 | unsigned rb, unsigned rx, int scale, target_sreg disp, | |
1509 | unsigned sp, int modify, bool is_phys) | |
1510 | { | |
1511 | TCGv_reg base = load_gpr(ctx, rb); | |
1512 | TCGv_reg ofs; | |
698240d1 | 1513 | TCGv_tl addr; |
86f8d05f RH |
1514 | |
1515 | /* Note that RX is mutually exclusive with DISP. */ | |
1516 | if (rx) { | |
e12c6309 | 1517 | ofs = tcg_temp_new(); |
86f8d05f RH |
1518 | tcg_gen_shli_reg(ofs, cpu_gr[rx], scale); |
1519 | tcg_gen_add_reg(ofs, ofs, base); | |
1520 | } else if (disp || modify) { | |
e12c6309 | 1521 | ofs = tcg_temp_new(); |
86f8d05f RH |
1522 | tcg_gen_addi_reg(ofs, base, disp); |
1523 | } else { | |
1524 | ofs = base; | |
1525 | } | |
1526 | ||
1527 | *pofs = ofs; | |
698240d1 | 1528 | *pgva = addr = tcg_temp_new_tl(); |
86f8d05f | 1529 | tcg_gen_extu_reg_tl(addr, modify <= 0 ? ofs : base); |
698240d1 RH |
1530 | tcg_gen_andi_tl(addr, addr, gva_offset_mask(ctx)); |
1531 | #ifndef CONFIG_USER_ONLY | |
86f8d05f RH |
1532 | if (!is_phys) { |
1533 | tcg_gen_or_tl(addr, addr, space_select(ctx, sp, base)); | |
1534 | } | |
86f8d05f RH |
1535 | #endif |
1536 | } | |
1537 | ||
96d6407f RH |
1538 | /* Emit a memory load. The modify parameter should be |
1539 | * < 0 for pre-modify, | |
1540 | * > 0 for post-modify, | |
1541 | * = 0 for no base register update. | |
1542 | */ | |
1543 | static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb, | |
eaa3783b | 1544 | unsigned rx, int scale, target_sreg disp, |
14776ab5 | 1545 | unsigned sp, int modify, MemOp mop) |
96d6407f | 1546 | { |
86f8d05f RH |
1547 | TCGv_reg ofs; |
1548 | TCGv_tl addr; | |
96d6407f RH |
1549 | |
1550 | /* Caller uses nullify_over/nullify_end. */ | |
1551 | assert(ctx->null_cond.c == TCG_COND_NEVER); | |
1552 | ||
86f8d05f RH |
1553 | form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, |
1554 | ctx->mmu_idx == MMU_PHYS_IDX); | |
c1f55d97 | 1555 | tcg_gen_qemu_ld_i32(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); |
86f8d05f RH |
1556 | if (modify) { |
1557 | save_gpr(ctx, rb, ofs); | |
96d6407f | 1558 | } |
96d6407f RH |
1559 | } |
1560 | ||
1561 | static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb, | |
eaa3783b | 1562 | unsigned rx, int scale, target_sreg disp, |
14776ab5 | 1563 | unsigned sp, int modify, MemOp mop) |
96d6407f | 1564 | { |
86f8d05f RH |
1565 | TCGv_reg ofs; |
1566 | TCGv_tl addr; | |
96d6407f RH |
1567 | |
1568 | /* Caller uses nullify_over/nullify_end. */ | |
1569 | assert(ctx->null_cond.c == TCG_COND_NEVER); | |
1570 | ||
86f8d05f RH |
1571 | form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, |
1572 | ctx->mmu_idx == MMU_PHYS_IDX); | |
217d1a5e | 1573 | tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); |
86f8d05f RH |
1574 | if (modify) { |
1575 | save_gpr(ctx, rb, ofs); | |
96d6407f | 1576 | } |
96d6407f RH |
1577 | } |
1578 | ||
1579 | static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb, | |
eaa3783b | 1580 | unsigned rx, int scale, target_sreg disp, |
14776ab5 | 1581 | unsigned sp, int modify, MemOp mop) |
96d6407f | 1582 | { |
86f8d05f RH |
1583 | TCGv_reg ofs; |
1584 | TCGv_tl addr; | |
96d6407f RH |
1585 | |
1586 | /* Caller uses nullify_over/nullify_end. */ | |
1587 | assert(ctx->null_cond.c == TCG_COND_NEVER); | |
1588 | ||
86f8d05f RH |
1589 | form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, |
1590 | ctx->mmu_idx == MMU_PHYS_IDX); | |
217d1a5e | 1591 | tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); |
86f8d05f RH |
1592 | if (modify) { |
1593 | save_gpr(ctx, rb, ofs); | |
96d6407f | 1594 | } |
96d6407f RH |
1595 | } |
1596 | ||
1597 | static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb, | |
eaa3783b | 1598 | unsigned rx, int scale, target_sreg disp, |
14776ab5 | 1599 | unsigned sp, int modify, MemOp mop) |
96d6407f | 1600 | { |
86f8d05f RH |
1601 | TCGv_reg ofs; |
1602 | TCGv_tl addr; | |
96d6407f RH |
1603 | |
1604 | /* Caller uses nullify_over/nullify_end. */ | |
1605 | assert(ctx->null_cond.c == TCG_COND_NEVER); | |
1606 | ||
86f8d05f RH |
1607 | form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, |
1608 | ctx->mmu_idx == MMU_PHYS_IDX); | |
217d1a5e | 1609 | tcg_gen_qemu_st_i64(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); |
86f8d05f RH |
1610 | if (modify) { |
1611 | save_gpr(ctx, rb, ofs); | |
96d6407f | 1612 | } |
96d6407f RH |
1613 | } |
1614 | ||
eaa3783b RH |
1615 | #if TARGET_REGISTER_BITS == 64 |
1616 | #define do_load_reg do_load_64 | |
1617 | #define do_store_reg do_store_64 | |
96d6407f | 1618 | #else |
eaa3783b RH |
1619 | #define do_load_reg do_load_32 |
1620 | #define do_store_reg do_store_32 | |
96d6407f RH |
1621 | #endif |
1622 | ||
1cd012a5 | 1623 | static bool do_load(DisasContext *ctx, unsigned rt, unsigned rb, |
31234768 | 1624 | unsigned rx, int scale, target_sreg disp, |
14776ab5 | 1625 | unsigned sp, int modify, MemOp mop) |
96d6407f | 1626 | { |
eaa3783b | 1627 | TCGv_reg dest; |
96d6407f RH |
1628 | |
1629 | nullify_over(ctx); | |
1630 | ||
1631 | if (modify == 0) { | |
1632 | /* No base register update. */ | |
1633 | dest = dest_gpr(ctx, rt); | |
1634 | } else { | |
1635 | /* Make sure if RT == RB, we see the result of the load. */ | |
e12c6309 | 1636 | dest = tcg_temp_new(); |
96d6407f | 1637 | } |
86f8d05f | 1638 | do_load_reg(ctx, dest, rb, rx, scale, disp, sp, modify, mop); |
96d6407f RH |
1639 | save_gpr(ctx, rt, dest); |
1640 | ||
1cd012a5 | 1641 | return nullify_end(ctx); |
96d6407f RH |
1642 | } |
1643 | ||
740038d7 | 1644 | static bool do_floadw(DisasContext *ctx, unsigned rt, unsigned rb, |
31234768 RH |
1645 | unsigned rx, int scale, target_sreg disp, |
1646 | unsigned sp, int modify) | |
96d6407f RH |
1647 | { |
1648 | TCGv_i32 tmp; | |
1649 | ||
1650 | nullify_over(ctx); | |
1651 | ||
1652 | tmp = tcg_temp_new_i32(); | |
86f8d05f | 1653 | do_load_32(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEUL); |
96d6407f | 1654 | save_frw_i32(rt, tmp); |
96d6407f RH |
1655 | |
1656 | if (rt == 0) { | |
ad75a51e | 1657 | gen_helper_loaded_fr0(tcg_env); |
96d6407f RH |
1658 | } |
1659 | ||
740038d7 RH |
1660 | return nullify_end(ctx); |
1661 | } | |
1662 | ||
1663 | static bool trans_fldw(DisasContext *ctx, arg_ldst *a) | |
1664 | { | |
1665 | return do_floadw(ctx, a->t, a->b, a->x, a->scale ? 2 : 0, | |
1666 | a->disp, a->sp, a->m); | |
96d6407f RH |
1667 | } |
1668 | ||
740038d7 | 1669 | static bool do_floadd(DisasContext *ctx, unsigned rt, unsigned rb, |
31234768 RH |
1670 | unsigned rx, int scale, target_sreg disp, |
1671 | unsigned sp, int modify) | |
96d6407f RH |
1672 | { |
1673 | TCGv_i64 tmp; | |
1674 | ||
1675 | nullify_over(ctx); | |
1676 | ||
1677 | tmp = tcg_temp_new_i64(); | |
fc313c64 | 1678 | do_load_64(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEUQ); |
96d6407f | 1679 | save_frd(rt, tmp); |
96d6407f RH |
1680 | |
1681 | if (rt == 0) { | |
ad75a51e | 1682 | gen_helper_loaded_fr0(tcg_env); |
96d6407f RH |
1683 | } |
1684 | ||
740038d7 RH |
1685 | return nullify_end(ctx); |
1686 | } | |
1687 | ||
1688 | static bool trans_fldd(DisasContext *ctx, arg_ldst *a) | |
1689 | { | |
1690 | return do_floadd(ctx, a->t, a->b, a->x, a->scale ? 3 : 0, | |
1691 | a->disp, a->sp, a->m); | |
96d6407f RH |
1692 | } |
1693 | ||
1cd012a5 | 1694 | static bool do_store(DisasContext *ctx, unsigned rt, unsigned rb, |
31234768 | 1695 | target_sreg disp, unsigned sp, |
14776ab5 | 1696 | int modify, MemOp mop) |
96d6407f RH |
1697 | { |
1698 | nullify_over(ctx); | |
86f8d05f | 1699 | do_store_reg(ctx, load_gpr(ctx, rt), rb, 0, 0, disp, sp, modify, mop); |
1cd012a5 | 1700 | return nullify_end(ctx); |
96d6407f RH |
1701 | } |
1702 | ||
740038d7 | 1703 | static bool do_fstorew(DisasContext *ctx, unsigned rt, unsigned rb, |
31234768 RH |
1704 | unsigned rx, int scale, target_sreg disp, |
1705 | unsigned sp, int modify) | |
96d6407f RH |
1706 | { |
1707 | TCGv_i32 tmp; | |
1708 | ||
1709 | nullify_over(ctx); | |
1710 | ||
1711 | tmp = load_frw_i32(rt); | |
86f8d05f | 1712 | do_store_32(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEUL); |
96d6407f | 1713 | |
740038d7 RH |
1714 | return nullify_end(ctx); |
1715 | } | |
1716 | ||
1717 | static bool trans_fstw(DisasContext *ctx, arg_ldst *a) | |
1718 | { | |
1719 | return do_fstorew(ctx, a->t, a->b, a->x, a->scale ? 2 : 0, | |
1720 | a->disp, a->sp, a->m); | |
96d6407f RH |
1721 | } |
1722 | ||
740038d7 | 1723 | static bool do_fstored(DisasContext *ctx, unsigned rt, unsigned rb, |
31234768 RH |
1724 | unsigned rx, int scale, target_sreg disp, |
1725 | unsigned sp, int modify) | |
96d6407f RH |
1726 | { |
1727 | TCGv_i64 tmp; | |
1728 | ||
1729 | nullify_over(ctx); | |
1730 | ||
1731 | tmp = load_frd(rt); | |
fc313c64 | 1732 | do_store_64(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEUQ); |
96d6407f | 1733 | |
740038d7 RH |
1734 | return nullify_end(ctx); |
1735 | } | |
1736 | ||
1737 | static bool trans_fstd(DisasContext *ctx, arg_ldst *a) | |
1738 | { | |
1739 | return do_fstored(ctx, a->t, a->b, a->x, a->scale ? 3 : 0, | |
1740 | a->disp, a->sp, a->m); | |
96d6407f RH |
1741 | } |
1742 | ||
1ca74648 | 1743 | static bool do_fop_wew(DisasContext *ctx, unsigned rt, unsigned ra, |
31234768 | 1744 | void (*func)(TCGv_i32, TCGv_env, TCGv_i32)) |
ebe9383c RH |
1745 | { |
1746 | TCGv_i32 tmp; | |
1747 | ||
1748 | nullify_over(ctx); | |
1749 | tmp = load_frw0_i32(ra); | |
1750 | ||
ad75a51e | 1751 | func(tmp, tcg_env, tmp); |
ebe9383c RH |
1752 | |
1753 | save_frw_i32(rt, tmp); | |
1ca74648 | 1754 | return nullify_end(ctx); |
ebe9383c RH |
1755 | } |
1756 | ||
1ca74648 | 1757 | static bool do_fop_wed(DisasContext *ctx, unsigned rt, unsigned ra, |
31234768 | 1758 | void (*func)(TCGv_i32, TCGv_env, TCGv_i64)) |
ebe9383c RH |
1759 | { |
1760 | TCGv_i32 dst; | |
1761 | TCGv_i64 src; | |
1762 | ||
1763 | nullify_over(ctx); | |
1764 | src = load_frd(ra); | |
1765 | dst = tcg_temp_new_i32(); | |
1766 | ||
ad75a51e | 1767 | func(dst, tcg_env, src); |
ebe9383c | 1768 | |
ebe9383c | 1769 | save_frw_i32(rt, dst); |
1ca74648 | 1770 | return nullify_end(ctx); |
ebe9383c RH |
1771 | } |
1772 | ||
1ca74648 | 1773 | static bool do_fop_ded(DisasContext *ctx, unsigned rt, unsigned ra, |
31234768 | 1774 | void (*func)(TCGv_i64, TCGv_env, TCGv_i64)) |
ebe9383c RH |
1775 | { |
1776 | TCGv_i64 tmp; | |
1777 | ||
1778 | nullify_over(ctx); | |
1779 | tmp = load_frd0(ra); | |
1780 | ||
ad75a51e | 1781 | func(tmp, tcg_env, tmp); |
ebe9383c RH |
1782 | |
1783 | save_frd(rt, tmp); | |
1ca74648 | 1784 | return nullify_end(ctx); |
ebe9383c RH |
1785 | } |
1786 | ||
1ca74648 | 1787 | static bool do_fop_dew(DisasContext *ctx, unsigned rt, unsigned ra, |
31234768 | 1788 | void (*func)(TCGv_i64, TCGv_env, TCGv_i32)) |
ebe9383c RH |
1789 | { |
1790 | TCGv_i32 src; | |
1791 | TCGv_i64 dst; | |
1792 | ||
1793 | nullify_over(ctx); | |
1794 | src = load_frw0_i32(ra); | |
1795 | dst = tcg_temp_new_i64(); | |
1796 | ||
ad75a51e | 1797 | func(dst, tcg_env, src); |
ebe9383c | 1798 | |
ebe9383c | 1799 | save_frd(rt, dst); |
1ca74648 | 1800 | return nullify_end(ctx); |
ebe9383c RH |
1801 | } |
1802 | ||
1ca74648 | 1803 | static bool do_fop_weww(DisasContext *ctx, unsigned rt, |
31234768 RH |
1804 | unsigned ra, unsigned rb, |
1805 | void (*func)(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32)) | |
ebe9383c RH |
1806 | { |
1807 | TCGv_i32 a, b; | |
1808 | ||
1809 | nullify_over(ctx); | |
1810 | a = load_frw0_i32(ra); | |
1811 | b = load_frw0_i32(rb); | |
1812 | ||
ad75a51e | 1813 | func(a, tcg_env, a, b); |
ebe9383c | 1814 | |
ebe9383c | 1815 | save_frw_i32(rt, a); |
1ca74648 | 1816 | return nullify_end(ctx); |
ebe9383c RH |
1817 | } |
1818 | ||
1ca74648 | 1819 | static bool do_fop_dedd(DisasContext *ctx, unsigned rt, |
31234768 RH |
1820 | unsigned ra, unsigned rb, |
1821 | void (*func)(TCGv_i64, TCGv_env, TCGv_i64, TCGv_i64)) | |
ebe9383c RH |
1822 | { |
1823 | TCGv_i64 a, b; | |
1824 | ||
1825 | nullify_over(ctx); | |
1826 | a = load_frd0(ra); | |
1827 | b = load_frd0(rb); | |
1828 | ||
ad75a51e | 1829 | func(a, tcg_env, a, b); |
ebe9383c | 1830 | |
ebe9383c | 1831 | save_frd(rt, a); |
1ca74648 | 1832 | return nullify_end(ctx); |
ebe9383c RH |
1833 | } |
1834 | ||
98cd9ca7 RH |
1835 | /* Emit an unconditional branch to a direct target, which may or may not |
1836 | have already had nullification handled. */ | |
01afb7be | 1837 | static bool do_dbranch(DisasContext *ctx, target_ureg dest, |
31234768 | 1838 | unsigned link, bool is_n) |
98cd9ca7 RH |
1839 | { |
1840 | if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) { | |
1841 | if (link != 0) { | |
741322f4 | 1842 | copy_iaoq_entry(ctx, cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); |
98cd9ca7 RH |
1843 | } |
1844 | ctx->iaoq_n = dest; | |
1845 | if (is_n) { | |
1846 | ctx->null_cond.c = TCG_COND_ALWAYS; | |
1847 | } | |
98cd9ca7 RH |
1848 | } else { |
1849 | nullify_over(ctx); | |
1850 | ||
1851 | if (link != 0) { | |
741322f4 | 1852 | copy_iaoq_entry(ctx, cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); |
98cd9ca7 RH |
1853 | } |
1854 | ||
1855 | if (is_n && use_nullify_skip(ctx)) { | |
1856 | nullify_set(ctx, 0); | |
1857 | gen_goto_tb(ctx, 0, dest, dest + 4); | |
1858 | } else { | |
1859 | nullify_set(ctx, is_n); | |
1860 | gen_goto_tb(ctx, 0, ctx->iaoq_b, dest); | |
1861 | } | |
1862 | ||
31234768 | 1863 | nullify_end(ctx); |
98cd9ca7 RH |
1864 | |
1865 | nullify_set(ctx, 0); | |
1866 | gen_goto_tb(ctx, 1, ctx->iaoq_b, ctx->iaoq_n); | |
31234768 | 1867 | ctx->base.is_jmp = DISAS_NORETURN; |
98cd9ca7 | 1868 | } |
01afb7be | 1869 | return true; |
98cd9ca7 RH |
1870 | } |
1871 | ||
1872 | /* Emit a conditional branch to a direct target. If the branch itself | |
1873 | is nullified, we should have already used nullify_over. */ | |
01afb7be | 1874 | static bool do_cbranch(DisasContext *ctx, target_sreg disp, bool is_n, |
31234768 | 1875 | DisasCond *cond) |
98cd9ca7 | 1876 | { |
eaa3783b | 1877 | target_ureg dest = iaoq_dest(ctx, disp); |
98cd9ca7 RH |
1878 | TCGLabel *taken = NULL; |
1879 | TCGCond c = cond->c; | |
98cd9ca7 RH |
1880 | bool n; |
1881 | ||
1882 | assert(ctx->null_cond.c == TCG_COND_NEVER); | |
1883 | ||
1884 | /* Handle TRUE and NEVER as direct branches. */ | |
1885 | if (c == TCG_COND_ALWAYS) { | |
01afb7be | 1886 | return do_dbranch(ctx, dest, 0, is_n && disp >= 0); |
98cd9ca7 RH |
1887 | } |
1888 | if (c == TCG_COND_NEVER) { | |
01afb7be | 1889 | return do_dbranch(ctx, ctx->iaoq_n, 0, is_n && disp < 0); |
98cd9ca7 RH |
1890 | } |
1891 | ||
1892 | taken = gen_new_label(); | |
eaa3783b | 1893 | tcg_gen_brcond_reg(c, cond->a0, cond->a1, taken); |
98cd9ca7 RH |
1894 | cond_free(cond); |
1895 | ||
1896 | /* Not taken: Condition not satisfied; nullify on backward branches. */ | |
1897 | n = is_n && disp < 0; | |
1898 | if (n && use_nullify_skip(ctx)) { | |
1899 | nullify_set(ctx, 0); | |
a881c8e7 | 1900 | gen_goto_tb(ctx, 0, ctx->iaoq_n, ctx->iaoq_n + 4); |
98cd9ca7 RH |
1901 | } else { |
1902 | if (!n && ctx->null_lab) { | |
1903 | gen_set_label(ctx->null_lab); | |
1904 | ctx->null_lab = NULL; | |
1905 | } | |
1906 | nullify_set(ctx, n); | |
c301f34e RH |
1907 | if (ctx->iaoq_n == -1) { |
1908 | /* The temporary iaoq_n_var died at the branch above. | |
1909 | Regenerate it here instead of saving it. */ | |
1910 | tcg_gen_addi_reg(ctx->iaoq_n_var, cpu_iaoq_b, 4); | |
1911 | } | |
a881c8e7 | 1912 | gen_goto_tb(ctx, 0, ctx->iaoq_b, ctx->iaoq_n); |
98cd9ca7 RH |
1913 | } |
1914 | ||
1915 | gen_set_label(taken); | |
1916 | ||
1917 | /* Taken: Condition satisfied; nullify on forward branches. */ | |
1918 | n = is_n && disp >= 0; | |
1919 | if (n && use_nullify_skip(ctx)) { | |
1920 | nullify_set(ctx, 0); | |
a881c8e7 | 1921 | gen_goto_tb(ctx, 1, dest, dest + 4); |
98cd9ca7 RH |
1922 | } else { |
1923 | nullify_set(ctx, n); | |
a881c8e7 | 1924 | gen_goto_tb(ctx, 1, ctx->iaoq_b, dest); |
98cd9ca7 RH |
1925 | } |
1926 | ||
1927 | /* Not taken: the branch itself was nullified. */ | |
1928 | if (ctx->null_lab) { | |
1929 | gen_set_label(ctx->null_lab); | |
1930 | ctx->null_lab = NULL; | |
31234768 | 1931 | ctx->base.is_jmp = DISAS_IAQ_N_STALE; |
98cd9ca7 | 1932 | } else { |
31234768 | 1933 | ctx->base.is_jmp = DISAS_NORETURN; |
98cd9ca7 | 1934 | } |
01afb7be | 1935 | return true; |
98cd9ca7 RH |
1936 | } |
1937 | ||
1938 | /* Emit an unconditional branch to an indirect target. This handles | |
1939 | nullification of the branch itself. */ | |
01afb7be | 1940 | static bool do_ibranch(DisasContext *ctx, TCGv_reg dest, |
31234768 | 1941 | unsigned link, bool is_n) |
98cd9ca7 | 1942 | { |
eaa3783b | 1943 | TCGv_reg a0, a1, next, tmp; |
98cd9ca7 RH |
1944 | TCGCond c; |
1945 | ||
1946 | assert(ctx->null_lab == NULL); | |
1947 | ||
1948 | if (ctx->null_cond.c == TCG_COND_NEVER) { | |
1949 | if (link != 0) { | |
741322f4 | 1950 | copy_iaoq_entry(ctx, cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); |
98cd9ca7 | 1951 | } |
e12c6309 | 1952 | next = tcg_temp_new(); |
eaa3783b | 1953 | tcg_gen_mov_reg(next, dest); |
98cd9ca7 | 1954 | if (is_n) { |
c301f34e | 1955 | if (use_nullify_skip(ctx)) { |
a0180973 RH |
1956 | copy_iaoq_entry(ctx, cpu_iaoq_f, -1, next); |
1957 | tcg_gen_addi_reg(next, next, 4); | |
1958 | copy_iaoq_entry(ctx, cpu_iaoq_b, -1, next); | |
c301f34e | 1959 | nullify_set(ctx, 0); |
31234768 | 1960 | ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; |
01afb7be | 1961 | return true; |
c301f34e | 1962 | } |
98cd9ca7 RH |
1963 | ctx->null_cond.c = TCG_COND_ALWAYS; |
1964 | } | |
c301f34e RH |
1965 | ctx->iaoq_n = -1; |
1966 | ctx->iaoq_n_var = next; | |
98cd9ca7 RH |
1967 | } else if (is_n && use_nullify_skip(ctx)) { |
1968 | /* The (conditional) branch, B, nullifies the next insn, N, | |
1969 | and we're allowed to skip execution N (no single-step or | |
4137cb83 | 1970 | tracepoint in effect). Since the goto_ptr that we must use |
98cd9ca7 RH |
1971 | for the indirect branch consumes no special resources, we |
1972 | can (conditionally) skip B and continue execution. */ | |
1973 | /* The use_nullify_skip test implies we have a known control path. */ | |
1974 | tcg_debug_assert(ctx->iaoq_b != -1); | |
1975 | tcg_debug_assert(ctx->iaoq_n != -1); | |
1976 | ||
1977 | /* We do have to handle the non-local temporary, DEST, before | |
1978 | branching. Since IOAQ_F is not really live at this point, we | |
1979 | can simply store DEST optimistically. Similarly with IAOQ_B. */ | |
a0180973 RH |
1980 | copy_iaoq_entry(ctx, cpu_iaoq_f, -1, dest); |
1981 | next = tcg_temp_new(); | |
1982 | tcg_gen_addi_reg(next, dest, 4); | |
1983 | copy_iaoq_entry(ctx, cpu_iaoq_b, -1, next); | |
98cd9ca7 RH |
1984 | |
1985 | nullify_over(ctx); | |
1986 | if (link != 0) { | |
9a91dd84 | 1987 | copy_iaoq_entry(ctx, cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); |
98cd9ca7 | 1988 | } |
7f11636d | 1989 | tcg_gen_lookup_and_goto_ptr(); |
01afb7be | 1990 | return nullify_end(ctx); |
98cd9ca7 | 1991 | } else { |
98cd9ca7 RH |
1992 | c = ctx->null_cond.c; |
1993 | a0 = ctx->null_cond.a0; | |
1994 | a1 = ctx->null_cond.a1; | |
1995 | ||
1996 | tmp = tcg_temp_new(); | |
e12c6309 | 1997 | next = tcg_temp_new(); |
98cd9ca7 | 1998 | |
741322f4 | 1999 | copy_iaoq_entry(ctx, tmp, ctx->iaoq_n, ctx->iaoq_n_var); |
eaa3783b | 2000 | tcg_gen_movcond_reg(c, next, a0, a1, tmp, dest); |
98cd9ca7 RH |
2001 | ctx->iaoq_n = -1; |
2002 | ctx->iaoq_n_var = next; | |
2003 | ||
2004 | if (link != 0) { | |
eaa3783b | 2005 | tcg_gen_movcond_reg(c, cpu_gr[link], a0, a1, cpu_gr[link], tmp); |
98cd9ca7 RH |
2006 | } |
2007 | ||
2008 | if (is_n) { | |
2009 | /* The branch nullifies the next insn, which means the state of N | |
2010 | after the branch is the inverse of the state of N that applied | |
2011 | to the branch. */ | |
eaa3783b | 2012 | tcg_gen_setcond_reg(tcg_invert_cond(c), cpu_psw_n, a0, a1); |
98cd9ca7 RH |
2013 | cond_free(&ctx->null_cond); |
2014 | ctx->null_cond = cond_make_n(); | |
2015 | ctx->psw_n_nonzero = true; | |
2016 | } else { | |
2017 | cond_free(&ctx->null_cond); | |
2018 | } | |
2019 | } | |
01afb7be | 2020 | return true; |
98cd9ca7 RH |
2021 | } |
2022 | ||
660eefe1 RH |
2023 | /* Implement |
2024 | * if (IAOQ_Front{30..31} < GR[b]{30..31}) | |
2025 | * IAOQ_Next{30..31} ← GR[b]{30..31}; | |
2026 | * else | |
2027 | * IAOQ_Next{30..31} ← IAOQ_Front{30..31}; | |
2028 | * which keeps the privilege level from being increased. | |
2029 | */ | |
2030 | static TCGv_reg do_ibranch_priv(DisasContext *ctx, TCGv_reg offset) | |
2031 | { | |
660eefe1 RH |
2032 | TCGv_reg dest; |
2033 | switch (ctx->privilege) { | |
2034 | case 0: | |
2035 | /* Privilege 0 is maximum and is allowed to decrease. */ | |
2036 | return offset; | |
2037 | case 3: | |
993119fe | 2038 | /* Privilege 3 is minimum and is never allowed to increase. */ |
e12c6309 | 2039 | dest = tcg_temp_new(); |
660eefe1 RH |
2040 | tcg_gen_ori_reg(dest, offset, 3); |
2041 | break; | |
2042 | default: | |
e12c6309 | 2043 | dest = tcg_temp_new(); |
660eefe1 RH |
2044 | tcg_gen_andi_reg(dest, offset, -4); |
2045 | tcg_gen_ori_reg(dest, dest, ctx->privilege); | |
2046 | tcg_gen_movcond_reg(TCG_COND_GTU, dest, dest, offset, dest, offset); | |
660eefe1 RH |
2047 | break; |
2048 | } | |
2049 | return dest; | |
660eefe1 RH |
2050 | } |
2051 | ||
ba1d0b44 | 2052 | #ifdef CONFIG_USER_ONLY |
7ad439df RH |
2053 | /* On Linux, page zero is normally marked execute only + gateway. |
2054 | Therefore normal read or write is supposed to fail, but specific | |
2055 | offsets have kernel code mapped to raise permissions to implement | |
2056 | system calls. Handling this via an explicit check here, rather | |
2057 | in than the "be disp(sr2,r0)" instruction that probably sent us | |
2058 | here, is the easiest way to handle the branch delay slot on the | |
2059 | aforementioned BE. */ | |
31234768 | 2060 | static void do_page_zero(DisasContext *ctx) |
7ad439df | 2061 | { |
a0180973 RH |
2062 | TCGv_reg tmp; |
2063 | ||
7ad439df RH |
2064 | /* If by some means we get here with PSW[N]=1, that implies that |
2065 | the B,GATE instruction would be skipped, and we'd fault on the | |
8b81968c | 2066 | next insn within the privileged page. */ |
7ad439df RH |
2067 | switch (ctx->null_cond.c) { |
2068 | case TCG_COND_NEVER: | |
2069 | break; | |
2070 | case TCG_COND_ALWAYS: | |
eaa3783b | 2071 | tcg_gen_movi_reg(cpu_psw_n, 0); |
7ad439df RH |
2072 | goto do_sigill; |
2073 | default: | |
2074 | /* Since this is always the first (and only) insn within the | |
2075 | TB, we should know the state of PSW[N] from TB->FLAGS. */ | |
2076 | g_assert_not_reached(); | |
2077 | } | |
2078 | ||
2079 | /* Check that we didn't arrive here via some means that allowed | |
2080 | non-sequential instruction execution. Normally the PSW[B] bit | |
2081 | detects this by disallowing the B,GATE instruction to execute | |
2082 | under such conditions. */ | |
2083 | if (ctx->iaoq_b != ctx->iaoq_f + 4) { | |
2084 | goto do_sigill; | |
2085 | } | |
2086 | ||
ebd0e151 | 2087 | switch (ctx->iaoq_f & -4) { |
7ad439df | 2088 | case 0x00: /* Null pointer call */ |
2986721d | 2089 | gen_excp_1(EXCP_IMP); |
31234768 RH |
2090 | ctx->base.is_jmp = DISAS_NORETURN; |
2091 | break; | |
7ad439df RH |
2092 | |
2093 | case 0xb0: /* LWS */ | |
2094 | gen_excp_1(EXCP_SYSCALL_LWS); | |
31234768 RH |
2095 | ctx->base.is_jmp = DISAS_NORETURN; |
2096 | break; | |
7ad439df RH |
2097 | |
2098 | case 0xe0: /* SET_THREAD_POINTER */ | |
ad75a51e | 2099 | tcg_gen_st_reg(cpu_gr[26], tcg_env, offsetof(CPUHPPAState, cr[27])); |
a0180973 RH |
2100 | tmp = tcg_temp_new(); |
2101 | tcg_gen_ori_reg(tmp, cpu_gr[31], 3); | |
2102 | copy_iaoq_entry(ctx, cpu_iaoq_f, -1, tmp); | |
2103 | tcg_gen_addi_reg(tmp, tmp, 4); | |
2104 | copy_iaoq_entry(ctx, cpu_iaoq_b, -1, tmp); | |
31234768 RH |
2105 | ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; |
2106 | break; | |
7ad439df RH |
2107 | |
2108 | case 0x100: /* SYSCALL */ | |
2109 | gen_excp_1(EXCP_SYSCALL); | |
31234768 RH |
2110 | ctx->base.is_jmp = DISAS_NORETURN; |
2111 | break; | |
7ad439df RH |
2112 | |
2113 | default: | |
2114 | do_sigill: | |
2986721d | 2115 | gen_excp_1(EXCP_ILL); |
31234768 RH |
2116 | ctx->base.is_jmp = DISAS_NORETURN; |
2117 | break; | |
7ad439df RH |
2118 | } |
2119 | } | |
ba1d0b44 | 2120 | #endif |
7ad439df | 2121 | |
deee69a1 | 2122 | static bool trans_nop(DisasContext *ctx, arg_nop *a) |
b2167459 RH |
2123 | { |
2124 | cond_free(&ctx->null_cond); | |
31234768 | 2125 | return true; |
b2167459 RH |
2126 | } |
2127 | ||
40f9f908 | 2128 | static bool trans_break(DisasContext *ctx, arg_break *a) |
98a9cb79 | 2129 | { |
31234768 | 2130 | return gen_excp_iir(ctx, EXCP_BREAK); |
98a9cb79 RH |
2131 | } |
2132 | ||
e36f27ef | 2133 | static bool trans_sync(DisasContext *ctx, arg_sync *a) |
98a9cb79 RH |
2134 | { |
2135 | /* No point in nullifying the memory barrier. */ | |
2136 | tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); | |
2137 | ||
2138 | cond_free(&ctx->null_cond); | |
31234768 | 2139 | return true; |
98a9cb79 RH |
2140 | } |
2141 | ||
c603e14a | 2142 | static bool trans_mfia(DisasContext *ctx, arg_mfia *a) |
98a9cb79 | 2143 | { |
c603e14a | 2144 | unsigned rt = a->t; |
eaa3783b RH |
2145 | TCGv_reg tmp = dest_gpr(ctx, rt); |
2146 | tcg_gen_movi_reg(tmp, ctx->iaoq_f); | |
98a9cb79 RH |
2147 | save_gpr(ctx, rt, tmp); |
2148 | ||
2149 | cond_free(&ctx->null_cond); | |
31234768 | 2150 | return true; |
98a9cb79 RH |
2151 | } |
2152 | ||
c603e14a | 2153 | static bool trans_mfsp(DisasContext *ctx, arg_mfsp *a) |
98a9cb79 | 2154 | { |
c603e14a RH |
2155 | unsigned rt = a->t; |
2156 | unsigned rs = a->sp; | |
33423472 RH |
2157 | TCGv_i64 t0 = tcg_temp_new_i64(); |
2158 | TCGv_reg t1 = tcg_temp_new(); | |
98a9cb79 | 2159 | |
33423472 RH |
2160 | load_spr(ctx, t0, rs); |
2161 | tcg_gen_shri_i64(t0, t0, 32); | |
2162 | tcg_gen_trunc_i64_reg(t1, t0); | |
2163 | ||
2164 | save_gpr(ctx, rt, t1); | |
98a9cb79 RH |
2165 | |
2166 | cond_free(&ctx->null_cond); | |
31234768 | 2167 | return true; |
98a9cb79 RH |
2168 | } |
2169 | ||
c603e14a | 2170 | static bool trans_mfctl(DisasContext *ctx, arg_mfctl *a) |
98a9cb79 | 2171 | { |
c603e14a RH |
2172 | unsigned rt = a->t; |
2173 | unsigned ctl = a->r; | |
eaa3783b | 2174 | TCGv_reg tmp; |
98a9cb79 RH |
2175 | |
2176 | switch (ctl) { | |
35136a77 | 2177 | case CR_SAR: |
c603e14a | 2178 | if (a->e == 0) { |
98a9cb79 RH |
2179 | /* MFSAR without ,W masks low 5 bits. */ |
2180 | tmp = dest_gpr(ctx, rt); | |
eaa3783b | 2181 | tcg_gen_andi_reg(tmp, cpu_sar, 31); |
98a9cb79 | 2182 | save_gpr(ctx, rt, tmp); |
35136a77 | 2183 | goto done; |
98a9cb79 | 2184 | } |
98a9cb79 | 2185 | save_gpr(ctx, rt, cpu_sar); |
35136a77 RH |
2186 | goto done; |
2187 | case CR_IT: /* Interval Timer */ | |
2188 | /* FIXME: Respect PSW_S bit. */ | |
2189 | nullify_over(ctx); | |
98a9cb79 | 2190 | tmp = dest_gpr(ctx, rt); |
dfd1b812 | 2191 | if (translator_io_start(&ctx->base)) { |
49c29d6c | 2192 | gen_helper_read_interval_timer(tmp); |
31234768 | 2193 | ctx->base.is_jmp = DISAS_IAQ_N_STALE; |
49c29d6c RH |
2194 | } else { |
2195 | gen_helper_read_interval_timer(tmp); | |
49c29d6c | 2196 | } |
98a9cb79 | 2197 | save_gpr(ctx, rt, tmp); |
31234768 | 2198 | return nullify_end(ctx); |
98a9cb79 | 2199 | case 26: |
98a9cb79 | 2200 | case 27: |
98a9cb79 RH |
2201 | break; |
2202 | default: | |
2203 | /* All other control registers are privileged. */ | |
35136a77 RH |
2204 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG); |
2205 | break; | |
98a9cb79 RH |
2206 | } |
2207 | ||
e12c6309 | 2208 | tmp = tcg_temp_new(); |
ad75a51e | 2209 | tcg_gen_ld_reg(tmp, tcg_env, offsetof(CPUHPPAState, cr[ctl])); |
35136a77 RH |
2210 | save_gpr(ctx, rt, tmp); |
2211 | ||
2212 | done: | |
98a9cb79 | 2213 | cond_free(&ctx->null_cond); |
31234768 | 2214 | return true; |
98a9cb79 RH |
2215 | } |
2216 | ||
c603e14a | 2217 | static bool trans_mtsp(DisasContext *ctx, arg_mtsp *a) |
33423472 | 2218 | { |
c603e14a RH |
2219 | unsigned rr = a->r; |
2220 | unsigned rs = a->sp; | |
33423472 RH |
2221 | TCGv_i64 t64; |
2222 | ||
2223 | if (rs >= 5) { | |
2224 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG); | |
2225 | } | |
2226 | nullify_over(ctx); | |
2227 | ||
2228 | t64 = tcg_temp_new_i64(); | |
2229 | tcg_gen_extu_reg_i64(t64, load_gpr(ctx, rr)); | |
2230 | tcg_gen_shli_i64(t64, t64, 32); | |
2231 | ||
2232 | if (rs >= 4) { | |
ad75a51e | 2233 | tcg_gen_st_i64(t64, tcg_env, offsetof(CPUHPPAState, sr[rs])); |
494737b7 | 2234 | ctx->tb_flags &= ~TB_FLAG_SR_SAME; |
33423472 RH |
2235 | } else { |
2236 | tcg_gen_mov_i64(cpu_sr[rs], t64); | |
2237 | } | |
33423472 | 2238 | |
31234768 | 2239 | return nullify_end(ctx); |
33423472 RH |
2240 | } |
2241 | ||
c603e14a | 2242 | static bool trans_mtctl(DisasContext *ctx, arg_mtctl *a) |
98a9cb79 | 2243 | { |
c603e14a | 2244 | unsigned ctl = a->t; |
4845f015 | 2245 | TCGv_reg reg; |
eaa3783b | 2246 | TCGv_reg tmp; |
98a9cb79 | 2247 | |
35136a77 | 2248 | if (ctl == CR_SAR) { |
4845f015 | 2249 | reg = load_gpr(ctx, a->r); |
98a9cb79 | 2250 | tmp = tcg_temp_new(); |
f3618f59 | 2251 | tcg_gen_andi_reg(tmp, reg, ctx->is_pa20 ? 63 : 31); |
98a9cb79 | 2252 | save_or_nullify(ctx, cpu_sar, tmp); |
35136a77 RH |
2253 | |
2254 | cond_free(&ctx->null_cond); | |
31234768 | 2255 | return true; |
98a9cb79 RH |
2256 | } |
2257 | ||
35136a77 RH |
2258 | /* All other control registers are privileged or read-only. */ |
2259 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG); | |
2260 | ||
c603e14a | 2261 | #ifndef CONFIG_USER_ONLY |
35136a77 | 2262 | nullify_over(ctx); |
4845f015 SS |
2263 | reg = load_gpr(ctx, a->r); |
2264 | ||
35136a77 RH |
2265 | switch (ctl) { |
2266 | case CR_IT: | |
ad75a51e | 2267 | gen_helper_write_interval_timer(tcg_env, reg); |
35136a77 | 2268 | break; |
4f5f2548 | 2269 | case CR_EIRR: |
ad75a51e | 2270 | gen_helper_write_eirr(tcg_env, reg); |
4f5f2548 RH |
2271 | break; |
2272 | case CR_EIEM: | |
ad75a51e | 2273 | gen_helper_write_eiem(tcg_env, reg); |
31234768 | 2274 | ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; |
4f5f2548 RH |
2275 | break; |
2276 | ||
35136a77 RH |
2277 | case CR_IIASQ: |
2278 | case CR_IIAOQ: | |
2279 | /* FIXME: Respect PSW_Q bit */ | |
2280 | /* The write advances the queue and stores to the back element. */ | |
e12c6309 | 2281 | tmp = tcg_temp_new(); |
ad75a51e | 2282 | tcg_gen_ld_reg(tmp, tcg_env, |
35136a77 | 2283 | offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ])); |
ad75a51e RH |
2284 | tcg_gen_st_reg(tmp, tcg_env, offsetof(CPUHPPAState, cr[ctl])); |
2285 | tcg_gen_st_reg(reg, tcg_env, | |
35136a77 RH |
2286 | offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ])); |
2287 | break; | |
2288 | ||
d5de20bd SS |
2289 | case CR_PID1: |
2290 | case CR_PID2: | |
2291 | case CR_PID3: | |
2292 | case CR_PID4: | |
ad75a51e | 2293 | tcg_gen_st_reg(reg, tcg_env, offsetof(CPUHPPAState, cr[ctl])); |
d5de20bd | 2294 | #ifndef CONFIG_USER_ONLY |
ad75a51e | 2295 | gen_helper_change_prot_id(tcg_env); |
d5de20bd SS |
2296 | #endif |
2297 | break; | |
2298 | ||
35136a77 | 2299 | default: |
ad75a51e | 2300 | tcg_gen_st_reg(reg, tcg_env, offsetof(CPUHPPAState, cr[ctl])); |
35136a77 RH |
2301 | break; |
2302 | } | |
31234768 | 2303 | return nullify_end(ctx); |
4f5f2548 | 2304 | #endif |
98a9cb79 RH |
2305 | } |
2306 | ||
c603e14a | 2307 | static bool trans_mtsarcm(DisasContext *ctx, arg_mtsarcm *a) |
98a9cb79 | 2308 | { |
eaa3783b | 2309 | TCGv_reg tmp = tcg_temp_new(); |
98a9cb79 | 2310 | |
c603e14a | 2311 | tcg_gen_not_reg(tmp, load_gpr(ctx, a->r)); |
f3618f59 | 2312 | tcg_gen_andi_reg(tmp, tmp, ctx->is_pa20 ? 63 : 31); |
98a9cb79 | 2313 | save_or_nullify(ctx, cpu_sar, tmp); |
98a9cb79 RH |
2314 | |
2315 | cond_free(&ctx->null_cond); | |
31234768 | 2316 | return true; |
98a9cb79 RH |
2317 | } |
2318 | ||
e36f27ef | 2319 | static bool trans_ldsid(DisasContext *ctx, arg_ldsid *a) |
98a9cb79 | 2320 | { |
e36f27ef | 2321 | TCGv_reg dest = dest_gpr(ctx, a->t); |
98a9cb79 | 2322 | |
2330504c HD |
2323 | #ifdef CONFIG_USER_ONLY |
2324 | /* We don't implement space registers in user mode. */ | |
eaa3783b | 2325 | tcg_gen_movi_reg(dest, 0); |
2330504c | 2326 | #else |
2330504c HD |
2327 | TCGv_i64 t0 = tcg_temp_new_i64(); |
2328 | ||
e36f27ef | 2329 | tcg_gen_mov_i64(t0, space_select(ctx, a->sp, load_gpr(ctx, a->b))); |
2330504c HD |
2330 | tcg_gen_shri_i64(t0, t0, 32); |
2331 | tcg_gen_trunc_i64_reg(dest, t0); | |
2330504c | 2332 | #endif |
e36f27ef | 2333 | save_gpr(ctx, a->t, dest); |
98a9cb79 RH |
2334 | |
2335 | cond_free(&ctx->null_cond); | |
31234768 | 2336 | return true; |
98a9cb79 RH |
2337 | } |
2338 | ||
e36f27ef | 2339 | static bool trans_rsm(DisasContext *ctx, arg_rsm *a) |
e1b5a5ed | 2340 | { |
e36f27ef RH |
2341 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); |
2342 | #ifndef CONFIG_USER_ONLY | |
e1b5a5ed RH |
2343 | TCGv_reg tmp; |
2344 | ||
e1b5a5ed RH |
2345 | nullify_over(ctx); |
2346 | ||
e12c6309 | 2347 | tmp = tcg_temp_new(); |
ad75a51e | 2348 | tcg_gen_ld_reg(tmp, tcg_env, offsetof(CPUHPPAState, psw)); |
e36f27ef | 2349 | tcg_gen_andi_reg(tmp, tmp, ~a->i); |
ad75a51e | 2350 | gen_helper_swap_system_mask(tmp, tcg_env, tmp); |
e36f27ef | 2351 | save_gpr(ctx, a->t, tmp); |
e1b5a5ed RH |
2352 | |
2353 | /* Exit the TB to recognize new interrupts, e.g. PSW_M. */ | |
31234768 RH |
2354 | ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; |
2355 | return nullify_end(ctx); | |
e36f27ef | 2356 | #endif |
e1b5a5ed RH |
2357 | } |
2358 | ||
e36f27ef | 2359 | static bool trans_ssm(DisasContext *ctx, arg_ssm *a) |
e1b5a5ed | 2360 | { |
e36f27ef RH |
2361 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); |
2362 | #ifndef CONFIG_USER_ONLY | |
e1b5a5ed RH |
2363 | TCGv_reg tmp; |
2364 | ||
e1b5a5ed RH |
2365 | nullify_over(ctx); |
2366 | ||
e12c6309 | 2367 | tmp = tcg_temp_new(); |
ad75a51e | 2368 | tcg_gen_ld_reg(tmp, tcg_env, offsetof(CPUHPPAState, psw)); |
e36f27ef | 2369 | tcg_gen_ori_reg(tmp, tmp, a->i); |
ad75a51e | 2370 | gen_helper_swap_system_mask(tmp, tcg_env, tmp); |
e36f27ef | 2371 | save_gpr(ctx, a->t, tmp); |
e1b5a5ed RH |
2372 | |
2373 | /* Exit the TB to recognize new interrupts, e.g. PSW_I. */ | |
31234768 RH |
2374 | ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; |
2375 | return nullify_end(ctx); | |
e36f27ef | 2376 | #endif |
e1b5a5ed RH |
2377 | } |
2378 | ||
c603e14a | 2379 | static bool trans_mtsm(DisasContext *ctx, arg_mtsm *a) |
e1b5a5ed | 2380 | { |
e1b5a5ed | 2381 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); |
c603e14a RH |
2382 | #ifndef CONFIG_USER_ONLY |
2383 | TCGv_reg tmp, reg; | |
e1b5a5ed RH |
2384 | nullify_over(ctx); |
2385 | ||
c603e14a | 2386 | reg = load_gpr(ctx, a->r); |
e12c6309 | 2387 | tmp = tcg_temp_new(); |
ad75a51e | 2388 | gen_helper_swap_system_mask(tmp, tcg_env, reg); |
e1b5a5ed RH |
2389 | |
2390 | /* Exit the TB to recognize new interrupts. */ | |
31234768 RH |
2391 | ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; |
2392 | return nullify_end(ctx); | |
c603e14a | 2393 | #endif |
e1b5a5ed | 2394 | } |
f49b3537 | 2395 | |
e36f27ef | 2396 | static bool do_rfi(DisasContext *ctx, bool rfi_r) |
f49b3537 | 2397 | { |
f49b3537 | 2398 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); |
e36f27ef | 2399 | #ifndef CONFIG_USER_ONLY |
f49b3537 RH |
2400 | nullify_over(ctx); |
2401 | ||
e36f27ef | 2402 | if (rfi_r) { |
ad75a51e | 2403 | gen_helper_rfi_r(tcg_env); |
f49b3537 | 2404 | } else { |
ad75a51e | 2405 | gen_helper_rfi(tcg_env); |
f49b3537 | 2406 | } |
31234768 | 2407 | /* Exit the TB to recognize new interrupts. */ |
8532a14e | 2408 | tcg_gen_exit_tb(NULL, 0); |
31234768 | 2409 | ctx->base.is_jmp = DISAS_NORETURN; |
f49b3537 | 2410 | |
31234768 | 2411 | return nullify_end(ctx); |
e36f27ef RH |
2412 | #endif |
2413 | } | |
2414 | ||
2415 | static bool trans_rfi(DisasContext *ctx, arg_rfi *a) | |
2416 | { | |
2417 | return do_rfi(ctx, false); | |
2418 | } | |
2419 | ||
2420 | static bool trans_rfi_r(DisasContext *ctx, arg_rfi_r *a) | |
2421 | { | |
2422 | return do_rfi(ctx, true); | |
f49b3537 | 2423 | } |
6210db05 | 2424 | |
96927adb RH |
2425 | static bool trans_halt(DisasContext *ctx, arg_halt *a) |
2426 | { | |
2427 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); | |
e36f27ef | 2428 | #ifndef CONFIG_USER_ONLY |
96927adb | 2429 | nullify_over(ctx); |
ad75a51e | 2430 | gen_helper_halt(tcg_env); |
96927adb RH |
2431 | ctx->base.is_jmp = DISAS_NORETURN; |
2432 | return nullify_end(ctx); | |
2433 | #endif | |
2434 | } | |
2435 | ||
2436 | static bool trans_reset(DisasContext *ctx, arg_reset *a) | |
6210db05 HD |
2437 | { |
2438 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); | |
96927adb | 2439 | #ifndef CONFIG_USER_ONLY |
6210db05 | 2440 | nullify_over(ctx); |
ad75a51e | 2441 | gen_helper_reset(tcg_env); |
31234768 RH |
2442 | ctx->base.is_jmp = DISAS_NORETURN; |
2443 | return nullify_end(ctx); | |
96927adb | 2444 | #endif |
6210db05 | 2445 | } |
e1b5a5ed | 2446 | |
4a4554c6 HD |
2447 | static bool trans_getshadowregs(DisasContext *ctx, arg_getshadowregs *a) |
2448 | { | |
2449 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); | |
2450 | #ifndef CONFIG_USER_ONLY | |
2451 | nullify_over(ctx); | |
ad75a51e | 2452 | gen_helper_getshadowregs(tcg_env); |
4a4554c6 HD |
2453 | return nullify_end(ctx); |
2454 | #endif | |
2455 | } | |
2456 | ||
deee69a1 | 2457 | static bool trans_nop_addrx(DisasContext *ctx, arg_ldst *a) |
98a9cb79 | 2458 | { |
deee69a1 RH |
2459 | if (a->m) { |
2460 | TCGv_reg dest = dest_gpr(ctx, a->b); | |
2461 | TCGv_reg src1 = load_gpr(ctx, a->b); | |
2462 | TCGv_reg src2 = load_gpr(ctx, a->x); | |
98a9cb79 | 2463 | |
deee69a1 RH |
2464 | /* The only thing we need to do is the base register modification. */ |
2465 | tcg_gen_add_reg(dest, src1, src2); | |
2466 | save_gpr(ctx, a->b, dest); | |
2467 | } | |
98a9cb79 | 2468 | cond_free(&ctx->null_cond); |
31234768 | 2469 | return true; |
98a9cb79 RH |
2470 | } |
2471 | ||
deee69a1 | 2472 | static bool trans_probe(DisasContext *ctx, arg_probe *a) |
98a9cb79 | 2473 | { |
86f8d05f | 2474 | TCGv_reg dest, ofs; |
eed14219 | 2475 | TCGv_i32 level, want; |
86f8d05f | 2476 | TCGv_tl addr; |
98a9cb79 RH |
2477 | |
2478 | nullify_over(ctx); | |
2479 | ||
deee69a1 RH |
2480 | dest = dest_gpr(ctx, a->t); |
2481 | form_gva(ctx, &addr, &ofs, a->b, 0, 0, 0, a->sp, 0, false); | |
eed14219 | 2482 | |
deee69a1 | 2483 | if (a->imm) { |
29dd6f64 | 2484 | level = tcg_constant_i32(a->ri); |
98a9cb79 | 2485 | } else { |
eed14219 | 2486 | level = tcg_temp_new_i32(); |
deee69a1 | 2487 | tcg_gen_trunc_reg_i32(level, load_gpr(ctx, a->ri)); |
eed14219 | 2488 | tcg_gen_andi_i32(level, level, 3); |
98a9cb79 | 2489 | } |
29dd6f64 | 2490 | want = tcg_constant_i32(a->write ? PAGE_WRITE : PAGE_READ); |
eed14219 | 2491 | |
ad75a51e | 2492 | gen_helper_probe(dest, tcg_env, addr, level, want); |
eed14219 | 2493 | |
deee69a1 | 2494 | save_gpr(ctx, a->t, dest); |
31234768 | 2495 | return nullify_end(ctx); |
98a9cb79 RH |
2496 | } |
2497 | ||
deee69a1 | 2498 | static bool trans_ixtlbx(DisasContext *ctx, arg_ixtlbx *a) |
8d6ae7fb | 2499 | { |
deee69a1 RH |
2500 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); |
2501 | #ifndef CONFIG_USER_ONLY | |
8d6ae7fb RH |
2502 | TCGv_tl addr; |
2503 | TCGv_reg ofs, reg; | |
2504 | ||
8d6ae7fb RH |
2505 | nullify_over(ctx); |
2506 | ||
deee69a1 RH |
2507 | form_gva(ctx, &addr, &ofs, a->b, 0, 0, 0, a->sp, 0, false); |
2508 | reg = load_gpr(ctx, a->r); | |
2509 | if (a->addr) { | |
ad75a51e | 2510 | gen_helper_itlba(tcg_env, addr, reg); |
8d6ae7fb | 2511 | } else { |
ad75a51e | 2512 | gen_helper_itlbp(tcg_env, addr, reg); |
8d6ae7fb RH |
2513 | } |
2514 | ||
32dc7569 SS |
2515 | /* Exit TB for TLB change if mmu is enabled. */ |
2516 | if (ctx->tb_flags & PSW_C) { | |
31234768 RH |
2517 | ctx->base.is_jmp = DISAS_IAQ_N_STALE; |
2518 | } | |
2519 | return nullify_end(ctx); | |
deee69a1 | 2520 | #endif |
8d6ae7fb | 2521 | } |
63300a00 | 2522 | |
deee69a1 | 2523 | static bool trans_pxtlbx(DisasContext *ctx, arg_pxtlbx *a) |
63300a00 | 2524 | { |
deee69a1 RH |
2525 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); |
2526 | #ifndef CONFIG_USER_ONLY | |
63300a00 RH |
2527 | TCGv_tl addr; |
2528 | TCGv_reg ofs; | |
2529 | ||
63300a00 RH |
2530 | nullify_over(ctx); |
2531 | ||
deee69a1 RH |
2532 | form_gva(ctx, &addr, &ofs, a->b, a->x, 0, 0, a->sp, a->m, false); |
2533 | if (a->m) { | |
2534 | save_gpr(ctx, a->b, ofs); | |
63300a00 | 2535 | } |
deee69a1 | 2536 | if (a->local) { |
ad75a51e | 2537 | gen_helper_ptlbe(tcg_env); |
63300a00 | 2538 | } else { |
ad75a51e | 2539 | gen_helper_ptlb(tcg_env, addr); |
63300a00 RH |
2540 | } |
2541 | ||
2542 | /* Exit TB for TLB change if mmu is enabled. */ | |
6797c315 NH |
2543 | if (ctx->tb_flags & PSW_C) { |
2544 | ctx->base.is_jmp = DISAS_IAQ_N_STALE; | |
2545 | } | |
2546 | return nullify_end(ctx); | |
2547 | #endif | |
2548 | } | |
2549 | ||
2550 | /* | |
2551 | * Implement the pcxl and pcxl2 Fast TLB Insert instructions. | |
2552 | * See | |
2553 | * https://parisc.wiki.kernel.org/images-parisc/a/a9/Pcxl2_ers.pdf | |
2554 | * page 13-9 (195/206) | |
2555 | */ | |
2556 | static bool trans_ixtlbxf(DisasContext *ctx, arg_ixtlbxf *a) | |
2557 | { | |
2558 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); | |
2559 | #ifndef CONFIG_USER_ONLY | |
2560 | TCGv_tl addr, atl, stl; | |
2561 | TCGv_reg reg; | |
2562 | ||
2563 | nullify_over(ctx); | |
2564 | ||
2565 | /* | |
2566 | * FIXME: | |
2567 | * if (not (pcxl or pcxl2)) | |
2568 | * return gen_illegal(ctx); | |
2569 | * | |
2570 | * Note for future: these are 32-bit systems; no hppa64. | |
2571 | */ | |
2572 | ||
2573 | atl = tcg_temp_new_tl(); | |
2574 | stl = tcg_temp_new_tl(); | |
2575 | addr = tcg_temp_new_tl(); | |
2576 | ||
ad75a51e | 2577 | tcg_gen_ld32u_i64(stl, tcg_env, |
6797c315 NH |
2578 | a->data ? offsetof(CPUHPPAState, cr[CR_ISR]) |
2579 | : offsetof(CPUHPPAState, cr[CR_IIASQ])); | |
ad75a51e | 2580 | tcg_gen_ld32u_i64(atl, tcg_env, |
6797c315 NH |
2581 | a->data ? offsetof(CPUHPPAState, cr[CR_IOR]) |
2582 | : offsetof(CPUHPPAState, cr[CR_IIAOQ])); | |
2583 | tcg_gen_shli_i64(stl, stl, 32); | |
2584 | tcg_gen_or_tl(addr, atl, stl); | |
6797c315 NH |
2585 | |
2586 | reg = load_gpr(ctx, a->r); | |
2587 | if (a->addr) { | |
ad75a51e | 2588 | gen_helper_itlba(tcg_env, addr, reg); |
6797c315 | 2589 | } else { |
ad75a51e | 2590 | gen_helper_itlbp(tcg_env, addr, reg); |
6797c315 | 2591 | } |
6797c315 NH |
2592 | |
2593 | /* Exit TB for TLB change if mmu is enabled. */ | |
32dc7569 | 2594 | if (ctx->tb_flags & PSW_C) { |
31234768 RH |
2595 | ctx->base.is_jmp = DISAS_IAQ_N_STALE; |
2596 | } | |
2597 | return nullify_end(ctx); | |
deee69a1 | 2598 | #endif |
63300a00 | 2599 | } |
2dfcca9f | 2600 | |
deee69a1 | 2601 | static bool trans_lpa(DisasContext *ctx, arg_ldst *a) |
2dfcca9f | 2602 | { |
deee69a1 RH |
2603 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); |
2604 | #ifndef CONFIG_USER_ONLY | |
2dfcca9f RH |
2605 | TCGv_tl vaddr; |
2606 | TCGv_reg ofs, paddr; | |
2607 | ||
2dfcca9f RH |
2608 | nullify_over(ctx); |
2609 | ||
deee69a1 | 2610 | form_gva(ctx, &vaddr, &ofs, a->b, a->x, 0, 0, a->sp, a->m, false); |
2dfcca9f RH |
2611 | |
2612 | paddr = tcg_temp_new(); | |
ad75a51e | 2613 | gen_helper_lpa(paddr, tcg_env, vaddr); |
2dfcca9f RH |
2614 | |
2615 | /* Note that physical address result overrides base modification. */ | |
deee69a1 RH |
2616 | if (a->m) { |
2617 | save_gpr(ctx, a->b, ofs); | |
2dfcca9f | 2618 | } |
deee69a1 | 2619 | save_gpr(ctx, a->t, paddr); |
2dfcca9f | 2620 | |
31234768 | 2621 | return nullify_end(ctx); |
deee69a1 | 2622 | #endif |
2dfcca9f | 2623 | } |
43a97b81 | 2624 | |
deee69a1 | 2625 | static bool trans_lci(DisasContext *ctx, arg_lci *a) |
43a97b81 | 2626 | { |
43a97b81 RH |
2627 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); |
2628 | ||
2629 | /* The Coherence Index is an implementation-defined function of the | |
2630 | physical address. Two addresses with the same CI have a coherent | |
2631 | view of the cache. Our implementation is to return 0 for all, | |
2632 | since the entire address space is coherent. */ | |
29dd6f64 | 2633 | save_gpr(ctx, a->t, tcg_constant_reg(0)); |
43a97b81 | 2634 | |
31234768 RH |
2635 | cond_free(&ctx->null_cond); |
2636 | return true; | |
43a97b81 | 2637 | } |
98a9cb79 | 2638 | |
0c982a28 | 2639 | static bool trans_add(DisasContext *ctx, arg_rrr_cf_sh *a) |
b2167459 | 2640 | { |
0c982a28 RH |
2641 | return do_add_reg(ctx, a, false, false, false, false); |
2642 | } | |
b2167459 | 2643 | |
0c982a28 RH |
2644 | static bool trans_add_l(DisasContext *ctx, arg_rrr_cf_sh *a) |
2645 | { | |
2646 | return do_add_reg(ctx, a, true, false, false, false); | |
2647 | } | |
b2167459 | 2648 | |
0c982a28 RH |
2649 | static bool trans_add_tsv(DisasContext *ctx, arg_rrr_cf_sh *a) |
2650 | { | |
2651 | return do_add_reg(ctx, a, false, true, false, false); | |
b2167459 RH |
2652 | } |
2653 | ||
0c982a28 | 2654 | static bool trans_add_c(DisasContext *ctx, arg_rrr_cf_sh *a) |
b2167459 | 2655 | { |
0c982a28 RH |
2656 | return do_add_reg(ctx, a, false, false, false, true); |
2657 | } | |
b2167459 | 2658 | |
0c982a28 RH |
2659 | static bool trans_add_c_tsv(DisasContext *ctx, arg_rrr_cf_sh *a) |
2660 | { | |
2661 | return do_add_reg(ctx, a, false, true, false, true); | |
2662 | } | |
b2167459 | 2663 | |
0c982a28 RH |
2664 | static bool trans_sub(DisasContext *ctx, arg_rrr_cf *a) |
2665 | { | |
2666 | return do_sub_reg(ctx, a, false, false, false); | |
b2167459 RH |
2667 | } |
2668 | ||
0c982a28 | 2669 | static bool trans_sub_tsv(DisasContext *ctx, arg_rrr_cf *a) |
b2167459 | 2670 | { |
0c982a28 RH |
2671 | return do_sub_reg(ctx, a, true, false, false); |
2672 | } | |
b2167459 | 2673 | |
0c982a28 RH |
2674 | static bool trans_sub_tc(DisasContext *ctx, arg_rrr_cf *a) |
2675 | { | |
2676 | return do_sub_reg(ctx, a, false, false, true); | |
b2167459 RH |
2677 | } |
2678 | ||
0c982a28 | 2679 | static bool trans_sub_tsv_tc(DisasContext *ctx, arg_rrr_cf *a) |
b2167459 | 2680 | { |
0c982a28 RH |
2681 | return do_sub_reg(ctx, a, true, false, true); |
2682 | } | |
2683 | ||
2684 | static bool trans_sub_b(DisasContext *ctx, arg_rrr_cf *a) | |
2685 | { | |
2686 | return do_sub_reg(ctx, a, false, true, false); | |
2687 | } | |
2688 | ||
2689 | static bool trans_sub_b_tsv(DisasContext *ctx, arg_rrr_cf *a) | |
2690 | { | |
2691 | return do_sub_reg(ctx, a, true, true, false); | |
2692 | } | |
2693 | ||
fa8e3bed | 2694 | static bool trans_andcm(DisasContext *ctx, arg_rrr_cf_d *a) |
0c982a28 RH |
2695 | { |
2696 | return do_log_reg(ctx, a, tcg_gen_andc_reg); | |
2697 | } | |
2698 | ||
fa8e3bed | 2699 | static bool trans_and(DisasContext *ctx, arg_rrr_cf_d *a) |
0c982a28 RH |
2700 | { |
2701 | return do_log_reg(ctx, a, tcg_gen_and_reg); | |
2702 | } | |
2703 | ||
fa8e3bed | 2704 | static bool trans_or(DisasContext *ctx, arg_rrr_cf_d *a) |
0c982a28 RH |
2705 | { |
2706 | if (a->cf == 0) { | |
2707 | unsigned r2 = a->r2; | |
2708 | unsigned r1 = a->r1; | |
2709 | unsigned rt = a->t; | |
b2167459 | 2710 | |
7aee8189 RH |
2711 | if (rt == 0) { /* NOP */ |
2712 | cond_free(&ctx->null_cond); | |
2713 | return true; | |
2714 | } | |
2715 | if (r2 == 0) { /* COPY */ | |
2716 | if (r1 == 0) { | |
2717 | TCGv_reg dest = dest_gpr(ctx, rt); | |
2718 | tcg_gen_movi_reg(dest, 0); | |
2719 | save_gpr(ctx, rt, dest); | |
2720 | } else { | |
2721 | save_gpr(ctx, rt, cpu_gr[r1]); | |
2722 | } | |
2723 | cond_free(&ctx->null_cond); | |
2724 | return true; | |
2725 | } | |
2726 | #ifndef CONFIG_USER_ONLY | |
2727 | /* These are QEMU extensions and are nops in the real architecture: | |
2728 | * | |
2729 | * or %r10,%r10,%r10 -- idle loop; wait for interrupt | |
2730 | * or %r31,%r31,%r31 -- death loop; offline cpu | |
2731 | * currently implemented as idle. | |
2732 | */ | |
2733 | if ((rt == 10 || rt == 31) && r1 == rt && r2 == rt) { /* PAUSE */ | |
7aee8189 RH |
2734 | /* No need to check for supervisor, as userland can only pause |
2735 | until the next timer interrupt. */ | |
2736 | nullify_over(ctx); | |
2737 | ||
2738 | /* Advance the instruction queue. */ | |
741322f4 RH |
2739 | copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); |
2740 | copy_iaoq_entry(ctx, cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var); | |
7aee8189 RH |
2741 | nullify_set(ctx, 0); |
2742 | ||
2743 | /* Tell the qemu main loop to halt until this cpu has work. */ | |
ad75a51e | 2744 | tcg_gen_st_i32(tcg_constant_i32(1), tcg_env, |
29dd6f64 | 2745 | offsetof(CPUState, halted) - offsetof(HPPACPU, env)); |
7aee8189 RH |
2746 | gen_excp_1(EXCP_HALTED); |
2747 | ctx->base.is_jmp = DISAS_NORETURN; | |
2748 | ||
2749 | return nullify_end(ctx); | |
2750 | } | |
2751 | #endif | |
b2167459 | 2752 | } |
0c982a28 RH |
2753 | return do_log_reg(ctx, a, tcg_gen_or_reg); |
2754 | } | |
7aee8189 | 2755 | |
fa8e3bed | 2756 | static bool trans_xor(DisasContext *ctx, arg_rrr_cf_d *a) |
0c982a28 RH |
2757 | { |
2758 | return do_log_reg(ctx, a, tcg_gen_xor_reg); | |
b2167459 RH |
2759 | } |
2760 | ||
0c982a28 | 2761 | static bool trans_cmpclr(DisasContext *ctx, arg_rrr_cf *a) |
b2167459 | 2762 | { |
eaa3783b | 2763 | TCGv_reg tcg_r1, tcg_r2; |
b2167459 | 2764 | |
0c982a28 | 2765 | if (a->cf) { |
b2167459 RH |
2766 | nullify_over(ctx); |
2767 | } | |
0c982a28 RH |
2768 | tcg_r1 = load_gpr(ctx, a->r1); |
2769 | tcg_r2 = load_gpr(ctx, a->r2); | |
2770 | do_cmpclr(ctx, a->t, tcg_r1, tcg_r2, a->cf); | |
31234768 | 2771 | return nullify_end(ctx); |
b2167459 RH |
2772 | } |
2773 | ||
af240753 | 2774 | static bool trans_uxor(DisasContext *ctx, arg_rrr_cf_d *a) |
b2167459 | 2775 | { |
eaa3783b | 2776 | TCGv_reg tcg_r1, tcg_r2; |
b2167459 | 2777 | |
0c982a28 | 2778 | if (a->cf) { |
b2167459 RH |
2779 | nullify_over(ctx); |
2780 | } | |
0c982a28 RH |
2781 | tcg_r1 = load_gpr(ctx, a->r1); |
2782 | tcg_r2 = load_gpr(ctx, a->r2); | |
af240753 | 2783 | do_unit(ctx, a->t, tcg_r1, tcg_r2, a->cf, a->d, false, tcg_gen_xor_reg); |
31234768 | 2784 | return nullify_end(ctx); |
b2167459 RH |
2785 | } |
2786 | ||
af240753 | 2787 | static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf_d *a, bool is_tc) |
b2167459 | 2788 | { |
eaa3783b | 2789 | TCGv_reg tcg_r1, tcg_r2, tmp; |
b2167459 | 2790 | |
0c982a28 | 2791 | if (a->cf) { |
b2167459 RH |
2792 | nullify_over(ctx); |
2793 | } | |
0c982a28 RH |
2794 | tcg_r1 = load_gpr(ctx, a->r1); |
2795 | tcg_r2 = load_gpr(ctx, a->r2); | |
e12c6309 | 2796 | tmp = tcg_temp_new(); |
eaa3783b | 2797 | tcg_gen_not_reg(tmp, tcg_r2); |
af240753 | 2798 | do_unit(ctx, a->t, tcg_r1, tmp, a->cf, a->d, is_tc, tcg_gen_add_reg); |
31234768 | 2799 | return nullify_end(ctx); |
b2167459 RH |
2800 | } |
2801 | ||
af240753 | 2802 | static bool trans_uaddcm(DisasContext *ctx, arg_rrr_cf_d *a) |
0c982a28 RH |
2803 | { |
2804 | return do_uaddcm(ctx, a, false); | |
2805 | } | |
2806 | ||
af240753 | 2807 | static bool trans_uaddcm_tc(DisasContext *ctx, arg_rrr_cf_d *a) |
0c982a28 RH |
2808 | { |
2809 | return do_uaddcm(ctx, a, true); | |
2810 | } | |
2811 | ||
af240753 | 2812 | static bool do_dcor(DisasContext *ctx, arg_rr_cf_d *a, bool is_i) |
b2167459 | 2813 | { |
eaa3783b | 2814 | TCGv_reg tmp; |
b2167459 RH |
2815 | |
2816 | nullify_over(ctx); | |
2817 | ||
e12c6309 | 2818 | tmp = tcg_temp_new(); |
eaa3783b | 2819 | tcg_gen_shri_reg(tmp, cpu_psw_cb, 3); |
b2167459 | 2820 | if (!is_i) { |
eaa3783b | 2821 | tcg_gen_not_reg(tmp, tmp); |
b2167459 | 2822 | } |
af240753 | 2823 | tcg_gen_andi_reg(tmp, tmp, (target_ureg)0x1111111111111111ull); |
eaa3783b | 2824 | tcg_gen_muli_reg(tmp, tmp, 6); |
af240753 | 2825 | do_unit(ctx, a->t, load_gpr(ctx, a->r), tmp, a->cf, a->d, false, |
31234768 | 2826 | is_i ? tcg_gen_add_reg : tcg_gen_sub_reg); |
31234768 | 2827 | return nullify_end(ctx); |
b2167459 RH |
2828 | } |
2829 | ||
af240753 | 2830 | static bool trans_dcor(DisasContext *ctx, arg_rr_cf_d *a) |
0c982a28 RH |
2831 | { |
2832 | return do_dcor(ctx, a, false); | |
2833 | } | |
2834 | ||
af240753 | 2835 | static bool trans_dcor_i(DisasContext *ctx, arg_rr_cf_d *a) |
0c982a28 RH |
2836 | { |
2837 | return do_dcor(ctx, a, true); | |
2838 | } | |
2839 | ||
2840 | static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a) | |
b2167459 | 2841 | { |
eaa3783b | 2842 | TCGv_reg dest, add1, add2, addc, zero, in1, in2; |
72ca8753 | 2843 | TCGv_reg cout; |
b2167459 RH |
2844 | |
2845 | nullify_over(ctx); | |
2846 | ||
0c982a28 RH |
2847 | in1 = load_gpr(ctx, a->r1); |
2848 | in2 = load_gpr(ctx, a->r2); | |
b2167459 RH |
2849 | |
2850 | add1 = tcg_temp_new(); | |
2851 | add2 = tcg_temp_new(); | |
2852 | addc = tcg_temp_new(); | |
2853 | dest = tcg_temp_new(); | |
29dd6f64 | 2854 | zero = tcg_constant_reg(0); |
b2167459 RH |
2855 | |
2856 | /* Form R1 << 1 | PSW[CB]{8}. */ | |
eaa3783b | 2857 | tcg_gen_add_reg(add1, in1, in1); |
72ca8753 | 2858 | tcg_gen_add_reg(add1, add1, get_psw_carry(ctx, false)); |
b2167459 | 2859 | |
72ca8753 RH |
2860 | /* |
2861 | * Add or subtract R2, depending on PSW[V]. Proper computation of | |
2862 | * carry requires that we subtract via + ~R2 + 1, as described in | |
2863 | * the manual. By extracting and masking V, we can produce the | |
2864 | * proper inputs to the addition without movcond. | |
2865 | */ | |
2866 | tcg_gen_sextract_reg(addc, cpu_psw_v, 31, 1); | |
eaa3783b RH |
2867 | tcg_gen_xor_reg(add2, in2, addc); |
2868 | tcg_gen_andi_reg(addc, addc, 1); | |
72ca8753 RH |
2869 | |
2870 | tcg_gen_add2_reg(dest, cpu_psw_cb_msb, add1, zero, add2, zero); | |
2871 | tcg_gen_add2_reg(dest, cpu_psw_cb_msb, dest, cpu_psw_cb_msb, addc, zero); | |
b2167459 | 2872 | |
b2167459 | 2873 | /* Write back the result register. */ |
0c982a28 | 2874 | save_gpr(ctx, a->t, dest); |
b2167459 RH |
2875 | |
2876 | /* Write back PSW[CB]. */ | |
eaa3783b RH |
2877 | tcg_gen_xor_reg(cpu_psw_cb, add1, add2); |
2878 | tcg_gen_xor_reg(cpu_psw_cb, cpu_psw_cb, dest); | |
b2167459 RH |
2879 | |
2880 | /* Write back PSW[V] for the division step. */ | |
72ca8753 RH |
2881 | cout = get_psw_carry(ctx, false); |
2882 | tcg_gen_neg_reg(cpu_psw_v, cout); | |
eaa3783b | 2883 | tcg_gen_xor_reg(cpu_psw_v, cpu_psw_v, in2); |
b2167459 RH |
2884 | |
2885 | /* Install the new nullification. */ | |
0c982a28 | 2886 | if (a->cf) { |
eaa3783b | 2887 | TCGv_reg sv = NULL; |
b47a4a02 | 2888 | if (cond_need_sv(a->cf >> 1)) { |
b2167459 RH |
2889 | /* ??? The lshift is supposed to contribute to overflow. */ |
2890 | sv = do_add_sv(ctx, dest, add1, add2); | |
2891 | } | |
a751eb31 | 2892 | ctx->null_cond = do_cond(ctx, a->cf, false, dest, cout, sv); |
b2167459 RH |
2893 | } |
2894 | ||
31234768 | 2895 | return nullify_end(ctx); |
b2167459 RH |
2896 | } |
2897 | ||
0588e061 | 2898 | static bool trans_addi(DisasContext *ctx, arg_rri_cf *a) |
b2167459 | 2899 | { |
0588e061 RH |
2900 | return do_add_imm(ctx, a, false, false); |
2901 | } | |
b2167459 | 2902 | |
0588e061 RH |
2903 | static bool trans_addi_tsv(DisasContext *ctx, arg_rri_cf *a) |
2904 | { | |
2905 | return do_add_imm(ctx, a, true, false); | |
b2167459 RH |
2906 | } |
2907 | ||
0588e061 | 2908 | static bool trans_addi_tc(DisasContext *ctx, arg_rri_cf *a) |
b2167459 | 2909 | { |
0588e061 RH |
2910 | return do_add_imm(ctx, a, false, true); |
2911 | } | |
b2167459 | 2912 | |
0588e061 RH |
2913 | static bool trans_addi_tc_tsv(DisasContext *ctx, arg_rri_cf *a) |
2914 | { | |
2915 | return do_add_imm(ctx, a, true, true); | |
2916 | } | |
b2167459 | 2917 | |
0588e061 RH |
2918 | static bool trans_subi(DisasContext *ctx, arg_rri_cf *a) |
2919 | { | |
2920 | return do_sub_imm(ctx, a, false); | |
2921 | } | |
b2167459 | 2922 | |
0588e061 RH |
2923 | static bool trans_subi_tsv(DisasContext *ctx, arg_rri_cf *a) |
2924 | { | |
2925 | return do_sub_imm(ctx, a, true); | |
b2167459 RH |
2926 | } |
2927 | ||
0588e061 | 2928 | static bool trans_cmpiclr(DisasContext *ctx, arg_rri_cf *a) |
b2167459 | 2929 | { |
eaa3783b | 2930 | TCGv_reg tcg_im, tcg_r2; |
b2167459 | 2931 | |
0588e061 | 2932 | if (a->cf) { |
b2167459 RH |
2933 | nullify_over(ctx); |
2934 | } | |
2935 | ||
d4e58033 | 2936 | tcg_im = tcg_constant_reg(a->i); |
0588e061 RH |
2937 | tcg_r2 = load_gpr(ctx, a->r); |
2938 | do_cmpclr(ctx, a->t, tcg_im, tcg_r2, a->cf); | |
b2167459 | 2939 | |
31234768 | 2940 | return nullify_end(ctx); |
b2167459 RH |
2941 | } |
2942 | ||
1cd012a5 | 2943 | static bool trans_ld(DisasContext *ctx, arg_ldst *a) |
96d6407f | 2944 | { |
0786a3b6 HD |
2945 | if (unlikely(TARGET_REGISTER_BITS == 32 && a->size > MO_32)) { |
2946 | return gen_illegal(ctx); | |
2947 | } else { | |
2948 | return do_load(ctx, a->t, a->b, a->x, a->scale ? a->size : 0, | |
1cd012a5 | 2949 | a->disp, a->sp, a->m, a->size | MO_TE); |
0786a3b6 | 2950 | } |
96d6407f RH |
2951 | } |
2952 | ||
1cd012a5 | 2953 | static bool trans_st(DisasContext *ctx, arg_ldst *a) |
96d6407f | 2954 | { |
1cd012a5 | 2955 | assert(a->x == 0 && a->scale == 0); |
0786a3b6 HD |
2956 | if (unlikely(TARGET_REGISTER_BITS == 32 && a->size > MO_32)) { |
2957 | return gen_illegal(ctx); | |
2958 | } else { | |
2959 | return do_store(ctx, a->t, a->b, a->disp, a->sp, a->m, a->size | MO_TE); | |
2960 | } | |
96d6407f RH |
2961 | } |
2962 | ||
1cd012a5 | 2963 | static bool trans_ldc(DisasContext *ctx, arg_ldst *a) |
96d6407f | 2964 | { |
b1af755c | 2965 | MemOp mop = MO_TE | MO_ALIGN | a->size; |
86f8d05f RH |
2966 | TCGv_reg zero, dest, ofs; |
2967 | TCGv_tl addr; | |
96d6407f RH |
2968 | |
2969 | nullify_over(ctx); | |
2970 | ||
1cd012a5 | 2971 | if (a->m) { |
86f8d05f RH |
2972 | /* Base register modification. Make sure if RT == RB, |
2973 | we see the result of the load. */ | |
e12c6309 | 2974 | dest = tcg_temp_new(); |
96d6407f | 2975 | } else { |
1cd012a5 | 2976 | dest = dest_gpr(ctx, a->t); |
96d6407f RH |
2977 | } |
2978 | ||
1cd012a5 RH |
2979 | form_gva(ctx, &addr, &ofs, a->b, a->x, a->scale ? a->size : 0, |
2980 | a->disp, a->sp, a->m, ctx->mmu_idx == MMU_PHYS_IDX); | |
b1af755c RH |
2981 | |
2982 | /* | |
2983 | * For hppa1.1, LDCW is undefined unless aligned mod 16. | |
2984 | * However actual hardware succeeds with aligned mod 4. | |
2985 | * Detect this case and log a GUEST_ERROR. | |
2986 | * | |
2987 | * TODO: HPPA64 relaxes the over-alignment requirement | |
2988 | * with the ,co completer. | |
2989 | */ | |
2990 | gen_helper_ldc_check(addr); | |
2991 | ||
29dd6f64 | 2992 | zero = tcg_constant_reg(0); |
86f8d05f | 2993 | tcg_gen_atomic_xchg_reg(dest, addr, zero, ctx->mmu_idx, mop); |
b1af755c | 2994 | |
1cd012a5 RH |
2995 | if (a->m) { |
2996 | save_gpr(ctx, a->b, ofs); | |
96d6407f | 2997 | } |
1cd012a5 | 2998 | save_gpr(ctx, a->t, dest); |
96d6407f | 2999 | |
31234768 | 3000 | return nullify_end(ctx); |
96d6407f RH |
3001 | } |
3002 | ||
1cd012a5 | 3003 | static bool trans_stby(DisasContext *ctx, arg_stby *a) |
96d6407f | 3004 | { |
86f8d05f RH |
3005 | TCGv_reg ofs, val; |
3006 | TCGv_tl addr; | |
96d6407f RH |
3007 | |
3008 | nullify_over(ctx); | |
3009 | ||
1cd012a5 | 3010 | form_gva(ctx, &addr, &ofs, a->b, 0, 0, a->disp, a->sp, a->m, |
86f8d05f | 3011 | ctx->mmu_idx == MMU_PHYS_IDX); |
1cd012a5 RH |
3012 | val = load_gpr(ctx, a->r); |
3013 | if (a->a) { | |
f9f46db4 | 3014 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { |
ad75a51e | 3015 | gen_helper_stby_e_parallel(tcg_env, addr, val); |
f9f46db4 | 3016 | } else { |
ad75a51e | 3017 | gen_helper_stby_e(tcg_env, addr, val); |
f9f46db4 | 3018 | } |
96d6407f | 3019 | } else { |
f9f46db4 | 3020 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { |
ad75a51e | 3021 | gen_helper_stby_b_parallel(tcg_env, addr, val); |
f9f46db4 | 3022 | } else { |
ad75a51e | 3023 | gen_helper_stby_b(tcg_env, addr, val); |
f9f46db4 | 3024 | } |
96d6407f | 3025 | } |
1cd012a5 | 3026 | if (a->m) { |
86f8d05f | 3027 | tcg_gen_andi_reg(ofs, ofs, ~3); |
1cd012a5 | 3028 | save_gpr(ctx, a->b, ofs); |
96d6407f | 3029 | } |
96d6407f | 3030 | |
31234768 | 3031 | return nullify_end(ctx); |
96d6407f RH |
3032 | } |
3033 | ||
1cd012a5 | 3034 | static bool trans_lda(DisasContext *ctx, arg_ldst *a) |
d0a851cc RH |
3035 | { |
3036 | int hold_mmu_idx = ctx->mmu_idx; | |
d0a851cc RH |
3037 | |
3038 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); | |
d0a851cc | 3039 | ctx->mmu_idx = MMU_PHYS_IDX; |
1cd012a5 | 3040 | trans_ld(ctx, a); |
d0a851cc | 3041 | ctx->mmu_idx = hold_mmu_idx; |
31234768 | 3042 | return true; |
d0a851cc RH |
3043 | } |
3044 | ||
1cd012a5 | 3045 | static bool trans_sta(DisasContext *ctx, arg_ldst *a) |
d0a851cc RH |
3046 | { |
3047 | int hold_mmu_idx = ctx->mmu_idx; | |
d0a851cc RH |
3048 | |
3049 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); | |
d0a851cc | 3050 | ctx->mmu_idx = MMU_PHYS_IDX; |
1cd012a5 | 3051 | trans_st(ctx, a); |
d0a851cc | 3052 | ctx->mmu_idx = hold_mmu_idx; |
31234768 | 3053 | return true; |
d0a851cc | 3054 | } |
95412a61 | 3055 | |
0588e061 | 3056 | static bool trans_ldil(DisasContext *ctx, arg_ldil *a) |
b2167459 | 3057 | { |
0588e061 | 3058 | TCGv_reg tcg_rt = dest_gpr(ctx, a->t); |
b2167459 | 3059 | |
0588e061 RH |
3060 | tcg_gen_movi_reg(tcg_rt, a->i); |
3061 | save_gpr(ctx, a->t, tcg_rt); | |
b2167459 | 3062 | cond_free(&ctx->null_cond); |
31234768 | 3063 | return true; |
b2167459 RH |
3064 | } |
3065 | ||
0588e061 | 3066 | static bool trans_addil(DisasContext *ctx, arg_addil *a) |
b2167459 | 3067 | { |
0588e061 | 3068 | TCGv_reg tcg_rt = load_gpr(ctx, a->r); |
eaa3783b | 3069 | TCGv_reg tcg_r1 = dest_gpr(ctx, 1); |
b2167459 | 3070 | |
0588e061 | 3071 | tcg_gen_addi_reg(tcg_r1, tcg_rt, a->i); |
b2167459 RH |
3072 | save_gpr(ctx, 1, tcg_r1); |
3073 | cond_free(&ctx->null_cond); | |
31234768 | 3074 | return true; |
b2167459 RH |
3075 | } |
3076 | ||
0588e061 | 3077 | static bool trans_ldo(DisasContext *ctx, arg_ldo *a) |
b2167459 | 3078 | { |
0588e061 | 3079 | TCGv_reg tcg_rt = dest_gpr(ctx, a->t); |
b2167459 RH |
3080 | |
3081 | /* Special case rb == 0, for the LDI pseudo-op. | |
3082 | The COPY pseudo-op is handled for free within tcg_gen_addi_tl. */ | |
0588e061 RH |
3083 | if (a->b == 0) { |
3084 | tcg_gen_movi_reg(tcg_rt, a->i); | |
b2167459 | 3085 | } else { |
0588e061 | 3086 | tcg_gen_addi_reg(tcg_rt, cpu_gr[a->b], a->i); |
b2167459 | 3087 | } |
0588e061 | 3088 | save_gpr(ctx, a->t, tcg_rt); |
b2167459 | 3089 | cond_free(&ctx->null_cond); |
31234768 | 3090 | return true; |
b2167459 RH |
3091 | } |
3092 | ||
01afb7be RH |
3093 | static bool do_cmpb(DisasContext *ctx, unsigned r, TCGv_reg in1, |
3094 | unsigned c, unsigned f, unsigned n, int disp) | |
98cd9ca7 | 3095 | { |
01afb7be | 3096 | TCGv_reg dest, in2, sv; |
98cd9ca7 | 3097 | DisasCond cond; |
4fe9533a | 3098 | bool d = false; |
98cd9ca7 | 3099 | |
98cd9ca7 | 3100 | in2 = load_gpr(ctx, r); |
e12c6309 | 3101 | dest = tcg_temp_new(); |
98cd9ca7 | 3102 | |
eaa3783b | 3103 | tcg_gen_sub_reg(dest, in1, in2); |
98cd9ca7 | 3104 | |
f764718d | 3105 | sv = NULL; |
b47a4a02 | 3106 | if (cond_need_sv(c)) { |
98cd9ca7 RH |
3107 | sv = do_sub_sv(ctx, dest, in1, in2); |
3108 | } | |
3109 | ||
4fe9533a | 3110 | cond = do_sub_cond(ctx, c * 2 + f, d, dest, in1, in2, sv); |
01afb7be | 3111 | return do_cbranch(ctx, disp, n, &cond); |
98cd9ca7 RH |
3112 | } |
3113 | ||
01afb7be | 3114 | static bool trans_cmpb(DisasContext *ctx, arg_cmpb *a) |
98cd9ca7 | 3115 | { |
01afb7be RH |
3116 | nullify_over(ctx); |
3117 | return do_cmpb(ctx, a->r2, load_gpr(ctx, a->r1), a->c, a->f, a->n, a->disp); | |
3118 | } | |
98cd9ca7 | 3119 | |
01afb7be RH |
3120 | static bool trans_cmpbi(DisasContext *ctx, arg_cmpbi *a) |
3121 | { | |
98cd9ca7 | 3122 | nullify_over(ctx); |
d4e58033 | 3123 | return do_cmpb(ctx, a->r, tcg_constant_reg(a->i), a->c, a->f, a->n, a->disp); |
01afb7be RH |
3124 | } |
3125 | ||
3126 | static bool do_addb(DisasContext *ctx, unsigned r, TCGv_reg in1, | |
3127 | unsigned c, unsigned f, unsigned n, int disp) | |
3128 | { | |
bdcccc17 | 3129 | TCGv_reg dest, in2, sv, cb_cond; |
01afb7be | 3130 | DisasCond cond; |
bdcccc17 | 3131 | bool d = false; |
98cd9ca7 | 3132 | |
98cd9ca7 | 3133 | in2 = load_gpr(ctx, r); |
43675d20 | 3134 | dest = tcg_temp_new(); |
f764718d | 3135 | sv = NULL; |
bdcccc17 | 3136 | cb_cond = NULL; |
98cd9ca7 | 3137 | |
b47a4a02 | 3138 | if (cond_need_cb(c)) { |
bdcccc17 RH |
3139 | TCGv_reg cb = tcg_temp_new(); |
3140 | TCGv_reg cb_msb = tcg_temp_new(); | |
3141 | ||
eaa3783b RH |
3142 | tcg_gen_movi_reg(cb_msb, 0); |
3143 | tcg_gen_add2_reg(dest, cb_msb, in1, cb_msb, in2, cb_msb); | |
bdcccc17 RH |
3144 | tcg_gen_xor_reg(cb, in1, in2); |
3145 | tcg_gen_xor_reg(cb, cb, dest); | |
3146 | cb_cond = get_carry(ctx, d, cb, cb_msb); | |
b47a4a02 | 3147 | } else { |
eaa3783b | 3148 | tcg_gen_add_reg(dest, in1, in2); |
b47a4a02 SS |
3149 | } |
3150 | if (cond_need_sv(c)) { | |
98cd9ca7 | 3151 | sv = do_add_sv(ctx, dest, in1, in2); |
98cd9ca7 RH |
3152 | } |
3153 | ||
a751eb31 | 3154 | cond = do_cond(ctx, c * 2 + f, d, dest, cb_cond, sv); |
43675d20 | 3155 | save_gpr(ctx, r, dest); |
01afb7be | 3156 | return do_cbranch(ctx, disp, n, &cond); |
98cd9ca7 RH |
3157 | } |
3158 | ||
01afb7be RH |
3159 | static bool trans_addb(DisasContext *ctx, arg_addb *a) |
3160 | { | |
3161 | nullify_over(ctx); | |
3162 | return do_addb(ctx, a->r2, load_gpr(ctx, a->r1), a->c, a->f, a->n, a->disp); | |
3163 | } | |
3164 | ||
3165 | static bool trans_addbi(DisasContext *ctx, arg_addbi *a) | |
3166 | { | |
3167 | nullify_over(ctx); | |
d4e58033 | 3168 | return do_addb(ctx, a->r, tcg_constant_reg(a->i), a->c, a->f, a->n, a->disp); |
01afb7be RH |
3169 | } |
3170 | ||
3171 | static bool trans_bb_sar(DisasContext *ctx, arg_bb_sar *a) | |
98cd9ca7 | 3172 | { |
eaa3783b | 3173 | TCGv_reg tmp, tcg_r; |
98cd9ca7 | 3174 | DisasCond cond; |
1e9ab9fb | 3175 | bool d = false; |
98cd9ca7 RH |
3176 | |
3177 | nullify_over(ctx); | |
3178 | ||
3179 | tmp = tcg_temp_new(); | |
01afb7be | 3180 | tcg_r = load_gpr(ctx, a->r); |
1e9ab9fb RH |
3181 | if (cond_need_ext(ctx, d)) { |
3182 | /* Force shift into [32,63] */ | |
3183 | tcg_gen_ori_reg(tmp, cpu_sar, 32); | |
3184 | tcg_gen_shl_reg(tmp, tcg_r, tmp); | |
3185 | } else { | |
3186 | tcg_gen_shl_reg(tmp, tcg_r, cpu_sar); | |
3187 | } | |
98cd9ca7 | 3188 | |
1e9ab9fb | 3189 | cond = cond_make_0_tmp(a->c ? TCG_COND_GE : TCG_COND_LT, tmp); |
01afb7be | 3190 | return do_cbranch(ctx, a->disp, a->n, &cond); |
98cd9ca7 RH |
3191 | } |
3192 | ||
01afb7be RH |
3193 | static bool trans_bb_imm(DisasContext *ctx, arg_bb_imm *a) |
3194 | { | |
3195 | TCGv_reg tmp, tcg_r; | |
3196 | DisasCond cond; | |
1e9ab9fb RH |
3197 | bool d = false; |
3198 | int p; | |
01afb7be RH |
3199 | |
3200 | nullify_over(ctx); | |
3201 | ||
3202 | tmp = tcg_temp_new(); | |
3203 | tcg_r = load_gpr(ctx, a->r); | |
1e9ab9fb RH |
3204 | p = a->p | (cond_need_ext(ctx, d) ? 32 : 0); |
3205 | tcg_gen_shli_reg(tmp, tcg_r, p); | |
01afb7be RH |
3206 | |
3207 | cond = cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp); | |
01afb7be RH |
3208 | return do_cbranch(ctx, a->disp, a->n, &cond); |
3209 | } | |
3210 | ||
3211 | static bool trans_movb(DisasContext *ctx, arg_movb *a) | |
98cd9ca7 | 3212 | { |
eaa3783b | 3213 | TCGv_reg dest; |
98cd9ca7 RH |
3214 | DisasCond cond; |
3215 | ||
3216 | nullify_over(ctx); | |
3217 | ||
01afb7be RH |
3218 | dest = dest_gpr(ctx, a->r2); |
3219 | if (a->r1 == 0) { | |
eaa3783b | 3220 | tcg_gen_movi_reg(dest, 0); |
98cd9ca7 | 3221 | } else { |
01afb7be | 3222 | tcg_gen_mov_reg(dest, cpu_gr[a->r1]); |
98cd9ca7 RH |
3223 | } |
3224 | ||
4fa52edf RH |
3225 | /* All MOVB conditions are 32-bit. */ |
3226 | cond = do_sed_cond(ctx, a->c, false, dest); | |
01afb7be RH |
3227 | return do_cbranch(ctx, a->disp, a->n, &cond); |
3228 | } | |
3229 | ||
3230 | static bool trans_movbi(DisasContext *ctx, arg_movbi *a) | |
3231 | { | |
3232 | TCGv_reg dest; | |
3233 | DisasCond cond; | |
3234 | ||
3235 | nullify_over(ctx); | |
3236 | ||
3237 | dest = dest_gpr(ctx, a->r); | |
3238 | tcg_gen_movi_reg(dest, a->i); | |
3239 | ||
4fa52edf RH |
3240 | /* All MOVBI conditions are 32-bit. */ |
3241 | cond = do_sed_cond(ctx, a->c, false, dest); | |
01afb7be | 3242 | return do_cbranch(ctx, a->disp, a->n, &cond); |
98cd9ca7 RH |
3243 | } |
3244 | ||
30878590 | 3245 | static bool trans_shrpw_sar(DisasContext *ctx, arg_shrpw_sar *a) |
0b1347d2 | 3246 | { |
eaa3783b | 3247 | TCGv_reg dest; |
0b1347d2 | 3248 | |
30878590 | 3249 | if (a->c) { |
0b1347d2 RH |
3250 | nullify_over(ctx); |
3251 | } | |
3252 | ||
30878590 RH |
3253 | dest = dest_gpr(ctx, a->t); |
3254 | if (a->r1 == 0) { | |
3255 | tcg_gen_ext32u_reg(dest, load_gpr(ctx, a->r2)); | |
eaa3783b | 3256 | tcg_gen_shr_reg(dest, dest, cpu_sar); |
30878590 | 3257 | } else if (a->r1 == a->r2) { |
0b1347d2 | 3258 | TCGv_i32 t32 = tcg_temp_new_i32(); |
e1d635e8 RH |
3259 | TCGv_i32 s32 = tcg_temp_new_i32(); |
3260 | ||
30878590 | 3261 | tcg_gen_trunc_reg_i32(t32, load_gpr(ctx, a->r2)); |
e1d635e8 RH |
3262 | tcg_gen_trunc_reg_i32(s32, cpu_sar); |
3263 | tcg_gen_rotr_i32(t32, t32, s32); | |
eaa3783b | 3264 | tcg_gen_extu_i32_reg(dest, t32); |
0b1347d2 RH |
3265 | } else { |
3266 | TCGv_i64 t = tcg_temp_new_i64(); | |
3267 | TCGv_i64 s = tcg_temp_new_i64(); | |
3268 | ||
30878590 | 3269 | tcg_gen_concat_reg_i64(t, load_gpr(ctx, a->r2), load_gpr(ctx, a->r1)); |
eaa3783b | 3270 | tcg_gen_extu_reg_i64(s, cpu_sar); |
0b1347d2 | 3271 | tcg_gen_shr_i64(t, t, s); |
eaa3783b | 3272 | tcg_gen_trunc_i64_reg(dest, t); |
0b1347d2 | 3273 | } |
30878590 | 3274 | save_gpr(ctx, a->t, dest); |
0b1347d2 RH |
3275 | |
3276 | /* Install the new nullification. */ | |
3277 | cond_free(&ctx->null_cond); | |
30878590 | 3278 | if (a->c) { |
4fa52edf | 3279 | ctx->null_cond = do_sed_cond(ctx, a->c, false, dest); |
0b1347d2 | 3280 | } |
31234768 | 3281 | return nullify_end(ctx); |
0b1347d2 RH |
3282 | } |
3283 | ||
30878590 | 3284 | static bool trans_shrpw_imm(DisasContext *ctx, arg_shrpw_imm *a) |
0b1347d2 | 3285 | { |
30878590 | 3286 | unsigned sa = 31 - a->cpos; |
eaa3783b | 3287 | TCGv_reg dest, t2; |
0b1347d2 | 3288 | |
30878590 | 3289 | if (a->c) { |
0b1347d2 RH |
3290 | nullify_over(ctx); |
3291 | } | |
3292 | ||
30878590 RH |
3293 | dest = dest_gpr(ctx, a->t); |
3294 | t2 = load_gpr(ctx, a->r2); | |
05bfd4db RH |
3295 | if (a->r1 == 0) { |
3296 | tcg_gen_extract_reg(dest, t2, sa, 32 - sa); | |
3297 | } else if (TARGET_REGISTER_BITS == 32) { | |
3298 | tcg_gen_extract2_reg(dest, t2, cpu_gr[a->r1], sa); | |
3299 | } else if (a->r1 == a->r2) { | |
0b1347d2 | 3300 | TCGv_i32 t32 = tcg_temp_new_i32(); |
eaa3783b | 3301 | tcg_gen_trunc_reg_i32(t32, t2); |
0b1347d2 | 3302 | tcg_gen_rotri_i32(t32, t32, sa); |
eaa3783b | 3303 | tcg_gen_extu_i32_reg(dest, t32); |
0b1347d2 | 3304 | } else { |
05bfd4db RH |
3305 | TCGv_i64 t64 = tcg_temp_new_i64(); |
3306 | tcg_gen_concat_reg_i64(t64, t2, cpu_gr[a->r1]); | |
3307 | tcg_gen_shri_i64(t64, t64, sa); | |
3308 | tcg_gen_trunc_i64_reg(dest, t64); | |
0b1347d2 | 3309 | } |
30878590 | 3310 | save_gpr(ctx, a->t, dest); |
0b1347d2 RH |
3311 | |
3312 | /* Install the new nullification. */ | |
3313 | cond_free(&ctx->null_cond); | |
30878590 | 3314 | if (a->c) { |
4fa52edf | 3315 | ctx->null_cond = do_sed_cond(ctx, a->c, false, dest); |
0b1347d2 | 3316 | } |
31234768 | 3317 | return nullify_end(ctx); |
0b1347d2 RH |
3318 | } |
3319 | ||
30878590 | 3320 | static bool trans_extrw_sar(DisasContext *ctx, arg_extrw_sar *a) |
0b1347d2 | 3321 | { |
30878590 | 3322 | unsigned len = 32 - a->clen; |
eaa3783b | 3323 | TCGv_reg dest, src, tmp; |
0b1347d2 | 3324 | |
30878590 | 3325 | if (a->c) { |
0b1347d2 RH |
3326 | nullify_over(ctx); |
3327 | } | |
3328 | ||
30878590 RH |
3329 | dest = dest_gpr(ctx, a->t); |
3330 | src = load_gpr(ctx, a->r); | |
0b1347d2 RH |
3331 | tmp = tcg_temp_new(); |
3332 | ||
3333 | /* Recall that SAR is using big-endian bit numbering. */ | |
d781cb77 RH |
3334 | tcg_gen_andi_reg(tmp, cpu_sar, 31); |
3335 | tcg_gen_xori_reg(tmp, tmp, 31); | |
3336 | ||
30878590 | 3337 | if (a->se) { |
eaa3783b RH |
3338 | tcg_gen_sar_reg(dest, src, tmp); |
3339 | tcg_gen_sextract_reg(dest, dest, 0, len); | |
0b1347d2 | 3340 | } else { |
eaa3783b RH |
3341 | tcg_gen_shr_reg(dest, src, tmp); |
3342 | tcg_gen_extract_reg(dest, dest, 0, len); | |
0b1347d2 | 3343 | } |
30878590 | 3344 | save_gpr(ctx, a->t, dest); |
0b1347d2 RH |
3345 | |
3346 | /* Install the new nullification. */ | |
3347 | cond_free(&ctx->null_cond); | |
30878590 | 3348 | if (a->c) { |
4fa52edf | 3349 | ctx->null_cond = do_sed_cond(ctx, a->c, false, dest); |
0b1347d2 | 3350 | } |
31234768 | 3351 | return nullify_end(ctx); |
0b1347d2 RH |
3352 | } |
3353 | ||
30878590 | 3354 | static bool trans_extrw_imm(DisasContext *ctx, arg_extrw_imm *a) |
0b1347d2 | 3355 | { |
30878590 RH |
3356 | unsigned len = 32 - a->clen; |
3357 | unsigned cpos = 31 - a->pos; | |
eaa3783b | 3358 | TCGv_reg dest, src; |
0b1347d2 | 3359 | |
30878590 | 3360 | if (a->c) { |
0b1347d2 RH |
3361 | nullify_over(ctx); |
3362 | } | |
3363 | ||
30878590 RH |
3364 | dest = dest_gpr(ctx, a->t); |
3365 | src = load_gpr(ctx, a->r); | |
3366 | if (a->se) { | |
eaa3783b | 3367 | tcg_gen_sextract_reg(dest, src, cpos, len); |
0b1347d2 | 3368 | } else { |
eaa3783b | 3369 | tcg_gen_extract_reg(dest, src, cpos, len); |
0b1347d2 | 3370 | } |
30878590 | 3371 | save_gpr(ctx, a->t, dest); |
0b1347d2 RH |
3372 | |
3373 | /* Install the new nullification. */ | |
3374 | cond_free(&ctx->null_cond); | |
30878590 | 3375 | if (a->c) { |
4fa52edf | 3376 | ctx->null_cond = do_sed_cond(ctx, a->c, false, dest); |
0b1347d2 | 3377 | } |
31234768 | 3378 | return nullify_end(ctx); |
0b1347d2 RH |
3379 | } |
3380 | ||
30878590 | 3381 | static bool trans_depwi_imm(DisasContext *ctx, arg_depwi_imm *a) |
0b1347d2 | 3382 | { |
30878590 | 3383 | unsigned len = 32 - a->clen; |
eaa3783b RH |
3384 | target_sreg mask0, mask1; |
3385 | TCGv_reg dest; | |
0b1347d2 | 3386 | |
30878590 | 3387 | if (a->c) { |
0b1347d2 RH |
3388 | nullify_over(ctx); |
3389 | } | |
30878590 RH |
3390 | if (a->cpos + len > 32) { |
3391 | len = 32 - a->cpos; | |
0b1347d2 RH |
3392 | } |
3393 | ||
30878590 RH |
3394 | dest = dest_gpr(ctx, a->t); |
3395 | mask0 = deposit64(0, a->cpos, len, a->i); | |
3396 | mask1 = deposit64(-1, a->cpos, len, a->i); | |
0b1347d2 | 3397 | |
30878590 RH |
3398 | if (a->nz) { |
3399 | TCGv_reg src = load_gpr(ctx, a->t); | |
0b1347d2 | 3400 | if (mask1 != -1) { |
eaa3783b | 3401 | tcg_gen_andi_reg(dest, src, mask1); |
0b1347d2 RH |
3402 | src = dest; |
3403 | } | |
eaa3783b | 3404 | tcg_gen_ori_reg(dest, src, mask0); |
0b1347d2 | 3405 | } else { |
eaa3783b | 3406 | tcg_gen_movi_reg(dest, mask0); |
0b1347d2 | 3407 | } |
30878590 | 3408 | save_gpr(ctx, a->t, dest); |
0b1347d2 RH |
3409 | |
3410 | /* Install the new nullification. */ | |
3411 | cond_free(&ctx->null_cond); | |
30878590 | 3412 | if (a->c) { |
4fa52edf | 3413 | ctx->null_cond = do_sed_cond(ctx, a->c, false, dest); |
0b1347d2 | 3414 | } |
31234768 | 3415 | return nullify_end(ctx); |
0b1347d2 RH |
3416 | } |
3417 | ||
30878590 | 3418 | static bool trans_depw_imm(DisasContext *ctx, arg_depw_imm *a) |
0b1347d2 | 3419 | { |
30878590 RH |
3420 | unsigned rs = a->nz ? a->t : 0; |
3421 | unsigned len = 32 - a->clen; | |
eaa3783b | 3422 | TCGv_reg dest, val; |
0b1347d2 | 3423 | |
30878590 | 3424 | if (a->c) { |
0b1347d2 RH |
3425 | nullify_over(ctx); |
3426 | } | |
30878590 RH |
3427 | if (a->cpos + len > 32) { |
3428 | len = 32 - a->cpos; | |
0b1347d2 RH |
3429 | } |
3430 | ||
30878590 RH |
3431 | dest = dest_gpr(ctx, a->t); |
3432 | val = load_gpr(ctx, a->r); | |
0b1347d2 | 3433 | if (rs == 0) { |
30878590 | 3434 | tcg_gen_deposit_z_reg(dest, val, a->cpos, len); |
0b1347d2 | 3435 | } else { |
30878590 | 3436 | tcg_gen_deposit_reg(dest, cpu_gr[rs], val, a->cpos, len); |
0b1347d2 | 3437 | } |
30878590 | 3438 | save_gpr(ctx, a->t, dest); |
0b1347d2 RH |
3439 | |
3440 | /* Install the new nullification. */ | |
3441 | cond_free(&ctx->null_cond); | |
30878590 | 3442 | if (a->c) { |
4fa52edf | 3443 | ctx->null_cond = do_sed_cond(ctx, a->c, false, dest); |
0b1347d2 | 3444 | } |
31234768 | 3445 | return nullify_end(ctx); |
0b1347d2 RH |
3446 | } |
3447 | ||
30878590 RH |
3448 | static bool do_depw_sar(DisasContext *ctx, unsigned rt, unsigned c, |
3449 | unsigned nz, unsigned clen, TCGv_reg val) | |
0b1347d2 | 3450 | { |
0b1347d2 RH |
3451 | unsigned rs = nz ? rt : 0; |
3452 | unsigned len = 32 - clen; | |
30878590 | 3453 | TCGv_reg mask, tmp, shift, dest; |
0b1347d2 RH |
3454 | unsigned msb = 1U << (len - 1); |
3455 | ||
0b1347d2 RH |
3456 | dest = dest_gpr(ctx, rt); |
3457 | shift = tcg_temp_new(); | |
3458 | tmp = tcg_temp_new(); | |
3459 | ||
3460 | /* Convert big-endian bit numbering in SAR to left-shift. */ | |
d781cb77 RH |
3461 | tcg_gen_andi_reg(shift, cpu_sar, 31); |
3462 | tcg_gen_xori_reg(shift, shift, 31); | |
0b1347d2 | 3463 | |
0992a930 RH |
3464 | mask = tcg_temp_new(); |
3465 | tcg_gen_movi_reg(mask, msb + (msb - 1)); | |
eaa3783b | 3466 | tcg_gen_and_reg(tmp, val, mask); |
0b1347d2 | 3467 | if (rs) { |
eaa3783b RH |
3468 | tcg_gen_shl_reg(mask, mask, shift); |
3469 | tcg_gen_shl_reg(tmp, tmp, shift); | |
3470 | tcg_gen_andc_reg(dest, cpu_gr[rs], mask); | |
3471 | tcg_gen_or_reg(dest, dest, tmp); | |
0b1347d2 | 3472 | } else { |
eaa3783b | 3473 | tcg_gen_shl_reg(dest, tmp, shift); |
0b1347d2 | 3474 | } |
0b1347d2 RH |
3475 | save_gpr(ctx, rt, dest); |
3476 | ||
3477 | /* Install the new nullification. */ | |
3478 | cond_free(&ctx->null_cond); | |
3479 | if (c) { | |
4fa52edf | 3480 | ctx->null_cond = do_sed_cond(ctx, c, false, dest); |
0b1347d2 | 3481 | } |
31234768 | 3482 | return nullify_end(ctx); |
0b1347d2 RH |
3483 | } |
3484 | ||
30878590 RH |
3485 | static bool trans_depw_sar(DisasContext *ctx, arg_depw_sar *a) |
3486 | { | |
a6deecce SS |
3487 | if (a->c) { |
3488 | nullify_over(ctx); | |
3489 | } | |
30878590 RH |
3490 | return do_depw_sar(ctx, a->t, a->c, a->nz, a->clen, load_gpr(ctx, a->r)); |
3491 | } | |
3492 | ||
3493 | static bool trans_depwi_sar(DisasContext *ctx, arg_depwi_sar *a) | |
3494 | { | |
a6deecce SS |
3495 | if (a->c) { |
3496 | nullify_over(ctx); | |
3497 | } | |
d4e58033 | 3498 | return do_depw_sar(ctx, a->t, a->c, a->nz, a->clen, tcg_constant_reg(a->i)); |
30878590 | 3499 | } |
0b1347d2 | 3500 | |
8340f534 | 3501 | static bool trans_be(DisasContext *ctx, arg_be *a) |
98cd9ca7 | 3502 | { |
660eefe1 | 3503 | TCGv_reg tmp; |
98cd9ca7 | 3504 | |
c301f34e | 3505 | #ifdef CONFIG_USER_ONLY |
98cd9ca7 RH |
3506 | /* ??? It seems like there should be a good way of using |
3507 | "be disp(sr2, r0)", the canonical gateway entry mechanism | |
3508 | to our advantage. But that appears to be inconvenient to | |
3509 | manage along side branch delay slots. Therefore we handle | |
3510 | entry into the gateway page via absolute address. */ | |
98cd9ca7 RH |
3511 | /* Since we don't implement spaces, just branch. Do notice the special |
3512 | case of "be disp(*,r0)" using a direct branch to disp, so that we can | |
3513 | goto_tb to the TB containing the syscall. */ | |
8340f534 RH |
3514 | if (a->b == 0) { |
3515 | return do_dbranch(ctx, a->disp, a->l, a->n); | |
98cd9ca7 | 3516 | } |
c301f34e | 3517 | #else |
c301f34e | 3518 | nullify_over(ctx); |
660eefe1 RH |
3519 | #endif |
3520 | ||
e12c6309 | 3521 | tmp = tcg_temp_new(); |
8340f534 | 3522 | tcg_gen_addi_reg(tmp, load_gpr(ctx, a->b), a->disp); |
660eefe1 | 3523 | tmp = do_ibranch_priv(ctx, tmp); |
c301f34e RH |
3524 | |
3525 | #ifdef CONFIG_USER_ONLY | |
8340f534 | 3526 | return do_ibranch(ctx, tmp, a->l, a->n); |
c301f34e RH |
3527 | #else |
3528 | TCGv_i64 new_spc = tcg_temp_new_i64(); | |
3529 | ||
8340f534 RH |
3530 | load_spr(ctx, new_spc, a->sp); |
3531 | if (a->l) { | |
741322f4 | 3532 | copy_iaoq_entry(ctx, cpu_gr[31], ctx->iaoq_n, ctx->iaoq_n_var); |
c301f34e RH |
3533 | tcg_gen_mov_i64(cpu_sr[0], cpu_iasq_f); |
3534 | } | |
8340f534 | 3535 | if (a->n && use_nullify_skip(ctx)) { |
a0180973 RH |
3536 | copy_iaoq_entry(ctx, cpu_iaoq_f, -1, tmp); |
3537 | tcg_gen_addi_reg(tmp, tmp, 4); | |
3538 | copy_iaoq_entry(ctx, cpu_iaoq_b, -1, tmp); | |
c301f34e RH |
3539 | tcg_gen_mov_i64(cpu_iasq_f, new_spc); |
3540 | tcg_gen_mov_i64(cpu_iasq_b, cpu_iasq_f); | |
3541 | } else { | |
741322f4 | 3542 | copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); |
c301f34e RH |
3543 | if (ctx->iaoq_b == -1) { |
3544 | tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); | |
3545 | } | |
a0180973 | 3546 | copy_iaoq_entry(ctx, cpu_iaoq_b, -1, tmp); |
c301f34e | 3547 | tcg_gen_mov_i64(cpu_iasq_b, new_spc); |
8340f534 | 3548 | nullify_set(ctx, a->n); |
c301f34e | 3549 | } |
c301f34e | 3550 | tcg_gen_lookup_and_goto_ptr(); |
31234768 RH |
3551 | ctx->base.is_jmp = DISAS_NORETURN; |
3552 | return nullify_end(ctx); | |
c301f34e | 3553 | #endif |
98cd9ca7 RH |
3554 | } |
3555 | ||
8340f534 | 3556 | static bool trans_bl(DisasContext *ctx, arg_bl *a) |
98cd9ca7 | 3557 | { |
8340f534 | 3558 | return do_dbranch(ctx, iaoq_dest(ctx, a->disp), a->l, a->n); |
98cd9ca7 RH |
3559 | } |
3560 | ||
8340f534 | 3561 | static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) |
43e05652 | 3562 | { |
8340f534 | 3563 | target_ureg dest = iaoq_dest(ctx, a->disp); |
43e05652 | 3564 | |
6e5f5300 SS |
3565 | nullify_over(ctx); |
3566 | ||
43e05652 RH |
3567 | /* Make sure the caller hasn't done something weird with the queue. |
3568 | * ??? This is not quite the same as the PSW[B] bit, which would be | |
3569 | * expensive to track. Real hardware will trap for | |
3570 | * b gateway | |
3571 | * b gateway+4 (in delay slot of first branch) | |
3572 | * However, checking for a non-sequential instruction queue *will* | |
3573 | * diagnose the security hole | |
3574 | * b gateway | |
3575 | * b evil | |
3576 | * in which instructions at evil would run with increased privs. | |
3577 | */ | |
3578 | if (ctx->iaoq_b == -1 || ctx->iaoq_b != ctx->iaoq_f + 4) { | |
3579 | return gen_illegal(ctx); | |
3580 | } | |
3581 | ||
3582 | #ifndef CONFIG_USER_ONLY | |
3583 | if (ctx->tb_flags & PSW_C) { | |
b77af26e | 3584 | CPUHPPAState *env = cpu_env(ctx->cs); |
43e05652 RH |
3585 | int type = hppa_artype_for_page(env, ctx->base.pc_next); |
3586 | /* If we could not find a TLB entry, then we need to generate an | |
3587 | ITLB miss exception so the kernel will provide it. | |
3588 | The resulting TLB fill operation will invalidate this TB and | |
3589 | we will re-translate, at which point we *will* be able to find | |
3590 | the TLB entry and determine if this is in fact a gateway page. */ | |
3591 | if (type < 0) { | |
31234768 RH |
3592 | gen_excp(ctx, EXCP_ITLB_MISS); |
3593 | return true; | |
43e05652 RH |
3594 | } |
3595 | /* No change for non-gateway pages or for priv decrease. */ | |
3596 | if (type >= 4 && type - 4 < ctx->privilege) { | |
3597 | dest = deposit32(dest, 0, 2, type - 4); | |
3598 | } | |
3599 | } else { | |
3600 | dest &= -4; /* priv = 0 */ | |
3601 | } | |
3602 | #endif | |
3603 | ||
6e5f5300 SS |
3604 | if (a->l) { |
3605 | TCGv_reg tmp = dest_gpr(ctx, a->l); | |
3606 | if (ctx->privilege < 3) { | |
3607 | tcg_gen_andi_reg(tmp, tmp, -4); | |
3608 | } | |
3609 | tcg_gen_ori_reg(tmp, tmp, ctx->privilege); | |
3610 | save_gpr(ctx, a->l, tmp); | |
3611 | } | |
3612 | ||
3613 | return do_dbranch(ctx, dest, 0, a->n); | |
43e05652 RH |
3614 | } |
3615 | ||
8340f534 | 3616 | static bool trans_blr(DisasContext *ctx, arg_blr *a) |
98cd9ca7 | 3617 | { |
b35aec85 | 3618 | if (a->x) { |
e12c6309 | 3619 | TCGv_reg tmp = tcg_temp_new(); |
b35aec85 RH |
3620 | tcg_gen_shli_reg(tmp, load_gpr(ctx, a->x), 3); |
3621 | tcg_gen_addi_reg(tmp, tmp, ctx->iaoq_f + 8); | |
3622 | /* The computation here never changes privilege level. */ | |
3623 | return do_ibranch(ctx, tmp, a->l, a->n); | |
3624 | } else { | |
3625 | /* BLR R0,RX is a good way to load PC+8 into RX. */ | |
3626 | return do_dbranch(ctx, ctx->iaoq_f + 8, a->l, a->n); | |
3627 | } | |
98cd9ca7 RH |
3628 | } |
3629 | ||
8340f534 | 3630 | static bool trans_bv(DisasContext *ctx, arg_bv *a) |
98cd9ca7 | 3631 | { |
eaa3783b | 3632 | TCGv_reg dest; |
98cd9ca7 | 3633 | |
8340f534 RH |
3634 | if (a->x == 0) { |
3635 | dest = load_gpr(ctx, a->b); | |
98cd9ca7 | 3636 | } else { |
e12c6309 | 3637 | dest = tcg_temp_new(); |
8340f534 RH |
3638 | tcg_gen_shli_reg(dest, load_gpr(ctx, a->x), 3); |
3639 | tcg_gen_add_reg(dest, dest, load_gpr(ctx, a->b)); | |
98cd9ca7 | 3640 | } |
660eefe1 | 3641 | dest = do_ibranch_priv(ctx, dest); |
8340f534 | 3642 | return do_ibranch(ctx, dest, 0, a->n); |
98cd9ca7 RH |
3643 | } |
3644 | ||
8340f534 | 3645 | static bool trans_bve(DisasContext *ctx, arg_bve *a) |
98cd9ca7 | 3646 | { |
660eefe1 | 3647 | TCGv_reg dest; |
98cd9ca7 | 3648 | |
c301f34e | 3649 | #ifdef CONFIG_USER_ONLY |
8340f534 RH |
3650 | dest = do_ibranch_priv(ctx, load_gpr(ctx, a->b)); |
3651 | return do_ibranch(ctx, dest, a->l, a->n); | |
c301f34e RH |
3652 | #else |
3653 | nullify_over(ctx); | |
8340f534 | 3654 | dest = do_ibranch_priv(ctx, load_gpr(ctx, a->b)); |
c301f34e | 3655 | |
741322f4 | 3656 | copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); |
c301f34e RH |
3657 | if (ctx->iaoq_b == -1) { |
3658 | tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); | |
3659 | } | |
741322f4 | 3660 | copy_iaoq_entry(ctx, cpu_iaoq_b, -1, dest); |
c301f34e | 3661 | tcg_gen_mov_i64(cpu_iasq_b, space_select(ctx, 0, dest)); |
8340f534 | 3662 | if (a->l) { |
741322f4 | 3663 | copy_iaoq_entry(ctx, cpu_gr[a->l], ctx->iaoq_n, ctx->iaoq_n_var); |
c301f34e | 3664 | } |
8340f534 | 3665 | nullify_set(ctx, a->n); |
c301f34e | 3666 | tcg_gen_lookup_and_goto_ptr(); |
31234768 RH |
3667 | ctx->base.is_jmp = DISAS_NORETURN; |
3668 | return nullify_end(ctx); | |
c301f34e | 3669 | #endif |
98cd9ca7 RH |
3670 | } |
3671 | ||
1ca74648 RH |
3672 | /* |
3673 | * Float class 0 | |
3674 | */ | |
ebe9383c | 3675 | |
1ca74648 | 3676 | static void gen_fcpy_f(TCGv_i32 dst, TCGv_env unused, TCGv_i32 src) |
ebe9383c | 3677 | { |
1ca74648 | 3678 | tcg_gen_mov_i32(dst, src); |
ebe9383c RH |
3679 | } |
3680 | ||
59f8c04b HD |
3681 | static bool trans_fid_f(DisasContext *ctx, arg_fid_f *a) |
3682 | { | |
a300dad3 RH |
3683 | uint64_t ret; |
3684 | ||
3685 | if (TARGET_REGISTER_BITS == 64) { | |
3686 | ret = 0x13080000000000ULL; /* PA8700 (PCX-W2) */ | |
3687 | } else { | |
3688 | ret = 0x0f080000000000ULL; /* PA7300LC (PCX-L2) */ | |
3689 | } | |
3690 | ||
59f8c04b | 3691 | nullify_over(ctx); |
a300dad3 | 3692 | save_frd(0, tcg_constant_i64(ret)); |
59f8c04b HD |
3693 | return nullify_end(ctx); |
3694 | } | |
3695 | ||
1ca74648 | 3696 | static bool trans_fcpy_f(DisasContext *ctx, arg_fclass01 *a) |
ebe9383c | 3697 | { |
1ca74648 | 3698 | return do_fop_wew(ctx, a->t, a->r, gen_fcpy_f); |
ebe9383c RH |
3699 | } |
3700 | ||
1ca74648 | 3701 | static void gen_fcpy_d(TCGv_i64 dst, TCGv_env unused, TCGv_i64 src) |
ebe9383c | 3702 | { |
1ca74648 | 3703 | tcg_gen_mov_i64(dst, src); |
ebe9383c RH |
3704 | } |
3705 | ||
1ca74648 | 3706 | static bool trans_fcpy_d(DisasContext *ctx, arg_fclass01 *a) |
ebe9383c | 3707 | { |
1ca74648 | 3708 | return do_fop_ded(ctx, a->t, a->r, gen_fcpy_d); |
ebe9383c RH |
3709 | } |
3710 | ||
1ca74648 | 3711 | static void gen_fabs_f(TCGv_i32 dst, TCGv_env unused, TCGv_i32 src) |
ebe9383c | 3712 | { |
1ca74648 | 3713 | tcg_gen_andi_i32(dst, src, INT32_MAX); |
ebe9383c RH |
3714 | } |
3715 | ||
1ca74648 | 3716 | static bool trans_fabs_f(DisasContext *ctx, arg_fclass01 *a) |
ebe9383c | 3717 | { |
1ca74648 | 3718 | return do_fop_wew(ctx, a->t, a->r, gen_fabs_f); |
ebe9383c RH |
3719 | } |
3720 | ||
1ca74648 | 3721 | static void gen_fabs_d(TCGv_i64 dst, TCGv_env unused, TCGv_i64 src) |
ebe9383c | 3722 | { |
1ca74648 | 3723 | tcg_gen_andi_i64(dst, src, INT64_MAX); |
ebe9383c RH |
3724 | } |
3725 | ||
1ca74648 | 3726 | static bool trans_fabs_d(DisasContext *ctx, arg_fclass01 *a) |
ebe9383c | 3727 | { |
1ca74648 | 3728 | return do_fop_ded(ctx, a->t, a->r, gen_fabs_d); |
ebe9383c RH |
3729 | } |
3730 | ||
1ca74648 | 3731 | static bool trans_fsqrt_f(DisasContext *ctx, arg_fclass01 *a) |
ebe9383c | 3732 | { |
1ca74648 | 3733 | return do_fop_wew(ctx, a->t, a->r, gen_helper_fsqrt_s); |
ebe9383c RH |
3734 | } |
3735 | ||
1ca74648 | 3736 | static bool trans_fsqrt_d(DisasContext *ctx, arg_fclass01 *a) |
ebe9383c | 3737 | { |
1ca74648 | 3738 | return do_fop_ded(ctx, a->t, a->r, gen_helper_fsqrt_d); |
ebe9383c RH |
3739 | } |
3740 | ||
1ca74648 | 3741 | static bool trans_frnd_f(DisasContext *ctx, arg_fclass01 *a) |
ebe9383c | 3742 | { |
1ca74648 | 3743 | return do_fop_wew(ctx, a->t, a->r, gen_helper_frnd_s); |
ebe9383c RH |
3744 | } |
3745 | ||
1ca74648 | 3746 | static bool trans_frnd_d(DisasContext *ctx, arg_fclass01 *a) |
ebe9383c | 3747 | { |
1ca74648 | 3748 | return do_fop_ded(ctx, a->t, a->r, gen_helper_frnd_d); |
ebe9383c RH |
3749 | } |
3750 | ||
1ca74648 | 3751 | static void gen_fneg_f(TCGv_i32 dst, TCGv_env unused, TCGv_i32 src) |
ebe9383c | 3752 | { |
1ca74648 | 3753 | tcg_gen_xori_i32(dst, src, INT32_MIN); |
ebe9383c RH |
3754 | } |
3755 | ||
1ca74648 | 3756 | static bool trans_fneg_f(DisasContext *ctx, arg_fclass01 *a) |
ebe9383c | 3757 | { |
1ca74648 | 3758 | return do_fop_wew(ctx, a->t, a->r, gen_fneg_f); |
ebe9383c RH |
3759 | } |
3760 | ||
3761 | static void gen_fneg_d(TCGv_i64 dst, TCGv_env unused, TCGv_i64 src) | |
3762 | { | |
3763 | tcg_gen_xori_i64(dst, src, INT64_MIN); | |
3764 | } | |
3765 | ||
1ca74648 RH |
3766 | static bool trans_fneg_d(DisasContext *ctx, arg_fclass01 *a) |
3767 | { | |
3768 | return do_fop_ded(ctx, a->t, a->r, gen_fneg_d); | |
3769 | } | |
3770 | ||
3771 | static void gen_fnegabs_f(TCGv_i32 dst, TCGv_env unused, TCGv_i32 src) | |
ebe9383c RH |
3772 | { |
3773 | tcg_gen_ori_i32(dst, src, INT32_MIN); | |
3774 | } | |
3775 | ||
1ca74648 RH |
3776 | static bool trans_fnegabs_f(DisasContext *ctx, arg_fclass01 *a) |
3777 | { | |
3778 | return do_fop_wew(ctx, a->t, a->r, gen_fnegabs_f); | |
3779 | } | |
3780 | ||
ebe9383c RH |
3781 | static void gen_fnegabs_d(TCGv_i64 dst, TCGv_env unused, TCGv_i64 src) |
3782 | { | |
3783 | tcg_gen_ori_i64(dst, src, INT64_MIN); | |
3784 | } | |
3785 | ||
1ca74648 RH |
3786 | static bool trans_fnegabs_d(DisasContext *ctx, arg_fclass01 *a) |
3787 | { | |
3788 | return do_fop_ded(ctx, a->t, a->r, gen_fnegabs_d); | |
3789 | } | |
3790 | ||
3791 | /* | |
3792 | * Float class 1 | |
3793 | */ | |
3794 | ||
3795 | static bool trans_fcnv_d_f(DisasContext *ctx, arg_fclass01 *a) | |
3796 | { | |
3797 | return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_d_s); | |
3798 | } | |
3799 | ||
3800 | static bool trans_fcnv_f_d(DisasContext *ctx, arg_fclass01 *a) | |
3801 | { | |
3802 | return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_s_d); | |
3803 | } | |
3804 | ||
3805 | static bool trans_fcnv_w_f(DisasContext *ctx, arg_fclass01 *a) | |
3806 | { | |
3807 | return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_w_s); | |
3808 | } | |
3809 | ||
3810 | static bool trans_fcnv_q_f(DisasContext *ctx, arg_fclass01 *a) | |
3811 | { | |
3812 | return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_dw_s); | |
3813 | } | |
3814 | ||
3815 | static bool trans_fcnv_w_d(DisasContext *ctx, arg_fclass01 *a) | |
3816 | { | |
3817 | return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_w_d); | |
3818 | } | |
3819 | ||
3820 | static bool trans_fcnv_q_d(DisasContext *ctx, arg_fclass01 *a) | |
3821 | { | |
3822 | return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_dw_d); | |
3823 | } | |
3824 | ||
3825 | static bool trans_fcnv_f_w(DisasContext *ctx, arg_fclass01 *a) | |
3826 | { | |
3827 | return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_s_w); | |
3828 | } | |
3829 | ||
3830 | static bool trans_fcnv_d_w(DisasContext *ctx, arg_fclass01 *a) | |
3831 | { | |
3832 | return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_d_w); | |
3833 | } | |
3834 | ||
3835 | static bool trans_fcnv_f_q(DisasContext *ctx, arg_fclass01 *a) | |
3836 | { | |
3837 | return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_s_dw); | |
3838 | } | |
3839 | ||
3840 | static bool trans_fcnv_d_q(DisasContext *ctx, arg_fclass01 *a) | |
3841 | { | |
3842 | return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_d_dw); | |
3843 | } | |
3844 | ||
3845 | static bool trans_fcnv_t_f_w(DisasContext *ctx, arg_fclass01 *a) | |
3846 | { | |
3847 | return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_t_s_w); | |
3848 | } | |
3849 | ||
3850 | static bool trans_fcnv_t_d_w(DisasContext *ctx, arg_fclass01 *a) | |
3851 | { | |
3852 | return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_t_d_w); | |
3853 | } | |
3854 | ||
3855 | static bool trans_fcnv_t_f_q(DisasContext *ctx, arg_fclass01 *a) | |
3856 | { | |
3857 | return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_t_s_dw); | |
3858 | } | |
3859 | ||
3860 | static bool trans_fcnv_t_d_q(DisasContext *ctx, arg_fclass01 *a) | |
3861 | { | |
3862 | return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_t_d_dw); | |
3863 | } | |
3864 | ||
3865 | static bool trans_fcnv_uw_f(DisasContext *ctx, arg_fclass01 *a) | |
3866 | { | |
3867 | return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_uw_s); | |
3868 | } | |
3869 | ||
3870 | static bool trans_fcnv_uq_f(DisasContext *ctx, arg_fclass01 *a) | |
3871 | { | |
3872 | return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_udw_s); | |
3873 | } | |
3874 | ||
3875 | static bool trans_fcnv_uw_d(DisasContext *ctx, arg_fclass01 *a) | |
3876 | { | |
3877 | return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_uw_d); | |
3878 | } | |
3879 | ||
3880 | static bool trans_fcnv_uq_d(DisasContext *ctx, arg_fclass01 *a) | |
3881 | { | |
3882 | return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_udw_d); | |
3883 | } | |
3884 | ||
3885 | static bool trans_fcnv_f_uw(DisasContext *ctx, arg_fclass01 *a) | |
3886 | { | |
3887 | return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_s_uw); | |
3888 | } | |
3889 | ||
3890 | static bool trans_fcnv_d_uw(DisasContext *ctx, arg_fclass01 *a) | |
3891 | { | |
3892 | return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_d_uw); | |
3893 | } | |
3894 | ||
3895 | static bool trans_fcnv_f_uq(DisasContext *ctx, arg_fclass01 *a) | |
3896 | { | |
3897 | return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_s_udw); | |
3898 | } | |
3899 | ||
3900 | static bool trans_fcnv_d_uq(DisasContext *ctx, arg_fclass01 *a) | |
3901 | { | |
3902 | return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_d_udw); | |
3903 | } | |
3904 | ||
3905 | static bool trans_fcnv_t_f_uw(DisasContext *ctx, arg_fclass01 *a) | |
3906 | { | |
3907 | return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_t_s_uw); | |
3908 | } | |
3909 | ||
3910 | static bool trans_fcnv_t_d_uw(DisasContext *ctx, arg_fclass01 *a) | |
3911 | { | |
3912 | return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_t_d_uw); | |
3913 | } | |
3914 | ||
3915 | static bool trans_fcnv_t_f_uq(DisasContext *ctx, arg_fclass01 *a) | |
3916 | { | |
3917 | return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_t_s_udw); | |
3918 | } | |
3919 | ||
3920 | static bool trans_fcnv_t_d_uq(DisasContext *ctx, arg_fclass01 *a) | |
3921 | { | |
3922 | return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_t_d_udw); | |
3923 | } | |
3924 | ||
3925 | /* | |
3926 | * Float class 2 | |
3927 | */ | |
3928 | ||
3929 | static bool trans_fcmp_f(DisasContext *ctx, arg_fclass2 *a) | |
ebe9383c RH |
3930 | { |
3931 | TCGv_i32 ta, tb, tc, ty; | |
3932 | ||
3933 | nullify_over(ctx); | |
3934 | ||
1ca74648 RH |
3935 | ta = load_frw0_i32(a->r1); |
3936 | tb = load_frw0_i32(a->r2); | |
29dd6f64 RH |
3937 | ty = tcg_constant_i32(a->y); |
3938 | tc = tcg_constant_i32(a->c); | |
ebe9383c | 3939 | |
ad75a51e | 3940 | gen_helper_fcmp_s(tcg_env, ta, tb, ty, tc); |
ebe9383c | 3941 | |
1ca74648 | 3942 | return nullify_end(ctx); |
ebe9383c RH |
3943 | } |
3944 | ||
1ca74648 | 3945 | static bool trans_fcmp_d(DisasContext *ctx, arg_fclass2 *a) |
ebe9383c | 3946 | { |
ebe9383c RH |
3947 | TCGv_i64 ta, tb; |
3948 | TCGv_i32 tc, ty; | |
3949 | ||
3950 | nullify_over(ctx); | |
3951 | ||
1ca74648 RH |
3952 | ta = load_frd0(a->r1); |
3953 | tb = load_frd0(a->r2); | |
29dd6f64 RH |
3954 | ty = tcg_constant_i32(a->y); |
3955 | tc = tcg_constant_i32(a->c); | |
ebe9383c | 3956 | |
ad75a51e | 3957 | gen_helper_fcmp_d(tcg_env, ta, tb, ty, tc); |
ebe9383c | 3958 | |
31234768 | 3959 | return nullify_end(ctx); |
ebe9383c RH |
3960 | } |
3961 | ||
1ca74648 | 3962 | static bool trans_ftest(DisasContext *ctx, arg_ftest *a) |
ebe9383c | 3963 | { |
eaa3783b | 3964 | TCGv_reg t; |
ebe9383c RH |
3965 | |
3966 | nullify_over(ctx); | |
3967 | ||
e12c6309 | 3968 | t = tcg_temp_new(); |
ad75a51e | 3969 | tcg_gen_ld32u_reg(t, tcg_env, offsetof(CPUHPPAState, fr0_shadow)); |
ebe9383c | 3970 | |
1ca74648 RH |
3971 | if (a->y == 1) { |
3972 | int mask; | |
3973 | bool inv = false; | |
3974 | ||
3975 | switch (a->c) { | |
3976 | case 0: /* simple */ | |
3977 | tcg_gen_andi_reg(t, t, 0x4000000); | |
3978 | ctx->null_cond = cond_make_0(TCG_COND_NE, t); | |
3979 | goto done; | |
3980 | case 2: /* rej */ | |
3981 | inv = true; | |
3982 | /* fallthru */ | |
3983 | case 1: /* acc */ | |
3984 | mask = 0x43ff800; | |
3985 | break; | |
3986 | case 6: /* rej8 */ | |
3987 | inv = true; | |
3988 | /* fallthru */ | |
3989 | case 5: /* acc8 */ | |
3990 | mask = 0x43f8000; | |
3991 | break; | |
3992 | case 9: /* acc6 */ | |
3993 | mask = 0x43e0000; | |
3994 | break; | |
3995 | case 13: /* acc4 */ | |
3996 | mask = 0x4380000; | |
3997 | break; | |
3998 | case 17: /* acc2 */ | |
3999 | mask = 0x4200000; | |
4000 | break; | |
4001 | default: | |
4002 | gen_illegal(ctx); | |
4003 | return true; | |
4004 | } | |
4005 | if (inv) { | |
d4e58033 | 4006 | TCGv_reg c = tcg_constant_reg(mask); |
1ca74648 RH |
4007 | tcg_gen_or_reg(t, t, c); |
4008 | ctx->null_cond = cond_make(TCG_COND_EQ, t, c); | |
4009 | } else { | |
4010 | tcg_gen_andi_reg(t, t, mask); | |
4011 | ctx->null_cond = cond_make_0(TCG_COND_EQ, t); | |
4012 | } | |
4013 | } else { | |
4014 | unsigned cbit = (a->y ^ 1) - 1; | |
4015 | ||
4016 | tcg_gen_extract_reg(t, t, 21 - cbit, 1); | |
4017 | ctx->null_cond = cond_make_0(TCG_COND_NE, t); | |
1ca74648 RH |
4018 | } |
4019 | ||
4020 | done: | |
31234768 | 4021 | return nullify_end(ctx); |
ebe9383c RH |
4022 | } |
4023 | ||
1ca74648 RH |
4024 | /* |
4025 | * Float class 2 | |
4026 | */ | |
4027 | ||
4028 | static bool trans_fadd_f(DisasContext *ctx, arg_fclass3 *a) | |
ebe9383c | 4029 | { |
1ca74648 RH |
4030 | return do_fop_weww(ctx, a->t, a->r1, a->r2, gen_helper_fadd_s); |
4031 | } | |
ebe9383c | 4032 | |
1ca74648 RH |
4033 | static bool trans_fadd_d(DisasContext *ctx, arg_fclass3 *a) |
4034 | { | |
4035 | return do_fop_dedd(ctx, a->t, a->r1, a->r2, gen_helper_fadd_d); | |
4036 | } | |
ebe9383c | 4037 | |
1ca74648 RH |
4038 | static bool trans_fsub_f(DisasContext *ctx, arg_fclass3 *a) |
4039 | { | |
4040 | return do_fop_weww(ctx, a->t, a->r1, a->r2, gen_helper_fsub_s); | |
4041 | } | |
ebe9383c | 4042 | |
1ca74648 RH |
4043 | static bool trans_fsub_d(DisasContext *ctx, arg_fclass3 *a) |
4044 | { | |
4045 | return do_fop_dedd(ctx, a->t, a->r1, a->r2, gen_helper_fsub_d); | |
ebe9383c RH |
4046 | } |
4047 | ||
1ca74648 | 4048 | static bool trans_fmpy_f(DisasContext *ctx, arg_fclass3 *a) |
ebe9383c | 4049 | { |
1ca74648 RH |
4050 | return do_fop_weww(ctx, a->t, a->r1, a->r2, gen_helper_fmpy_s); |
4051 | } | |
4052 | ||
4053 | static bool trans_fmpy_d(DisasContext *ctx, arg_fclass3 *a) | |
4054 | { | |
4055 | return do_fop_dedd(ctx, a->t, a->r1, a->r2, gen_helper_fmpy_d); | |
4056 | } | |
4057 | ||
4058 | static bool trans_fdiv_f(DisasContext *ctx, arg_fclass3 *a) | |
4059 | { | |
4060 | return do_fop_weww(ctx, a->t, a->r1, a->r2, gen_helper_fdiv_s); | |
4061 | } | |
4062 | ||
4063 | static bool trans_fdiv_d(DisasContext *ctx, arg_fclass3 *a) | |
4064 | { | |
4065 | return do_fop_dedd(ctx, a->t, a->r1, a->r2, gen_helper_fdiv_d); | |
4066 | } | |
4067 | ||
4068 | static bool trans_xmpyu(DisasContext *ctx, arg_xmpyu *a) | |
4069 | { | |
4070 | TCGv_i64 x, y; | |
ebe9383c RH |
4071 | |
4072 | nullify_over(ctx); | |
4073 | ||
1ca74648 RH |
4074 | x = load_frw0_i64(a->r1); |
4075 | y = load_frw0_i64(a->r2); | |
4076 | tcg_gen_mul_i64(x, x, y); | |
4077 | save_frd(a->t, x); | |
ebe9383c | 4078 | |
31234768 | 4079 | return nullify_end(ctx); |
ebe9383c RH |
4080 | } |
4081 | ||
ebe9383c RH |
4082 | /* Convert the fmpyadd single-precision register encodings to standard. */ |
4083 | static inline int fmpyadd_s_reg(unsigned r) | |
4084 | { | |
4085 | return (r & 16) * 2 + 16 + (r & 15); | |
4086 | } | |
4087 | ||
b1e2af57 | 4088 | static bool do_fmpyadd_s(DisasContext *ctx, arg_mpyadd *a, bool is_sub) |
ebe9383c | 4089 | { |
b1e2af57 RH |
4090 | int tm = fmpyadd_s_reg(a->tm); |
4091 | int ra = fmpyadd_s_reg(a->ra); | |
4092 | int ta = fmpyadd_s_reg(a->ta); | |
4093 | int rm2 = fmpyadd_s_reg(a->rm2); | |
4094 | int rm1 = fmpyadd_s_reg(a->rm1); | |
ebe9383c RH |
4095 | |
4096 | nullify_over(ctx); | |
4097 | ||
b1e2af57 RH |
4098 | do_fop_weww(ctx, tm, rm1, rm2, gen_helper_fmpy_s); |
4099 | do_fop_weww(ctx, ta, ta, ra, | |
4100 | is_sub ? gen_helper_fsub_s : gen_helper_fadd_s); | |
ebe9383c | 4101 | |
31234768 | 4102 | return nullify_end(ctx); |
ebe9383c RH |
4103 | } |
4104 | ||
b1e2af57 RH |
4105 | static bool trans_fmpyadd_f(DisasContext *ctx, arg_mpyadd *a) |
4106 | { | |
4107 | return do_fmpyadd_s(ctx, a, false); | |
4108 | } | |
4109 | ||
4110 | static bool trans_fmpysub_f(DisasContext *ctx, arg_mpyadd *a) | |
4111 | { | |
4112 | return do_fmpyadd_s(ctx, a, true); | |
4113 | } | |
4114 | ||
4115 | static bool do_fmpyadd_d(DisasContext *ctx, arg_mpyadd *a, bool is_sub) | |
4116 | { | |
4117 | nullify_over(ctx); | |
4118 | ||
4119 | do_fop_dedd(ctx, a->tm, a->rm1, a->rm2, gen_helper_fmpy_d); | |
4120 | do_fop_dedd(ctx, a->ta, a->ta, a->ra, | |
4121 | is_sub ? gen_helper_fsub_d : gen_helper_fadd_d); | |
4122 | ||
4123 | return nullify_end(ctx); | |
4124 | } | |
4125 | ||
4126 | static bool trans_fmpyadd_d(DisasContext *ctx, arg_mpyadd *a) | |
4127 | { | |
4128 | return do_fmpyadd_d(ctx, a, false); | |
4129 | } | |
4130 | ||
4131 | static bool trans_fmpysub_d(DisasContext *ctx, arg_mpyadd *a) | |
4132 | { | |
4133 | return do_fmpyadd_d(ctx, a, true); | |
4134 | } | |
4135 | ||
c3bad4f8 | 4136 | static bool trans_fmpyfadd_f(DisasContext *ctx, arg_fmpyfadd_f *a) |
ebe9383c | 4137 | { |
c3bad4f8 | 4138 | TCGv_i32 x, y, z; |
ebe9383c RH |
4139 | |
4140 | nullify_over(ctx); | |
c3bad4f8 RH |
4141 | x = load_frw0_i32(a->rm1); |
4142 | y = load_frw0_i32(a->rm2); | |
4143 | z = load_frw0_i32(a->ra3); | |
ebe9383c | 4144 | |
c3bad4f8 | 4145 | if (a->neg) { |
ad75a51e | 4146 | gen_helper_fmpynfadd_s(x, tcg_env, x, y, z); |
ebe9383c | 4147 | } else { |
ad75a51e | 4148 | gen_helper_fmpyfadd_s(x, tcg_env, x, y, z); |
ebe9383c RH |
4149 | } |
4150 | ||
c3bad4f8 | 4151 | save_frw_i32(a->t, x); |
31234768 | 4152 | return nullify_end(ctx); |
ebe9383c RH |
4153 | } |
4154 | ||
c3bad4f8 | 4155 | static bool trans_fmpyfadd_d(DisasContext *ctx, arg_fmpyfadd_d *a) |
ebe9383c | 4156 | { |
c3bad4f8 | 4157 | TCGv_i64 x, y, z; |
ebe9383c RH |
4158 | |
4159 | nullify_over(ctx); | |
c3bad4f8 RH |
4160 | x = load_frd0(a->rm1); |
4161 | y = load_frd0(a->rm2); | |
4162 | z = load_frd0(a->ra3); | |
ebe9383c | 4163 | |
c3bad4f8 | 4164 | if (a->neg) { |
ad75a51e | 4165 | gen_helper_fmpynfadd_d(x, tcg_env, x, y, z); |
ebe9383c | 4166 | } else { |
ad75a51e | 4167 | gen_helper_fmpyfadd_d(x, tcg_env, x, y, z); |
ebe9383c RH |
4168 | } |
4169 | ||
c3bad4f8 | 4170 | save_frd(a->t, x); |
31234768 | 4171 | return nullify_end(ctx); |
ebe9383c RH |
4172 | } |
4173 | ||
15da177b SS |
4174 | static bool trans_diag(DisasContext *ctx, arg_diag *a) |
4175 | { | |
cf6b28d4 HD |
4176 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); |
4177 | #ifndef CONFIG_USER_ONLY | |
4178 | if (a->i == 0x100) { | |
4179 | /* emulate PDC BTLB, called by SeaBIOS-hppa */ | |
ad75a51e RH |
4180 | nullify_over(ctx); |
4181 | gen_helper_diag_btlb(tcg_env); | |
4182 | return nullify_end(ctx); | |
cf6b28d4 | 4183 | } |
ad75a51e RH |
4184 | #endif |
4185 | qemu_log_mask(LOG_UNIMP, "DIAG opcode 0x%04x ignored\n", a->i); | |
4186 | return true; | |
15da177b SS |
4187 | } |
4188 | ||
b542683d | 4189 | static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) |
61766fe9 | 4190 | { |
51b061fb | 4191 | DisasContext *ctx = container_of(dcbase, DisasContext, base); |
f764718d | 4192 | int bound; |
61766fe9 | 4193 | |
51b061fb | 4194 | ctx->cs = cs; |
494737b7 | 4195 | ctx->tb_flags = ctx->base.tb->flags; |
bd6243a3 | 4196 | ctx->is_pa20 = hppa_is_pa20(cpu_env(cs)); |
3d68ee7b RH |
4197 | |
4198 | #ifdef CONFIG_USER_ONLY | |
c01e5dfb | 4199 | ctx->privilege = MMU_IDX_TO_PRIV(MMU_USER_IDX); |
3d68ee7b | 4200 | ctx->mmu_idx = MMU_USER_IDX; |
c01e5dfb HD |
4201 | ctx->iaoq_f = ctx->base.pc_first | ctx->privilege; |
4202 | ctx->iaoq_b = ctx->base.tb->cs_base | ctx->privilege; | |
217d1a5e | 4203 | ctx->unalign = (ctx->tb_flags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN); |
3d68ee7b | 4204 | #else |
494737b7 | 4205 | ctx->privilege = (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3; |
bb67ec32 RH |
4206 | ctx->mmu_idx = (ctx->tb_flags & PSW_D |
4207 | ? PRIV_P_TO_MMU_IDX(ctx->privilege, ctx->tb_flags & PSW_P) | |
4208 | : MMU_PHYS_IDX); | |
3d68ee7b | 4209 | |
c301f34e RH |
4210 | /* Recover the IAOQ values from the GVA + PRIV. */ |
4211 | uint64_t cs_base = ctx->base.tb->cs_base; | |
4212 | uint64_t iasq_f = cs_base & ~0xffffffffull; | |
4213 | int32_t diff = cs_base; | |
4214 | ||
4215 | ctx->iaoq_f = (ctx->base.pc_first & ~iasq_f) + ctx->privilege; | |
4216 | ctx->iaoq_b = (diff ? ctx->iaoq_f + diff : -1); | |
4217 | #endif | |
51b061fb | 4218 | ctx->iaoq_n = -1; |
f764718d | 4219 | ctx->iaoq_n_var = NULL; |
61766fe9 | 4220 | |
3d68ee7b RH |
4221 | /* Bound the number of instructions by those left on the page. */ |
4222 | bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; | |
b542683d | 4223 | ctx->base.max_insns = MIN(ctx->base.max_insns, bound); |
51b061fb | 4224 | } |
61766fe9 | 4225 | |
51b061fb RH |
4226 | static void hppa_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) |
4227 | { | |
4228 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
61766fe9 | 4229 | |
3d68ee7b | 4230 | /* Seed the nullification status from PSW[N], as saved in TB->FLAGS. */ |
51b061fb RH |
4231 | ctx->null_cond = cond_make_f(); |
4232 | ctx->psw_n_nonzero = false; | |
494737b7 | 4233 | if (ctx->tb_flags & PSW_N) { |
51b061fb RH |
4234 | ctx->null_cond.c = TCG_COND_ALWAYS; |
4235 | ctx->psw_n_nonzero = true; | |
129e9cc3 | 4236 | } |
51b061fb RH |
4237 | ctx->null_lab = NULL; |
4238 | } | |
129e9cc3 | 4239 | |
51b061fb RH |
4240 | static void hppa_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) |
4241 | { | |
4242 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
61766fe9 | 4243 | |
51b061fb RH |
4244 | tcg_gen_insn_start(ctx->iaoq_f, ctx->iaoq_b); |
4245 | } | |
4246 | ||
51b061fb RH |
4247 | static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) |
4248 | { | |
4249 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
b77af26e | 4250 | CPUHPPAState *env = cpu_env(cs); |
51b061fb | 4251 | DisasJumpType ret; |
51b061fb RH |
4252 | |
4253 | /* Execute one insn. */ | |
ba1d0b44 | 4254 | #ifdef CONFIG_USER_ONLY |
c301f34e | 4255 | if (ctx->base.pc_next < TARGET_PAGE_SIZE) { |
31234768 RH |
4256 | do_page_zero(ctx); |
4257 | ret = ctx->base.is_jmp; | |
51b061fb | 4258 | assert(ret != DISAS_NEXT); |
ba1d0b44 RH |
4259 | } else |
4260 | #endif | |
4261 | { | |
51b061fb RH |
4262 | /* Always fetch the insn, even if nullified, so that we check |
4263 | the page permissions for execute. */ | |
4e116893 | 4264 | uint32_t insn = translator_ldl(env, &ctx->base, ctx->base.pc_next); |
51b061fb RH |
4265 | |
4266 | /* Set up the IA queue for the next insn. | |
4267 | This will be overwritten by a branch. */ | |
4268 | if (ctx->iaoq_b == -1) { | |
4269 | ctx->iaoq_n = -1; | |
e12c6309 | 4270 | ctx->iaoq_n_var = tcg_temp_new(); |
eaa3783b | 4271 | tcg_gen_addi_reg(ctx->iaoq_n_var, cpu_iaoq_b, 4); |
7ad439df | 4272 | } else { |
51b061fb | 4273 | ctx->iaoq_n = ctx->iaoq_b + 4; |
f764718d | 4274 | ctx->iaoq_n_var = NULL; |
61766fe9 RH |
4275 | } |
4276 | ||
51b061fb RH |
4277 | if (unlikely(ctx->null_cond.c == TCG_COND_ALWAYS)) { |
4278 | ctx->null_cond.c = TCG_COND_NEVER; | |
4279 | ret = DISAS_NEXT; | |
4280 | } else { | |
1a19da0d | 4281 | ctx->insn = insn; |
31274b46 RH |
4282 | if (!decode(ctx, insn)) { |
4283 | gen_illegal(ctx); | |
4284 | } | |
31234768 | 4285 | ret = ctx->base.is_jmp; |
51b061fb | 4286 | assert(ctx->null_lab == NULL); |
61766fe9 | 4287 | } |
51b061fb | 4288 | } |
61766fe9 | 4289 | |
3d68ee7b RH |
4290 | /* Advance the insn queue. Note that this check also detects |
4291 | a priority change within the instruction queue. */ | |
51b061fb | 4292 | if (ret == DISAS_NEXT && ctx->iaoq_b != ctx->iaoq_f + 4) { |
c301f34e RH |
4293 | if (ctx->iaoq_b != -1 && ctx->iaoq_n != -1 |
4294 | && use_goto_tb(ctx, ctx->iaoq_b) | |
4295 | && (ctx->null_cond.c == TCG_COND_NEVER | |
4296 | || ctx->null_cond.c == TCG_COND_ALWAYS)) { | |
51b061fb RH |
4297 | nullify_set(ctx, ctx->null_cond.c == TCG_COND_ALWAYS); |
4298 | gen_goto_tb(ctx, 0, ctx->iaoq_b, ctx->iaoq_n); | |
31234768 | 4299 | ctx->base.is_jmp = ret = DISAS_NORETURN; |
51b061fb | 4300 | } else { |
31234768 | 4301 | ctx->base.is_jmp = ret = DISAS_IAQ_N_STALE; |
c301f34e | 4302 | } |
61766fe9 | 4303 | } |
51b061fb RH |
4304 | ctx->iaoq_f = ctx->iaoq_b; |
4305 | ctx->iaoq_b = ctx->iaoq_n; | |
c301f34e | 4306 | ctx->base.pc_next += 4; |
51b061fb | 4307 | |
c5d0aec2 RH |
4308 | switch (ret) { |
4309 | case DISAS_NORETURN: | |
4310 | case DISAS_IAQ_N_UPDATED: | |
4311 | break; | |
4312 | ||
4313 | case DISAS_NEXT: | |
4314 | case DISAS_IAQ_N_STALE: | |
4315 | case DISAS_IAQ_N_STALE_EXIT: | |
4316 | if (ctx->iaoq_f == -1) { | |
a0180973 | 4317 | copy_iaoq_entry(ctx, cpu_iaoq_f, -1, cpu_iaoq_b); |
741322f4 | 4318 | copy_iaoq_entry(ctx, cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var); |
c301f34e | 4319 | #ifndef CONFIG_USER_ONLY |
c5d0aec2 | 4320 | tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); |
c301f34e | 4321 | #endif |
c5d0aec2 RH |
4322 | nullify_save(ctx); |
4323 | ctx->base.is_jmp = (ret == DISAS_IAQ_N_STALE_EXIT | |
4324 | ? DISAS_EXIT | |
4325 | : DISAS_IAQ_N_UPDATED); | |
4326 | } else if (ctx->iaoq_b == -1) { | |
a0180973 | 4327 | copy_iaoq_entry(ctx, cpu_iaoq_b, -1, ctx->iaoq_n_var); |
c5d0aec2 RH |
4328 | } |
4329 | break; | |
4330 | ||
4331 | default: | |
4332 | g_assert_not_reached(); | |
51b061fb RH |
4333 | } |
4334 | } | |
4335 | ||
4336 | static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) | |
4337 | { | |
4338 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
e1b5a5ed | 4339 | DisasJumpType is_jmp = ctx->base.is_jmp; |
61766fe9 | 4340 | |
e1b5a5ed | 4341 | switch (is_jmp) { |
869051ea | 4342 | case DISAS_NORETURN: |
61766fe9 | 4343 | break; |
51b061fb | 4344 | case DISAS_TOO_MANY: |
869051ea | 4345 | case DISAS_IAQ_N_STALE: |
e1b5a5ed | 4346 | case DISAS_IAQ_N_STALE_EXIT: |
741322f4 RH |
4347 | copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_f, cpu_iaoq_f); |
4348 | copy_iaoq_entry(ctx, cpu_iaoq_b, ctx->iaoq_b, cpu_iaoq_b); | |
51b061fb | 4349 | nullify_save(ctx); |
61766fe9 | 4350 | /* FALLTHRU */ |
869051ea | 4351 | case DISAS_IAQ_N_UPDATED: |
8532a14e | 4352 | if (is_jmp != DISAS_IAQ_N_STALE_EXIT) { |
7f11636d | 4353 | tcg_gen_lookup_and_goto_ptr(); |
8532a14e | 4354 | break; |
61766fe9 | 4355 | } |
c5d0aec2 RH |
4356 | /* FALLTHRU */ |
4357 | case DISAS_EXIT: | |
4358 | tcg_gen_exit_tb(NULL, 0); | |
61766fe9 RH |
4359 | break; |
4360 | default: | |
51b061fb | 4361 | g_assert_not_reached(); |
61766fe9 | 4362 | } |
51b061fb | 4363 | } |
61766fe9 | 4364 | |
8eb806a7 RH |
4365 | static void hppa_tr_disas_log(const DisasContextBase *dcbase, |
4366 | CPUState *cs, FILE *logfile) | |
51b061fb | 4367 | { |
c301f34e | 4368 | target_ulong pc = dcbase->pc_first; |
61766fe9 | 4369 | |
ba1d0b44 RH |
4370 | #ifdef CONFIG_USER_ONLY |
4371 | switch (pc) { | |
51b061fb | 4372 | case 0x00: |
8eb806a7 | 4373 | fprintf(logfile, "IN:\n0x00000000: (null)\n"); |
ba1d0b44 | 4374 | return; |
51b061fb | 4375 | case 0xb0: |
8eb806a7 | 4376 | fprintf(logfile, "IN:\n0x000000b0: light-weight-syscall\n"); |
ba1d0b44 | 4377 | return; |
51b061fb | 4378 | case 0xe0: |
8eb806a7 | 4379 | fprintf(logfile, "IN:\n0x000000e0: set-thread-pointer-syscall\n"); |
ba1d0b44 | 4380 | return; |
51b061fb | 4381 | case 0x100: |
8eb806a7 | 4382 | fprintf(logfile, "IN:\n0x00000100: syscall\n"); |
ba1d0b44 | 4383 | return; |
61766fe9 | 4384 | } |
ba1d0b44 RH |
4385 | #endif |
4386 | ||
8eb806a7 RH |
4387 | fprintf(logfile, "IN: %s\n", lookup_symbol(pc)); |
4388 | target_disas(logfile, cs, pc, dcbase->tb->size); | |
51b061fb RH |
4389 | } |
4390 | ||
4391 | static const TranslatorOps hppa_tr_ops = { | |
4392 | .init_disas_context = hppa_tr_init_disas_context, | |
4393 | .tb_start = hppa_tr_tb_start, | |
4394 | .insn_start = hppa_tr_insn_start, | |
51b061fb RH |
4395 | .translate_insn = hppa_tr_translate_insn, |
4396 | .tb_stop = hppa_tr_tb_stop, | |
4397 | .disas_log = hppa_tr_disas_log, | |
4398 | }; | |
4399 | ||
597f9b2d | 4400 | void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, |
306c8721 | 4401 | target_ulong pc, void *host_pc) |
51b061fb RH |
4402 | { |
4403 | DisasContext ctx; | |
306c8721 | 4404 | translator_loop(cs, tb, max_insns, pc, host_pc, &hppa_tr_ops, &ctx.base); |
61766fe9 | 4405 | } |