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61766fe9 RH |
1 | /* |
2 | * HPPA emulation cpu translation for qemu. | |
3 | * | |
4 | * Copyright (c) 2016 Richard Henderson <rth@twiddle.net> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
d6ea4236 | 9 | * version 2.1 of the License, or (at your option) any later version. |
61766fe9 RH |
10 | * |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
21 | #include "cpu.h" | |
22 | #include "disas/disas.h" | |
23 | #include "qemu/host-utils.h" | |
24 | #include "exec/exec-all.h" | |
dcb32f1d | 25 | #include "tcg/tcg-op.h" |
61766fe9 | 26 | #include "exec/cpu_ldst.h" |
61766fe9 RH |
27 | #include "exec/helper-proto.h" |
28 | #include "exec/helper-gen.h" | |
869051ea | 29 | #include "exec/translator.h" |
61766fe9 RH |
30 | #include "exec/log.h" |
31 | ||
eaa3783b RH |
32 | /* Since we have a distinction between register size and address size, |
33 | we need to redefine all of these. */ | |
34 | ||
35 | #undef TCGv | |
36 | #undef tcg_temp_new | |
eaa3783b RH |
37 | #undef tcg_global_mem_new |
38 | #undef tcg_temp_local_new | |
39 | #undef tcg_temp_free | |
40 | ||
41 | #if TARGET_LONG_BITS == 64 | |
42 | #define TCGv_tl TCGv_i64 | |
43 | #define tcg_temp_new_tl tcg_temp_new_i64 | |
44 | #define tcg_temp_free_tl tcg_temp_free_i64 | |
45 | #if TARGET_REGISTER_BITS == 64 | |
46 | #define tcg_gen_extu_reg_tl tcg_gen_mov_i64 | |
47 | #else | |
48 | #define tcg_gen_extu_reg_tl tcg_gen_extu_i32_i64 | |
49 | #endif | |
50 | #else | |
51 | #define TCGv_tl TCGv_i32 | |
52 | #define tcg_temp_new_tl tcg_temp_new_i32 | |
53 | #define tcg_temp_free_tl tcg_temp_free_i32 | |
54 | #define tcg_gen_extu_reg_tl tcg_gen_mov_i32 | |
55 | #endif | |
56 | ||
57 | #if TARGET_REGISTER_BITS == 64 | |
58 | #define TCGv_reg TCGv_i64 | |
59 | ||
60 | #define tcg_temp_new tcg_temp_new_i64 | |
eaa3783b RH |
61 | #define tcg_global_mem_new tcg_global_mem_new_i64 |
62 | #define tcg_temp_local_new tcg_temp_local_new_i64 | |
63 | #define tcg_temp_free tcg_temp_free_i64 | |
64 | ||
65 | #define tcg_gen_movi_reg tcg_gen_movi_i64 | |
66 | #define tcg_gen_mov_reg tcg_gen_mov_i64 | |
67 | #define tcg_gen_ld8u_reg tcg_gen_ld8u_i64 | |
68 | #define tcg_gen_ld8s_reg tcg_gen_ld8s_i64 | |
69 | #define tcg_gen_ld16u_reg tcg_gen_ld16u_i64 | |
70 | #define tcg_gen_ld16s_reg tcg_gen_ld16s_i64 | |
71 | #define tcg_gen_ld32u_reg tcg_gen_ld32u_i64 | |
72 | #define tcg_gen_ld32s_reg tcg_gen_ld32s_i64 | |
73 | #define tcg_gen_ld_reg tcg_gen_ld_i64 | |
74 | #define tcg_gen_st8_reg tcg_gen_st8_i64 | |
75 | #define tcg_gen_st16_reg tcg_gen_st16_i64 | |
76 | #define tcg_gen_st32_reg tcg_gen_st32_i64 | |
77 | #define tcg_gen_st_reg tcg_gen_st_i64 | |
78 | #define tcg_gen_add_reg tcg_gen_add_i64 | |
79 | #define tcg_gen_addi_reg tcg_gen_addi_i64 | |
80 | #define tcg_gen_sub_reg tcg_gen_sub_i64 | |
81 | #define tcg_gen_neg_reg tcg_gen_neg_i64 | |
82 | #define tcg_gen_subfi_reg tcg_gen_subfi_i64 | |
83 | #define tcg_gen_subi_reg tcg_gen_subi_i64 | |
84 | #define tcg_gen_and_reg tcg_gen_and_i64 | |
85 | #define tcg_gen_andi_reg tcg_gen_andi_i64 | |
86 | #define tcg_gen_or_reg tcg_gen_or_i64 | |
87 | #define tcg_gen_ori_reg tcg_gen_ori_i64 | |
88 | #define tcg_gen_xor_reg tcg_gen_xor_i64 | |
89 | #define tcg_gen_xori_reg tcg_gen_xori_i64 | |
90 | #define tcg_gen_not_reg tcg_gen_not_i64 | |
91 | #define tcg_gen_shl_reg tcg_gen_shl_i64 | |
92 | #define tcg_gen_shli_reg tcg_gen_shli_i64 | |
93 | #define tcg_gen_shr_reg tcg_gen_shr_i64 | |
94 | #define tcg_gen_shri_reg tcg_gen_shri_i64 | |
95 | #define tcg_gen_sar_reg tcg_gen_sar_i64 | |
96 | #define tcg_gen_sari_reg tcg_gen_sari_i64 | |
97 | #define tcg_gen_brcond_reg tcg_gen_brcond_i64 | |
98 | #define tcg_gen_brcondi_reg tcg_gen_brcondi_i64 | |
99 | #define tcg_gen_setcond_reg tcg_gen_setcond_i64 | |
100 | #define tcg_gen_setcondi_reg tcg_gen_setcondi_i64 | |
101 | #define tcg_gen_mul_reg tcg_gen_mul_i64 | |
102 | #define tcg_gen_muli_reg tcg_gen_muli_i64 | |
103 | #define tcg_gen_div_reg tcg_gen_div_i64 | |
104 | #define tcg_gen_rem_reg tcg_gen_rem_i64 | |
105 | #define tcg_gen_divu_reg tcg_gen_divu_i64 | |
106 | #define tcg_gen_remu_reg tcg_gen_remu_i64 | |
107 | #define tcg_gen_discard_reg tcg_gen_discard_i64 | |
108 | #define tcg_gen_trunc_reg_i32 tcg_gen_extrl_i64_i32 | |
109 | #define tcg_gen_trunc_i64_reg tcg_gen_mov_i64 | |
110 | #define tcg_gen_extu_i32_reg tcg_gen_extu_i32_i64 | |
111 | #define tcg_gen_ext_i32_reg tcg_gen_ext_i32_i64 | |
112 | #define tcg_gen_extu_reg_i64 tcg_gen_mov_i64 | |
113 | #define tcg_gen_ext_reg_i64 tcg_gen_mov_i64 | |
114 | #define tcg_gen_ext8u_reg tcg_gen_ext8u_i64 | |
115 | #define tcg_gen_ext8s_reg tcg_gen_ext8s_i64 | |
116 | #define tcg_gen_ext16u_reg tcg_gen_ext16u_i64 | |
117 | #define tcg_gen_ext16s_reg tcg_gen_ext16s_i64 | |
118 | #define tcg_gen_ext32u_reg tcg_gen_ext32u_i64 | |
119 | #define tcg_gen_ext32s_reg tcg_gen_ext32s_i64 | |
120 | #define tcg_gen_bswap16_reg tcg_gen_bswap16_i64 | |
121 | #define tcg_gen_bswap32_reg tcg_gen_bswap32_i64 | |
122 | #define tcg_gen_bswap64_reg tcg_gen_bswap64_i64 | |
123 | #define tcg_gen_concat_reg_i64 tcg_gen_concat32_i64 | |
124 | #define tcg_gen_andc_reg tcg_gen_andc_i64 | |
125 | #define tcg_gen_eqv_reg tcg_gen_eqv_i64 | |
126 | #define tcg_gen_nand_reg tcg_gen_nand_i64 | |
127 | #define tcg_gen_nor_reg tcg_gen_nor_i64 | |
128 | #define tcg_gen_orc_reg tcg_gen_orc_i64 | |
129 | #define tcg_gen_clz_reg tcg_gen_clz_i64 | |
130 | #define tcg_gen_ctz_reg tcg_gen_ctz_i64 | |
131 | #define tcg_gen_clzi_reg tcg_gen_clzi_i64 | |
132 | #define tcg_gen_ctzi_reg tcg_gen_ctzi_i64 | |
133 | #define tcg_gen_clrsb_reg tcg_gen_clrsb_i64 | |
134 | #define tcg_gen_ctpop_reg tcg_gen_ctpop_i64 | |
135 | #define tcg_gen_rotl_reg tcg_gen_rotl_i64 | |
136 | #define tcg_gen_rotli_reg tcg_gen_rotli_i64 | |
137 | #define tcg_gen_rotr_reg tcg_gen_rotr_i64 | |
138 | #define tcg_gen_rotri_reg tcg_gen_rotri_i64 | |
139 | #define tcg_gen_deposit_reg tcg_gen_deposit_i64 | |
140 | #define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i64 | |
141 | #define tcg_gen_extract_reg tcg_gen_extract_i64 | |
142 | #define tcg_gen_sextract_reg tcg_gen_sextract_i64 | |
05bfd4db | 143 | #define tcg_gen_extract2_reg tcg_gen_extract2_i64 |
eaa3783b RH |
144 | #define tcg_const_reg tcg_const_i64 |
145 | #define tcg_const_local_reg tcg_const_local_i64 | |
29dd6f64 | 146 | #define tcg_constant_reg tcg_constant_i64 |
eaa3783b RH |
147 | #define tcg_gen_movcond_reg tcg_gen_movcond_i64 |
148 | #define tcg_gen_add2_reg tcg_gen_add2_i64 | |
149 | #define tcg_gen_sub2_reg tcg_gen_sub2_i64 | |
150 | #define tcg_gen_qemu_ld_reg tcg_gen_qemu_ld_i64 | |
151 | #define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i64 | |
152 | #define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i64 | |
5bfa8034 | 153 | #define tcg_gen_trunc_reg_ptr tcg_gen_trunc_i64_ptr |
eaa3783b RH |
154 | #else |
155 | #define TCGv_reg TCGv_i32 | |
156 | #define tcg_temp_new tcg_temp_new_i32 | |
eaa3783b RH |
157 | #define tcg_global_mem_new tcg_global_mem_new_i32 |
158 | #define tcg_temp_local_new tcg_temp_local_new_i32 | |
159 | #define tcg_temp_free tcg_temp_free_i32 | |
160 | ||
161 | #define tcg_gen_movi_reg tcg_gen_movi_i32 | |
162 | #define tcg_gen_mov_reg tcg_gen_mov_i32 | |
163 | #define tcg_gen_ld8u_reg tcg_gen_ld8u_i32 | |
164 | #define tcg_gen_ld8s_reg tcg_gen_ld8s_i32 | |
165 | #define tcg_gen_ld16u_reg tcg_gen_ld16u_i32 | |
166 | #define tcg_gen_ld16s_reg tcg_gen_ld16s_i32 | |
167 | #define tcg_gen_ld32u_reg tcg_gen_ld_i32 | |
168 | #define tcg_gen_ld32s_reg tcg_gen_ld_i32 | |
169 | #define tcg_gen_ld_reg tcg_gen_ld_i32 | |
170 | #define tcg_gen_st8_reg tcg_gen_st8_i32 | |
171 | #define tcg_gen_st16_reg tcg_gen_st16_i32 | |
172 | #define tcg_gen_st32_reg tcg_gen_st32_i32 | |
173 | #define tcg_gen_st_reg tcg_gen_st_i32 | |
174 | #define tcg_gen_add_reg tcg_gen_add_i32 | |
175 | #define tcg_gen_addi_reg tcg_gen_addi_i32 | |
176 | #define tcg_gen_sub_reg tcg_gen_sub_i32 | |
177 | #define tcg_gen_neg_reg tcg_gen_neg_i32 | |
178 | #define tcg_gen_subfi_reg tcg_gen_subfi_i32 | |
179 | #define tcg_gen_subi_reg tcg_gen_subi_i32 | |
180 | #define tcg_gen_and_reg tcg_gen_and_i32 | |
181 | #define tcg_gen_andi_reg tcg_gen_andi_i32 | |
182 | #define tcg_gen_or_reg tcg_gen_or_i32 | |
183 | #define tcg_gen_ori_reg tcg_gen_ori_i32 | |
184 | #define tcg_gen_xor_reg tcg_gen_xor_i32 | |
185 | #define tcg_gen_xori_reg tcg_gen_xori_i32 | |
186 | #define tcg_gen_not_reg tcg_gen_not_i32 | |
187 | #define tcg_gen_shl_reg tcg_gen_shl_i32 | |
188 | #define tcg_gen_shli_reg tcg_gen_shli_i32 | |
189 | #define tcg_gen_shr_reg tcg_gen_shr_i32 | |
190 | #define tcg_gen_shri_reg tcg_gen_shri_i32 | |
191 | #define tcg_gen_sar_reg tcg_gen_sar_i32 | |
192 | #define tcg_gen_sari_reg tcg_gen_sari_i32 | |
193 | #define tcg_gen_brcond_reg tcg_gen_brcond_i32 | |
194 | #define tcg_gen_brcondi_reg tcg_gen_brcondi_i32 | |
195 | #define tcg_gen_setcond_reg tcg_gen_setcond_i32 | |
196 | #define tcg_gen_setcondi_reg tcg_gen_setcondi_i32 | |
197 | #define tcg_gen_mul_reg tcg_gen_mul_i32 | |
198 | #define tcg_gen_muli_reg tcg_gen_muli_i32 | |
199 | #define tcg_gen_div_reg tcg_gen_div_i32 | |
200 | #define tcg_gen_rem_reg tcg_gen_rem_i32 | |
201 | #define tcg_gen_divu_reg tcg_gen_divu_i32 | |
202 | #define tcg_gen_remu_reg tcg_gen_remu_i32 | |
203 | #define tcg_gen_discard_reg tcg_gen_discard_i32 | |
204 | #define tcg_gen_trunc_reg_i32 tcg_gen_mov_i32 | |
205 | #define tcg_gen_trunc_i64_reg tcg_gen_extrl_i64_i32 | |
206 | #define tcg_gen_extu_i32_reg tcg_gen_mov_i32 | |
207 | #define tcg_gen_ext_i32_reg tcg_gen_mov_i32 | |
208 | #define tcg_gen_extu_reg_i64 tcg_gen_extu_i32_i64 | |
209 | #define tcg_gen_ext_reg_i64 tcg_gen_ext_i32_i64 | |
210 | #define tcg_gen_ext8u_reg tcg_gen_ext8u_i32 | |
211 | #define tcg_gen_ext8s_reg tcg_gen_ext8s_i32 | |
212 | #define tcg_gen_ext16u_reg tcg_gen_ext16u_i32 | |
213 | #define tcg_gen_ext16s_reg tcg_gen_ext16s_i32 | |
214 | #define tcg_gen_ext32u_reg tcg_gen_mov_i32 | |
215 | #define tcg_gen_ext32s_reg tcg_gen_mov_i32 | |
216 | #define tcg_gen_bswap16_reg tcg_gen_bswap16_i32 | |
217 | #define tcg_gen_bswap32_reg tcg_gen_bswap32_i32 | |
218 | #define tcg_gen_concat_reg_i64 tcg_gen_concat_i32_i64 | |
219 | #define tcg_gen_andc_reg tcg_gen_andc_i32 | |
220 | #define tcg_gen_eqv_reg tcg_gen_eqv_i32 | |
221 | #define tcg_gen_nand_reg tcg_gen_nand_i32 | |
222 | #define tcg_gen_nor_reg tcg_gen_nor_i32 | |
223 | #define tcg_gen_orc_reg tcg_gen_orc_i32 | |
224 | #define tcg_gen_clz_reg tcg_gen_clz_i32 | |
225 | #define tcg_gen_ctz_reg tcg_gen_ctz_i32 | |
226 | #define tcg_gen_clzi_reg tcg_gen_clzi_i32 | |
227 | #define tcg_gen_ctzi_reg tcg_gen_ctzi_i32 | |
228 | #define tcg_gen_clrsb_reg tcg_gen_clrsb_i32 | |
229 | #define tcg_gen_ctpop_reg tcg_gen_ctpop_i32 | |
230 | #define tcg_gen_rotl_reg tcg_gen_rotl_i32 | |
231 | #define tcg_gen_rotli_reg tcg_gen_rotli_i32 | |
232 | #define tcg_gen_rotr_reg tcg_gen_rotr_i32 | |
233 | #define tcg_gen_rotri_reg tcg_gen_rotri_i32 | |
234 | #define tcg_gen_deposit_reg tcg_gen_deposit_i32 | |
235 | #define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i32 | |
236 | #define tcg_gen_extract_reg tcg_gen_extract_i32 | |
237 | #define tcg_gen_sextract_reg tcg_gen_sextract_i32 | |
05bfd4db | 238 | #define tcg_gen_extract2_reg tcg_gen_extract2_i32 |
eaa3783b RH |
239 | #define tcg_const_reg tcg_const_i32 |
240 | #define tcg_const_local_reg tcg_const_local_i32 | |
29dd6f64 | 241 | #define tcg_constant_reg tcg_constant_i32 |
eaa3783b RH |
242 | #define tcg_gen_movcond_reg tcg_gen_movcond_i32 |
243 | #define tcg_gen_add2_reg tcg_gen_add2_i32 | |
244 | #define tcg_gen_sub2_reg tcg_gen_sub2_i32 | |
245 | #define tcg_gen_qemu_ld_reg tcg_gen_qemu_ld_i32 | |
246 | #define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i32 | |
247 | #define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i32 | |
5bfa8034 | 248 | #define tcg_gen_trunc_reg_ptr tcg_gen_ext_i32_ptr |
eaa3783b RH |
249 | #endif /* TARGET_REGISTER_BITS */ |
250 | ||
61766fe9 RH |
251 | typedef struct DisasCond { |
252 | TCGCond c; | |
eaa3783b | 253 | TCGv_reg a0, a1; |
61766fe9 RH |
254 | } DisasCond; |
255 | ||
256 | typedef struct DisasContext { | |
d01a3625 | 257 | DisasContextBase base; |
61766fe9 RH |
258 | CPUState *cs; |
259 | ||
eaa3783b RH |
260 | target_ureg iaoq_f; |
261 | target_ureg iaoq_b; | |
262 | target_ureg iaoq_n; | |
263 | TCGv_reg iaoq_n_var; | |
61766fe9 | 264 | |
86f8d05f | 265 | int ntempr, ntempl; |
5eecd37a | 266 | TCGv_reg tempr[8]; |
86f8d05f | 267 | TCGv_tl templ[4]; |
61766fe9 RH |
268 | |
269 | DisasCond null_cond; | |
270 | TCGLabel *null_lab; | |
271 | ||
1a19da0d | 272 | uint32_t insn; |
494737b7 | 273 | uint32_t tb_flags; |
3d68ee7b RH |
274 | int mmu_idx; |
275 | int privilege; | |
61766fe9 | 276 | bool psw_n_nonzero; |
217d1a5e RH |
277 | |
278 | #ifdef CONFIG_USER_ONLY | |
279 | MemOp unalign; | |
280 | #endif | |
61766fe9 RH |
281 | } DisasContext; |
282 | ||
217d1a5e RH |
283 | #ifdef CONFIG_USER_ONLY |
284 | #define UNALIGN(C) (C)->unalign | |
285 | #else | |
286 | #define UNALIGN(C) 0 | |
287 | #endif | |
288 | ||
e36f27ef | 289 | /* Note that ssm/rsm instructions number PSW_W and PSW_E differently. */ |
451e4ffd | 290 | static int expand_sm_imm(DisasContext *ctx, int val) |
e36f27ef RH |
291 | { |
292 | if (val & PSW_SM_E) { | |
293 | val = (val & ~PSW_SM_E) | PSW_E; | |
294 | } | |
295 | if (val & PSW_SM_W) { | |
296 | val = (val & ~PSW_SM_W) | PSW_W; | |
297 | } | |
298 | return val; | |
299 | } | |
300 | ||
deee69a1 | 301 | /* Inverted space register indicates 0 means sr0 not inferred from base. */ |
451e4ffd | 302 | static int expand_sr3x(DisasContext *ctx, int val) |
deee69a1 RH |
303 | { |
304 | return ~val; | |
305 | } | |
306 | ||
1cd012a5 RH |
307 | /* Convert the M:A bits within a memory insn to the tri-state value |
308 | we use for the final M. */ | |
451e4ffd | 309 | static int ma_to_m(DisasContext *ctx, int val) |
1cd012a5 RH |
310 | { |
311 | return val & 2 ? (val & 1 ? -1 : 1) : 0; | |
312 | } | |
313 | ||
740038d7 | 314 | /* Convert the sign of the displacement to a pre or post-modify. */ |
451e4ffd | 315 | static int pos_to_m(DisasContext *ctx, int val) |
740038d7 RH |
316 | { |
317 | return val ? 1 : -1; | |
318 | } | |
319 | ||
451e4ffd | 320 | static int neg_to_m(DisasContext *ctx, int val) |
740038d7 RH |
321 | { |
322 | return val ? -1 : 1; | |
323 | } | |
324 | ||
325 | /* Used for branch targets and fp memory ops. */ | |
451e4ffd | 326 | static int expand_shl2(DisasContext *ctx, int val) |
01afb7be RH |
327 | { |
328 | return val << 2; | |
329 | } | |
330 | ||
740038d7 | 331 | /* Used for fp memory ops. */ |
451e4ffd | 332 | static int expand_shl3(DisasContext *ctx, int val) |
740038d7 RH |
333 | { |
334 | return val << 3; | |
335 | } | |
336 | ||
0588e061 | 337 | /* Used for assemble_21. */ |
451e4ffd | 338 | static int expand_shl11(DisasContext *ctx, int val) |
0588e061 RH |
339 | { |
340 | return val << 11; | |
341 | } | |
342 | ||
01afb7be | 343 | |
40f9f908 | 344 | /* Include the auto-generated decoder. */ |
abff1abf | 345 | #include "decode-insns.c.inc" |
40f9f908 | 346 | |
869051ea RH |
347 | /* We are not using a goto_tb (for whatever reason), but have updated |
348 | the iaq (for whatever reason), so don't do it again on exit. */ | |
349 | #define DISAS_IAQ_N_UPDATED DISAS_TARGET_0 | |
61766fe9 | 350 | |
869051ea RH |
351 | /* We are exiting the TB, but have neither emitted a goto_tb, nor |
352 | updated the iaq for the next instruction to be executed. */ | |
353 | #define DISAS_IAQ_N_STALE DISAS_TARGET_1 | |
61766fe9 | 354 | |
e1b5a5ed RH |
355 | /* Similarly, but we want to return to the main loop immediately |
356 | to recognize unmasked interrupts. */ | |
357 | #define DISAS_IAQ_N_STALE_EXIT DISAS_TARGET_2 | |
c5d0aec2 | 358 | #define DISAS_EXIT DISAS_TARGET_3 |
e1b5a5ed | 359 | |
61766fe9 | 360 | /* global register indexes */ |
eaa3783b | 361 | static TCGv_reg cpu_gr[32]; |
33423472 | 362 | static TCGv_i64 cpu_sr[4]; |
494737b7 | 363 | static TCGv_i64 cpu_srH; |
eaa3783b RH |
364 | static TCGv_reg cpu_iaoq_f; |
365 | static TCGv_reg cpu_iaoq_b; | |
c301f34e RH |
366 | static TCGv_i64 cpu_iasq_f; |
367 | static TCGv_i64 cpu_iasq_b; | |
eaa3783b RH |
368 | static TCGv_reg cpu_sar; |
369 | static TCGv_reg cpu_psw_n; | |
370 | static TCGv_reg cpu_psw_v; | |
371 | static TCGv_reg cpu_psw_cb; | |
372 | static TCGv_reg cpu_psw_cb_msb; | |
61766fe9 RH |
373 | |
374 | #include "exec/gen-icount.h" | |
375 | ||
376 | void hppa_translate_init(void) | |
377 | { | |
378 | #define DEF_VAR(V) { &cpu_##V, #V, offsetof(CPUHPPAState, V) } | |
379 | ||
eaa3783b | 380 | typedef struct { TCGv_reg *var; const char *name; int ofs; } GlobalVar; |
61766fe9 | 381 | static const GlobalVar vars[] = { |
35136a77 | 382 | { &cpu_sar, "sar", offsetof(CPUHPPAState, cr[CR_SAR]) }, |
61766fe9 RH |
383 | DEF_VAR(psw_n), |
384 | DEF_VAR(psw_v), | |
385 | DEF_VAR(psw_cb), | |
386 | DEF_VAR(psw_cb_msb), | |
387 | DEF_VAR(iaoq_f), | |
388 | DEF_VAR(iaoq_b), | |
389 | }; | |
390 | ||
391 | #undef DEF_VAR | |
392 | ||
393 | /* Use the symbolic register names that match the disassembler. */ | |
394 | static const char gr_names[32][4] = { | |
395 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
396 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
397 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
398 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | |
399 | }; | |
33423472 | 400 | /* SR[4-7] are not global registers so that we can index them. */ |
494737b7 RH |
401 | static const char sr_names[5][4] = { |
402 | "sr0", "sr1", "sr2", "sr3", "srH" | |
33423472 | 403 | }; |
61766fe9 | 404 | |
61766fe9 RH |
405 | int i; |
406 | ||
f764718d | 407 | cpu_gr[0] = NULL; |
61766fe9 RH |
408 | for (i = 1; i < 32; i++) { |
409 | cpu_gr[i] = tcg_global_mem_new(cpu_env, | |
410 | offsetof(CPUHPPAState, gr[i]), | |
411 | gr_names[i]); | |
412 | } | |
33423472 RH |
413 | for (i = 0; i < 4; i++) { |
414 | cpu_sr[i] = tcg_global_mem_new_i64(cpu_env, | |
415 | offsetof(CPUHPPAState, sr[i]), | |
416 | sr_names[i]); | |
417 | } | |
494737b7 RH |
418 | cpu_srH = tcg_global_mem_new_i64(cpu_env, |
419 | offsetof(CPUHPPAState, sr[4]), | |
420 | sr_names[4]); | |
61766fe9 RH |
421 | |
422 | for (i = 0; i < ARRAY_SIZE(vars); ++i) { | |
423 | const GlobalVar *v = &vars[i]; | |
424 | *v->var = tcg_global_mem_new(cpu_env, v->ofs, v->name); | |
425 | } | |
c301f34e RH |
426 | |
427 | cpu_iasq_f = tcg_global_mem_new_i64(cpu_env, | |
428 | offsetof(CPUHPPAState, iasq_f), | |
429 | "iasq_f"); | |
430 | cpu_iasq_b = tcg_global_mem_new_i64(cpu_env, | |
431 | offsetof(CPUHPPAState, iasq_b), | |
432 | "iasq_b"); | |
61766fe9 RH |
433 | } |
434 | ||
129e9cc3 RH |
435 | static DisasCond cond_make_f(void) |
436 | { | |
f764718d RH |
437 | return (DisasCond){ |
438 | .c = TCG_COND_NEVER, | |
439 | .a0 = NULL, | |
440 | .a1 = NULL, | |
441 | }; | |
129e9cc3 RH |
442 | } |
443 | ||
df0232fe RH |
444 | static DisasCond cond_make_t(void) |
445 | { | |
446 | return (DisasCond){ | |
447 | .c = TCG_COND_ALWAYS, | |
448 | .a0 = NULL, | |
449 | .a1 = NULL, | |
450 | }; | |
451 | } | |
452 | ||
129e9cc3 RH |
453 | static DisasCond cond_make_n(void) |
454 | { | |
f764718d RH |
455 | return (DisasCond){ |
456 | .c = TCG_COND_NE, | |
457 | .a0 = cpu_psw_n, | |
6e94937a | 458 | .a1 = tcg_constant_reg(0) |
f764718d | 459 | }; |
129e9cc3 RH |
460 | } |
461 | ||
b47a4a02 | 462 | static DisasCond cond_make_0_tmp(TCGCond c, TCGv_reg a0) |
129e9cc3 | 463 | { |
129e9cc3 | 464 | assert (c != TCG_COND_NEVER && c != TCG_COND_ALWAYS); |
b47a4a02 | 465 | return (DisasCond){ |
6e94937a | 466 | .c = c, .a0 = a0, .a1 = tcg_constant_reg(0) |
b47a4a02 SS |
467 | }; |
468 | } | |
129e9cc3 | 469 | |
b47a4a02 SS |
470 | static DisasCond cond_make_0(TCGCond c, TCGv_reg a0) |
471 | { | |
472 | TCGv_reg tmp = tcg_temp_new(); | |
473 | tcg_gen_mov_reg(tmp, a0); | |
474 | return cond_make_0_tmp(c, tmp); | |
129e9cc3 RH |
475 | } |
476 | ||
eaa3783b | 477 | static DisasCond cond_make(TCGCond c, TCGv_reg a0, TCGv_reg a1) |
129e9cc3 RH |
478 | { |
479 | DisasCond r = { .c = c }; | |
480 | ||
481 | assert (c != TCG_COND_NEVER && c != TCG_COND_ALWAYS); | |
482 | r.a0 = tcg_temp_new(); | |
eaa3783b | 483 | tcg_gen_mov_reg(r.a0, a0); |
129e9cc3 | 484 | r.a1 = tcg_temp_new(); |
eaa3783b | 485 | tcg_gen_mov_reg(r.a1, a1); |
129e9cc3 RH |
486 | |
487 | return r; | |
488 | } | |
489 | ||
129e9cc3 RH |
490 | static void cond_free(DisasCond *cond) |
491 | { | |
492 | switch (cond->c) { | |
493 | default: | |
6e94937a | 494 | if (cond->a0 != cpu_psw_n) { |
129e9cc3 RH |
495 | tcg_temp_free(cond->a0); |
496 | } | |
6e94937a | 497 | tcg_temp_free(cond->a1); |
f764718d RH |
498 | cond->a0 = NULL; |
499 | cond->a1 = NULL; | |
129e9cc3 RH |
500 | /* fallthru */ |
501 | case TCG_COND_ALWAYS: | |
502 | cond->c = TCG_COND_NEVER; | |
503 | break; | |
504 | case TCG_COND_NEVER: | |
505 | break; | |
506 | } | |
507 | } | |
508 | ||
eaa3783b | 509 | static TCGv_reg get_temp(DisasContext *ctx) |
61766fe9 | 510 | { |
86f8d05f RH |
511 | unsigned i = ctx->ntempr++; |
512 | g_assert(i < ARRAY_SIZE(ctx->tempr)); | |
513 | return ctx->tempr[i] = tcg_temp_new(); | |
61766fe9 RH |
514 | } |
515 | ||
86f8d05f RH |
516 | #ifndef CONFIG_USER_ONLY |
517 | static TCGv_tl get_temp_tl(DisasContext *ctx) | |
518 | { | |
519 | unsigned i = ctx->ntempl++; | |
520 | g_assert(i < ARRAY_SIZE(ctx->templ)); | |
521 | return ctx->templ[i] = tcg_temp_new_tl(); | |
522 | } | |
523 | #endif | |
524 | ||
eaa3783b | 525 | static TCGv_reg load_const(DisasContext *ctx, target_sreg v) |
61766fe9 | 526 | { |
eaa3783b RH |
527 | TCGv_reg t = get_temp(ctx); |
528 | tcg_gen_movi_reg(t, v); | |
61766fe9 RH |
529 | return t; |
530 | } | |
531 | ||
eaa3783b | 532 | static TCGv_reg load_gpr(DisasContext *ctx, unsigned reg) |
61766fe9 RH |
533 | { |
534 | if (reg == 0) { | |
eaa3783b RH |
535 | TCGv_reg t = get_temp(ctx); |
536 | tcg_gen_movi_reg(t, 0); | |
61766fe9 RH |
537 | return t; |
538 | } else { | |
539 | return cpu_gr[reg]; | |
540 | } | |
541 | } | |
542 | ||
eaa3783b | 543 | static TCGv_reg dest_gpr(DisasContext *ctx, unsigned reg) |
61766fe9 | 544 | { |
129e9cc3 | 545 | if (reg == 0 || ctx->null_cond.c != TCG_COND_NEVER) { |
61766fe9 RH |
546 | return get_temp(ctx); |
547 | } else { | |
548 | return cpu_gr[reg]; | |
549 | } | |
550 | } | |
551 | ||
eaa3783b | 552 | static void save_or_nullify(DisasContext *ctx, TCGv_reg dest, TCGv_reg t) |
129e9cc3 RH |
553 | { |
554 | if (ctx->null_cond.c != TCG_COND_NEVER) { | |
eaa3783b | 555 | tcg_gen_movcond_reg(ctx->null_cond.c, dest, ctx->null_cond.a0, |
6e94937a | 556 | ctx->null_cond.a1, dest, t); |
129e9cc3 | 557 | } else { |
eaa3783b | 558 | tcg_gen_mov_reg(dest, t); |
129e9cc3 RH |
559 | } |
560 | } | |
561 | ||
eaa3783b | 562 | static void save_gpr(DisasContext *ctx, unsigned reg, TCGv_reg t) |
129e9cc3 RH |
563 | { |
564 | if (reg != 0) { | |
565 | save_or_nullify(ctx, cpu_gr[reg], t); | |
566 | } | |
567 | } | |
568 | ||
e03b5686 | 569 | #if HOST_BIG_ENDIAN |
96d6407f RH |
570 | # define HI_OFS 0 |
571 | # define LO_OFS 4 | |
572 | #else | |
573 | # define HI_OFS 4 | |
574 | # define LO_OFS 0 | |
575 | #endif | |
576 | ||
577 | static TCGv_i32 load_frw_i32(unsigned rt) | |
578 | { | |
579 | TCGv_i32 ret = tcg_temp_new_i32(); | |
580 | tcg_gen_ld_i32(ret, cpu_env, | |
581 | offsetof(CPUHPPAState, fr[rt & 31]) | |
582 | + (rt & 32 ? LO_OFS : HI_OFS)); | |
583 | return ret; | |
584 | } | |
585 | ||
ebe9383c RH |
586 | static TCGv_i32 load_frw0_i32(unsigned rt) |
587 | { | |
588 | if (rt == 0) { | |
589 | return tcg_const_i32(0); | |
590 | } else { | |
591 | return load_frw_i32(rt); | |
592 | } | |
593 | } | |
594 | ||
595 | static TCGv_i64 load_frw0_i64(unsigned rt) | |
596 | { | |
597 | if (rt == 0) { | |
598 | return tcg_const_i64(0); | |
599 | } else { | |
600 | TCGv_i64 ret = tcg_temp_new_i64(); | |
601 | tcg_gen_ld32u_i64(ret, cpu_env, | |
602 | offsetof(CPUHPPAState, fr[rt & 31]) | |
603 | + (rt & 32 ? LO_OFS : HI_OFS)); | |
604 | return ret; | |
605 | } | |
606 | } | |
607 | ||
96d6407f RH |
608 | static void save_frw_i32(unsigned rt, TCGv_i32 val) |
609 | { | |
610 | tcg_gen_st_i32(val, cpu_env, | |
611 | offsetof(CPUHPPAState, fr[rt & 31]) | |
612 | + (rt & 32 ? LO_OFS : HI_OFS)); | |
613 | } | |
614 | ||
615 | #undef HI_OFS | |
616 | #undef LO_OFS | |
617 | ||
618 | static TCGv_i64 load_frd(unsigned rt) | |
619 | { | |
620 | TCGv_i64 ret = tcg_temp_new_i64(); | |
621 | tcg_gen_ld_i64(ret, cpu_env, offsetof(CPUHPPAState, fr[rt])); | |
622 | return ret; | |
623 | } | |
624 | ||
ebe9383c RH |
625 | static TCGv_i64 load_frd0(unsigned rt) |
626 | { | |
627 | if (rt == 0) { | |
628 | return tcg_const_i64(0); | |
629 | } else { | |
630 | return load_frd(rt); | |
631 | } | |
632 | } | |
633 | ||
96d6407f RH |
634 | static void save_frd(unsigned rt, TCGv_i64 val) |
635 | { | |
636 | tcg_gen_st_i64(val, cpu_env, offsetof(CPUHPPAState, fr[rt])); | |
637 | } | |
638 | ||
33423472 RH |
639 | static void load_spr(DisasContext *ctx, TCGv_i64 dest, unsigned reg) |
640 | { | |
641 | #ifdef CONFIG_USER_ONLY | |
642 | tcg_gen_movi_i64(dest, 0); | |
643 | #else | |
644 | if (reg < 4) { | |
645 | tcg_gen_mov_i64(dest, cpu_sr[reg]); | |
494737b7 RH |
646 | } else if (ctx->tb_flags & TB_FLAG_SR_SAME) { |
647 | tcg_gen_mov_i64(dest, cpu_srH); | |
33423472 RH |
648 | } else { |
649 | tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUHPPAState, sr[reg])); | |
650 | } | |
651 | #endif | |
652 | } | |
653 | ||
129e9cc3 RH |
654 | /* Skip over the implementation of an insn that has been nullified. |
655 | Use this when the insn is too complex for a conditional move. */ | |
656 | static void nullify_over(DisasContext *ctx) | |
657 | { | |
658 | if (ctx->null_cond.c != TCG_COND_NEVER) { | |
659 | /* The always condition should have been handled in the main loop. */ | |
660 | assert(ctx->null_cond.c != TCG_COND_ALWAYS); | |
661 | ||
662 | ctx->null_lab = gen_new_label(); | |
129e9cc3 RH |
663 | |
664 | /* If we're using PSW[N], copy it to a temp because... */ | |
6e94937a | 665 | if (ctx->null_cond.a0 == cpu_psw_n) { |
129e9cc3 | 666 | ctx->null_cond.a0 = tcg_temp_new(); |
eaa3783b | 667 | tcg_gen_mov_reg(ctx->null_cond.a0, cpu_psw_n); |
129e9cc3 RH |
668 | } |
669 | /* ... we clear it before branching over the implementation, | |
670 | so that (1) it's clear after nullifying this insn and | |
671 | (2) if this insn nullifies the next, PSW[N] is valid. */ | |
672 | if (ctx->psw_n_nonzero) { | |
673 | ctx->psw_n_nonzero = false; | |
eaa3783b | 674 | tcg_gen_movi_reg(cpu_psw_n, 0); |
129e9cc3 RH |
675 | } |
676 | ||
eaa3783b | 677 | tcg_gen_brcond_reg(ctx->null_cond.c, ctx->null_cond.a0, |
6e94937a | 678 | ctx->null_cond.a1, ctx->null_lab); |
129e9cc3 RH |
679 | cond_free(&ctx->null_cond); |
680 | } | |
681 | } | |
682 | ||
683 | /* Save the current nullification state to PSW[N]. */ | |
684 | static void nullify_save(DisasContext *ctx) | |
685 | { | |
686 | if (ctx->null_cond.c == TCG_COND_NEVER) { | |
687 | if (ctx->psw_n_nonzero) { | |
eaa3783b | 688 | tcg_gen_movi_reg(cpu_psw_n, 0); |
129e9cc3 RH |
689 | } |
690 | return; | |
691 | } | |
6e94937a | 692 | if (ctx->null_cond.a0 != cpu_psw_n) { |
eaa3783b | 693 | tcg_gen_setcond_reg(ctx->null_cond.c, cpu_psw_n, |
6e94937a | 694 | ctx->null_cond.a0, ctx->null_cond.a1); |
129e9cc3 RH |
695 | ctx->psw_n_nonzero = true; |
696 | } | |
697 | cond_free(&ctx->null_cond); | |
698 | } | |
699 | ||
700 | /* Set a PSW[N] to X. The intention is that this is used immediately | |
701 | before a goto_tb/exit_tb, so that there is no fallthru path to other | |
702 | code within the TB. Therefore we do not update psw_n_nonzero. */ | |
703 | static void nullify_set(DisasContext *ctx, bool x) | |
704 | { | |
705 | if (ctx->psw_n_nonzero || x) { | |
eaa3783b | 706 | tcg_gen_movi_reg(cpu_psw_n, x); |
129e9cc3 RH |
707 | } |
708 | } | |
709 | ||
710 | /* Mark the end of an instruction that may have been nullified. | |
40f9f908 RH |
711 | This is the pair to nullify_over. Always returns true so that |
712 | it may be tail-called from a translate function. */ | |
31234768 | 713 | static bool nullify_end(DisasContext *ctx) |
129e9cc3 RH |
714 | { |
715 | TCGLabel *null_lab = ctx->null_lab; | |
31234768 | 716 | DisasJumpType status = ctx->base.is_jmp; |
129e9cc3 | 717 | |
f49b3537 RH |
718 | /* For NEXT, NORETURN, STALE, we can easily continue (or exit). |
719 | For UPDATED, we cannot update on the nullified path. */ | |
720 | assert(status != DISAS_IAQ_N_UPDATED); | |
721 | ||
129e9cc3 RH |
722 | if (likely(null_lab == NULL)) { |
723 | /* The current insn wasn't conditional or handled the condition | |
724 | applied to it without a branch, so the (new) setting of | |
725 | NULL_COND can be applied directly to the next insn. */ | |
31234768 | 726 | return true; |
129e9cc3 RH |
727 | } |
728 | ctx->null_lab = NULL; | |
729 | ||
730 | if (likely(ctx->null_cond.c == TCG_COND_NEVER)) { | |
731 | /* The next instruction will be unconditional, | |
732 | and NULL_COND already reflects that. */ | |
733 | gen_set_label(null_lab); | |
734 | } else { | |
735 | /* The insn that we just executed is itself nullifying the next | |
736 | instruction. Store the condition in the PSW[N] global. | |
737 | We asserted PSW[N] = 0 in nullify_over, so that after the | |
738 | label we have the proper value in place. */ | |
739 | nullify_save(ctx); | |
740 | gen_set_label(null_lab); | |
741 | ctx->null_cond = cond_make_n(); | |
742 | } | |
869051ea | 743 | if (status == DISAS_NORETURN) { |
31234768 | 744 | ctx->base.is_jmp = DISAS_NEXT; |
129e9cc3 | 745 | } |
31234768 | 746 | return true; |
129e9cc3 RH |
747 | } |
748 | ||
eaa3783b | 749 | static void copy_iaoq_entry(TCGv_reg dest, target_ureg ival, TCGv_reg vval) |
61766fe9 RH |
750 | { |
751 | if (unlikely(ival == -1)) { | |
eaa3783b | 752 | tcg_gen_mov_reg(dest, vval); |
61766fe9 | 753 | } else { |
eaa3783b | 754 | tcg_gen_movi_reg(dest, ival); |
61766fe9 RH |
755 | } |
756 | } | |
757 | ||
eaa3783b | 758 | static inline target_ureg iaoq_dest(DisasContext *ctx, target_sreg disp) |
61766fe9 RH |
759 | { |
760 | return ctx->iaoq_f + disp + 8; | |
761 | } | |
762 | ||
763 | static void gen_excp_1(int exception) | |
764 | { | |
29dd6f64 | 765 | gen_helper_excp(cpu_env, tcg_constant_i32(exception)); |
61766fe9 RH |
766 | } |
767 | ||
31234768 | 768 | static void gen_excp(DisasContext *ctx, int exception) |
61766fe9 RH |
769 | { |
770 | copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_f, cpu_iaoq_f); | |
771 | copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_b, cpu_iaoq_b); | |
129e9cc3 | 772 | nullify_save(ctx); |
61766fe9 | 773 | gen_excp_1(exception); |
31234768 | 774 | ctx->base.is_jmp = DISAS_NORETURN; |
61766fe9 RH |
775 | } |
776 | ||
31234768 | 777 | static bool gen_excp_iir(DisasContext *ctx, int exc) |
1a19da0d | 778 | { |
31234768 | 779 | nullify_over(ctx); |
29dd6f64 RH |
780 | tcg_gen_st_reg(tcg_constant_reg(ctx->insn), |
781 | cpu_env, offsetof(CPUHPPAState, cr[CR_IIR])); | |
31234768 RH |
782 | gen_excp(ctx, exc); |
783 | return nullify_end(ctx); | |
1a19da0d RH |
784 | } |
785 | ||
31234768 | 786 | static bool gen_illegal(DisasContext *ctx) |
61766fe9 | 787 | { |
31234768 | 788 | return gen_excp_iir(ctx, EXCP_ILL); |
61766fe9 RH |
789 | } |
790 | ||
40f9f908 RH |
791 | #ifdef CONFIG_USER_ONLY |
792 | #define CHECK_MOST_PRIVILEGED(EXCP) \ | |
793 | return gen_excp_iir(ctx, EXCP) | |
794 | #else | |
795 | #define CHECK_MOST_PRIVILEGED(EXCP) \ | |
31234768 RH |
796 | do { \ |
797 | if (ctx->privilege != 0) { \ | |
798 | return gen_excp_iir(ctx, EXCP); \ | |
799 | } \ | |
e1b5a5ed | 800 | } while (0) |
40f9f908 | 801 | #endif |
e1b5a5ed | 802 | |
eaa3783b | 803 | static bool use_goto_tb(DisasContext *ctx, target_ureg dest) |
61766fe9 | 804 | { |
57f91498 | 805 | return translator_use_goto_tb(&ctx->base, dest); |
61766fe9 RH |
806 | } |
807 | ||
129e9cc3 RH |
808 | /* If the next insn is to be nullified, and it's on the same page, |
809 | and we're not attempting to set a breakpoint on it, then we can | |
810 | totally skip the nullified insn. This avoids creating and | |
811 | executing a TB that merely branches to the next TB. */ | |
812 | static bool use_nullify_skip(DisasContext *ctx) | |
813 | { | |
814 | return (((ctx->iaoq_b ^ ctx->iaoq_f) & TARGET_PAGE_MASK) == 0 | |
815 | && !cpu_breakpoint_test(ctx->cs, ctx->iaoq_b, BP_ANY)); | |
816 | } | |
817 | ||
61766fe9 | 818 | static void gen_goto_tb(DisasContext *ctx, int which, |
eaa3783b | 819 | target_ureg f, target_ureg b) |
61766fe9 RH |
820 | { |
821 | if (f != -1 && b != -1 && use_goto_tb(ctx, f)) { | |
822 | tcg_gen_goto_tb(which); | |
eaa3783b RH |
823 | tcg_gen_movi_reg(cpu_iaoq_f, f); |
824 | tcg_gen_movi_reg(cpu_iaoq_b, b); | |
07ea28b4 | 825 | tcg_gen_exit_tb(ctx->base.tb, which); |
61766fe9 RH |
826 | } else { |
827 | copy_iaoq_entry(cpu_iaoq_f, f, cpu_iaoq_b); | |
828 | copy_iaoq_entry(cpu_iaoq_b, b, ctx->iaoq_n_var); | |
8532a14e | 829 | tcg_gen_lookup_and_goto_ptr(); |
61766fe9 RH |
830 | } |
831 | } | |
832 | ||
b47a4a02 SS |
833 | static bool cond_need_sv(int c) |
834 | { | |
835 | return c == 2 || c == 3 || c == 6; | |
836 | } | |
837 | ||
838 | static bool cond_need_cb(int c) | |
839 | { | |
840 | return c == 4 || c == 5; | |
841 | } | |
842 | ||
843 | /* | |
844 | * Compute conditional for arithmetic. See Page 5-3, Table 5-1, of | |
845 | * the Parisc 1.1 Architecture Reference Manual for details. | |
846 | */ | |
b2167459 | 847 | |
eaa3783b RH |
848 | static DisasCond do_cond(unsigned cf, TCGv_reg res, |
849 | TCGv_reg cb_msb, TCGv_reg sv) | |
b2167459 RH |
850 | { |
851 | DisasCond cond; | |
eaa3783b | 852 | TCGv_reg tmp; |
b2167459 RH |
853 | |
854 | switch (cf >> 1) { | |
b47a4a02 | 855 | case 0: /* Never / TR (0 / 1) */ |
b2167459 RH |
856 | cond = cond_make_f(); |
857 | break; | |
858 | case 1: /* = / <> (Z / !Z) */ | |
859 | cond = cond_make_0(TCG_COND_EQ, res); | |
860 | break; | |
b47a4a02 SS |
861 | case 2: /* < / >= (N ^ V / !(N ^ V) */ |
862 | tmp = tcg_temp_new(); | |
863 | tcg_gen_xor_reg(tmp, res, sv); | |
864 | cond = cond_make_0_tmp(TCG_COND_LT, tmp); | |
b2167459 | 865 | break; |
b47a4a02 SS |
866 | case 3: /* <= / > (N ^ V) | Z / !((N ^ V) | Z) */ |
867 | /* | |
868 | * Simplify: | |
869 | * (N ^ V) | Z | |
870 | * ((res < 0) ^ (sv < 0)) | !res | |
871 | * ((res ^ sv) < 0) | !res | |
872 | * (~(res ^ sv) >= 0) | !res | |
873 | * !(~(res ^ sv) >> 31) | !res | |
874 | * !(~(res ^ sv) >> 31 & res) | |
875 | */ | |
876 | tmp = tcg_temp_new(); | |
877 | tcg_gen_eqv_reg(tmp, res, sv); | |
878 | tcg_gen_sari_reg(tmp, tmp, TARGET_REGISTER_BITS - 1); | |
879 | tcg_gen_and_reg(tmp, tmp, res); | |
880 | cond = cond_make_0_tmp(TCG_COND_EQ, tmp); | |
b2167459 RH |
881 | break; |
882 | case 4: /* NUV / UV (!C / C) */ | |
883 | cond = cond_make_0(TCG_COND_EQ, cb_msb); | |
884 | break; | |
885 | case 5: /* ZNV / VNZ (!C | Z / C & !Z) */ | |
886 | tmp = tcg_temp_new(); | |
eaa3783b RH |
887 | tcg_gen_neg_reg(tmp, cb_msb); |
888 | tcg_gen_and_reg(tmp, tmp, res); | |
b47a4a02 | 889 | cond = cond_make_0_tmp(TCG_COND_EQ, tmp); |
b2167459 RH |
890 | break; |
891 | case 6: /* SV / NSV (V / !V) */ | |
892 | cond = cond_make_0(TCG_COND_LT, sv); | |
893 | break; | |
894 | case 7: /* OD / EV */ | |
895 | tmp = tcg_temp_new(); | |
eaa3783b | 896 | tcg_gen_andi_reg(tmp, res, 1); |
b47a4a02 | 897 | cond = cond_make_0_tmp(TCG_COND_NE, tmp); |
b2167459 RH |
898 | break; |
899 | default: | |
900 | g_assert_not_reached(); | |
901 | } | |
902 | if (cf & 1) { | |
903 | cond.c = tcg_invert_cond(cond.c); | |
904 | } | |
905 | ||
906 | return cond; | |
907 | } | |
908 | ||
909 | /* Similar, but for the special case of subtraction without borrow, we | |
910 | can use the inputs directly. This can allow other computation to be | |
911 | deleted as unused. */ | |
912 | ||
eaa3783b RH |
913 | static DisasCond do_sub_cond(unsigned cf, TCGv_reg res, |
914 | TCGv_reg in1, TCGv_reg in2, TCGv_reg sv) | |
b2167459 RH |
915 | { |
916 | DisasCond cond; | |
917 | ||
918 | switch (cf >> 1) { | |
919 | case 1: /* = / <> */ | |
920 | cond = cond_make(TCG_COND_EQ, in1, in2); | |
921 | break; | |
922 | case 2: /* < / >= */ | |
923 | cond = cond_make(TCG_COND_LT, in1, in2); | |
924 | break; | |
925 | case 3: /* <= / > */ | |
926 | cond = cond_make(TCG_COND_LE, in1, in2); | |
927 | break; | |
928 | case 4: /* << / >>= */ | |
929 | cond = cond_make(TCG_COND_LTU, in1, in2); | |
930 | break; | |
931 | case 5: /* <<= / >> */ | |
932 | cond = cond_make(TCG_COND_LEU, in1, in2); | |
933 | break; | |
934 | default: | |
b47a4a02 | 935 | return do_cond(cf, res, NULL, sv); |
b2167459 RH |
936 | } |
937 | if (cf & 1) { | |
938 | cond.c = tcg_invert_cond(cond.c); | |
939 | } | |
940 | ||
941 | return cond; | |
942 | } | |
943 | ||
df0232fe RH |
944 | /* |
945 | * Similar, but for logicals, where the carry and overflow bits are not | |
946 | * computed, and use of them is undefined. | |
947 | * | |
948 | * Undefined or not, hardware does not trap. It seems reasonable to | |
949 | * assume hardware treats cases c={4,5,6} as if C=0 & V=0, since that's | |
950 | * how cases c={2,3} are treated. | |
951 | */ | |
b2167459 | 952 | |
eaa3783b | 953 | static DisasCond do_log_cond(unsigned cf, TCGv_reg res) |
b2167459 | 954 | { |
df0232fe RH |
955 | switch (cf) { |
956 | case 0: /* never */ | |
957 | case 9: /* undef, C */ | |
958 | case 11: /* undef, C & !Z */ | |
959 | case 12: /* undef, V */ | |
960 | return cond_make_f(); | |
961 | ||
962 | case 1: /* true */ | |
963 | case 8: /* undef, !C */ | |
964 | case 10: /* undef, !C | Z */ | |
965 | case 13: /* undef, !V */ | |
966 | return cond_make_t(); | |
967 | ||
968 | case 2: /* == */ | |
969 | return cond_make_0(TCG_COND_EQ, res); | |
970 | case 3: /* <> */ | |
971 | return cond_make_0(TCG_COND_NE, res); | |
972 | case 4: /* < */ | |
973 | return cond_make_0(TCG_COND_LT, res); | |
974 | case 5: /* >= */ | |
975 | return cond_make_0(TCG_COND_GE, res); | |
976 | case 6: /* <= */ | |
977 | return cond_make_0(TCG_COND_LE, res); | |
978 | case 7: /* > */ | |
979 | return cond_make_0(TCG_COND_GT, res); | |
980 | ||
981 | case 14: /* OD */ | |
982 | case 15: /* EV */ | |
983 | return do_cond(cf, res, NULL, NULL); | |
984 | ||
985 | default: | |
986 | g_assert_not_reached(); | |
b2167459 | 987 | } |
b2167459 RH |
988 | } |
989 | ||
98cd9ca7 RH |
990 | /* Similar, but for shift/extract/deposit conditions. */ |
991 | ||
eaa3783b | 992 | static DisasCond do_sed_cond(unsigned orig, TCGv_reg res) |
98cd9ca7 RH |
993 | { |
994 | unsigned c, f; | |
995 | ||
996 | /* Convert the compressed condition codes to standard. | |
997 | 0-2 are the same as logicals (nv,<,<=), while 3 is OD. | |
998 | 4-7 are the reverse of 0-3. */ | |
999 | c = orig & 3; | |
1000 | if (c == 3) { | |
1001 | c = 7; | |
1002 | } | |
1003 | f = (orig & 4) / 4; | |
1004 | ||
1005 | return do_log_cond(c * 2 + f, res); | |
1006 | } | |
1007 | ||
b2167459 RH |
1008 | /* Similar, but for unit conditions. */ |
1009 | ||
eaa3783b RH |
1010 | static DisasCond do_unit_cond(unsigned cf, TCGv_reg res, |
1011 | TCGv_reg in1, TCGv_reg in2) | |
b2167459 RH |
1012 | { |
1013 | DisasCond cond; | |
eaa3783b | 1014 | TCGv_reg tmp, cb = NULL; |
b2167459 | 1015 | |
b2167459 RH |
1016 | if (cf & 8) { |
1017 | /* Since we want to test lots of carry-out bits all at once, do not | |
1018 | * do our normal thing and compute carry-in of bit B+1 since that | |
1019 | * leaves us with carry bits spread across two words. | |
1020 | */ | |
1021 | cb = tcg_temp_new(); | |
1022 | tmp = tcg_temp_new(); | |
eaa3783b RH |
1023 | tcg_gen_or_reg(cb, in1, in2); |
1024 | tcg_gen_and_reg(tmp, in1, in2); | |
1025 | tcg_gen_andc_reg(cb, cb, res); | |
1026 | tcg_gen_or_reg(cb, cb, tmp); | |
b2167459 RH |
1027 | tcg_temp_free(tmp); |
1028 | } | |
1029 | ||
1030 | switch (cf >> 1) { | |
1031 | case 0: /* never / TR */ | |
1032 | case 1: /* undefined */ | |
1033 | case 5: /* undefined */ | |
1034 | cond = cond_make_f(); | |
1035 | break; | |
1036 | ||
1037 | case 2: /* SBZ / NBZ */ | |
1038 | /* See hasless(v,1) from | |
1039 | * https://graphics.stanford.edu/~seander/bithacks.html#ZeroInWord | |
1040 | */ | |
1041 | tmp = tcg_temp_new(); | |
eaa3783b RH |
1042 | tcg_gen_subi_reg(tmp, res, 0x01010101u); |
1043 | tcg_gen_andc_reg(tmp, tmp, res); | |
1044 | tcg_gen_andi_reg(tmp, tmp, 0x80808080u); | |
b2167459 RH |
1045 | cond = cond_make_0(TCG_COND_NE, tmp); |
1046 | tcg_temp_free(tmp); | |
1047 | break; | |
1048 | ||
1049 | case 3: /* SHZ / NHZ */ | |
1050 | tmp = tcg_temp_new(); | |
eaa3783b RH |
1051 | tcg_gen_subi_reg(tmp, res, 0x00010001u); |
1052 | tcg_gen_andc_reg(tmp, tmp, res); | |
1053 | tcg_gen_andi_reg(tmp, tmp, 0x80008000u); | |
b2167459 RH |
1054 | cond = cond_make_0(TCG_COND_NE, tmp); |
1055 | tcg_temp_free(tmp); | |
1056 | break; | |
1057 | ||
1058 | case 4: /* SDC / NDC */ | |
eaa3783b | 1059 | tcg_gen_andi_reg(cb, cb, 0x88888888u); |
b2167459 RH |
1060 | cond = cond_make_0(TCG_COND_NE, cb); |
1061 | break; | |
1062 | ||
1063 | case 6: /* SBC / NBC */ | |
eaa3783b | 1064 | tcg_gen_andi_reg(cb, cb, 0x80808080u); |
b2167459 RH |
1065 | cond = cond_make_0(TCG_COND_NE, cb); |
1066 | break; | |
1067 | ||
1068 | case 7: /* SHC / NHC */ | |
eaa3783b | 1069 | tcg_gen_andi_reg(cb, cb, 0x80008000u); |
b2167459 RH |
1070 | cond = cond_make_0(TCG_COND_NE, cb); |
1071 | break; | |
1072 | ||
1073 | default: | |
1074 | g_assert_not_reached(); | |
1075 | } | |
1076 | if (cf & 8) { | |
1077 | tcg_temp_free(cb); | |
1078 | } | |
1079 | if (cf & 1) { | |
1080 | cond.c = tcg_invert_cond(cond.c); | |
1081 | } | |
1082 | ||
1083 | return cond; | |
1084 | } | |
1085 | ||
1086 | /* Compute signed overflow for addition. */ | |
eaa3783b RH |
1087 | static TCGv_reg do_add_sv(DisasContext *ctx, TCGv_reg res, |
1088 | TCGv_reg in1, TCGv_reg in2) | |
b2167459 | 1089 | { |
eaa3783b RH |
1090 | TCGv_reg sv = get_temp(ctx); |
1091 | TCGv_reg tmp = tcg_temp_new(); | |
b2167459 | 1092 | |
eaa3783b RH |
1093 | tcg_gen_xor_reg(sv, res, in1); |
1094 | tcg_gen_xor_reg(tmp, in1, in2); | |
1095 | tcg_gen_andc_reg(sv, sv, tmp); | |
b2167459 RH |
1096 | tcg_temp_free(tmp); |
1097 | ||
1098 | return sv; | |
1099 | } | |
1100 | ||
1101 | /* Compute signed overflow for subtraction. */ | |
eaa3783b RH |
1102 | static TCGv_reg do_sub_sv(DisasContext *ctx, TCGv_reg res, |
1103 | TCGv_reg in1, TCGv_reg in2) | |
b2167459 | 1104 | { |
eaa3783b RH |
1105 | TCGv_reg sv = get_temp(ctx); |
1106 | TCGv_reg tmp = tcg_temp_new(); | |
b2167459 | 1107 | |
eaa3783b RH |
1108 | tcg_gen_xor_reg(sv, res, in1); |
1109 | tcg_gen_xor_reg(tmp, in1, in2); | |
1110 | tcg_gen_and_reg(sv, sv, tmp); | |
b2167459 RH |
1111 | tcg_temp_free(tmp); |
1112 | ||
1113 | return sv; | |
1114 | } | |
1115 | ||
31234768 RH |
1116 | static void do_add(DisasContext *ctx, unsigned rt, TCGv_reg in1, |
1117 | TCGv_reg in2, unsigned shift, bool is_l, | |
1118 | bool is_tsv, bool is_tc, bool is_c, unsigned cf) | |
b2167459 | 1119 | { |
eaa3783b | 1120 | TCGv_reg dest, cb, cb_msb, sv, tmp; |
b2167459 RH |
1121 | unsigned c = cf >> 1; |
1122 | DisasCond cond; | |
1123 | ||
1124 | dest = tcg_temp_new(); | |
f764718d RH |
1125 | cb = NULL; |
1126 | cb_msb = NULL; | |
b2167459 RH |
1127 | |
1128 | if (shift) { | |
1129 | tmp = get_temp(ctx); | |
eaa3783b | 1130 | tcg_gen_shli_reg(tmp, in1, shift); |
b2167459 RH |
1131 | in1 = tmp; |
1132 | } | |
1133 | ||
b47a4a02 | 1134 | if (!is_l || cond_need_cb(c)) { |
29dd6f64 | 1135 | TCGv_reg zero = tcg_constant_reg(0); |
b2167459 | 1136 | cb_msb = get_temp(ctx); |
eaa3783b | 1137 | tcg_gen_add2_reg(dest, cb_msb, in1, zero, in2, zero); |
b2167459 | 1138 | if (is_c) { |
eaa3783b | 1139 | tcg_gen_add2_reg(dest, cb_msb, dest, cb_msb, cpu_psw_cb_msb, zero); |
b2167459 | 1140 | } |
b2167459 RH |
1141 | if (!is_l) { |
1142 | cb = get_temp(ctx); | |
eaa3783b RH |
1143 | tcg_gen_xor_reg(cb, in1, in2); |
1144 | tcg_gen_xor_reg(cb, cb, dest); | |
b2167459 RH |
1145 | } |
1146 | } else { | |
eaa3783b | 1147 | tcg_gen_add_reg(dest, in1, in2); |
b2167459 | 1148 | if (is_c) { |
eaa3783b | 1149 | tcg_gen_add_reg(dest, dest, cpu_psw_cb_msb); |
b2167459 RH |
1150 | } |
1151 | } | |
1152 | ||
1153 | /* Compute signed overflow if required. */ | |
f764718d | 1154 | sv = NULL; |
b47a4a02 | 1155 | if (is_tsv || cond_need_sv(c)) { |
b2167459 RH |
1156 | sv = do_add_sv(ctx, dest, in1, in2); |
1157 | if (is_tsv) { | |
1158 | /* ??? Need to include overflow from shift. */ | |
1159 | gen_helper_tsv(cpu_env, sv); | |
1160 | } | |
1161 | } | |
1162 | ||
1163 | /* Emit any conditional trap before any writeback. */ | |
1164 | cond = do_cond(cf, dest, cb_msb, sv); | |
1165 | if (is_tc) { | |
b2167459 | 1166 | tmp = tcg_temp_new(); |
eaa3783b | 1167 | tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); |
b2167459 RH |
1168 | gen_helper_tcond(cpu_env, tmp); |
1169 | tcg_temp_free(tmp); | |
1170 | } | |
1171 | ||
1172 | /* Write back the result. */ | |
1173 | if (!is_l) { | |
1174 | save_or_nullify(ctx, cpu_psw_cb, cb); | |
1175 | save_or_nullify(ctx, cpu_psw_cb_msb, cb_msb); | |
1176 | } | |
1177 | save_gpr(ctx, rt, dest); | |
1178 | tcg_temp_free(dest); | |
1179 | ||
1180 | /* Install the new nullification. */ | |
1181 | cond_free(&ctx->null_cond); | |
1182 | ctx->null_cond = cond; | |
b2167459 RH |
1183 | } |
1184 | ||
0c982a28 RH |
1185 | static bool do_add_reg(DisasContext *ctx, arg_rrr_cf_sh *a, |
1186 | bool is_l, bool is_tsv, bool is_tc, bool is_c) | |
1187 | { | |
1188 | TCGv_reg tcg_r1, tcg_r2; | |
1189 | ||
1190 | if (a->cf) { | |
1191 | nullify_over(ctx); | |
1192 | } | |
1193 | tcg_r1 = load_gpr(ctx, a->r1); | |
1194 | tcg_r2 = load_gpr(ctx, a->r2); | |
1195 | do_add(ctx, a->t, tcg_r1, tcg_r2, a->sh, is_l, is_tsv, is_tc, is_c, a->cf); | |
1196 | return nullify_end(ctx); | |
1197 | } | |
1198 | ||
0588e061 RH |
1199 | static bool do_add_imm(DisasContext *ctx, arg_rri_cf *a, |
1200 | bool is_tsv, bool is_tc) | |
1201 | { | |
1202 | TCGv_reg tcg_im, tcg_r2; | |
1203 | ||
1204 | if (a->cf) { | |
1205 | nullify_over(ctx); | |
1206 | } | |
1207 | tcg_im = load_const(ctx, a->i); | |
1208 | tcg_r2 = load_gpr(ctx, a->r); | |
1209 | do_add(ctx, a->t, tcg_im, tcg_r2, 0, 0, is_tsv, is_tc, 0, a->cf); | |
1210 | return nullify_end(ctx); | |
1211 | } | |
1212 | ||
31234768 RH |
1213 | static void do_sub(DisasContext *ctx, unsigned rt, TCGv_reg in1, |
1214 | TCGv_reg in2, bool is_tsv, bool is_b, | |
1215 | bool is_tc, unsigned cf) | |
b2167459 | 1216 | { |
eaa3783b | 1217 | TCGv_reg dest, sv, cb, cb_msb, zero, tmp; |
b2167459 RH |
1218 | unsigned c = cf >> 1; |
1219 | DisasCond cond; | |
1220 | ||
1221 | dest = tcg_temp_new(); | |
1222 | cb = tcg_temp_new(); | |
1223 | cb_msb = tcg_temp_new(); | |
1224 | ||
29dd6f64 | 1225 | zero = tcg_constant_reg(0); |
b2167459 RH |
1226 | if (is_b) { |
1227 | /* DEST,C = IN1 + ~IN2 + C. */ | |
eaa3783b RH |
1228 | tcg_gen_not_reg(cb, in2); |
1229 | tcg_gen_add2_reg(dest, cb_msb, in1, zero, cpu_psw_cb_msb, zero); | |
1230 | tcg_gen_add2_reg(dest, cb_msb, dest, cb_msb, cb, zero); | |
1231 | tcg_gen_xor_reg(cb, cb, in1); | |
1232 | tcg_gen_xor_reg(cb, cb, dest); | |
b2167459 RH |
1233 | } else { |
1234 | /* DEST,C = IN1 + ~IN2 + 1. We can produce the same result in fewer | |
1235 | operations by seeding the high word with 1 and subtracting. */ | |
eaa3783b RH |
1236 | tcg_gen_movi_reg(cb_msb, 1); |
1237 | tcg_gen_sub2_reg(dest, cb_msb, in1, cb_msb, in2, zero); | |
1238 | tcg_gen_eqv_reg(cb, in1, in2); | |
1239 | tcg_gen_xor_reg(cb, cb, dest); | |
b2167459 | 1240 | } |
b2167459 RH |
1241 | |
1242 | /* Compute signed overflow if required. */ | |
f764718d | 1243 | sv = NULL; |
b47a4a02 | 1244 | if (is_tsv || cond_need_sv(c)) { |
b2167459 RH |
1245 | sv = do_sub_sv(ctx, dest, in1, in2); |
1246 | if (is_tsv) { | |
1247 | gen_helper_tsv(cpu_env, sv); | |
1248 | } | |
1249 | } | |
1250 | ||
1251 | /* Compute the condition. We cannot use the special case for borrow. */ | |
1252 | if (!is_b) { | |
1253 | cond = do_sub_cond(cf, dest, in1, in2, sv); | |
1254 | } else { | |
1255 | cond = do_cond(cf, dest, cb_msb, sv); | |
1256 | } | |
1257 | ||
1258 | /* Emit any conditional trap before any writeback. */ | |
1259 | if (is_tc) { | |
b2167459 | 1260 | tmp = tcg_temp_new(); |
eaa3783b | 1261 | tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); |
b2167459 RH |
1262 | gen_helper_tcond(cpu_env, tmp); |
1263 | tcg_temp_free(tmp); | |
1264 | } | |
1265 | ||
1266 | /* Write back the result. */ | |
1267 | save_or_nullify(ctx, cpu_psw_cb, cb); | |
1268 | save_or_nullify(ctx, cpu_psw_cb_msb, cb_msb); | |
1269 | save_gpr(ctx, rt, dest); | |
1270 | tcg_temp_free(dest); | |
79826f99 RH |
1271 | tcg_temp_free(cb); |
1272 | tcg_temp_free(cb_msb); | |
b2167459 RH |
1273 | |
1274 | /* Install the new nullification. */ | |
1275 | cond_free(&ctx->null_cond); | |
1276 | ctx->null_cond = cond; | |
b2167459 RH |
1277 | } |
1278 | ||
0c982a28 RH |
1279 | static bool do_sub_reg(DisasContext *ctx, arg_rrr_cf *a, |
1280 | bool is_tsv, bool is_b, bool is_tc) | |
1281 | { | |
1282 | TCGv_reg tcg_r1, tcg_r2; | |
1283 | ||
1284 | if (a->cf) { | |
1285 | nullify_over(ctx); | |
1286 | } | |
1287 | tcg_r1 = load_gpr(ctx, a->r1); | |
1288 | tcg_r2 = load_gpr(ctx, a->r2); | |
1289 | do_sub(ctx, a->t, tcg_r1, tcg_r2, is_tsv, is_b, is_tc, a->cf); | |
1290 | return nullify_end(ctx); | |
1291 | } | |
1292 | ||
0588e061 RH |
1293 | static bool do_sub_imm(DisasContext *ctx, arg_rri_cf *a, bool is_tsv) |
1294 | { | |
1295 | TCGv_reg tcg_im, tcg_r2; | |
1296 | ||
1297 | if (a->cf) { | |
1298 | nullify_over(ctx); | |
1299 | } | |
1300 | tcg_im = load_const(ctx, a->i); | |
1301 | tcg_r2 = load_gpr(ctx, a->r); | |
1302 | do_sub(ctx, a->t, tcg_im, tcg_r2, is_tsv, 0, 0, a->cf); | |
1303 | return nullify_end(ctx); | |
1304 | } | |
1305 | ||
31234768 RH |
1306 | static void do_cmpclr(DisasContext *ctx, unsigned rt, TCGv_reg in1, |
1307 | TCGv_reg in2, unsigned cf) | |
b2167459 | 1308 | { |
eaa3783b | 1309 | TCGv_reg dest, sv; |
b2167459 RH |
1310 | DisasCond cond; |
1311 | ||
1312 | dest = tcg_temp_new(); | |
eaa3783b | 1313 | tcg_gen_sub_reg(dest, in1, in2); |
b2167459 RH |
1314 | |
1315 | /* Compute signed overflow if required. */ | |
f764718d | 1316 | sv = NULL; |
b47a4a02 | 1317 | if (cond_need_sv(cf >> 1)) { |
b2167459 RH |
1318 | sv = do_sub_sv(ctx, dest, in1, in2); |
1319 | } | |
1320 | ||
1321 | /* Form the condition for the compare. */ | |
1322 | cond = do_sub_cond(cf, dest, in1, in2, sv); | |
1323 | ||
1324 | /* Clear. */ | |
eaa3783b | 1325 | tcg_gen_movi_reg(dest, 0); |
b2167459 RH |
1326 | save_gpr(ctx, rt, dest); |
1327 | tcg_temp_free(dest); | |
1328 | ||
1329 | /* Install the new nullification. */ | |
1330 | cond_free(&ctx->null_cond); | |
1331 | ctx->null_cond = cond; | |
b2167459 RH |
1332 | } |
1333 | ||
31234768 RH |
1334 | static void do_log(DisasContext *ctx, unsigned rt, TCGv_reg in1, |
1335 | TCGv_reg in2, unsigned cf, | |
1336 | void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) | |
b2167459 | 1337 | { |
eaa3783b | 1338 | TCGv_reg dest = dest_gpr(ctx, rt); |
b2167459 RH |
1339 | |
1340 | /* Perform the operation, and writeback. */ | |
1341 | fn(dest, in1, in2); | |
1342 | save_gpr(ctx, rt, dest); | |
1343 | ||
1344 | /* Install the new nullification. */ | |
1345 | cond_free(&ctx->null_cond); | |
1346 | if (cf) { | |
1347 | ctx->null_cond = do_log_cond(cf, dest); | |
1348 | } | |
b2167459 RH |
1349 | } |
1350 | ||
0c982a28 RH |
1351 | static bool do_log_reg(DisasContext *ctx, arg_rrr_cf *a, |
1352 | void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) | |
1353 | { | |
1354 | TCGv_reg tcg_r1, tcg_r2; | |
1355 | ||
1356 | if (a->cf) { | |
1357 | nullify_over(ctx); | |
1358 | } | |
1359 | tcg_r1 = load_gpr(ctx, a->r1); | |
1360 | tcg_r2 = load_gpr(ctx, a->r2); | |
1361 | do_log(ctx, a->t, tcg_r1, tcg_r2, a->cf, fn); | |
1362 | return nullify_end(ctx); | |
1363 | } | |
1364 | ||
31234768 RH |
1365 | static void do_unit(DisasContext *ctx, unsigned rt, TCGv_reg in1, |
1366 | TCGv_reg in2, unsigned cf, bool is_tc, | |
1367 | void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) | |
b2167459 | 1368 | { |
eaa3783b | 1369 | TCGv_reg dest; |
b2167459 RH |
1370 | DisasCond cond; |
1371 | ||
1372 | if (cf == 0) { | |
1373 | dest = dest_gpr(ctx, rt); | |
1374 | fn(dest, in1, in2); | |
1375 | save_gpr(ctx, rt, dest); | |
1376 | cond_free(&ctx->null_cond); | |
1377 | } else { | |
1378 | dest = tcg_temp_new(); | |
1379 | fn(dest, in1, in2); | |
1380 | ||
1381 | cond = do_unit_cond(cf, dest, in1, in2); | |
1382 | ||
1383 | if (is_tc) { | |
eaa3783b | 1384 | TCGv_reg tmp = tcg_temp_new(); |
eaa3783b | 1385 | tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); |
b2167459 RH |
1386 | gen_helper_tcond(cpu_env, tmp); |
1387 | tcg_temp_free(tmp); | |
1388 | } | |
1389 | save_gpr(ctx, rt, dest); | |
1390 | ||
1391 | cond_free(&ctx->null_cond); | |
1392 | ctx->null_cond = cond; | |
1393 | } | |
b2167459 RH |
1394 | } |
1395 | ||
86f8d05f | 1396 | #ifndef CONFIG_USER_ONLY |
8d6ae7fb RH |
1397 | /* The "normal" usage is SP >= 0, wherein SP == 0 selects the space |
1398 | from the top 2 bits of the base register. There are a few system | |
1399 | instructions that have a 3-bit space specifier, for which SR0 is | |
1400 | not special. To handle this, pass ~SP. */ | |
86f8d05f RH |
1401 | static TCGv_i64 space_select(DisasContext *ctx, int sp, TCGv_reg base) |
1402 | { | |
1403 | TCGv_ptr ptr; | |
1404 | TCGv_reg tmp; | |
1405 | TCGv_i64 spc; | |
1406 | ||
1407 | if (sp != 0) { | |
8d6ae7fb RH |
1408 | if (sp < 0) { |
1409 | sp = ~sp; | |
1410 | } | |
1411 | spc = get_temp_tl(ctx); | |
1412 | load_spr(ctx, spc, sp); | |
1413 | return spc; | |
86f8d05f | 1414 | } |
494737b7 RH |
1415 | if (ctx->tb_flags & TB_FLAG_SR_SAME) { |
1416 | return cpu_srH; | |
1417 | } | |
86f8d05f RH |
1418 | |
1419 | ptr = tcg_temp_new_ptr(); | |
1420 | tmp = tcg_temp_new(); | |
1421 | spc = get_temp_tl(ctx); | |
1422 | ||
1423 | tcg_gen_shri_reg(tmp, base, TARGET_REGISTER_BITS - 5); | |
1424 | tcg_gen_andi_reg(tmp, tmp, 030); | |
1425 | tcg_gen_trunc_reg_ptr(ptr, tmp); | |
1426 | tcg_temp_free(tmp); | |
1427 | ||
1428 | tcg_gen_add_ptr(ptr, ptr, cpu_env); | |
1429 | tcg_gen_ld_i64(spc, ptr, offsetof(CPUHPPAState, sr[4])); | |
1430 | tcg_temp_free_ptr(ptr); | |
1431 | ||
1432 | return spc; | |
1433 | } | |
1434 | #endif | |
1435 | ||
1436 | static void form_gva(DisasContext *ctx, TCGv_tl *pgva, TCGv_reg *pofs, | |
1437 | unsigned rb, unsigned rx, int scale, target_sreg disp, | |
1438 | unsigned sp, int modify, bool is_phys) | |
1439 | { | |
1440 | TCGv_reg base = load_gpr(ctx, rb); | |
1441 | TCGv_reg ofs; | |
1442 | ||
1443 | /* Note that RX is mutually exclusive with DISP. */ | |
1444 | if (rx) { | |
1445 | ofs = get_temp(ctx); | |
1446 | tcg_gen_shli_reg(ofs, cpu_gr[rx], scale); | |
1447 | tcg_gen_add_reg(ofs, ofs, base); | |
1448 | } else if (disp || modify) { | |
1449 | ofs = get_temp(ctx); | |
1450 | tcg_gen_addi_reg(ofs, base, disp); | |
1451 | } else { | |
1452 | ofs = base; | |
1453 | } | |
1454 | ||
1455 | *pofs = ofs; | |
1456 | #ifdef CONFIG_USER_ONLY | |
1457 | *pgva = (modify <= 0 ? ofs : base); | |
1458 | #else | |
1459 | TCGv_tl addr = get_temp_tl(ctx); | |
1460 | tcg_gen_extu_reg_tl(addr, modify <= 0 ? ofs : base); | |
494737b7 | 1461 | if (ctx->tb_flags & PSW_W) { |
86f8d05f RH |
1462 | tcg_gen_andi_tl(addr, addr, 0x3fffffffffffffffull); |
1463 | } | |
1464 | if (!is_phys) { | |
1465 | tcg_gen_or_tl(addr, addr, space_select(ctx, sp, base)); | |
1466 | } | |
1467 | *pgva = addr; | |
1468 | #endif | |
1469 | } | |
1470 | ||
96d6407f RH |
1471 | /* Emit a memory load. The modify parameter should be |
1472 | * < 0 for pre-modify, | |
1473 | * > 0 for post-modify, | |
1474 | * = 0 for no base register update. | |
1475 | */ | |
1476 | static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb, | |
eaa3783b | 1477 | unsigned rx, int scale, target_sreg disp, |
14776ab5 | 1478 | unsigned sp, int modify, MemOp mop) |
96d6407f | 1479 | { |
86f8d05f RH |
1480 | TCGv_reg ofs; |
1481 | TCGv_tl addr; | |
96d6407f RH |
1482 | |
1483 | /* Caller uses nullify_over/nullify_end. */ | |
1484 | assert(ctx->null_cond.c == TCG_COND_NEVER); | |
1485 | ||
86f8d05f RH |
1486 | form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, |
1487 | ctx->mmu_idx == MMU_PHYS_IDX); | |
217d1a5e | 1488 | tcg_gen_qemu_ld_reg(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); |
86f8d05f RH |
1489 | if (modify) { |
1490 | save_gpr(ctx, rb, ofs); | |
96d6407f | 1491 | } |
96d6407f RH |
1492 | } |
1493 | ||
1494 | static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb, | |
eaa3783b | 1495 | unsigned rx, int scale, target_sreg disp, |
14776ab5 | 1496 | unsigned sp, int modify, MemOp mop) |
96d6407f | 1497 | { |
86f8d05f RH |
1498 | TCGv_reg ofs; |
1499 | TCGv_tl addr; | |
96d6407f RH |
1500 | |
1501 | /* Caller uses nullify_over/nullify_end. */ | |
1502 | assert(ctx->null_cond.c == TCG_COND_NEVER); | |
1503 | ||
86f8d05f RH |
1504 | form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, |
1505 | ctx->mmu_idx == MMU_PHYS_IDX); | |
217d1a5e | 1506 | tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); |
86f8d05f RH |
1507 | if (modify) { |
1508 | save_gpr(ctx, rb, ofs); | |
96d6407f | 1509 | } |
96d6407f RH |
1510 | } |
1511 | ||
1512 | static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb, | |
eaa3783b | 1513 | unsigned rx, int scale, target_sreg disp, |
14776ab5 | 1514 | unsigned sp, int modify, MemOp mop) |
96d6407f | 1515 | { |
86f8d05f RH |
1516 | TCGv_reg ofs; |
1517 | TCGv_tl addr; | |
96d6407f RH |
1518 | |
1519 | /* Caller uses nullify_over/nullify_end. */ | |
1520 | assert(ctx->null_cond.c == TCG_COND_NEVER); | |
1521 | ||
86f8d05f RH |
1522 | form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, |
1523 | ctx->mmu_idx == MMU_PHYS_IDX); | |
217d1a5e | 1524 | tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); |
86f8d05f RH |
1525 | if (modify) { |
1526 | save_gpr(ctx, rb, ofs); | |
96d6407f | 1527 | } |
96d6407f RH |
1528 | } |
1529 | ||
1530 | static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb, | |
eaa3783b | 1531 | unsigned rx, int scale, target_sreg disp, |
14776ab5 | 1532 | unsigned sp, int modify, MemOp mop) |
96d6407f | 1533 | { |
86f8d05f RH |
1534 | TCGv_reg ofs; |
1535 | TCGv_tl addr; | |
96d6407f RH |
1536 | |
1537 | /* Caller uses nullify_over/nullify_end. */ | |
1538 | assert(ctx->null_cond.c == TCG_COND_NEVER); | |
1539 | ||
86f8d05f RH |
1540 | form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, |
1541 | ctx->mmu_idx == MMU_PHYS_IDX); | |
217d1a5e | 1542 | tcg_gen_qemu_st_i64(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); |
86f8d05f RH |
1543 | if (modify) { |
1544 | save_gpr(ctx, rb, ofs); | |
96d6407f | 1545 | } |
96d6407f RH |
1546 | } |
1547 | ||
eaa3783b RH |
1548 | #if TARGET_REGISTER_BITS == 64 |
1549 | #define do_load_reg do_load_64 | |
1550 | #define do_store_reg do_store_64 | |
96d6407f | 1551 | #else |
eaa3783b RH |
1552 | #define do_load_reg do_load_32 |
1553 | #define do_store_reg do_store_32 | |
96d6407f RH |
1554 | #endif |
1555 | ||
1cd012a5 | 1556 | static bool do_load(DisasContext *ctx, unsigned rt, unsigned rb, |
31234768 | 1557 | unsigned rx, int scale, target_sreg disp, |
14776ab5 | 1558 | unsigned sp, int modify, MemOp mop) |
96d6407f | 1559 | { |
eaa3783b | 1560 | TCGv_reg dest; |
96d6407f RH |
1561 | |
1562 | nullify_over(ctx); | |
1563 | ||
1564 | if (modify == 0) { | |
1565 | /* No base register update. */ | |
1566 | dest = dest_gpr(ctx, rt); | |
1567 | } else { | |
1568 | /* Make sure if RT == RB, we see the result of the load. */ | |
1569 | dest = get_temp(ctx); | |
1570 | } | |
86f8d05f | 1571 | do_load_reg(ctx, dest, rb, rx, scale, disp, sp, modify, mop); |
96d6407f RH |
1572 | save_gpr(ctx, rt, dest); |
1573 | ||
1cd012a5 | 1574 | return nullify_end(ctx); |
96d6407f RH |
1575 | } |
1576 | ||
740038d7 | 1577 | static bool do_floadw(DisasContext *ctx, unsigned rt, unsigned rb, |
31234768 RH |
1578 | unsigned rx, int scale, target_sreg disp, |
1579 | unsigned sp, int modify) | |
96d6407f RH |
1580 | { |
1581 | TCGv_i32 tmp; | |
1582 | ||
1583 | nullify_over(ctx); | |
1584 | ||
1585 | tmp = tcg_temp_new_i32(); | |
86f8d05f | 1586 | do_load_32(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEUL); |
96d6407f RH |
1587 | save_frw_i32(rt, tmp); |
1588 | tcg_temp_free_i32(tmp); | |
1589 | ||
1590 | if (rt == 0) { | |
1591 | gen_helper_loaded_fr0(cpu_env); | |
1592 | } | |
1593 | ||
740038d7 RH |
1594 | return nullify_end(ctx); |
1595 | } | |
1596 | ||
1597 | static bool trans_fldw(DisasContext *ctx, arg_ldst *a) | |
1598 | { | |
1599 | return do_floadw(ctx, a->t, a->b, a->x, a->scale ? 2 : 0, | |
1600 | a->disp, a->sp, a->m); | |
96d6407f RH |
1601 | } |
1602 | ||
740038d7 | 1603 | static bool do_floadd(DisasContext *ctx, unsigned rt, unsigned rb, |
31234768 RH |
1604 | unsigned rx, int scale, target_sreg disp, |
1605 | unsigned sp, int modify) | |
96d6407f RH |
1606 | { |
1607 | TCGv_i64 tmp; | |
1608 | ||
1609 | nullify_over(ctx); | |
1610 | ||
1611 | tmp = tcg_temp_new_i64(); | |
fc313c64 | 1612 | do_load_64(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEUQ); |
96d6407f RH |
1613 | save_frd(rt, tmp); |
1614 | tcg_temp_free_i64(tmp); | |
1615 | ||
1616 | if (rt == 0) { | |
1617 | gen_helper_loaded_fr0(cpu_env); | |
1618 | } | |
1619 | ||
740038d7 RH |
1620 | return nullify_end(ctx); |
1621 | } | |
1622 | ||
1623 | static bool trans_fldd(DisasContext *ctx, arg_ldst *a) | |
1624 | { | |
1625 | return do_floadd(ctx, a->t, a->b, a->x, a->scale ? 3 : 0, | |
1626 | a->disp, a->sp, a->m); | |
96d6407f RH |
1627 | } |
1628 | ||
1cd012a5 | 1629 | static bool do_store(DisasContext *ctx, unsigned rt, unsigned rb, |
31234768 | 1630 | target_sreg disp, unsigned sp, |
14776ab5 | 1631 | int modify, MemOp mop) |
96d6407f RH |
1632 | { |
1633 | nullify_over(ctx); | |
86f8d05f | 1634 | do_store_reg(ctx, load_gpr(ctx, rt), rb, 0, 0, disp, sp, modify, mop); |
1cd012a5 | 1635 | return nullify_end(ctx); |
96d6407f RH |
1636 | } |
1637 | ||
740038d7 | 1638 | static bool do_fstorew(DisasContext *ctx, unsigned rt, unsigned rb, |
31234768 RH |
1639 | unsigned rx, int scale, target_sreg disp, |
1640 | unsigned sp, int modify) | |
96d6407f RH |
1641 | { |
1642 | TCGv_i32 tmp; | |
1643 | ||
1644 | nullify_over(ctx); | |
1645 | ||
1646 | tmp = load_frw_i32(rt); | |
86f8d05f | 1647 | do_store_32(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEUL); |
96d6407f RH |
1648 | tcg_temp_free_i32(tmp); |
1649 | ||
740038d7 RH |
1650 | return nullify_end(ctx); |
1651 | } | |
1652 | ||
1653 | static bool trans_fstw(DisasContext *ctx, arg_ldst *a) | |
1654 | { | |
1655 | return do_fstorew(ctx, a->t, a->b, a->x, a->scale ? 2 : 0, | |
1656 | a->disp, a->sp, a->m); | |
96d6407f RH |
1657 | } |
1658 | ||
740038d7 | 1659 | static bool do_fstored(DisasContext *ctx, unsigned rt, unsigned rb, |
31234768 RH |
1660 | unsigned rx, int scale, target_sreg disp, |
1661 | unsigned sp, int modify) | |
96d6407f RH |
1662 | { |
1663 | TCGv_i64 tmp; | |
1664 | ||
1665 | nullify_over(ctx); | |
1666 | ||
1667 | tmp = load_frd(rt); | |
fc313c64 | 1668 | do_store_64(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEUQ); |
96d6407f RH |
1669 | tcg_temp_free_i64(tmp); |
1670 | ||
740038d7 RH |
1671 | return nullify_end(ctx); |
1672 | } | |
1673 | ||
1674 | static bool trans_fstd(DisasContext *ctx, arg_ldst *a) | |
1675 | { | |
1676 | return do_fstored(ctx, a->t, a->b, a->x, a->scale ? 3 : 0, | |
1677 | a->disp, a->sp, a->m); | |
96d6407f RH |
1678 | } |
1679 | ||
1ca74648 | 1680 | static bool do_fop_wew(DisasContext *ctx, unsigned rt, unsigned ra, |
31234768 | 1681 | void (*func)(TCGv_i32, TCGv_env, TCGv_i32)) |
ebe9383c RH |
1682 | { |
1683 | TCGv_i32 tmp; | |
1684 | ||
1685 | nullify_over(ctx); | |
1686 | tmp = load_frw0_i32(ra); | |
1687 | ||
1688 | func(tmp, cpu_env, tmp); | |
1689 | ||
1690 | save_frw_i32(rt, tmp); | |
1691 | tcg_temp_free_i32(tmp); | |
1ca74648 | 1692 | return nullify_end(ctx); |
ebe9383c RH |
1693 | } |
1694 | ||
1ca74648 | 1695 | static bool do_fop_wed(DisasContext *ctx, unsigned rt, unsigned ra, |
31234768 | 1696 | void (*func)(TCGv_i32, TCGv_env, TCGv_i64)) |
ebe9383c RH |
1697 | { |
1698 | TCGv_i32 dst; | |
1699 | TCGv_i64 src; | |
1700 | ||
1701 | nullify_over(ctx); | |
1702 | src = load_frd(ra); | |
1703 | dst = tcg_temp_new_i32(); | |
1704 | ||
1705 | func(dst, cpu_env, src); | |
1706 | ||
1707 | tcg_temp_free_i64(src); | |
1708 | save_frw_i32(rt, dst); | |
1709 | tcg_temp_free_i32(dst); | |
1ca74648 | 1710 | return nullify_end(ctx); |
ebe9383c RH |
1711 | } |
1712 | ||
1ca74648 | 1713 | static bool do_fop_ded(DisasContext *ctx, unsigned rt, unsigned ra, |
31234768 | 1714 | void (*func)(TCGv_i64, TCGv_env, TCGv_i64)) |
ebe9383c RH |
1715 | { |
1716 | TCGv_i64 tmp; | |
1717 | ||
1718 | nullify_over(ctx); | |
1719 | tmp = load_frd0(ra); | |
1720 | ||
1721 | func(tmp, cpu_env, tmp); | |
1722 | ||
1723 | save_frd(rt, tmp); | |
1724 | tcg_temp_free_i64(tmp); | |
1ca74648 | 1725 | return nullify_end(ctx); |
ebe9383c RH |
1726 | } |
1727 | ||
1ca74648 | 1728 | static bool do_fop_dew(DisasContext *ctx, unsigned rt, unsigned ra, |
31234768 | 1729 | void (*func)(TCGv_i64, TCGv_env, TCGv_i32)) |
ebe9383c RH |
1730 | { |
1731 | TCGv_i32 src; | |
1732 | TCGv_i64 dst; | |
1733 | ||
1734 | nullify_over(ctx); | |
1735 | src = load_frw0_i32(ra); | |
1736 | dst = tcg_temp_new_i64(); | |
1737 | ||
1738 | func(dst, cpu_env, src); | |
1739 | ||
1740 | tcg_temp_free_i32(src); | |
1741 | save_frd(rt, dst); | |
1742 | tcg_temp_free_i64(dst); | |
1ca74648 | 1743 | return nullify_end(ctx); |
ebe9383c RH |
1744 | } |
1745 | ||
1ca74648 | 1746 | static bool do_fop_weww(DisasContext *ctx, unsigned rt, |
31234768 RH |
1747 | unsigned ra, unsigned rb, |
1748 | void (*func)(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32)) | |
ebe9383c RH |
1749 | { |
1750 | TCGv_i32 a, b; | |
1751 | ||
1752 | nullify_over(ctx); | |
1753 | a = load_frw0_i32(ra); | |
1754 | b = load_frw0_i32(rb); | |
1755 | ||
1756 | func(a, cpu_env, a, b); | |
1757 | ||
1758 | tcg_temp_free_i32(b); | |
1759 | save_frw_i32(rt, a); | |
1760 | tcg_temp_free_i32(a); | |
1ca74648 | 1761 | return nullify_end(ctx); |
ebe9383c RH |
1762 | } |
1763 | ||
1ca74648 | 1764 | static bool do_fop_dedd(DisasContext *ctx, unsigned rt, |
31234768 RH |
1765 | unsigned ra, unsigned rb, |
1766 | void (*func)(TCGv_i64, TCGv_env, TCGv_i64, TCGv_i64)) | |
ebe9383c RH |
1767 | { |
1768 | TCGv_i64 a, b; | |
1769 | ||
1770 | nullify_over(ctx); | |
1771 | a = load_frd0(ra); | |
1772 | b = load_frd0(rb); | |
1773 | ||
1774 | func(a, cpu_env, a, b); | |
1775 | ||
1776 | tcg_temp_free_i64(b); | |
1777 | save_frd(rt, a); | |
1778 | tcg_temp_free_i64(a); | |
1ca74648 | 1779 | return nullify_end(ctx); |
ebe9383c RH |
1780 | } |
1781 | ||
98cd9ca7 RH |
1782 | /* Emit an unconditional branch to a direct target, which may or may not |
1783 | have already had nullification handled. */ | |
01afb7be | 1784 | static bool do_dbranch(DisasContext *ctx, target_ureg dest, |
31234768 | 1785 | unsigned link, bool is_n) |
98cd9ca7 RH |
1786 | { |
1787 | if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) { | |
1788 | if (link != 0) { | |
1789 | copy_iaoq_entry(cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); | |
1790 | } | |
1791 | ctx->iaoq_n = dest; | |
1792 | if (is_n) { | |
1793 | ctx->null_cond.c = TCG_COND_ALWAYS; | |
1794 | } | |
98cd9ca7 RH |
1795 | } else { |
1796 | nullify_over(ctx); | |
1797 | ||
1798 | if (link != 0) { | |
1799 | copy_iaoq_entry(cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); | |
1800 | } | |
1801 | ||
1802 | if (is_n && use_nullify_skip(ctx)) { | |
1803 | nullify_set(ctx, 0); | |
1804 | gen_goto_tb(ctx, 0, dest, dest + 4); | |
1805 | } else { | |
1806 | nullify_set(ctx, is_n); | |
1807 | gen_goto_tb(ctx, 0, ctx->iaoq_b, dest); | |
1808 | } | |
1809 | ||
31234768 | 1810 | nullify_end(ctx); |
98cd9ca7 RH |
1811 | |
1812 | nullify_set(ctx, 0); | |
1813 | gen_goto_tb(ctx, 1, ctx->iaoq_b, ctx->iaoq_n); | |
31234768 | 1814 | ctx->base.is_jmp = DISAS_NORETURN; |
98cd9ca7 | 1815 | } |
01afb7be | 1816 | return true; |
98cd9ca7 RH |
1817 | } |
1818 | ||
1819 | /* Emit a conditional branch to a direct target. If the branch itself | |
1820 | is nullified, we should have already used nullify_over. */ | |
01afb7be | 1821 | static bool do_cbranch(DisasContext *ctx, target_sreg disp, bool is_n, |
31234768 | 1822 | DisasCond *cond) |
98cd9ca7 | 1823 | { |
eaa3783b | 1824 | target_ureg dest = iaoq_dest(ctx, disp); |
98cd9ca7 RH |
1825 | TCGLabel *taken = NULL; |
1826 | TCGCond c = cond->c; | |
98cd9ca7 RH |
1827 | bool n; |
1828 | ||
1829 | assert(ctx->null_cond.c == TCG_COND_NEVER); | |
1830 | ||
1831 | /* Handle TRUE and NEVER as direct branches. */ | |
1832 | if (c == TCG_COND_ALWAYS) { | |
01afb7be | 1833 | return do_dbranch(ctx, dest, 0, is_n && disp >= 0); |
98cd9ca7 RH |
1834 | } |
1835 | if (c == TCG_COND_NEVER) { | |
01afb7be | 1836 | return do_dbranch(ctx, ctx->iaoq_n, 0, is_n && disp < 0); |
98cd9ca7 RH |
1837 | } |
1838 | ||
1839 | taken = gen_new_label(); | |
eaa3783b | 1840 | tcg_gen_brcond_reg(c, cond->a0, cond->a1, taken); |
98cd9ca7 RH |
1841 | cond_free(cond); |
1842 | ||
1843 | /* Not taken: Condition not satisfied; nullify on backward branches. */ | |
1844 | n = is_n && disp < 0; | |
1845 | if (n && use_nullify_skip(ctx)) { | |
1846 | nullify_set(ctx, 0); | |
a881c8e7 | 1847 | gen_goto_tb(ctx, 0, ctx->iaoq_n, ctx->iaoq_n + 4); |
98cd9ca7 RH |
1848 | } else { |
1849 | if (!n && ctx->null_lab) { | |
1850 | gen_set_label(ctx->null_lab); | |
1851 | ctx->null_lab = NULL; | |
1852 | } | |
1853 | nullify_set(ctx, n); | |
c301f34e RH |
1854 | if (ctx->iaoq_n == -1) { |
1855 | /* The temporary iaoq_n_var died at the branch above. | |
1856 | Regenerate it here instead of saving it. */ | |
1857 | tcg_gen_addi_reg(ctx->iaoq_n_var, cpu_iaoq_b, 4); | |
1858 | } | |
a881c8e7 | 1859 | gen_goto_tb(ctx, 0, ctx->iaoq_b, ctx->iaoq_n); |
98cd9ca7 RH |
1860 | } |
1861 | ||
1862 | gen_set_label(taken); | |
1863 | ||
1864 | /* Taken: Condition satisfied; nullify on forward branches. */ | |
1865 | n = is_n && disp >= 0; | |
1866 | if (n && use_nullify_skip(ctx)) { | |
1867 | nullify_set(ctx, 0); | |
a881c8e7 | 1868 | gen_goto_tb(ctx, 1, dest, dest + 4); |
98cd9ca7 RH |
1869 | } else { |
1870 | nullify_set(ctx, n); | |
a881c8e7 | 1871 | gen_goto_tb(ctx, 1, ctx->iaoq_b, dest); |
98cd9ca7 RH |
1872 | } |
1873 | ||
1874 | /* Not taken: the branch itself was nullified. */ | |
1875 | if (ctx->null_lab) { | |
1876 | gen_set_label(ctx->null_lab); | |
1877 | ctx->null_lab = NULL; | |
31234768 | 1878 | ctx->base.is_jmp = DISAS_IAQ_N_STALE; |
98cd9ca7 | 1879 | } else { |
31234768 | 1880 | ctx->base.is_jmp = DISAS_NORETURN; |
98cd9ca7 | 1881 | } |
01afb7be | 1882 | return true; |
98cd9ca7 RH |
1883 | } |
1884 | ||
1885 | /* Emit an unconditional branch to an indirect target. This handles | |
1886 | nullification of the branch itself. */ | |
01afb7be | 1887 | static bool do_ibranch(DisasContext *ctx, TCGv_reg dest, |
31234768 | 1888 | unsigned link, bool is_n) |
98cd9ca7 | 1889 | { |
eaa3783b | 1890 | TCGv_reg a0, a1, next, tmp; |
98cd9ca7 RH |
1891 | TCGCond c; |
1892 | ||
1893 | assert(ctx->null_lab == NULL); | |
1894 | ||
1895 | if (ctx->null_cond.c == TCG_COND_NEVER) { | |
1896 | if (link != 0) { | |
1897 | copy_iaoq_entry(cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); | |
1898 | } | |
1899 | next = get_temp(ctx); | |
eaa3783b | 1900 | tcg_gen_mov_reg(next, dest); |
98cd9ca7 | 1901 | if (is_n) { |
c301f34e RH |
1902 | if (use_nullify_skip(ctx)) { |
1903 | tcg_gen_mov_reg(cpu_iaoq_f, next); | |
1904 | tcg_gen_addi_reg(cpu_iaoq_b, next, 4); | |
1905 | nullify_set(ctx, 0); | |
31234768 | 1906 | ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; |
01afb7be | 1907 | return true; |
c301f34e | 1908 | } |
98cd9ca7 RH |
1909 | ctx->null_cond.c = TCG_COND_ALWAYS; |
1910 | } | |
c301f34e RH |
1911 | ctx->iaoq_n = -1; |
1912 | ctx->iaoq_n_var = next; | |
98cd9ca7 RH |
1913 | } else if (is_n && use_nullify_skip(ctx)) { |
1914 | /* The (conditional) branch, B, nullifies the next insn, N, | |
1915 | and we're allowed to skip execution N (no single-step or | |
4137cb83 | 1916 | tracepoint in effect). Since the goto_ptr that we must use |
98cd9ca7 RH |
1917 | for the indirect branch consumes no special resources, we |
1918 | can (conditionally) skip B and continue execution. */ | |
1919 | /* The use_nullify_skip test implies we have a known control path. */ | |
1920 | tcg_debug_assert(ctx->iaoq_b != -1); | |
1921 | tcg_debug_assert(ctx->iaoq_n != -1); | |
1922 | ||
1923 | /* We do have to handle the non-local temporary, DEST, before | |
1924 | branching. Since IOAQ_F is not really live at this point, we | |
1925 | can simply store DEST optimistically. Similarly with IAOQ_B. */ | |
eaa3783b RH |
1926 | tcg_gen_mov_reg(cpu_iaoq_f, dest); |
1927 | tcg_gen_addi_reg(cpu_iaoq_b, dest, 4); | |
98cd9ca7 RH |
1928 | |
1929 | nullify_over(ctx); | |
1930 | if (link != 0) { | |
eaa3783b | 1931 | tcg_gen_movi_reg(cpu_gr[link], ctx->iaoq_n); |
98cd9ca7 | 1932 | } |
7f11636d | 1933 | tcg_gen_lookup_and_goto_ptr(); |
01afb7be | 1934 | return nullify_end(ctx); |
98cd9ca7 | 1935 | } else { |
98cd9ca7 RH |
1936 | c = ctx->null_cond.c; |
1937 | a0 = ctx->null_cond.a0; | |
1938 | a1 = ctx->null_cond.a1; | |
1939 | ||
1940 | tmp = tcg_temp_new(); | |
1941 | next = get_temp(ctx); | |
1942 | ||
1943 | copy_iaoq_entry(tmp, ctx->iaoq_n, ctx->iaoq_n_var); | |
eaa3783b | 1944 | tcg_gen_movcond_reg(c, next, a0, a1, tmp, dest); |
98cd9ca7 RH |
1945 | ctx->iaoq_n = -1; |
1946 | ctx->iaoq_n_var = next; | |
1947 | ||
1948 | if (link != 0) { | |
eaa3783b | 1949 | tcg_gen_movcond_reg(c, cpu_gr[link], a0, a1, cpu_gr[link], tmp); |
98cd9ca7 RH |
1950 | } |
1951 | ||
1952 | if (is_n) { | |
1953 | /* The branch nullifies the next insn, which means the state of N | |
1954 | after the branch is the inverse of the state of N that applied | |
1955 | to the branch. */ | |
eaa3783b | 1956 | tcg_gen_setcond_reg(tcg_invert_cond(c), cpu_psw_n, a0, a1); |
98cd9ca7 RH |
1957 | cond_free(&ctx->null_cond); |
1958 | ctx->null_cond = cond_make_n(); | |
1959 | ctx->psw_n_nonzero = true; | |
1960 | } else { | |
1961 | cond_free(&ctx->null_cond); | |
1962 | } | |
1963 | } | |
01afb7be | 1964 | return true; |
98cd9ca7 RH |
1965 | } |
1966 | ||
660eefe1 RH |
1967 | /* Implement |
1968 | * if (IAOQ_Front{30..31} < GR[b]{30..31}) | |
1969 | * IAOQ_Next{30..31} ← GR[b]{30..31}; | |
1970 | * else | |
1971 | * IAOQ_Next{30..31} ← IAOQ_Front{30..31}; | |
1972 | * which keeps the privilege level from being increased. | |
1973 | */ | |
1974 | static TCGv_reg do_ibranch_priv(DisasContext *ctx, TCGv_reg offset) | |
1975 | { | |
660eefe1 RH |
1976 | TCGv_reg dest; |
1977 | switch (ctx->privilege) { | |
1978 | case 0: | |
1979 | /* Privilege 0 is maximum and is allowed to decrease. */ | |
1980 | return offset; | |
1981 | case 3: | |
993119fe | 1982 | /* Privilege 3 is minimum and is never allowed to increase. */ |
660eefe1 RH |
1983 | dest = get_temp(ctx); |
1984 | tcg_gen_ori_reg(dest, offset, 3); | |
1985 | break; | |
1986 | default: | |
993119fe | 1987 | dest = get_temp(ctx); |
660eefe1 RH |
1988 | tcg_gen_andi_reg(dest, offset, -4); |
1989 | tcg_gen_ori_reg(dest, dest, ctx->privilege); | |
1990 | tcg_gen_movcond_reg(TCG_COND_GTU, dest, dest, offset, dest, offset); | |
660eefe1 RH |
1991 | break; |
1992 | } | |
1993 | return dest; | |
660eefe1 RH |
1994 | } |
1995 | ||
ba1d0b44 | 1996 | #ifdef CONFIG_USER_ONLY |
7ad439df RH |
1997 | /* On Linux, page zero is normally marked execute only + gateway. |
1998 | Therefore normal read or write is supposed to fail, but specific | |
1999 | offsets have kernel code mapped to raise permissions to implement | |
2000 | system calls. Handling this via an explicit check here, rather | |
2001 | in than the "be disp(sr2,r0)" instruction that probably sent us | |
2002 | here, is the easiest way to handle the branch delay slot on the | |
2003 | aforementioned BE. */ | |
31234768 | 2004 | static void do_page_zero(DisasContext *ctx) |
7ad439df RH |
2005 | { |
2006 | /* If by some means we get here with PSW[N]=1, that implies that | |
2007 | the B,GATE instruction would be skipped, and we'd fault on the | |
2008 | next insn within the privilaged page. */ | |
2009 | switch (ctx->null_cond.c) { | |
2010 | case TCG_COND_NEVER: | |
2011 | break; | |
2012 | case TCG_COND_ALWAYS: | |
eaa3783b | 2013 | tcg_gen_movi_reg(cpu_psw_n, 0); |
7ad439df RH |
2014 | goto do_sigill; |
2015 | default: | |
2016 | /* Since this is always the first (and only) insn within the | |
2017 | TB, we should know the state of PSW[N] from TB->FLAGS. */ | |
2018 | g_assert_not_reached(); | |
2019 | } | |
2020 | ||
2021 | /* Check that we didn't arrive here via some means that allowed | |
2022 | non-sequential instruction execution. Normally the PSW[B] bit | |
2023 | detects this by disallowing the B,GATE instruction to execute | |
2024 | under such conditions. */ | |
2025 | if (ctx->iaoq_b != ctx->iaoq_f + 4) { | |
2026 | goto do_sigill; | |
2027 | } | |
2028 | ||
ebd0e151 | 2029 | switch (ctx->iaoq_f & -4) { |
7ad439df | 2030 | case 0x00: /* Null pointer call */ |
2986721d | 2031 | gen_excp_1(EXCP_IMP); |
31234768 RH |
2032 | ctx->base.is_jmp = DISAS_NORETURN; |
2033 | break; | |
7ad439df RH |
2034 | |
2035 | case 0xb0: /* LWS */ | |
2036 | gen_excp_1(EXCP_SYSCALL_LWS); | |
31234768 RH |
2037 | ctx->base.is_jmp = DISAS_NORETURN; |
2038 | break; | |
7ad439df RH |
2039 | |
2040 | case 0xe0: /* SET_THREAD_POINTER */ | |
35136a77 | 2041 | tcg_gen_st_reg(cpu_gr[26], cpu_env, offsetof(CPUHPPAState, cr[27])); |
ebd0e151 | 2042 | tcg_gen_ori_reg(cpu_iaoq_f, cpu_gr[31], 3); |
eaa3783b | 2043 | tcg_gen_addi_reg(cpu_iaoq_b, cpu_iaoq_f, 4); |
31234768 RH |
2044 | ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; |
2045 | break; | |
7ad439df RH |
2046 | |
2047 | case 0x100: /* SYSCALL */ | |
2048 | gen_excp_1(EXCP_SYSCALL); | |
31234768 RH |
2049 | ctx->base.is_jmp = DISAS_NORETURN; |
2050 | break; | |
7ad439df RH |
2051 | |
2052 | default: | |
2053 | do_sigill: | |
2986721d | 2054 | gen_excp_1(EXCP_ILL); |
31234768 RH |
2055 | ctx->base.is_jmp = DISAS_NORETURN; |
2056 | break; | |
7ad439df RH |
2057 | } |
2058 | } | |
ba1d0b44 | 2059 | #endif |
7ad439df | 2060 | |
deee69a1 | 2061 | static bool trans_nop(DisasContext *ctx, arg_nop *a) |
b2167459 RH |
2062 | { |
2063 | cond_free(&ctx->null_cond); | |
31234768 | 2064 | return true; |
b2167459 RH |
2065 | } |
2066 | ||
40f9f908 | 2067 | static bool trans_break(DisasContext *ctx, arg_break *a) |
98a9cb79 | 2068 | { |
31234768 | 2069 | return gen_excp_iir(ctx, EXCP_BREAK); |
98a9cb79 RH |
2070 | } |
2071 | ||
e36f27ef | 2072 | static bool trans_sync(DisasContext *ctx, arg_sync *a) |
98a9cb79 RH |
2073 | { |
2074 | /* No point in nullifying the memory barrier. */ | |
2075 | tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); | |
2076 | ||
2077 | cond_free(&ctx->null_cond); | |
31234768 | 2078 | return true; |
98a9cb79 RH |
2079 | } |
2080 | ||
c603e14a | 2081 | static bool trans_mfia(DisasContext *ctx, arg_mfia *a) |
98a9cb79 | 2082 | { |
c603e14a | 2083 | unsigned rt = a->t; |
eaa3783b RH |
2084 | TCGv_reg tmp = dest_gpr(ctx, rt); |
2085 | tcg_gen_movi_reg(tmp, ctx->iaoq_f); | |
98a9cb79 RH |
2086 | save_gpr(ctx, rt, tmp); |
2087 | ||
2088 | cond_free(&ctx->null_cond); | |
31234768 | 2089 | return true; |
98a9cb79 RH |
2090 | } |
2091 | ||
c603e14a | 2092 | static bool trans_mfsp(DisasContext *ctx, arg_mfsp *a) |
98a9cb79 | 2093 | { |
c603e14a RH |
2094 | unsigned rt = a->t; |
2095 | unsigned rs = a->sp; | |
33423472 RH |
2096 | TCGv_i64 t0 = tcg_temp_new_i64(); |
2097 | TCGv_reg t1 = tcg_temp_new(); | |
98a9cb79 | 2098 | |
33423472 RH |
2099 | load_spr(ctx, t0, rs); |
2100 | tcg_gen_shri_i64(t0, t0, 32); | |
2101 | tcg_gen_trunc_i64_reg(t1, t0); | |
2102 | ||
2103 | save_gpr(ctx, rt, t1); | |
2104 | tcg_temp_free(t1); | |
2105 | tcg_temp_free_i64(t0); | |
98a9cb79 RH |
2106 | |
2107 | cond_free(&ctx->null_cond); | |
31234768 | 2108 | return true; |
98a9cb79 RH |
2109 | } |
2110 | ||
c603e14a | 2111 | static bool trans_mfctl(DisasContext *ctx, arg_mfctl *a) |
98a9cb79 | 2112 | { |
c603e14a RH |
2113 | unsigned rt = a->t; |
2114 | unsigned ctl = a->r; | |
eaa3783b | 2115 | TCGv_reg tmp; |
98a9cb79 RH |
2116 | |
2117 | switch (ctl) { | |
35136a77 | 2118 | case CR_SAR: |
98a9cb79 | 2119 | #ifdef TARGET_HPPA64 |
c603e14a | 2120 | if (a->e == 0) { |
98a9cb79 RH |
2121 | /* MFSAR without ,W masks low 5 bits. */ |
2122 | tmp = dest_gpr(ctx, rt); | |
eaa3783b | 2123 | tcg_gen_andi_reg(tmp, cpu_sar, 31); |
98a9cb79 | 2124 | save_gpr(ctx, rt, tmp); |
35136a77 | 2125 | goto done; |
98a9cb79 RH |
2126 | } |
2127 | #endif | |
2128 | save_gpr(ctx, rt, cpu_sar); | |
35136a77 RH |
2129 | goto done; |
2130 | case CR_IT: /* Interval Timer */ | |
2131 | /* FIXME: Respect PSW_S bit. */ | |
2132 | nullify_over(ctx); | |
98a9cb79 | 2133 | tmp = dest_gpr(ctx, rt); |
84b41e65 | 2134 | if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { |
49c29d6c RH |
2135 | gen_io_start(); |
2136 | gen_helper_read_interval_timer(tmp); | |
31234768 | 2137 | ctx->base.is_jmp = DISAS_IAQ_N_STALE; |
49c29d6c RH |
2138 | } else { |
2139 | gen_helper_read_interval_timer(tmp); | |
49c29d6c | 2140 | } |
98a9cb79 | 2141 | save_gpr(ctx, rt, tmp); |
31234768 | 2142 | return nullify_end(ctx); |
98a9cb79 | 2143 | case 26: |
98a9cb79 | 2144 | case 27: |
98a9cb79 RH |
2145 | break; |
2146 | default: | |
2147 | /* All other control registers are privileged. */ | |
35136a77 RH |
2148 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG); |
2149 | break; | |
98a9cb79 RH |
2150 | } |
2151 | ||
35136a77 RH |
2152 | tmp = get_temp(ctx); |
2153 | tcg_gen_ld_reg(tmp, cpu_env, offsetof(CPUHPPAState, cr[ctl])); | |
2154 | save_gpr(ctx, rt, tmp); | |
2155 | ||
2156 | done: | |
98a9cb79 | 2157 | cond_free(&ctx->null_cond); |
31234768 | 2158 | return true; |
98a9cb79 RH |
2159 | } |
2160 | ||
c603e14a | 2161 | static bool trans_mtsp(DisasContext *ctx, arg_mtsp *a) |
33423472 | 2162 | { |
c603e14a RH |
2163 | unsigned rr = a->r; |
2164 | unsigned rs = a->sp; | |
33423472 RH |
2165 | TCGv_i64 t64; |
2166 | ||
2167 | if (rs >= 5) { | |
2168 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG); | |
2169 | } | |
2170 | nullify_over(ctx); | |
2171 | ||
2172 | t64 = tcg_temp_new_i64(); | |
2173 | tcg_gen_extu_reg_i64(t64, load_gpr(ctx, rr)); | |
2174 | tcg_gen_shli_i64(t64, t64, 32); | |
2175 | ||
2176 | if (rs >= 4) { | |
2177 | tcg_gen_st_i64(t64, cpu_env, offsetof(CPUHPPAState, sr[rs])); | |
494737b7 | 2178 | ctx->tb_flags &= ~TB_FLAG_SR_SAME; |
33423472 RH |
2179 | } else { |
2180 | tcg_gen_mov_i64(cpu_sr[rs], t64); | |
2181 | } | |
2182 | tcg_temp_free_i64(t64); | |
2183 | ||
31234768 | 2184 | return nullify_end(ctx); |
33423472 RH |
2185 | } |
2186 | ||
c603e14a | 2187 | static bool trans_mtctl(DisasContext *ctx, arg_mtctl *a) |
98a9cb79 | 2188 | { |
c603e14a | 2189 | unsigned ctl = a->t; |
4845f015 | 2190 | TCGv_reg reg; |
eaa3783b | 2191 | TCGv_reg tmp; |
98a9cb79 | 2192 | |
35136a77 | 2193 | if (ctl == CR_SAR) { |
4845f015 | 2194 | reg = load_gpr(ctx, a->r); |
98a9cb79 | 2195 | tmp = tcg_temp_new(); |
35136a77 | 2196 | tcg_gen_andi_reg(tmp, reg, TARGET_REGISTER_BITS - 1); |
98a9cb79 RH |
2197 | save_or_nullify(ctx, cpu_sar, tmp); |
2198 | tcg_temp_free(tmp); | |
35136a77 RH |
2199 | |
2200 | cond_free(&ctx->null_cond); | |
31234768 | 2201 | return true; |
98a9cb79 RH |
2202 | } |
2203 | ||
35136a77 RH |
2204 | /* All other control registers are privileged or read-only. */ |
2205 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG); | |
2206 | ||
c603e14a | 2207 | #ifndef CONFIG_USER_ONLY |
35136a77 | 2208 | nullify_over(ctx); |
4845f015 SS |
2209 | reg = load_gpr(ctx, a->r); |
2210 | ||
35136a77 RH |
2211 | switch (ctl) { |
2212 | case CR_IT: | |
49c29d6c | 2213 | gen_helper_write_interval_timer(cpu_env, reg); |
35136a77 | 2214 | break; |
4f5f2548 RH |
2215 | case CR_EIRR: |
2216 | gen_helper_write_eirr(cpu_env, reg); | |
2217 | break; | |
2218 | case CR_EIEM: | |
2219 | gen_helper_write_eiem(cpu_env, reg); | |
31234768 | 2220 | ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; |
4f5f2548 RH |
2221 | break; |
2222 | ||
35136a77 RH |
2223 | case CR_IIASQ: |
2224 | case CR_IIAOQ: | |
2225 | /* FIXME: Respect PSW_Q bit */ | |
2226 | /* The write advances the queue and stores to the back element. */ | |
2227 | tmp = get_temp(ctx); | |
2228 | tcg_gen_ld_reg(tmp, cpu_env, | |
2229 | offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ])); | |
2230 | tcg_gen_st_reg(tmp, cpu_env, offsetof(CPUHPPAState, cr[ctl])); | |
2231 | tcg_gen_st_reg(reg, cpu_env, | |
2232 | offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ])); | |
2233 | break; | |
2234 | ||
d5de20bd SS |
2235 | case CR_PID1: |
2236 | case CR_PID2: | |
2237 | case CR_PID3: | |
2238 | case CR_PID4: | |
2239 | tcg_gen_st_reg(reg, cpu_env, offsetof(CPUHPPAState, cr[ctl])); | |
2240 | #ifndef CONFIG_USER_ONLY | |
2241 | gen_helper_change_prot_id(cpu_env); | |
2242 | #endif | |
2243 | break; | |
2244 | ||
35136a77 RH |
2245 | default: |
2246 | tcg_gen_st_reg(reg, cpu_env, offsetof(CPUHPPAState, cr[ctl])); | |
2247 | break; | |
2248 | } | |
31234768 | 2249 | return nullify_end(ctx); |
4f5f2548 | 2250 | #endif |
98a9cb79 RH |
2251 | } |
2252 | ||
c603e14a | 2253 | static bool trans_mtsarcm(DisasContext *ctx, arg_mtsarcm *a) |
98a9cb79 | 2254 | { |
eaa3783b | 2255 | TCGv_reg tmp = tcg_temp_new(); |
98a9cb79 | 2256 | |
c603e14a | 2257 | tcg_gen_not_reg(tmp, load_gpr(ctx, a->r)); |
eaa3783b | 2258 | tcg_gen_andi_reg(tmp, tmp, TARGET_REGISTER_BITS - 1); |
98a9cb79 RH |
2259 | save_or_nullify(ctx, cpu_sar, tmp); |
2260 | tcg_temp_free(tmp); | |
2261 | ||
2262 | cond_free(&ctx->null_cond); | |
31234768 | 2263 | return true; |
98a9cb79 RH |
2264 | } |
2265 | ||
e36f27ef | 2266 | static bool trans_ldsid(DisasContext *ctx, arg_ldsid *a) |
98a9cb79 | 2267 | { |
e36f27ef | 2268 | TCGv_reg dest = dest_gpr(ctx, a->t); |
98a9cb79 | 2269 | |
2330504c HD |
2270 | #ifdef CONFIG_USER_ONLY |
2271 | /* We don't implement space registers in user mode. */ | |
eaa3783b | 2272 | tcg_gen_movi_reg(dest, 0); |
2330504c | 2273 | #else |
2330504c HD |
2274 | TCGv_i64 t0 = tcg_temp_new_i64(); |
2275 | ||
e36f27ef | 2276 | tcg_gen_mov_i64(t0, space_select(ctx, a->sp, load_gpr(ctx, a->b))); |
2330504c HD |
2277 | tcg_gen_shri_i64(t0, t0, 32); |
2278 | tcg_gen_trunc_i64_reg(dest, t0); | |
2279 | ||
2280 | tcg_temp_free_i64(t0); | |
2281 | #endif | |
e36f27ef | 2282 | save_gpr(ctx, a->t, dest); |
98a9cb79 RH |
2283 | |
2284 | cond_free(&ctx->null_cond); | |
31234768 | 2285 | return true; |
98a9cb79 RH |
2286 | } |
2287 | ||
e36f27ef | 2288 | static bool trans_rsm(DisasContext *ctx, arg_rsm *a) |
e1b5a5ed | 2289 | { |
e36f27ef RH |
2290 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); |
2291 | #ifndef CONFIG_USER_ONLY | |
e1b5a5ed RH |
2292 | TCGv_reg tmp; |
2293 | ||
e1b5a5ed RH |
2294 | nullify_over(ctx); |
2295 | ||
2296 | tmp = get_temp(ctx); | |
2297 | tcg_gen_ld_reg(tmp, cpu_env, offsetof(CPUHPPAState, psw)); | |
e36f27ef | 2298 | tcg_gen_andi_reg(tmp, tmp, ~a->i); |
e1b5a5ed | 2299 | gen_helper_swap_system_mask(tmp, cpu_env, tmp); |
e36f27ef | 2300 | save_gpr(ctx, a->t, tmp); |
e1b5a5ed RH |
2301 | |
2302 | /* Exit the TB to recognize new interrupts, e.g. PSW_M. */ | |
31234768 RH |
2303 | ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; |
2304 | return nullify_end(ctx); | |
e36f27ef | 2305 | #endif |
e1b5a5ed RH |
2306 | } |
2307 | ||
e36f27ef | 2308 | static bool trans_ssm(DisasContext *ctx, arg_ssm *a) |
e1b5a5ed | 2309 | { |
e36f27ef RH |
2310 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); |
2311 | #ifndef CONFIG_USER_ONLY | |
e1b5a5ed RH |
2312 | TCGv_reg tmp; |
2313 | ||
e1b5a5ed RH |
2314 | nullify_over(ctx); |
2315 | ||
2316 | tmp = get_temp(ctx); | |
2317 | tcg_gen_ld_reg(tmp, cpu_env, offsetof(CPUHPPAState, psw)); | |
e36f27ef | 2318 | tcg_gen_ori_reg(tmp, tmp, a->i); |
e1b5a5ed | 2319 | gen_helper_swap_system_mask(tmp, cpu_env, tmp); |
e36f27ef | 2320 | save_gpr(ctx, a->t, tmp); |
e1b5a5ed RH |
2321 | |
2322 | /* Exit the TB to recognize new interrupts, e.g. PSW_I. */ | |
31234768 RH |
2323 | ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; |
2324 | return nullify_end(ctx); | |
e36f27ef | 2325 | #endif |
e1b5a5ed RH |
2326 | } |
2327 | ||
c603e14a | 2328 | static bool trans_mtsm(DisasContext *ctx, arg_mtsm *a) |
e1b5a5ed | 2329 | { |
e1b5a5ed | 2330 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); |
c603e14a RH |
2331 | #ifndef CONFIG_USER_ONLY |
2332 | TCGv_reg tmp, reg; | |
e1b5a5ed RH |
2333 | nullify_over(ctx); |
2334 | ||
c603e14a | 2335 | reg = load_gpr(ctx, a->r); |
e1b5a5ed RH |
2336 | tmp = get_temp(ctx); |
2337 | gen_helper_swap_system_mask(tmp, cpu_env, reg); | |
2338 | ||
2339 | /* Exit the TB to recognize new interrupts. */ | |
31234768 RH |
2340 | ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; |
2341 | return nullify_end(ctx); | |
c603e14a | 2342 | #endif |
e1b5a5ed | 2343 | } |
f49b3537 | 2344 | |
e36f27ef | 2345 | static bool do_rfi(DisasContext *ctx, bool rfi_r) |
f49b3537 | 2346 | { |
f49b3537 | 2347 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); |
e36f27ef | 2348 | #ifndef CONFIG_USER_ONLY |
f49b3537 RH |
2349 | nullify_over(ctx); |
2350 | ||
e36f27ef | 2351 | if (rfi_r) { |
f49b3537 RH |
2352 | gen_helper_rfi_r(cpu_env); |
2353 | } else { | |
2354 | gen_helper_rfi(cpu_env); | |
2355 | } | |
31234768 | 2356 | /* Exit the TB to recognize new interrupts. */ |
8532a14e | 2357 | tcg_gen_exit_tb(NULL, 0); |
31234768 | 2358 | ctx->base.is_jmp = DISAS_NORETURN; |
f49b3537 | 2359 | |
31234768 | 2360 | return nullify_end(ctx); |
e36f27ef RH |
2361 | #endif |
2362 | } | |
2363 | ||
2364 | static bool trans_rfi(DisasContext *ctx, arg_rfi *a) | |
2365 | { | |
2366 | return do_rfi(ctx, false); | |
2367 | } | |
2368 | ||
2369 | static bool trans_rfi_r(DisasContext *ctx, arg_rfi_r *a) | |
2370 | { | |
2371 | return do_rfi(ctx, true); | |
f49b3537 | 2372 | } |
6210db05 | 2373 | |
96927adb RH |
2374 | static bool trans_halt(DisasContext *ctx, arg_halt *a) |
2375 | { | |
2376 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); | |
e36f27ef | 2377 | #ifndef CONFIG_USER_ONLY |
96927adb RH |
2378 | nullify_over(ctx); |
2379 | gen_helper_halt(cpu_env); | |
2380 | ctx->base.is_jmp = DISAS_NORETURN; | |
2381 | return nullify_end(ctx); | |
2382 | #endif | |
2383 | } | |
2384 | ||
2385 | static bool trans_reset(DisasContext *ctx, arg_reset *a) | |
6210db05 HD |
2386 | { |
2387 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); | |
96927adb | 2388 | #ifndef CONFIG_USER_ONLY |
6210db05 | 2389 | nullify_over(ctx); |
96927adb | 2390 | gen_helper_reset(cpu_env); |
31234768 RH |
2391 | ctx->base.is_jmp = DISAS_NORETURN; |
2392 | return nullify_end(ctx); | |
96927adb | 2393 | #endif |
6210db05 | 2394 | } |
e1b5a5ed | 2395 | |
4a4554c6 HD |
2396 | static bool trans_getshadowregs(DisasContext *ctx, arg_getshadowregs *a) |
2397 | { | |
2398 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); | |
2399 | #ifndef CONFIG_USER_ONLY | |
2400 | nullify_over(ctx); | |
2401 | gen_helper_getshadowregs(cpu_env); | |
2402 | return nullify_end(ctx); | |
2403 | #endif | |
2404 | } | |
2405 | ||
deee69a1 | 2406 | static bool trans_nop_addrx(DisasContext *ctx, arg_ldst *a) |
98a9cb79 | 2407 | { |
deee69a1 RH |
2408 | if (a->m) { |
2409 | TCGv_reg dest = dest_gpr(ctx, a->b); | |
2410 | TCGv_reg src1 = load_gpr(ctx, a->b); | |
2411 | TCGv_reg src2 = load_gpr(ctx, a->x); | |
98a9cb79 | 2412 | |
deee69a1 RH |
2413 | /* The only thing we need to do is the base register modification. */ |
2414 | tcg_gen_add_reg(dest, src1, src2); | |
2415 | save_gpr(ctx, a->b, dest); | |
2416 | } | |
98a9cb79 | 2417 | cond_free(&ctx->null_cond); |
31234768 | 2418 | return true; |
98a9cb79 RH |
2419 | } |
2420 | ||
deee69a1 | 2421 | static bool trans_probe(DisasContext *ctx, arg_probe *a) |
98a9cb79 | 2422 | { |
86f8d05f | 2423 | TCGv_reg dest, ofs; |
eed14219 | 2424 | TCGv_i32 level, want; |
86f8d05f | 2425 | TCGv_tl addr; |
98a9cb79 RH |
2426 | |
2427 | nullify_over(ctx); | |
2428 | ||
deee69a1 RH |
2429 | dest = dest_gpr(ctx, a->t); |
2430 | form_gva(ctx, &addr, &ofs, a->b, 0, 0, 0, a->sp, 0, false); | |
eed14219 | 2431 | |
deee69a1 | 2432 | if (a->imm) { |
29dd6f64 | 2433 | level = tcg_constant_i32(a->ri); |
98a9cb79 | 2434 | } else { |
eed14219 | 2435 | level = tcg_temp_new_i32(); |
deee69a1 | 2436 | tcg_gen_trunc_reg_i32(level, load_gpr(ctx, a->ri)); |
eed14219 | 2437 | tcg_gen_andi_i32(level, level, 3); |
98a9cb79 | 2438 | } |
29dd6f64 | 2439 | want = tcg_constant_i32(a->write ? PAGE_WRITE : PAGE_READ); |
eed14219 RH |
2440 | |
2441 | gen_helper_probe(dest, cpu_env, addr, level, want); | |
2442 | ||
eed14219 RH |
2443 | tcg_temp_free_i32(level); |
2444 | ||
deee69a1 | 2445 | save_gpr(ctx, a->t, dest); |
31234768 | 2446 | return nullify_end(ctx); |
98a9cb79 RH |
2447 | } |
2448 | ||
deee69a1 | 2449 | static bool trans_ixtlbx(DisasContext *ctx, arg_ixtlbx *a) |
8d6ae7fb | 2450 | { |
deee69a1 RH |
2451 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); |
2452 | #ifndef CONFIG_USER_ONLY | |
8d6ae7fb RH |
2453 | TCGv_tl addr; |
2454 | TCGv_reg ofs, reg; | |
2455 | ||
8d6ae7fb RH |
2456 | nullify_over(ctx); |
2457 | ||
deee69a1 RH |
2458 | form_gva(ctx, &addr, &ofs, a->b, 0, 0, 0, a->sp, 0, false); |
2459 | reg = load_gpr(ctx, a->r); | |
2460 | if (a->addr) { | |
8d6ae7fb RH |
2461 | gen_helper_itlba(cpu_env, addr, reg); |
2462 | } else { | |
2463 | gen_helper_itlbp(cpu_env, addr, reg); | |
2464 | } | |
2465 | ||
32dc7569 SS |
2466 | /* Exit TB for TLB change if mmu is enabled. */ |
2467 | if (ctx->tb_flags & PSW_C) { | |
31234768 RH |
2468 | ctx->base.is_jmp = DISAS_IAQ_N_STALE; |
2469 | } | |
2470 | return nullify_end(ctx); | |
deee69a1 | 2471 | #endif |
8d6ae7fb | 2472 | } |
63300a00 | 2473 | |
deee69a1 | 2474 | static bool trans_pxtlbx(DisasContext *ctx, arg_pxtlbx *a) |
63300a00 | 2475 | { |
deee69a1 RH |
2476 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); |
2477 | #ifndef CONFIG_USER_ONLY | |
63300a00 RH |
2478 | TCGv_tl addr; |
2479 | TCGv_reg ofs; | |
2480 | ||
63300a00 RH |
2481 | nullify_over(ctx); |
2482 | ||
deee69a1 RH |
2483 | form_gva(ctx, &addr, &ofs, a->b, a->x, 0, 0, a->sp, a->m, false); |
2484 | if (a->m) { | |
2485 | save_gpr(ctx, a->b, ofs); | |
63300a00 | 2486 | } |
deee69a1 | 2487 | if (a->local) { |
63300a00 RH |
2488 | gen_helper_ptlbe(cpu_env); |
2489 | } else { | |
2490 | gen_helper_ptlb(cpu_env, addr); | |
2491 | } | |
2492 | ||
2493 | /* Exit TB for TLB change if mmu is enabled. */ | |
6797c315 NH |
2494 | if (ctx->tb_flags & PSW_C) { |
2495 | ctx->base.is_jmp = DISAS_IAQ_N_STALE; | |
2496 | } | |
2497 | return nullify_end(ctx); | |
2498 | #endif | |
2499 | } | |
2500 | ||
2501 | /* | |
2502 | * Implement the pcxl and pcxl2 Fast TLB Insert instructions. | |
2503 | * See | |
2504 | * https://parisc.wiki.kernel.org/images-parisc/a/a9/Pcxl2_ers.pdf | |
2505 | * page 13-9 (195/206) | |
2506 | */ | |
2507 | static bool trans_ixtlbxf(DisasContext *ctx, arg_ixtlbxf *a) | |
2508 | { | |
2509 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); | |
2510 | #ifndef CONFIG_USER_ONLY | |
2511 | TCGv_tl addr, atl, stl; | |
2512 | TCGv_reg reg; | |
2513 | ||
2514 | nullify_over(ctx); | |
2515 | ||
2516 | /* | |
2517 | * FIXME: | |
2518 | * if (not (pcxl or pcxl2)) | |
2519 | * return gen_illegal(ctx); | |
2520 | * | |
2521 | * Note for future: these are 32-bit systems; no hppa64. | |
2522 | */ | |
2523 | ||
2524 | atl = tcg_temp_new_tl(); | |
2525 | stl = tcg_temp_new_tl(); | |
2526 | addr = tcg_temp_new_tl(); | |
2527 | ||
2528 | tcg_gen_ld32u_i64(stl, cpu_env, | |
2529 | a->data ? offsetof(CPUHPPAState, cr[CR_ISR]) | |
2530 | : offsetof(CPUHPPAState, cr[CR_IIASQ])); | |
2531 | tcg_gen_ld32u_i64(atl, cpu_env, | |
2532 | a->data ? offsetof(CPUHPPAState, cr[CR_IOR]) | |
2533 | : offsetof(CPUHPPAState, cr[CR_IIAOQ])); | |
2534 | tcg_gen_shli_i64(stl, stl, 32); | |
2535 | tcg_gen_or_tl(addr, atl, stl); | |
2536 | tcg_temp_free_tl(atl); | |
2537 | tcg_temp_free_tl(stl); | |
2538 | ||
2539 | reg = load_gpr(ctx, a->r); | |
2540 | if (a->addr) { | |
2541 | gen_helper_itlba(cpu_env, addr, reg); | |
2542 | } else { | |
2543 | gen_helper_itlbp(cpu_env, addr, reg); | |
2544 | } | |
2545 | tcg_temp_free_tl(addr); | |
2546 | ||
2547 | /* Exit TB for TLB change if mmu is enabled. */ | |
32dc7569 | 2548 | if (ctx->tb_flags & PSW_C) { |
31234768 RH |
2549 | ctx->base.is_jmp = DISAS_IAQ_N_STALE; |
2550 | } | |
2551 | return nullify_end(ctx); | |
deee69a1 | 2552 | #endif |
63300a00 | 2553 | } |
2dfcca9f | 2554 | |
deee69a1 | 2555 | static bool trans_lpa(DisasContext *ctx, arg_ldst *a) |
2dfcca9f | 2556 | { |
deee69a1 RH |
2557 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); |
2558 | #ifndef CONFIG_USER_ONLY | |
2dfcca9f RH |
2559 | TCGv_tl vaddr; |
2560 | TCGv_reg ofs, paddr; | |
2561 | ||
2dfcca9f RH |
2562 | nullify_over(ctx); |
2563 | ||
deee69a1 | 2564 | form_gva(ctx, &vaddr, &ofs, a->b, a->x, 0, 0, a->sp, a->m, false); |
2dfcca9f RH |
2565 | |
2566 | paddr = tcg_temp_new(); | |
2567 | gen_helper_lpa(paddr, cpu_env, vaddr); | |
2568 | ||
2569 | /* Note that physical address result overrides base modification. */ | |
deee69a1 RH |
2570 | if (a->m) { |
2571 | save_gpr(ctx, a->b, ofs); | |
2dfcca9f | 2572 | } |
deee69a1 | 2573 | save_gpr(ctx, a->t, paddr); |
2dfcca9f RH |
2574 | tcg_temp_free(paddr); |
2575 | ||
31234768 | 2576 | return nullify_end(ctx); |
deee69a1 | 2577 | #endif |
2dfcca9f | 2578 | } |
43a97b81 | 2579 | |
deee69a1 | 2580 | static bool trans_lci(DisasContext *ctx, arg_lci *a) |
43a97b81 | 2581 | { |
43a97b81 RH |
2582 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); |
2583 | ||
2584 | /* The Coherence Index is an implementation-defined function of the | |
2585 | physical address. Two addresses with the same CI have a coherent | |
2586 | view of the cache. Our implementation is to return 0 for all, | |
2587 | since the entire address space is coherent. */ | |
29dd6f64 | 2588 | save_gpr(ctx, a->t, tcg_constant_reg(0)); |
43a97b81 | 2589 | |
31234768 RH |
2590 | cond_free(&ctx->null_cond); |
2591 | return true; | |
43a97b81 | 2592 | } |
98a9cb79 | 2593 | |
0c982a28 | 2594 | static bool trans_add(DisasContext *ctx, arg_rrr_cf_sh *a) |
b2167459 | 2595 | { |
0c982a28 RH |
2596 | return do_add_reg(ctx, a, false, false, false, false); |
2597 | } | |
b2167459 | 2598 | |
0c982a28 RH |
2599 | static bool trans_add_l(DisasContext *ctx, arg_rrr_cf_sh *a) |
2600 | { | |
2601 | return do_add_reg(ctx, a, true, false, false, false); | |
2602 | } | |
b2167459 | 2603 | |
0c982a28 RH |
2604 | static bool trans_add_tsv(DisasContext *ctx, arg_rrr_cf_sh *a) |
2605 | { | |
2606 | return do_add_reg(ctx, a, false, true, false, false); | |
b2167459 RH |
2607 | } |
2608 | ||
0c982a28 | 2609 | static bool trans_add_c(DisasContext *ctx, arg_rrr_cf_sh *a) |
b2167459 | 2610 | { |
0c982a28 RH |
2611 | return do_add_reg(ctx, a, false, false, false, true); |
2612 | } | |
b2167459 | 2613 | |
0c982a28 RH |
2614 | static bool trans_add_c_tsv(DisasContext *ctx, arg_rrr_cf_sh *a) |
2615 | { | |
2616 | return do_add_reg(ctx, a, false, true, false, true); | |
2617 | } | |
b2167459 | 2618 | |
0c982a28 RH |
2619 | static bool trans_sub(DisasContext *ctx, arg_rrr_cf *a) |
2620 | { | |
2621 | return do_sub_reg(ctx, a, false, false, false); | |
b2167459 RH |
2622 | } |
2623 | ||
0c982a28 | 2624 | static bool trans_sub_tsv(DisasContext *ctx, arg_rrr_cf *a) |
b2167459 | 2625 | { |
0c982a28 RH |
2626 | return do_sub_reg(ctx, a, true, false, false); |
2627 | } | |
b2167459 | 2628 | |
0c982a28 RH |
2629 | static bool trans_sub_tc(DisasContext *ctx, arg_rrr_cf *a) |
2630 | { | |
2631 | return do_sub_reg(ctx, a, false, false, true); | |
b2167459 RH |
2632 | } |
2633 | ||
0c982a28 | 2634 | static bool trans_sub_tsv_tc(DisasContext *ctx, arg_rrr_cf *a) |
b2167459 | 2635 | { |
0c982a28 RH |
2636 | return do_sub_reg(ctx, a, true, false, true); |
2637 | } | |
2638 | ||
2639 | static bool trans_sub_b(DisasContext *ctx, arg_rrr_cf *a) | |
2640 | { | |
2641 | return do_sub_reg(ctx, a, false, true, false); | |
2642 | } | |
2643 | ||
2644 | static bool trans_sub_b_tsv(DisasContext *ctx, arg_rrr_cf *a) | |
2645 | { | |
2646 | return do_sub_reg(ctx, a, true, true, false); | |
2647 | } | |
2648 | ||
2649 | static bool trans_andcm(DisasContext *ctx, arg_rrr_cf *a) | |
2650 | { | |
2651 | return do_log_reg(ctx, a, tcg_gen_andc_reg); | |
2652 | } | |
2653 | ||
2654 | static bool trans_and(DisasContext *ctx, arg_rrr_cf *a) | |
2655 | { | |
2656 | return do_log_reg(ctx, a, tcg_gen_and_reg); | |
2657 | } | |
2658 | ||
2659 | static bool trans_or(DisasContext *ctx, arg_rrr_cf *a) | |
2660 | { | |
2661 | if (a->cf == 0) { | |
2662 | unsigned r2 = a->r2; | |
2663 | unsigned r1 = a->r1; | |
2664 | unsigned rt = a->t; | |
b2167459 | 2665 | |
7aee8189 RH |
2666 | if (rt == 0) { /* NOP */ |
2667 | cond_free(&ctx->null_cond); | |
2668 | return true; | |
2669 | } | |
2670 | if (r2 == 0) { /* COPY */ | |
2671 | if (r1 == 0) { | |
2672 | TCGv_reg dest = dest_gpr(ctx, rt); | |
2673 | tcg_gen_movi_reg(dest, 0); | |
2674 | save_gpr(ctx, rt, dest); | |
2675 | } else { | |
2676 | save_gpr(ctx, rt, cpu_gr[r1]); | |
2677 | } | |
2678 | cond_free(&ctx->null_cond); | |
2679 | return true; | |
2680 | } | |
2681 | #ifndef CONFIG_USER_ONLY | |
2682 | /* These are QEMU extensions and are nops in the real architecture: | |
2683 | * | |
2684 | * or %r10,%r10,%r10 -- idle loop; wait for interrupt | |
2685 | * or %r31,%r31,%r31 -- death loop; offline cpu | |
2686 | * currently implemented as idle. | |
2687 | */ | |
2688 | if ((rt == 10 || rt == 31) && r1 == rt && r2 == rt) { /* PAUSE */ | |
7aee8189 RH |
2689 | /* No need to check for supervisor, as userland can only pause |
2690 | until the next timer interrupt. */ | |
2691 | nullify_over(ctx); | |
2692 | ||
2693 | /* Advance the instruction queue. */ | |
2694 | copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); | |
2695 | copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var); | |
2696 | nullify_set(ctx, 0); | |
2697 | ||
2698 | /* Tell the qemu main loop to halt until this cpu has work. */ | |
29dd6f64 RH |
2699 | tcg_gen_st_i32(tcg_constant_i32(1), cpu_env, |
2700 | offsetof(CPUState, halted) - offsetof(HPPACPU, env)); | |
7aee8189 RH |
2701 | gen_excp_1(EXCP_HALTED); |
2702 | ctx->base.is_jmp = DISAS_NORETURN; | |
2703 | ||
2704 | return nullify_end(ctx); | |
2705 | } | |
2706 | #endif | |
b2167459 | 2707 | } |
0c982a28 RH |
2708 | return do_log_reg(ctx, a, tcg_gen_or_reg); |
2709 | } | |
7aee8189 | 2710 | |
0c982a28 RH |
2711 | static bool trans_xor(DisasContext *ctx, arg_rrr_cf *a) |
2712 | { | |
2713 | return do_log_reg(ctx, a, tcg_gen_xor_reg); | |
b2167459 RH |
2714 | } |
2715 | ||
0c982a28 | 2716 | static bool trans_cmpclr(DisasContext *ctx, arg_rrr_cf *a) |
b2167459 | 2717 | { |
eaa3783b | 2718 | TCGv_reg tcg_r1, tcg_r2; |
b2167459 | 2719 | |
0c982a28 | 2720 | if (a->cf) { |
b2167459 RH |
2721 | nullify_over(ctx); |
2722 | } | |
0c982a28 RH |
2723 | tcg_r1 = load_gpr(ctx, a->r1); |
2724 | tcg_r2 = load_gpr(ctx, a->r2); | |
2725 | do_cmpclr(ctx, a->t, tcg_r1, tcg_r2, a->cf); | |
31234768 | 2726 | return nullify_end(ctx); |
b2167459 RH |
2727 | } |
2728 | ||
0c982a28 | 2729 | static bool trans_uxor(DisasContext *ctx, arg_rrr_cf *a) |
b2167459 | 2730 | { |
eaa3783b | 2731 | TCGv_reg tcg_r1, tcg_r2; |
b2167459 | 2732 | |
0c982a28 | 2733 | if (a->cf) { |
b2167459 RH |
2734 | nullify_over(ctx); |
2735 | } | |
0c982a28 RH |
2736 | tcg_r1 = load_gpr(ctx, a->r1); |
2737 | tcg_r2 = load_gpr(ctx, a->r2); | |
2738 | do_unit(ctx, a->t, tcg_r1, tcg_r2, a->cf, false, tcg_gen_xor_reg); | |
31234768 | 2739 | return nullify_end(ctx); |
b2167459 RH |
2740 | } |
2741 | ||
0c982a28 | 2742 | static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf *a, bool is_tc) |
b2167459 | 2743 | { |
eaa3783b | 2744 | TCGv_reg tcg_r1, tcg_r2, tmp; |
b2167459 | 2745 | |
0c982a28 | 2746 | if (a->cf) { |
b2167459 RH |
2747 | nullify_over(ctx); |
2748 | } | |
0c982a28 RH |
2749 | tcg_r1 = load_gpr(ctx, a->r1); |
2750 | tcg_r2 = load_gpr(ctx, a->r2); | |
b2167459 | 2751 | tmp = get_temp(ctx); |
eaa3783b | 2752 | tcg_gen_not_reg(tmp, tcg_r2); |
0c982a28 | 2753 | do_unit(ctx, a->t, tcg_r1, tmp, a->cf, is_tc, tcg_gen_add_reg); |
31234768 | 2754 | return nullify_end(ctx); |
b2167459 RH |
2755 | } |
2756 | ||
0c982a28 RH |
2757 | static bool trans_uaddcm(DisasContext *ctx, arg_rrr_cf *a) |
2758 | { | |
2759 | return do_uaddcm(ctx, a, false); | |
2760 | } | |
2761 | ||
2762 | static bool trans_uaddcm_tc(DisasContext *ctx, arg_rrr_cf *a) | |
2763 | { | |
2764 | return do_uaddcm(ctx, a, true); | |
2765 | } | |
2766 | ||
2767 | static bool do_dcor(DisasContext *ctx, arg_rr_cf *a, bool is_i) | |
b2167459 | 2768 | { |
eaa3783b | 2769 | TCGv_reg tmp; |
b2167459 RH |
2770 | |
2771 | nullify_over(ctx); | |
2772 | ||
2773 | tmp = get_temp(ctx); | |
eaa3783b | 2774 | tcg_gen_shri_reg(tmp, cpu_psw_cb, 3); |
b2167459 | 2775 | if (!is_i) { |
eaa3783b | 2776 | tcg_gen_not_reg(tmp, tmp); |
b2167459 | 2777 | } |
eaa3783b RH |
2778 | tcg_gen_andi_reg(tmp, tmp, 0x11111111); |
2779 | tcg_gen_muli_reg(tmp, tmp, 6); | |
60e29463 | 2780 | do_unit(ctx, a->t, load_gpr(ctx, a->r), tmp, a->cf, false, |
31234768 | 2781 | is_i ? tcg_gen_add_reg : tcg_gen_sub_reg); |
31234768 | 2782 | return nullify_end(ctx); |
b2167459 RH |
2783 | } |
2784 | ||
0c982a28 RH |
2785 | static bool trans_dcor(DisasContext *ctx, arg_rr_cf *a) |
2786 | { | |
2787 | return do_dcor(ctx, a, false); | |
2788 | } | |
2789 | ||
2790 | static bool trans_dcor_i(DisasContext *ctx, arg_rr_cf *a) | |
2791 | { | |
2792 | return do_dcor(ctx, a, true); | |
2793 | } | |
2794 | ||
2795 | static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a) | |
b2167459 | 2796 | { |
eaa3783b | 2797 | TCGv_reg dest, add1, add2, addc, zero, in1, in2; |
b2167459 RH |
2798 | |
2799 | nullify_over(ctx); | |
2800 | ||
0c982a28 RH |
2801 | in1 = load_gpr(ctx, a->r1); |
2802 | in2 = load_gpr(ctx, a->r2); | |
b2167459 RH |
2803 | |
2804 | add1 = tcg_temp_new(); | |
2805 | add2 = tcg_temp_new(); | |
2806 | addc = tcg_temp_new(); | |
2807 | dest = tcg_temp_new(); | |
29dd6f64 | 2808 | zero = tcg_constant_reg(0); |
b2167459 RH |
2809 | |
2810 | /* Form R1 << 1 | PSW[CB]{8}. */ | |
eaa3783b RH |
2811 | tcg_gen_add_reg(add1, in1, in1); |
2812 | tcg_gen_add_reg(add1, add1, cpu_psw_cb_msb); | |
b2167459 RH |
2813 | |
2814 | /* Add or subtract R2, depending on PSW[V]. Proper computation of | |
2815 | carry{8} requires that we subtract via + ~R2 + 1, as described in | |
2816 | the manual. By extracting and masking V, we can produce the | |
2817 | proper inputs to the addition without movcond. */ | |
eaa3783b RH |
2818 | tcg_gen_sari_reg(addc, cpu_psw_v, TARGET_REGISTER_BITS - 1); |
2819 | tcg_gen_xor_reg(add2, in2, addc); | |
2820 | tcg_gen_andi_reg(addc, addc, 1); | |
b2167459 RH |
2821 | /* ??? This is only correct for 32-bit. */ |
2822 | tcg_gen_add2_i32(dest, cpu_psw_cb_msb, add1, zero, add2, zero); | |
2823 | tcg_gen_add2_i32(dest, cpu_psw_cb_msb, dest, cpu_psw_cb_msb, addc, zero); | |
2824 | ||
2825 | tcg_temp_free(addc); | |
b2167459 RH |
2826 | |
2827 | /* Write back the result register. */ | |
0c982a28 | 2828 | save_gpr(ctx, a->t, dest); |
b2167459 RH |
2829 | |
2830 | /* Write back PSW[CB]. */ | |
eaa3783b RH |
2831 | tcg_gen_xor_reg(cpu_psw_cb, add1, add2); |
2832 | tcg_gen_xor_reg(cpu_psw_cb, cpu_psw_cb, dest); | |
b2167459 RH |
2833 | |
2834 | /* Write back PSW[V] for the division step. */ | |
eaa3783b RH |
2835 | tcg_gen_neg_reg(cpu_psw_v, cpu_psw_cb_msb); |
2836 | tcg_gen_xor_reg(cpu_psw_v, cpu_psw_v, in2); | |
b2167459 RH |
2837 | |
2838 | /* Install the new nullification. */ | |
0c982a28 | 2839 | if (a->cf) { |
eaa3783b | 2840 | TCGv_reg sv = NULL; |
b47a4a02 | 2841 | if (cond_need_sv(a->cf >> 1)) { |
b2167459 RH |
2842 | /* ??? The lshift is supposed to contribute to overflow. */ |
2843 | sv = do_add_sv(ctx, dest, add1, add2); | |
2844 | } | |
0c982a28 | 2845 | ctx->null_cond = do_cond(a->cf, dest, cpu_psw_cb_msb, sv); |
b2167459 RH |
2846 | } |
2847 | ||
2848 | tcg_temp_free(add1); | |
2849 | tcg_temp_free(add2); | |
2850 | tcg_temp_free(dest); | |
2851 | ||
31234768 | 2852 | return nullify_end(ctx); |
b2167459 RH |
2853 | } |
2854 | ||
0588e061 | 2855 | static bool trans_addi(DisasContext *ctx, arg_rri_cf *a) |
b2167459 | 2856 | { |
0588e061 RH |
2857 | return do_add_imm(ctx, a, false, false); |
2858 | } | |
b2167459 | 2859 | |
0588e061 RH |
2860 | static bool trans_addi_tsv(DisasContext *ctx, arg_rri_cf *a) |
2861 | { | |
2862 | return do_add_imm(ctx, a, true, false); | |
b2167459 RH |
2863 | } |
2864 | ||
0588e061 | 2865 | static bool trans_addi_tc(DisasContext *ctx, arg_rri_cf *a) |
b2167459 | 2866 | { |
0588e061 RH |
2867 | return do_add_imm(ctx, a, false, true); |
2868 | } | |
b2167459 | 2869 | |
0588e061 RH |
2870 | static bool trans_addi_tc_tsv(DisasContext *ctx, arg_rri_cf *a) |
2871 | { | |
2872 | return do_add_imm(ctx, a, true, true); | |
2873 | } | |
b2167459 | 2874 | |
0588e061 RH |
2875 | static bool trans_subi(DisasContext *ctx, arg_rri_cf *a) |
2876 | { | |
2877 | return do_sub_imm(ctx, a, false); | |
2878 | } | |
b2167459 | 2879 | |
0588e061 RH |
2880 | static bool trans_subi_tsv(DisasContext *ctx, arg_rri_cf *a) |
2881 | { | |
2882 | return do_sub_imm(ctx, a, true); | |
b2167459 RH |
2883 | } |
2884 | ||
0588e061 | 2885 | static bool trans_cmpiclr(DisasContext *ctx, arg_rri_cf *a) |
b2167459 | 2886 | { |
eaa3783b | 2887 | TCGv_reg tcg_im, tcg_r2; |
b2167459 | 2888 | |
0588e061 | 2889 | if (a->cf) { |
b2167459 RH |
2890 | nullify_over(ctx); |
2891 | } | |
2892 | ||
0588e061 RH |
2893 | tcg_im = load_const(ctx, a->i); |
2894 | tcg_r2 = load_gpr(ctx, a->r); | |
2895 | do_cmpclr(ctx, a->t, tcg_im, tcg_r2, a->cf); | |
b2167459 | 2896 | |
31234768 | 2897 | return nullify_end(ctx); |
b2167459 RH |
2898 | } |
2899 | ||
1cd012a5 | 2900 | static bool trans_ld(DisasContext *ctx, arg_ldst *a) |
96d6407f | 2901 | { |
1cd012a5 RH |
2902 | return do_load(ctx, a->t, a->b, a->x, a->scale ? a->size : 0, |
2903 | a->disp, a->sp, a->m, a->size | MO_TE); | |
96d6407f RH |
2904 | } |
2905 | ||
1cd012a5 | 2906 | static bool trans_st(DisasContext *ctx, arg_ldst *a) |
96d6407f | 2907 | { |
1cd012a5 RH |
2908 | assert(a->x == 0 && a->scale == 0); |
2909 | return do_store(ctx, a->t, a->b, a->disp, a->sp, a->m, a->size | MO_TE); | |
96d6407f RH |
2910 | } |
2911 | ||
1cd012a5 | 2912 | static bool trans_ldc(DisasContext *ctx, arg_ldst *a) |
96d6407f | 2913 | { |
b1af755c | 2914 | MemOp mop = MO_TE | MO_ALIGN | a->size; |
86f8d05f RH |
2915 | TCGv_reg zero, dest, ofs; |
2916 | TCGv_tl addr; | |
96d6407f RH |
2917 | |
2918 | nullify_over(ctx); | |
2919 | ||
1cd012a5 | 2920 | if (a->m) { |
86f8d05f RH |
2921 | /* Base register modification. Make sure if RT == RB, |
2922 | we see the result of the load. */ | |
96d6407f RH |
2923 | dest = get_temp(ctx); |
2924 | } else { | |
1cd012a5 | 2925 | dest = dest_gpr(ctx, a->t); |
96d6407f RH |
2926 | } |
2927 | ||
1cd012a5 RH |
2928 | form_gva(ctx, &addr, &ofs, a->b, a->x, a->scale ? a->size : 0, |
2929 | a->disp, a->sp, a->m, ctx->mmu_idx == MMU_PHYS_IDX); | |
b1af755c RH |
2930 | |
2931 | /* | |
2932 | * For hppa1.1, LDCW is undefined unless aligned mod 16. | |
2933 | * However actual hardware succeeds with aligned mod 4. | |
2934 | * Detect this case and log a GUEST_ERROR. | |
2935 | * | |
2936 | * TODO: HPPA64 relaxes the over-alignment requirement | |
2937 | * with the ,co completer. | |
2938 | */ | |
2939 | gen_helper_ldc_check(addr); | |
2940 | ||
29dd6f64 | 2941 | zero = tcg_constant_reg(0); |
86f8d05f | 2942 | tcg_gen_atomic_xchg_reg(dest, addr, zero, ctx->mmu_idx, mop); |
b1af755c | 2943 | |
1cd012a5 RH |
2944 | if (a->m) { |
2945 | save_gpr(ctx, a->b, ofs); | |
96d6407f | 2946 | } |
1cd012a5 | 2947 | save_gpr(ctx, a->t, dest); |
96d6407f | 2948 | |
31234768 | 2949 | return nullify_end(ctx); |
96d6407f RH |
2950 | } |
2951 | ||
1cd012a5 | 2952 | static bool trans_stby(DisasContext *ctx, arg_stby *a) |
96d6407f | 2953 | { |
86f8d05f RH |
2954 | TCGv_reg ofs, val; |
2955 | TCGv_tl addr; | |
96d6407f RH |
2956 | |
2957 | nullify_over(ctx); | |
2958 | ||
1cd012a5 | 2959 | form_gva(ctx, &addr, &ofs, a->b, 0, 0, a->disp, a->sp, a->m, |
86f8d05f | 2960 | ctx->mmu_idx == MMU_PHYS_IDX); |
1cd012a5 RH |
2961 | val = load_gpr(ctx, a->r); |
2962 | if (a->a) { | |
f9f46db4 EC |
2963 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { |
2964 | gen_helper_stby_e_parallel(cpu_env, addr, val); | |
2965 | } else { | |
2966 | gen_helper_stby_e(cpu_env, addr, val); | |
2967 | } | |
96d6407f | 2968 | } else { |
f9f46db4 EC |
2969 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { |
2970 | gen_helper_stby_b_parallel(cpu_env, addr, val); | |
2971 | } else { | |
2972 | gen_helper_stby_b(cpu_env, addr, val); | |
2973 | } | |
96d6407f | 2974 | } |
1cd012a5 | 2975 | if (a->m) { |
86f8d05f | 2976 | tcg_gen_andi_reg(ofs, ofs, ~3); |
1cd012a5 | 2977 | save_gpr(ctx, a->b, ofs); |
96d6407f | 2978 | } |
96d6407f | 2979 | |
31234768 | 2980 | return nullify_end(ctx); |
96d6407f RH |
2981 | } |
2982 | ||
1cd012a5 | 2983 | static bool trans_lda(DisasContext *ctx, arg_ldst *a) |
d0a851cc RH |
2984 | { |
2985 | int hold_mmu_idx = ctx->mmu_idx; | |
d0a851cc RH |
2986 | |
2987 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); | |
d0a851cc | 2988 | ctx->mmu_idx = MMU_PHYS_IDX; |
1cd012a5 | 2989 | trans_ld(ctx, a); |
d0a851cc | 2990 | ctx->mmu_idx = hold_mmu_idx; |
31234768 | 2991 | return true; |
d0a851cc RH |
2992 | } |
2993 | ||
1cd012a5 | 2994 | static bool trans_sta(DisasContext *ctx, arg_ldst *a) |
d0a851cc RH |
2995 | { |
2996 | int hold_mmu_idx = ctx->mmu_idx; | |
d0a851cc RH |
2997 | |
2998 | CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); | |
d0a851cc | 2999 | ctx->mmu_idx = MMU_PHYS_IDX; |
1cd012a5 | 3000 | trans_st(ctx, a); |
d0a851cc | 3001 | ctx->mmu_idx = hold_mmu_idx; |
31234768 | 3002 | return true; |
d0a851cc | 3003 | } |
95412a61 | 3004 | |
0588e061 | 3005 | static bool trans_ldil(DisasContext *ctx, arg_ldil *a) |
b2167459 | 3006 | { |
0588e061 | 3007 | TCGv_reg tcg_rt = dest_gpr(ctx, a->t); |
b2167459 | 3008 | |
0588e061 RH |
3009 | tcg_gen_movi_reg(tcg_rt, a->i); |
3010 | save_gpr(ctx, a->t, tcg_rt); | |
b2167459 | 3011 | cond_free(&ctx->null_cond); |
31234768 | 3012 | return true; |
b2167459 RH |
3013 | } |
3014 | ||
0588e061 | 3015 | static bool trans_addil(DisasContext *ctx, arg_addil *a) |
b2167459 | 3016 | { |
0588e061 | 3017 | TCGv_reg tcg_rt = load_gpr(ctx, a->r); |
eaa3783b | 3018 | TCGv_reg tcg_r1 = dest_gpr(ctx, 1); |
b2167459 | 3019 | |
0588e061 | 3020 | tcg_gen_addi_reg(tcg_r1, tcg_rt, a->i); |
b2167459 RH |
3021 | save_gpr(ctx, 1, tcg_r1); |
3022 | cond_free(&ctx->null_cond); | |
31234768 | 3023 | return true; |
b2167459 RH |
3024 | } |
3025 | ||
0588e061 | 3026 | static bool trans_ldo(DisasContext *ctx, arg_ldo *a) |
b2167459 | 3027 | { |
0588e061 | 3028 | TCGv_reg tcg_rt = dest_gpr(ctx, a->t); |
b2167459 RH |
3029 | |
3030 | /* Special case rb == 0, for the LDI pseudo-op. | |
3031 | The COPY pseudo-op is handled for free within tcg_gen_addi_tl. */ | |
0588e061 RH |
3032 | if (a->b == 0) { |
3033 | tcg_gen_movi_reg(tcg_rt, a->i); | |
b2167459 | 3034 | } else { |
0588e061 | 3035 | tcg_gen_addi_reg(tcg_rt, cpu_gr[a->b], a->i); |
b2167459 | 3036 | } |
0588e061 | 3037 | save_gpr(ctx, a->t, tcg_rt); |
b2167459 | 3038 | cond_free(&ctx->null_cond); |
31234768 | 3039 | return true; |
b2167459 RH |
3040 | } |
3041 | ||
01afb7be RH |
3042 | static bool do_cmpb(DisasContext *ctx, unsigned r, TCGv_reg in1, |
3043 | unsigned c, unsigned f, unsigned n, int disp) | |
98cd9ca7 | 3044 | { |
01afb7be | 3045 | TCGv_reg dest, in2, sv; |
98cd9ca7 RH |
3046 | DisasCond cond; |
3047 | ||
98cd9ca7 RH |
3048 | in2 = load_gpr(ctx, r); |
3049 | dest = get_temp(ctx); | |
3050 | ||
eaa3783b | 3051 | tcg_gen_sub_reg(dest, in1, in2); |
98cd9ca7 | 3052 | |
f764718d | 3053 | sv = NULL; |
b47a4a02 | 3054 | if (cond_need_sv(c)) { |
98cd9ca7 RH |
3055 | sv = do_sub_sv(ctx, dest, in1, in2); |
3056 | } | |
3057 | ||
01afb7be RH |
3058 | cond = do_sub_cond(c * 2 + f, dest, in1, in2, sv); |
3059 | return do_cbranch(ctx, disp, n, &cond); | |
98cd9ca7 RH |
3060 | } |
3061 | ||
01afb7be | 3062 | static bool trans_cmpb(DisasContext *ctx, arg_cmpb *a) |
98cd9ca7 | 3063 | { |
01afb7be RH |
3064 | nullify_over(ctx); |
3065 | return do_cmpb(ctx, a->r2, load_gpr(ctx, a->r1), a->c, a->f, a->n, a->disp); | |
3066 | } | |
98cd9ca7 | 3067 | |
01afb7be RH |
3068 | static bool trans_cmpbi(DisasContext *ctx, arg_cmpbi *a) |
3069 | { | |
98cd9ca7 | 3070 | nullify_over(ctx); |
01afb7be RH |
3071 | return do_cmpb(ctx, a->r, load_const(ctx, a->i), a->c, a->f, a->n, a->disp); |
3072 | } | |
3073 | ||
3074 | static bool do_addb(DisasContext *ctx, unsigned r, TCGv_reg in1, | |
3075 | unsigned c, unsigned f, unsigned n, int disp) | |
3076 | { | |
3077 | TCGv_reg dest, in2, sv, cb_msb; | |
3078 | DisasCond cond; | |
98cd9ca7 | 3079 | |
98cd9ca7 | 3080 | in2 = load_gpr(ctx, r); |
43675d20 | 3081 | dest = tcg_temp_new(); |
f764718d RH |
3082 | sv = NULL; |
3083 | cb_msb = NULL; | |
98cd9ca7 | 3084 | |
b47a4a02 | 3085 | if (cond_need_cb(c)) { |
98cd9ca7 | 3086 | cb_msb = get_temp(ctx); |
eaa3783b RH |
3087 | tcg_gen_movi_reg(cb_msb, 0); |
3088 | tcg_gen_add2_reg(dest, cb_msb, in1, cb_msb, in2, cb_msb); | |
b47a4a02 | 3089 | } else { |
eaa3783b | 3090 | tcg_gen_add_reg(dest, in1, in2); |
b47a4a02 SS |
3091 | } |
3092 | if (cond_need_sv(c)) { | |
98cd9ca7 | 3093 | sv = do_add_sv(ctx, dest, in1, in2); |
98cd9ca7 RH |
3094 | } |
3095 | ||
01afb7be | 3096 | cond = do_cond(c * 2 + f, dest, cb_msb, sv); |
43675d20 SS |
3097 | save_gpr(ctx, r, dest); |
3098 | tcg_temp_free(dest); | |
01afb7be | 3099 | return do_cbranch(ctx, disp, n, &cond); |
98cd9ca7 RH |
3100 | } |
3101 | ||
01afb7be RH |
3102 | static bool trans_addb(DisasContext *ctx, arg_addb *a) |
3103 | { | |
3104 | nullify_over(ctx); | |
3105 | return do_addb(ctx, a->r2, load_gpr(ctx, a->r1), a->c, a->f, a->n, a->disp); | |
3106 | } | |
3107 | ||
3108 | static bool trans_addbi(DisasContext *ctx, arg_addbi *a) | |
3109 | { | |
3110 | nullify_over(ctx); | |
3111 | return do_addb(ctx, a->r, load_const(ctx, a->i), a->c, a->f, a->n, a->disp); | |
3112 | } | |
3113 | ||
3114 | static bool trans_bb_sar(DisasContext *ctx, arg_bb_sar *a) | |
98cd9ca7 | 3115 | { |
eaa3783b | 3116 | TCGv_reg tmp, tcg_r; |
98cd9ca7 RH |
3117 | DisasCond cond; |
3118 | ||
3119 | nullify_over(ctx); | |
3120 | ||
3121 | tmp = tcg_temp_new(); | |
01afb7be RH |
3122 | tcg_r = load_gpr(ctx, a->r); |
3123 | tcg_gen_shl_reg(tmp, tcg_r, cpu_sar); | |
98cd9ca7 | 3124 | |
01afb7be | 3125 | cond = cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp); |
98cd9ca7 | 3126 | tcg_temp_free(tmp); |
01afb7be | 3127 | return do_cbranch(ctx, a->disp, a->n, &cond); |
98cd9ca7 RH |
3128 | } |
3129 | ||
01afb7be RH |
3130 | static bool trans_bb_imm(DisasContext *ctx, arg_bb_imm *a) |
3131 | { | |
3132 | TCGv_reg tmp, tcg_r; | |
3133 | DisasCond cond; | |
3134 | ||
3135 | nullify_over(ctx); | |
3136 | ||
3137 | tmp = tcg_temp_new(); | |
3138 | tcg_r = load_gpr(ctx, a->r); | |
3139 | tcg_gen_shli_reg(tmp, tcg_r, a->p); | |
3140 | ||
3141 | cond = cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp); | |
3142 | tcg_temp_free(tmp); | |
3143 | return do_cbranch(ctx, a->disp, a->n, &cond); | |
3144 | } | |
3145 | ||
3146 | static bool trans_movb(DisasContext *ctx, arg_movb *a) | |
98cd9ca7 | 3147 | { |
eaa3783b | 3148 | TCGv_reg dest; |
98cd9ca7 RH |
3149 | DisasCond cond; |
3150 | ||
3151 | nullify_over(ctx); | |
3152 | ||
01afb7be RH |
3153 | dest = dest_gpr(ctx, a->r2); |
3154 | if (a->r1 == 0) { | |
eaa3783b | 3155 | tcg_gen_movi_reg(dest, 0); |
98cd9ca7 | 3156 | } else { |
01afb7be | 3157 | tcg_gen_mov_reg(dest, cpu_gr[a->r1]); |
98cd9ca7 RH |
3158 | } |
3159 | ||
01afb7be RH |
3160 | cond = do_sed_cond(a->c, dest); |
3161 | return do_cbranch(ctx, a->disp, a->n, &cond); | |
3162 | } | |
3163 | ||
3164 | static bool trans_movbi(DisasContext *ctx, arg_movbi *a) | |
3165 | { | |
3166 | TCGv_reg dest; | |
3167 | DisasCond cond; | |
3168 | ||
3169 | nullify_over(ctx); | |
3170 | ||
3171 | dest = dest_gpr(ctx, a->r); | |
3172 | tcg_gen_movi_reg(dest, a->i); | |
3173 | ||
3174 | cond = do_sed_cond(a->c, dest); | |
3175 | return do_cbranch(ctx, a->disp, a->n, &cond); | |
98cd9ca7 RH |
3176 | } |
3177 | ||
30878590 | 3178 | static bool trans_shrpw_sar(DisasContext *ctx, arg_shrpw_sar *a) |
0b1347d2 | 3179 | { |
eaa3783b | 3180 | TCGv_reg dest; |
0b1347d2 | 3181 | |
30878590 | 3182 | if (a->c) { |
0b1347d2 RH |
3183 | nullify_over(ctx); |
3184 | } | |
3185 | ||
30878590 RH |
3186 | dest = dest_gpr(ctx, a->t); |
3187 | if (a->r1 == 0) { | |
3188 | tcg_gen_ext32u_reg(dest, load_gpr(ctx, a->r2)); | |
eaa3783b | 3189 | tcg_gen_shr_reg(dest, dest, cpu_sar); |
30878590 | 3190 | } else if (a->r1 == a->r2) { |
0b1347d2 | 3191 | TCGv_i32 t32 = tcg_temp_new_i32(); |
30878590 | 3192 | tcg_gen_trunc_reg_i32(t32, load_gpr(ctx, a->r2)); |
0b1347d2 | 3193 | tcg_gen_rotr_i32(t32, t32, cpu_sar); |
eaa3783b | 3194 | tcg_gen_extu_i32_reg(dest, t32); |
0b1347d2 RH |
3195 | tcg_temp_free_i32(t32); |
3196 | } else { | |
3197 | TCGv_i64 t = tcg_temp_new_i64(); | |
3198 | TCGv_i64 s = tcg_temp_new_i64(); | |
3199 | ||
30878590 | 3200 | tcg_gen_concat_reg_i64(t, load_gpr(ctx, a->r2), load_gpr(ctx, a->r1)); |
eaa3783b | 3201 | tcg_gen_extu_reg_i64(s, cpu_sar); |
0b1347d2 | 3202 | tcg_gen_shr_i64(t, t, s); |
eaa3783b | 3203 | tcg_gen_trunc_i64_reg(dest, t); |
0b1347d2 RH |
3204 | |
3205 | tcg_temp_free_i64(t); | |
3206 | tcg_temp_free_i64(s); | |
3207 | } | |
30878590 | 3208 | save_gpr(ctx, a->t, dest); |
0b1347d2 RH |
3209 | |
3210 | /* Install the new nullification. */ | |
3211 | cond_free(&ctx->null_cond); | |
30878590 RH |
3212 | if (a->c) { |
3213 | ctx->null_cond = do_sed_cond(a->c, dest); | |
0b1347d2 | 3214 | } |
31234768 | 3215 | return nullify_end(ctx); |
0b1347d2 RH |
3216 | } |
3217 | ||
30878590 | 3218 | static bool trans_shrpw_imm(DisasContext *ctx, arg_shrpw_imm *a) |
0b1347d2 | 3219 | { |
30878590 | 3220 | unsigned sa = 31 - a->cpos; |
eaa3783b | 3221 | TCGv_reg dest, t2; |
0b1347d2 | 3222 | |
30878590 | 3223 | if (a->c) { |
0b1347d2 RH |
3224 | nullify_over(ctx); |
3225 | } | |
3226 | ||
30878590 RH |
3227 | dest = dest_gpr(ctx, a->t); |
3228 | t2 = load_gpr(ctx, a->r2); | |
05bfd4db RH |
3229 | if (a->r1 == 0) { |
3230 | tcg_gen_extract_reg(dest, t2, sa, 32 - sa); | |
3231 | } else if (TARGET_REGISTER_BITS == 32) { | |
3232 | tcg_gen_extract2_reg(dest, t2, cpu_gr[a->r1], sa); | |
3233 | } else if (a->r1 == a->r2) { | |
0b1347d2 | 3234 | TCGv_i32 t32 = tcg_temp_new_i32(); |
eaa3783b | 3235 | tcg_gen_trunc_reg_i32(t32, t2); |
0b1347d2 | 3236 | tcg_gen_rotri_i32(t32, t32, sa); |
eaa3783b | 3237 | tcg_gen_extu_i32_reg(dest, t32); |
0b1347d2 | 3238 | tcg_temp_free_i32(t32); |
0b1347d2 | 3239 | } else { |
05bfd4db RH |
3240 | TCGv_i64 t64 = tcg_temp_new_i64(); |
3241 | tcg_gen_concat_reg_i64(t64, t2, cpu_gr[a->r1]); | |
3242 | tcg_gen_shri_i64(t64, t64, sa); | |
3243 | tcg_gen_trunc_i64_reg(dest, t64); | |
3244 | tcg_temp_free_i64(t64); | |
0b1347d2 | 3245 | } |
30878590 | 3246 | save_gpr(ctx, a->t, dest); |
0b1347d2 RH |
3247 | |
3248 | /* Install the new nullification. */ | |
3249 | cond_free(&ctx->null_cond); | |
30878590 RH |
3250 | if (a->c) { |
3251 | ctx->null_cond = do_sed_cond(a->c, dest); | |
0b1347d2 | 3252 | } |
31234768 | 3253 | return nullify_end(ctx); |
0b1347d2 RH |
3254 | } |
3255 | ||
30878590 | 3256 | static bool trans_extrw_sar(DisasContext *ctx, arg_extrw_sar *a) |
0b1347d2 | 3257 | { |
30878590 | 3258 | unsigned len = 32 - a->clen; |
eaa3783b | 3259 | TCGv_reg dest, src, tmp; |
0b1347d2 | 3260 | |
30878590 | 3261 | if (a->c) { |
0b1347d2 RH |
3262 | nullify_over(ctx); |
3263 | } | |
3264 | ||
30878590 RH |
3265 | dest = dest_gpr(ctx, a->t); |
3266 | src = load_gpr(ctx, a->r); | |
0b1347d2 RH |
3267 | tmp = tcg_temp_new(); |
3268 | ||
3269 | /* Recall that SAR is using big-endian bit numbering. */ | |
eaa3783b | 3270 | tcg_gen_xori_reg(tmp, cpu_sar, TARGET_REGISTER_BITS - 1); |
30878590 | 3271 | if (a->se) { |
eaa3783b RH |
3272 | tcg_gen_sar_reg(dest, src, tmp); |
3273 | tcg_gen_sextract_reg(dest, dest, 0, len); | |
0b1347d2 | 3274 | } else { |
eaa3783b RH |
3275 | tcg_gen_shr_reg(dest, src, tmp); |
3276 | tcg_gen_extract_reg(dest, dest, 0, len); | |
0b1347d2 RH |
3277 | } |
3278 | tcg_temp_free(tmp); | |
30878590 | 3279 | save_gpr(ctx, a->t, dest); |
0b1347d2 RH |
3280 | |
3281 | /* Install the new nullification. */ | |
3282 | cond_free(&ctx->null_cond); | |
30878590 RH |
3283 | if (a->c) { |
3284 | ctx->null_cond = do_sed_cond(a->c, dest); | |
0b1347d2 | 3285 | } |
31234768 | 3286 | return nullify_end(ctx); |
0b1347d2 RH |
3287 | } |
3288 | ||
30878590 | 3289 | static bool trans_extrw_imm(DisasContext *ctx, arg_extrw_imm *a) |
0b1347d2 | 3290 | { |
30878590 RH |
3291 | unsigned len = 32 - a->clen; |
3292 | unsigned cpos = 31 - a->pos; | |
eaa3783b | 3293 | TCGv_reg dest, src; |
0b1347d2 | 3294 | |
30878590 | 3295 | if (a->c) { |
0b1347d2 RH |
3296 | nullify_over(ctx); |
3297 | } | |
3298 | ||
30878590 RH |
3299 | dest = dest_gpr(ctx, a->t); |
3300 | src = load_gpr(ctx, a->r); | |
3301 | if (a->se) { | |
eaa3783b | 3302 | tcg_gen_sextract_reg(dest, src, cpos, len); |
0b1347d2 | 3303 | } else { |
eaa3783b | 3304 | tcg_gen_extract_reg(dest, src, cpos, len); |
0b1347d2 | 3305 | } |
30878590 | 3306 | save_gpr(ctx, a->t, dest); |
0b1347d2 RH |
3307 | |
3308 | /* Install the new nullification. */ | |
3309 | cond_free(&ctx->null_cond); | |
30878590 RH |
3310 | if (a->c) { |
3311 | ctx->null_cond = do_sed_cond(a->c, dest); | |
0b1347d2 | 3312 | } |
31234768 | 3313 | return nullify_end(ctx); |
0b1347d2 RH |
3314 | } |
3315 | ||
30878590 | 3316 | static bool trans_depwi_imm(DisasContext *ctx, arg_depwi_imm *a) |
0b1347d2 | 3317 | { |
30878590 | 3318 | unsigned len = 32 - a->clen; |
eaa3783b RH |
3319 | target_sreg mask0, mask1; |
3320 | TCGv_reg dest; | |
0b1347d2 | 3321 | |
30878590 | 3322 | if (a->c) { |
0b1347d2 RH |
3323 | nullify_over(ctx); |
3324 | } | |
30878590 RH |
3325 | if (a->cpos + len > 32) { |
3326 | len = 32 - a->cpos; | |
0b1347d2 RH |
3327 | } |
3328 | ||
30878590 RH |
3329 | dest = dest_gpr(ctx, a->t); |
3330 | mask0 = deposit64(0, a->cpos, len, a->i); | |
3331 | mask1 = deposit64(-1, a->cpos, len, a->i); | |
0b1347d2 | 3332 | |
30878590 RH |
3333 | if (a->nz) { |
3334 | TCGv_reg src = load_gpr(ctx, a->t); | |
0b1347d2 | 3335 | if (mask1 != -1) { |
eaa3783b | 3336 | tcg_gen_andi_reg(dest, src, mask1); |
0b1347d2 RH |
3337 | src = dest; |
3338 | } | |
eaa3783b | 3339 | tcg_gen_ori_reg(dest, src, mask0); |
0b1347d2 | 3340 | } else { |
eaa3783b | 3341 | tcg_gen_movi_reg(dest, mask0); |
0b1347d2 | 3342 | } |
30878590 | 3343 | save_gpr(ctx, a->t, dest); |
0b1347d2 RH |
3344 | |
3345 | /* Install the new nullification. */ | |
3346 | cond_free(&ctx->null_cond); | |
30878590 RH |
3347 | if (a->c) { |
3348 | ctx->null_cond = do_sed_cond(a->c, dest); | |
0b1347d2 | 3349 | } |
31234768 | 3350 | return nullify_end(ctx); |
0b1347d2 RH |
3351 | } |
3352 | ||
30878590 | 3353 | static bool trans_depw_imm(DisasContext *ctx, arg_depw_imm *a) |
0b1347d2 | 3354 | { |
30878590 RH |
3355 | unsigned rs = a->nz ? a->t : 0; |
3356 | unsigned len = 32 - a->clen; | |
eaa3783b | 3357 | TCGv_reg dest, val; |
0b1347d2 | 3358 | |
30878590 | 3359 | if (a->c) { |
0b1347d2 RH |
3360 | nullify_over(ctx); |
3361 | } | |
30878590 RH |
3362 | if (a->cpos + len > 32) { |
3363 | len = 32 - a->cpos; | |
0b1347d2 RH |
3364 | } |
3365 | ||
30878590 RH |
3366 | dest = dest_gpr(ctx, a->t); |
3367 | val = load_gpr(ctx, a->r); | |
0b1347d2 | 3368 | if (rs == 0) { |
30878590 | 3369 | tcg_gen_deposit_z_reg(dest, val, a->cpos, len); |
0b1347d2 | 3370 | } else { |
30878590 | 3371 | tcg_gen_deposit_reg(dest, cpu_gr[rs], val, a->cpos, len); |
0b1347d2 | 3372 | } |
30878590 | 3373 | save_gpr(ctx, a->t, dest); |
0b1347d2 RH |
3374 | |
3375 | /* Install the new nullification. */ | |
3376 | cond_free(&ctx->null_cond); | |
30878590 RH |
3377 | if (a->c) { |
3378 | ctx->null_cond = do_sed_cond(a->c, dest); | |
0b1347d2 | 3379 | } |
31234768 | 3380 | return nullify_end(ctx); |
0b1347d2 RH |
3381 | } |
3382 | ||
30878590 RH |
3383 | static bool do_depw_sar(DisasContext *ctx, unsigned rt, unsigned c, |
3384 | unsigned nz, unsigned clen, TCGv_reg val) | |
0b1347d2 | 3385 | { |
0b1347d2 RH |
3386 | unsigned rs = nz ? rt : 0; |
3387 | unsigned len = 32 - clen; | |
30878590 | 3388 | TCGv_reg mask, tmp, shift, dest; |
0b1347d2 RH |
3389 | unsigned msb = 1U << (len - 1); |
3390 | ||
0b1347d2 RH |
3391 | dest = dest_gpr(ctx, rt); |
3392 | shift = tcg_temp_new(); | |
3393 | tmp = tcg_temp_new(); | |
3394 | ||
3395 | /* Convert big-endian bit numbering in SAR to left-shift. */ | |
eaa3783b | 3396 | tcg_gen_xori_reg(shift, cpu_sar, TARGET_REGISTER_BITS - 1); |
0b1347d2 | 3397 | |
eaa3783b RH |
3398 | mask = tcg_const_reg(msb + (msb - 1)); |
3399 | tcg_gen_and_reg(tmp, val, mask); | |
0b1347d2 | 3400 | if (rs) { |
eaa3783b RH |
3401 | tcg_gen_shl_reg(mask, mask, shift); |
3402 | tcg_gen_shl_reg(tmp, tmp, shift); | |
3403 | tcg_gen_andc_reg(dest, cpu_gr[rs], mask); | |
3404 | tcg_gen_or_reg(dest, dest, tmp); | |
0b1347d2 | 3405 | } else { |
eaa3783b | 3406 | tcg_gen_shl_reg(dest, tmp, shift); |
0b1347d2 RH |
3407 | } |
3408 | tcg_temp_free(shift); | |
3409 | tcg_temp_free(mask); | |
3410 | tcg_temp_free(tmp); | |
3411 | save_gpr(ctx, rt, dest); | |
3412 | ||
3413 | /* Install the new nullification. */ | |
3414 | cond_free(&ctx->null_cond); | |
3415 | if (c) { | |
3416 | ctx->null_cond = do_sed_cond(c, dest); | |
3417 | } | |
31234768 | 3418 | return nullify_end(ctx); |
0b1347d2 RH |
3419 | } |
3420 | ||
30878590 RH |
3421 | static bool trans_depw_sar(DisasContext *ctx, arg_depw_sar *a) |
3422 | { | |
a6deecce SS |
3423 | if (a->c) { |
3424 | nullify_over(ctx); | |
3425 | } | |
30878590 RH |
3426 | return do_depw_sar(ctx, a->t, a->c, a->nz, a->clen, load_gpr(ctx, a->r)); |
3427 | } | |
3428 | ||
3429 | static bool trans_depwi_sar(DisasContext *ctx, arg_depwi_sar *a) | |
3430 | { | |
a6deecce SS |
3431 | if (a->c) { |
3432 | nullify_over(ctx); | |
3433 | } | |
30878590 RH |
3434 | return do_depw_sar(ctx, a->t, a->c, a->nz, a->clen, load_const(ctx, a->i)); |
3435 | } | |
0b1347d2 | 3436 | |
8340f534 | 3437 | static bool trans_be(DisasContext *ctx, arg_be *a) |
98cd9ca7 | 3438 | { |
660eefe1 | 3439 | TCGv_reg tmp; |
98cd9ca7 | 3440 | |
c301f34e | 3441 | #ifdef CONFIG_USER_ONLY |
98cd9ca7 RH |
3442 | /* ??? It seems like there should be a good way of using |
3443 | "be disp(sr2, r0)", the canonical gateway entry mechanism | |
3444 | to our advantage. But that appears to be inconvenient to | |
3445 | manage along side branch delay slots. Therefore we handle | |
3446 | entry into the gateway page via absolute address. */ | |
98cd9ca7 RH |
3447 | /* Since we don't implement spaces, just branch. Do notice the special |
3448 | case of "be disp(*,r0)" using a direct branch to disp, so that we can | |
3449 | goto_tb to the TB containing the syscall. */ | |
8340f534 RH |
3450 | if (a->b == 0) { |
3451 | return do_dbranch(ctx, a->disp, a->l, a->n); | |
98cd9ca7 | 3452 | } |
c301f34e | 3453 | #else |
c301f34e | 3454 | nullify_over(ctx); |
660eefe1 RH |
3455 | #endif |
3456 | ||
3457 | tmp = get_temp(ctx); | |
8340f534 | 3458 | tcg_gen_addi_reg(tmp, load_gpr(ctx, a->b), a->disp); |
660eefe1 | 3459 | tmp = do_ibranch_priv(ctx, tmp); |
c301f34e RH |
3460 | |
3461 | #ifdef CONFIG_USER_ONLY | |
8340f534 | 3462 | return do_ibranch(ctx, tmp, a->l, a->n); |
c301f34e RH |
3463 | #else |
3464 | TCGv_i64 new_spc = tcg_temp_new_i64(); | |
3465 | ||
8340f534 RH |
3466 | load_spr(ctx, new_spc, a->sp); |
3467 | if (a->l) { | |
c301f34e RH |
3468 | copy_iaoq_entry(cpu_gr[31], ctx->iaoq_n, ctx->iaoq_n_var); |
3469 | tcg_gen_mov_i64(cpu_sr[0], cpu_iasq_f); | |
3470 | } | |
8340f534 | 3471 | if (a->n && use_nullify_skip(ctx)) { |
c301f34e RH |
3472 | tcg_gen_mov_reg(cpu_iaoq_f, tmp); |
3473 | tcg_gen_addi_reg(cpu_iaoq_b, cpu_iaoq_f, 4); | |
3474 | tcg_gen_mov_i64(cpu_iasq_f, new_spc); | |
3475 | tcg_gen_mov_i64(cpu_iasq_b, cpu_iasq_f); | |
3476 | } else { | |
3477 | copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); | |
3478 | if (ctx->iaoq_b == -1) { | |
3479 | tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); | |
3480 | } | |
3481 | tcg_gen_mov_reg(cpu_iaoq_b, tmp); | |
3482 | tcg_gen_mov_i64(cpu_iasq_b, new_spc); | |
8340f534 | 3483 | nullify_set(ctx, a->n); |
c301f34e RH |
3484 | } |
3485 | tcg_temp_free_i64(new_spc); | |
3486 | tcg_gen_lookup_and_goto_ptr(); | |
31234768 RH |
3487 | ctx->base.is_jmp = DISAS_NORETURN; |
3488 | return nullify_end(ctx); | |
c301f34e | 3489 | #endif |
98cd9ca7 RH |
3490 | } |
3491 | ||
8340f534 | 3492 | static bool trans_bl(DisasContext *ctx, arg_bl *a) |
98cd9ca7 | 3493 | { |
8340f534 | 3494 | return do_dbranch(ctx, iaoq_dest(ctx, a->disp), a->l, a->n); |
98cd9ca7 RH |
3495 | } |
3496 | ||
8340f534 | 3497 | static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) |
43e05652 | 3498 | { |
8340f534 | 3499 | target_ureg dest = iaoq_dest(ctx, a->disp); |
43e05652 | 3500 | |
6e5f5300 SS |
3501 | nullify_over(ctx); |
3502 | ||
43e05652 RH |
3503 | /* Make sure the caller hasn't done something weird with the queue. |
3504 | * ??? This is not quite the same as the PSW[B] bit, which would be | |
3505 | * expensive to track. Real hardware will trap for | |
3506 | * b gateway | |
3507 | * b gateway+4 (in delay slot of first branch) | |
3508 | * However, checking for a non-sequential instruction queue *will* | |
3509 | * diagnose the security hole | |
3510 | * b gateway | |
3511 | * b evil | |
3512 | * in which instructions at evil would run with increased privs. | |
3513 | */ | |
3514 | if (ctx->iaoq_b == -1 || ctx->iaoq_b != ctx->iaoq_f + 4) { | |
3515 | return gen_illegal(ctx); | |
3516 | } | |
3517 | ||
3518 | #ifndef CONFIG_USER_ONLY | |
3519 | if (ctx->tb_flags & PSW_C) { | |
3520 | CPUHPPAState *env = ctx->cs->env_ptr; | |
3521 | int type = hppa_artype_for_page(env, ctx->base.pc_next); | |
3522 | /* If we could not find a TLB entry, then we need to generate an | |
3523 | ITLB miss exception so the kernel will provide it. | |
3524 | The resulting TLB fill operation will invalidate this TB and | |
3525 | we will re-translate, at which point we *will* be able to find | |
3526 | the TLB entry and determine if this is in fact a gateway page. */ | |
3527 | if (type < 0) { | |
31234768 RH |
3528 | gen_excp(ctx, EXCP_ITLB_MISS); |
3529 | return true; | |
43e05652 RH |
3530 | } |
3531 | /* No change for non-gateway pages or for priv decrease. */ | |
3532 | if (type >= 4 && type - 4 < ctx->privilege) { | |
3533 | dest = deposit32(dest, 0, 2, type - 4); | |
3534 | } | |
3535 | } else { | |
3536 | dest &= -4; /* priv = 0 */ | |
3537 | } | |
3538 | #endif | |
3539 | ||
6e5f5300 SS |
3540 | if (a->l) { |
3541 | TCGv_reg tmp = dest_gpr(ctx, a->l); | |
3542 | if (ctx->privilege < 3) { | |
3543 | tcg_gen_andi_reg(tmp, tmp, -4); | |
3544 | } | |
3545 | tcg_gen_ori_reg(tmp, tmp, ctx->privilege); | |
3546 | save_gpr(ctx, a->l, tmp); | |
3547 | } | |
3548 | ||
3549 | return do_dbranch(ctx, dest, 0, a->n); | |
43e05652 RH |
3550 | } |
3551 | ||
8340f534 | 3552 | static bool trans_blr(DisasContext *ctx, arg_blr *a) |
98cd9ca7 | 3553 | { |
b35aec85 RH |
3554 | if (a->x) { |
3555 | TCGv_reg tmp = get_temp(ctx); | |
3556 | tcg_gen_shli_reg(tmp, load_gpr(ctx, a->x), 3); | |
3557 | tcg_gen_addi_reg(tmp, tmp, ctx->iaoq_f + 8); | |
3558 | /* The computation here never changes privilege level. */ | |
3559 | return do_ibranch(ctx, tmp, a->l, a->n); | |
3560 | } else { | |
3561 | /* BLR R0,RX is a good way to load PC+8 into RX. */ | |
3562 | return do_dbranch(ctx, ctx->iaoq_f + 8, a->l, a->n); | |
3563 | } | |
98cd9ca7 RH |
3564 | } |
3565 | ||
8340f534 | 3566 | static bool trans_bv(DisasContext *ctx, arg_bv *a) |
98cd9ca7 | 3567 | { |
eaa3783b | 3568 | TCGv_reg dest; |
98cd9ca7 | 3569 | |
8340f534 RH |
3570 | if (a->x == 0) { |
3571 | dest = load_gpr(ctx, a->b); | |
98cd9ca7 RH |
3572 | } else { |
3573 | dest = get_temp(ctx); | |
8340f534 RH |
3574 | tcg_gen_shli_reg(dest, load_gpr(ctx, a->x), 3); |
3575 | tcg_gen_add_reg(dest, dest, load_gpr(ctx, a->b)); | |
98cd9ca7 | 3576 | } |
660eefe1 | 3577 | dest = do_ibranch_priv(ctx, dest); |
8340f534 | 3578 | return do_ibranch(ctx, dest, 0, a->n); |
98cd9ca7 RH |
3579 | } |
3580 | ||
8340f534 | 3581 | static bool trans_bve(DisasContext *ctx, arg_bve *a) |
98cd9ca7 | 3582 | { |
660eefe1 | 3583 | TCGv_reg dest; |
98cd9ca7 | 3584 | |
c301f34e | 3585 | #ifdef CONFIG_USER_ONLY |
8340f534 RH |
3586 | dest = do_ibranch_priv(ctx, load_gpr(ctx, a->b)); |
3587 | return do_ibranch(ctx, dest, a->l, a->n); | |
c301f34e RH |
3588 | #else |
3589 | nullify_over(ctx); | |
8340f534 | 3590 | dest = do_ibranch_priv(ctx, load_gpr(ctx, a->b)); |
c301f34e RH |
3591 | |
3592 | copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); | |
3593 | if (ctx->iaoq_b == -1) { | |
3594 | tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); | |
3595 | } | |
3596 | copy_iaoq_entry(cpu_iaoq_b, -1, dest); | |
3597 | tcg_gen_mov_i64(cpu_iasq_b, space_select(ctx, 0, dest)); | |
8340f534 RH |
3598 | if (a->l) { |
3599 | copy_iaoq_entry(cpu_gr[a->l], ctx->iaoq_n, ctx->iaoq_n_var); | |
c301f34e | 3600 | } |
8340f534 | 3601 | nullify_set(ctx, a->n); |
c301f34e | 3602 | tcg_gen_lookup_and_goto_ptr(); |
31234768 RH |
3603 | ctx->base.is_jmp = DISAS_NORETURN; |
3604 | return nullify_end(ctx); | |
c301f34e | 3605 | #endif |
98cd9ca7 RH |
3606 | } |
3607 | ||
1ca74648 RH |
3608 | /* |
3609 | * Float class 0 | |
3610 | */ | |
ebe9383c | 3611 | |
1ca74648 | 3612 | static void gen_fcpy_f(TCGv_i32 dst, TCGv_env unused, TCGv_i32 src) |
ebe9383c | 3613 | { |
1ca74648 | 3614 | tcg_gen_mov_i32(dst, src); |
ebe9383c RH |
3615 | } |
3616 | ||
1ca74648 | 3617 | static bool trans_fcpy_f(DisasContext *ctx, arg_fclass01 *a) |
ebe9383c | 3618 | { |
1ca74648 | 3619 | return do_fop_wew(ctx, a->t, a->r, gen_fcpy_f); |
ebe9383c RH |
3620 | } |
3621 | ||
1ca74648 | 3622 | static void gen_fcpy_d(TCGv_i64 dst, TCGv_env unused, TCGv_i64 src) |
ebe9383c | 3623 | { |
1ca74648 | 3624 | tcg_gen_mov_i64(dst, src); |
ebe9383c RH |
3625 | } |
3626 | ||
1ca74648 | 3627 | static bool trans_fcpy_d(DisasContext *ctx, arg_fclass01 *a) |
ebe9383c | 3628 | { |
1ca74648 | 3629 | return do_fop_ded(ctx, a->t, a->r, gen_fcpy_d); |
ebe9383c RH |
3630 | } |
3631 | ||
1ca74648 | 3632 | static void gen_fabs_f(TCGv_i32 dst, TCGv_env unused, TCGv_i32 src) |
ebe9383c | 3633 | { |
1ca74648 | 3634 | tcg_gen_andi_i32(dst, src, INT32_MAX); |
ebe9383c RH |
3635 | } |
3636 | ||
1ca74648 | 3637 | static bool trans_fabs_f(DisasContext *ctx, arg_fclass01 *a) |
ebe9383c | 3638 | { |
1ca74648 | 3639 | return do_fop_wew(ctx, a->t, a->r, gen_fabs_f); |
ebe9383c RH |
3640 | } |
3641 | ||
1ca74648 | 3642 | static void gen_fabs_d(TCGv_i64 dst, TCGv_env unused, TCGv_i64 src) |
ebe9383c | 3643 | { |
1ca74648 | 3644 | tcg_gen_andi_i64(dst, src, INT64_MAX); |
ebe9383c RH |
3645 | } |
3646 | ||
1ca74648 | 3647 | static bool trans_fabs_d(DisasContext *ctx, arg_fclass01 *a) |
ebe9383c | 3648 | { |
1ca74648 | 3649 | return do_fop_ded(ctx, a->t, a->r, gen_fabs_d); |
ebe9383c RH |
3650 | } |
3651 | ||
1ca74648 | 3652 | static bool trans_fsqrt_f(DisasContext *ctx, arg_fclass01 *a) |
ebe9383c | 3653 | { |
1ca74648 | 3654 | return do_fop_wew(ctx, a->t, a->r, gen_helper_fsqrt_s); |
ebe9383c RH |
3655 | } |
3656 | ||
1ca74648 | 3657 | static bool trans_fsqrt_d(DisasContext *ctx, arg_fclass01 *a) |
ebe9383c | 3658 | { |
1ca74648 | 3659 | return do_fop_ded(ctx, a->t, a->r, gen_helper_fsqrt_d); |
ebe9383c RH |
3660 | } |
3661 | ||
1ca74648 | 3662 | static bool trans_frnd_f(DisasContext *ctx, arg_fclass01 *a) |
ebe9383c | 3663 | { |
1ca74648 | 3664 | return do_fop_wew(ctx, a->t, a->r, gen_helper_frnd_s); |
ebe9383c RH |
3665 | } |
3666 | ||
1ca74648 | 3667 | static bool trans_frnd_d(DisasContext *ctx, arg_fclass01 *a) |
ebe9383c | 3668 | { |
1ca74648 | 3669 | return do_fop_ded(ctx, a->t, a->r, gen_helper_frnd_d); |
ebe9383c RH |
3670 | } |
3671 | ||
1ca74648 | 3672 | static void gen_fneg_f(TCGv_i32 dst, TCGv_env unused, TCGv_i32 src) |
ebe9383c | 3673 | { |
1ca74648 | 3674 | tcg_gen_xori_i32(dst, src, INT32_MIN); |
ebe9383c RH |
3675 | } |
3676 | ||
1ca74648 | 3677 | static bool trans_fneg_f(DisasContext *ctx, arg_fclass01 *a) |
ebe9383c | 3678 | { |
1ca74648 | 3679 | return do_fop_wew(ctx, a->t, a->r, gen_fneg_f); |
ebe9383c RH |
3680 | } |
3681 | ||
3682 | static void gen_fneg_d(TCGv_i64 dst, TCGv_env unused, TCGv_i64 src) | |
3683 | { | |
3684 | tcg_gen_xori_i64(dst, src, INT64_MIN); | |
3685 | } | |
3686 | ||
1ca74648 RH |
3687 | static bool trans_fneg_d(DisasContext *ctx, arg_fclass01 *a) |
3688 | { | |
3689 | return do_fop_ded(ctx, a->t, a->r, gen_fneg_d); | |
3690 | } | |
3691 | ||
3692 | static void gen_fnegabs_f(TCGv_i32 dst, TCGv_env unused, TCGv_i32 src) | |
ebe9383c RH |
3693 | { |
3694 | tcg_gen_ori_i32(dst, src, INT32_MIN); | |
3695 | } | |
3696 | ||
1ca74648 RH |
3697 | static bool trans_fnegabs_f(DisasContext *ctx, arg_fclass01 *a) |
3698 | { | |
3699 | return do_fop_wew(ctx, a->t, a->r, gen_fnegabs_f); | |
3700 | } | |
3701 | ||
ebe9383c RH |
3702 | static void gen_fnegabs_d(TCGv_i64 dst, TCGv_env unused, TCGv_i64 src) |
3703 | { | |
3704 | tcg_gen_ori_i64(dst, src, INT64_MIN); | |
3705 | } | |
3706 | ||
1ca74648 RH |
3707 | static bool trans_fnegabs_d(DisasContext *ctx, arg_fclass01 *a) |
3708 | { | |
3709 | return do_fop_ded(ctx, a->t, a->r, gen_fnegabs_d); | |
3710 | } | |
3711 | ||
3712 | /* | |
3713 | * Float class 1 | |
3714 | */ | |
3715 | ||
3716 | static bool trans_fcnv_d_f(DisasContext *ctx, arg_fclass01 *a) | |
3717 | { | |
3718 | return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_d_s); | |
3719 | } | |
3720 | ||
3721 | static bool trans_fcnv_f_d(DisasContext *ctx, arg_fclass01 *a) | |
3722 | { | |
3723 | return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_s_d); | |
3724 | } | |
3725 | ||
3726 | static bool trans_fcnv_w_f(DisasContext *ctx, arg_fclass01 *a) | |
3727 | { | |
3728 | return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_w_s); | |
3729 | } | |
3730 | ||
3731 | static bool trans_fcnv_q_f(DisasContext *ctx, arg_fclass01 *a) | |
3732 | { | |
3733 | return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_dw_s); | |
3734 | } | |
3735 | ||
3736 | static bool trans_fcnv_w_d(DisasContext *ctx, arg_fclass01 *a) | |
3737 | { | |
3738 | return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_w_d); | |
3739 | } | |
3740 | ||
3741 | static bool trans_fcnv_q_d(DisasContext *ctx, arg_fclass01 *a) | |
3742 | { | |
3743 | return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_dw_d); | |
3744 | } | |
3745 | ||
3746 | static bool trans_fcnv_f_w(DisasContext *ctx, arg_fclass01 *a) | |
3747 | { | |
3748 | return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_s_w); | |
3749 | } | |
3750 | ||
3751 | static bool trans_fcnv_d_w(DisasContext *ctx, arg_fclass01 *a) | |
3752 | { | |
3753 | return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_d_w); | |
3754 | } | |
3755 | ||
3756 | static bool trans_fcnv_f_q(DisasContext *ctx, arg_fclass01 *a) | |
3757 | { | |
3758 | return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_s_dw); | |
3759 | } | |
3760 | ||
3761 | static bool trans_fcnv_d_q(DisasContext *ctx, arg_fclass01 *a) | |
3762 | { | |
3763 | return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_d_dw); | |
3764 | } | |
3765 | ||
3766 | static bool trans_fcnv_t_f_w(DisasContext *ctx, arg_fclass01 *a) | |
3767 | { | |
3768 | return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_t_s_w); | |
3769 | } | |
3770 | ||
3771 | static bool trans_fcnv_t_d_w(DisasContext *ctx, arg_fclass01 *a) | |
3772 | { | |
3773 | return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_t_d_w); | |
3774 | } | |
3775 | ||
3776 | static bool trans_fcnv_t_f_q(DisasContext *ctx, arg_fclass01 *a) | |
3777 | { | |
3778 | return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_t_s_dw); | |
3779 | } | |
3780 | ||
3781 | static bool trans_fcnv_t_d_q(DisasContext *ctx, arg_fclass01 *a) | |
3782 | { | |
3783 | return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_t_d_dw); | |
3784 | } | |
3785 | ||
3786 | static bool trans_fcnv_uw_f(DisasContext *ctx, arg_fclass01 *a) | |
3787 | { | |
3788 | return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_uw_s); | |
3789 | } | |
3790 | ||
3791 | static bool trans_fcnv_uq_f(DisasContext *ctx, arg_fclass01 *a) | |
3792 | { | |
3793 | return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_udw_s); | |
3794 | } | |
3795 | ||
3796 | static bool trans_fcnv_uw_d(DisasContext *ctx, arg_fclass01 *a) | |
3797 | { | |
3798 | return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_uw_d); | |
3799 | } | |
3800 | ||
3801 | static bool trans_fcnv_uq_d(DisasContext *ctx, arg_fclass01 *a) | |
3802 | { | |
3803 | return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_udw_d); | |
3804 | } | |
3805 | ||
3806 | static bool trans_fcnv_f_uw(DisasContext *ctx, arg_fclass01 *a) | |
3807 | { | |
3808 | return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_s_uw); | |
3809 | } | |
3810 | ||
3811 | static bool trans_fcnv_d_uw(DisasContext *ctx, arg_fclass01 *a) | |
3812 | { | |
3813 | return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_d_uw); | |
3814 | } | |
3815 | ||
3816 | static bool trans_fcnv_f_uq(DisasContext *ctx, arg_fclass01 *a) | |
3817 | { | |
3818 | return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_s_udw); | |
3819 | } | |
3820 | ||
3821 | static bool trans_fcnv_d_uq(DisasContext *ctx, arg_fclass01 *a) | |
3822 | { | |
3823 | return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_d_udw); | |
3824 | } | |
3825 | ||
3826 | static bool trans_fcnv_t_f_uw(DisasContext *ctx, arg_fclass01 *a) | |
3827 | { | |
3828 | return do_fop_wew(ctx, a->t, a->r, gen_helper_fcnv_t_s_uw); | |
3829 | } | |
3830 | ||
3831 | static bool trans_fcnv_t_d_uw(DisasContext *ctx, arg_fclass01 *a) | |
3832 | { | |
3833 | return do_fop_wed(ctx, a->t, a->r, gen_helper_fcnv_t_d_uw); | |
3834 | } | |
3835 | ||
3836 | static bool trans_fcnv_t_f_uq(DisasContext *ctx, arg_fclass01 *a) | |
3837 | { | |
3838 | return do_fop_dew(ctx, a->t, a->r, gen_helper_fcnv_t_s_udw); | |
3839 | } | |
3840 | ||
3841 | static bool trans_fcnv_t_d_uq(DisasContext *ctx, arg_fclass01 *a) | |
3842 | { | |
3843 | return do_fop_ded(ctx, a->t, a->r, gen_helper_fcnv_t_d_udw); | |
3844 | } | |
3845 | ||
3846 | /* | |
3847 | * Float class 2 | |
3848 | */ | |
3849 | ||
3850 | static bool trans_fcmp_f(DisasContext *ctx, arg_fclass2 *a) | |
ebe9383c RH |
3851 | { |
3852 | TCGv_i32 ta, tb, tc, ty; | |
3853 | ||
3854 | nullify_over(ctx); | |
3855 | ||
1ca74648 RH |
3856 | ta = load_frw0_i32(a->r1); |
3857 | tb = load_frw0_i32(a->r2); | |
29dd6f64 RH |
3858 | ty = tcg_constant_i32(a->y); |
3859 | tc = tcg_constant_i32(a->c); | |
ebe9383c RH |
3860 | |
3861 | gen_helper_fcmp_s(cpu_env, ta, tb, ty, tc); | |
3862 | ||
3863 | tcg_temp_free_i32(ta); | |
3864 | tcg_temp_free_i32(tb); | |
ebe9383c | 3865 | |
1ca74648 | 3866 | return nullify_end(ctx); |
ebe9383c RH |
3867 | } |
3868 | ||
1ca74648 | 3869 | static bool trans_fcmp_d(DisasContext *ctx, arg_fclass2 *a) |
ebe9383c | 3870 | { |
ebe9383c RH |
3871 | TCGv_i64 ta, tb; |
3872 | TCGv_i32 tc, ty; | |
3873 | ||
3874 | nullify_over(ctx); | |
3875 | ||
1ca74648 RH |
3876 | ta = load_frd0(a->r1); |
3877 | tb = load_frd0(a->r2); | |
29dd6f64 RH |
3878 | ty = tcg_constant_i32(a->y); |
3879 | tc = tcg_constant_i32(a->c); | |
ebe9383c RH |
3880 | |
3881 | gen_helper_fcmp_d(cpu_env, ta, tb, ty, tc); | |
3882 | ||
3883 | tcg_temp_free_i64(ta); | |
3884 | tcg_temp_free_i64(tb); | |
ebe9383c | 3885 | |
31234768 | 3886 | return nullify_end(ctx); |
ebe9383c RH |
3887 | } |
3888 | ||
1ca74648 | 3889 | static bool trans_ftest(DisasContext *ctx, arg_ftest *a) |
ebe9383c | 3890 | { |
eaa3783b | 3891 | TCGv_reg t; |
ebe9383c RH |
3892 | |
3893 | nullify_over(ctx); | |
3894 | ||
1ca74648 | 3895 | t = get_temp(ctx); |
eaa3783b | 3896 | tcg_gen_ld32u_reg(t, cpu_env, offsetof(CPUHPPAState, fr0_shadow)); |
ebe9383c | 3897 | |
1ca74648 RH |
3898 | if (a->y == 1) { |
3899 | int mask; | |
3900 | bool inv = false; | |
3901 | ||
3902 | switch (a->c) { | |
3903 | case 0: /* simple */ | |
3904 | tcg_gen_andi_reg(t, t, 0x4000000); | |
3905 | ctx->null_cond = cond_make_0(TCG_COND_NE, t); | |
3906 | goto done; | |
3907 | case 2: /* rej */ | |
3908 | inv = true; | |
3909 | /* fallthru */ | |
3910 | case 1: /* acc */ | |
3911 | mask = 0x43ff800; | |
3912 | break; | |
3913 | case 6: /* rej8 */ | |
3914 | inv = true; | |
3915 | /* fallthru */ | |
3916 | case 5: /* acc8 */ | |
3917 | mask = 0x43f8000; | |
3918 | break; | |
3919 | case 9: /* acc6 */ | |
3920 | mask = 0x43e0000; | |
3921 | break; | |
3922 | case 13: /* acc4 */ | |
3923 | mask = 0x4380000; | |
3924 | break; | |
3925 | case 17: /* acc2 */ | |
3926 | mask = 0x4200000; | |
3927 | break; | |
3928 | default: | |
3929 | gen_illegal(ctx); | |
3930 | return true; | |
3931 | } | |
3932 | if (inv) { | |
3933 | TCGv_reg c = load_const(ctx, mask); | |
3934 | tcg_gen_or_reg(t, t, c); | |
3935 | ctx->null_cond = cond_make(TCG_COND_EQ, t, c); | |
3936 | } else { | |
3937 | tcg_gen_andi_reg(t, t, mask); | |
3938 | ctx->null_cond = cond_make_0(TCG_COND_EQ, t); | |
3939 | } | |
3940 | } else { | |
3941 | unsigned cbit = (a->y ^ 1) - 1; | |
3942 | ||
3943 | tcg_gen_extract_reg(t, t, 21 - cbit, 1); | |
3944 | ctx->null_cond = cond_make_0(TCG_COND_NE, t); | |
3945 | tcg_temp_free(t); | |
3946 | } | |
3947 | ||
3948 | done: | |
31234768 | 3949 | return nullify_end(ctx); |
ebe9383c RH |
3950 | } |
3951 | ||
1ca74648 RH |
3952 | /* |
3953 | * Float class 2 | |
3954 | */ | |
3955 | ||
3956 | static bool trans_fadd_f(DisasContext *ctx, arg_fclass3 *a) | |
ebe9383c | 3957 | { |
1ca74648 RH |
3958 | return do_fop_weww(ctx, a->t, a->r1, a->r2, gen_helper_fadd_s); |
3959 | } | |
ebe9383c | 3960 | |
1ca74648 RH |
3961 | static bool trans_fadd_d(DisasContext *ctx, arg_fclass3 *a) |
3962 | { | |
3963 | return do_fop_dedd(ctx, a->t, a->r1, a->r2, gen_helper_fadd_d); | |
3964 | } | |
ebe9383c | 3965 | |
1ca74648 RH |
3966 | static bool trans_fsub_f(DisasContext *ctx, arg_fclass3 *a) |
3967 | { | |
3968 | return do_fop_weww(ctx, a->t, a->r1, a->r2, gen_helper_fsub_s); | |
3969 | } | |
ebe9383c | 3970 | |
1ca74648 RH |
3971 | static bool trans_fsub_d(DisasContext *ctx, arg_fclass3 *a) |
3972 | { | |
3973 | return do_fop_dedd(ctx, a->t, a->r1, a->r2, gen_helper_fsub_d); | |
ebe9383c RH |
3974 | } |
3975 | ||
1ca74648 | 3976 | static bool trans_fmpy_f(DisasContext *ctx, arg_fclass3 *a) |
ebe9383c | 3977 | { |
1ca74648 RH |
3978 | return do_fop_weww(ctx, a->t, a->r1, a->r2, gen_helper_fmpy_s); |
3979 | } | |
3980 | ||
3981 | static bool trans_fmpy_d(DisasContext *ctx, arg_fclass3 *a) | |
3982 | { | |
3983 | return do_fop_dedd(ctx, a->t, a->r1, a->r2, gen_helper_fmpy_d); | |
3984 | } | |
3985 | ||
3986 | static bool trans_fdiv_f(DisasContext *ctx, arg_fclass3 *a) | |
3987 | { | |
3988 | return do_fop_weww(ctx, a->t, a->r1, a->r2, gen_helper_fdiv_s); | |
3989 | } | |
3990 | ||
3991 | static bool trans_fdiv_d(DisasContext *ctx, arg_fclass3 *a) | |
3992 | { | |
3993 | return do_fop_dedd(ctx, a->t, a->r1, a->r2, gen_helper_fdiv_d); | |
3994 | } | |
3995 | ||
3996 | static bool trans_xmpyu(DisasContext *ctx, arg_xmpyu *a) | |
3997 | { | |
3998 | TCGv_i64 x, y; | |
ebe9383c RH |
3999 | |
4000 | nullify_over(ctx); | |
4001 | ||
1ca74648 RH |
4002 | x = load_frw0_i64(a->r1); |
4003 | y = load_frw0_i64(a->r2); | |
4004 | tcg_gen_mul_i64(x, x, y); | |
4005 | save_frd(a->t, x); | |
4006 | tcg_temp_free_i64(x); | |
4007 | tcg_temp_free_i64(y); | |
ebe9383c | 4008 | |
31234768 | 4009 | return nullify_end(ctx); |
ebe9383c RH |
4010 | } |
4011 | ||
ebe9383c RH |
4012 | /* Convert the fmpyadd single-precision register encodings to standard. */ |
4013 | static inline int fmpyadd_s_reg(unsigned r) | |
4014 | { | |
4015 | return (r & 16) * 2 + 16 + (r & 15); | |
4016 | } | |
4017 | ||
b1e2af57 | 4018 | static bool do_fmpyadd_s(DisasContext *ctx, arg_mpyadd *a, bool is_sub) |
ebe9383c | 4019 | { |
b1e2af57 RH |
4020 | int tm = fmpyadd_s_reg(a->tm); |
4021 | int ra = fmpyadd_s_reg(a->ra); | |
4022 | int ta = fmpyadd_s_reg(a->ta); | |
4023 | int rm2 = fmpyadd_s_reg(a->rm2); | |
4024 | int rm1 = fmpyadd_s_reg(a->rm1); | |
ebe9383c RH |
4025 | |
4026 | nullify_over(ctx); | |
4027 | ||
b1e2af57 RH |
4028 | do_fop_weww(ctx, tm, rm1, rm2, gen_helper_fmpy_s); |
4029 | do_fop_weww(ctx, ta, ta, ra, | |
4030 | is_sub ? gen_helper_fsub_s : gen_helper_fadd_s); | |
ebe9383c | 4031 | |
31234768 | 4032 | return nullify_end(ctx); |
ebe9383c RH |
4033 | } |
4034 | ||
b1e2af57 RH |
4035 | static bool trans_fmpyadd_f(DisasContext *ctx, arg_mpyadd *a) |
4036 | { | |
4037 | return do_fmpyadd_s(ctx, a, false); | |
4038 | } | |
4039 | ||
4040 | static bool trans_fmpysub_f(DisasContext *ctx, arg_mpyadd *a) | |
4041 | { | |
4042 | return do_fmpyadd_s(ctx, a, true); | |
4043 | } | |
4044 | ||
4045 | static bool do_fmpyadd_d(DisasContext *ctx, arg_mpyadd *a, bool is_sub) | |
4046 | { | |
4047 | nullify_over(ctx); | |
4048 | ||
4049 | do_fop_dedd(ctx, a->tm, a->rm1, a->rm2, gen_helper_fmpy_d); | |
4050 | do_fop_dedd(ctx, a->ta, a->ta, a->ra, | |
4051 | is_sub ? gen_helper_fsub_d : gen_helper_fadd_d); | |
4052 | ||
4053 | return nullify_end(ctx); | |
4054 | } | |
4055 | ||
4056 | static bool trans_fmpyadd_d(DisasContext *ctx, arg_mpyadd *a) | |
4057 | { | |
4058 | return do_fmpyadd_d(ctx, a, false); | |
4059 | } | |
4060 | ||
4061 | static bool trans_fmpysub_d(DisasContext *ctx, arg_mpyadd *a) | |
4062 | { | |
4063 | return do_fmpyadd_d(ctx, a, true); | |
4064 | } | |
4065 | ||
c3bad4f8 | 4066 | static bool trans_fmpyfadd_f(DisasContext *ctx, arg_fmpyfadd_f *a) |
ebe9383c | 4067 | { |
c3bad4f8 | 4068 | TCGv_i32 x, y, z; |
ebe9383c RH |
4069 | |
4070 | nullify_over(ctx); | |
c3bad4f8 RH |
4071 | x = load_frw0_i32(a->rm1); |
4072 | y = load_frw0_i32(a->rm2); | |
4073 | z = load_frw0_i32(a->ra3); | |
ebe9383c | 4074 | |
c3bad4f8 RH |
4075 | if (a->neg) { |
4076 | gen_helper_fmpynfadd_s(x, cpu_env, x, y, z); | |
ebe9383c | 4077 | } else { |
c3bad4f8 | 4078 | gen_helper_fmpyfadd_s(x, cpu_env, x, y, z); |
ebe9383c RH |
4079 | } |
4080 | ||
c3bad4f8 RH |
4081 | tcg_temp_free_i32(y); |
4082 | tcg_temp_free_i32(z); | |
4083 | save_frw_i32(a->t, x); | |
4084 | tcg_temp_free_i32(x); | |
31234768 | 4085 | return nullify_end(ctx); |
ebe9383c RH |
4086 | } |
4087 | ||
c3bad4f8 | 4088 | static bool trans_fmpyfadd_d(DisasContext *ctx, arg_fmpyfadd_d *a) |
ebe9383c | 4089 | { |
c3bad4f8 | 4090 | TCGv_i64 x, y, z; |
ebe9383c RH |
4091 | |
4092 | nullify_over(ctx); | |
c3bad4f8 RH |
4093 | x = load_frd0(a->rm1); |
4094 | y = load_frd0(a->rm2); | |
4095 | z = load_frd0(a->ra3); | |
ebe9383c | 4096 | |
c3bad4f8 RH |
4097 | if (a->neg) { |
4098 | gen_helper_fmpynfadd_d(x, cpu_env, x, y, z); | |
ebe9383c | 4099 | } else { |
c3bad4f8 | 4100 | gen_helper_fmpyfadd_d(x, cpu_env, x, y, z); |
ebe9383c RH |
4101 | } |
4102 | ||
c3bad4f8 RH |
4103 | tcg_temp_free_i64(y); |
4104 | tcg_temp_free_i64(z); | |
4105 | save_frd(a->t, x); | |
4106 | tcg_temp_free_i64(x); | |
31234768 | 4107 | return nullify_end(ctx); |
ebe9383c RH |
4108 | } |
4109 | ||
15da177b SS |
4110 | static bool trans_diag(DisasContext *ctx, arg_diag *a) |
4111 | { | |
4112 | qemu_log_mask(LOG_UNIMP, "DIAG opcode ignored\n"); | |
4113 | cond_free(&ctx->null_cond); | |
4114 | return true; | |
4115 | } | |
4116 | ||
b542683d | 4117 | static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) |
61766fe9 | 4118 | { |
51b061fb | 4119 | DisasContext *ctx = container_of(dcbase, DisasContext, base); |
f764718d | 4120 | int bound; |
61766fe9 | 4121 | |
51b061fb | 4122 | ctx->cs = cs; |
494737b7 | 4123 | ctx->tb_flags = ctx->base.tb->flags; |
3d68ee7b RH |
4124 | |
4125 | #ifdef CONFIG_USER_ONLY | |
4126 | ctx->privilege = MMU_USER_IDX; | |
4127 | ctx->mmu_idx = MMU_USER_IDX; | |
ebd0e151 RH |
4128 | ctx->iaoq_f = ctx->base.pc_first | MMU_USER_IDX; |
4129 | ctx->iaoq_b = ctx->base.tb->cs_base | MMU_USER_IDX; | |
217d1a5e | 4130 | ctx->unalign = (ctx->tb_flags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN); |
3d68ee7b | 4131 | #else |
494737b7 RH |
4132 | ctx->privilege = (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3; |
4133 | ctx->mmu_idx = (ctx->tb_flags & PSW_D ? ctx->privilege : MMU_PHYS_IDX); | |
3d68ee7b | 4134 | |
c301f34e RH |
4135 | /* Recover the IAOQ values from the GVA + PRIV. */ |
4136 | uint64_t cs_base = ctx->base.tb->cs_base; | |
4137 | uint64_t iasq_f = cs_base & ~0xffffffffull; | |
4138 | int32_t diff = cs_base; | |
4139 | ||
4140 | ctx->iaoq_f = (ctx->base.pc_first & ~iasq_f) + ctx->privilege; | |
4141 | ctx->iaoq_b = (diff ? ctx->iaoq_f + diff : -1); | |
4142 | #endif | |
51b061fb | 4143 | ctx->iaoq_n = -1; |
f764718d | 4144 | ctx->iaoq_n_var = NULL; |
61766fe9 | 4145 | |
3d68ee7b RH |
4146 | /* Bound the number of instructions by those left on the page. */ |
4147 | bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; | |
b542683d | 4148 | ctx->base.max_insns = MIN(ctx->base.max_insns, bound); |
3d68ee7b | 4149 | |
86f8d05f RH |
4150 | ctx->ntempr = 0; |
4151 | ctx->ntempl = 0; | |
4152 | memset(ctx->tempr, 0, sizeof(ctx->tempr)); | |
4153 | memset(ctx->templ, 0, sizeof(ctx->templ)); | |
51b061fb | 4154 | } |
61766fe9 | 4155 | |
51b061fb RH |
4156 | static void hppa_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) |
4157 | { | |
4158 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
61766fe9 | 4159 | |
3d68ee7b | 4160 | /* Seed the nullification status from PSW[N], as saved in TB->FLAGS. */ |
51b061fb RH |
4161 | ctx->null_cond = cond_make_f(); |
4162 | ctx->psw_n_nonzero = false; | |
494737b7 | 4163 | if (ctx->tb_flags & PSW_N) { |
51b061fb RH |
4164 | ctx->null_cond.c = TCG_COND_ALWAYS; |
4165 | ctx->psw_n_nonzero = true; | |
129e9cc3 | 4166 | } |
51b061fb RH |
4167 | ctx->null_lab = NULL; |
4168 | } | |
129e9cc3 | 4169 | |
51b061fb RH |
4170 | static void hppa_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) |
4171 | { | |
4172 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
61766fe9 | 4173 | |
51b061fb RH |
4174 | tcg_gen_insn_start(ctx->iaoq_f, ctx->iaoq_b); |
4175 | } | |
4176 | ||
51b061fb RH |
4177 | static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) |
4178 | { | |
4179 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
4180 | CPUHPPAState *env = cs->env_ptr; | |
4181 | DisasJumpType ret; | |
4182 | int i, n; | |
4183 | ||
4184 | /* Execute one insn. */ | |
ba1d0b44 | 4185 | #ifdef CONFIG_USER_ONLY |
c301f34e | 4186 | if (ctx->base.pc_next < TARGET_PAGE_SIZE) { |
31234768 RH |
4187 | do_page_zero(ctx); |
4188 | ret = ctx->base.is_jmp; | |
51b061fb | 4189 | assert(ret != DISAS_NEXT); |
ba1d0b44 RH |
4190 | } else |
4191 | #endif | |
4192 | { | |
51b061fb RH |
4193 | /* Always fetch the insn, even if nullified, so that we check |
4194 | the page permissions for execute. */ | |
4e116893 | 4195 | uint32_t insn = translator_ldl(env, &ctx->base, ctx->base.pc_next); |
51b061fb RH |
4196 | |
4197 | /* Set up the IA queue for the next insn. | |
4198 | This will be overwritten by a branch. */ | |
4199 | if (ctx->iaoq_b == -1) { | |
4200 | ctx->iaoq_n = -1; | |
4201 | ctx->iaoq_n_var = get_temp(ctx); | |
eaa3783b | 4202 | tcg_gen_addi_reg(ctx->iaoq_n_var, cpu_iaoq_b, 4); |
7ad439df | 4203 | } else { |
51b061fb | 4204 | ctx->iaoq_n = ctx->iaoq_b + 4; |
f764718d | 4205 | ctx->iaoq_n_var = NULL; |
61766fe9 RH |
4206 | } |
4207 | ||
51b061fb RH |
4208 | if (unlikely(ctx->null_cond.c == TCG_COND_ALWAYS)) { |
4209 | ctx->null_cond.c = TCG_COND_NEVER; | |
4210 | ret = DISAS_NEXT; | |
4211 | } else { | |
1a19da0d | 4212 | ctx->insn = insn; |
31274b46 RH |
4213 | if (!decode(ctx, insn)) { |
4214 | gen_illegal(ctx); | |
4215 | } | |
31234768 | 4216 | ret = ctx->base.is_jmp; |
51b061fb | 4217 | assert(ctx->null_lab == NULL); |
61766fe9 | 4218 | } |
51b061fb | 4219 | } |
61766fe9 | 4220 | |
51b061fb | 4221 | /* Free any temporaries allocated. */ |
86f8d05f RH |
4222 | for (i = 0, n = ctx->ntempr; i < n; ++i) { |
4223 | tcg_temp_free(ctx->tempr[i]); | |
4224 | ctx->tempr[i] = NULL; | |
4225 | } | |
4226 | for (i = 0, n = ctx->ntempl; i < n; ++i) { | |
4227 | tcg_temp_free_tl(ctx->templ[i]); | |
4228 | ctx->templ[i] = NULL; | |
51b061fb | 4229 | } |
86f8d05f RH |
4230 | ctx->ntempr = 0; |
4231 | ctx->ntempl = 0; | |
61766fe9 | 4232 | |
3d68ee7b RH |
4233 | /* Advance the insn queue. Note that this check also detects |
4234 | a priority change within the instruction queue. */ | |
51b061fb | 4235 | if (ret == DISAS_NEXT && ctx->iaoq_b != ctx->iaoq_f + 4) { |
c301f34e RH |
4236 | if (ctx->iaoq_b != -1 && ctx->iaoq_n != -1 |
4237 | && use_goto_tb(ctx, ctx->iaoq_b) | |
4238 | && (ctx->null_cond.c == TCG_COND_NEVER | |
4239 | || ctx->null_cond.c == TCG_COND_ALWAYS)) { | |
51b061fb RH |
4240 | nullify_set(ctx, ctx->null_cond.c == TCG_COND_ALWAYS); |
4241 | gen_goto_tb(ctx, 0, ctx->iaoq_b, ctx->iaoq_n); | |
31234768 | 4242 | ctx->base.is_jmp = ret = DISAS_NORETURN; |
51b061fb | 4243 | } else { |
31234768 | 4244 | ctx->base.is_jmp = ret = DISAS_IAQ_N_STALE; |
c301f34e | 4245 | } |
61766fe9 | 4246 | } |
51b061fb RH |
4247 | ctx->iaoq_f = ctx->iaoq_b; |
4248 | ctx->iaoq_b = ctx->iaoq_n; | |
c301f34e | 4249 | ctx->base.pc_next += 4; |
51b061fb | 4250 | |
c5d0aec2 RH |
4251 | switch (ret) { |
4252 | case DISAS_NORETURN: | |
4253 | case DISAS_IAQ_N_UPDATED: | |
4254 | break; | |
4255 | ||
4256 | case DISAS_NEXT: | |
4257 | case DISAS_IAQ_N_STALE: | |
4258 | case DISAS_IAQ_N_STALE_EXIT: | |
4259 | if (ctx->iaoq_f == -1) { | |
4260 | tcg_gen_mov_reg(cpu_iaoq_f, cpu_iaoq_b); | |
4261 | copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var); | |
c301f34e | 4262 | #ifndef CONFIG_USER_ONLY |
c5d0aec2 | 4263 | tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); |
c301f34e | 4264 | #endif |
c5d0aec2 RH |
4265 | nullify_save(ctx); |
4266 | ctx->base.is_jmp = (ret == DISAS_IAQ_N_STALE_EXIT | |
4267 | ? DISAS_EXIT | |
4268 | : DISAS_IAQ_N_UPDATED); | |
4269 | } else if (ctx->iaoq_b == -1) { | |
4270 | tcg_gen_mov_reg(cpu_iaoq_b, ctx->iaoq_n_var); | |
4271 | } | |
4272 | break; | |
4273 | ||
4274 | default: | |
4275 | g_assert_not_reached(); | |
51b061fb RH |
4276 | } |
4277 | } | |
4278 | ||
4279 | static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) | |
4280 | { | |
4281 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
e1b5a5ed | 4282 | DisasJumpType is_jmp = ctx->base.is_jmp; |
61766fe9 | 4283 | |
e1b5a5ed | 4284 | switch (is_jmp) { |
869051ea | 4285 | case DISAS_NORETURN: |
61766fe9 | 4286 | break; |
51b061fb | 4287 | case DISAS_TOO_MANY: |
869051ea | 4288 | case DISAS_IAQ_N_STALE: |
e1b5a5ed | 4289 | case DISAS_IAQ_N_STALE_EXIT: |
51b061fb RH |
4290 | copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_f, cpu_iaoq_f); |
4291 | copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_b, cpu_iaoq_b); | |
4292 | nullify_save(ctx); | |
61766fe9 | 4293 | /* FALLTHRU */ |
869051ea | 4294 | case DISAS_IAQ_N_UPDATED: |
8532a14e | 4295 | if (is_jmp != DISAS_IAQ_N_STALE_EXIT) { |
7f11636d | 4296 | tcg_gen_lookup_and_goto_ptr(); |
8532a14e | 4297 | break; |
61766fe9 | 4298 | } |
c5d0aec2 RH |
4299 | /* FALLTHRU */ |
4300 | case DISAS_EXIT: | |
4301 | tcg_gen_exit_tb(NULL, 0); | |
61766fe9 RH |
4302 | break; |
4303 | default: | |
51b061fb | 4304 | g_assert_not_reached(); |
61766fe9 | 4305 | } |
51b061fb | 4306 | } |
61766fe9 | 4307 | |
8eb806a7 RH |
4308 | static void hppa_tr_disas_log(const DisasContextBase *dcbase, |
4309 | CPUState *cs, FILE *logfile) | |
51b061fb | 4310 | { |
c301f34e | 4311 | target_ulong pc = dcbase->pc_first; |
61766fe9 | 4312 | |
ba1d0b44 RH |
4313 | #ifdef CONFIG_USER_ONLY |
4314 | switch (pc) { | |
51b061fb | 4315 | case 0x00: |
8eb806a7 | 4316 | fprintf(logfile, "IN:\n0x00000000: (null)\n"); |
ba1d0b44 | 4317 | return; |
51b061fb | 4318 | case 0xb0: |
8eb806a7 | 4319 | fprintf(logfile, "IN:\n0x000000b0: light-weight-syscall\n"); |
ba1d0b44 | 4320 | return; |
51b061fb | 4321 | case 0xe0: |
8eb806a7 | 4322 | fprintf(logfile, "IN:\n0x000000e0: set-thread-pointer-syscall\n"); |
ba1d0b44 | 4323 | return; |
51b061fb | 4324 | case 0x100: |
8eb806a7 | 4325 | fprintf(logfile, "IN:\n0x00000100: syscall\n"); |
ba1d0b44 | 4326 | return; |
61766fe9 | 4327 | } |
ba1d0b44 RH |
4328 | #endif |
4329 | ||
8eb806a7 RH |
4330 | fprintf(logfile, "IN: %s\n", lookup_symbol(pc)); |
4331 | target_disas(logfile, cs, pc, dcbase->tb->size); | |
51b061fb RH |
4332 | } |
4333 | ||
4334 | static const TranslatorOps hppa_tr_ops = { | |
4335 | .init_disas_context = hppa_tr_init_disas_context, | |
4336 | .tb_start = hppa_tr_tb_start, | |
4337 | .insn_start = hppa_tr_insn_start, | |
51b061fb RH |
4338 | .translate_insn = hppa_tr_translate_insn, |
4339 | .tb_stop = hppa_tr_tb_stop, | |
4340 | .disas_log = hppa_tr_disas_log, | |
4341 | }; | |
4342 | ||
306c8721 RH |
4343 | void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns, |
4344 | target_ulong pc, void *host_pc) | |
51b061fb RH |
4345 | { |
4346 | DisasContext ctx; | |
306c8721 | 4347 | translator_loop(cs, tb, max_insns, pc, host_pc, &hppa_tr_ops, &ctx.base); |
61766fe9 | 4348 | } |