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2c0262af FB |
1 | /* |
2 | * i386 virtual CPU header | |
5fafdf24 | 3 | * |
2c0262af FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
d9ff33ad | 9 | * version 2.1 of the License, or (at your option) any later version. |
2c0262af FB |
10 | * |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
2c0262af | 18 | */ |
07f5a258 MA |
19 | |
20 | #ifndef I386_CPU_H | |
21 | #define I386_CPU_H | |
2c0262af | 22 | |
14a48c1d | 23 | #include "sysemu/tcg.h" |
4da6f8d9 | 24 | #include "cpu-qom.h" |
a9dc68d9 | 25 | #include "kvm/hyperv-proto.h" |
c97d6d2c | 26 | #include "exec/cpu-defs.h" |
30d6ff66 | 27 | #include "qapi/qapi-types-common.h" |
c97d6d2c | 28 | |
72c1701f AB |
29 | /* The x86 has a strong memory model with some store-after-load re-ordering */ |
30 | #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) | |
31 | ||
e24fd076 DG |
32 | #define KVM_HAVE_MCE_INJECTION 1 |
33 | ||
d720b93d FB |
34 | /* support for self modifying code even if the modified instruction is |
35 | close to the modifying instruction */ | |
36 | #define TARGET_HAS_PRECISE_SMC | |
37 | ||
9042c0e2 | 38 | #ifdef TARGET_X86_64 |
a5e8788f | 39 | #define I386_ELF_MACHINE EM_X86_64 |
4ab23a91 | 40 | #define ELF_MACHINE_UNAME "x86_64" |
9042c0e2 | 41 | #else |
a5e8788f | 42 | #define I386_ELF_MACHINE EM_386 |
4ab23a91 | 43 | #define ELF_MACHINE_UNAME "i686" |
9042c0e2 TS |
44 | #endif |
45 | ||
6701d81d PB |
46 | enum { |
47 | R_EAX = 0, | |
48 | R_ECX = 1, | |
49 | R_EDX = 2, | |
50 | R_EBX = 3, | |
51 | R_ESP = 4, | |
52 | R_EBP = 5, | |
53 | R_ESI = 6, | |
54 | R_EDI = 7, | |
55 | R_R8 = 8, | |
56 | R_R9 = 9, | |
57 | R_R10 = 10, | |
58 | R_R11 = 11, | |
59 | R_R12 = 12, | |
60 | R_R13 = 13, | |
61 | R_R14 = 14, | |
62 | R_R15 = 15, | |
2c0262af | 63 | |
6701d81d PB |
64 | R_AL = 0, |
65 | R_CL = 1, | |
66 | R_DL = 2, | |
67 | R_BL = 3, | |
68 | R_AH = 4, | |
69 | R_CH = 5, | |
70 | R_DH = 6, | |
71 | R_BH = 7, | |
72 | }; | |
2c0262af | 73 | |
6701d81d PB |
74 | typedef enum X86Seg { |
75 | R_ES = 0, | |
76 | R_CS = 1, | |
77 | R_SS = 2, | |
78 | R_DS = 3, | |
79 | R_FS = 4, | |
80 | R_GS = 5, | |
81 | R_LDTR = 6, | |
82 | R_TR = 7, | |
83 | } X86Seg; | |
2c0262af FB |
84 | |
85 | /* segment descriptor fields */ | |
c97d6d2c SAGDR |
86 | #define DESC_G_SHIFT 23 |
87 | #define DESC_G_MASK (1 << DESC_G_SHIFT) | |
2c0262af FB |
88 | #define DESC_B_SHIFT 22 |
89 | #define DESC_B_MASK (1 << DESC_B_SHIFT) | |
14ce26e7 FB |
90 | #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ |
91 | #define DESC_L_MASK (1 << DESC_L_SHIFT) | |
c97d6d2c SAGDR |
92 | #define DESC_AVL_SHIFT 20 |
93 | #define DESC_AVL_MASK (1 << DESC_AVL_SHIFT) | |
94 | #define DESC_P_SHIFT 15 | |
95 | #define DESC_P_MASK (1 << DESC_P_SHIFT) | |
2c0262af | 96 | #define DESC_DPL_SHIFT 13 |
a3867ed2 | 97 | #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT) |
c97d6d2c SAGDR |
98 | #define DESC_S_SHIFT 12 |
99 | #define DESC_S_MASK (1 << DESC_S_SHIFT) | |
2c0262af | 100 | #define DESC_TYPE_SHIFT 8 |
a3867ed2 | 101 | #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT) |
2c0262af FB |
102 | #define DESC_A_MASK (1 << 8) |
103 | ||
e670b89e FB |
104 | #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ |
105 | #define DESC_C_MASK (1 << 10) /* code: conforming */ | |
106 | #define DESC_R_MASK (1 << 9) /* code: readable */ | |
2c0262af | 107 | |
e670b89e FB |
108 | #define DESC_E_MASK (1 << 10) /* data: expansion direction */ |
109 | #define DESC_W_MASK (1 << 9) /* data: writable */ | |
110 | ||
111 | #define DESC_TSS_BUSY_MASK (1 << 9) | |
2c0262af FB |
112 | |
113 | /* eflags masks */ | |
e4a09c96 PB |
114 | #define CC_C 0x0001 |
115 | #define CC_P 0x0004 | |
116 | #define CC_A 0x0010 | |
117 | #define CC_Z 0x0040 | |
2c0262af FB |
118 | #define CC_S 0x0080 |
119 | #define CC_O 0x0800 | |
120 | ||
121 | #define TF_SHIFT 8 | |
122 | #define IOPL_SHIFT 12 | |
123 | #define VM_SHIFT 17 | |
124 | ||
e4a09c96 PB |
125 | #define TF_MASK 0x00000100 |
126 | #define IF_MASK 0x00000200 | |
127 | #define DF_MASK 0x00000400 | |
128 | #define IOPL_MASK 0x00003000 | |
129 | #define NT_MASK 0x00004000 | |
130 | #define RF_MASK 0x00010000 | |
131 | #define VM_MASK 0x00020000 | |
132 | #define AC_MASK 0x00040000 | |
2c0262af FB |
133 | #define VIF_MASK 0x00080000 |
134 | #define VIP_MASK 0x00100000 | |
135 | #define ID_MASK 0x00200000 | |
136 | ||
aa1f17c1 | 137 | /* hidden flags - used internally by qemu to represent additional cpu |
7848c8d1 KC |
138 | states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We |
139 | avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit | |
140 | positions to ease oring with eflags. */ | |
2c0262af FB |
141 | /* current cpl */ |
142 | #define HF_CPL_SHIFT 0 | |
2c0262af FB |
143 | /* true if hardware interrupts must be disabled for next instruction */ |
144 | #define HF_INHIBIT_IRQ_SHIFT 3 | |
145 | /* 16 or 32 segments */ | |
146 | #define HF_CS32_SHIFT 4 | |
147 | #define HF_SS32_SHIFT 5 | |
dc196a57 | 148 | /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */ |
2c0262af | 149 | #define HF_ADDSEG_SHIFT 6 |
65262d57 FB |
150 | /* copy of CR0.PE (protected mode) */ |
151 | #define HF_PE_SHIFT 7 | |
152 | #define HF_TF_SHIFT 8 /* must be same as eflags */ | |
7eee2a50 FB |
153 | #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ |
154 | #define HF_EM_SHIFT 10 | |
155 | #define HF_TS_SHIFT 11 | |
65262d57 | 156 | #define HF_IOPL_SHIFT 12 /* must be same as eflags */ |
14ce26e7 FB |
157 | #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ |
158 | #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ | |
a2397807 | 159 | #define HF_RF_SHIFT 16 /* must be same as eflags */ |
65262d57 | 160 | #define HF_VM_SHIFT 17 /* must be same as eflags */ |
a9321a4d | 161 | #define HF_AC_SHIFT 18 /* must be same as eflags */ |
3b21e03e | 162 | #define HF_SMM_SHIFT 19 /* CPU in SMM mode */ |
db620f46 | 163 | #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */ |
f8dc4c64 | 164 | #define HF_GUEST_SHIFT 21 /* SVM intercepts are active */ |
a2397807 | 165 | #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */ |
a9321a4d | 166 | #define HF_SMAP_SHIFT 23 /* CR4.SMAP */ |
5223a942 | 167 | #define HF_IOBPT_SHIFT 24 /* an io breakpoint enabled */ |
f4f1110e RH |
168 | #define HF_MPX_EN_SHIFT 25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */ |
169 | #define HF_MPX_IU_SHIFT 26 /* BND registers in-use */ | |
2c0262af FB |
170 | |
171 | #define HF_CPL_MASK (3 << HF_CPL_SHIFT) | |
2c0262af FB |
172 | #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) |
173 | #define HF_CS32_MASK (1 << HF_CS32_SHIFT) | |
174 | #define HF_SS32_MASK (1 << HF_SS32_SHIFT) | |
175 | #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) | |
65262d57 | 176 | #define HF_PE_MASK (1 << HF_PE_SHIFT) |
58fe2f10 | 177 | #define HF_TF_MASK (1 << HF_TF_SHIFT) |
7eee2a50 FB |
178 | #define HF_MP_MASK (1 << HF_MP_SHIFT) |
179 | #define HF_EM_MASK (1 << HF_EM_SHIFT) | |
180 | #define HF_TS_MASK (1 << HF_TS_SHIFT) | |
0650f1ab | 181 | #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT) |
14ce26e7 FB |
182 | #define HF_LMA_MASK (1 << HF_LMA_SHIFT) |
183 | #define HF_CS64_MASK (1 << HF_CS64_SHIFT) | |
a2397807 | 184 | #define HF_RF_MASK (1 << HF_RF_SHIFT) |
0650f1ab | 185 | #define HF_VM_MASK (1 << HF_VM_SHIFT) |
a9321a4d | 186 | #define HF_AC_MASK (1 << HF_AC_SHIFT) |
3b21e03e | 187 | #define HF_SMM_MASK (1 << HF_SMM_SHIFT) |
872929aa | 188 | #define HF_SVME_MASK (1 << HF_SVME_SHIFT) |
f8dc4c64 | 189 | #define HF_GUEST_MASK (1 << HF_GUEST_SHIFT) |
a2397807 | 190 | #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) |
a9321a4d | 191 | #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT) |
5223a942 | 192 | #define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT) |
f4f1110e RH |
193 | #define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT) |
194 | #define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT) | |
2c0262af | 195 | |
db620f46 FB |
196 | /* hflags2 */ |
197 | ||
9982f74b PB |
198 | #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */ |
199 | #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */ | |
200 | #define HF2_NMI_SHIFT 2 /* CPU serving NMI */ | |
201 | #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */ | |
202 | #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */ | |
f4f1110e | 203 | #define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */ |
fe441054 | 204 | #define HF2_NPT_SHIFT 6 /* Nested Paging enabled */ |
bf13bfab | 205 | #define HF2_IGNNE_SHIFT 7 /* Ignore CR0.NE=0 */ |
9982f74b PB |
206 | |
207 | #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT) | |
208 | #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT) | |
209 | #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT) | |
210 | #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT) | |
211 | #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT) | |
f4f1110e | 212 | #define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT) |
fe441054 | 213 | #define HF2_NPT_MASK (1 << HF2_NPT_SHIFT) |
bf13bfab | 214 | #define HF2_IGNNE_MASK (1 << HF2_IGNNE_SHIFT) |
db620f46 | 215 | |
0650f1ab AL |
216 | #define CR0_PE_SHIFT 0 |
217 | #define CR0_MP_SHIFT 1 | |
218 | ||
2cd49cbf PM |
219 | #define CR0_PE_MASK (1U << 0) |
220 | #define CR0_MP_MASK (1U << 1) | |
221 | #define CR0_EM_MASK (1U << 2) | |
222 | #define CR0_TS_MASK (1U << 3) | |
223 | #define CR0_ET_MASK (1U << 4) | |
224 | #define CR0_NE_MASK (1U << 5) | |
225 | #define CR0_WP_MASK (1U << 16) | |
226 | #define CR0_AM_MASK (1U << 18) | |
227 | #define CR0_PG_MASK (1U << 31) | |
228 | ||
229 | #define CR4_VME_MASK (1U << 0) | |
230 | #define CR4_PVI_MASK (1U << 1) | |
231 | #define CR4_TSD_MASK (1U << 2) | |
232 | #define CR4_DE_MASK (1U << 3) | |
233 | #define CR4_PSE_MASK (1U << 4) | |
234 | #define CR4_PAE_MASK (1U << 5) | |
235 | #define CR4_MCE_MASK (1U << 6) | |
236 | #define CR4_PGE_MASK (1U << 7) | |
237 | #define CR4_PCE_MASK (1U << 8) | |
0650f1ab | 238 | #define CR4_OSFXSR_SHIFT 9 |
2cd49cbf PM |
239 | #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT) |
240 | #define CR4_OSXMMEXCPT_MASK (1U << 10) | |
6c7c3c21 | 241 | #define CR4_LA57_MASK (1U << 12) |
2cd49cbf PM |
242 | #define CR4_VMXE_MASK (1U << 13) |
243 | #define CR4_SMXE_MASK (1U << 14) | |
244 | #define CR4_FSGSBASE_MASK (1U << 16) | |
245 | #define CR4_PCIDE_MASK (1U << 17) | |
246 | #define CR4_OSXSAVE_MASK (1U << 18) | |
247 | #define CR4_SMEP_MASK (1U << 20) | |
248 | #define CR4_SMAP_MASK (1U << 21) | |
0f70ed47 | 249 | #define CR4_PKE_MASK (1U << 22) |
e7e7bdab | 250 | #define CR4_PKS_MASK (1U << 24) |
2c0262af | 251 | |
01df040b AL |
252 | #define DR6_BD (1 << 13) |
253 | #define DR6_BS (1 << 14) | |
254 | #define DR6_BT (1 << 15) | |
255 | #define DR6_FIXED_1 0xffff0ff0 | |
256 | ||
257 | #define DR7_GD (1 << 13) | |
258 | #define DR7_TYPE_SHIFT 16 | |
259 | #define DR7_LEN_SHIFT 18 | |
260 | #define DR7_FIXED_1 0x00000400 | |
93d00d0f | 261 | #define DR7_GLOBAL_BP_MASK 0xaa |
428065ce LG |
262 | #define DR7_LOCAL_BP_MASK 0x55 |
263 | #define DR7_MAX_BP 4 | |
264 | #define DR7_TYPE_BP_INST 0x0 | |
265 | #define DR7_TYPE_DATA_WR 0x1 | |
266 | #define DR7_TYPE_IO_RW 0x2 | |
267 | #define DR7_TYPE_DATA_RW 0x3 | |
01df040b | 268 | |
e4a09c96 PB |
269 | #define PG_PRESENT_BIT 0 |
270 | #define PG_RW_BIT 1 | |
271 | #define PG_USER_BIT 2 | |
272 | #define PG_PWT_BIT 3 | |
273 | #define PG_PCD_BIT 4 | |
274 | #define PG_ACCESSED_BIT 5 | |
275 | #define PG_DIRTY_BIT 6 | |
276 | #define PG_PSE_BIT 7 | |
277 | #define PG_GLOBAL_BIT 8 | |
eaad03e4 | 278 | #define PG_PSE_PAT_BIT 12 |
0f70ed47 | 279 | #define PG_PKRU_BIT 59 |
e4a09c96 | 280 | #define PG_NX_BIT 63 |
2c0262af FB |
281 | |
282 | #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) | |
e4a09c96 PB |
283 | #define PG_RW_MASK (1 << PG_RW_BIT) |
284 | #define PG_USER_MASK (1 << PG_USER_BIT) | |
285 | #define PG_PWT_MASK (1 << PG_PWT_BIT) | |
286 | #define PG_PCD_MASK (1 << PG_PCD_BIT) | |
2c0262af | 287 | #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) |
e4a09c96 PB |
288 | #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) |
289 | #define PG_PSE_MASK (1 << PG_PSE_BIT) | |
290 | #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) | |
eaad03e4 | 291 | #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT) |
e8f6d00c PB |
292 | #define PG_ADDRESS_MASK 0x000ffffffffff000LL |
293 | #define PG_HI_RSVD_MASK (PG_ADDRESS_MASK & ~PHYS_ADDR_MASK) | |
3f2cbf0d | 294 | #define PG_HI_USER_MASK 0x7ff0000000000000LL |
0f70ed47 PB |
295 | #define PG_PKRU_MASK (15ULL << PG_PKRU_BIT) |
296 | #define PG_NX_MASK (1ULL << PG_NX_BIT) | |
2c0262af FB |
297 | |
298 | #define PG_ERROR_W_BIT 1 | |
299 | ||
300 | #define PG_ERROR_P_MASK 0x01 | |
301 | #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) | |
302 | #define PG_ERROR_U_MASK 0x04 | |
303 | #define PG_ERROR_RSVD_MASK 0x08 | |
5cf38396 | 304 | #define PG_ERROR_I_D_MASK 0x10 |
0f70ed47 | 305 | #define PG_ERROR_PK_MASK 0x20 |
2c0262af | 306 | |
e4a09c96 PB |
307 | #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */ |
308 | #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ | |
87f8b626 | 309 | #define MCG_LMCE_P (1ULL<<27) /* Local Machine Check Supported */ |
79c4f6b0 | 310 | |
e4a09c96 PB |
311 | #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P) |
312 | #define MCE_BANKS_DEF 10 | |
79c4f6b0 | 313 | |
2590f15b EH |
314 | #define MCG_CAP_BANKS_MASK 0xff |
315 | ||
e4a09c96 PB |
316 | #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ |
317 | #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ | |
318 | #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ | |
87f8b626 AR |
319 | #define MCG_STATUS_LMCE (1ULL<<3) /* Local MCE signaled */ |
320 | ||
321 | #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */ | |
79c4f6b0 | 322 | |
e4a09c96 PB |
323 | #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ |
324 | #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ | |
325 | #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ | |
326 | #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ | |
327 | #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ | |
328 | #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ | |
329 | #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ | |
330 | #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ | |
331 | #define MCI_STATUS_AR (1ULL<<55) /* Action required */ | |
c0532a76 MT |
332 | |
333 | /* MISC register defines */ | |
e4a09c96 PB |
334 | #define MCM_ADDR_SEGOFF 0 /* segment offset */ |
335 | #define MCM_ADDR_LINEAR 1 /* linear address */ | |
336 | #define MCM_ADDR_PHYS 2 /* physical address */ | |
337 | #define MCM_ADDR_MEM 3 /* memory address */ | |
338 | #define MCM_ADDR_GENERIC 7 /* generic */ | |
79c4f6b0 | 339 | |
0650f1ab | 340 | #define MSR_IA32_TSC 0x10 |
2c0262af FB |
341 | #define MSR_IA32_APICBASE 0x1b |
342 | #define MSR_IA32_APICBASE_BSP (1<<8) | |
343 | #define MSR_IA32_APICBASE_ENABLE (1<<11) | |
33d7a288 | 344 | #define MSR_IA32_APICBASE_EXTD (1 << 10) |
458cf469 | 345 | #define MSR_IA32_APICBASE_BASE (0xfffffU<<12) |
0779caeb | 346 | #define MSR_IA32_FEATURE_CONTROL 0x0000003a |
f28558d3 | 347 | #define MSR_TSC_ADJUST 0x0000003b |
a33a2cfe | 348 | #define MSR_IA32_SPEC_CTRL 0x48 |
cfeea0c0 | 349 | #define MSR_VIRT_SSBD 0xc001011f |
8c80c99f | 350 | #define MSR_IA32_PRED_CMD 0x49 |
4e45aff3 | 351 | #define MSR_IA32_UCODE_REV 0x8b |
597360c0 | 352 | #define MSR_IA32_CORE_CAPABILITY 0xcf |
2a9758c5 | 353 | |
8c80c99f | 354 | #define MSR_IA32_ARCH_CAPABILITIES 0x10a |
2a9758c5 PB |
355 | #define ARCH_CAP_TSX_CTRL_MSR (1<<7) |
356 | ||
ea39f9b6 LX |
357 | #define MSR_IA32_PERF_CAPABILITIES 0x345 |
358 | ||
2a9758c5 | 359 | #define MSR_IA32_TSX_CTRL 0x122 |
aa82ba54 | 360 | #define MSR_IA32_TSCDEADLINE 0x6e0 |
e7e7bdab | 361 | #define MSR_IA32_PKRS 0x6e1 |
2c0262af | 362 | |
217f1b4a HZ |
363 | #define FEATURE_CONTROL_LOCKED (1<<0) |
364 | #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) | |
365 | #define FEATURE_CONTROL_LMCE (1<<20) | |
366 | ||
0d894367 PB |
367 | #define MSR_P6_PERFCTR0 0xc1 |
368 | ||
fc12d72e | 369 | #define MSR_IA32_SMBASE 0x9e |
e13713db | 370 | #define MSR_SMI_COUNT 0x34 |
027ac0cb | 371 | #define MSR_CORE_THREAD_COUNT 0x35 |
e4a09c96 PB |
372 | #define MSR_MTRRcap 0xfe |
373 | #define MSR_MTRRcap_VCNT 8 | |
374 | #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8) | |
375 | #define MSR_MTRRcap_WC_SUPPORTED (1 << 10) | |
dd5e3b17 | 376 | |
2c0262af FB |
377 | #define MSR_IA32_SYSENTER_CS 0x174 |
378 | #define MSR_IA32_SYSENTER_ESP 0x175 | |
379 | #define MSR_IA32_SYSENTER_EIP 0x176 | |
380 | ||
8f091a59 FB |
381 | #define MSR_MCG_CAP 0x179 |
382 | #define MSR_MCG_STATUS 0x17a | |
383 | #define MSR_MCG_CTL 0x17b | |
87f8b626 | 384 | #define MSR_MCG_EXT_CTL 0x4d0 |
8f091a59 | 385 | |
0d894367 PB |
386 | #define MSR_P6_EVNTSEL0 0x186 |
387 | ||
e737b32a AZ |
388 | #define MSR_IA32_PERF_STATUS 0x198 |
389 | ||
e4a09c96 | 390 | #define MSR_IA32_MISC_ENABLE 0x1a0 |
21e87c46 AK |
391 | /* Indicates good rep/movs microcode on some processors: */ |
392 | #define MSR_IA32_MISC_ENABLE_DEFAULT 1 | |
4cfd7bab | 393 | #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) |
21e87c46 | 394 | |
e4a09c96 PB |
395 | #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) |
396 | #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1) | |
397 | ||
d1ae67f6 AW |
398 | #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2) |
399 | ||
e4a09c96 PB |
400 | #define MSR_MTRRfix64K_00000 0x250 |
401 | #define MSR_MTRRfix16K_80000 0x258 | |
402 | #define MSR_MTRRfix16K_A0000 0x259 | |
403 | #define MSR_MTRRfix4K_C0000 0x268 | |
404 | #define MSR_MTRRfix4K_C8000 0x269 | |
405 | #define MSR_MTRRfix4K_D0000 0x26a | |
406 | #define MSR_MTRRfix4K_D8000 0x26b | |
407 | #define MSR_MTRRfix4K_E0000 0x26c | |
408 | #define MSR_MTRRfix4K_E8000 0x26d | |
409 | #define MSR_MTRRfix4K_F0000 0x26e | |
410 | #define MSR_MTRRfix4K_F8000 0x26f | |
165d9b82 | 411 | |
8f091a59 FB |
412 | #define MSR_PAT 0x277 |
413 | ||
e4a09c96 | 414 | #define MSR_MTRRdefType 0x2ff |
165d9b82 | 415 | |
0d894367 PB |
416 | #define MSR_CORE_PERF_FIXED_CTR0 0x309 |
417 | #define MSR_CORE_PERF_FIXED_CTR1 0x30a | |
418 | #define MSR_CORE_PERF_FIXED_CTR2 0x30b | |
419 | #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d | |
420 | #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e | |
421 | #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f | |
422 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 | |
165d9b82 | 423 | |
e4a09c96 PB |
424 | #define MSR_MC0_CTL 0x400 |
425 | #define MSR_MC0_STATUS 0x401 | |
426 | #define MSR_MC0_ADDR 0x402 | |
427 | #define MSR_MC0_MISC 0x403 | |
79c4f6b0 | 428 | |
b77146e9 CP |
429 | #define MSR_IA32_RTIT_OUTPUT_BASE 0x560 |
430 | #define MSR_IA32_RTIT_OUTPUT_MASK 0x561 | |
431 | #define MSR_IA32_RTIT_CTL 0x570 | |
432 | #define MSR_IA32_RTIT_STATUS 0x571 | |
433 | #define MSR_IA32_RTIT_CR3_MATCH 0x572 | |
434 | #define MSR_IA32_RTIT_ADDR0_A 0x580 | |
435 | #define MSR_IA32_RTIT_ADDR0_B 0x581 | |
436 | #define MSR_IA32_RTIT_ADDR1_A 0x582 | |
437 | #define MSR_IA32_RTIT_ADDR1_B 0x583 | |
438 | #define MSR_IA32_RTIT_ADDR2_A 0x584 | |
439 | #define MSR_IA32_RTIT_ADDR2_B 0x585 | |
440 | #define MSR_IA32_RTIT_ADDR3_A 0x586 | |
441 | #define MSR_IA32_RTIT_ADDR3_B 0x587 | |
442 | #define MAX_RTIT_ADDRS 8 | |
443 | ||
14ce26e7 FB |
444 | #define MSR_EFER 0xc0000080 |
445 | ||
446 | #define MSR_EFER_SCE (1 << 0) | |
447 | #define MSR_EFER_LME (1 << 8) | |
448 | #define MSR_EFER_LMA (1 << 10) | |
449 | #define MSR_EFER_NXE (1 << 11) | |
872929aa | 450 | #define MSR_EFER_SVME (1 << 12) |
14ce26e7 FB |
451 | #define MSR_EFER_FFXSR (1 << 14) |
452 | ||
453 | #define MSR_STAR 0xc0000081 | |
454 | #define MSR_LSTAR 0xc0000082 | |
455 | #define MSR_CSTAR 0xc0000083 | |
456 | #define MSR_FMASK 0xc0000084 | |
457 | #define MSR_FSBASE 0xc0000100 | |
458 | #define MSR_GSBASE 0xc0000101 | |
459 | #define MSR_KERNELGSBASE 0xc0000102 | |
1b050077 | 460 | #define MSR_TSC_AUX 0xc0000103 |
14ce26e7 | 461 | |
0573fbfc TS |
462 | #define MSR_VM_HSAVE_PA 0xc0010117 |
463 | ||
79e9ebeb | 464 | #define MSR_IA32_BNDCFGS 0x00000d90 |
18cd2c17 | 465 | #define MSR_IA32_XSS 0x00000da0 |
65087997 | 466 | #define MSR_IA32_UMWAIT_CONTROL 0xe1 |
79e9ebeb | 467 | |
704798ad PB |
468 | #define MSR_IA32_VMX_BASIC 0x00000480 |
469 | #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 | |
470 | #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 | |
471 | #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 | |
472 | #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 | |
473 | #define MSR_IA32_VMX_MISC 0x00000485 | |
474 | #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 | |
475 | #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 | |
476 | #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 | |
477 | #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 | |
478 | #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a | |
479 | #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b | |
480 | #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c | |
481 | #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d | |
482 | #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e | |
483 | #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f | |
484 | #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 | |
485 | #define MSR_IA32_VMX_VMFUNC 0x00000491 | |
486 | ||
cfc3b074 PB |
487 | #define XSTATE_FP_BIT 0 |
488 | #define XSTATE_SSE_BIT 1 | |
489 | #define XSTATE_YMM_BIT 2 | |
490 | #define XSTATE_BNDREGS_BIT 3 | |
491 | #define XSTATE_BNDCSR_BIT 4 | |
492 | #define XSTATE_OPMASK_BIT 5 | |
493 | #define XSTATE_ZMM_Hi256_BIT 6 | |
494 | #define XSTATE_Hi16_ZMM_BIT 7 | |
495 | #define XSTATE_PKRU_BIT 9 | |
496 | ||
497 | #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT) | |
498 | #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT) | |
499 | #define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT) | |
500 | #define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT) | |
501 | #define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT) | |
502 | #define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT) | |
503 | #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT) | |
504 | #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) | |
505 | #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) | |
c74f41bb | 506 | |
5ef57876 EH |
507 | /* CPUID feature words */ |
508 | typedef enum FeatureWord { | |
509 | FEAT_1_EDX, /* CPUID[1].EDX */ | |
510 | FEAT_1_ECX, /* CPUID[1].ECX */ | |
511 | FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */ | |
f74eefe0 | 512 | FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */ |
95ea69fb | 513 | FEAT_7_0_EDX, /* CPUID[EAX=7,ECX=0].EDX */ |
80db491d | 514 | FEAT_7_1_EAX, /* CPUID[EAX=7,ECX=1].EAX */ |
5ef57876 EH |
515 | FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */ |
516 | FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */ | |
303752a9 | 517 | FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */ |
1b3420e1 | 518 | FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */ |
5ef57876 EH |
519 | FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */ |
520 | FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ | |
be777326 | 521 | FEAT_KVM_HINTS, /* CPUID[4000_0001].EDX */ |
c35bd19a EY |
522 | FEAT_HYPERV_EAX, /* CPUID[4000_0003].EAX */ |
523 | FEAT_HYPERV_EBX, /* CPUID[4000_0003].EBX */ | |
524 | FEAT_HYPERV_EDX, /* CPUID[4000_0003].EDX */ | |
a2b107db VK |
525 | FEAT_HV_RECOMM_EAX, /* CPUID[4000_0004].EAX */ |
526 | FEAT_HV_NESTED_EAX, /* CPUID[4000_000A].EAX */ | |
5ef57876 | 527 | FEAT_SVM, /* CPUID[8000_000A].EDX */ |
0bb0b2d2 | 528 | FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */ |
28b8e4d0 | 529 | FEAT_6_EAX, /* CPUID[6].EAX */ |
96193c22 EH |
530 | FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */ |
531 | FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */ | |
d86f9636 | 532 | FEAT_ARCH_CAPABILITIES, |
597360c0 | 533 | FEAT_CORE_CAPABILITY, |
ea39f9b6 | 534 | FEAT_PERF_CAPABILITIES, |
20a78b02 PB |
535 | FEAT_VMX_PROCBASED_CTLS, |
536 | FEAT_VMX_SECONDARY_CTLS, | |
537 | FEAT_VMX_PINBASED_CTLS, | |
538 | FEAT_VMX_EXIT_CTLS, | |
539 | FEAT_VMX_ENTRY_CTLS, | |
540 | FEAT_VMX_MISC, | |
541 | FEAT_VMX_EPT_VPID_CAPS, | |
542 | FEAT_VMX_BASIC, | |
543 | FEAT_VMX_VMFUNC, | |
d1615ea5 | 544 | FEAT_14_0_ECX, |
5ef57876 EH |
545 | FEATURE_WORDS, |
546 | } FeatureWord; | |
547 | ||
ede146c2 | 548 | typedef uint64_t FeatureWordArray[FEATURE_WORDS]; |
5ef57876 | 549 | |
14ce26e7 | 550 | /* cpuid_features bits */ |
2cd49cbf PM |
551 | #define CPUID_FP87 (1U << 0) |
552 | #define CPUID_VME (1U << 1) | |
553 | #define CPUID_DE (1U << 2) | |
554 | #define CPUID_PSE (1U << 3) | |
555 | #define CPUID_TSC (1U << 4) | |
556 | #define CPUID_MSR (1U << 5) | |
557 | #define CPUID_PAE (1U << 6) | |
558 | #define CPUID_MCE (1U << 7) | |
559 | #define CPUID_CX8 (1U << 8) | |
560 | #define CPUID_APIC (1U << 9) | |
561 | #define CPUID_SEP (1U << 11) /* sysenter/sysexit */ | |
562 | #define CPUID_MTRR (1U << 12) | |
563 | #define CPUID_PGE (1U << 13) | |
564 | #define CPUID_MCA (1U << 14) | |
565 | #define CPUID_CMOV (1U << 15) | |
566 | #define CPUID_PAT (1U << 16) | |
567 | #define CPUID_PSE36 (1U << 17) | |
568 | #define CPUID_PN (1U << 18) | |
569 | #define CPUID_CLFLUSH (1U << 19) | |
570 | #define CPUID_DTS (1U << 21) | |
571 | #define CPUID_ACPI (1U << 22) | |
572 | #define CPUID_MMX (1U << 23) | |
573 | #define CPUID_FXSR (1U << 24) | |
574 | #define CPUID_SSE (1U << 25) | |
575 | #define CPUID_SSE2 (1U << 26) | |
576 | #define CPUID_SS (1U << 27) | |
577 | #define CPUID_HT (1U << 28) | |
578 | #define CPUID_TM (1U << 29) | |
579 | #define CPUID_IA64 (1U << 30) | |
580 | #define CPUID_PBE (1U << 31) | |
581 | ||
582 | #define CPUID_EXT_SSE3 (1U << 0) | |
583 | #define CPUID_EXT_PCLMULQDQ (1U << 1) | |
584 | #define CPUID_EXT_DTES64 (1U << 2) | |
585 | #define CPUID_EXT_MONITOR (1U << 3) | |
586 | #define CPUID_EXT_DSCPL (1U << 4) | |
587 | #define CPUID_EXT_VMX (1U << 5) | |
588 | #define CPUID_EXT_SMX (1U << 6) | |
589 | #define CPUID_EXT_EST (1U << 7) | |
590 | #define CPUID_EXT_TM2 (1U << 8) | |
591 | #define CPUID_EXT_SSSE3 (1U << 9) | |
592 | #define CPUID_EXT_CID (1U << 10) | |
593 | #define CPUID_EXT_FMA (1U << 12) | |
594 | #define CPUID_EXT_CX16 (1U << 13) | |
595 | #define CPUID_EXT_XTPR (1U << 14) | |
596 | #define CPUID_EXT_PDCM (1U << 15) | |
597 | #define CPUID_EXT_PCID (1U << 17) | |
598 | #define CPUID_EXT_DCA (1U << 18) | |
599 | #define CPUID_EXT_SSE41 (1U << 19) | |
600 | #define CPUID_EXT_SSE42 (1U << 20) | |
601 | #define CPUID_EXT_X2APIC (1U << 21) | |
602 | #define CPUID_EXT_MOVBE (1U << 22) | |
603 | #define CPUID_EXT_POPCNT (1U << 23) | |
604 | #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24) | |
605 | #define CPUID_EXT_AES (1U << 25) | |
606 | #define CPUID_EXT_XSAVE (1U << 26) | |
607 | #define CPUID_EXT_OSXSAVE (1U << 27) | |
608 | #define CPUID_EXT_AVX (1U << 28) | |
609 | #define CPUID_EXT_F16C (1U << 29) | |
610 | #define CPUID_EXT_RDRAND (1U << 30) | |
611 | #define CPUID_EXT_HYPERVISOR (1U << 31) | |
612 | ||
613 | #define CPUID_EXT2_FPU (1U << 0) | |
614 | #define CPUID_EXT2_VME (1U << 1) | |
615 | #define CPUID_EXT2_DE (1U << 2) | |
616 | #define CPUID_EXT2_PSE (1U << 3) | |
617 | #define CPUID_EXT2_TSC (1U << 4) | |
618 | #define CPUID_EXT2_MSR (1U << 5) | |
619 | #define CPUID_EXT2_PAE (1U << 6) | |
620 | #define CPUID_EXT2_MCE (1U << 7) | |
621 | #define CPUID_EXT2_CX8 (1U << 8) | |
622 | #define CPUID_EXT2_APIC (1U << 9) | |
623 | #define CPUID_EXT2_SYSCALL (1U << 11) | |
624 | #define CPUID_EXT2_MTRR (1U << 12) | |
625 | #define CPUID_EXT2_PGE (1U << 13) | |
626 | #define CPUID_EXT2_MCA (1U << 14) | |
627 | #define CPUID_EXT2_CMOV (1U << 15) | |
628 | #define CPUID_EXT2_PAT (1U << 16) | |
629 | #define CPUID_EXT2_PSE36 (1U << 17) | |
630 | #define CPUID_EXT2_MP (1U << 19) | |
631 | #define CPUID_EXT2_NX (1U << 20) | |
632 | #define CPUID_EXT2_MMXEXT (1U << 22) | |
633 | #define CPUID_EXT2_MMX (1U << 23) | |
634 | #define CPUID_EXT2_FXSR (1U << 24) | |
635 | #define CPUID_EXT2_FFXSR (1U << 25) | |
636 | #define CPUID_EXT2_PDPE1GB (1U << 26) | |
637 | #define CPUID_EXT2_RDTSCP (1U << 27) | |
638 | #define CPUID_EXT2_LM (1U << 29) | |
639 | #define CPUID_EXT2_3DNOWEXT (1U << 30) | |
640 | #define CPUID_EXT2_3DNOW (1U << 31) | |
9df217a3 | 641 | |
8fad4b44 EH |
642 | /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */ |
643 | #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \ | |
644 | CPUID_EXT2_DE | CPUID_EXT2_PSE | \ | |
645 | CPUID_EXT2_TSC | CPUID_EXT2_MSR | \ | |
646 | CPUID_EXT2_PAE | CPUID_EXT2_MCE | \ | |
647 | CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \ | |
648 | CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \ | |
649 | CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \ | |
650 | CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \ | |
651 | CPUID_EXT2_MMX | CPUID_EXT2_FXSR) | |
652 | ||
2cd49cbf PM |
653 | #define CPUID_EXT3_LAHF_LM (1U << 0) |
654 | #define CPUID_EXT3_CMP_LEG (1U << 1) | |
655 | #define CPUID_EXT3_SVM (1U << 2) | |
656 | #define CPUID_EXT3_EXTAPIC (1U << 3) | |
657 | #define CPUID_EXT3_CR8LEG (1U << 4) | |
658 | #define CPUID_EXT3_ABM (1U << 5) | |
659 | #define CPUID_EXT3_SSE4A (1U << 6) | |
660 | #define CPUID_EXT3_MISALIGNSSE (1U << 7) | |
661 | #define CPUID_EXT3_3DNOWPREFETCH (1U << 8) | |
662 | #define CPUID_EXT3_OSVW (1U << 9) | |
663 | #define CPUID_EXT3_IBS (1U << 10) | |
664 | #define CPUID_EXT3_XOP (1U << 11) | |
665 | #define CPUID_EXT3_SKINIT (1U << 12) | |
666 | #define CPUID_EXT3_WDT (1U << 13) | |
667 | #define CPUID_EXT3_LWP (1U << 15) | |
668 | #define CPUID_EXT3_FMA4 (1U << 16) | |
669 | #define CPUID_EXT3_TCE (1U << 17) | |
670 | #define CPUID_EXT3_NODEID (1U << 19) | |
671 | #define CPUID_EXT3_TBM (1U << 21) | |
672 | #define CPUID_EXT3_TOPOEXT (1U << 22) | |
673 | #define CPUID_EXT3_PERFCORE (1U << 23) | |
674 | #define CPUID_EXT3_PERFNB (1U << 24) | |
675 | ||
5447089c WH |
676 | #define CPUID_SVM_NPT (1U << 0) |
677 | #define CPUID_SVM_LBRV (1U << 1) | |
678 | #define CPUID_SVM_SVMLOCK (1U << 2) | |
679 | #define CPUID_SVM_NRIPSAVE (1U << 3) | |
680 | #define CPUID_SVM_TSCSCALE (1U << 4) | |
681 | #define CPUID_SVM_VMCBCLEAN (1U << 5) | |
682 | #define CPUID_SVM_FLUSHASID (1U << 6) | |
683 | #define CPUID_SVM_DECODEASSIST (1U << 7) | |
684 | #define CPUID_SVM_PAUSEFILTER (1U << 10) | |
685 | #define CPUID_SVM_PFTHRESHOLD (1U << 12) | |
686 | #define CPUID_SVM_AVIC (1U << 13) | |
687 | #define CPUID_SVM_V_VMSAVE_VMLOAD (1U << 15) | |
688 | #define CPUID_SVM_VGIF (1U << 16) | |
689 | #define CPUID_SVM_SVME_ADDR_CHK (1U << 28) | |
2cd49cbf | 690 | |
f2be0beb TX |
691 | /* Support RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */ |
692 | #define CPUID_7_0_EBX_FSGSBASE (1U << 0) | |
693 | /* 1st Group of Advanced Bit Manipulation Extensions */ | |
694 | #define CPUID_7_0_EBX_BMI1 (1U << 3) | |
695 | /* Hardware Lock Elision */ | |
696 | #define CPUID_7_0_EBX_HLE (1U << 4) | |
697 | /* Intel Advanced Vector Extensions 2 */ | |
698 | #define CPUID_7_0_EBX_AVX2 (1U << 5) | |
699 | /* Supervisor-mode Execution Prevention */ | |
700 | #define CPUID_7_0_EBX_SMEP (1U << 7) | |
701 | /* 2nd Group of Advanced Bit Manipulation Extensions */ | |
702 | #define CPUID_7_0_EBX_BMI2 (1U << 8) | |
703 | /* Enhanced REP MOVSB/STOSB */ | |
704 | #define CPUID_7_0_EBX_ERMS (1U << 9) | |
705 | /* Invalidate Process-Context Identifier */ | |
706 | #define CPUID_7_0_EBX_INVPCID (1U << 10) | |
707 | /* Restricted Transactional Memory */ | |
708 | #define CPUID_7_0_EBX_RTM (1U << 11) | |
709 | /* Memory Protection Extension */ | |
710 | #define CPUID_7_0_EBX_MPX (1U << 14) | |
711 | /* AVX-512 Foundation */ | |
712 | #define CPUID_7_0_EBX_AVX512F (1U << 16) | |
713 | /* AVX-512 Doubleword & Quadword Instruction */ | |
714 | #define CPUID_7_0_EBX_AVX512DQ (1U << 17) | |
715 | /* Read Random SEED */ | |
716 | #define CPUID_7_0_EBX_RDSEED (1U << 18) | |
717 | /* ADCX and ADOX instructions */ | |
718 | #define CPUID_7_0_EBX_ADX (1U << 19) | |
719 | /* Supervisor Mode Access Prevention */ | |
720 | #define CPUID_7_0_EBX_SMAP (1U << 20) | |
721 | /* AVX-512 Integer Fused Multiply Add */ | |
722 | #define CPUID_7_0_EBX_AVX512IFMA (1U << 21) | |
723 | /* Persistent Commit */ | |
724 | #define CPUID_7_0_EBX_PCOMMIT (1U << 22) | |
725 | /* Flush a Cache Line Optimized */ | |
726 | #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) | |
727 | /* Cache Line Write Back */ | |
728 | #define CPUID_7_0_EBX_CLWB (1U << 24) | |
729 | /* Intel Processor Trace */ | |
730 | #define CPUID_7_0_EBX_INTEL_PT (1U << 25) | |
731 | /* AVX-512 Prefetch */ | |
732 | #define CPUID_7_0_EBX_AVX512PF (1U << 26) | |
733 | /* AVX-512 Exponential and Reciprocal */ | |
734 | #define CPUID_7_0_EBX_AVX512ER (1U << 27) | |
735 | /* AVX-512 Conflict Detection */ | |
736 | #define CPUID_7_0_EBX_AVX512CD (1U << 28) | |
737 | /* SHA1/SHA256 Instruction Extensions */ | |
738 | #define CPUID_7_0_EBX_SHA_NI (1U << 29) | |
739 | /* AVX-512 Byte and Word Instructions */ | |
740 | #define CPUID_7_0_EBX_AVX512BW (1U << 30) | |
741 | /* AVX-512 Vector Length Extensions */ | |
742 | #define CPUID_7_0_EBX_AVX512VL (1U << 31) | |
743 | ||
744 | /* AVX-512 Vector Byte Manipulation Instruction */ | |
e7694a5e | 745 | #define CPUID_7_0_ECX_AVX512_VBMI (1U << 1) |
f2be0beb TX |
746 | /* User-Mode Instruction Prevention */ |
747 | #define CPUID_7_0_ECX_UMIP (1U << 2) | |
748 | /* Protection Keys for User-mode Pages */ | |
749 | #define CPUID_7_0_ECX_PKU (1U << 3) | |
750 | /* OS Enable Protection Keys */ | |
751 | #define CPUID_7_0_ECX_OSPKE (1U << 4) | |
67192a29 TX |
752 | /* UMONITOR/UMWAIT/TPAUSE Instructions */ |
753 | #define CPUID_7_0_ECX_WAITPKG (1U << 5) | |
f2be0beb | 754 | /* Additional AVX-512 Vector Byte Manipulation Instruction */ |
e7694a5e | 755 | #define CPUID_7_0_ECX_AVX512_VBMI2 (1U << 6) |
f2be0beb TX |
756 | /* Galois Field New Instructions */ |
757 | #define CPUID_7_0_ECX_GFNI (1U << 8) | |
758 | /* Vector AES Instructions */ | |
759 | #define CPUID_7_0_ECX_VAES (1U << 9) | |
760 | /* Carry-Less Multiplication Quadword */ | |
761 | #define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10) | |
762 | /* Vector Neural Network Instructions */ | |
763 | #define CPUID_7_0_ECX_AVX512VNNI (1U << 11) | |
764 | /* Support for VPOPCNT[B,W] and VPSHUFBITQMB */ | |
765 | #define CPUID_7_0_ECX_AVX512BITALG (1U << 12) | |
766 | /* POPCNT for vectors of DW/QW */ | |
767 | #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) | |
768 | /* 5-level Page Tables */ | |
769 | #define CPUID_7_0_ECX_LA57 (1U << 16) | |
770 | /* Read Processor ID */ | |
771 | #define CPUID_7_0_ECX_RDPID (1U << 22) | |
772 | /* Cache Line Demote Instruction */ | |
773 | #define CPUID_7_0_ECX_CLDEMOTE (1U << 25) | |
774 | /* Move Doubleword as Direct Store Instruction */ | |
775 | #define CPUID_7_0_ECX_MOVDIRI (1U << 27) | |
776 | /* Move 64 Bytes as Direct Store Instruction */ | |
777 | #define CPUID_7_0_ECX_MOVDIR64B (1U << 28) | |
e7e7bdab PB |
778 | /* Protection Keys for Supervisor-mode Pages */ |
779 | #define CPUID_7_0_ECX_PKS (1U << 31) | |
f2be0beb TX |
780 | |
781 | /* AVX512 Neural Network Instructions */ | |
782 | #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) | |
783 | /* AVX512 Multiply Accumulation Single Precision */ | |
784 | #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) | |
5cb287d2 CQ |
785 | /* Fast Short Rep Mov */ |
786 | #define CPUID_7_0_EDX_FSRM (1U << 4) | |
353f98c9 CZ |
787 | /* AVX512 Vector Pair Intersection to a Pair of Mask Registers */ |
788 | #define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8) | |
5dd13f2a CZ |
789 | /* SERIALIZE instruction */ |
790 | #define CPUID_7_0_EDX_SERIALIZE (1U << 14) | |
b3c7344e CZ |
791 | /* TSX Suspend Load Address Tracking instruction */ |
792 | #define CPUID_7_0_EDX_TSX_LDTRK (1U << 16) | |
40399ecb CZ |
793 | /* AVX512_FP16 instruction */ |
794 | #define CPUID_7_0_EDX_AVX512_FP16 (1U << 23) | |
f2be0beb TX |
795 | /* Speculation Control */ |
796 | #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) | |
5af514d0 CZ |
797 | /* Single Thread Indirect Branch Predictors */ |
798 | #define CPUID_7_0_EDX_STIBP (1U << 27) | |
f2be0beb TX |
799 | /* Arch Capabilities */ |
800 | #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) | |
801 | /* Core Capability */ | |
802 | #define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30) | |
803 | /* Speculative Store Bypass Disable */ | |
804 | #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) | |
805 | ||
806 | /* AVX512 BFloat16 Instruction */ | |
807 | #define CPUID_7_1_EAX_AVX512_BF16 (1U << 5) | |
808 | ||
d1615ea5 LK |
809 | /* Packets which contain IP payload have LIP values */ |
810 | #define CPUID_14_0_ECX_LIP (1U << 31) | |
811 | ||
f2be0beb TX |
812 | /* CLZERO instruction */ |
813 | #define CPUID_8000_0008_EBX_CLZERO (1U << 0) | |
814 | /* Always save/restore FP error pointers */ | |
815 | #define CPUID_8000_0008_EBX_XSAVEERPTR (1U << 2) | |
816 | /* Write back and do not invalidate cache */ | |
817 | #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) | |
818 | /* Indirect Branch Prediction Barrier */ | |
819 | #define CPUID_8000_0008_EBX_IBPB (1U << 12) | |
143c30d4 MB |
820 | /* Single Thread Indirect Branch Predictors */ |
821 | #define CPUID_8000_0008_EBX_STIBP (1U << 15) | |
1b3420e1 | 822 | |
0bb0b2d2 PB |
823 | #define CPUID_XSAVE_XSAVEOPT (1U << 0) |
824 | #define CPUID_XSAVE_XSAVEC (1U << 1) | |
825 | #define CPUID_XSAVE_XGETBV1 (1U << 2) | |
826 | #define CPUID_XSAVE_XSAVES (1U << 3) | |
827 | ||
28b8e4d0 JK |
828 | #define CPUID_6_EAX_ARAT (1U << 2) |
829 | ||
303752a9 MT |
830 | /* CPUID[0x80000007].EDX flags: */ |
831 | #define CPUID_APM_INVTSC (1U << 8) | |
832 | ||
9df694ee IM |
833 | #define CPUID_VENDOR_SZ 12 |
834 | ||
c5096daf AZ |
835 | #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */ |
836 | #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */ | |
837 | #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */ | |
99b88a17 | 838 | #define CPUID_VENDOR_INTEL "GenuineIntel" |
c5096daf AZ |
839 | |
840 | #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */ | |
b3baa152 | 841 | #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ |
c5096daf | 842 | #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ |
99b88a17 | 843 | #define CPUID_VENDOR_AMD "AuthenticAMD" |
c5096daf | 844 | |
99b88a17 | 845 | #define CPUID_VENDOR_VIA "CentaurHauls" |
b3baa152 | 846 | |
8d031cec PW |
847 | #define CPUID_VENDOR_HYGON "HygonGenuine" |
848 | ||
18ab37ba LA |
849 | #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \ |
850 | (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \ | |
851 | (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3) | |
852 | #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \ | |
853 | (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \ | |
854 | (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3) | |
855 | ||
2cd49cbf PM |
856 | #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */ |
857 | #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */ | |
e737b32a | 858 | |
5232d00a RK |
859 | /* CPUID[0xB].ECX level types */ |
860 | #define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8) | |
861 | #define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8) | |
862 | #define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8) | |
a94e1428 | 863 | #define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8) |
5232d00a | 864 | |
d86f9636 | 865 | /* MSR Feature Bits */ |
6c997b4a XL |
866 | #define MSR_ARCH_CAP_RDCL_NO (1U << 0) |
867 | #define MSR_ARCH_CAP_IBRS_ALL (1U << 1) | |
868 | #define MSR_ARCH_CAP_RSBA (1U << 2) | |
d86f9636 | 869 | #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3) |
6c997b4a XL |
870 | #define MSR_ARCH_CAP_SSB_NO (1U << 4) |
871 | #define MSR_ARCH_CAP_MDS_NO (1U << 5) | |
872 | #define MSR_ARCH_CAP_PSCHANGE_MC_NO (1U << 6) | |
873 | #define MSR_ARCH_CAP_TSX_CTRL_MSR (1U << 7) | |
874 | #define MSR_ARCH_CAP_TAA_NO (1U << 8) | |
d86f9636 | 875 | |
597360c0 XL |
876 | #define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5) |
877 | ||
704798ad PB |
878 | /* VMX MSR features */ |
879 | #define MSR_VMX_BASIC_VMCS_REVISION_MASK 0x7FFFFFFFull | |
880 | #define MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK (0x00001FFFull << 32) | |
881 | #define MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK (0x003C0000ull << 32) | |
882 | #define MSR_VMX_BASIC_DUAL_MONITOR (1ULL << 49) | |
883 | #define MSR_VMX_BASIC_INS_OUTS (1ULL << 54) | |
884 | #define MSR_VMX_BASIC_TRUE_CTLS (1ULL << 55) | |
885 | ||
886 | #define MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK 0x1Full | |
887 | #define MSR_VMX_MISC_STORE_LMA (1ULL << 5) | |
888 | #define MSR_VMX_MISC_ACTIVITY_HLT (1ULL << 6) | |
889 | #define MSR_VMX_MISC_ACTIVITY_SHUTDOWN (1ULL << 7) | |
890 | #define MSR_VMX_MISC_ACTIVITY_WAIT_SIPI (1ULL << 8) | |
891 | #define MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK 0x0E000000ull | |
892 | #define MSR_VMX_MISC_VMWRITE_VMEXIT (1ULL << 29) | |
893 | #define MSR_VMX_MISC_ZERO_LEN_INJECT (1ULL << 30) | |
894 | ||
895 | #define MSR_VMX_EPT_EXECONLY (1ULL << 0) | |
896 | #define MSR_VMX_EPT_PAGE_WALK_LENGTH_4 (1ULL << 6) | |
897 | #define MSR_VMX_EPT_PAGE_WALK_LENGTH_5 (1ULL << 7) | |
898 | #define MSR_VMX_EPT_UC (1ULL << 8) | |
899 | #define MSR_VMX_EPT_WB (1ULL << 14) | |
900 | #define MSR_VMX_EPT_2MB (1ULL << 16) | |
901 | #define MSR_VMX_EPT_1GB (1ULL << 17) | |
902 | #define MSR_VMX_EPT_INVEPT (1ULL << 20) | |
903 | #define MSR_VMX_EPT_AD_BITS (1ULL << 21) | |
904 | #define MSR_VMX_EPT_ADVANCED_VMEXIT_INFO (1ULL << 22) | |
905 | #define MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT (1ULL << 25) | |
906 | #define MSR_VMX_EPT_INVEPT_ALL_CONTEXT (1ULL << 26) | |
907 | #define MSR_VMX_EPT_INVVPID (1ULL << 32) | |
908 | #define MSR_VMX_EPT_INVVPID_SINGLE_ADDR (1ULL << 40) | |
909 | #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT (1ULL << 41) | |
910 | #define MSR_VMX_EPT_INVVPID_ALL_CONTEXT (1ULL << 42) | |
911 | #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS (1ULL << 43) | |
912 | ||
913 | #define MSR_VMX_VMFUNC_EPT_SWITCHING (1ULL << 0) | |
914 | ||
915 | ||
916 | /* VMX controls */ | |
917 | #define VMX_CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004 | |
918 | #define VMX_CPU_BASED_USE_TSC_OFFSETING 0x00000008 | |
919 | #define VMX_CPU_BASED_HLT_EXITING 0x00000080 | |
920 | #define VMX_CPU_BASED_INVLPG_EXITING 0x00000200 | |
921 | #define VMX_CPU_BASED_MWAIT_EXITING 0x00000400 | |
922 | #define VMX_CPU_BASED_RDPMC_EXITING 0x00000800 | |
923 | #define VMX_CPU_BASED_RDTSC_EXITING 0x00001000 | |
924 | #define VMX_CPU_BASED_CR3_LOAD_EXITING 0x00008000 | |
925 | #define VMX_CPU_BASED_CR3_STORE_EXITING 0x00010000 | |
926 | #define VMX_CPU_BASED_CR8_LOAD_EXITING 0x00080000 | |
927 | #define VMX_CPU_BASED_CR8_STORE_EXITING 0x00100000 | |
928 | #define VMX_CPU_BASED_TPR_SHADOW 0x00200000 | |
929 | #define VMX_CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000 | |
930 | #define VMX_CPU_BASED_MOV_DR_EXITING 0x00800000 | |
931 | #define VMX_CPU_BASED_UNCOND_IO_EXITING 0x01000000 | |
932 | #define VMX_CPU_BASED_USE_IO_BITMAPS 0x02000000 | |
933 | #define VMX_CPU_BASED_MONITOR_TRAP_FLAG 0x08000000 | |
934 | #define VMX_CPU_BASED_USE_MSR_BITMAPS 0x10000000 | |
935 | #define VMX_CPU_BASED_MONITOR_EXITING 0x20000000 | |
936 | #define VMX_CPU_BASED_PAUSE_EXITING 0x40000000 | |
937 | #define VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000 | |
938 | ||
939 | #define VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001 | |
940 | #define VMX_SECONDARY_EXEC_ENABLE_EPT 0x00000002 | |
941 | #define VMX_SECONDARY_EXEC_DESC 0x00000004 | |
942 | #define VMX_SECONDARY_EXEC_RDTSCP 0x00000008 | |
943 | #define VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010 | |
944 | #define VMX_SECONDARY_EXEC_ENABLE_VPID 0x00000020 | |
945 | #define VMX_SECONDARY_EXEC_WBINVD_EXITING 0x00000040 | |
946 | #define VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080 | |
947 | #define VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100 | |
948 | #define VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200 | |
949 | #define VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400 | |
950 | #define VMX_SECONDARY_EXEC_RDRAND_EXITING 0x00000800 | |
951 | #define VMX_SECONDARY_EXEC_ENABLE_INVPCID 0x00001000 | |
952 | #define VMX_SECONDARY_EXEC_ENABLE_VMFUNC 0x00002000 | |
953 | #define VMX_SECONDARY_EXEC_SHADOW_VMCS 0x00004000 | |
954 | #define VMX_SECONDARY_EXEC_ENCLS_EXITING 0x00008000 | |
955 | #define VMX_SECONDARY_EXEC_RDSEED_EXITING 0x00010000 | |
956 | #define VMX_SECONDARY_EXEC_ENABLE_PML 0x00020000 | |
957 | #define VMX_SECONDARY_EXEC_XSAVES 0x00100000 | |
958 | ||
959 | #define VMX_PIN_BASED_EXT_INTR_MASK 0x00000001 | |
960 | #define VMX_PIN_BASED_NMI_EXITING 0x00000008 | |
961 | #define VMX_PIN_BASED_VIRTUAL_NMIS 0x00000020 | |
962 | #define VMX_PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040 | |
963 | #define VMX_PIN_BASED_POSTED_INTR 0x00000080 | |
964 | ||
965 | #define VMX_VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004 | |
966 | #define VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200 | |
967 | #define VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000 | |
968 | #define VMX_VM_EXIT_ACK_INTR_ON_EXIT 0x00008000 | |
969 | #define VMX_VM_EXIT_SAVE_IA32_PAT 0x00040000 | |
970 | #define VMX_VM_EXIT_LOAD_IA32_PAT 0x00080000 | |
971 | #define VMX_VM_EXIT_SAVE_IA32_EFER 0x00100000 | |
972 | #define VMX_VM_EXIT_LOAD_IA32_EFER 0x00200000 | |
973 | #define VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000 | |
974 | #define VMX_VM_EXIT_CLEAR_BNDCFGS 0x00800000 | |
975 | #define VMX_VM_EXIT_PT_CONCEAL_PIP 0x01000000 | |
976 | #define VMX_VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000 | |
52a44ad2 | 977 | #define VMX_VM_EXIT_LOAD_IA32_PKRS 0x20000000 |
704798ad PB |
978 | |
979 | #define VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004 | |
980 | #define VMX_VM_ENTRY_IA32E_MODE 0x00000200 | |
981 | #define VMX_VM_ENTRY_SMM 0x00000400 | |
982 | #define VMX_VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800 | |
983 | #define VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000 | |
984 | #define VMX_VM_ENTRY_LOAD_IA32_PAT 0x00004000 | |
985 | #define VMX_VM_ENTRY_LOAD_IA32_EFER 0x00008000 | |
986 | #define VMX_VM_ENTRY_LOAD_BNDCFGS 0x00010000 | |
987 | #define VMX_VM_ENTRY_PT_CONCEAL_PIP 0x00020000 | |
988 | #define VMX_VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000 | |
52a44ad2 | 989 | #define VMX_VM_ENTRY_LOAD_IA32_PKRS 0x00400000 |
704798ad | 990 | |
2d384d7c VK |
991 | /* Supported Hyper-V Enlightenments */ |
992 | #define HYPERV_FEAT_RELAXED 0 | |
993 | #define HYPERV_FEAT_VAPIC 1 | |
994 | #define HYPERV_FEAT_TIME 2 | |
995 | #define HYPERV_FEAT_CRASH 3 | |
996 | #define HYPERV_FEAT_RESET 4 | |
997 | #define HYPERV_FEAT_VPINDEX 5 | |
998 | #define HYPERV_FEAT_RUNTIME 6 | |
999 | #define HYPERV_FEAT_SYNIC 7 | |
1000 | #define HYPERV_FEAT_STIMER 8 | |
1001 | #define HYPERV_FEAT_FREQUENCIES 9 | |
1002 | #define HYPERV_FEAT_REENLIGHTENMENT 10 | |
1003 | #define HYPERV_FEAT_TLBFLUSH 11 | |
1004 | #define HYPERV_FEAT_EVMCS 12 | |
1005 | #define HYPERV_FEAT_IPI 13 | |
128531d9 | 1006 | #define HYPERV_FEAT_STIMER_DIRECT 14 |
2d384d7c | 1007 | |
f701c082 VK |
1008 | #ifndef HYPERV_SPINLOCK_NEVER_NOTIFY |
1009 | #define HYPERV_SPINLOCK_NEVER_NOTIFY 0xFFFFFFFF | |
92067bf4 IM |
1010 | #endif |
1011 | ||
2c0262af | 1012 | #define EXCP00_DIVZ 0 |
01df040b | 1013 | #define EXCP01_DB 1 |
2c0262af FB |
1014 | #define EXCP02_NMI 2 |
1015 | #define EXCP03_INT3 3 | |
1016 | #define EXCP04_INTO 4 | |
1017 | #define EXCP05_BOUND 5 | |
1018 | #define EXCP06_ILLOP 6 | |
1019 | #define EXCP07_PREX 7 | |
1020 | #define EXCP08_DBLE 8 | |
1021 | #define EXCP09_XERR 9 | |
1022 | #define EXCP0A_TSS 10 | |
1023 | #define EXCP0B_NOSEG 11 | |
1024 | #define EXCP0C_STACK 12 | |
1025 | #define EXCP0D_GPF 13 | |
1026 | #define EXCP0E_PAGE 14 | |
1027 | #define EXCP10_COPR 16 | |
1028 | #define EXCP11_ALGN 17 | |
1029 | #define EXCP12_MCHK 18 | |
1030 | ||
62846089 RH |
1031 | #define EXCP_VMEXIT 0x100 /* only for system emulation */ |
1032 | #define EXCP_SYSCALL 0x101 /* only for user emulation */ | |
b26491b4 | 1033 | #define EXCP_VSYSCALL 0x102 /* only for user emulation */ |
d2fd1af7 | 1034 | |
00a152b4 | 1035 | /* i386-specific interrupt pending bits. */ |
5d62c43a | 1036 | #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1 |
00a152b4 | 1037 | #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2 |
85097db6 | 1038 | #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 |
00a152b4 RH |
1039 | #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4 |
1040 | #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0 | |
4a92a558 PB |
1041 | #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1 |
1042 | #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2 | |
00a152b4 | 1043 | |
4a92a558 PB |
1044 | /* Use a clearer name for this. */ |
1045 | #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET | |
00a152b4 | 1046 | |
c3ce5a23 PB |
1047 | /* Instead of computing the condition codes after each x86 instruction, |
1048 | * QEMU just stores one operand (called CC_SRC), the result | |
1049 | * (called CC_DST) and the type of operation (called CC_OP). When the | |
1050 | * condition codes are needed, the condition codes can be calculated | |
1051 | * using this information. Condition codes are not generated if they | |
1052 | * are only needed for conditional branches. | |
1053 | */ | |
fee71888 | 1054 | typedef enum { |
2c0262af | 1055 | CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ |
1235fc06 | 1056 | CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */ |
d36cd60e FB |
1057 | |
1058 | CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */ | |
1059 | CC_OP_MULW, | |
1060 | CC_OP_MULL, | |
14ce26e7 | 1061 | CC_OP_MULQ, |
2c0262af FB |
1062 | |
1063 | CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
1064 | CC_OP_ADDW, | |
1065 | CC_OP_ADDL, | |
14ce26e7 | 1066 | CC_OP_ADDQ, |
2c0262af FB |
1067 | |
1068 | CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
1069 | CC_OP_ADCW, | |
1070 | CC_OP_ADCL, | |
14ce26e7 | 1071 | CC_OP_ADCQ, |
2c0262af FB |
1072 | |
1073 | CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
1074 | CC_OP_SUBW, | |
1075 | CC_OP_SUBL, | |
14ce26e7 | 1076 | CC_OP_SUBQ, |
2c0262af FB |
1077 | |
1078 | CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
1079 | CC_OP_SBBW, | |
1080 | CC_OP_SBBL, | |
14ce26e7 | 1081 | CC_OP_SBBQ, |
2c0262af FB |
1082 | |
1083 | CC_OP_LOGICB, /* modify all flags, CC_DST = res */ | |
1084 | CC_OP_LOGICW, | |
1085 | CC_OP_LOGICL, | |
14ce26e7 | 1086 | CC_OP_LOGICQ, |
2c0262af FB |
1087 | |
1088 | CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */ | |
1089 | CC_OP_INCW, | |
1090 | CC_OP_INCL, | |
14ce26e7 | 1091 | CC_OP_INCQ, |
2c0262af FB |
1092 | |
1093 | CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */ | |
1094 | CC_OP_DECW, | |
1095 | CC_OP_DECL, | |
14ce26e7 | 1096 | CC_OP_DECQ, |
2c0262af | 1097 | |
6b652794 | 1098 | CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */ |
2c0262af FB |
1099 | CC_OP_SHLW, |
1100 | CC_OP_SHLL, | |
14ce26e7 | 1101 | CC_OP_SHLQ, |
2c0262af FB |
1102 | |
1103 | CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */ | |
1104 | CC_OP_SARW, | |
1105 | CC_OP_SARL, | |
14ce26e7 | 1106 | CC_OP_SARQ, |
2c0262af | 1107 | |
bc4b43dc RH |
1108 | CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */ |
1109 | CC_OP_BMILGW, | |
1110 | CC_OP_BMILGL, | |
1111 | CC_OP_BMILGQ, | |
1112 | ||
cd7f97ca RH |
1113 | CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */ |
1114 | CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest. */ | |
1115 | CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */ | |
1116 | ||
436ff2d2 | 1117 | CC_OP_CLR, /* Z set, all other flags clear. */ |
4885c3c4 | 1118 | CC_OP_POPCNT, /* Z via CC_SRC, all other flags clear. */ |
436ff2d2 | 1119 | |
2c0262af | 1120 | CC_OP_NB, |
fee71888 | 1121 | } CCOp; |
2c0262af | 1122 | |
2c0262af FB |
1123 | typedef struct SegmentCache { |
1124 | uint32_t selector; | |
14ce26e7 | 1125 | target_ulong base; |
2c0262af FB |
1126 | uint32_t limit; |
1127 | uint32_t flags; | |
1128 | } SegmentCache; | |
1129 | ||
f23a9db6 EH |
1130 | #define MMREG_UNION(n, bits) \ |
1131 | union n { \ | |
1132 | uint8_t _b_##n[(bits)/8]; \ | |
1133 | uint16_t _w_##n[(bits)/16]; \ | |
1134 | uint32_t _l_##n[(bits)/32]; \ | |
1135 | uint64_t _q_##n[(bits)/64]; \ | |
1136 | float32 _s_##n[(bits)/32]; \ | |
1137 | float64 _d_##n[(bits)/64]; \ | |
31d414d6 EH |
1138 | } |
1139 | ||
c97d6d2c SAGDR |
1140 | typedef union { |
1141 | uint8_t _b[16]; | |
1142 | uint16_t _w[8]; | |
1143 | uint32_t _l[4]; | |
1144 | uint64_t _q[2]; | |
1145 | } XMMReg; | |
1146 | ||
1147 | typedef union { | |
1148 | uint8_t _b[32]; | |
1149 | uint16_t _w[16]; | |
1150 | uint32_t _l[8]; | |
1151 | uint64_t _q[4]; | |
1152 | } YMMReg; | |
1153 | ||
f23a9db6 EH |
1154 | typedef MMREG_UNION(ZMMReg, 512) ZMMReg; |
1155 | typedef MMREG_UNION(MMXReg, 64) MMXReg; | |
826461bb | 1156 | |
79e9ebeb LJ |
1157 | typedef struct BNDReg { |
1158 | uint64_t lb; | |
1159 | uint64_t ub; | |
1160 | } BNDReg; | |
1161 | ||
1162 | typedef struct BNDCSReg { | |
1163 | uint64_t cfgu; | |
1164 | uint64_t sts; | |
1165 | } BNDCSReg; | |
1166 | ||
f4f1110e RH |
1167 | #define BNDCFG_ENABLE 1ULL |
1168 | #define BNDCFG_BNDPRESERVE 2ULL | |
1169 | #define BNDCFG_BDIR_MASK TARGET_PAGE_MASK | |
1170 | ||
e2542fe2 | 1171 | #ifdef HOST_WORDS_BIGENDIAN |
f23a9db6 EH |
1172 | #define ZMM_B(n) _b_ZMMReg[63 - (n)] |
1173 | #define ZMM_W(n) _w_ZMMReg[31 - (n)] | |
1174 | #define ZMM_L(n) _l_ZMMReg[15 - (n)] | |
1175 | #define ZMM_S(n) _s_ZMMReg[15 - (n)] | |
1176 | #define ZMM_Q(n) _q_ZMMReg[7 - (n)] | |
1177 | #define ZMM_D(n) _d_ZMMReg[7 - (n)] | |
1178 | ||
1179 | #define MMX_B(n) _b_MMXReg[7 - (n)] | |
1180 | #define MMX_W(n) _w_MMXReg[3 - (n)] | |
1181 | #define MMX_L(n) _l_MMXReg[1 - (n)] | |
1182 | #define MMX_S(n) _s_MMXReg[1 - (n)] | |
826461bb | 1183 | #else |
f23a9db6 EH |
1184 | #define ZMM_B(n) _b_ZMMReg[n] |
1185 | #define ZMM_W(n) _w_ZMMReg[n] | |
1186 | #define ZMM_L(n) _l_ZMMReg[n] | |
1187 | #define ZMM_S(n) _s_ZMMReg[n] | |
1188 | #define ZMM_Q(n) _q_ZMMReg[n] | |
1189 | #define ZMM_D(n) _d_ZMMReg[n] | |
1190 | ||
1191 | #define MMX_B(n) _b_MMXReg[n] | |
1192 | #define MMX_W(n) _w_MMXReg[n] | |
1193 | #define MMX_L(n) _l_MMXReg[n] | |
1194 | #define MMX_S(n) _s_MMXReg[n] | |
826461bb | 1195 | #endif |
f23a9db6 | 1196 | #define MMX_Q(n) _q_MMXReg[n] |
826461bb | 1197 | |
acc68836 | 1198 | typedef union { |
c31da136 | 1199 | floatx80 d __attribute__((aligned(16))); |
acc68836 JQ |
1200 | MMXReg mmx; |
1201 | } FPReg; | |
1202 | ||
c1a54d57 JQ |
1203 | typedef struct { |
1204 | uint64_t base; | |
1205 | uint64_t mask; | |
1206 | } MTRRVar; | |
1207 | ||
5f30fa18 JK |
1208 | #define CPU_NB_REGS64 16 |
1209 | #define CPU_NB_REGS32 8 | |
1210 | ||
14ce26e7 | 1211 | #ifdef TARGET_X86_64 |
5f30fa18 | 1212 | #define CPU_NB_REGS CPU_NB_REGS64 |
14ce26e7 | 1213 | #else |
5f30fa18 | 1214 | #define CPU_NB_REGS CPU_NB_REGS32 |
14ce26e7 FB |
1215 | #endif |
1216 | ||
0d894367 PB |
1217 | #define MAX_FIXED_COUNTERS 3 |
1218 | #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0) | |
1219 | ||
2066d095 | 1220 | #define TARGET_INSN_START_EXTRA_WORDS 1 |
6ebbf390 | 1221 | |
9aecd6f8 CP |
1222 | #define NB_OPMASK_REGS 8 |
1223 | ||
d9c84f19 IM |
1224 | /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish |
1225 | * that APIC ID hasn't been set yet | |
1226 | */ | |
1227 | #define UNASSIGNED_APIC_ID 0xFFFFFFFF | |
1228 | ||
b503717d EH |
1229 | typedef union X86LegacyXSaveArea { |
1230 | struct { | |
1231 | uint16_t fcw; | |
1232 | uint16_t fsw; | |
1233 | uint8_t ftw; | |
1234 | uint8_t reserved; | |
1235 | uint16_t fpop; | |
1236 | uint64_t fpip; | |
1237 | uint64_t fpdp; | |
1238 | uint32_t mxcsr; | |
1239 | uint32_t mxcsr_mask; | |
1240 | FPReg fpregs[8]; | |
1241 | uint8_t xmm_regs[16][16]; | |
1242 | }; | |
1243 | uint8_t data[512]; | |
1244 | } X86LegacyXSaveArea; | |
1245 | ||
1246 | typedef struct X86XSaveHeader { | |
1247 | uint64_t xstate_bv; | |
1248 | uint64_t xcomp_bv; | |
3f32bd21 RH |
1249 | uint64_t reserve0; |
1250 | uint8_t reserved[40]; | |
b503717d EH |
1251 | } X86XSaveHeader; |
1252 | ||
1253 | /* Ext. save area 2: AVX State */ | |
1254 | typedef struct XSaveAVX { | |
1255 | uint8_t ymmh[16][16]; | |
1256 | } XSaveAVX; | |
1257 | ||
1258 | /* Ext. save area 3: BNDREG */ | |
1259 | typedef struct XSaveBNDREG { | |
1260 | BNDReg bnd_regs[4]; | |
1261 | } XSaveBNDREG; | |
1262 | ||
1263 | /* Ext. save area 4: BNDCSR */ | |
1264 | typedef union XSaveBNDCSR { | |
1265 | BNDCSReg bndcsr; | |
1266 | uint8_t data[64]; | |
1267 | } XSaveBNDCSR; | |
1268 | ||
1269 | /* Ext. save area 5: Opmask */ | |
1270 | typedef struct XSaveOpmask { | |
1271 | uint64_t opmask_regs[NB_OPMASK_REGS]; | |
1272 | } XSaveOpmask; | |
1273 | ||
1274 | /* Ext. save area 6: ZMM_Hi256 */ | |
1275 | typedef struct XSaveZMM_Hi256 { | |
1276 | uint8_t zmm_hi256[16][32]; | |
1277 | } XSaveZMM_Hi256; | |
1278 | ||
1279 | /* Ext. save area 7: Hi16_ZMM */ | |
1280 | typedef struct XSaveHi16_ZMM { | |
1281 | uint8_t hi16_zmm[16][64]; | |
1282 | } XSaveHi16_ZMM; | |
1283 | ||
1284 | /* Ext. save area 9: PKRU state */ | |
1285 | typedef struct XSavePKRU { | |
1286 | uint32_t pkru; | |
1287 | uint32_t padding; | |
1288 | } XSavePKRU; | |
1289 | ||
1290 | typedef struct X86XSaveArea { | |
1291 | X86LegacyXSaveArea legacy; | |
1292 | X86XSaveHeader header; | |
1293 | ||
1294 | /* Extended save areas: */ | |
1295 | ||
1296 | /* AVX State: */ | |
1297 | XSaveAVX avx_state; | |
1298 | uint8_t padding[960 - 576 - sizeof(XSaveAVX)]; | |
1299 | /* MPX State: */ | |
1300 | XSaveBNDREG bndreg_state; | |
1301 | XSaveBNDCSR bndcsr_state; | |
1302 | /* AVX-512 State: */ | |
1303 | XSaveOpmask opmask_state; | |
1304 | XSaveZMM_Hi256 zmm_hi256_state; | |
1305 | XSaveHi16_ZMM hi16_zmm_state; | |
1306 | /* PKRU State: */ | |
1307 | XSavePKRU pkru_state; | |
1308 | } X86XSaveArea; | |
1309 | ||
1310 | QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != 0x240); | |
1311 | QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100); | |
1312 | QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) != 0x3c0); | |
1313 | QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40); | |
1314 | QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) != 0x400); | |
1315 | QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40); | |
1316 | QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) != 0x440); | |
1317 | QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40); | |
1318 | QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != 0x480); | |
1319 | QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200); | |
1320 | QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != 0x680); | |
1321 | QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400); | |
1322 | QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != 0xA80); | |
1323 | QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8); | |
1324 | ||
d362e757 JK |
1325 | typedef enum TPRAccess { |
1326 | TPR_ACCESS_READ, | |
1327 | TPR_ACCESS_WRITE, | |
1328 | } TPRAccess; | |
1329 | ||
7e3482f8 EH |
1330 | /* Cache information data structures: */ |
1331 | ||
1332 | enum CacheType { | |
5f00335a EH |
1333 | DATA_CACHE, |
1334 | INSTRUCTION_CACHE, | |
7e3482f8 EH |
1335 | UNIFIED_CACHE |
1336 | }; | |
1337 | ||
1338 | typedef struct CPUCacheInfo { | |
1339 | enum CacheType type; | |
1340 | uint8_t level; | |
1341 | /* Size in bytes */ | |
1342 | uint32_t size; | |
1343 | /* Line size, in bytes */ | |
1344 | uint16_t line_size; | |
1345 | /* | |
1346 | * Associativity. | |
1347 | * Note: representation of fully-associative caches is not implemented | |
1348 | */ | |
1349 | uint8_t associativity; | |
1350 | /* Physical line partitions. CPUID[0x8000001D].EBX, CPUID[4].EBX */ | |
1351 | uint8_t partitions; | |
1352 | /* Number of sets. CPUID[0x8000001D].ECX, CPUID[4].ECX */ | |
1353 | uint32_t sets; | |
1354 | /* | |
1355 | * Lines per tag. | |
1356 | * AMD-specific: CPUID[0x80000005], CPUID[0x80000006]. | |
1357 | * (Is this synonym to @partitions?) | |
1358 | */ | |
1359 | uint8_t lines_per_tag; | |
1360 | ||
1361 | /* Self-initializing cache */ | |
1362 | bool self_init; | |
1363 | /* | |
1364 | * WBINVD/INVD is not guaranteed to act upon lower level caches of | |
1365 | * non-originating threads sharing this cache. | |
1366 | * CPUID[4].EDX[bit 0], CPUID[0x8000001D].EDX[bit 0] | |
1367 | */ | |
1368 | bool no_invd_sharing; | |
1369 | /* | |
1370 | * Cache is inclusive of lower cache levels. | |
1371 | * CPUID[4].EDX[bit 1], CPUID[0x8000001D].EDX[bit 1]. | |
1372 | */ | |
1373 | bool inclusive; | |
1374 | /* | |
1375 | * A complex function is used to index the cache, potentially using all | |
1376 | * address bits. CPUID[4].EDX[bit 2]. | |
1377 | */ | |
1378 | bool complex_indexing; | |
1379 | } CPUCacheInfo; | |
1380 | ||
1381 | ||
6aaeb054 | 1382 | typedef struct CPUCaches { |
a9f27ea9 EH |
1383 | CPUCacheInfo *l1d_cache; |
1384 | CPUCacheInfo *l1i_cache; | |
1385 | CPUCacheInfo *l2_cache; | |
1386 | CPUCacheInfo *l3_cache; | |
6aaeb054 | 1387 | } CPUCaches; |
7e3482f8 | 1388 | |
577f02b8 RB |
1389 | typedef struct HVFX86LazyFlags { |
1390 | target_ulong result; | |
1391 | target_ulong auxbits; | |
1392 | } HVFX86LazyFlags; | |
1393 | ||
2c0262af FB |
1394 | typedef struct CPUX86State { |
1395 | /* standard registers */ | |
14ce26e7 FB |
1396 | target_ulong regs[CPU_NB_REGS]; |
1397 | target_ulong eip; | |
1398 | target_ulong eflags; /* eflags register. During CPU emulation, CC | |
2c0262af FB |
1399 | flags and DF are set to zero because they are |
1400 | stored elsewhere */ | |
1401 | ||
1402 | /* emulator internal eflags handling */ | |
14ce26e7 | 1403 | target_ulong cc_dst; |
988c3eb0 RH |
1404 | target_ulong cc_src; |
1405 | target_ulong cc_src2; | |
2c0262af FB |
1406 | uint32_t cc_op; |
1407 | int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */ | |
db620f46 FB |
1408 | uint32_t hflags; /* TB flags, see HF_xxx constants. These flags |
1409 | are known at translation time. */ | |
1410 | uint32_t hflags2; /* various other flags, see HF2_xxx constants. */ | |
2c0262af | 1411 | |
9df217a3 FB |
1412 | /* segments */ |
1413 | SegmentCache segs[6]; /* selector values */ | |
1414 | SegmentCache ldt; | |
1415 | SegmentCache tr; | |
1416 | SegmentCache gdt; /* only base and limit are used */ | |
1417 | SegmentCache idt; /* only base and limit are used */ | |
1418 | ||
db620f46 | 1419 | target_ulong cr[5]; /* NOTE: cr1 is unused */ |
5ee0ffaa | 1420 | int32_t a20_mask; |
9df217a3 | 1421 | |
05e7e819 PB |
1422 | BNDReg bnd_regs[4]; |
1423 | BNDCSReg bndcs_regs; | |
1424 | uint64_t msr_bndcfgs; | |
2188cc52 | 1425 | uint64_t efer; |
05e7e819 | 1426 | |
43175fa9 PB |
1427 | /* Beginning of state preserved by INIT (dummy marker). */ |
1428 | struct {} start_init_save; | |
1429 | ||
2c0262af FB |
1430 | /* FPU state */ |
1431 | unsigned int fpstt; /* top of stack index */ | |
67b8f419 | 1432 | uint16_t fpus; |
eb831623 | 1433 | uint16_t fpuc; |
2c0262af | 1434 | uint8_t fptags[8]; /* 0 = valid, 1 = empty */ |
acc68836 | 1435 | FPReg fpregs[8]; |
42cc8fa6 JK |
1436 | /* KVM-only so far */ |
1437 | uint16_t fpop; | |
1438 | uint64_t fpip; | |
1439 | uint64_t fpdp; | |
2c0262af FB |
1440 | |
1441 | /* emulator internal variables */ | |
7a0e1f41 | 1442 | float_status fp_status; |
c31da136 | 1443 | floatx80 ft0; |
3b46e624 | 1444 | |
a35f3ec7 | 1445 | float_status mmx_status; /* for 3DNow! float ops */ |
7a0e1f41 | 1446 | float_status sse_status; |
664e0f19 | 1447 | uint32_t mxcsr; |
fa451874 EH |
1448 | ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32]; |
1449 | ZMMReg xmm_t0; | |
664e0f19 | 1450 | MMXReg mmx_t0; |
14ce26e7 | 1451 | |
c97d6d2c SAGDR |
1452 | XMMReg ymmh_regs[CPU_NB_REGS]; |
1453 | ||
9aecd6f8 | 1454 | uint64_t opmask_regs[NB_OPMASK_REGS]; |
c97d6d2c SAGDR |
1455 | YMMReg zmmh_regs[CPU_NB_REGS]; |
1456 | ZMMReg hi16_zmm_regs[CPU_NB_REGS]; | |
9aecd6f8 | 1457 | |
2c0262af FB |
1458 | /* sysenter registers */ |
1459 | uint32_t sysenter_cs; | |
2436b61a AZ |
1460 | target_ulong sysenter_esp; |
1461 | target_ulong sysenter_eip; | |
8d9bfc2b | 1462 | uint64_t star; |
0573fbfc | 1463 | |
5cc1d1e6 | 1464 | uint64_t vm_hsave; |
0573fbfc | 1465 | |
14ce26e7 | 1466 | #ifdef TARGET_X86_64 |
14ce26e7 FB |
1467 | target_ulong lstar; |
1468 | target_ulong cstar; | |
1469 | target_ulong fmask; | |
1470 | target_ulong kernelgsbase; | |
1471 | #endif | |
58fe2f10 | 1472 | |
7ba1e619 | 1473 | uint64_t tsc; |
f28558d3 | 1474 | uint64_t tsc_adjust; |
aa82ba54 | 1475 | uint64_t tsc_deadline; |
7616f1c2 PB |
1476 | uint64_t tsc_aux; |
1477 | ||
1478 | uint64_t xcr0; | |
7ba1e619 | 1479 | |
18559232 | 1480 | uint64_t mcg_status; |
21e87c46 | 1481 | uint64_t msr_ia32_misc_enable; |
0779caeb | 1482 | uint64_t msr_ia32_feature_control; |
18559232 | 1483 | |
0d894367 PB |
1484 | uint64_t msr_fixed_ctr_ctrl; |
1485 | uint64_t msr_global_ctrl; | |
1486 | uint64_t msr_global_status; | |
1487 | uint64_t msr_global_ovf_ctrl; | |
1488 | uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS]; | |
1489 | uint64_t msr_gp_counters[MAX_GP_COUNTERS]; | |
1490 | uint64_t msr_gp_evtsel[MAX_GP_COUNTERS]; | |
43175fa9 PB |
1491 | |
1492 | uint64_t pat; | |
1493 | uint32_t smbase; | |
e13713db | 1494 | uint64_t msr_smi_count; |
43175fa9 | 1495 | |
7616f1c2 | 1496 | uint32_t pkru; |
e7e7bdab | 1497 | uint32_t pkrs; |
2a9758c5 | 1498 | uint32_t tsx_ctrl; |
7616f1c2 | 1499 | |
a33a2cfe | 1500 | uint64_t spec_ctrl; |
cfeea0c0 | 1501 | uint64_t virt_ssbd; |
a33a2cfe | 1502 | |
43175fa9 PB |
1503 | /* End of state preserved by INIT (dummy marker). */ |
1504 | struct {} end_init_save; | |
1505 | ||
1506 | uint64_t system_time_msr; | |
1507 | uint64_t wall_clock_msr; | |
1508 | uint64_t steal_time_msr; | |
1509 | uint64_t async_pf_en_msr; | |
db5daafa | 1510 | uint64_t async_pf_int_msr; |
43175fa9 | 1511 | uint64_t pv_eoi_en_msr; |
d645e132 | 1512 | uint64_t poll_control_msr; |
43175fa9 | 1513 | |
da1cc323 | 1514 | /* Partition-wide HV MSRs, will be updated only on the first vcpu */ |
1c90ef26 VR |
1515 | uint64_t msr_hv_hypercall; |
1516 | uint64_t msr_hv_guest_os_id; | |
48a5f3bc | 1517 | uint64_t msr_hv_tsc; |
da1cc323 EY |
1518 | |
1519 | /* Per-VCPU HV MSRs */ | |
1520 | uint64_t msr_hv_vapic; | |
5e953812 | 1521 | uint64_t msr_hv_crash_params[HV_CRASH_PARAMS]; |
46eb8f98 | 1522 | uint64_t msr_hv_runtime; |
866eea9a | 1523 | uint64_t msr_hv_synic_control; |
866eea9a AS |
1524 | uint64_t msr_hv_synic_evt_page; |
1525 | uint64_t msr_hv_synic_msg_page; | |
5e953812 RK |
1526 | uint64_t msr_hv_synic_sint[HV_SINT_COUNT]; |
1527 | uint64_t msr_hv_stimer_config[HV_STIMER_COUNT]; | |
1528 | uint64_t msr_hv_stimer_count[HV_STIMER_COUNT]; | |
ba6a4fd9 VK |
1529 | uint64_t msr_hv_reenlightenment_control; |
1530 | uint64_t msr_hv_tsc_emulation_control; | |
1531 | uint64_t msr_hv_tsc_emulation_status; | |
18559232 | 1532 | |
b77146e9 CP |
1533 | uint64_t msr_rtit_ctrl; |
1534 | uint64_t msr_rtit_status; | |
1535 | uint64_t msr_rtit_output_base; | |
1536 | uint64_t msr_rtit_output_mask; | |
1537 | uint64_t msr_rtit_cr3_match; | |
1538 | uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS]; | |
1539 | ||
2c0262af | 1540 | /* exception/interrupt handling */ |
2c0262af FB |
1541 | int error_code; |
1542 | int exception_is_int; | |
826461bb | 1543 | target_ulong exception_next_eip; |
d0052339 | 1544 | target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */ |
01df040b | 1545 | union { |
f0c3c505 | 1546 | struct CPUBreakpoint *cpu_breakpoint[4]; |
ff4700b0 | 1547 | struct CPUWatchpoint *cpu_watchpoint[4]; |
01df040b | 1548 | }; /* break/watchpoints for dr[0..3] */ |
678dde13 | 1549 | int old_exception; /* exception in flight */ |
2c0262af | 1550 | |
43175fa9 PB |
1551 | uint64_t vm_vmcb; |
1552 | uint64_t tsc_offset; | |
1553 | uint64_t intercept; | |
1554 | uint16_t intercept_cr_read; | |
1555 | uint16_t intercept_cr_write; | |
1556 | uint16_t intercept_dr_read; | |
1557 | uint16_t intercept_dr_write; | |
1558 | uint32_t intercept_exceptions; | |
fe441054 JK |
1559 | uint64_t nested_cr3; |
1560 | uint32_t nested_pg_mode; | |
43175fa9 PB |
1561 | uint8_t v_tpr; |
1562 | ||
d8f771d9 JK |
1563 | /* KVM states, automatically cleared on reset */ |
1564 | uint8_t nmi_injected; | |
1565 | uint8_t nmi_pending; | |
1566 | ||
fe441054 JK |
1567 | uintptr_t retaddr; |
1568 | ||
1f5c00cf AB |
1569 | /* Fields up to this point are cleared by a CPU reset */ |
1570 | struct {} end_reset_fields; | |
1571 | ||
e8b5fae5 | 1572 | /* Fields after this point are preserved across CPU reset. */ |
ebda377f | 1573 | |
14ce26e7 | 1574 | /* processor features (e.g. for CPUID insn) */ |
80db491d JL |
1575 | /* Minimum cpuid leaf 7 value */ |
1576 | uint32_t cpuid_level_func7; | |
1577 | /* Actual cpuid leaf 7 value */ | |
1578 | uint32_t cpuid_min_level_func7; | |
c39c0edf EH |
1579 | /* Minimum level/xlevel/xlevel2, based on CPU model + features */ |
1580 | uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2; | |
1581 | /* Maximum level/xlevel/xlevel2 value for auto-assignment: */ | |
1582 | uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2; | |
1583 | /* Actual level/xlevel/xlevel2 value: */ | |
1584 | uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2; | |
14ce26e7 FB |
1585 | uint32_t cpuid_vendor1; |
1586 | uint32_t cpuid_vendor2; | |
1587 | uint32_t cpuid_vendor3; | |
1588 | uint32_t cpuid_version; | |
0514ef2f | 1589 | FeatureWordArray features; |
d4a606b3 EH |
1590 | /* Features that were explicitly enabled/disabled */ |
1591 | FeatureWordArray user_features; | |
8d9bfc2b | 1592 | uint32_t cpuid_model[12]; |
a9f27ea9 EH |
1593 | /* Cache information for CPUID. When legacy-cache=on, the cache data |
1594 | * on each CPUID leaf will be different, because we keep compatibility | |
1595 | * with old QEMU versions. | |
1596 | */ | |
1597 | CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd; | |
3b46e624 | 1598 | |
165d9b82 AL |
1599 | /* MTRRs */ |
1600 | uint64_t mtrr_fixed[11]; | |
1601 | uint64_t mtrr_deftype; | |
d8b5c67b | 1602 | MTRRVar mtrr_var[MSR_MTRRcap_VCNT]; |
165d9b82 | 1603 | |
7ba1e619 | 1604 | /* For KVM */ |
f8d926e9 | 1605 | uint32_t mp_state; |
fd13f23b | 1606 | int32_t exception_nr; |
0e607a80 | 1607 | int32_t interrupt_injected; |
a0fb002c | 1608 | uint8_t soft_interrupt; |
fd13f23b LA |
1609 | uint8_t exception_pending; |
1610 | uint8_t exception_injected; | |
a0fb002c | 1611 | uint8_t has_error_code; |
fd13f23b LA |
1612 | uint8_t exception_has_payload; |
1613 | uint64_t exception_payload; | |
c97d6d2c | 1614 | uint32_t ins_len; |
a0fb002c | 1615 | uint32_t sipi_vector; |
b8cc45d6 | 1616 | bool tsc_valid; |
06ef227e | 1617 | int64_t tsc_khz; |
36f96c4b | 1618 | int64_t user_tsc_khz; /* for sanity check only */ |
73b994f6 | 1619 | uint64_t apic_bus_freq; |
5b8063c4 LA |
1620 | #if defined(CONFIG_KVM) || defined(CONFIG_HVF) |
1621 | void *xsave_buf; | |
1622 | #endif | |
ebbfef2f LA |
1623 | #if defined(CONFIG_KVM) |
1624 | struct kvm_nested_state *nested_state; | |
1625 | #endif | |
c97d6d2c | 1626 | #if defined(CONFIG_HVF) |
577f02b8 | 1627 | HVFX86LazyFlags hvf_lflags; |
fe76b09c | 1628 | void *hvf_mmio_buf; |
c97d6d2c | 1629 | #endif |
fabacc0f | 1630 | |
ac6c4120 | 1631 | uint64_t mcg_cap; |
ac6c4120 | 1632 | uint64_t mcg_ctl; |
87f8b626 | 1633 | uint64_t mcg_ext_ctl; |
ac6c4120 | 1634 | uint64_t mce_banks[MCE_BANKS_DEF*4]; |
7616f1c2 | 1635 | uint64_t xstate_bv; |
5a2d0e57 AJ |
1636 | |
1637 | /* vmstate */ | |
1638 | uint16_t fpus_vmstate; | |
1639 | uint16_t fptag_vmstate; | |
1640 | uint16_t fpregs_format_vmstate; | |
f1665b21 | 1641 | |
18cd2c17 | 1642 | uint64_t xss; |
65087997 | 1643 | uint32_t umwait; |
d362e757 JK |
1644 | |
1645 | TPRAccess tpr_access_type; | |
c26ae610 LX |
1646 | |
1647 | unsigned nr_dies; | |
2c0262af FB |
1648 | } CPUX86State; |
1649 | ||
d71b62a1 EH |
1650 | struct kvm_msrs; |
1651 | ||
4da6f8d9 PB |
1652 | /** |
1653 | * X86CPU: | |
1654 | * @env: #CPUX86State | |
1655 | * @migratable: If set, only migratable flags will be accepted when "enforce" | |
1656 | * mode is used, and only migratable flags will be included in the "host" | |
1657 | * CPU model. | |
1658 | * | |
1659 | * An x86 CPU. | |
1660 | */ | |
1661 | struct X86CPU { | |
1662 | /*< private >*/ | |
1663 | CPUState parent_obj; | |
1664 | /*< public >*/ | |
1665 | ||
5b146dc7 | 1666 | CPUNegativeOffsetState neg; |
4da6f8d9 | 1667 | CPUX86State env; |
2a693142 | 1668 | VMChangeStateEntry *vmsentry; |
4da6f8d9 | 1669 | |
4e45aff3 PB |
1670 | uint64_t ucode_rev; |
1671 | ||
4f2beda4 | 1672 | uint32_t hyperv_spinlock_attempts; |
08856771 | 1673 | char *hyperv_vendor; |
9b4cf107 | 1674 | bool hyperv_synic_kvm_only; |
2d384d7c | 1675 | uint64_t hyperv_features; |
e48ddcc6 | 1676 | bool hyperv_passthrough; |
30d6ff66 | 1677 | OnOffAuto hyperv_no_nonarch_cs; |
08856771 | 1678 | uint32_t hyperv_vendor_id[3]; |
735db465 | 1679 | uint32_t hyperv_interface_id[4]; |
fb7e31aa | 1680 | uint32_t hyperv_version_id[4]; |
23eb5d03 | 1681 | uint32_t hyperv_limits[3]; |
2d384d7c | 1682 | |
4da6f8d9 PB |
1683 | bool check_cpuid; |
1684 | bool enforce_cpuid; | |
dac1deae EH |
1685 | /* |
1686 | * Force features to be enabled even if the host doesn't support them. | |
1687 | * This is dangerous and should be done only for testing CPUID | |
1688 | * compatibility. | |
1689 | */ | |
1690 | bool force_features; | |
4da6f8d9 | 1691 | bool expose_kvm; |
1ce36bfe | 1692 | bool expose_tcg; |
4da6f8d9 | 1693 | bool migratable; |
990e0be2 | 1694 | bool migrate_smi_count; |
44bd8e53 | 1695 | bool max_features; /* Enable all supported features automatically */ |
d9c84f19 | 1696 | uint32_t apic_id; |
4da6f8d9 | 1697 | |
9954a158 PDJ |
1698 | /* Enables publishing of TSC increment and Local APIC bus frequencies to |
1699 | * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */ | |
1700 | bool vmware_cpuid_freq; | |
1701 | ||
4da6f8d9 PB |
1702 | /* if true the CPUID code directly forward host cache leaves to the guest */ |
1703 | bool cache_info_passthrough; | |
1704 | ||
2266d443 MT |
1705 | /* if true the CPUID code directly forwards |
1706 | * host monitor/mwait leaves to the guest */ | |
1707 | struct { | |
1708 | uint32_t eax; | |
1709 | uint32_t ebx; | |
1710 | uint32_t ecx; | |
1711 | uint32_t edx; | |
1712 | } mwait; | |
1713 | ||
4da6f8d9 | 1714 | /* Features that were filtered out because of missing host capabilities */ |
f69ecddb | 1715 | FeatureWordArray filtered_features; |
4da6f8d9 PB |
1716 | |
1717 | /* Enable PMU CPUID bits. This can't be enabled by default yet because | |
1718 | * it doesn't have ABI stability guarantees, as it passes all PMU CPUID | |
1719 | * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel | |
1720 | * capabilities) directly to the guest. | |
1721 | */ | |
1722 | bool enable_pmu; | |
1723 | ||
87f8b626 AR |
1724 | /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is |
1725 | * disabled by default to avoid breaking migration between QEMU with | |
1726 | * different LMCE configurations. | |
1727 | */ | |
1728 | bool enable_lmce; | |
1729 | ||
14c985cf LM |
1730 | /* Compatibility bits for old machine types. |
1731 | * If true present virtual l3 cache for VM, the vcpus in the same virtual | |
1732 | * socket share an virtual l3 cache. | |
1733 | */ | |
1734 | bool enable_l3_cache; | |
1735 | ||
ab8f992e BM |
1736 | /* Compatibility bits for old machine types. |
1737 | * If true present the old cache topology information | |
1738 | */ | |
1739 | bool legacy_cache; | |
1740 | ||
5232d00a RK |
1741 | /* Compatibility bits for old machine types: */ |
1742 | bool enable_cpuid_0xb; | |
1743 | ||
c39c0edf EH |
1744 | /* Enable auto level-increase for all CPUID leaves */ |
1745 | bool full_cpuid_auto_level; | |
1746 | ||
f24c3a79 LK |
1747 | /* Enable auto level-increase for Intel Processor Trace leave */ |
1748 | bool intel_pt_auto_level; | |
1749 | ||
fcc35e7c DDAG |
1750 | /* if true fill the top bits of the MTRR_PHYSMASKn variable range */ |
1751 | bool fill_mtrr_mask; | |
1752 | ||
11f6fee5 DDAG |
1753 | /* if true override the phys_bits value with a value read from the host */ |
1754 | bool host_phys_bits; | |
1755 | ||
258fe08b EH |
1756 | /* if set, limit maximum value for phys_bits when host_phys_bits is true */ |
1757 | uint8_t host_phys_bits_limit; | |
1758 | ||
fc3a1fd7 DDAG |
1759 | /* Stop SMI delivery for migration compatibility with old machines */ |
1760 | bool kvm_no_smi_migration; | |
1761 | ||
af45907a DDAG |
1762 | /* Number of physical address bits supported */ |
1763 | uint32_t phys_bits; | |
1764 | ||
4da6f8d9 PB |
1765 | /* in order to simplify APIC support, we leave this pointer to the |
1766 | user */ | |
1767 | struct DeviceState *apic_state; | |
1768 | struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram; | |
1769 | Notifier machine_done; | |
d71b62a1 EH |
1770 | |
1771 | struct kvm_msrs *kvm_msr_buf; | |
d89c2b8b | 1772 | |
15f8b142 | 1773 | int32_t node_id; /* NUMA node this CPU belongs to */ |
d89c2b8b | 1774 | int32_t socket_id; |
176d2cda | 1775 | int32_t die_id; |
d89c2b8b IM |
1776 | int32_t core_id; |
1777 | int32_t thread_id; | |
6c69dfb6 GA |
1778 | |
1779 | int32_t hv_max_vps; | |
4da6f8d9 PB |
1780 | }; |
1781 | ||
4da6f8d9 PB |
1782 | |
1783 | #ifndef CONFIG_USER_ONLY | |
8a9358cc | 1784 | extern VMStateDescription vmstate_x86_cpu; |
4da6f8d9 PB |
1785 | #endif |
1786 | ||
92d5f1a4 | 1787 | int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request); |
4da6f8d9 PB |
1788 | |
1789 | int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, | |
1790 | int cpuid, void *opaque); | |
1791 | int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, | |
1792 | int cpuid, void *opaque); | |
1793 | int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
1794 | void *opaque); | |
1795 | int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
1796 | void *opaque); | |
1797 | ||
1798 | void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, | |
1799 | Error **errp); | |
1800 | ||
90c84c56 | 1801 | void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags); |
4da6f8d9 | 1802 | |
56f99750 DP |
1803 | hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, |
1804 | MemTxAttrs *attrs); | |
4da6f8d9 | 1805 | |
a010bdbe | 1806 | int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); |
4da6f8d9 PB |
1807 | int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); |
1808 | ||
0442428a | 1809 | void x86_cpu_list(void); |
317ac620 | 1810 | int cpu_x86_support_mca_broadcast(CPUX86State *env); |
b5ec5ce0 | 1811 | |
d720b93d | 1812 | int cpu_get_pic_interrupt(CPUX86State *s); |
2ee73ac3 | 1813 | /* MSDOS compatibility mode FPU exception support */ |
6f529b75 | 1814 | void x86_register_ferr_irq(qemu_irq irq); |
bf13bfab | 1815 | void cpu_set_ignne(void); |
5e76d84e PB |
1816 | /* mpx_helper.c */ |
1817 | void cpu_sync_bndcs_hflags(CPUX86State *env); | |
2c0262af FB |
1818 | |
1819 | /* this function must always be used to load data in the segment | |
1820 | cache: it synchronizes the hflags with the segment cache values */ | |
5fafdf24 | 1821 | static inline void cpu_x86_load_seg_cache(CPUX86State *env, |
c117e5b1 | 1822 | X86Seg seg_reg, unsigned int selector, |
8988ae89 | 1823 | target_ulong base, |
5fafdf24 | 1824 | unsigned int limit, |
2c0262af FB |
1825 | unsigned int flags) |
1826 | { | |
1827 | SegmentCache *sc; | |
1828 | unsigned int new_hflags; | |
3b46e624 | 1829 | |
2c0262af FB |
1830 | sc = &env->segs[seg_reg]; |
1831 | sc->selector = selector; | |
1832 | sc->base = base; | |
1833 | sc->limit = limit; | |
1834 | sc->flags = flags; | |
1835 | ||
1836 | /* update the hidden flags */ | |
14ce26e7 FB |
1837 | { |
1838 | if (seg_reg == R_CS) { | |
1839 | #ifdef TARGET_X86_64 | |
1840 | if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) { | |
1841 | /* long mode */ | |
1842 | env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; | |
1843 | env->hflags &= ~(HF_ADDSEG_MASK); | |
5fafdf24 | 1844 | } else |
14ce26e7 FB |
1845 | #endif |
1846 | { | |
1847 | /* legacy / compatibility case */ | |
1848 | new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) | |
1849 | >> (DESC_B_SHIFT - HF_CS32_SHIFT); | |
1850 | env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | | |
1851 | new_hflags; | |
1852 | } | |
7125c937 PB |
1853 | } |
1854 | if (seg_reg == R_SS) { | |
1855 | int cpl = (flags >> DESC_DPL_SHIFT) & 3; | |
7848c8d1 KC |
1856 | #if HF_CPL_MASK != 3 |
1857 | #error HF_CPL_MASK is hardcoded | |
1858 | #endif | |
1859 | env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl; | |
5e76d84e PB |
1860 | /* Possibly switch between BNDCFGS and BNDCFGU */ |
1861 | cpu_sync_bndcs_hflags(env); | |
14ce26e7 FB |
1862 | } |
1863 | new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) | |
1864 | >> (DESC_B_SHIFT - HF_SS32_SHIFT); | |
1865 | if (env->hflags & HF_CS64_MASK) { | |
1866 | /* zero base assumed for DS, ES and SS in long mode */ | |
5fafdf24 | 1867 | } else if (!(env->cr[0] & CR0_PE_MASK) || |
735a8fd3 FB |
1868 | (env->eflags & VM_MASK) || |
1869 | !(env->hflags & HF_CS32_MASK)) { | |
14ce26e7 FB |
1870 | /* XXX: try to avoid this test. The problem comes from the |
1871 | fact that is real mode or vm86 mode we only modify the | |
1872 | 'base' and 'selector' fields of the segment cache to go | |
1873 | faster. A solution may be to force addseg to one in | |
1874 | translate-i386.c. */ | |
1875 | new_hflags |= HF_ADDSEG_MASK; | |
1876 | } else { | |
5fafdf24 | 1877 | new_hflags |= ((env->segs[R_DS].base | |
735a8fd3 | 1878 | env->segs[R_ES].base | |
5fafdf24 | 1879 | env->segs[R_SS].base) != 0) << |
14ce26e7 FB |
1880 | HF_ADDSEG_SHIFT; |
1881 | } | |
5fafdf24 | 1882 | env->hflags = (env->hflags & |
14ce26e7 | 1883 | ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; |
2c0262af | 1884 | } |
2c0262af FB |
1885 | } |
1886 | ||
e9f9d6b1 | 1887 | static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu, |
e6a33e45 | 1888 | uint8_t sipi_vector) |
0e26b7b8 | 1889 | { |
259186a7 | 1890 | CPUState *cs = CPU(cpu); |
e9f9d6b1 AF |
1891 | CPUX86State *env = &cpu->env; |
1892 | ||
0e26b7b8 BS |
1893 | env->eip = 0; |
1894 | cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8, | |
1895 | sipi_vector << 12, | |
1896 | env->segs[R_CS].limit, | |
1897 | env->segs[R_CS].flags); | |
259186a7 | 1898 | cs->halted = 0; |
0e26b7b8 BS |
1899 | } |
1900 | ||
84273177 JK |
1901 | int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector, |
1902 | target_ulong *base, unsigned int *limit, | |
1903 | unsigned int *flags); | |
1904 | ||
d9957a8b | 1905 | /* op_helper.c */ |
1f1af9fd | 1906 | /* used for debug or cpu save/restore */ |
1f1af9fd | 1907 | |
d9957a8b | 1908 | /* cpu-exec.c */ |
2c0262af FB |
1909 | /* the following helpers are only usable in user mode simulation as |
1910 | they can trigger unexpected exceptions */ | |
c117e5b1 | 1911 | void cpu_x86_load_seg(CPUX86State *s, X86Seg seg_reg, int selector); |
6f12a2a6 FB |
1912 | void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32); |
1913 | void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); | |
1c1df019 PK |
1914 | void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr); |
1915 | void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr); | |
2c0262af FB |
1916 | |
1917 | /* you can call this signal handler from your SIGBUS and SIGSEGV | |
1918 | signal handlers to inform the virtual CPU of exceptions. non zero | |
1919 | is returned if the signal was handled by the virtual CPU. */ | |
5fafdf24 | 1920 | int cpu_x86_signal_handler(int host_signum, void *pinfo, |
2c0262af | 1921 | void *puc); |
d9957a8b | 1922 | |
f4f1110e | 1923 | /* cpu.c */ |
c6dc6f63 AP |
1924 | void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, |
1925 | uint32_t *eax, uint32_t *ebx, | |
1926 | uint32_t *ecx, uint32_t *edx); | |
0e26b7b8 | 1927 | void cpu_clear_apic_feature(CPUX86State *env); |
bb44e0d1 JK |
1928 | void host_cpuid(uint32_t function, uint32_t count, |
1929 | uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx); | |
20271d48 | 1930 | void host_vendor_fms(char *vendor, int *family, int *model, int *stepping); |
c6dc6f63 | 1931 | |
d9957a8b | 1932 | /* helper.c */ |
cc36a7a2 | 1933 | void x86_cpu_set_a20(X86CPU *cpu, int a20_state); |
2c0262af | 1934 | |
b216aa6c | 1935 | #ifndef CONFIG_USER_ONLY |
f8c45c65 PB |
1936 | static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) |
1937 | { | |
1938 | return !!attrs.secure; | |
1939 | } | |
1940 | ||
1941 | static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs) | |
1942 | { | |
1943 | return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs)); | |
1944 | } | |
1945 | ||
b216aa6c PB |
1946 | uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr); |
1947 | uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr); | |
1948 | uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr); | |
1949 | uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr); | |
1950 | void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val); | |
1951 | void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val); | |
1952 | void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val); | |
1953 | void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val); | |
1954 | void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val); | |
1955 | #endif | |
1956 | ||
d9957a8b BS |
1957 | /* will be suppressed */ |
1958 | void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); | |
1959 | void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3); | |
1960 | void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4); | |
93d00d0f | 1961 | void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7); |
d9957a8b | 1962 | |
d9957a8b | 1963 | /* hw/pc.c */ |
d9957a8b | 1964 | uint64_t cpu_get_tsc(CPUX86State *env); |
6fd805e1 | 1965 | |
311ca98d IM |
1966 | #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU |
1967 | #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) | |
0dacec87 | 1968 | #define CPU_RESOLVING_TYPE TYPE_X86_CPU |
311ca98d IM |
1969 | |
1970 | #ifdef TARGET_X86_64 | |
1971 | #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64") | |
1972 | #else | |
1973 | #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32") | |
1974 | #endif | |
1975 | ||
9467d44c | 1976 | #define cpu_signal_handler cpu_x86_signal_handler |
e916cbf8 | 1977 | #define cpu_list x86_cpu_list |
9467d44c | 1978 | |
6ebbf390 | 1979 | /* MMU modes definitions */ |
8a201bd4 | 1980 | #define MMU_KSMAP_IDX 0 |
a9321a4d | 1981 | #define MMU_USER_IDX 1 |
43773ed3 | 1982 | #define MMU_KNOSMAP_IDX 2 |
97ed5ccd | 1983 | static inline int cpu_mmu_index(CPUX86State *env, bool ifetch) |
6ebbf390 | 1984 | { |
a9321a4d | 1985 | return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX : |
f57584dc | 1986 | (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK)) |
8a201bd4 PB |
1987 | ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; |
1988 | } | |
1989 | ||
1990 | static inline int cpu_mmu_index_kernel(CPUX86State *env) | |
1991 | { | |
1992 | return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX : | |
1993 | ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK)) | |
1994 | ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; | |
6ebbf390 JM |
1995 | } |
1996 | ||
988c3eb0 RH |
1997 | #define CC_DST (env->cc_dst) |
1998 | #define CC_SRC (env->cc_src) | |
1999 | #define CC_SRC2 (env->cc_src2) | |
2000 | #define CC_OP (env->cc_op) | |
f081c76c | 2001 | |
4f7c64b3 | 2002 | typedef CPUX86State CPUArchState; |
2161a612 | 2003 | typedef X86CPU ArchCPU; |
4f7c64b3 | 2004 | |
022c62cb | 2005 | #include "exec/cpu-all.h" |
0573fbfc TS |
2006 | #include "svm.h" |
2007 | ||
0e26b7b8 | 2008 | #if !defined(CONFIG_USER_ONLY) |
0d09e41a | 2009 | #include "hw/i386/apic.h" |
0e26b7b8 BS |
2010 | #endif |
2011 | ||
317ac620 | 2012 | static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc, |
89fee74a | 2013 | target_ulong *cs_base, uint32_t *flags) |
6b917547 AL |
2014 | { |
2015 | *cs_base = env->segs[R_CS].base; | |
2016 | *pc = *cs_base + env->eip; | |
a2397807 | 2017 | *flags = env->hflags | |
a9321a4d | 2018 | (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)); |
6b917547 AL |
2019 | } |
2020 | ||
232fc23b AF |
2021 | void do_cpu_init(X86CPU *cpu); |
2022 | void do_cpu_sipi(X86CPU *cpu); | |
2fa11da0 | 2023 | |
747461c7 JK |
2024 | #define MCE_INJECT_BROADCAST 1 |
2025 | #define MCE_INJECT_UNCOND_AO 2 | |
2026 | ||
8c5cf3b6 | 2027 | void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank, |
316378e4 | 2028 | uint64_t status, uint64_t mcg_status, uint64_t addr, |
747461c7 | 2029 | uint64_t misc, int flags); |
2fa11da0 | 2030 | |
5918fffb BS |
2031 | uint32_t cpu_cc_compute_all(CPUX86State *env1, int op); |
2032 | ||
2033 | static inline uint32_t cpu_compute_eflags(CPUX86State *env) | |
2034 | { | |
79c664f6 YZ |
2035 | uint32_t eflags = env->eflags; |
2036 | if (tcg_enabled()) { | |
2037 | eflags |= cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK); | |
2038 | } | |
2039 | return eflags; | |
5918fffb BS |
2040 | } |
2041 | ||
5918fffb BS |
2042 | |
2043 | /* load efer and update the corresponding hflags. XXX: do consistency | |
2044 | checks with cpuid bits? */ | |
2045 | static inline void cpu_load_efer(CPUX86State *env, uint64_t val) | |
2046 | { | |
2047 | env->efer = val; | |
2048 | env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK); | |
2049 | if (env->efer & MSR_EFER_LMA) { | |
2050 | env->hflags |= HF_LMA_MASK; | |
2051 | } | |
2052 | if (env->efer & MSR_EFER_SVME) { | |
2053 | env->hflags |= HF_SVME_MASK; | |
2054 | } | |
2055 | } | |
2056 | ||
f794aa4a PB |
2057 | static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env) |
2058 | { | |
2059 | return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 }); | |
2060 | } | |
2061 | ||
c8bc83a4 PB |
2062 | static inline int32_t x86_get_a20_mask(CPUX86State *env) |
2063 | { | |
2064 | if (env->hflags & HF_SMM_MASK) { | |
2065 | return -1; | |
2066 | } else { | |
2067 | return env->a20_mask; | |
2068 | } | |
2069 | } | |
2070 | ||
18ab37ba LA |
2071 | static inline bool cpu_has_vmx(CPUX86State *env) |
2072 | { | |
2073 | return env->features[FEAT_1_ECX] & CPUID_EXT_VMX; | |
2074 | } | |
2075 | ||
b16c0e20 PB |
2076 | static inline bool cpu_has_svm(CPUX86State *env) |
2077 | { | |
2078 | return env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM; | |
2079 | } | |
2080 | ||
79a197ab LA |
2081 | /* |
2082 | * In order for a vCPU to enter VMX operation it must have CR4.VMXE set. | |
2083 | * Since it was set, CR4.VMXE must remain set as long as vCPU is in | |
2084 | * VMX operation. This is because CR4.VMXE is one of the bits set | |
2085 | * in MSR_IA32_VMX_CR4_FIXED1. | |
2086 | * | |
2087 | * There is one exception to above statement when vCPU enters SMM mode. | |
2088 | * When a vCPU enters SMM mode, it temporarily exit VMX operation and | |
2089 | * may also reset CR4.VMXE during execution in SMM mode. | |
2090 | * When vCPU exits SMM mode, vCPU state is restored to be in VMX operation | |
2091 | * and CR4.VMXE is restored to it's original value of being set. | |
2092 | * | |
2093 | * Therefore, when vCPU is not in SMM mode, we can infer whether | |
2094 | * VMX is being used by examining CR4.VMXE. Otherwise, we cannot | |
2095 | * know for certain. | |
2096 | */ | |
2097 | static inline bool cpu_vmx_maybe_enabled(CPUX86State *env) | |
2098 | { | |
2099 | return cpu_has_vmx(env) && | |
2100 | ((env->cr[4] & CR4_VMXE_MASK) || (env->hflags & HF_SMM_MASK)); | |
2101 | } | |
2102 | ||
4e47e39a | 2103 | /* fpu_helper.c */ |
1d8ad165 YZ |
2104 | void update_fp_status(CPUX86State *env); |
2105 | void update_mxcsr_status(CPUX86State *env); | |
418b0f93 | 2106 | void update_mxcsr_from_sse_status(CPUX86State *env); |
1d8ad165 YZ |
2107 | |
2108 | static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr) | |
2109 | { | |
2110 | env->mxcsr = mxcsr; | |
2111 | if (tcg_enabled()) { | |
2112 | update_mxcsr_status(env); | |
2113 | } | |
2114 | } | |
2115 | ||
2116 | static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc) | |
2117 | { | |
2118 | env->fpuc = fpuc; | |
2119 | if (tcg_enabled()) { | |
2120 | update_fp_status(env); | |
2121 | } | |
2122 | } | |
4e47e39a | 2123 | |
677ef623 FK |
2124 | /* mem_helper.c */ |
2125 | void helper_lock_init(void); | |
2126 | ||
6bada5e8 BS |
2127 | /* svm_helper.c */ |
2128 | void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, | |
65c9d60a | 2129 | uint64_t param, uintptr_t retaddr); |
d613f8cc | 2130 | /* apic.c */ |
317ac620 | 2131 | void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); |
d613f8cc PB |
2132 | void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, |
2133 | TPRAccess access); | |
2134 | ||
d362e757 | 2135 | |
5114e842 EH |
2136 | /* Change the value of a KVM-specific default |
2137 | * | |
2138 | * If value is NULL, no default will be set and the original | |
2139 | * value from the CPU model table will be kept. | |
2140 | * | |
cb8d4c8f | 2141 | * It is valid to call this function only for properties that |
5114e842 EH |
2142 | * are already present in the kvm_default_props table. |
2143 | */ | |
2144 | void x86_cpu_change_kvm_default(const char *prop, const char *value); | |
8fb4f821 | 2145 | |
dcafd1ef EH |
2146 | /* Special values for X86CPUVersion: */ |
2147 | ||
2148 | /* Resolve to latest CPU version */ | |
2149 | #define CPU_VERSION_LATEST -1 | |
2150 | ||
0788a56b EH |
2151 | /* |
2152 | * Resolve to version defined by current machine type. | |
2153 | * See x86_cpu_set_default_version() | |
2154 | */ | |
2155 | #define CPU_VERSION_AUTO -2 | |
2156 | ||
dcafd1ef EH |
2157 | /* Don't resolve to any versioned CPU models, like old QEMU versions */ |
2158 | #define CPU_VERSION_LEGACY 0 | |
2159 | ||
2160 | typedef int X86CPUVersion; | |
2161 | ||
0788a56b EH |
2162 | /* |
2163 | * Set default CPU model version for CPU models having | |
2164 | * version == CPU_VERSION_AUTO. | |
2165 | */ | |
2166 | void x86_cpu_set_default_version(X86CPUVersion version); | |
2167 | ||
dab86234 | 2168 | #define APIC_DEFAULT_ADDRESS 0xfee00000 |
baaeda08 | 2169 | #define APIC_SPACE_SIZE 0x100000 |
dab86234 | 2170 | |
0c36af8c | 2171 | /* cpu-dump.c */ |
d3fd9e4b | 2172 | void x86_cpu_dump_local_apic_state(CPUState *cs, int flags); |
1f871d49 | 2173 | |
d613f8cc PB |
2174 | /* cpu.c */ |
2175 | bool cpu_is_bsp(X86CPU *cpu); | |
2176 | ||
86a57621 SAGDR |
2177 | void x86_cpu_xrstor_all_areas(X86CPU *cpu, const X86XSaveArea *buf); |
2178 | void x86_cpu_xsave_all_areas(X86CPU *cpu, X86XSaveArea *buf); | |
35b1b927 TW |
2179 | void x86_update_hflags(CPUX86State* env); |
2180 | ||
2d384d7c VK |
2181 | static inline bool hyperv_feat_enabled(X86CPU *cpu, int feat) |
2182 | { | |
2183 | return !!(cpu->hyperv_features & BIT(feat)); | |
2184 | } | |
2185 | ||
b26491b4 RH |
2186 | #if defined(TARGET_X86_64) && \ |
2187 | defined(CONFIG_USER_ONLY) && \ | |
2188 | defined(CONFIG_LINUX) | |
2189 | # define TARGET_VSYSCALL_PAGE (UINT64_C(-10) << 20) | |
2190 | #endif | |
2191 | ||
07f5a258 | 2192 | #endif /* I386_CPU_H */ |