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Commit | Line | Data |
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e6e5906b PB |
1 | /* |
2 | * m68k virtual CPU header | |
5fafdf24 | 3 | * |
0633879f | 4 | * Copyright (c) 2005-2007 CodeSourcery |
e6e5906b PB |
5 | * Written by Paul Brook |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
d749fb85 | 10 | * version 2.1 of the License, or (at your option) any later version. |
e6e5906b PB |
11 | * |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
d749fb85 | 15 | * Lesser General Public License for more details. |
e6e5906b PB |
16 | * |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
e6e5906b | 19 | */ |
07f5a258 MA |
20 | |
21 | #ifndef M68K_CPU_H | |
22 | #define M68K_CPU_H | |
e6e5906b | 23 | |
022c62cb | 24 | #include "exec/cpu-defs.h" |
69242e7e | 25 | #include "qemu/cpu-float.h" |
a836b8fa | 26 | #include "cpu-qom.h" |
e6e5906b | 27 | |
7ef25cdd LV |
28 | #define OS_BYTE 0 |
29 | #define OS_WORD 1 | |
30 | #define OS_LONG 2 | |
31 | #define OS_SINGLE 3 | |
32 | #define OS_DOUBLE 4 | |
33 | #define OS_EXTENDED 5 | |
34 | #define OS_PACKED 6 | |
f2224f2c | 35 | #define OS_UNSIZED 7 |
7ef25cdd | 36 | |
e6e5906b PB |
37 | #define EXCP_ACCESS 2 /* Access (MMU) error. */ |
38 | #define EXCP_ADDRESS 3 /* Address error. */ | |
39 | #define EXCP_ILLEGAL 4 /* Illegal instruction. */ | |
40 | #define EXCP_DIV0 5 /* Divide by zero */ | |
5beb144e LV |
41 | #define EXCP_CHK 6 /* CHK, CHK2 Instructions */ |
42 | #define EXCP_TRAPCC 7 /* FTRAPcc, TRAPcc, TRAPV Instructions */ | |
e6e5906b PB |
43 | #define EXCP_PRIVILEGE 8 /* Privilege violation. */ |
44 | #define EXCP_TRACE 9 | |
45 | #define EXCP_LINEA 10 /* Unimplemented line-A (MAC) opcode. */ | |
46 | #define EXCP_LINEF 11 /* Unimplemented line-F (FPU) opcode. */ | |
47 | #define EXCP_DEBUGNBP 12 /* Non-breakpoint debug interrupt. */ | |
48 | #define EXCP_DEBEGBP 13 /* Breakpoint debug interrupt. */ | |
49 | #define EXCP_FORMAT 14 /* RTE format error. */ | |
50 | #define EXCP_UNINITIALIZED 15 | |
5beb144e LV |
51 | #define EXCP_SPURIOUS 24 /* Spurious interrupt */ |
52 | #define EXCP_INT_LEVEL_1 25 /* Level 1 Interrupt autovector */ | |
53 | #define EXCP_INT_LEVEL_7 31 /* Level 7 Interrupt autovector */ | |
e6e5906b PB |
54 | #define EXCP_TRAP0 32 /* User trap #0. */ |
55 | #define EXCP_TRAP15 47 /* User trap #15. */ | |
f83311e4 LV |
56 | #define EXCP_FP_BSUN 48 /* Branch Set on Unordered */ |
57 | #define EXCP_FP_INEX 49 /* Inexact result */ | |
58 | #define EXCP_FP_DZ 50 /* Divide by Zero */ | |
59 | #define EXCP_FP_UNFL 51 /* Underflow */ | |
60 | #define EXCP_FP_OPERR 52 /* Operand Error */ | |
61 | #define EXCP_FP_OVFL 53 /* Overflow */ | |
62 | #define EXCP_FP_SNAN 54 /* Signaling Not-A-Number */ | |
63 | #define EXCP_FP_UNIMP 55 /* Unimplemented Data type */ | |
5beb144e LV |
64 | #define EXCP_MMU_CONF 56 /* MMU Configuration Error */ |
65 | #define EXCP_MMU_ILLEGAL 57 /* MMU Illegal Operation Error */ | |
66 | #define EXCP_MMU_ACCESS 58 /* MMU Access Level Violation Error */ | |
e6e5906b | 67 | |
0633879f | 68 | #define EXCP_RTE 0x100 |
a87295e8 | 69 | #define EXCP_HALT_INSN 0x101 |
0633879f | 70 | |
c05c73b0 LV |
71 | #define M68K_DTTR0 0 |
72 | #define M68K_DTTR1 1 | |
73 | #define M68K_ITTR0 2 | |
74 | #define M68K_ITTR1 3 | |
75 | ||
76 | #define M68K_MAX_TTR 2 | |
77 | #define TTR(type, index) ttr[((type & ACCESS_CODE) == ACCESS_CODE) * 2 + index] | |
78 | ||
20a8856e | 79 | #define TARGET_INSN_START_EXTRA_WORDS 1 |
6ebbf390 | 80 | |
f83311e4 LV |
81 | typedef CPU_LDoubleU FPReg; |
82 | ||
1ea4a06a | 83 | typedef struct CPUArchState { |
e6e5906b PB |
84 | uint32_t dregs[8]; |
85 | uint32_t aregs[8]; | |
86 | uint32_t pc; | |
87 | uint32_t sr; | |
88 | ||
7525a9b9 LMP |
89 | /* |
90 | * The 68020/30/40 support two supervisor stacks, ISP and MSP. | |
91 | * The 68000/10, Coldfire, and CPU32 only have USP/SSP. | |
92 | * | |
93 | * The current_sp is stored in aregs[7], the other here. | |
94 | * The USP, SSP, and if used the additional ISP for 68020/30/40. | |
95 | */ | |
20dcee94 | 96 | int current_sp; |
6e22b28e | 97 | uint32_t sp[3]; |
20dcee94 | 98 | |
e6e5906b PB |
99 | /* Condition flags. */ |
100 | uint32_t cc_op; | |
620c6cf6 RH |
101 | uint32_t cc_x; /* always 0/1 */ |
102 | uint32_t cc_n; /* in bit 31 (i.e. negative) */ | |
103 | uint32_t cc_v; /* in bit 31, unused, or computed from cc_n and cc_v */ | |
104 | uint32_t cc_c; /* either 0/1, unused, or computed from cc_n and cc_v */ | |
105 | uint32_t cc_z; /* == 0 or unused */ | |
e6e5906b | 106 | |
f83311e4 LV |
107 | FPReg fregs[8]; |
108 | FPReg fp_result; | |
e6e5906b PB |
109 | uint32_t fpcr; |
110 | uint32_t fpsr; | |
111 | float_status fp_status; | |
112 | ||
acf930aa | 113 | uint64_t mactmp; |
808d77bc LMP |
114 | /* |
115 | * EMAC Hardware deals with 48-bit values composed of one 32-bit and | |
116 | * two 8-bit parts. We store a single 64-bit value and | |
117 | * rearrange/extend this when changing modes. | |
118 | */ | |
acf930aa PB |
119 | uint64_t macc[4]; |
120 | uint32_t macsr; | |
121 | uint32_t mac_mask; | |
122 | ||
e6e5906b PB |
123 | /* MMU status. */ |
124 | struct { | |
ad5a5cf9 RH |
125 | /* |
126 | * Holds the "address" value in between raising an exception | |
127 | * and creation of the exception stack frame. | |
128 | * Used for both Format 7 exceptions (Access, i.e. mmu) | |
129 | * and Format 2 exceptions (chk, div0, trapcc, etc). | |
130 | */ | |
e6e5906b | 131 | uint32_t ar; |
88b2fef6 LV |
132 | uint32_t ssw; |
133 | /* 68040 */ | |
134 | uint16_t tcr; | |
135 | uint32_t urp; | |
136 | uint32_t srp; | |
137 | bool fault; | |
c05c73b0 | 138 | uint32_t ttr[4]; |
e55886c3 | 139 | uint32_t mmusr; |
e6e5906b | 140 | } mmu; |
0633879f PB |
141 | |
142 | /* Control registers. */ | |
143 | uint32_t vbr; | |
144 | uint32_t mbar; | |
145 | uint32_t rambar0; | |
20dcee94 | 146 | uint32_t cacr; |
5fa9f1f2 LV |
147 | uint32_t sfc; |
148 | uint32_t dfc; | |
0633879f | 149 | |
0633879f PB |
150 | int pending_vector; |
151 | int pending_level; | |
e6e5906b | 152 | |
1f5c00cf AB |
153 | /* Fields up to this point are cleared by a CPU reset */ |
154 | struct {} end_reset_fields; | |
155 | ||
f0c3c505 | 156 | /* Fields from here on are preserved across CPU reset. */ |
2dc7bf63 | 157 | uint64_t features; |
e6e5906b PB |
158 | } CPUM68KState; |
159 | ||
808d77bc | 160 | /* |
a836b8fa PB |
161 | * M68kCPU: |
162 | * @env: #CPUM68KState | |
163 | * | |
164 | * A Motorola 68k CPU. | |
165 | */ | |
b36e239e | 166 | struct ArchCPU { |
a836b8fa PB |
167 | /*< private >*/ |
168 | CPUState parent_obj; | |
169 | /*< public >*/ | |
170 | ||
5b146dc7 | 171 | CPUNegativeOffsetState neg; |
a836b8fa PB |
172 | CPUM68KState env; |
173 | }; | |
174 | ||
a836b8fa | 175 | |
d5db810c | 176 | #ifndef CONFIG_USER_ONLY |
a836b8fa PB |
177 | void m68k_cpu_do_interrupt(CPUState *cpu); |
178 | bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req); | |
6d2d454a | 179 | hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); |
d5db810c | 180 | #endif /* !CONFIG_USER_ONLY */ |
90c84c56 | 181 | void m68k_cpu_dump_state(CPUState *cpu, FILE *f, int flags); |
a010bdbe | 182 | int m68k_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); |
a836b8fa PB |
183 | int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); |
184 | ||
e1f3808e | 185 | void m68k_tcg_init(void); |
6d1bbc62 | 186 | void m68k_cpu_init_gdb(M68kCPU *cpu); |
99c51448 RH |
187 | uint32_t cpu_m68k_get_ccr(CPUM68KState *env); |
188 | void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t); | |
d2f8fb8e | 189 | void cpu_m68k_set_sr(CPUM68KState *env, uint32_t); |
d21f73c6 | 190 | void cpu_m68k_restore_fp_status(CPUM68KState *env); |
ba624944 | 191 | void cpu_m68k_set_fpcr(CPUM68KState *env, uint32_t val); |
e6e5906b | 192 | |
c3ce5a23 | 193 | |
808d77bc LMP |
194 | /* |
195 | * Instead of computing the condition codes after each m68k instruction, | |
c3ce5a23 PB |
196 | * QEMU just stores one operand (called CC_SRC), the result |
197 | * (called CC_DEST) and the type of operation (called CC_OP). When the | |
198 | * condition codes are needed, the condition codes can be calculated | |
199 | * using this information. Condition codes are not generated if they | |
200 | * are only needed for conditional branches. | |
201 | */ | |
9fdb533f | 202 | typedef enum { |
620c6cf6 | 203 | /* Translator only -- use env->cc_op. */ |
7deddf96 | 204 | CC_OP_DYNAMIC, |
620c6cf6 RH |
205 | |
206 | /* Each flag bit computed into cc_[xcnvz]. */ | |
207 | CC_OP_FLAGS, | |
208 | ||
209 | /* X in cc_x, C = X, N in cc_n, Z in cc_n, V via cc_n/cc_v. */ | |
db3d7945 LV |
210 | CC_OP_ADDB, CC_OP_ADDW, CC_OP_ADDL, |
211 | CC_OP_SUBB, CC_OP_SUBW, CC_OP_SUBL, | |
620c6cf6 RH |
212 | |
213 | /* X in cc_x, {N,Z,C,V} via cc_n/cc_v. */ | |
db3d7945 | 214 | CC_OP_CMPB, CC_OP_CMPW, CC_OP_CMPL, |
620c6cf6 RH |
215 | |
216 | /* X in cc_x, C = 0, V = 0, N in cc_n, Z in cc_n. */ | |
217 | CC_OP_LOGIC, | |
218 | ||
219 | CC_OP_NB | |
9fdb533f | 220 | } CCOp; |
e6e5906b PB |
221 | |
222 | #define CCF_C 0x01 | |
223 | #define CCF_V 0x02 | |
224 | #define CCF_Z 0x04 | |
225 | #define CCF_N 0x08 | |
0633879f PB |
226 | #define CCF_X 0x10 |
227 | ||
228 | #define SR_I_SHIFT 8 | |
229 | #define SR_I 0x0700 | |
230 | #define SR_M 0x1000 | |
231 | #define SR_S 0x2000 | |
cc523026 LV |
232 | #define SR_T_SHIFT 14 |
233 | #define SR_T 0xc000 | |
e6e5906b | 234 | |
5e50c6c7 MCA |
235 | #define M68K_SR_TRACE(sr) ((sr & SR_T) >> SR_T_SHIFT) |
236 | #define M68K_SR_TRACE_ANY_INS 0x2 | |
237 | ||
20dcee94 PB |
238 | #define M68K_SSP 0 |
239 | #define M68K_USP 1 | |
6e22b28e LV |
240 | #define M68K_ISP 2 |
241 | ||
88b2fef6 LV |
242 | /* bits for 68040 special status word */ |
243 | #define M68K_CP_040 0x8000 | |
244 | #define M68K_CU_040 0x4000 | |
245 | #define M68K_CT_040 0x2000 | |
246 | #define M68K_CM_040 0x1000 | |
247 | #define M68K_MA_040 0x0800 | |
248 | #define M68K_ATC_040 0x0400 | |
249 | #define M68K_LK_040 0x0200 | |
250 | #define M68K_RW_040 0x0100 | |
251 | #define M68K_SIZ_040 0x0060 | |
252 | #define M68K_TT_040 0x0018 | |
253 | #define M68K_TM_040 0x0007 | |
254 | ||
255 | #define M68K_TM_040_DATA 0x0001 | |
256 | #define M68K_TM_040_CODE 0x0002 | |
257 | #define M68K_TM_040_SUPER 0x0004 | |
258 | ||
259 | /* bits for 68040 write back status word */ | |
260 | #define M68K_WBV_040 0x80 | |
261 | #define M68K_WBSIZ_040 0x60 | |
262 | #define M68K_WBBYT_040 0x20 | |
263 | #define M68K_WBWRD_040 0x40 | |
264 | #define M68K_WBLNG_040 0x00 | |
265 | #define M68K_WBTT_040 0x18 | |
266 | #define M68K_WBTM_040 0x07 | |
267 | ||
268 | /* bus access size codes */ | |
269 | #define M68K_BA_SIZE_MASK 0x60 | |
270 | #define M68K_BA_SIZE_BYTE 0x20 | |
271 | #define M68K_BA_SIZE_WORD 0x40 | |
272 | #define M68K_BA_SIZE_LONG 0x00 | |
273 | #define M68K_BA_SIZE_LINE 0x60 | |
274 | ||
275 | /* bus access transfer type codes */ | |
276 | #define M68K_BA_TT_MOVE16 0x08 | |
277 | ||
278 | /* bits for 68040 MMU status register (mmusr) */ | |
279 | #define M68K_MMU_B_040 0x0800 | |
280 | #define M68K_MMU_G_040 0x0400 | |
281 | #define M68K_MMU_U1_040 0x0200 | |
282 | #define M68K_MMU_U0_040 0x0100 | |
283 | #define M68K_MMU_S_040 0x0080 | |
284 | #define M68K_MMU_CM_040 0x0060 | |
285 | #define M68K_MMU_M_040 0x0010 | |
286 | #define M68K_MMU_WP_040 0x0004 | |
287 | #define M68K_MMU_T_040 0x0002 | |
288 | #define M68K_MMU_R_040 0x0001 | |
289 | ||
290 | #define M68K_MMU_SR_MASK_040 (M68K_MMU_G_040 | M68K_MMU_U1_040 | \ | |
291 | M68K_MMU_U0_040 | M68K_MMU_S_040 | \ | |
292 | M68K_MMU_CM_040 | M68K_MMU_M_040 | \ | |
293 | M68K_MMU_WP_040) | |
294 | ||
295 | /* bits for 68040 MMU Translation Control Register */ | |
296 | #define M68K_TCR_ENABLED 0x8000 | |
297 | #define M68K_TCR_PAGE_8K 0x4000 | |
298 | ||
299 | /* bits for 68040 MMU Table Descriptor / Page Descriptor / TTR */ | |
300 | #define M68K_DESC_WRITEPROT 0x00000004 | |
301 | #define M68K_DESC_USED 0x00000008 | |
302 | #define M68K_DESC_MODIFIED 0x00000010 | |
303 | #define M68K_DESC_CACHEMODE 0x00000060 | |
304 | #define M68K_DESC_CM_WRTHRU 0x00000000 | |
305 | #define M68K_DESC_CM_COPYBK 0x00000020 | |
306 | #define M68K_DESC_CM_SERIAL 0x00000040 | |
307 | #define M68K_DESC_CM_NCACHE 0x00000060 | |
308 | #define M68K_DESC_SUPERONLY 0x00000080 | |
309 | #define M68K_DESC_USERATTR 0x00000300 | |
310 | #define M68K_DESC_USERATTR_SHIFT 8 | |
311 | #define M68K_DESC_GLOBAL 0x00000400 | |
312 | #define M68K_DESC_URESERVED 0x00000800 | |
313 | ||
2097dca6 | 314 | #define M68K_ROOT_POINTER_ENTRIES 128 |
88b2fef6 LV |
315 | #define M68K_4K_PAGE_MASK (~0xff) |
316 | #define M68K_POINTER_BASE(entry) (entry & ~0x1ff) | |
317 | #define M68K_ROOT_INDEX(addr) ((address >> 23) & 0x1fc) | |
318 | #define M68K_POINTER_INDEX(addr) ((address >> 16) & 0x1fc) | |
319 | #define M68K_4K_PAGE_BASE(entry) (next & M68K_4K_PAGE_MASK) | |
320 | #define M68K_4K_PAGE_INDEX(addr) ((address >> 10) & 0xfc) | |
321 | #define M68K_8K_PAGE_MASK (~0x7f) | |
322 | #define M68K_8K_PAGE_BASE(entry) (next & M68K_8K_PAGE_MASK) | |
323 | #define M68K_8K_PAGE_INDEX(addr) ((address >> 11) & 0x7c) | |
324 | #define M68K_UDT_VALID(entry) (entry & 2) | |
325 | #define M68K_PDT_VALID(entry) (entry & 3) | |
326 | #define M68K_PDT_INDIRECT(entry) ((entry & 3) == 2) | |
327 | #define M68K_INDIRECT_POINTER(addr) (addr & ~3) | |
2097dca6 LV |
328 | #define M68K_TTS_POINTER_SHIFT 18 |
329 | #define M68K_TTS_ROOT_SHIFT 25 | |
88b2fef6 | 330 | |
c05c73b0 LV |
331 | /* bits for 68040 MMU Transparent Translation Registers */ |
332 | #define M68K_TTR_ADDR_BASE 0xff000000 | |
333 | #define M68K_TTR_ADDR_MASK 0x00ff0000 | |
334 | #define M68K_TTR_ADDR_MASK_SHIFT 8 | |
335 | #define M68K_TTR_ENABLED 0x00008000 | |
336 | #define M68K_TTR_SFIELD 0x00006000 | |
337 | #define M68K_TTR_SFIELD_USER 0x0000 | |
338 | #define M68K_TTR_SFIELD_SUPER 0x2000 | |
339 | ||
6e22b28e LV |
340 | /* m68k Control Registers */ |
341 | ||
342 | /* ColdFire */ | |
343 | /* Memory Management Control Registers */ | |
344 | #define M68K_CR_ASID 0x003 | |
345 | #define M68K_CR_ACR0 0x004 | |
346 | #define M68K_CR_ACR1 0x005 | |
347 | #define M68K_CR_ACR2 0x006 | |
348 | #define M68K_CR_ACR3 0x007 | |
349 | #define M68K_CR_MMUBAR 0x008 | |
350 | ||
351 | /* Processor Miscellaneous Registers */ | |
352 | #define M68K_CR_PC 0x80F | |
353 | ||
354 | /* Local Memory and Module Control Registers */ | |
355 | #define M68K_CR_ROMBAR0 0xC00 | |
356 | #define M68K_CR_ROMBAR1 0xC01 | |
357 | #define M68K_CR_RAMBAR0 0xC04 | |
358 | #define M68K_CR_RAMBAR1 0xC05 | |
359 | #define M68K_CR_MPCR 0xC0C | |
360 | #define M68K_CR_EDRAMBAR 0xC0D | |
361 | #define M68K_CR_SECMBAR 0xC0E | |
362 | #define M68K_CR_MBAR 0xC0F | |
363 | ||
364 | /* Local Memory Address Permutation Control Registers */ | |
365 | #define M68K_CR_PCR1U0 0xD02 | |
366 | #define M68K_CR_PCR1L0 0xD03 | |
367 | #define M68K_CR_PCR2U0 0xD04 | |
368 | #define M68K_CR_PCR2L0 0xD05 | |
369 | #define M68K_CR_PCR3U0 0xD06 | |
370 | #define M68K_CR_PCR3L0 0xD07 | |
371 | #define M68K_CR_PCR1U1 0xD0A | |
372 | #define M68K_CR_PCR1L1 0xD0B | |
373 | #define M68K_CR_PCR2U1 0xD0C | |
374 | #define M68K_CR_PCR2L1 0xD0D | |
375 | #define M68K_CR_PCR3U1 0xD0E | |
376 | #define M68K_CR_PCR3L1 0xD0F | |
377 | ||
378 | /* MC680x0 */ | |
379 | /* MC680[1234]0/CPU32 */ | |
380 | #define M68K_CR_SFC 0x000 | |
381 | #define M68K_CR_DFC 0x001 | |
382 | #define M68K_CR_USP 0x800 | |
383 | #define M68K_CR_VBR 0x801 /* + Coldfire */ | |
384 | ||
385 | /* MC680[234]0 */ | |
386 | #define M68K_CR_CACR 0x002 /* + Coldfire */ | |
387 | #define M68K_CR_CAAR 0x802 /* MC68020 and MC68030 only */ | |
388 | #define M68K_CR_MSP 0x803 | |
389 | #define M68K_CR_ISP 0x804 | |
390 | ||
391 | /* MC68040/MC68LC040 */ | |
392 | #define M68K_CR_TC 0x003 | |
393 | #define M68K_CR_ITT0 0x004 | |
394 | #define M68K_CR_ITT1 0x005 | |
395 | #define M68K_CR_DTT0 0x006 | |
396 | #define M68K_CR_DTT1 0x007 | |
397 | #define M68K_CR_MMUSR 0x805 | |
398 | #define M68K_CR_URP 0x806 | |
399 | #define M68K_CR_SRP 0x807 | |
400 | ||
401 | /* MC68EC040 */ | |
402 | #define M68K_CR_IACR0 0x004 | |
403 | #define M68K_CR_IACR1 0x005 | |
404 | #define M68K_CR_DACR0 0x006 | |
405 | #define M68K_CR_DACR1 0x007 | |
20dcee94 | 406 | |
5736526c LMP |
407 | /* MC68060 */ |
408 | #define M68K_CR_BUSCR 0x008 | |
409 | #define M68K_CR_PCR 0x808 | |
410 | ||
ba624944 LV |
411 | #define M68K_FPIAR_SHIFT 0 |
412 | #define M68K_FPIAR (1 << M68K_FPIAR_SHIFT) | |
413 | #define M68K_FPSR_SHIFT 1 | |
414 | #define M68K_FPSR (1 << M68K_FPSR_SHIFT) | |
415 | #define M68K_FPCR_SHIFT 2 | |
416 | #define M68K_FPCR (1 << M68K_FPCR_SHIFT) | |
417 | ||
418 | /* Floating-Point Status Register */ | |
419 | ||
420 | /* Condition Code */ | |
421 | #define FPSR_CC_MASK 0x0f000000 | |
422 | #define FPSR_CC_A 0x01000000 /* Not-A-Number */ | |
423 | #define FPSR_CC_I 0x02000000 /* Infinity */ | |
424 | #define FPSR_CC_Z 0x04000000 /* Zero */ | |
425 | #define FPSR_CC_N 0x08000000 /* Negative */ | |
426 | ||
427 | /* Quotient */ | |
428 | ||
429 | #define FPSR_QT_MASK 0x00ff0000 | |
591596b7 | 430 | #define FPSR_QT_SHIFT 16 |
ba624944 LV |
431 | |
432 | /* Floating-Point Control Register */ | |
433 | /* Rounding mode */ | |
434 | #define FPCR_RND_MASK 0x0030 | |
435 | #define FPCR_RND_N 0x0000 | |
436 | #define FPCR_RND_Z 0x0010 | |
437 | #define FPCR_RND_M 0x0020 | |
438 | #define FPCR_RND_P 0x0030 | |
439 | ||
440 | /* Rounding precision */ | |
441 | #define FPCR_PREC_MASK 0x00c0 | |
442 | #define FPCR_PREC_X 0x0000 | |
443 | #define FPCR_PREC_S 0x0040 | |
444 | #define FPCR_PREC_D 0x0080 | |
445 | #define FPCR_PREC_U 0x00c0 | |
446 | ||
447 | #define FPCR_EXCP_MASK 0xff00 | |
448 | ||
20dcee94 PB |
449 | /* CACR fields are implementation defined, but some bits are common. */ |
450 | #define M68K_CACR_EUSP 0x10 | |
451 | ||
acf930aa PB |
452 | #define MACSR_PAV0 0x100 |
453 | #define MACSR_OMC 0x080 | |
454 | #define MACSR_SU 0x040 | |
455 | #define MACSR_FI 0x020 | |
456 | #define MACSR_RT 0x010 | |
457 | #define MACSR_N 0x008 | |
458 | #define MACSR_Z 0x004 | |
459 | #define MACSR_V 0x002 | |
460 | #define MACSR_EV 0x001 | |
461 | ||
cb3fb38e | 462 | void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector); |
20dcee94 | 463 | void m68k_switch_sp(CPUM68KState *env); |
e6e5906b | 464 | |
a87295e8 PB |
465 | void do_m68k_semihosting(CPUM68KState *env, int nr); |
466 | ||
808d77bc | 467 | /* |
ee2fc6c6 LMP |
468 | * The 68000 family is defined in six main CPU classes, the 680[012346]0. |
469 | * Generally each successive CPU adds enhanced data/stack/instructions. | |
470 | * However, some features are only common to one, or a few classes. | |
471 | * The features covers those subsets of instructons. | |
472 | * | |
473 | * CPU32/32+ are basically 680010 compatible with some 68020 class instructons, | |
474 | * and some additional CPU32 instructions. Mostly Supervisor state differences. | |
475 | * | |
476 | * The ColdFire core ISA is a RISC-style reduction of the 68000 series cpu. | |
808d77bc LMP |
477 | * There are 4 ColdFire core ISA revisions: A, A+, B and C. |
478 | * Each feature covers the subset of instructions common to the | |
479 | * ISA revisions mentioned. | |
480 | */ | |
d315c888 | 481 | |
0402f767 | 482 | enum m68k_features { |
aece90d8 MCA |
483 | /* Base Motorola CPU set (not set for Coldfire CPUs) */ |
484 | M68K_FEATURE_M68K, | |
485 | /* Motorola CPU feature sets */ | |
4ecce5fb | 486 | M68K_FEATURE_M68010, |
18b6102e LV |
487 | M68K_FEATURE_M68020, |
488 | M68K_FEATURE_M68030, | |
489 | M68K_FEATURE_M68040, | |
490 | M68K_FEATURE_M68060, | |
469949c9 MCA |
491 | /* Base Coldfire set Rev A. */ |
492 | M68K_FEATURE_CF_ISA_A, | |
493 | /* (ISA B or C). */ | |
494 | M68K_FEATURE_CF_ISA_B, | |
495 | /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */ | |
496 | M68K_FEATURE_CF_ISA_APLUSC, | |
497 | /* BRA with Long branch. (680[2346]0, ISA A+ or B). */ | |
498 | M68K_FEATURE_BRAL, | |
0402f767 PB |
499 | M68K_FEATURE_CF_FPU, |
500 | M68K_FEATURE_CF_MAC, | |
501 | M68K_FEATURE_CF_EMAC, | |
469949c9 MCA |
502 | /* Revision B EMAC (dual accumulate). */ |
503 | M68K_FEATURE_CF_EMAC_B, | |
504 | /* User Stack Pointer. (680[012346]0, ISA A+, B or C). */ | |
505 | M68K_FEATURE_USP, | |
506 | /* Master Stack Pointer. (680[234]0) */ | |
507 | M68K_FEATURE_MSP, | |
508 | /* 68020+ full extension word. */ | |
509 | M68K_FEATURE_EXT_FULL, | |
510 | /* word sized address index registers. */ | |
511 | M68K_FEATURE_WORD_INDEX, | |
512 | /* scaled address index registers. */ | |
513 | M68K_FEATURE_SCALED_INDEX, | |
514 | /* 32 bit mul/div. (680[2346]0, and CPU32) */ | |
515 | M68K_FEATURE_LONG_MULDIV, | |
516 | /* 64 bit mul/div. (680[2346]0, and CPU32) */ | |
517 | M68K_FEATURE_QUAD_MULDIV, | |
518 | /* Bcc with Long branches. (680[2346]0, and CPU32) */ | |
519 | M68K_FEATURE_BCCL, | |
520 | /* BFxxx Bit field insns. (680[2346]0) */ | |
521 | M68K_FEATURE_BITFIELD, | |
522 | /* fpu insn. (680[46]0) */ | |
523 | M68K_FEATURE_FPU, | |
524 | /* CAS/CAS2[WL] insns. (680[2346]0) */ | |
525 | M68K_FEATURE_CAS, | |
526 | /* BKPT insn. (680[12346]0, and CPU32) */ | |
527 | M68K_FEATURE_BKPT, | |
528 | /* RTD insn. (680[12346]0, and CPU32) */ | |
529 | M68K_FEATURE_RTD, | |
530 | /* CHK2 insn. (680[2346]0, and CPU32) */ | |
531 | M68K_FEATURE_CHK2, | |
532 | /* MOVEP insn. (680[01234]0, and CPU32) */ | |
533 | M68K_FEATURE_MOVEP, | |
534 | /* MOVEC insn. (from 68010) */ | |
535 | M68K_FEATURE_MOVEC, | |
a9431a03 MCA |
536 | /* Unaligned data accesses (680[2346]0) */ |
537 | M68K_FEATURE_UNALIGNED_DATA, | |
aeeb90af RH |
538 | /* TRAPcc insn. (680[2346]0, and CPU32) */ |
539 | M68K_FEATURE_TRAPCC, | |
b342e56b MCA |
540 | /* MOVE from SR privileged (from 68010) */ |
541 | M68K_FEATURE_MOVEFROMSR_PRIV, | |
0402f767 PB |
542 | }; |
543 | ||
2dc7bf63 | 544 | static inline bool m68k_feature(CPUM68KState *env, int feature) |
0402f767 | 545 | { |
2dc7bf63 | 546 | return (env->features & BIT_ULL(feature)) != 0; |
0402f767 PB |
547 | } |
548 | ||
0442428a | 549 | void m68k_cpu_list(void); |
009a4356 | 550 | |
0402f767 PB |
551 | void register_m68k_insns (CPUM68KState *env); |
552 | ||
88b2fef6 LV |
553 | enum { |
554 | /* 1 bit to define user level / supervisor access */ | |
555 | ACCESS_SUPER = 0x01, | |
556 | /* 1 bit to indicate direction */ | |
557 | ACCESS_STORE = 0x02, | |
558 | /* 1 bit to indicate debug access */ | |
559 | ACCESS_DEBUG = 0x04, | |
e55886c3 LV |
560 | /* PTEST instruction */ |
561 | ACCESS_PTEST = 0x08, | |
88b2fef6 LV |
562 | /* Type of instruction that generated the access */ |
563 | ACCESS_CODE = 0x10, /* Code fetch access */ | |
564 | ACCESS_DATA = 0x20, /* Data load/store access */ | |
565 | }; | |
9467d44c | 566 | |
f61797bd IM |
567 | #define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU |
568 | #define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX | |
0dacec87 | 569 | #define CPU_RESOLVING_TYPE TYPE_M68K_CPU |
f61797bd | 570 | |
009a4356 | 571 | #define cpu_list m68k_cpu_list |
9467d44c | 572 | |
6ebbf390 | 573 | /* MMU modes definitions */ |
88b2fef6 | 574 | #define MMU_KERNEL_IDX 0 |
6ebbf390 | 575 | #define MMU_USER_IDX 1 |
97ed5ccd | 576 | static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch) |
6ebbf390 JM |
577 | { |
578 | return (env->sr & SR_S) == 0 ? 1 : 0; | |
579 | } | |
580 | ||
fe5f7b1b RH |
581 | bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
582 | MMUAccessType access_type, int mmu_idx, | |
583 | bool probe, uintptr_t retaddr); | |
d90ebc47 | 584 | #ifndef CONFIG_USER_ONLY |
e1aaf3a8 PM |
585 | void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, |
586 | unsigned size, MMUAccessType access_type, | |
587 | int mmu_idx, MemTxAttrs attrs, | |
588 | MemTxResult response, uintptr_t retaddr); | |
d90ebc47 | 589 | #endif |
aaedd1f9 | 590 | |
022c62cb | 591 | #include "exec/cpu-all.h" |
622ed360 | 592 | |
5fa9f1f2 LV |
593 | /* TB flags */ |
594 | #define TB_FLAGS_MACSR 0x0f | |
595 | #define TB_FLAGS_MSR_S_BIT 13 | |
596 | #define TB_FLAGS_MSR_S (1 << TB_FLAGS_MSR_S_BIT) | |
597 | #define TB_FLAGS_SFC_S_BIT 14 | |
598 | #define TB_FLAGS_SFC_S (1 << TB_FLAGS_SFC_S_BIT) | |
599 | #define TB_FLAGS_DFC_S_BIT 15 | |
600 | #define TB_FLAGS_DFC_S (1 << TB_FLAGS_DFC_S_BIT) | |
5e50c6c7 MCA |
601 | #define TB_FLAGS_TRACE 16 |
602 | #define TB_FLAGS_TRACE_BIT (1 << TB_FLAGS_TRACE) | |
5fa9f1f2 | 603 | |
2b3e3cfe | 604 | static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc, |
89fee74a | 605 | target_ulong *cs_base, uint32_t *flags) |
6b917547 AL |
606 | { |
607 | *pc = env->pc; | |
608 | *cs_base = 0; | |
5fa9f1f2 LV |
609 | *flags = (env->macsr >> 4) & TB_FLAGS_MACSR; |
610 | if (env->sr & SR_S) { | |
611 | *flags |= TB_FLAGS_MSR_S; | |
612 | *flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S; | |
613 | *flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S; | |
614 | } | |
5e50c6c7 MCA |
615 | if (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS) { |
616 | *flags |= TB_FLAGS_TRACE; | |
617 | } | |
6b917547 AL |
618 | } |
619 | ||
fad866da MA |
620 | void dump_mmu(CPUM68KState *env); |
621 | ||
e6e5906b | 622 | #endif |