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Commit | Line | Data |
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7ba0e95b AM |
1 | /* |
2 | * MIPS internal definitions and helpers | |
26aa3d9a PMD |
3 | * |
4 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
5 | * See the COPYING file in the top-level directory. | |
6 | */ | |
7 | ||
8 | #ifndef MIPS_INTERNAL_H | |
9 | #define MIPS_INTERNAL_H | |
10 | ||
34cffe96 | 11 | #include "exec/memattrs.h" |
6fe25ce5 PMD |
12 | #ifdef CONFIG_TCG |
13 | #include "tcg/tcg-internal.h" | |
14 | #endif | |
41da212c | 15 | |
7ba0e95b AM |
16 | /* |
17 | * MMU types, the first four entries have the same layout as the | |
18 | * CP0C0_MT field. | |
19 | */ | |
41da212c | 20 | enum mips_mmu_types { |
1ab3a0de PMD |
21 | MMU_TYPE_NONE = 0, |
22 | MMU_TYPE_R4000 = 1, /* Standard TLB */ | |
23 | MMU_TYPE_BAT = 2, /* Block Address Translation */ | |
24 | MMU_TYPE_FMT = 3, /* Fixed Mapping */ | |
25 | MMU_TYPE_DVF = 4, /* Dual VTLB and FTLB */ | |
41da212c IM |
26 | MMU_TYPE_R3000, |
27 | MMU_TYPE_R6000, | |
28 | MMU_TYPE_R8000 | |
29 | }; | |
30 | ||
31 | struct mips_def_t { | |
32 | const char *name; | |
33 | int32_t CP0_PRid; | |
34 | int32_t CP0_Config0; | |
35 | int32_t CP0_Config1; | |
36 | int32_t CP0_Config2; | |
37 | int32_t CP0_Config3; | |
38 | int32_t CP0_Config4; | |
39 | int32_t CP0_Config4_rw_bitmask; | |
40 | int32_t CP0_Config5; | |
41 | int32_t CP0_Config5_rw_bitmask; | |
42 | int32_t CP0_Config6; | |
af868995 | 43 | int32_t CP0_Config6_rw_bitmask; |
41da212c | 44 | int32_t CP0_Config7; |
af868995 | 45 | int32_t CP0_Config7_rw_bitmask; |
41da212c IM |
46 | target_ulong CP0_LLAddr_rw_bitmask; |
47 | int CP0_LLAddr_shift; | |
48 | int32_t SYNCI_Step; | |
49 | int32_t CCRes; | |
50 | int32_t CP0_Status_rw_bitmask; | |
51 | int32_t CP0_TCStatus_rw_bitmask; | |
52 | int32_t CP0_SRSCtl; | |
53 | int32_t CP1_fcr0; | |
54 | int32_t CP1_fcr31_rw_bitmask; | |
55 | int32_t CP1_fcr31; | |
56 | int32_t MSAIR; | |
57 | int32_t SEGBITS; | |
58 | int32_t PABITS; | |
59 | int32_t CP0_SRSConf0_rw_bitmask; | |
60 | int32_t CP0_SRSConf0; | |
61 | int32_t CP0_SRSConf1_rw_bitmask; | |
62 | int32_t CP0_SRSConf1; | |
63 | int32_t CP0_SRSConf2_rw_bitmask; | |
64 | int32_t CP0_SRSConf2; | |
65 | int32_t CP0_SRSConf3_rw_bitmask; | |
66 | int32_t CP0_SRSConf3; | |
67 | int32_t CP0_SRSConf4_rw_bitmask; | |
68 | int32_t CP0_SRSConf4; | |
69 | int32_t CP0_PageGrain_rw_bitmask; | |
70 | int32_t CP0_PageGrain; | |
71 | target_ulong CP0_EBaseWG_rw_bitmask; | |
f9c9cd63 | 72 | uint64_t insn_flags; |
41da212c | 73 | enum mips_mmu_types mmu_type; |
5fb2dcd1 | 74 | int32_t SAARP; |
41da212c IM |
75 | }; |
76 | ||
830b87ea PMD |
77 | extern const char regnames[32][4]; |
78 | extern const char fregnames[32][4]; | |
adbf1be3 | 79 | |
41da212c IM |
80 | extern const struct mips_def_t mips_defs[]; |
81 | extern const int mips_defs_number; | |
82 | ||
26aa3d9a | 83 | bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); |
26aa3d9a | 84 | hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); |
a010bdbe | 85 | int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); |
26aa3d9a PMD |
86 | int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); |
87 | void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, | |
88 | MMUAccessType access_type, | |
89 | int mmu_idx, uintptr_t retaddr); | |
90 | ||
91 | #if !defined(CONFIG_USER_ONLY) | |
92 | ||
93 | typedef struct r4k_tlb_t r4k_tlb_t; | |
94 | struct r4k_tlb_t { | |
95 | target_ulong VPN; | |
96 | uint32_t PageMask; | |
97 | uint16_t ASID; | |
99029be1 | 98 | uint32_t MMID; |
26aa3d9a PMD |
99 | unsigned int G:1; |
100 | unsigned int C0:3; | |
101 | unsigned int C1:3; | |
102 | unsigned int V0:1; | |
103 | unsigned int V1:1; | |
104 | unsigned int D0:1; | |
105 | unsigned int D1:1; | |
106 | unsigned int XI0:1; | |
107 | unsigned int XI1:1; | |
108 | unsigned int RI0:1; | |
109 | unsigned int RI1:1; | |
110 | unsigned int EHINV:1; | |
111 | uint64_t PFN[2]; | |
112 | }; | |
113 | ||
114 | struct CPUMIPSTLBContext { | |
115 | uint32_t nb_tlb; | |
116 | uint32_t tlb_in_use; | |
117 | int (*map_address)(struct CPUMIPSState *env, hwaddr *physical, int *prot, | |
edbd4992 | 118 | target_ulong address, MMUAccessType access_type); |
26aa3d9a PMD |
119 | void (*helper_tlbwi)(struct CPUMIPSState *env); |
120 | void (*helper_tlbwr)(struct CPUMIPSState *env); | |
121 | void (*helper_tlbp)(struct CPUMIPSState *env); | |
122 | void (*helper_tlbr)(struct CPUMIPSState *env); | |
123 | void (*helper_tlbinv)(struct CPUMIPSState *env); | |
124 | void (*helper_tlbinvf)(struct CPUMIPSState *env); | |
125 | union { | |
126 | struct { | |
127 | r4k_tlb_t tlb[MIPS_TLB_MAX]; | |
128 | } r4k; | |
129 | } mmu; | |
130 | }; | |
131 | ||
132 | int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, | |
edbd4992 | 133 | target_ulong address, MMUAccessType access_type); |
26aa3d9a | 134 | int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, |
edbd4992 | 135 | target_ulong address, MMUAccessType access_type); |
26aa3d9a | 136 | int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, |
edbd4992 | 137 | target_ulong address, MMUAccessType access_type); |
26aa3d9a PMD |
138 | void r4k_helper_tlbwi(CPUMIPSState *env); |
139 | void r4k_helper_tlbwr(CPUMIPSState *env); | |
140 | void r4k_helper_tlbp(CPUMIPSState *env); | |
141 | void r4k_helper_tlbr(CPUMIPSState *env); | |
142 | void r4k_helper_tlbinv(CPUMIPSState *env); | |
143 | void r4k_helper_tlbinvf(CPUMIPSState *env); | |
144 | void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra); | |
2dc29222 | 145 | uint32_t cpu_mips_get_random(CPUMIPSState *env); |
26aa3d9a | 146 | |
4f02a06d PM |
147 | void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, |
148 | vaddr addr, unsigned size, | |
149 | MMUAccessType access_type, | |
150 | int mmu_idx, MemTxAttrs attrs, | |
151 | MemTxResult response, uintptr_t retaddr); | |
26aa3d9a | 152 | hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, |
0debf140 | 153 | MMUAccessType access_type, uintptr_t retaddr); |
26aa3d9a | 154 | |
8a9358cc | 155 | extern const VMStateDescription vmstate_mips_cpu; |
44e3b050 PMD |
156 | |
157 | #endif /* !CONFIG_USER_ONLY */ | |
158 | ||
159 | #define cpu_signal_handler cpu_mips_signal_handler | |
26aa3d9a PMD |
160 | |
161 | static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env) | |
162 | { | |
163 | return (env->CP0_Status & (1 << CP0St_IE)) && | |
164 | !(env->CP0_Status & (1 << CP0St_EXL)) && | |
165 | !(env->CP0_Status & (1 << CP0St_ERL)) && | |
166 | !(env->hflags & MIPS_HFLAG_DM) && | |
7ba0e95b AM |
167 | /* |
168 | * Note that the TCStatus IXMT field is initialized to zero, | |
169 | * and only MT capable cores can set it to one. So we don't | |
170 | * need to check for MT capabilities here. | |
171 | */ | |
26aa3d9a PMD |
172 | !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT)); |
173 | } | |
174 | ||
175 | /* Check if there is pending and not masked out interrupt */ | |
176 | static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env) | |
177 | { | |
178 | int32_t pending; | |
179 | int32_t status; | |
180 | bool r; | |
181 | ||
182 | pending = env->CP0_Cause & CP0Ca_IP_mask; | |
183 | status = env->CP0_Status & CP0Ca_IP_mask; | |
184 | ||
185 | if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { | |
7ba0e95b AM |
186 | /* |
187 | * A MIPS configured with a vectorizing external interrupt controller | |
188 | * will feed a vector into the Cause pending lines. The core treats | |
8cdf8869 | 189 | * the status lines as a vector level, not as individual masks. |
7ba0e95b | 190 | */ |
26aa3d9a PMD |
191 | r = pending > status; |
192 | } else { | |
7ba0e95b AM |
193 | /* |
194 | * A MIPS configured with compatibility or VInt (Vectored Interrupts) | |
195 | * treats the pending lines as individual interrupt lines, the status | |
196 | * lines are individual masks. | |
197 | */ | |
26aa3d9a PMD |
198 | r = (pending & status) != 0; |
199 | } | |
200 | return r; | |
201 | } | |
202 | ||
203 | void mips_tcg_init(void); | |
204 | ||
03e4d95c PMD |
205 | void msa_reset(CPUMIPSState *env); |
206 | ||
26aa3d9a | 207 | /* cp0_timer.c */ |
26aa3d9a PMD |
208 | uint32_t cpu_mips_get_count(CPUMIPSState *env); |
209 | void cpu_mips_store_count(CPUMIPSState *env, uint32_t value); | |
210 | void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value); | |
211 | void cpu_mips_start_count(CPUMIPSState *env); | |
212 | void cpu_mips_stop_count(CPUMIPSState *env); | |
213 | ||
214 | /* helper.c */ | |
f2c5b39e | 215 | void mmu_init(CPUMIPSState *env, const mips_def_t *def); |
26aa3d9a PMD |
216 | |
217 | /* op_helper.c */ | |
074cfcb4 | 218 | void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask); |
26aa3d9a | 219 | |
533fc64f PMD |
220 | static inline void mips_env_set_pc(CPUMIPSState *env, target_ulong value) |
221 | { | |
222 | env->active_tc.PC = value & ~(target_ulong)1; | |
223 | if (value & 1) { | |
224 | env->hflags |= MIPS_HFLAG_M16; | |
225 | } else { | |
226 | env->hflags &= ~(MIPS_HFLAG_M16); | |
227 | } | |
228 | } | |
229 | ||
26aa3d9a PMD |
230 | static inline void restore_pamask(CPUMIPSState *env) |
231 | { | |
232 | if (env->hflags & MIPS_HFLAG_ELPA) { | |
233 | env->PAMask = (1ULL << env->PABITS) - 1; | |
234 | } else { | |
235 | env->PAMask = PAMASK_BASE; | |
236 | } | |
237 | } | |
238 | ||
239 | static inline int mips_vpe_active(CPUMIPSState *env) | |
240 | { | |
241 | int active = 1; | |
242 | ||
243 | /* Check that the VPE is enabled. */ | |
244 | if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) { | |
245 | active = 0; | |
246 | } | |
247 | /* Check that the VPE is activated. */ | |
248 | if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) { | |
249 | active = 0; | |
250 | } | |
251 | ||
7ba0e95b AM |
252 | /* |
253 | * Now verify that there are active thread contexts in the VPE. | |
254 | * | |
255 | * This assumes the CPU model will internally reschedule threads | |
256 | * if the active one goes to sleep. If there are no threads available | |
257 | * the active one will be in a sleeping state, and we can turn off | |
258 | * the entire VPE. | |
259 | */ | |
26aa3d9a PMD |
260 | if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) { |
261 | /* TC is not activated. */ | |
262 | active = 0; | |
263 | } | |
264 | if (env->active_tc.CP0_TCHalt & 1) { | |
265 | /* TC is in halt state. */ | |
266 | active = 0; | |
267 | } | |
268 | ||
269 | return active; | |
270 | } | |
271 | ||
272 | static inline int mips_vp_active(CPUMIPSState *env) | |
273 | { | |
274 | CPUState *other_cs = first_cpu; | |
275 | ||
276 | /* Check if the VP disabled other VPs (which means the VP is enabled) */ | |
277 | if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) { | |
278 | return 1; | |
279 | } | |
280 | ||
281 | /* Check if the virtual processor is disabled due to a DVP */ | |
282 | CPU_FOREACH(other_cs) { | |
283 | MIPSCPU *other_cpu = MIPS_CPU(other_cs); | |
284 | if ((&other_cpu->env != env) && | |
285 | ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) { | |
286 | return 0; | |
287 | } | |
288 | } | |
289 | return 1; | |
290 | } | |
291 | ||
292 | static inline void compute_hflags(CPUMIPSState *env) | |
293 | { | |
294 | env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | | |
295 | MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU | | |
908f6be1 SM |
296 | MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 | |
297 | MIPS_HFLAG_DSP_R3 | MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | | |
59e781fb | 298 | MIPS_HFLAG_FRE | MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL); |
26aa3d9a PMD |
299 | if (env->CP0_Status & (1 << CP0St_ERL)) { |
300 | env->hflags |= MIPS_HFLAG_ERL; | |
301 | } | |
302 | if (!(env->CP0_Status & (1 << CP0St_EXL)) && | |
303 | !(env->CP0_Status & (1 << CP0St_ERL)) && | |
304 | !(env->hflags & MIPS_HFLAG_DM)) { | |
7ba0e95b AM |
305 | env->hflags |= (env->CP0_Status >> CP0St_KSU) & |
306 | MIPS_HFLAG_KSU; | |
26aa3d9a PMD |
307 | } |
308 | #if defined(TARGET_MIPS64) | |
309 | if ((env->insn_flags & ISA_MIPS3) && | |
310 | (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) || | |
311 | (env->CP0_Status & (1 << CP0St_PX)) || | |
312 | (env->CP0_Status & (1 << CP0St_UX)))) { | |
313 | env->hflags |= MIPS_HFLAG_64; | |
314 | } | |
315 | ||
316 | if (!(env->insn_flags & ISA_MIPS3)) { | |
317 | env->hflags |= MIPS_HFLAG_AWRAP; | |
318 | } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) && | |
319 | !(env->CP0_Status & (1 << CP0St_UX))) { | |
320 | env->hflags |= MIPS_HFLAG_AWRAP; | |
2e211e0a | 321 | } else if (env->insn_flags & ISA_MIPS_R6) { |
26aa3d9a PMD |
322 | /* Address wrapping for Supervisor and Kernel is specified in R6 */ |
323 | if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) && | |
324 | !(env->CP0_Status & (1 << CP0St_SX))) || | |
325 | (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) && | |
326 | !(env->CP0_Status & (1 << CP0St_KX)))) { | |
327 | env->hflags |= MIPS_HFLAG_AWRAP; | |
328 | } | |
329 | } | |
330 | #endif | |
331 | if (((env->CP0_Status & (1 << CP0St_CU0)) && | |
2e211e0a | 332 | !(env->insn_flags & ISA_MIPS_R6)) || |
26aa3d9a PMD |
333 | !(env->hflags & MIPS_HFLAG_KSU)) { |
334 | env->hflags |= MIPS_HFLAG_CP0; | |
335 | } | |
336 | if (env->CP0_Status & (1 << CP0St_CU1)) { | |
337 | env->hflags |= MIPS_HFLAG_FPU; | |
338 | } | |
339 | if (env->CP0_Status & (1 << CP0St_FR)) { | |
340 | env->hflags |= MIPS_HFLAG_F64; | |
341 | } | |
342 | if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) && | |
343 | (env->CP0_Config5 & (1 << CP0C5_SBRI))) { | |
344 | env->hflags |= MIPS_HFLAG_SBRI; | |
345 | } | |
908f6be1 SM |
346 | if (env->insn_flags & ASE_DSP_R3) { |
347 | /* | |
348 | * Our cpu supports DSP R3 ASE, so enable | |
349 | * access to DSP R3 resources. | |
350 | */ | |
59e781fb | 351 | if (env->CP0_Status & (1 << CP0St_MX)) { |
908f6be1 SM |
352 | env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 | |
353 | MIPS_HFLAG_DSP_R3; | |
59e781fb | 354 | } |
908f6be1 SM |
355 | } else if (env->insn_flags & ASE_DSP_R2) { |
356 | /* | |
357 | * Our cpu supports DSP R2 ASE, so enable | |
358 | * access to DSP R2 resources. | |
359 | */ | |
26aa3d9a | 360 | if (env->CP0_Status & (1 << CP0St_MX)) { |
908f6be1 | 361 | env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2; |
26aa3d9a PMD |
362 | } |
363 | ||
364 | } else if (env->insn_flags & ASE_DSP) { | |
908f6be1 SM |
365 | /* |
366 | * Our cpu supports DSP ASE, so enable | |
367 | * access to DSP resources. | |
368 | */ | |
26aa3d9a PMD |
369 | if (env->CP0_Status & (1 << CP0St_MX)) { |
370 | env->hflags |= MIPS_HFLAG_DSP; | |
371 | } | |
372 | ||
373 | } | |
7a47bae5 | 374 | if (env->insn_flags & ISA_MIPS_R2) { |
26aa3d9a PMD |
375 | if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { |
376 | env->hflags |= MIPS_HFLAG_COP1X; | |
377 | } | |
bbd5e4a2 | 378 | } else if (env->insn_flags & ISA_MIPS_R1) { |
26aa3d9a PMD |
379 | if (env->hflags & MIPS_HFLAG_64) { |
380 | env->hflags |= MIPS_HFLAG_COP1X; | |
381 | } | |
382 | } else if (env->insn_flags & ISA_MIPS4) { | |
7ba0e95b AM |
383 | /* |
384 | * All supported MIPS IV CPUs use the XX (CU3) to enable | |
385 | * and disable the MIPS IV extensions to the MIPS III ISA. | |
386 | * Some other MIPS IV CPUs ignore the bit, so the check here | |
387 | * would be too restrictive for them. | |
388 | */ | |
26aa3d9a PMD |
389 | if (env->CP0_Status & (1U << CP0St_CU3)) { |
390 | env->hflags |= MIPS_HFLAG_COP1X; | |
391 | } | |
392 | } | |
aa314198 | 393 | if (ase_msa_available(env)) { |
26aa3d9a PMD |
394 | if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) { |
395 | env->hflags |= MIPS_HFLAG_MSA; | |
396 | } | |
397 | } | |
398 | if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { | |
399 | if (env->CP0_Config5 & (1 << CP0C5_FRE)) { | |
400 | env->hflags |= MIPS_HFLAG_FRE; | |
401 | } | |
402 | } | |
403 | if (env->CP0_Config3 & (1 << CP0C3_LPA)) { | |
404 | if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) { | |
405 | env->hflags |= MIPS_HFLAG_ELPA; | |
406 | } | |
407 | } | |
408 | } | |
409 | ||
410 | void cpu_mips_tlb_flush(CPUMIPSState *env); | |
411 | void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); | |
412 | void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); | |
413 | void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); | |
414 | ||
e9927723 PMD |
415 | const char *mips_exception_name(int32_t exception); |
416 | ||
26aa3d9a PMD |
417 | void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception, |
418 | int error_code, uintptr_t pc); | |
419 | ||
420 | static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env, | |
421 | uint32_t exception, | |
422 | uintptr_t pc) | |
423 | { | |
424 | do_raise_exception_err(env, exception, 0, pc); | |
425 | } | |
426 | ||
427 | #endif |