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032c76bc CW |
1 | /* |
2 | * QEMU Nios II CPU | |
3 | * | |
4 | * Copyright (c) 2012 Chris Wulff <crwulff@gmail.com> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2.1 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see | |
18 | * <http://www.gnu.org/licenses/lgpl-2.1.html> | |
19 | */ | |
20 | ||
21 | #include "qemu/osdep.h" | |
0b8fa32f | 22 | #include "qemu/module.h" |
032c76bc CW |
23 | #include "qapi/error.h" |
24 | #include "cpu.h" | |
25 | #include "exec/log.h" | |
26 | #include "exec/gdbstub.h" | |
27 | #include "hw/qdev-properties.h" | |
28 | ||
29 | static void nios2_cpu_set_pc(CPUState *cs, vaddr value) | |
30 | { | |
31 | Nios2CPU *cpu = NIOS2_CPU(cs); | |
32 | CPUNios2State *env = &cpu->env; | |
33 | ||
34 | env->regs[R_PC] = value; | |
35 | } | |
36 | ||
37 | static bool nios2_cpu_has_work(CPUState *cs) | |
38 | { | |
39 | return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); | |
40 | } | |
41 | ||
781c67ca | 42 | static void nios2_cpu_reset(DeviceState *dev) |
032c76bc | 43 | { |
781c67ca | 44 | CPUState *cs = CPU(dev); |
032c76bc CW |
45 | Nios2CPU *cpu = NIOS2_CPU(cs); |
46 | Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(cpu); | |
47 | CPUNios2State *env = &cpu->env; | |
48 | ||
49 | if (qemu_loglevel_mask(CPU_LOG_RESET)) { | |
50 | qemu_log("CPU Reset (CPU %d)\n", cs->cpu_index); | |
51 | log_cpu_state(cs, 0); | |
52 | } | |
53 | ||
781c67ca | 54 | ncc->parent_reset(dev); |
032c76bc CW |
55 | |
56 | memset(env->regs, 0, sizeof(uint32_t) * NUM_CORE_REGS); | |
57 | env->regs[R_PC] = cpu->reset_addr; | |
58 | ||
59 | #if defined(CONFIG_USER_ONLY) | |
60 | /* Start in user mode with interrupts enabled. */ | |
61 | env->regs[CR_STATUS] = CR_STATUS_U | CR_STATUS_PIE; | |
62 | #else | |
63 | env->regs[CR_STATUS] = 0; | |
64 | #endif | |
65 | } | |
66 | ||
cd2528de PM |
67 | #ifndef CONFIG_USER_ONLY |
68 | static void nios2_cpu_set_irq(void *opaque, int irq, int level) | |
69 | { | |
70 | Nios2CPU *cpu = opaque; | |
71 | CPUNios2State *env = &cpu->env; | |
72 | CPUState *cs = CPU(cpu); | |
73 | ||
05bcbcf2 | 74 | env->regs[CR_IPENDING] = deposit32(env->regs[CR_IPENDING], irq, 1, !!level); |
cd2528de PM |
75 | |
76 | env->irq_pending = env->regs[CR_IPENDING] & env->regs[CR_IENABLE]; | |
77 | ||
78 | if (env->irq_pending && (env->regs[CR_STATUS] & CR_STATUS_PIE)) { | |
79 | env->irq_pending = 0; | |
80 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); | |
81 | } else if (!env->irq_pending) { | |
82 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); | |
83 | } | |
84 | } | |
85 | #endif | |
86 | ||
032c76bc CW |
87 | static void nios2_cpu_initfn(Object *obj) |
88 | { | |
032c76bc | 89 | Nios2CPU *cpu = NIOS2_CPU(obj); |
032c76bc | 90 | |
7506ed90 | 91 | cpu_set_cpustate_pointers(cpu); |
032c76bc CW |
92 | |
93 | #if !defined(CONFIG_USER_ONLY) | |
7506ed90 | 94 | mmu_init(&cpu->env); |
cd2528de PM |
95 | |
96 | /* | |
97 | * These interrupt lines model the IIC (internal interrupt | |
98 | * controller). QEMU does not currently support the EIC | |
99 | * (external interrupt controller) -- if we did it would be | |
100 | * a separate device in hw/intc with a custom interface to | |
101 | * the CPU, and boards using it would not wire up these IRQ lines. | |
102 | */ | |
103 | qdev_init_gpio_in_named(DEVICE(cpu), nios2_cpu_set_irq, "IRQ", 32); | |
032c76bc | 104 | #endif |
032c76bc CW |
105 | } |
106 | ||
da9cbe02 | 107 | static ObjectClass *nios2_cpu_class_by_name(const char *cpu_model) |
032c76bc | 108 | { |
da9cbe02 | 109 | return object_class_by_name(TYPE_NIOS2_CPU); |
032c76bc CW |
110 | } |
111 | ||
112 | static void nios2_cpu_realizefn(DeviceState *dev, Error **errp) | |
113 | { | |
114 | CPUState *cs = CPU(dev); | |
115 | Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(dev); | |
116 | Error *local_err = NULL; | |
117 | ||
118 | cpu_exec_realizefn(cs, &local_err); | |
119 | if (local_err != NULL) { | |
120 | error_propagate(errp, local_err); | |
121 | return; | |
122 | } | |
123 | ||
124 | qemu_init_vcpu(cs); | |
125 | cpu_reset(cs); | |
126 | ||
127 | ncc->parent_realize(dev, errp); | |
128 | } | |
129 | ||
dabfe133 | 130 | #ifndef CONFIG_USER_ONLY |
032c76bc CW |
131 | static bool nios2_cpu_exec_interrupt(CPUState *cs, int interrupt_request) |
132 | { | |
133 | Nios2CPU *cpu = NIOS2_CPU(cs); | |
134 | CPUNios2State *env = &cpu->env; | |
135 | ||
136 | if ((interrupt_request & CPU_INTERRUPT_HARD) && | |
137 | (env->regs[CR_STATUS] & CR_STATUS_PIE)) { | |
138 | cs->exception_index = EXCP_IRQ; | |
139 | nios2_cpu_do_interrupt(cs); | |
140 | return true; | |
141 | } | |
142 | return false; | |
143 | } | |
dabfe133 | 144 | #endif /* !CONFIG_USER_ONLY */ |
032c76bc CW |
145 | |
146 | static void nios2_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) | |
147 | { | |
148 | /* NOTE: NiosII R2 is not supported yet. */ | |
149 | info->mach = bfd_arch_nios2; | |
dcc99bd8 | 150 | info->print_insn = print_insn_nios2; |
032c76bc CW |
151 | } |
152 | ||
a010bdbe | 153 | static int nios2_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) |
032c76bc CW |
154 | { |
155 | Nios2CPU *cpu = NIOS2_CPU(cs); | |
156 | CPUClass *cc = CPU_GET_CLASS(cs); | |
157 | CPUNios2State *env = &cpu->env; | |
158 | ||
159 | if (n > cc->gdb_num_core_regs) { | |
160 | return 0; | |
161 | } | |
162 | ||
163 | if (n < 32) { /* GP regs */ | |
164 | return gdb_get_reg32(mem_buf, env->regs[n]); | |
165 | } else if (n == 32) { /* PC */ | |
166 | return gdb_get_reg32(mem_buf, env->regs[R_PC]); | |
167 | } else if (n < 49) { /* Status regs */ | |
168 | return gdb_get_reg32(mem_buf, env->regs[n - 1]); | |
169 | } | |
170 | ||
171 | /* Invalid regs */ | |
172 | return 0; | |
173 | } | |
174 | ||
175 | static int nios2_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) | |
176 | { | |
177 | Nios2CPU *cpu = NIOS2_CPU(cs); | |
178 | CPUClass *cc = CPU_GET_CLASS(cs); | |
179 | CPUNios2State *env = &cpu->env; | |
180 | ||
181 | if (n > cc->gdb_num_core_regs) { | |
182 | return 0; | |
183 | } | |
184 | ||
185 | if (n < 32) { /* GP regs */ | |
186 | env->regs[n] = ldl_p(mem_buf); | |
187 | } else if (n == 32) { /* PC */ | |
188 | env->regs[R_PC] = ldl_p(mem_buf); | |
189 | } else if (n < 49) { /* Status regs */ | |
190 | env->regs[n - 1] = ldl_p(mem_buf); | |
191 | } | |
192 | ||
193 | return 4; | |
194 | } | |
195 | ||
196 | static Property nios2_properties[] = { | |
197 | DEFINE_PROP_BOOL("mmu_present", Nios2CPU, mmu_present, true), | |
198 | /* ALTR,pid-num-bits */ | |
199 | DEFINE_PROP_UINT32("mmu_pid_num_bits", Nios2CPU, pid_num_bits, 8), | |
200 | /* ALTR,tlb-num-ways */ | |
201 | DEFINE_PROP_UINT32("mmu_tlb_num_ways", Nios2CPU, tlb_num_ways, 16), | |
202 | /* ALTR,tlb-num-entries */ | |
203 | DEFINE_PROP_UINT32("mmu_pid_num_entries", Nios2CPU, tlb_num_entries, 256), | |
204 | DEFINE_PROP_END_OF_LIST(), | |
205 | }; | |
206 | ||
8b80bd28 PMD |
207 | #ifndef CONFIG_USER_ONLY |
208 | #include "hw/core/sysemu-cpu-ops.h" | |
209 | ||
210 | static const struct SysemuCPUOps nios2_sysemu_ops = { | |
08928c6d | 211 | .get_phys_page_debug = nios2_cpu_get_phys_page_debug, |
8b80bd28 PMD |
212 | }; |
213 | #endif | |
214 | ||
78271684 CF |
215 | #include "hw/core/tcg-cpu-ops.h" |
216 | ||
11906557 | 217 | static const struct TCGCPUOps nios2_tcg_ops = { |
78271684 | 218 | .initialize = nios2_tcg_init, |
78271684 CF |
219 | .tlb_fill = nios2_cpu_tlb_fill, |
220 | ||
221 | #ifndef CONFIG_USER_ONLY | |
dabfe133 | 222 | .cpu_exec_interrupt = nios2_cpu_exec_interrupt, |
78271684 CF |
223 | .do_interrupt = nios2_cpu_do_interrupt, |
224 | .do_unaligned_access = nios2_cpu_do_unaligned_access, | |
225 | #endif /* !CONFIG_USER_ONLY */ | |
226 | }; | |
032c76bc CW |
227 | |
228 | static void nios2_cpu_class_init(ObjectClass *oc, void *data) | |
229 | { | |
230 | DeviceClass *dc = DEVICE_CLASS(oc); | |
231 | CPUClass *cc = CPU_CLASS(oc); | |
232 | Nios2CPUClass *ncc = NIOS2_CPU_CLASS(oc); | |
233 | ||
bf853881 PMD |
234 | device_class_set_parent_realize(dc, nios2_cpu_realizefn, |
235 | &ncc->parent_realize); | |
4f67d30b | 236 | device_class_set_props(dc, nios2_properties); |
781c67ca | 237 | device_class_set_parent_reset(dc, nios2_cpu_reset, &ncc->parent_reset); |
032c76bc | 238 | |
da9cbe02 | 239 | cc->class_by_name = nios2_cpu_class_by_name; |
032c76bc | 240 | cc->has_work = nios2_cpu_has_work; |
032c76bc CW |
241 | cc->dump_state = nios2_cpu_dump_state; |
242 | cc->set_pc = nios2_cpu_set_pc; | |
243 | cc->disas_set_info = nios2_cpu_disas_set_info; | |
0137c93f | 244 | #ifndef CONFIG_USER_ONLY |
8b80bd28 | 245 | cc->sysemu_ops = &nios2_sysemu_ops; |
032c76bc CW |
246 | #endif |
247 | cc->gdb_read_register = nios2_cpu_gdb_read_register; | |
248 | cc->gdb_write_register = nios2_cpu_gdb_write_register; | |
249 | cc->gdb_num_core_regs = 49; | |
78271684 | 250 | cc->tcg_ops = &nios2_tcg_ops; |
032c76bc CW |
251 | } |
252 | ||
253 | static const TypeInfo nios2_cpu_type_info = { | |
254 | .name = TYPE_NIOS2_CPU, | |
255 | .parent = TYPE_CPU, | |
256 | .instance_size = sizeof(Nios2CPU), | |
257 | .instance_init = nios2_cpu_initfn, | |
258 | .class_size = sizeof(Nios2CPUClass), | |
259 | .class_init = nios2_cpu_class_init, | |
260 | }; | |
261 | ||
262 | static void nios2_cpu_register_types(void) | |
263 | { | |
264 | type_register_static(&nios2_cpu_type_info); | |
265 | } | |
266 | ||
267 | type_init(nios2_cpu_register_types) |