]> git.proxmox.com Git - mirror_qemu.git/blame - target/ppc/kvm.c
projects / mirror_qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
accel: Introduce the current_accel() wrapper
[mirror_qemu.git] / target / ppc / kvm.c
CommitLineData
d76d1650
AJ		 1/*
2 * PowerPC implementation of KVM hooks
3 *
4 * Copyright IBM Corp. 2007
90dc8812 5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
d76d1650
AJ		 6 *
7 * Authors:
8 * Jerone Young <jyoung5@us.ibm.com>
9 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
10 * Hollis Blanchard <hollisb@us.ibm.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2 or later.
13 * See the COPYING file in the top-level directory.
14 *
15 */
16
0d75590d 17#include "qemu/osdep.h"
eadaada1 18#include <dirent.h>
d76d1650 19#include <sys/ioctl.h>
4656e1f0 20#include <sys/vfs.h>
d76d1650
AJ		 21
22#include <linux/kvm.h>
23
24#include "qemu-common.h"
30f4b05b 25#include "qapi/error.h"
072ed5f2 26#include "qemu/error-report.h"
33c11879 27#include "cpu.h"
715d4b96 28#include "cpu-models.h"
1de7afc9 29#include "qemu/timer.h"
b3946626 30#include "sysemu/hw_accel.h"
d76d1650 31#include "kvm_ppc.h"
9c17d615
PB		 32#include "sysemu/cpus.h"
33#include "sysemu/device_tree.h"
d5aea6f3 34#include "mmu-hash64.h"
d76d1650 35
f61b4bed 36#include "hw/sysbus.h"
0d09e41a 37#include "hw/ppc/spapr.h"
7ebaf795 38#include "hw/ppc/spapr_cpu_core.h"
650d103d 39#include "hw/hw.h"
98a8b524 40#include "hw/ppc/ppc.h"
ca77ee28 41#include "migration/qemu-file-types.h"
31f2cb8f 42#include "sysemu/watchdog.h"
b36f100e 43#include "trace.h"
88365d17 44#include "exec/gdbstub.h"
4c663752 45#include "exec/memattrs.h"
9c607668 46#include "exec/ram_addr.h"
2d103aae 47#include "sysemu/hostmem.h"
f348b6d1 48#include "qemu/cutils.h"
db725815 49#include "qemu/main-loop.h"
9c607668 50#include "qemu/mmap-alloc.h"
f3d9f303 51#include "elf.h"
c64abd1f 52#include "sysemu/kvm_int.h"
f61b4bed 53
eadaada1
AG		 54#define PROC_DEVTREE_CPU "/proc/device-tree/cpus/"
55
94a8d39a
JK		 56const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
57 KVM_CAP_LAST_INFO
58};
59
c995e942 60static int cap_interrupt_unset;
90dc8812 61static int cap_segstate;
90dc8812 62static int cap_booke_sregs;
e97c3636 63static int cap_ppc_smt;
fa98fbfc 64static int cap_ppc_smt_possible;
0f5cb298 65static int cap_spapr_tce;
d6ee2a7c 66static int cap_spapr_tce_64;
da95324e 67static int cap_spapr_multitce;
9bb62a07 68static int cap_spapr_vfio;
f1af19d7 69static int cap_hior;
d67d40ea 70static int cap_one_reg;
3b961124 71static int cap_epr;
31f2cb8f 72static int cap_ppc_watchdog;
9b00ea49 73static int cap_papr;
e68cb8b4 74static int cap_htab_fd;
87a91de6 75static int cap_fixup_hcalls;
bac3bf28 76static int cap_htm; /* Hardware transactional memory support */
cf1c4cce
SB		 77static int cap_mmu_radix;
78static int cap_mmu_hash_v3;
38afd772 79static int cap_xive;
b55d295e 80static int cap_resize_hpt;
c363a37a 81static int cap_ppc_pvr_compat;
8acc2ae5
SJS		 82static int cap_ppc_safe_cache;
83static int cap_ppc_safe_bounds_check;
84static int cap_ppc_safe_indirect_branch;
8ff43ee4 85static int cap_ppc_count_cache_flush_assist;
b9a477b7 86static int cap_ppc_nested_kvm_hv;
7d050527 87static int cap_large_decr;
fc87e185 88
3c902d44
BB		 89static uint32_t debug_inst_opcode;
90
c995e942
DG		 91/*
92 * Check whether we are running with KVM-PR (instead of KVM-HV). This
96c9cff0
TH		 93 * should only be used for fallback tests - generally we should use
94 * explicit capabilities for the features we want, rather than
c995e942
DG		 95 * assuming what is/isn't available depending on the KVM variant.
96 */
96c9cff0
TH		 97static bool kvmppc_is_pr(KVMState *ks)
98{
99 /* Assume KVM-PR if the GET_PVINFO capability is available */
70a0c19e 100 return kvm_vm_check_extension(ks, KVM_CAP_PPC_GET_PVINFO) != 0;
96c9cff0
TH		 101}
102
165dc3ed 103static int kvm_ppc_register_host_cpu_type(void);
8acc2ae5 104static void kvmppc_get_cpu_characteristics(KVMState *s);
7d050527 105static int kvmppc_get_dec_bits(void);
5ba4576b 106
b16565b3 107int kvm_arch_init(MachineState *ms, KVMState *s)
d76d1650 108{
fc87e185 109 cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ);
90dc8812 110 cap_segstate = kvm_check_extension(s, KVM_CAP_PPC_SEGSTATE);
90dc8812 111 cap_booke_sregs = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_SREGS);
6977afda 112 cap_ppc_smt_possible = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT_POSSIBLE);
0f5cb298 113 cap_spapr_tce = kvm_check_extension(s, KVM_CAP_SPAPR_TCE);
d6ee2a7c 114 cap_spapr_tce_64 = kvm_check_extension(s, KVM_CAP_SPAPR_TCE_64);
da95324e 115 cap_spapr_multitce = kvm_check_extension(s, KVM_CAP_SPAPR_MULTITCE);
9ded780c 116 cap_spapr_vfio = kvm_vm_check_extension(s, KVM_CAP_SPAPR_TCE_VFIO);
d67d40ea 117 cap_one_reg = kvm_check_extension(s, KVM_CAP_ONE_REG);
f1af19d7 118 cap_hior = kvm_check_extension(s, KVM_CAP_PPC_HIOR);
3b961124 119 cap_epr = kvm_check_extension(s, KVM_CAP_PPC_EPR);
31f2cb8f 120 cap_ppc_watchdog = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_WATCHDOG);
c995e942
DG		 121 /*
122 * Note: we don't set cap_papr here, because this capability is
123 * only activated after this by kvmppc_set_papr()
124 */
6977afda 125 cap_htab_fd = kvm_vm_check_extension(s, KVM_CAP_PPC_HTAB_FD);
87a91de6 126 cap_fixup_hcalls = kvm_check_extension(s, KVM_CAP_PPC_FIXUP_HCALL);
fa98fbfc 127 cap_ppc_smt = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT);
bac3bf28 128 cap_htm = kvm_vm_check_extension(s, KVM_CAP_PPC_HTM);
cf1c4cce
SB		 129 cap_mmu_radix = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_RADIX);
130 cap_mmu_hash_v3 = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_HASH_V3);
38afd772 131 cap_xive = kvm_vm_check_extension(s, KVM_CAP_PPC_IRQ_XIVE);
b55d295e 132 cap_resize_hpt = kvm_vm_check_extension(s, KVM_CAP_SPAPR_RESIZE_HPT);
8acc2ae5 133 kvmppc_get_cpu_characteristics(s);
b9a477b7 134 cap_ppc_nested_kvm_hv = kvm_vm_check_extension(s, KVM_CAP_PPC_NESTED_HV);
7d050527 135 cap_large_decr = kvmppc_get_dec_bits();
c363a37a
DHB		 136 /*
137 * Note: setting it to false because there is not such capability
138 * in KVM at this moment.
139 *
140 * TODO: call kvm_vm_check_extension() with the right capability
c995e942
DG		 141 * after the kernel starts implementing it.
142 */
c363a37a 143 cap_ppc_pvr_compat = false;
fc87e185 144
1e8f51e8
SB		 145 if (!kvm_check_extension(s, KVM_CAP_PPC_IRQ_LEVEL)) {
146 error_report("KVM: Host kernel doesn't have level irq capability");
147 exit(1);
fc87e185
AG		 148 }
149
165dc3ed 150 kvm_ppc_register_host_cpu_type();
5ba4576b 151
d76d1650
AJ		 152 return 0;
153}
154
4376c40d 155int kvm_arch_irqchip_create(KVMState *s)
d525ffab
PB		 156{
157 return 0;
158}
159
1bc22652 160static int kvm_arch_sync_sregs(PowerPCCPU *cpu)
d76d1650 161{
1bc22652
AF		 162 CPUPPCState *cenv = &cpu->env;
163 CPUState *cs = CPU(cpu);
861bbc80 164 struct kvm_sregs sregs;
5666ca4a
SW		 165 int ret;
166
167 if (cenv->excp_model == POWERPC_EXCP_BOOKE) {
c995e942
DG		 168 /*
169 * What we're really trying to say is "if we're on BookE, we
170 * use the native PVR for now". This is the only sane way to
171 * check it though, so we potentially confuse users that they
172 * can run BookE guests on BookS. Let's hope nobody dares
173 * enough :)
174 */
5666ca4a
SW		 175 return 0;
176 } else {
90dc8812 177 if (!cap_segstate) {
64e07be5
AG		 178 fprintf(stderr, "kvm error: missing PVR setting capability\n");
179 return -ENOSYS;
5666ca4a 180 }
5666ca4a
SW		 181 }
182
1bc22652 183 ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs);
5666ca4a
SW		 184 if (ret) {
185 return ret;
186 }
861bbc80
AG		 187
188 sregs.pvr = cenv->spr[SPR_PVR];
1bc22652 189 return kvm_vcpu_ioctl(cs, KVM_SET_SREGS, &sregs);
5666ca4a
SW		 190}
191
93dd5e85 192/* Set up a shared TLB array with KVM */
1bc22652 193static int kvm_booke206_tlb_init(PowerPCCPU *cpu)
93dd5e85 194{
1bc22652
AF		 195 CPUPPCState *env = &cpu->env;
196 CPUState *cs = CPU(cpu);
93dd5e85
SW		 197 struct kvm_book3e_206_tlb_params params = {};
198 struct kvm_config_tlb cfg = {};
93dd5e85
SW		 199 unsigned int entries = 0;
200 int ret, i;
201
202 if (!kvm_enabled() ||
a60f24b5 203 !kvm_check_extension(cs->kvm_state, KVM_CAP_SW_TLB)) {
93dd5e85
SW		 204 return 0;
205 }
206
207 assert(ARRAY_SIZE(params.tlb_sizes) == BOOKE206_MAX_TLBN);
208
209 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
210 params.tlb_sizes[i] = booke206_tlb_size(env, i);
211 params.tlb_ways[i] = booke206_tlb_ways(env, i);
212 entries += params.tlb_sizes[i];
213 }
214
215 assert(entries == env->nb_tlb);
216 assert(sizeof(struct kvm_book3e_206_tlb_entry) == sizeof(ppcmas_tlb_t));
217
218 env->tlb_dirty = true;
219
220 cfg.array = (uintptr_t)env->tlb.tlbm;
221 cfg.array_len = sizeof(ppcmas_tlb_t) * entries;
222 cfg.params = (uintptr_t)&params;
223 cfg.mmu_type = KVM_MMU_FSL_BOOKE_NOHV;
224
48add816 225 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_SW_TLB, 0, (uintptr_t)&cfg);
93dd5e85
SW		 226 if (ret < 0) {
227 fprintf(stderr, "%s: couldn't enable KVM_CAP_SW_TLB: %s\n",
228 __func__, strerror(-ret));
229 return ret;
230 }
231
232 env->kvm_sw_tlb = true;
233 return 0;
234}
235
4656e1f0
BH		 236
237#if defined(TARGET_PPC64)
ab256960 238static void kvm_get_smmu_info(struct kvm_ppc_smmu_info *info, Error **errp)
4656e1f0 239{
71d0f1ea 240 int ret;
a60f24b5 241
ab256960
GK		 242 assert(kvm_state != NULL);
243
244 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_GET_SMMU_INFO)) {
71d0f1ea
GK		 245 error_setg(errp, "KVM doesn't expose the MMU features it supports");
246 error_append_hint(errp, "Consider switching to a newer KVM\n");
247 return;
4656e1f0 248 }
4656e1f0 249
ab256960 250 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_SMMU_INFO, info);
71d0f1ea
GK		 251 if (ret == 0) {
252 return;
4656e1f0
BH		 253 }
254
71d0f1ea
GK		 255 error_setg_errno(errp, -ret,
256 "KVM failed to provide the MMU features it supports");
4656e1f0
BH		 257}
258
c64abd1f
SB		 259struct ppc_radix_page_info *kvm_get_radix_page_info(void)
260{
261 KVMState *s = KVM_STATE(current_machine->accelerator);
262 struct ppc_radix_page_info *radix_page_info;
263 struct kvm_ppc_rmmu_info rmmu_info;
264 int i;
265
266 if (!kvm_check_extension(s, KVM_CAP_PPC_MMU_RADIX)) {
267 return NULL;
268 }
269 if (kvm_vm_ioctl(s, KVM_PPC_GET_RMMU_INFO, &rmmu_info)) {
270 return NULL;
271 }
272 radix_page_info = g_malloc0(sizeof(*radix_page_info));
273 radix_page_info->count = 0;
274 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
275 if (rmmu_info.ap_encodings[i]) {
276 radix_page_info->entries[i] = rmmu_info.ap_encodings[i];
277 radix_page_info->count++;
278 }
279 }
280 return radix_page_info;
281}
282
b4db5413
SJS		 283target_ulong kvmppc_configure_v3_mmu(PowerPCCPU *cpu,
284 bool radix, bool gtse,
285 uint64_t proc_tbl)
286{
287 CPUState *cs = CPU(cpu);
288 int ret;
289 uint64_t flags = 0;
290 struct kvm_ppc_mmuv3_cfg cfg = {
291 .process_table = proc_tbl,
292 };
293
294 if (radix) {
295 flags |= KVM_PPC_MMUV3_RADIX;
296 }
297 if (gtse) {
298 flags |= KVM_PPC_MMUV3_GTSE;
299 }
300 cfg.flags = flags;
301 ret = kvm_vm_ioctl(cs->kvm_state, KVM_PPC_CONFIGURE_V3_MMU, &cfg);
302 switch (ret) {
303 case 0:
304 return H_SUCCESS;
305 case -EINVAL:
306 return H_PARAMETER;
307 case -ENODEV:
308 return H_NOT_AVAILABLE;
309 default:
310 return H_HARDWARE;
311 }
312}
313
24c6863c
DG		 314bool kvmppc_hpt_needs_host_contiguous_pages(void)
315{
24c6863c
DG		 316 static struct kvm_ppc_smmu_info smmu_info;
317
318 if (!kvm_enabled()) {
319 return false;
320 }
321
ab256960 322 kvm_get_smmu_info(&smmu_info, &error_fatal);
24c6863c
DG		 323 return !!(smmu_info.flags & KVM_PPC_PAGE_SIZES_REAL);
324}
325
e5ca28ec 326void kvm_check_mmu(PowerPCCPU *cpu, Error **errp)
4656e1f0 327{
e5ca28ec 328 struct kvm_ppc_smmu_info smmu_info;
4656e1f0 329 int iq, ik, jq, jk;
71d0f1ea 330 Error *local_err = NULL;
4656e1f0 331
e5ca28ec
DG		 332 /* For now, we only have anything to check on hash64 MMUs */
333 if (!cpu->hash64_opts || !kvm_enabled()) {
4656e1f0
BH		 334 return;
335 }
336
ab256960 337 kvm_get_smmu_info(&smmu_info, &local_err);
71d0f1ea
GK		 338 if (local_err) {
339 error_propagate(errp, local_err);
340 return;
341 }
4656e1f0 342
e5ca28ec
DG		 343 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)
344 && !(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) {
345 error_setg(errp,
346 "KVM does not support 1TiB segments which guest expects");
347 return;
df587133 348 }
4656e1f0 349
e5ca28ec
DG		 350 if (smmu_info.slb_size < cpu->hash64_opts->slb_size) {
351 error_setg(errp, "KVM only supports %u SLB entries, but guest needs %u",
352 smmu_info.slb_size, cpu->hash64_opts->slb_size);
353 return;
90da0d5a
BH		 354 }
355
08215d8f 356 /*
e5ca28ec
DG		 357 * Verify that every pagesize supported by the cpu model is
358 * supported by KVM with the same encodings
08215d8f 359 */
e5ca28ec 360 for (iq = 0; iq < ARRAY_SIZE(cpu->hash64_opts->sps); iq++) {
b07c59f7 361 PPCHash64SegmentPageSizes *qsps = &cpu->hash64_opts->sps[iq];
e5ca28ec 362 struct kvm_ppc_one_seg_page_size *ksps;
4656e1f0 363
e5ca28ec
DG		 364 for (ik = 0; ik < ARRAY_SIZE(smmu_info.sps); ik++) {
365 if (qsps->page_shift == smmu_info.sps[ik].page_shift) {
4656e1f0
BH		 366 break;
367 }
368 }
e5ca28ec
DG		 369 if (ik >= ARRAY_SIZE(smmu_info.sps)) {
370 error_setg(errp, "KVM doesn't support for base page shift %u",
371 qsps->page_shift);
372 return;
373 }
374
375 ksps = &smmu_info.sps[ik];
376 if (ksps->slb_enc != qsps->slb_enc) {
377 error_setg(errp,
378"KVM uses SLB encoding 0x%x for page shift %u, but guest expects 0x%x",
379 ksps->slb_enc, ksps->page_shift, qsps->slb_enc);
380 return;
381 }
382
383 for (jq = 0; jq < ARRAY_SIZE(qsps->enc); jq++) {
384 for (jk = 0; jk < ARRAY_SIZE(ksps->enc); jk++) {
385 if (qsps->enc[jq].page_shift == ksps->enc[jk].page_shift) {
386 break;
387 }
388 }
389
390 if (jk >= ARRAY_SIZE(ksps->enc)) {
391 error_setg(errp, "KVM doesn't support page shift %u/%u",
392 qsps->enc[jq].page_shift, qsps->page_shift);
393 return;
394 }
395 if (qsps->enc[jq].pte_enc != ksps->enc[jk].pte_enc) {
396 error_setg(errp,
397"KVM uses PTE encoding 0x%x for page shift %u/%u, but guest expects 0x%x",
398 ksps->enc[jk].pte_enc, qsps->enc[jq].page_shift,
399 qsps->page_shift, qsps->enc[jq].pte_enc);
400 return;
401 }
4656e1f0
BH		 402 }
403 }
4656e1f0 404
e5ca28ec 405 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) {
c995e942
DG		 406 /*
407 * Mostly what guest pagesizes we can use are related to the
e5ca28ec
DG		 408 * host pages used to map guest RAM, which is handled in the
409 * platform code. Cache-Inhibited largepages (64k) however are
410 * used for I/O, so if they're mapped to the host at all it
411 * will be a normal mapping, not a special hugepage one used
c995e942
DG		 412 * for RAM.
413 */
038adc2f 414 if (qemu_real_host_page_size < 0x10000) {
e5ca28ec
DG		 415 error_setg(errp,
416 "KVM can't supply 64kiB CI pages, which guest expects");
417 }
418 }
4656e1f0 419}
4656e1f0
BH		 420#endif /* !defined (TARGET_PPC64) */
421
b164e48e
EH		 422unsigned long kvm_arch_vcpu_id(CPUState *cpu)
423{
2e886fb3 424 return POWERPC_CPU(cpu)->vcpu_id;
b164e48e
EH		 425}
426
c995e942
DG		 427/*
428 * e500 supports 2 h/w breakpoint and 2 watchpoint. book3s supports
429 * only 1 watchpoint, so array size of 4 is sufficient for now.
88365d17
BB		 430 */
431#define MAX_HW_BKPTS 4
432
433static struct HWBreakpoint {
434 target_ulong addr;
435 int type;
436} hw_debug_points[MAX_HW_BKPTS];
437
438static CPUWatchpoint hw_watchpoint;
439
440/* Default there is no breakpoint and watchpoint supported */
441static int max_hw_breakpoint;
442static int max_hw_watchpoint;
443static int nb_hw_breakpoint;
444static int nb_hw_watchpoint;
445
446static void kvmppc_hw_debug_points_init(CPUPPCState *cenv)
447{
448 if (cenv->excp_model == POWERPC_EXCP_BOOKE) {
449 max_hw_breakpoint = 2;
450 max_hw_watchpoint = 2;
451 }
452
453 if ((max_hw_breakpoint + max_hw_watchpoint) > MAX_HW_BKPTS) {
454 fprintf(stderr, "Error initializing h/w breakpoints\n");
455 return;
456 }
457}
458
20d695a9 459int kvm_arch_init_vcpu(CPUState *cs)
5666ca4a 460{
20d695a9
AF		 461 PowerPCCPU *cpu = POWERPC_CPU(cs);
462 CPUPPCState *cenv = &cpu->env;
5666ca4a
SW		 463 int ret;
464
4656e1f0 465 /* Synchronize sregs with kvm */
1bc22652 466 ret = kvm_arch_sync_sregs(cpu);
5666ca4a 467 if (ret) {
388e47c7
TH		 468 if (ret == -EINVAL) {
469 error_report("Register sync failed... If you're using kvm-hv.ko,"
470 " only \"-cpu host\" is possible");
471 }
5666ca4a
SW		 472 return ret;
473 }
861bbc80 474
93dd5e85
SW		 475 switch (cenv->mmu_model) {
476 case POWERPC_MMU_BOOKE206:
7f516c96 477 /* This target supports access to KVM's guest TLB */
1bc22652 478 ret = kvm_booke206_tlb_init(cpu);
93dd5e85 479 break;
7f516c96
TH		 480 case POWERPC_MMU_2_07:
481 if (!cap_htm && !kvmppc_is_pr(cs->kvm_state)) {
c995e942
DG		 482 /*
483 * KVM-HV has transactional memory on POWER8 also without
484 * the KVM_CAP_PPC_HTM extension, so enable it here
485 * instead as long as it's availble to userspace on the
486 * host.
487 */
f3d9f303
SB		 488 if (qemu_getauxval(AT_HWCAP2) & PPC_FEATURE2_HAS_HTM) {
489 cap_htm = true;
490 }
7f516c96
TH		 491 }
492 break;
93dd5e85
SW		 493 default:
494 break;
495 }
496
3c902d44 497 kvm_get_one_reg(cs, KVM_REG_PPC_DEBUG_INST, &debug_inst_opcode);
88365d17 498 kvmppc_hw_debug_points_init(cenv);
3c902d44 499
861bbc80 500 return ret;
d76d1650
AJ		 501}
502
b1115c99
LA		 503int kvm_arch_destroy_vcpu(CPUState *cs)
504{
505 return 0;
506}
507
1bc22652 508static void kvm_sw_tlb_put(PowerPCCPU *cpu)
93dd5e85 509{
1bc22652
AF		 510 CPUPPCState *env = &cpu->env;
511 CPUState *cs = CPU(cpu);
93dd5e85
SW		 512 struct kvm_dirty_tlb dirty_tlb;
513 unsigned char *bitmap;
514 int ret;
515
516 if (!env->kvm_sw_tlb) {
517 return;
518 }
519
520 bitmap = g_malloc((env->nb_tlb + 7) / 8);
521 memset(bitmap, 0xFF, (env->nb_tlb + 7) / 8);
522
523 dirty_tlb.bitmap = (uintptr_t)bitmap;
524 dirty_tlb.num_dirty = env->nb_tlb;
525
1bc22652 526 ret = kvm_vcpu_ioctl(cs, KVM_DIRTY_TLB, &dirty_tlb);
93dd5e85
SW		 527 if (ret) {
528 fprintf(stderr, "%s: KVM_DIRTY_TLB: %s\n",
529 __func__, strerror(-ret));
530 }
531
532 g_free(bitmap);
533}
534
d67d40ea
DG		 535static void kvm_get_one_spr(CPUState *cs, uint64_t id, int spr)
536{
537 PowerPCCPU *cpu = POWERPC_CPU(cs);
538 CPUPPCState *env = &cpu->env;
539 union {
540 uint32_t u32;
541 uint64_t u64;
542 } val;
543 struct kvm_one_reg reg = {
544 .id = id,
545 .addr = (uintptr_t) &val,
546 };
547 int ret;
548
549 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
550 if (ret != 0) {
b36f100e 551 trace_kvm_failed_spr_get(spr, strerror(errno));
d67d40ea
DG		 552 } else {
553 switch (id & KVM_REG_SIZE_MASK) {
554 case KVM_REG_SIZE_U32:
555 env->spr[spr] = val.u32;
556 break;
557
558 case KVM_REG_SIZE_U64:
559 env->spr[spr] = val.u64;
560 break;
561
562 default:
563 /* Don't handle this size yet */
564 abort();
565 }
566 }
567}
568
569static void kvm_put_one_spr(CPUState *cs, uint64_t id, int spr)
570{
571 PowerPCCPU *cpu = POWERPC_CPU(cs);
572 CPUPPCState *env = &cpu->env;
573 union {
574 uint32_t u32;
575 uint64_t u64;
576 } val;
577 struct kvm_one_reg reg = {
578 .id = id,
579 .addr = (uintptr_t) &val,
580 };
581 int ret;
582
583 switch (id & KVM_REG_SIZE_MASK) {
584 case KVM_REG_SIZE_U32:
585 val.u32 = env->spr[spr];
586 break;
587
588 case KVM_REG_SIZE_U64:
589 val.u64 = env->spr[spr];
590 break;
591
592 default:
593 /* Don't handle this size yet */
594 abort();
595 }
596
597 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
598 if (ret != 0) {
b36f100e 599 trace_kvm_failed_spr_set(spr, strerror(errno));
d67d40ea
DG		 600 }
601}
602
70b79849
DG		 603static int kvm_put_fp(CPUState *cs)
604{
605 PowerPCCPU *cpu = POWERPC_CPU(cs);
606 CPUPPCState *env = &cpu->env;
607 struct kvm_one_reg reg;
608 int i;
609 int ret;
610
611 if (env->insns_flags & PPC_FLOAT) {
612 uint64_t fpscr = env->fpscr;
613 bool vsx = !!(env->insns_flags2 & PPC2_VSX);
614
615 reg.id = KVM_REG_PPC_FPSCR;
616 reg.addr = (uintptr_t)&fpscr;
617 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
618 if (ret < 0) {
8d83cbf1 619 trace_kvm_failed_fpscr_set(strerror(errno));
70b79849
DG		 620 return ret;
621 }
622
623 for (i = 0; i < 32; i++) {
624 uint64_t vsr[2];
ef96e3ae
MCA		 625 uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i);
626 uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i);
70b79849 627
3a4b791b 628#ifdef HOST_WORDS_BIGENDIAN
ef96e3ae
MCA		 629 vsr[0] = float64_val(*fpr);
630 vsr[1] = *vsrl;
3a4b791b 631#else
ef96e3ae
MCA		 632 vsr[0] = *vsrl;
633 vsr[1] = float64_val(*fpr);
3a4b791b 634#endif
70b79849
DG		 635 reg.addr = (uintptr_t) &vsr;
636 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i);
637
638 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
639 if (ret < 0) {
8d83cbf1
GK		 640 trace_kvm_failed_fp_set(vsx ? "VSR" : "FPR", i,
641 strerror(errno));
70b79849
DG		 642 return ret;
643 }
644 }
645 }
646
647 if (env->insns_flags & PPC_ALTIVEC) {
648 reg.id = KVM_REG_PPC_VSCR;
649 reg.addr = (uintptr_t)&env->vscr;
650 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
651 if (ret < 0) {
8d83cbf1 652 trace_kvm_failed_vscr_set(strerror(errno));
70b79849
DG		 653 return ret;
654 }
655
656 for (i = 0; i < 32; i++) {
657 reg.id = KVM_REG_PPC_VR(i);
ef96e3ae 658 reg.addr = (uintptr_t)cpu_avr_ptr(env, i);
70b79849
DG		 659 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
660 if (ret < 0) {
8d83cbf1 661 trace_kvm_failed_vr_set(i, strerror(errno));
70b79849
DG		 662 return ret;
663 }
664 }
665 }
666
667 return 0;
668}
669
670static int kvm_get_fp(CPUState *cs)
671{
672 PowerPCCPU *cpu = POWERPC_CPU(cs);
673 CPUPPCState *env = &cpu->env;
674 struct kvm_one_reg reg;
675 int i;
676 int ret;
677
678 if (env->insns_flags & PPC_FLOAT) {
679 uint64_t fpscr;
680 bool vsx = !!(env->insns_flags2 & PPC2_VSX);
681
682 reg.id = KVM_REG_PPC_FPSCR;
683 reg.addr = (uintptr_t)&fpscr;
684 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
685 if (ret < 0) {
8d83cbf1 686 trace_kvm_failed_fpscr_get(strerror(errno));
70b79849
DG		 687 return ret;
688 } else {
689 env->fpscr = fpscr;
690 }
691
692 for (i = 0; i < 32; i++) {
693 uint64_t vsr[2];
ef96e3ae
MCA		 694 uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i);
695 uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i);
70b79849
DG		 696
697 reg.addr = (uintptr_t) &vsr;
698 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i);
699
700 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
701 if (ret < 0) {
8d83cbf1
GK		 702 trace_kvm_failed_fp_get(vsx ? "VSR" : "FPR", i,
703 strerror(errno));
70b79849
DG		 704 return ret;
705 } else {
3a4b791b 706#ifdef HOST_WORDS_BIGENDIAN
ef96e3ae 707 *fpr = vsr[0];
70b79849 708 if (vsx) {
ef96e3ae 709 *vsrl = vsr[1];
70b79849 710 }
3a4b791b 711#else
ef96e3ae 712 *fpr = vsr[1];
3a4b791b 713 if (vsx) {
ef96e3ae 714 *vsrl = vsr[0];
3a4b791b
GK		 715 }
716#endif
70b79849
DG		 717 }
718 }
719 }
720
721 if (env->insns_flags & PPC_ALTIVEC) {
722 reg.id = KVM_REG_PPC_VSCR;
723 reg.addr = (uintptr_t)&env->vscr;
724 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
725 if (ret < 0) {
8d83cbf1 726 trace_kvm_failed_vscr_get(strerror(errno));
70b79849
DG		 727 return ret;
728 }
729
730 for (i = 0; i < 32; i++) {
731 reg.id = KVM_REG_PPC_VR(i);
ef96e3ae 732 reg.addr = (uintptr_t)cpu_avr_ptr(env, i);
70b79849
DG		 733 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
734 if (ret < 0) {
8d83cbf1 735 trace_kvm_failed_vr_get(i, strerror(errno));
70b79849
DG		 736 return ret;
737 }
738 }
739 }
740
741 return 0;
742}
743
9b00ea49
DG		 744#if defined(TARGET_PPC64)
745static int kvm_get_vpa(CPUState *cs)
746{
747 PowerPCCPU *cpu = POWERPC_CPU(cs);
ce2918cb 748 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
9b00ea49
DG		 749 struct kvm_one_reg reg;
750 int ret;
751
752 reg.id = KVM_REG_PPC_VPA_ADDR;
7388efaf 753 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
9b00ea49
DG		 754 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
755 if (ret < 0) {
8d83cbf1 756 trace_kvm_failed_vpa_addr_get(strerror(errno));
9b00ea49
DG		 757 return ret;
758 }
759
7388efaf
DG		 760 assert((uintptr_t)&spapr_cpu->slb_shadow_size
761 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8));
9b00ea49 762 reg.id = KVM_REG_PPC_VPA_SLB;
7388efaf 763 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr;
9b00ea49
DG		 764 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
765 if (ret < 0) {
8d83cbf1 766 trace_kvm_failed_slb_get(strerror(errno));
9b00ea49
DG		 767 return ret;
768 }
769
7388efaf
DG		 770 assert((uintptr_t)&spapr_cpu->dtl_size
771 == ((uintptr_t)&spapr_cpu->dtl_addr + 8));
9b00ea49 772 reg.id = KVM_REG_PPC_VPA_DTL;
7388efaf 773 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr;
9b00ea49
DG		 774 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
775 if (ret < 0) {
8d83cbf1 776 trace_kvm_failed_dtl_get(strerror(errno));
9b00ea49
DG		 777 return ret;
778 }
779
780 return 0;
781}
782
783static int kvm_put_vpa(CPUState *cs)
784{
785 PowerPCCPU *cpu = POWERPC_CPU(cs);
ce2918cb 786 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
9b00ea49
DG		 787 struct kvm_one_reg reg;
788 int ret;
789
c995e942
DG		 790 /*
791 * SLB shadow or DTL can't be registered unless a master VPA is
9b00ea49
DG		 792 * registered. That means when restoring state, if a VPA *is*
793 * registered, we need to set that up first. If not, we need to
c995e942
DG		 794 * deregister the others before deregistering the master VPA
795 */
7388efaf
DG		 796 assert(spapr_cpu->vpa_addr
797 || !(spapr_cpu->slb_shadow_addr || spapr_cpu->dtl_addr));
9b00ea49 798
7388efaf 799 if (spapr_cpu->vpa_addr) {
9b00ea49 800 reg.id = KVM_REG_PPC_VPA_ADDR;
7388efaf 801 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
9b00ea49
DG		 802 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
803 if (ret < 0) {
8d83cbf1 804 trace_kvm_failed_vpa_addr_set(strerror(errno));
9b00ea49
DG		 805 return ret;
806 }
807 }
808
7388efaf
DG		 809 assert((uintptr_t)&spapr_cpu->slb_shadow_size
810 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8));
9b00ea49 811 reg.id = KVM_REG_PPC_VPA_SLB;
7388efaf 812 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr;
9b00ea49
DG		 813 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
814 if (ret < 0) {
8d83cbf1 815 trace_kvm_failed_slb_set(strerror(errno));
9b00ea49
DG		 816 return ret;
817 }
818
7388efaf
DG		 819 assert((uintptr_t)&spapr_cpu->dtl_size
820 == ((uintptr_t)&spapr_cpu->dtl_addr + 8));
9b00ea49 821 reg.id = KVM_REG_PPC_VPA_DTL;
7388efaf 822 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr;
9b00ea49
DG		 823 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
824 if (ret < 0) {
8d83cbf1 825 trace_kvm_failed_dtl_set(strerror(errno));
9b00ea49
DG		 826 return ret;
827 }
828
7388efaf 829 if (!spapr_cpu->vpa_addr) {
9b00ea49 830 reg.id = KVM_REG_PPC_VPA_ADDR;
7388efaf 831 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
9b00ea49
DG		 832 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
833 if (ret < 0) {
8d83cbf1 834 trace_kvm_failed_null_vpa_addr_set(strerror(errno));
9b00ea49
DG		 835 return ret;
836 }
837 }
838
839 return 0;
840}
841#endif /* TARGET_PPC64 */
842
e5c0d3ce 843int kvmppc_put_books_sregs(PowerPCCPU *cpu)
a7a00a72
DG		 844{
845 CPUPPCState *env = &cpu->env;
846 struct kvm_sregs sregs;
847 int i;
848
849 sregs.pvr = env->spr[SPR_PVR];
850
1ec26c75
GK		 851 if (cpu->vhyp) {
852 PPCVirtualHypervisorClass *vhc =
853 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
854 sregs.u.s.sdr1 = vhc->encode_hpt_for_kvm_pr(cpu->vhyp);
855 } else {
856 sregs.u.s.sdr1 = env->spr[SPR_SDR1];
857 }
a7a00a72
DG		 858
859 /* Sync SLB */
860#ifdef TARGET_PPC64
861 for (i = 0; i < ARRAY_SIZE(env->slb); i++) {
862 sregs.u.s.ppc64.slb[i].slbe = env->slb[i].esid;
863 if (env->slb[i].esid & SLB_ESID_V) {
864 sregs.u.s.ppc64.slb[i].slbe |= i;
865 }
866 sregs.u.s.ppc64.slb[i].slbv = env->slb[i].vsid;
867 }
868#endif
869
870 /* Sync SRs */
871 for (i = 0; i < 16; i++) {
872 sregs.u.s.ppc32.sr[i] = env->sr[i];
873 }
874
875 /* Sync BATs */
876 for (i = 0; i < 8; i++) {
877 /* Beware. We have to swap upper and lower bits here */
878 sregs.u.s.ppc32.dbat[i] = ((uint64_t)env->DBAT[0][i] << 32)
879 | env->DBAT[1][i];
880 sregs.u.s.ppc32.ibat[i] = ((uint64_t)env->IBAT[0][i] << 32)
881 | env->IBAT[1][i];
882 }
883
884 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
885}
886
20d695a9 887int kvm_arch_put_registers(CPUState *cs, int level)
d76d1650 888{
20d695a9
AF		 889 PowerPCCPU *cpu = POWERPC_CPU(cs);
890 CPUPPCState *env = &cpu->env;
d76d1650
AJ		 891 struct kvm_regs regs;
892 int ret;
893 int i;
894
1bc22652
AF		 895 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, &regs);
896 if (ret < 0) {
d76d1650 897 return ret;
1bc22652 898 }
d76d1650
AJ		 899
900 regs.ctr = env->ctr;
901 regs.lr = env->lr;
da91a00f 902 regs.xer = cpu_read_xer(env);
d76d1650
AJ		 903 regs.msr = env->msr;
904 regs.pc = env->nip;
905
906 regs.srr0 = env->spr[SPR_SRR0];
907 regs.srr1 = env->spr[SPR_SRR1];
908
909 regs.sprg0 = env->spr[SPR_SPRG0];
910 regs.sprg1 = env->spr[SPR_SPRG1];
911 regs.sprg2 = env->spr[SPR_SPRG2];
912 regs.sprg3 = env->spr[SPR_SPRG3];
913 regs.sprg4 = env->spr[SPR_SPRG4];
914 regs.sprg5 = env->spr[SPR_SPRG5];
915 regs.sprg6 = env->spr[SPR_SPRG6];
916 regs.sprg7 = env->spr[SPR_SPRG7];
917
90dc8812
SW		 918 regs.pid = env->spr[SPR_BOOKE_PID];
919
c995e942 920 for (i = 0; i < 32; i++) {
d76d1650 921 regs.gpr[i] = env->gpr[i];
c995e942 922 }
d76d1650 923
4bddaf55
AK		 924 regs.cr = 0;
925 for (i = 0; i < 8; i++) {
926 regs.cr |= (env->crf[i] & 15) << (4 * (7 - i));
927 }
928
1bc22652 929 ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, &regs);
c995e942 930 if (ret < 0) {
d76d1650 931 return ret;
c995e942 932 }
d76d1650 933
70b79849
DG		 934 kvm_put_fp(cs);
935
93dd5e85 936 if (env->tlb_dirty) {
1bc22652 937 kvm_sw_tlb_put(cpu);
93dd5e85
SW		 938 env->tlb_dirty = false;
939 }
940
f1af19d7 941 if (cap_segstate && (level >= KVM_PUT_RESET_STATE)) {
a7a00a72
DG		 942 ret = kvmppc_put_books_sregs(cpu);
943 if (ret < 0) {
f1af19d7
DG		 944 return ret;
945 }
946 }
947
948 if (cap_hior && (level >= KVM_PUT_RESET_STATE)) {
d67d40ea
DG		 949 kvm_put_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR);
950 }
f1af19d7 951
d67d40ea
DG		 952 if (cap_one_reg) {
953 int i;
954
c995e942
DG		 955 /*
956 * We deliberately ignore errors here, for kernels which have
d67d40ea
DG		 957 * the ONE_REG calls, but don't support the specific
958 * registers, there's a reasonable chance things will still
c995e942
DG		 959 * work, at least until we try to migrate.
960 */
d67d40ea
DG		 961 for (i = 0; i < 1024; i++) {
962 uint64_t id = env->spr_cb[i].one_reg_id;
963
964 if (id != 0) {
965 kvm_put_one_spr(cs, id, i);
966 }
f1af19d7 967 }
9b00ea49
DG		 968
969#ifdef TARGET_PPC64
80b3f79b
AK		 970 if (msr_ts) {
971 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
972 kvm_set_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
973 }
974 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) {
975 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]);
976 }
977 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr);
978 kvm_set_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr);
979 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr);
980 kvm_set_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr);
981 kvm_set_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr);
982 kvm_set_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr);
983 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave);
984 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr);
985 kvm_set_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr);
986 kvm_set_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar);
987 }
988
9b00ea49
DG		 989 if (cap_papr) {
990 if (kvm_put_vpa(cs) < 0) {
8d83cbf1 991 trace_kvm_failed_put_vpa();
9b00ea49
DG		 992 }
993 }
98a8b524
AK		 994
995 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset);
972bd576
AK		 996
997 if (level > KVM_PUT_RUNTIME_STATE) {
998 kvm_put_one_spr(cs, KVM_REG_PPC_DPDES, SPR_DPDES);
999 }
9b00ea49 1000#endif /* TARGET_PPC64 */
f1af19d7
DG		 1001 }
1002
d76d1650
AJ		 1003 return ret;
1004}
1005
c371c2e3
BB		 1006static void kvm_sync_excp(CPUPPCState *env, int vector, int ivor)
1007{
1008 env->excp_vectors[vector] = env->spr[ivor] + env->spr[SPR_BOOKE_IVPR];
1009}
1010
a7a00a72
DG		 1011static int kvmppc_get_booke_sregs(PowerPCCPU *cpu)
1012{
1013 CPUPPCState *env = &cpu->env;
1014 struct kvm_sregs sregs;
1015 int ret;
1016
1017 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1018 if (ret < 0) {
1019 return ret;
1020 }
1021
1022 if (sregs.u.e.features & KVM_SREGS_E_BASE) {
1023 env->spr[SPR_BOOKE_CSRR0] = sregs.u.e.csrr0;
1024 env->spr[SPR_BOOKE_CSRR1] = sregs.u.e.csrr1;
1025 env->spr[SPR_BOOKE_ESR] = sregs.u.e.esr;
1026 env->spr[SPR_BOOKE_DEAR] = sregs.u.e.dear;
1027 env->spr[SPR_BOOKE_MCSR] = sregs.u.e.mcsr;
1028 env->spr[SPR_BOOKE_TSR] = sregs.u.e.tsr;
1029 env->spr[SPR_BOOKE_TCR] = sregs.u.e.tcr;
1030 env->spr[SPR_DECR] = sregs.u.e.dec;
1031 env->spr[SPR_TBL] = sregs.u.e.tb & 0xffffffff;
1032 env->spr[SPR_TBU] = sregs.u.e.tb >> 32;
1033 env->spr[SPR_VRSAVE] = sregs.u.e.vrsave;
1034 }
1035
1036 if (sregs.u.e.features & KVM_SREGS_E_ARCH206) {
1037 env->spr[SPR_BOOKE_PIR] = sregs.u.e.pir;
1038 env->spr[SPR_BOOKE_MCSRR0] = sregs.u.e.mcsrr0;
1039 env->spr[SPR_BOOKE_MCSRR1] = sregs.u.e.mcsrr1;
1040 env->spr[SPR_BOOKE_DECAR] = sregs.u.e.decar;
1041 env->spr[SPR_BOOKE_IVPR] = sregs.u.e.ivpr;
1042 }
1043
1044 if (sregs.u.e.features & KVM_SREGS_E_64) {
1045 env->spr[SPR_BOOKE_EPCR] = sregs.u.e.epcr;
1046 }
1047
1048 if (sregs.u.e.features & KVM_SREGS_E_SPRG8) {
1049 env->spr[SPR_BOOKE_SPRG8] = sregs.u.e.sprg8;
1050 }
1051
1052 if (sregs.u.e.features & KVM_SREGS_E_IVOR) {
1053 env->spr[SPR_BOOKE_IVOR0] = sregs.u.e.ivor_low[0];
1054 kvm_sync_excp(env, POWERPC_EXCP_CRITICAL, SPR_BOOKE_IVOR0);
1055 env->spr[SPR_BOOKE_IVOR1] = sregs.u.e.ivor_low[1];
1056 kvm_sync_excp(env, POWERPC_EXCP_MCHECK, SPR_BOOKE_IVOR1);
1057 env->spr[SPR_BOOKE_IVOR2] = sregs.u.e.ivor_low[2];
1058 kvm_sync_excp(env, POWERPC_EXCP_DSI, SPR_BOOKE_IVOR2);
1059 env->spr[SPR_BOOKE_IVOR3] = sregs.u.e.ivor_low[3];
1060 kvm_sync_excp(env, POWERPC_EXCP_ISI, SPR_BOOKE_IVOR3);
1061 env->spr[SPR_BOOKE_IVOR4] = sregs.u.e.ivor_low[4];
1062 kvm_sync_excp(env, POWERPC_EXCP_EXTERNAL, SPR_BOOKE_IVOR4);
1063 env->spr[SPR_BOOKE_IVOR5] = sregs.u.e.ivor_low[5];
1064 kvm_sync_excp(env, POWERPC_EXCP_ALIGN, SPR_BOOKE_IVOR5);
1065 env->spr[SPR_BOOKE_IVOR6] = sregs.u.e.ivor_low[6];
1066 kvm_sync_excp(env, POWERPC_EXCP_PROGRAM, SPR_BOOKE_IVOR6);
1067 env->spr[SPR_BOOKE_IVOR7] = sregs.u.e.ivor_low[7];
1068 kvm_sync_excp(env, POWERPC_EXCP_FPU, SPR_BOOKE_IVOR7);
1069 env->spr[SPR_BOOKE_IVOR8] = sregs.u.e.ivor_low[8];
1070 kvm_sync_excp(env, POWERPC_EXCP_SYSCALL, SPR_BOOKE_IVOR8);
1071 env->spr[SPR_BOOKE_IVOR9] = sregs.u.e.ivor_low[9];
1072 kvm_sync_excp(env, POWERPC_EXCP_APU, SPR_BOOKE_IVOR9);
1073 env->spr[SPR_BOOKE_IVOR10] = sregs.u.e.ivor_low[10];
1074 kvm_sync_excp(env, POWERPC_EXCP_DECR, SPR_BOOKE_IVOR10);
1075 env->spr[SPR_BOOKE_IVOR11] = sregs.u.e.ivor_low[11];
1076 kvm_sync_excp(env, POWERPC_EXCP_FIT, SPR_BOOKE_IVOR11);
1077 env->spr[SPR_BOOKE_IVOR12] = sregs.u.e.ivor_low[12];
1078 kvm_sync_excp(env, POWERPC_EXCP_WDT, SPR_BOOKE_IVOR12);
1079 env->spr[SPR_BOOKE_IVOR13] = sregs.u.e.ivor_low[13];
1080 kvm_sync_excp(env, POWERPC_EXCP_DTLB, SPR_BOOKE_IVOR13);
1081 env->spr[SPR_BOOKE_IVOR14] = sregs.u.e.ivor_low[14];
1082 kvm_sync_excp(env, POWERPC_EXCP_ITLB, SPR_BOOKE_IVOR14);
1083 env->spr[SPR_BOOKE_IVOR15] = sregs.u.e.ivor_low[15];
1084 kvm_sync_excp(env, POWERPC_EXCP_DEBUG, SPR_BOOKE_IVOR15);
1085
1086 if (sregs.u.e.features & KVM_SREGS_E_SPE) {
1087 env->spr[SPR_BOOKE_IVOR32] = sregs.u.e.ivor_high[0];
1088 kvm_sync_excp(env, POWERPC_EXCP_SPEU, SPR_BOOKE_IVOR32);
1089 env->spr[SPR_BOOKE_IVOR33] = sregs.u.e.ivor_high[1];
1090 kvm_sync_excp(env, POWERPC_EXCP_EFPDI, SPR_BOOKE_IVOR33);
1091 env->spr[SPR_BOOKE_IVOR34] = sregs.u.e.ivor_high[2];
1092 kvm_sync_excp(env, POWERPC_EXCP_EFPRI, SPR_BOOKE_IVOR34);
1093 }
1094
1095 if (sregs.u.e.features & KVM_SREGS_E_PM) {
1096 env->spr[SPR_BOOKE_IVOR35] = sregs.u.e.ivor_high[3];
1097 kvm_sync_excp(env, POWERPC_EXCP_EPERFM, SPR_BOOKE_IVOR35);
1098 }
1099
1100 if (sregs.u.e.features & KVM_SREGS_E_PC) {
1101 env->spr[SPR_BOOKE_IVOR36] = sregs.u.e.ivor_high[4];
1102 kvm_sync_excp(env, POWERPC_EXCP_DOORI, SPR_BOOKE_IVOR36);
1103 env->spr[SPR_BOOKE_IVOR37] = sregs.u.e.ivor_high[5];
1104 kvm_sync_excp(env, POWERPC_EXCP_DOORCI, SPR_BOOKE_IVOR37);
1105 }
1106 }
1107
1108 if (sregs.u.e.features & KVM_SREGS_E_ARCH206_MMU) {
1109 env->spr[SPR_BOOKE_MAS0] = sregs.u.e.mas0;
1110 env->spr[SPR_BOOKE_MAS1] = sregs.u.e.mas1;
1111 env->spr[SPR_BOOKE_MAS2] = sregs.u.e.mas2;
1112 env->spr[SPR_BOOKE_MAS3] = sregs.u.e.mas7_3 & 0xffffffff;
1113 env->spr[SPR_BOOKE_MAS4] = sregs.u.e.mas4;
1114 env->spr[SPR_BOOKE_MAS6] = sregs.u.e.mas6;
1115 env->spr[SPR_BOOKE_MAS7] = sregs.u.e.mas7_3 >> 32;
1116 env->spr[SPR_MMUCFG] = sregs.u.e.mmucfg;
1117 env->spr[SPR_BOOKE_TLB0CFG] = sregs.u.e.tlbcfg[0];
1118 env->spr[SPR_BOOKE_TLB1CFG] = sregs.u.e.tlbcfg[1];
1119 }
1120
1121 if (sregs.u.e.features & KVM_SREGS_EXP) {
1122 env->spr[SPR_BOOKE_EPR] = sregs.u.e.epr;
1123 }
1124
1125 if (sregs.u.e.features & KVM_SREGS_E_PD) {
1126 env->spr[SPR_BOOKE_EPLC] = sregs.u.e.eplc;
1127 env->spr[SPR_BOOKE_EPSC] = sregs.u.e.epsc;
1128 }
1129
1130 if (sregs.u.e.impl_id == KVM_SREGS_E_IMPL_FSL) {
1131 env->spr[SPR_E500_SVR] = sregs.u.e.impl.fsl.svr;
1132 env->spr[SPR_Exxx_MCAR] = sregs.u.e.impl.fsl.mcar;
1133 env->spr[SPR_HID0] = sregs.u.e.impl.fsl.hid0;
1134
1135 if (sregs.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) {
1136 env->spr[SPR_BOOKE_PID1] = sregs.u.e.impl.fsl.pid1;
1137 env->spr[SPR_BOOKE_PID2] = sregs.u.e.impl.fsl.pid2;
1138 }
1139 }
1140
1141 return 0;
1142}
1143
1144static int kvmppc_get_books_sregs(PowerPCCPU *cpu)
1145{
1146 CPUPPCState *env = &cpu->env;
1147 struct kvm_sregs sregs;
1148 int ret;
1149 int i;
1150
1151 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1152 if (ret < 0) {
1153 return ret;
1154 }
1155
e57ca75c 1156 if (!cpu->vhyp) {
a7a00a72
DG		 1157 ppc_store_sdr1(env, sregs.u.s.sdr1);
1158 }
1159
1160 /* Sync SLB */
1161#ifdef TARGET_PPC64
1162 /*
1163 * The packed SLB array we get from KVM_GET_SREGS only contains
1164 * information about valid entries. So we flush our internal copy
1165 * to get rid of stale ones, then put all valid SLB entries back
1166 * in.
1167 */
1168 memset(env->slb, 0, sizeof(env->slb));
1169 for (i = 0; i < ARRAY_SIZE(env->slb); i++) {
1170 target_ulong rb = sregs.u.s.ppc64.slb[i].slbe;
1171 target_ulong rs = sregs.u.s.ppc64.slb[i].slbv;
1172 /*
1173 * Only restore valid entries
1174 */
1175 if (rb & SLB_ESID_V) {
1176 ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs);
1177 }
1178 }
1179#endif
1180
1181 /* Sync SRs */
1182 for (i = 0; i < 16; i++) {
1183 env->sr[i] = sregs.u.s.ppc32.sr[i];
1184 }
1185
1186 /* Sync BATs */
1187 for (i = 0; i < 8; i++) {
1188 env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff;
1189 env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32;
1190 env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff;
1191 env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32;
1192 }
1193
1194 return 0;
1195}
1196
20d695a9 1197int kvm_arch_get_registers(CPUState *cs)
d76d1650 1198{
20d695a9
AF		 1199 PowerPCCPU *cpu = POWERPC_CPU(cs);
1200 CPUPPCState *env = &cpu->env;
d76d1650 1201 struct kvm_regs regs;
90dc8812 1202 uint32_t cr;
138b38b6 1203 int i, ret;
d76d1650 1204
1bc22652 1205 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, &regs);
c995e942 1206 if (ret < 0) {
d76d1650 1207 return ret;
c995e942 1208 }
d76d1650 1209
90dc8812
SW		 1210 cr = regs.cr;
1211 for (i = 7; i >= 0; i--) {
1212 env->crf[i] = cr & 15;
1213 cr >>= 4;
1214 }
ba5e5090 1215
d76d1650
AJ		 1216 env->ctr = regs.ctr;
1217 env->lr = regs.lr;
da91a00f 1218 cpu_write_xer(env, regs.xer);
d76d1650
AJ		 1219 env->msr = regs.msr;
1220 env->nip = regs.pc;
1221
1222 env->spr[SPR_SRR0] = regs.srr0;
1223 env->spr[SPR_SRR1] = regs.srr1;
1224
1225 env->spr[SPR_SPRG0] = regs.sprg0;
1226 env->spr[SPR_SPRG1] = regs.sprg1;
1227 env->spr[SPR_SPRG2] = regs.sprg2;
1228 env->spr[SPR_SPRG3] = regs.sprg3;
1229 env->spr[SPR_SPRG4] = regs.sprg4;
1230 env->spr[SPR_SPRG5] = regs.sprg5;
1231 env->spr[SPR_SPRG6] = regs.sprg6;
1232 env->spr[SPR_SPRG7] = regs.sprg7;
1233
90dc8812
SW		 1234 env->spr[SPR_BOOKE_PID] = regs.pid;
1235
c995e942 1236 for (i = 0; i < 32; i++) {
d76d1650 1237 env->gpr[i] = regs.gpr[i];
c995e942 1238 }
d76d1650 1239
70b79849
DG		 1240 kvm_get_fp(cs);
1241
90dc8812 1242 if (cap_booke_sregs) {
a7a00a72 1243 ret = kvmppc_get_booke_sregs(cpu);
90dc8812
SW		 1244 if (ret < 0) {
1245 return ret;
1246 }
fafc0b6a 1247 }
90dc8812 1248
90dc8812 1249 if (cap_segstate) {
a7a00a72 1250 ret = kvmppc_get_books_sregs(cpu);
90dc8812
SW		 1251 if (ret < 0) {
1252 return ret;
1253 }
fafc0b6a 1254 }
ba5e5090 1255
d67d40ea
DG		 1256 if (cap_hior) {
1257 kvm_get_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR);
1258 }
1259
1260 if (cap_one_reg) {
1261 int i;
1262
c995e942
DG		 1263 /*
1264 * We deliberately ignore errors here, for kernels which have
d67d40ea
DG		 1265 * the ONE_REG calls, but don't support the specific
1266 * registers, there's a reasonable chance things will still
c995e942
DG		 1267 * work, at least until we try to migrate.
1268 */
d67d40ea
DG		 1269 for (i = 0; i < 1024; i++) {
1270 uint64_t id = env->spr_cb[i].one_reg_id;
1271
1272 if (id != 0) {
1273 kvm_get_one_spr(cs, id, i);
1274 }
1275 }
9b00ea49
DG		 1276
1277#ifdef TARGET_PPC64
80b3f79b
AK		 1278 if (msr_ts) {
1279 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
1280 kvm_get_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
1281 }
1282 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) {
1283 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]);
1284 }
1285 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr);
1286 kvm_get_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr);
1287 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr);
1288 kvm_get_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr);
1289 kvm_get_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr);
1290 kvm_get_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr);
1291 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave);
1292 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr);
1293 kvm_get_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr);
1294 kvm_get_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar);
1295 }
1296
9b00ea49
DG		 1297 if (cap_papr) {
1298 if (kvm_get_vpa(cs) < 0) {
8d83cbf1 1299 trace_kvm_failed_get_vpa();
9b00ea49
DG		 1300 }
1301 }
98a8b524
AK		 1302
1303 kvm_get_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset);
972bd576 1304 kvm_get_one_spr(cs, KVM_REG_PPC_DPDES, SPR_DPDES);
9b00ea49 1305#endif
d67d40ea
DG		 1306 }
1307
d76d1650
AJ		 1308 return 0;
1309}
1310
1bc22652 1311int kvmppc_set_interrupt(PowerPCCPU *cpu, int irq, int level)
fc87e185
AG		 1312{
1313 unsigned virq = level ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET;
1314
1315 if (irq != PPC_INTERRUPT_EXT) {
1316 return 0;
1317 }
1318
1e8f51e8 1319 if (!kvm_enabled() || !cap_interrupt_unset) {
fc87e185
AG		 1320 return 0;
1321 }
1322
1bc22652 1323 kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq);
fc87e185
AG		 1324
1325 return 0;
1326}
1327
20d695a9 1328void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
d76d1650 1329{
1e8f51e8 1330 return;
d76d1650
AJ		 1331}
1332
4c663752 1333MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
d76d1650 1334{
4c663752 1335 return MEMTXATTRS_UNSPECIFIED;
d76d1650
AJ		 1336}
1337
20d695a9 1338int kvm_arch_process_async_events(CPUState *cs)
0af691d7 1339{
259186a7 1340 return cs->halted;
0af691d7
MT		 1341}
1342
259186a7 1343static int kvmppc_handle_halt(PowerPCCPU *cpu)
d76d1650 1344{
259186a7
AF		 1345 CPUState *cs = CPU(cpu);
1346 CPUPPCState *env = &cpu->env;
1347
1348 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) {
1349 cs->halted = 1;
27103424 1350 cs->exception_index = EXCP_HLT;
d76d1650
AJ		 1351 }
1352
bb4ea393 1353 return 0;
d76d1650
AJ		 1354}
1355
1356/* map dcr access to existing qemu dcr emulation */
c995e942
DG		 1357static int kvmppc_handle_dcr_read(CPUPPCState *env,
1358 uint32_t dcrn, uint32_t *data)
d76d1650 1359{
c995e942 1360 if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0) {
d76d1650 1361 fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn);
c995e942 1362 }
d76d1650 1363
bb4ea393 1364 return 0;
d76d1650
AJ		 1365}
1366
c995e942
DG		 1367static int kvmppc_handle_dcr_write(CPUPPCState *env,
1368 uint32_t dcrn, uint32_t data)
d76d1650 1369{
c995e942 1370 if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0) {
d76d1650 1371 fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn);
c995e942 1372 }
d76d1650 1373
bb4ea393 1374 return 0;
d76d1650
AJ		 1375}
1376
8a0548f9
BB		 1377int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
1378{
1379 /* Mixed endian case is not handled */
1380 uint32_t sc = debug_inst_opcode;
1381
1382 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn,
1383 sizeof(sc), 0) ||
1384 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 1)) {
1385 return -EINVAL;
1386 }
1387
1388 return 0;
1389}
1390
1391int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
1392{
1393 uint32_t sc;
1394
1395 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 0) ||
1396 sc != debug_inst_opcode ||
1397 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn,
1398 sizeof(sc), 1)) {
1399 return -EINVAL;
1400 }
1401
1402 return 0;
1403}
1404
88365d17
BB		 1405static int find_hw_breakpoint(target_ulong addr, int type)
1406{
1407 int n;
1408
1409 assert((nb_hw_breakpoint + nb_hw_watchpoint)
1410 <= ARRAY_SIZE(hw_debug_points));
1411
1412 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) {
1413 if (hw_debug_points[n].addr == addr &&
1414 hw_debug_points[n].type == type) {
1415 return n;
1416 }
1417 }
1418
1419 return -1;
1420}
1421
1422static int find_hw_watchpoint(target_ulong addr, int *flag)
1423{
1424 int n;
1425
1426 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_ACCESS);
1427 if (n >= 0) {
1428 *flag = BP_MEM_ACCESS;
1429 return n;
1430 }
1431
1432 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_WRITE);
1433 if (n >= 0) {
1434 *flag = BP_MEM_WRITE;
1435 return n;
1436 }
1437
1438 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_READ);
1439 if (n >= 0) {
1440 *flag = BP_MEM_READ;
1441 return n;
1442 }
1443
1444 return -1;
1445}
1446
1447int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1448 target_ulong len, int type)
1449{
1450 if ((nb_hw_breakpoint + nb_hw_watchpoint) >= ARRAY_SIZE(hw_debug_points)) {
1451 return -ENOBUFS;
1452 }
1453
1454 hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint].addr = addr;
1455 hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint].type = type;
1456
1457 switch (type) {
1458 case GDB_BREAKPOINT_HW:
1459 if (nb_hw_breakpoint >= max_hw_breakpoint) {
1460 return -ENOBUFS;
1461 }
1462
1463 if (find_hw_breakpoint(addr, type) >= 0) {
1464 return -EEXIST;
1465 }
1466
1467 nb_hw_breakpoint++;
1468 break;
1469
1470 case GDB_WATCHPOINT_WRITE:
1471 case GDB_WATCHPOINT_READ:
1472 case GDB_WATCHPOINT_ACCESS:
1473 if (nb_hw_watchpoint >= max_hw_watchpoint) {
1474 return -ENOBUFS;
1475 }
1476
1477 if (find_hw_breakpoint(addr, type) >= 0) {
1478 return -EEXIST;
1479 }
1480
1481 nb_hw_watchpoint++;
1482 break;
1483
1484 default:
1485 return -ENOSYS;
1486 }
1487
1488 return 0;
1489}
1490
1491int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1492 target_ulong len, int type)
1493{
1494 int n;
1495
1496 n = find_hw_breakpoint(addr, type);
1497 if (n < 0) {
1498 return -ENOENT;
1499 }
1500
1501 switch (type) {
1502 case GDB_BREAKPOINT_HW:
1503 nb_hw_breakpoint--;
1504 break;
1505
1506 case GDB_WATCHPOINT_WRITE:
1507 case GDB_WATCHPOINT_READ:
1508 case GDB_WATCHPOINT_ACCESS:
1509 nb_hw_watchpoint--;
1510 break;
1511
1512 default:
1513 return -ENOSYS;
1514 }
1515 hw_debug_points[n] = hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint];
1516
1517 return 0;
1518}
1519
1520void kvm_arch_remove_all_hw_breakpoints(void)
1521{
1522 nb_hw_breakpoint = nb_hw_watchpoint = 0;
1523}
1524
8a0548f9
BB		 1525void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg)
1526{
88365d17
BB		 1527 int n;
1528
8a0548f9
BB		 1529 /* Software Breakpoint updates */
1530 if (kvm_sw_breakpoints_active(cs)) {
1531 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1532 }
88365d17
BB		 1533
1534 assert((nb_hw_breakpoint + nb_hw_watchpoint)
1535 <= ARRAY_SIZE(hw_debug_points));
1536 assert((nb_hw_breakpoint + nb_hw_watchpoint) <= ARRAY_SIZE(dbg->arch.bp));
1537
1538 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) {
1539 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1540 memset(dbg->arch.bp, 0, sizeof(dbg->arch.bp));
1541 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) {
1542 switch (hw_debug_points[n].type) {
1543 case GDB_BREAKPOINT_HW:
1544 dbg->arch.bp[n].type = KVMPPC_DEBUG_BREAKPOINT;
1545 break;
1546 case GDB_WATCHPOINT_WRITE:
1547 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE;
1548 break;
1549 case GDB_WATCHPOINT_READ:
1550 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_READ;
1551 break;
1552 case GDB_WATCHPOINT_ACCESS:
1553 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE |
1554 KVMPPC_DEBUG_WATCH_READ;
1555 break;
1556 default:
1557 cpu_abort(cs, "Unsupported breakpoint type\n");
1558 }
1559 dbg->arch.bp[n].addr = hw_debug_points[n].addr;
1560 }
1561 }
8a0548f9
BB		 1562}
1563
2cbd1581
FR		 1564static int kvm_handle_hw_breakpoint(CPUState *cs,
1565 struct kvm_debug_exit_arch *arch_info)
1566{
1567 int handle = 0;
1568 int n;
1569 int flag = 0;
1570
1571 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) {
1572 if (arch_info->status & KVMPPC_DEBUG_BREAKPOINT) {
1573 n = find_hw_breakpoint(arch_info->address, GDB_BREAKPOINT_HW);
1574 if (n >= 0) {
1575 handle = 1;
1576 }
1577 } else if (arch_info->status & (KVMPPC_DEBUG_WATCH_READ |
1578 KVMPPC_DEBUG_WATCH_WRITE)) {
1579 n = find_hw_watchpoint(arch_info->address, &flag);
1580 if (n >= 0) {
1581 handle = 1;
1582 cs->watchpoint_hit = &hw_watchpoint;
1583 hw_watchpoint.vaddr = hw_debug_points[n].addr;
1584 hw_watchpoint.flags = flag;
1585 }
1586 }
1587 }
1588 return handle;
1589}
1590
468e3a1a
FR		 1591static int kvm_handle_singlestep(void)
1592{
1593 return 1;
1594}
1595
1596static int kvm_handle_sw_breakpoint(void)
1597{
1598 return 1;
1599}
1600
8a0548f9
BB		 1601static int kvm_handle_debug(PowerPCCPU *cpu, struct kvm_run *run)
1602{
1603 CPUState *cs = CPU(cpu);
1604 CPUPPCState *env = &cpu->env;
1605 struct kvm_debug_exit_arch *arch_info = &run->debug.arch;
8a0548f9 1606
88365d17 1607 if (cs->singlestep_enabled) {
468e3a1a
FR		 1608 return kvm_handle_singlestep();
1609 }
8a0548f9 1610
468e3a1a
FR		 1611 if (arch_info->status) {
1612 return kvm_handle_hw_breakpoint(cs, arch_info);
8a0548f9
BB		 1613 }
1614
468e3a1a
FR		 1615 if (kvm_find_sw_breakpoint(cs, arch_info->address)) {
1616 return kvm_handle_sw_breakpoint();
1617 }
1618
1619 /*
1620 * QEMU is not able to handle debug exception, so inject
1621 * program exception to guest;
1622 * Yes program exception NOT debug exception !!
1623 * When QEMU is using debug resources then debug exception must
1624 * be always set. To achieve this we set MSR_DE and also set
1625 * MSRP_DEP so guest cannot change MSR_DE.
1626 * When emulating debug resource for guest we want guest
1627 * to control MSR_DE (enable/disable debug interrupt on need).
1628 * Supporting both configurations are NOT possible.
1629 * So the result is that we cannot share debug resources
1630 * between QEMU and Guest on BOOKE architecture.
1631 * In the current design QEMU gets the priority over guest,
1632 * this means that if QEMU is using debug resources then guest
1633 * cannot use them;
1634 * For software breakpoint QEMU uses a privileged instruction;
1635 * So there cannot be any reason that we are here for guest
1636 * set debug exception, only possibility is guest executed a
1637 * privileged / illegal instruction and that's why we are
1638 * injecting a program interrupt.
1639 */
1640 cpu_synchronize_state(cs);
1641 /*
1642 * env->nip is PC, so increment this by 4 to use
1643 * ppc_cpu_do_interrupt(), which set srr0 = env->nip - 4.
1644 */
1645 env->nip += 4;
1646 cs->exception_index = POWERPC_EXCP_PROGRAM;
1647 env->error_code = POWERPC_EXCP_INVAL;
1648 ppc_cpu_do_interrupt(cs);
1649
1650 return 0;
8a0548f9
BB		 1651}
1652
20d695a9 1653int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
d76d1650 1654{
20d695a9
AF		 1655 PowerPCCPU *cpu = POWERPC_CPU(cs);
1656 CPUPPCState *env = &cpu->env;
bb4ea393 1657 int ret;
d76d1650 1658
4b8523ee
JK		 1659 qemu_mutex_lock_iothread();
1660
d76d1650
AJ		 1661 switch (run->exit_reason) {
1662 case KVM_EXIT_DCR:
1663 if (run->dcr.is_write) {
8d83cbf1 1664 trace_kvm_handle_dcr_write();
d76d1650
AJ		 1665 ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data);
1666 } else {
228152c2 1667 trace_kvm_handle_dcr_read();
d76d1650
AJ		 1668 ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data);
1669 }
1670 break;
1671 case KVM_EXIT_HLT:
8d83cbf1 1672 trace_kvm_handle_halt();
259186a7 1673 ret = kvmppc_handle_halt(cpu);
d76d1650 1674 break;
c6304a4a 1675#if defined(TARGET_PPC64)
f61b4bed 1676 case KVM_EXIT_PAPR_HCALL:
8d83cbf1 1677 trace_kvm_handle_papr_hcall();
20d695a9 1678 run->papr_hcall.ret = spapr_hypercall(cpu,
aa100fa4 1679 run->papr_hcall.nr,
f61b4bed 1680 run->papr_hcall.args);
78e8fde2 1681 ret = 0;
f61b4bed
AG		 1682 break;
1683#endif
5b95b8b9 1684 case KVM_EXIT_EPR:
8d83cbf1 1685 trace_kvm_handle_epr();
933b19ea 1686 run->epr.epr = ldl_phys(cs->as, env->mpic_iack);
5b95b8b9
AG		 1687 ret = 0;
1688 break;
31f2cb8f 1689 case KVM_EXIT_WATCHDOG:
8d83cbf1 1690 trace_kvm_handle_watchdog_expiry();
31f2cb8f
BB		 1691 watchdog_perform_action();
1692 ret = 0;
1693 break;
1694
8a0548f9 1695 case KVM_EXIT_DEBUG:
8d83cbf1 1696 trace_kvm_handle_debug_exception();
8a0548f9
BB		 1697 if (kvm_handle_debug(cpu, run)) {
1698 ret = EXCP_DEBUG;
1699 break;
1700 }
1701 /* re-enter, this exception was guest-internal */
1702 ret = 0;
1703 break;
1704
73aaec4a
JK		 1705 default:
1706 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
1707 ret = -1;
1708 break;
d76d1650
AJ		 1709 }
1710
4b8523ee 1711 qemu_mutex_unlock_iothread();
d76d1650
AJ		 1712 return ret;
1713}
1714
31f2cb8f
BB		 1715int kvmppc_or_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits)
1716{
1717 CPUState *cs = CPU(cpu);
1718 uint32_t bits = tsr_bits;
1719 struct kvm_one_reg reg = {
1720 .id = KVM_REG_PPC_OR_TSR,
1721 .addr = (uintptr_t) &bits,
1722 };
1723
1724 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
1725}
1726
1727int kvmppc_clear_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits)
1728{
1729
1730 CPUState *cs = CPU(cpu);
1731 uint32_t bits = tsr_bits;
1732 struct kvm_one_reg reg = {
1733 .id = KVM_REG_PPC_CLEAR_TSR,
1734 .addr = (uintptr_t) &bits,
1735 };
1736
1737 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
1738}
1739
1740int kvmppc_set_tcr(PowerPCCPU *cpu)
1741{
1742 CPUState *cs = CPU(cpu);
1743 CPUPPCState *env = &cpu->env;
1744 uint32_t tcr = env->spr[SPR_BOOKE_TCR];
1745
1746 struct kvm_one_reg reg = {
1747 .id = KVM_REG_PPC_TCR,
1748 .addr = (uintptr_t) &tcr,
1749 };
1750
1751 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
1752}
1753
1754int kvmppc_booke_watchdog_enable(PowerPCCPU *cpu)
1755{
1756 CPUState *cs = CPU(cpu);
31f2cb8f
BB		 1757 int ret;
1758
1759 if (!kvm_enabled()) {
1760 return -1;
1761 }
1762
1763 if (!cap_ppc_watchdog) {
1764 printf("warning: KVM does not support watchdog");
1765 return -1;
1766 }
1767
48add816 1768 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_BOOKE_WATCHDOG, 0);
31f2cb8f
BB		 1769 if (ret < 0) {
1770 fprintf(stderr, "%s: couldn't enable KVM_CAP_PPC_BOOKE_WATCHDOG: %s\n",
1771 __func__, strerror(-ret));
1772 return ret;
1773 }
1774
1775 return ret;
1776}
1777
dc333cd6
AG		 1778static int read_cpuinfo(const char *field, char *value, int len)
1779{
1780 FILE *f;
1781 int ret = -1;
1782 int field_len = strlen(field);
1783 char line[512];
1784
1785 f = fopen("/proc/cpuinfo", "r");
1786 if (!f) {
1787 return -1;
1788 }
1789
1790 do {
ef951443 1791 if (!fgets(line, sizeof(line), f)) {
dc333cd6
AG		 1792 break;
1793 }
1794 if (!strncmp(line, field, field_len)) {
ae215068 1795 pstrcpy(value, len, line);
dc333cd6
AG		 1796 ret = 0;
1797 break;
1798 }
c995e942 1799 } while (*line);
dc333cd6
AG		 1800
1801 fclose(f);
1802
1803 return ret;
1804}
1805
1806uint32_t kvmppc_get_tbfreq(void)
1807{
1808 char line[512];
1809 char *ns;
73bcb24d 1810 uint32_t retval = NANOSECONDS_PER_SECOND;
dc333cd6
AG		 1811
1812 if (read_cpuinfo("timebase", line, sizeof(line))) {
1813 return retval;
1814 }
1815
c995e942
DG		 1816 ns = strchr(line, ':');
1817 if (!ns) {
dc333cd6
AG		 1818 return retval;
1819 }
1820
1821 ns++;
1822
f9b8e7f6 1823 return atoi(ns);
dc333cd6 1824}
4513d923 1825
ef951443
ND		 1826bool kvmppc_get_host_serial(char **value)
1827{
1828 return g_file_get_contents("/proc/device-tree/system-id", value, NULL,
1829 NULL);
1830}
1831
1832bool kvmppc_get_host_model(char **value)
1833{
1834 return g_file_get_contents("/proc/device-tree/model", value, NULL, NULL);
1835}
1836
eadaada1
AG		 1837/* Try to find a device tree node for a CPU with clock-frequency property */
1838static int kvmppc_find_cpu_dt(char *buf, int buf_len)
1839{
1840 struct dirent *dirp;
1841 DIR *dp;
1842
c995e942
DG		 1843 dp = opendir(PROC_DEVTREE_CPU);
1844 if (!dp) {
eadaada1
AG		 1845 printf("Can't open directory " PROC_DEVTREE_CPU "\n");
1846 return -1;
1847 }
1848
1849 buf[0] = '\0';
1850 while ((dirp = readdir(dp)) != NULL) {
1851 FILE *f;
1852 snprintf(buf, buf_len, "%s%s/clock-frequency", PROC_DEVTREE_CPU,
1853 dirp->d_name);
1854 f = fopen(buf, "r");
1855 if (f) {
1856 snprintf(buf, buf_len, "%s%s", PROC_DEVTREE_CPU, dirp->d_name);
1857 fclose(f);
1858 break;
1859 }
1860 buf[0] = '\0';
1861 }
1862 closedir(dp);
1863 if (buf[0] == '\0') {
1864 printf("Unknown host!\n");
1865 return -1;
1866 }
1867
1868 return 0;
1869}
1870
7d94a30b 1871static uint64_t kvmppc_read_int_dt(const char *filename)
eadaada1 1872{
9bc884b7
DG		 1873 union {
1874 uint32_t v32;
1875 uint64_t v64;
1876 } u;
eadaada1
AG		 1877 FILE *f;
1878 int len;
1879
7d94a30b 1880 f = fopen(filename, "rb");
eadaada1
AG		 1881 if (!f) {
1882 return -1;
1883 }
1884
9bc884b7 1885 len = fread(&u, 1, sizeof(u), f);
eadaada1
AG		 1886 fclose(f);
1887 switch (len) {
9bc884b7
DG		 1888 case 4:
1889 /* property is a 32-bit quantity */
1890 return be32_to_cpu(u.v32);
1891 case 8:
1892 return be64_to_cpu(u.v64);
eadaada1
AG		 1893 }
1894
1895 return 0;
1896}
1897
c995e942
DG		 1898/*
1899 * Read a CPU node property from the host device tree that's a single
7d94a30b 1900 * integer (32-bit or 64-bit). Returns 0 if anything goes wrong
c995e942
DG		 1901 * (can't find or open the property, or doesn't understand the format)
1902 */
7d94a30b
SB		 1903static uint64_t kvmppc_read_int_cpu_dt(const char *propname)
1904{
1905 char buf[PATH_MAX], *tmp;
1906 uint64_t val;
1907
1908 if (kvmppc_find_cpu_dt(buf, sizeof(buf))) {
1909 return -1;
1910 }
1911
1912 tmp = g_strdup_printf("%s/%s", buf, propname);
1913 val = kvmppc_read_int_dt(tmp);
1914 g_free(tmp);
1915
1916 return val;
1917}
1918
9bc884b7
DG		 1919uint64_t kvmppc_get_clockfreq(void)
1920{
1921 return kvmppc_read_int_cpu_dt("clock-frequency");
1922}
1923
7d050527
SJS		 1924static int kvmppc_get_dec_bits(void)
1925{
1926 int nr_bits = kvmppc_read_int_cpu_dt("ibm,dec-bits");
1927
1928 if (nr_bits > 0) {
1929 return nr_bits;
1930 }
1931 return 0;
1932}
1933
1a61a9ae 1934static int kvmppc_get_pvinfo(CPUPPCState *env, struct kvm_ppc_pvinfo *pvinfo)
db70b311
RH		 1935{
1936 CPUState *cs = env_cpu(env);
1a61a9ae 1937
6fd33a75 1938 if (kvm_vm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_PVINFO) &&
1a61a9ae
SY		 1939 !kvm_vm_ioctl(cs->kvm_state, KVM_PPC_GET_PVINFO, pvinfo)) {
1940 return 0;
1941 }
1942
1943 return 1;
1944}
1945
1946int kvmppc_get_hasidle(CPUPPCState *env)
1947{
1948 struct kvm_ppc_pvinfo pvinfo;
1949
1950 if (!kvmppc_get_pvinfo(env, &pvinfo) &&
1951 (pvinfo.flags & KVM_PPC_PVINFO_FLAGS_EV_IDLE)) {
1952 return 1;
1953 }
1954
1955 return 0;
1956}
1957
1328c2bf 1958int kvmppc_get_hypercall(CPUPPCState *env, uint8_t *buf, int buf_len)
45024f09 1959{
c995e942 1960 uint32_t *hc = (uint32_t *)buf;
45024f09
AG		 1961 struct kvm_ppc_pvinfo pvinfo;
1962
1a61a9ae 1963 if (!kvmppc_get_pvinfo(env, &pvinfo)) {
45024f09 1964 memcpy(buf, pvinfo.hcall, buf_len);
45024f09
AG		 1965 return 0;
1966 }
45024f09
AG		 1967
1968 /*
d13fc32e 1969 * Fallback to always fail hypercalls regardless of endianness:
45024f09 1970 *
d13fc32e 1971 * tdi 0,r0,72 (becomes b .+8 in wrong endian, nop in good endian)
45024f09 1972 * li r3, -1
d13fc32e
AG		 1973 * b .+8 (becomes nop in wrong endian)
1974 * bswap32(li r3, -1)
45024f09
AG		 1975 */
1976
d13fc32e
AG		 1977 hc[0] = cpu_to_be32(0x08000048);
1978 hc[1] = cpu_to_be32(0x3860ffff);
1979 hc[2] = cpu_to_be32(0x48000008);
1980 hc[3] = cpu_to_be32(bswap32(0x3860ffff));
45024f09 1981
0ddbd053 1982 return 1;
45024f09
AG		 1983}
1984
026bfd89
DG		 1985static inline int kvmppc_enable_hcall(KVMState *s, target_ulong hcall)
1986{
1987 return kvm_vm_enable_cap(s, KVM_CAP_PPC_ENABLE_HCALL, 0, hcall, 1);
1988}
1989
1990void kvmppc_enable_logical_ci_hcalls(void)
1991{
1992 /*
1993 * FIXME: it would be nice if we could detect the cases where
1994 * we're using a device which requires the in kernel
1995 * implementation of these hcalls, but the kernel lacks them and
1996 * produce a warning.
1997 */
1998 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_LOAD);
1999 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_STORE);
2000}
2001
ef9971dd
AK		 2002void kvmppc_enable_set_mode_hcall(void)
2003{
2004 kvmppc_enable_hcall(kvm_state, H_SET_MODE);
2005}
2006
5145ad4f
NW		 2007void kvmppc_enable_clear_ref_mod_hcalls(void)
2008{
2009 kvmppc_enable_hcall(kvm_state, H_CLEAR_REF);
2010 kvmppc_enable_hcall(kvm_state, H_CLEAR_MOD);
2011}
2012
68f9f708
SJS		 2013void kvmppc_enable_h_page_init(void)
2014{
2015 kvmppc_enable_hcall(kvm_state, H_PAGE_INIT);
2016}
2017
1bc22652 2018void kvmppc_set_papr(PowerPCCPU *cpu)
f61b4bed 2019{
1bc22652 2020 CPUState *cs = CPU(cpu);
f61b4bed
AG		 2021 int ret;
2022
da20aed1
DG		 2023 if (!kvm_enabled()) {
2024 return;
2025 }
2026
48add816 2027 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_PAPR, 0);
f61b4bed 2028 if (ret) {
072ed5f2
TH		 2029 error_report("This vCPU type or KVM version does not support PAPR");
2030 exit(1);
94135e81 2031 }
9b00ea49 2032
c995e942
DG		 2033 /*
2034 * Update the capability flag so we sync the right information
2035 * with kvm
2036 */
9b00ea49 2037 cap_papr = 1;
f61b4bed
AG		 2038}
2039
d6e166c0 2040int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr)
6db5bb0f 2041{
d6e166c0 2042 return kvm_set_one_reg(CPU(cpu), KVM_REG_PPC_ARCH_COMPAT, &compat_pvr);
6db5bb0f
AK		 2043}
2044
5b95b8b9
AG		 2045void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy)
2046{
5b95b8b9 2047 CPUState *cs = CPU(cpu);
5b95b8b9
AG		 2048 int ret;
2049
48add816 2050 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_EPR, 0, mpic_proxy);
5b95b8b9 2051 if (ret && mpic_proxy) {
072ed5f2
TH		 2052 error_report("This KVM version does not support EPR");
2053 exit(1);
5b95b8b9
AG		 2054 }
2055}
2056
e97c3636
DG		 2057int kvmppc_smt_threads(void)
2058{
2059 return cap_ppc_smt ? cap_ppc_smt : 1;
2060}
2061
fa98fbfc
SB		 2062int kvmppc_set_smt_threads(int smt)
2063{
2064 int ret;
2065
2066 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_SMT, 0, smt, 0);
2067 if (!ret) {
2068 cap_ppc_smt = smt;
2069 }
2070 return ret;
2071}
2072
0c115681 2073void kvmppc_error_append_smt_possible_hint(Error *const *errp)
fa98fbfc
SB		 2074{
2075 int i;
2076 GString *g;
2077 char *s;
2078
2079 assert(kvm_enabled());
2080 if (cap_ppc_smt_possible) {
2081 g = g_string_new("Available VSMT modes:");
2082 for (i = 63; i >= 0; i--) {
2083 if ((1UL << i) & cap_ppc_smt_possible) {
2084 g_string_append_printf(g, " %lu", (1UL << i));
2085 }
2086 }
2087 s = g_string_free(g, false);
1a639fdf 2088 error_append_hint(errp, "%s.\n", s);
fa98fbfc
SB		 2089 g_free(s);
2090 } else {
1a639fdf 2091 error_append_hint(errp,
fa98fbfc
SB		 2092 "This KVM seems to be too old to support VSMT.\n");
2093 }
2094}
2095
2096
7f763a5d 2097#ifdef TARGET_PPC64
7f763a5d
DG		 2098uint64_t kvmppc_rma_size(uint64_t current_size, unsigned int hash_shift)
2099{
f36951c1
DG		 2100 struct kvm_ppc_smmu_info info;
2101 long rampagesize, best_page_shift;
2102 int i;
2103
c995e942
DG		 2104 /*
2105 * Find the largest hardware supported page size that's less than
2106 * or equal to the (logical) backing page size of guest RAM
2107 */
ab256960 2108 kvm_get_smmu_info(&info, &error_fatal);
905b7ee4 2109 rampagesize = qemu_minrampagesize();
f36951c1
DG		 2110 best_page_shift = 0;
2111
2112 for (i = 0; i < KVM_PPC_PAGE_SIZES_MAX_SZ; i++) {
2113 struct kvm_ppc_one_seg_page_size *sps = &info.sps[i];
2114
2115 if (!sps->page_shift) {
2116 continue;
2117 }
2118
2119 if ((sps->page_shift > best_page_shift)
2120 && ((1UL << sps->page_shift) <= rampagesize)) {
2121 best_page_shift = sps->page_shift;
2122 }
2123 }
2124
7f763a5d 2125 return MIN(current_size,
f36951c1 2126 1ULL << (best_page_shift + hash_shift - 7));
7f763a5d
DG		 2127}
2128#endif
2129
da95324e
AK		 2130bool kvmppc_spapr_use_multitce(void)
2131{
2132 return cap_spapr_multitce;
2133}
2134
3dc410ae
AK		 2135int kvmppc_spapr_enable_inkernel_multitce(void)
2136{
2137 int ret;
2138
2139 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0,
2140 H_PUT_TCE_INDIRECT, 1);
2141 if (!ret) {
2142 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0,
2143 H_STUFF_TCE, 1);
2144 }
2145
2146 return ret;
2147}
2148
d6ee2a7c
AK		 2149void *kvmppc_create_spapr_tce(uint32_t liobn, uint32_t page_shift,
2150 uint64_t bus_offset, uint32_t nb_table,
2151 int *pfd, bool need_vfio)
0f5cb298 2152{
0f5cb298
DG		 2153 long len;
2154 int fd;
2155 void *table;
2156
c995e942
DG		 2157 /*
2158 * Must set fd to -1 so we don't try to munmap when called for
b5aec396
DG		 2159 * destroying the table, which the upper layers -will- do
2160 */
2161 *pfd = -1;
6a81dd17 2162 if (!cap_spapr_tce || (need_vfio && !cap_spapr_vfio)) {
0f5cb298
DG		 2163 return NULL;
2164 }
2165
d6ee2a7c
AK		 2166 if (cap_spapr_tce_64) {
2167 struct kvm_create_spapr_tce_64 args = {
2168 .liobn = liobn,
2169 .page_shift = page_shift,
2170 .offset = bus_offset >> page_shift,
2171 .size = nb_table,
2172 .flags = 0
2173 };
2174 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE_64, &args);
2175 if (fd < 0) {
2176 fprintf(stderr,
2177 "KVM: Failed to create TCE64 table for liobn 0x%x\n",
2178 liobn);
2179 return NULL;
2180 }
2181 } else if (cap_spapr_tce) {
2182 uint64_t window_size = (uint64_t) nb_table << page_shift;
2183 struct kvm_create_spapr_tce args = {
2184 .liobn = liobn,
2185 .window_size = window_size,
2186 };
2187 if ((window_size != args.window_size) || bus_offset) {
2188 return NULL;
2189 }
2190 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE, &args);
2191 if (fd < 0) {
2192 fprintf(stderr, "KVM: Failed to create TCE table for liobn 0x%x\n",
2193 liobn);
2194 return NULL;
2195 }
2196 } else {
0f5cb298
DG		 2197 return NULL;
2198 }
2199
d6ee2a7c 2200 len = nb_table * sizeof(uint64_t);
0f5cb298
DG		 2201 /* FIXME: round this up to page size */
2202
c995e942 2203 table = mmap(NULL, len, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
0f5cb298 2204 if (table == MAP_FAILED) {
b5aec396
DG		 2205 fprintf(stderr, "KVM: Failed to map TCE table for liobn 0x%x\n",
2206 liobn);
0f5cb298
DG		 2207 close(fd);
2208 return NULL;
2209 }
2210
2211 *pfd = fd;
2212 return table;
2213}
2214
523e7b8a 2215int kvmppc_remove_spapr_tce(void *table, int fd, uint32_t nb_table)
0f5cb298
DG		 2216{
2217 long len;
2218
2219 if (fd < 0) {
2220 return -1;
2221 }
2222
523e7b8a 2223 len = nb_table * sizeof(uint64_t);
0f5cb298
DG		 2224 if ((munmap(table, len) < 0) ||
2225 (close(fd) < 0)) {
b5aec396
DG		 2226 fprintf(stderr, "KVM: Unexpected error removing TCE table: %s",
2227 strerror(errno));
0f5cb298
DG		 2228 /* Leak the table */
2229 }
2230
2231 return 0;
2232}
2233
7f763a5d
DG		 2234int kvmppc_reset_htab(int shift_hint)
2235{
2236 uint32_t shift = shift_hint;
2237
ace9a2cb
DG		 2238 if (!kvm_enabled()) {
2239 /* Full emulation, tell caller to allocate htab itself */
2240 return 0;
2241 }
6977afda 2242 if (kvm_vm_check_extension(kvm_state, KVM_CAP_PPC_ALLOC_HTAB)) {
7f763a5d
DG		 2243 int ret;
2244 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_ALLOCATE_HTAB, &shift);
ace9a2cb 2245 if (ret == -ENOTTY) {
c995e942
DG		 2246 /*
2247 * At least some versions of PR KVM advertise the
ace9a2cb
DG		 2248 * capability, but don't implement the ioctl(). Oops.
2249 * Return 0 so that we allocate the htab in qemu, as is
c995e942
DG		 2250 * correct for PR.
2251 */
ace9a2cb
DG		 2252 return 0;
2253 } else if (ret < 0) {
7f763a5d
DG		 2254 return ret;
2255 }
2256 return shift;
2257 }
2258
c995e942
DG		 2259 /*
2260 * We have a kernel that predates the htab reset calls. For PR
ace9a2cb 2261 * KVM, we need to allocate the htab ourselves, for an HV KVM of
c995e942
DG		 2262 * this era, it has allocated a 16MB fixed size hash table
2263 * already.
2264 */
96c9cff0 2265 if (kvmppc_is_pr(kvm_state)) {
ace9a2cb
DG		 2266 /* PR - tell caller to allocate htab */
2267 return 0;
2268 } else {
2269 /* HV - assume 16MB kernel allocated htab */
2270 return 24;
2271 }
7f763a5d
DG		 2272}
2273
a1e98583
DG		 2274static inline uint32_t mfpvr(void)
2275{
2276 uint32_t pvr;
2277
2278 asm ("mfpvr %0"
2279 : "=r"(pvr));
2280 return pvr;
2281}
2282
a7342588
DG		 2283static void alter_insns(uint64_t *word, uint64_t flags, bool on)
2284{
2285 if (on) {
2286 *word |= flags;
2287 } else {
2288 *word &= ~flags;
2289 }
2290}
2291
2985b86b
AF		 2292static void kvmppc_host_cpu_class_init(ObjectClass *oc, void *data)
2293{
2294 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
0cbad81f
DG		 2295 uint32_t dcache_size = kvmppc_read_int_cpu_dt("d-cache-size");
2296 uint32_t icache_size = kvmppc_read_int_cpu_dt("i-cache-size");
a1e98583 2297
cfe34f44 2298 /* Now fix up the class with information we can query from the host */
3bc9ccc0 2299 pcc->pvr = mfpvr();
a7342588 2300
3f2ca480
DG		 2301 alter_insns(&pcc->insns_flags, PPC_ALTIVEC,
2302 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_ALTIVEC);
2303 alter_insns(&pcc->insns_flags2, PPC2_VSX,
2304 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_VSX);
2305 alter_insns(&pcc->insns_flags2, PPC2_DFP,
2306 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_DFP);
0cbad81f
DG		 2307
2308 if (dcache_size != -1) {
2309 pcc->l1_dcache_size = dcache_size;
2310 }
2311
2312 if (icache_size != -1) {
2313 pcc->l1_icache_size = icache_size;
2314 }
c64abd1f
SB		 2315
2316#if defined(TARGET_PPC64)
2317 pcc->radix_page_info = kvm_get_radix_page_info();
5f3066d8
DG		 2318
2319 if ((pcc->pvr & 0xffffff00) == CPU_POWERPC_POWER9_DD1) {
2320 /*
2321 * POWER9 DD1 has some bugs which make it not really ISA 3.00
2322 * compliant. More importantly, advertising ISA 3.00
2323 * architected mode may prevent guests from activating
2324 * necessary DD1 workarounds.
2325 */
2326 pcc->pcr_supported &= ~(PCR_COMPAT_3_00 | PCR_COMPAT_2_07
2327 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05);
2328 }
c64abd1f 2329#endif /* defined(TARGET_PPC64) */
a1e98583
DG		 2330}
2331
3b961124
SY		 2332bool kvmppc_has_cap_epr(void)
2333{
2334 return cap_epr;
2335}
2336
87a91de6
AG		 2337bool kvmppc_has_cap_fixup_hcalls(void)
2338{
2339 return cap_fixup_hcalls;
2340}
2341
bac3bf28
TH		 2342bool kvmppc_has_cap_htm(void)
2343{
2344 return cap_htm;
2345}
2346
cf1c4cce
SB		 2347bool kvmppc_has_cap_mmu_radix(void)
2348{
2349 return cap_mmu_radix;
2350}
2351
2352bool kvmppc_has_cap_mmu_hash_v3(void)
2353{
2354 return cap_mmu_hash_v3;
2355}
2356
072f416a
SJS		 2357static bool kvmppc_power8_host(void)
2358{
2359 bool ret = false;
2360#ifdef TARGET_PPC64
2361 {
2362 uint32_t base_pvr = CPU_POWERPC_POWER_SERVER_MASK & mfpvr();
2363 ret = (base_pvr == CPU_POWERPC_POWER8E_BASE) ||
2364 (base_pvr == CPU_POWERPC_POWER8NVL_BASE) ||
2365 (base_pvr == CPU_POWERPC_POWER8_BASE);
2366 }
2367#endif /* TARGET_PPC64 */
2368 return ret;
2369}
2370
8fea7044
SJS		 2371static int parse_cap_ppc_safe_cache(struct kvm_ppc_cpu_char c)
2372{
072f416a
SJS		 2373 bool l1d_thread_priv_req = !kvmppc_power8_host();
2374
8fea7044
SJS		 2375 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_L1D_FLUSH_PR) {
2376 return 2;
072f416a
SJS		 2377 } else if ((!l1d_thread_priv_req ||
2378 c.character & c.character_mask & H_CPU_CHAR_L1D_THREAD_PRIV) &&
8fea7044
SJS		 2379 (c.character & c.character_mask
2380 & (H_CPU_CHAR_L1D_FLUSH_ORI30 | H_CPU_CHAR_L1D_FLUSH_TRIG2))) {
2381 return 1;
2382 }
2383
2384 return 0;
2385}
2386
2387static int parse_cap_ppc_safe_bounds_check(struct kvm_ppc_cpu_char c)
2388{
2389 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_BNDS_CHK_SPEC_BAR) {
2390 return 2;
2391 } else if (c.character & c.character_mask & H_CPU_CHAR_SPEC_BAR_ORI31) {
2392 return 1;
2393 }
2394
2395 return 0;
2396}
2397
2398static int parse_cap_ppc_safe_indirect_branch(struct kvm_ppc_cpu_char c)
2399{
399b2896
SJS		 2400 if ((~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) &&
2401 (~c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) &&
2402 (~c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED)) {
2403 return SPAPR_CAP_FIXED_NA;
2404 } else if (c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) {
2405 return SPAPR_CAP_WORKAROUND;
2406 } else if (c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) {
8fea7044
SJS		 2407 return SPAPR_CAP_FIXED_CCD;
2408 } else if (c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED) {
2409 return SPAPR_CAP_FIXED_IBS;
2410 }
2411
2412 return 0;
2413}
2414
8ff43ee4
SJS		 2415static int parse_cap_ppc_count_cache_flush_assist(struct kvm_ppc_cpu_char c)
2416{
2417 if (c.character & c.character_mask & H_CPU_CHAR_BCCTR_FLUSH_ASSIST) {
2418 return 1;
2419 }
2420 return 0;
2421}
2422
38afd772
CLG		 2423bool kvmppc_has_cap_xive(void)
2424{
2425 return cap_xive;
2426}
2427
8acc2ae5
SJS		 2428static void kvmppc_get_cpu_characteristics(KVMState *s)
2429{
2430 struct kvm_ppc_cpu_char c;
2431 int ret;
2432
2433 /* Assume broken */
2434 cap_ppc_safe_cache = 0;
2435 cap_ppc_safe_bounds_check = 0;
2436 cap_ppc_safe_indirect_branch = 0;
2437
2438 ret = kvm_vm_check_extension(s, KVM_CAP_PPC_GET_CPU_CHAR);
2439 if (!ret) {
2440 return;
2441 }
2442 ret = kvm_vm_ioctl(s, KVM_PPC_GET_CPU_CHAR, &c);
2443 if (ret < 0) {
2444 return;
2445 }
8fea7044
SJS		 2446
2447 cap_ppc_safe_cache = parse_cap_ppc_safe_cache(c);
2448 cap_ppc_safe_bounds_check = parse_cap_ppc_safe_bounds_check(c);
2449 cap_ppc_safe_indirect_branch = parse_cap_ppc_safe_indirect_branch(c);
8ff43ee4
SJS		 2450 cap_ppc_count_cache_flush_assist =
2451 parse_cap_ppc_count_cache_flush_assist(c);
8acc2ae5
SJS		 2452}
2453
2454int kvmppc_get_cap_safe_cache(void)
2455{
2456 return cap_ppc_safe_cache;
2457}
2458
2459int kvmppc_get_cap_safe_bounds_check(void)
2460{
2461 return cap_ppc_safe_bounds_check;
2462}
2463
2464int kvmppc_get_cap_safe_indirect_branch(void)
2465{
2466 return cap_ppc_safe_indirect_branch;
2467}
2468
8ff43ee4
SJS		 2469int kvmppc_get_cap_count_cache_flush_assist(void)
2470{
2471 return cap_ppc_count_cache_flush_assist;
2472}
2473
b9a477b7
SJS		 2474bool kvmppc_has_cap_nested_kvm_hv(void)
2475{
2476 return !!cap_ppc_nested_kvm_hv;
2477}
2478
2479int kvmppc_set_cap_nested_kvm_hv(int enable)
2480{
2481 return kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_NESTED_HV, 0, enable);
2482}
2483
9ded780c
AK		 2484bool kvmppc_has_cap_spapr_vfio(void)
2485{
2486 return cap_spapr_vfio;
2487}
2488
7d050527
SJS		 2489int kvmppc_get_cap_large_decr(void)
2490{
2491 return cap_large_decr;
2492}
2493
2494int kvmppc_enable_cap_large_decr(PowerPCCPU *cpu, int enable)
2495{
2496 CPUState *cs = CPU(cpu);
2497 uint64_t lpcr;
2498
2499 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2500 /* Do we need to modify the LPCR? */
2501 if (!!(lpcr & LPCR_LD) != !!enable) {
2502 if (enable) {
2503 lpcr |= LPCR_LD;
2504 } else {
2505 lpcr &= ~LPCR_LD;
2506 }
2507 kvm_set_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2508 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2509
2510 if (!!(lpcr & LPCR_LD) != !!enable) {
2511 return -1;
2512 }
2513 }
2514
2515 return 0;
2516}
2517
52b2519c
TH		 2518PowerPCCPUClass *kvm_ppc_get_host_cpu_class(void)
2519{
2520 uint32_t host_pvr = mfpvr();
2521 PowerPCCPUClass *pvr_pcc;
2522
2523 pvr_pcc = ppc_cpu_class_by_pvr(host_pvr);
2524 if (pvr_pcc == NULL) {
2525 pvr_pcc = ppc_cpu_class_by_pvr_mask(host_pvr);
2526 }
2527
2528 return pvr_pcc;
2529}
2530
165dc3ed
DG		 2531static void pseries_machine_class_fixup(ObjectClass *oc, void *opaque)
2532{
2533 MachineClass *mc = MACHINE_CLASS(oc);
2534
2535 mc->default_cpu_type = TYPE_HOST_POWERPC_CPU;
2536}
2537
2538static int kvm_ppc_register_host_cpu_type(void)
5ba4576b
AF		 2539{
2540 TypeInfo type_info = {
2541 .name = TYPE_HOST_POWERPC_CPU,
5ba4576b
AF		 2542 .class_init = kvmppc_host_cpu_class_init,
2543 };
5ba4576b 2544 PowerPCCPUClass *pvr_pcc;
92e926e1 2545 ObjectClass *oc;
5b79b1ca 2546 DeviceClass *dc;
715d4b96 2547 int i;
5ba4576b 2548
52b2519c 2549 pvr_pcc = kvm_ppc_get_host_cpu_class();
5ba4576b
AF		 2550 if (pvr_pcc == NULL) {
2551 return -1;
2552 }
2553 type_info.parent = object_class_get_name(OBJECT_CLASS(pvr_pcc));
2554 type_register(&type_info);
165dc3ed
DG		 2555 /* override TCG default cpu type with 'host' cpu model */
2556 object_class_foreach(pseries_machine_class_fixup, TYPE_SPAPR_MACHINE,
2557 false, NULL);
5b79b1ca 2558
92e926e1
GK		 2559 oc = object_class_by_name(type_info.name);
2560 g_assert(oc);
2561
715d4b96
TH		 2562 /*
2563 * Update generic CPU family class alias (e.g. on a POWER8NVL host,
2564 * we want "POWER8" to be a "family" alias that points to the current
2565 * host CPU type, too)
2566 */
2567 dc = DEVICE_CLASS(ppc_cpu_get_family_class(pvr_pcc));
2568 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
c5354f54 2569 if (strcasecmp(ppc_cpu_aliases[i].alias, dc->desc) == 0) {
715d4b96
TH		 2570 char *suffix;
2571
2572 ppc_cpu_aliases[i].model = g_strdup(object_class_get_name(oc));
c9137065 2573 suffix = strstr(ppc_cpu_aliases[i].model, POWERPC_CPU_TYPE_SUFFIX);
715d4b96
TH		 2574 if (suffix) {
2575 *suffix = 0;
2576 }
715d4b96
TH		 2577 break;
2578 }
2579 }
2580
5ba4576b
AF		 2581 return 0;
2582}
2583
feaa64c4
DG		 2584int kvmppc_define_rtas_kernel_token(uint32_t token, const char *function)
2585{
2586 struct kvm_rtas_token_args args = {
2587 .token = token,
2588 };
2589
2590 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_RTAS)) {
2591 return -ENOENT;
2592 }
2593
7701aeed 2594 strncpy(args.name, function, sizeof(args.name) - 1);
feaa64c4
DG		 2595
2596 return kvm_vm_ioctl(kvm_state, KVM_PPC_RTAS_DEFINE_TOKEN, &args);
2597}
12b1143b 2598
14b0d748 2599int kvmppc_get_htab_fd(bool write, uint64_t index, Error **errp)
e68cb8b4
AK		 2600{
2601 struct kvm_get_htab_fd s = {
2602 .flags = write ? KVM_GET_HTAB_WRITE : 0,
14b0d748 2603 .start_index = index,
e68cb8b4 2604 };
82be8e73 2605 int ret;
e68cb8b4
AK		 2606
2607 if (!cap_htab_fd) {
14b0d748
GK		 2608 error_setg(errp, "KVM version doesn't support %s the HPT",
2609 write ? "writing" : "reading");
82be8e73
GK		 2610 return -ENOTSUP;
2611 }
2612
2613 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_HTAB_FD, &s);
2614 if (ret < 0) {
14b0d748
GK		 2615 error_setg(errp, "Unable to open fd for %s HPT %s KVM: %s",
2616 write ? "writing" : "reading", write ? "to" : "from",
2617 strerror(errno));
82be8e73 2618 return -errno;
e68cb8b4
AK		 2619 }
2620
82be8e73 2621 return ret;
e68cb8b4
AK		 2622}
2623
2624int kvmppc_save_htab(QEMUFile *f, int fd, size_t bufsize, int64_t max_ns)
2625{
bc72ad67 2626 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
e68cb8b4
AK		 2627 uint8_t buf[bufsize];
2628 ssize_t rc;
2629
2630 do {
2631 rc = read(fd, buf, bufsize);
2632 if (rc < 0) {
2633 fprintf(stderr, "Error reading data from KVM HTAB fd: %s\n",
2634 strerror(errno));
2635 return rc;
2636 } else if (rc) {
e094c4c1
CLG		 2637 uint8_t *buffer = buf;
2638 ssize_t n = rc;
2639 while (n) {
2640 struct kvm_get_htab_header *head =
2641 (struct kvm_get_htab_header *) buffer;
2642 size_t chunksize = sizeof(*head) +
2643 HASH_PTE_SIZE_64 * head->n_valid;
2644
2645 qemu_put_be32(f, head->index);
2646 qemu_put_be16(f, head->n_valid);
2647 qemu_put_be16(f, head->n_invalid);
2648 qemu_put_buffer(f, (void *)(head + 1),
2649 HASH_PTE_SIZE_64 * head->n_valid);
2650
2651 buffer += chunksize;
2652 n -= chunksize;
2653 }
e68cb8b4
AK		 2654 }
2655 } while ((rc != 0)
c995e942
DG		 2656 && ((max_ns < 0) ||
2657 ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) < max_ns)));
e68cb8b4
AK		 2658
2659 return (rc == 0) ? 1 : 0;
2660}
2661
2662int kvmppc_load_htab_chunk(QEMUFile *f, int fd, uint32_t index,
2663 uint16_t n_valid, uint16_t n_invalid)
2664{
2665 struct kvm_get_htab_header *buf;
c995e942 2666 size_t chunksize = sizeof(*buf) + n_valid * HASH_PTE_SIZE_64;
e68cb8b4
AK		 2667 ssize_t rc;
2668
2669 buf = alloca(chunksize);
e68cb8b4
AK		 2670 buf->index = index;
2671 buf->n_valid = n_valid;
2672 buf->n_invalid = n_invalid;
2673
c995e942 2674 qemu_get_buffer(f, (void *)(buf + 1), HASH_PTE_SIZE_64 * n_valid);
e68cb8b4
AK		 2675
2676 rc = write(fd, buf, chunksize);
2677 if (rc < 0) {
2678 fprintf(stderr, "Error writing KVM hash table: %s\n",
2679 strerror(errno));
2680 return rc;
2681 }
2682 if (rc != chunksize) {
2683 /* We should never get a short write on a single chunk */
2684 fprintf(stderr, "Short write, restoring KVM hash table\n");
2685 return -1;
2686 }
2687 return 0;
2688}
2689
20d695a9 2690bool kvm_arch_stop_on_emulation_error(CPUState *cpu)
4513d923
GN		 2691{
2692 return true;
2693}
a1b87fe0 2694
82169660
SW		 2695void kvm_arch_init_irq_routing(KVMState *s)
2696{
2697}
c65f9a07 2698
1ad9f0a4 2699void kvmppc_read_hptes(ppc_hash_pte64_t *hptes, hwaddr ptex, int n)
7c43bca0 2700{
1ad9f0a4
DG		 2701 int fd, rc;
2702 int i;
7c43bca0 2703
14b0d748 2704 fd = kvmppc_get_htab_fd(false, ptex, &error_abort);
7c43bca0 2705
1ad9f0a4
DG		 2706 i = 0;
2707 while (i < n) {
2708 struct kvm_get_htab_header *hdr;
2709 int m = n < HPTES_PER_GROUP ? n : HPTES_PER_GROUP;
2710 char buf[sizeof(*hdr) + m * HASH_PTE_SIZE_64];
7c43bca0 2711
1ad9f0a4
DG		 2712 rc = read(fd, buf, sizeof(buf));
2713 if (rc < 0) {
2714 hw_error("kvmppc_read_hptes: Unable to read HPTEs");
2715 }
7c43bca0 2716
1ad9f0a4
DG		 2717 hdr = (struct kvm_get_htab_header *)buf;
2718 while ((i < n) && ((char *)hdr < (buf + rc))) {
a36593e1 2719 int invalid = hdr->n_invalid, valid = hdr->n_valid;
7c43bca0 2720
1ad9f0a4
DG		 2721 if (hdr->index != (ptex + i)) {
2722 hw_error("kvmppc_read_hptes: Unexpected HPTE index %"PRIu32
2723 " != (%"HWADDR_PRIu" + %d", hdr->index, ptex, i);
2724 }
2725
a36593e1
AK		 2726 if (n - i < valid) {
2727 valid = n - i;
2728 }
2729 memcpy(hptes + i, hdr + 1, HASH_PTE_SIZE_64 * valid);
2730 i += valid;
7c43bca0 2731
1ad9f0a4
DG		 2732 if ((n - i) < invalid) {
2733 invalid = n - i;
2734 }
2735 memset(hptes + i, 0, invalid * HASH_PTE_SIZE_64);
a36593e1 2736 i += invalid;
1ad9f0a4
DG		 2737
2738 hdr = (struct kvm_get_htab_header *)
2739 ((char *)(hdr + 1) + HASH_PTE_SIZE_64 * hdr->n_valid);
2740 }
2741 }
2742
2743 close(fd);
7c43bca0 2744}
c1385933 2745
1ad9f0a4 2746void kvmppc_write_hpte(hwaddr ptex, uint64_t pte0, uint64_t pte1)
c1385933 2747{
1ad9f0a4 2748 int fd, rc;
1ad9f0a4
DG		 2749 struct {
2750 struct kvm_get_htab_header hdr;
2751 uint64_t pte0;
2752 uint64_t pte1;
2753 } buf;
c1385933 2754
14b0d748 2755 fd = kvmppc_get_htab_fd(true, 0 /* Ignored */, &error_abort);
c1385933 2756
1ad9f0a4
DG		 2757 buf.hdr.n_valid = 1;
2758 buf.hdr.n_invalid = 0;
2759 buf.hdr.index = ptex;
2760 buf.pte0 = cpu_to_be64(pte0);
2761 buf.pte1 = cpu_to_be64(pte1);
c1385933 2762
1ad9f0a4
DG		 2763 rc = write(fd, &buf, sizeof(buf));
2764 if (rc != sizeof(buf)) {
2765 hw_error("kvmppc_write_hpte: Unable to update KVM HPT");
2766 }
2767 close(fd);
c1385933 2768}
9e03a040
FB		 2769
2770int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 2771 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040
FB		 2772{
2773 return 0;
2774}
1850b6b7 2775
38d87493
PX		 2776int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
2777 int vector, PCIDevice *dev)
2778{
2779 return 0;
2780}
2781
2782int kvm_arch_release_virq_post(int virq)
2783{
2784 return 0;
2785}
2786
1850b6b7
EA		 2787int kvm_arch_msi_data_to_gsi(uint32_t data)
2788{
2789 return data & 0xffff;
2790}
4d9392be
TH		 2791
2792int kvmppc_enable_hwrng(void)
2793{
2794 if (!kvm_enabled() || !kvm_check_extension(kvm_state, KVM_CAP_PPC_HWRNG)) {
2795 return -1;
2796 }
2797
2798 return kvmppc_enable_hcall(kvm_state, H_RANDOM);
2799}
30f4b05b
DG		 2800
2801void kvmppc_check_papr_resize_hpt(Error **errp)
2802{
2803 if (!kvm_enabled()) {
b55d295e
DG		 2804 return; /* No KVM, we're good */
2805 }
2806
2807 if (cap_resize_hpt) {
2808 return; /* Kernel has explicit support, we're good */
30f4b05b
DG		 2809 }
2810
b55d295e
DG		 2811 /* Otherwise fallback on looking for PR KVM */
2812 if (kvmppc_is_pr(kvm_state)) {
2813 return;
2814 }
30f4b05b
DG		 2815
2816 error_setg(errp,
2817 "Hash page table resizing not available with this KVM version");
2818}
b55d295e
DG		 2819
2820int kvmppc_resize_hpt_prepare(PowerPCCPU *cpu, target_ulong flags, int shift)
2821{
2822 CPUState *cs = CPU(cpu);
2823 struct kvm_ppc_resize_hpt rhpt = {
2824 .flags = flags,
2825 .shift = shift,
2826 };
2827
2828 if (!cap_resize_hpt) {
2829 return -ENOSYS;
2830 }
2831
2832 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_PREPARE, &rhpt);
2833}
2834
2835int kvmppc_resize_hpt_commit(PowerPCCPU *cpu, target_ulong flags, int shift)
2836{
2837 CPUState *cs = CPU(cpu);
2838 struct kvm_ppc_resize_hpt rhpt = {
2839 .flags = flags,
2840 .shift = shift,
2841 };
2842
2843 if (!cap_resize_hpt) {
2844 return -ENOSYS;
2845 }
2846
2847 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_COMMIT, &rhpt);
2848}
2849
c363a37a
DHB		 2850/*
2851 * This is a helper function to detect a post migration scenario
2852 * in which a guest, running as KVM-HV, freezes in cpu_post_load because
2853 * the guest kernel can't handle a PVR value other than the actual host
2854 * PVR in KVM_SET_SREGS, even if pvr_match() returns true.
2855 *
2856 * If we don't have cap_ppc_pvr_compat and we're not running in PR
2857 * (so, we're HV), return true. The workaround itself is done in
2858 * cpu_post_load.
2859 *
2860 * The order here is important: we'll only check for KVM PR as a
2861 * fallback if the guest kernel can't handle the situation itself.
2862 * We need to avoid as much as possible querying the running KVM type
2863 * in QEMU level.
2864 */
2865bool kvmppc_pvr_workaround_required(PowerPCCPU *cpu)
2866{
2867 CPUState *cs = CPU(cpu);
2868
2869 if (!kvm_enabled()) {
2870 return false;
2871 }
2872
2873 if (cap_ppc_pvr_compat) {
2874 return false;
2875 }
2876
2877 return !kvmppc_is_pr(cs->kvm_state);
2878}
a84f7179
ND		 2879
2880void kvmppc_set_reg_ppc_online(PowerPCCPU *cpu, unsigned int online)
2881{
2882 CPUState *cs = CPU(cpu);
2883
2884 if (kvm_enabled()) {
2885 kvm_set_one_reg(cs, KVM_REG_PPC_ONLINE, &online);
2886 }
2887}
9723295a
GK		 2888
2889void kvmppc_set_reg_tb_offset(PowerPCCPU *cpu, int64_t tb_offset)
2890{
2891 CPUState *cs = CPU(cpu);
2892
2893 if (kvm_enabled()) {
2894 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &tb_offset);
2895 }
2896}
905db916
BR		 2897
2898/*
2899 * Don't set error if KVM_PPC_SVM_OFF ioctl is invoked on kernels
2900 * that don't support this ioctl.
2901 */
2902void kvmppc_svm_off(Error **errp)
2903{
2904 int rc;
905db916 2905
0b731978
BR		 2906 if (!kvm_enabled()) {
2907 return;
2908 }
2909
2910 rc = kvm_vm_ioctl(KVM_STATE(current_machine->accelerator), KVM_PPC_SVM_OFF);
905db916
BR		 2911 if (rc && rc != -ENOTTY) {
2912 error_setg_errno(errp, -rc, "KVM_PPC_SVM_OFF ioctl failed");
2913 }
2914}
QEMU mirror