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Commit | Line | Data |
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29e4bcb2 AF |
1 | /* |
2 | * QEMU S/390 CPU | |
3 | * | |
1ac1a749 AF |
4 | * Copyright (c) 2009 Ulrich Hecht |
5 | * Copyright (c) 2011 Alexander Graf | |
29e4bcb2 | 6 | * Copyright (c) 2012 SUSE LINUX Products GmbH |
70bada03 | 7 | * Copyright (c) 2012 IBM Corp. |
29e4bcb2 AF |
8 | * |
9 | * This library is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU Lesser General Public | |
11 | * License as published by the Free Software Foundation; either | |
12 | * version 2.1 of the License, or (at your option) any later version. | |
13 | * | |
14 | * This library is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * Lesser General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU Lesser General Public | |
20 | * License along with this library; if not, see | |
21 | * <http://www.gnu.org/licenses/lgpl-2.1.html> | |
70bada03 JF |
22 | * Contributions after 2012-12-11 are licensed under the terms of the |
23 | * GNU GPL, version 2 or (at your option) any later version. | |
29e4bcb2 AF |
24 | */ |
25 | ||
9615495a | 26 | #include "qemu/osdep.h" |
da34e65c | 27 | #include "qapi/error.h" |
564b863d | 28 | #include "cpu.h" |
4e58b838 | 29 | #include "internal.h" |
f16bbb9b DH |
30 | #include "kvm_s390x.h" |
31 | #include "sysemu/kvm.h" | |
29e4bcb2 | 32 | #include "qemu-common.h" |
f348b6d1 | 33 | #include "qemu/cutils.h" |
1de7afc9 | 34 | #include "qemu/timer.h" |
eb24f7c6 | 35 | #include "qemu/error-report.h" |
eb24f7c6 | 36 | #include "trace.h" |
96b1a8bb | 37 | #include "qapi/visitor.h" |
63c91552 | 38 | #include "exec/exec-all.h" |
ca5c1457 | 39 | #include "hw/qdev-properties.h" |
c7396bbb | 40 | #ifndef CONFIG_USER_ONLY |
741da0d3 | 41 | #include "hw/hw.h" |
904e5fd5 | 42 | #include "sysemu/arch_init.h" |
96b1a8bb | 43 | #include "sysemu/sysemu.h" |
904e5fd5 VM |
44 | #endif |
45 | ||
70bada03 JF |
46 | #define CR0_RESET 0xE0UL |
47 | #define CR14_RESET 0xC2000000UL; | |
48 | ||
f45748f1 AF |
49 | static void s390_cpu_set_pc(CPUState *cs, vaddr value) |
50 | { | |
51 | S390CPU *cpu = S390_CPU(cs); | |
52 | ||
53 | cpu->env.psw.addr = value; | |
54 | } | |
55 | ||
8c2e1b00 AF |
56 | static bool s390_cpu_has_work(CPUState *cs) |
57 | { | |
58 | S390CPU *cpu = S390_CPU(cs); | |
8c2e1b00 | 59 | |
4beab671 DH |
60 | /* STOPPED cpus can never wake up */ |
61 | if (s390_cpu_get_state(cpu) != CPU_STATE_LOAD && | |
62 | s390_cpu_get_state(cpu) != CPU_STATE_OPERATING) { | |
63 | return false; | |
64 | } | |
65 | ||
8417f904 DH |
66 | if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { |
67 | return false; | |
68 | } | |
69 | ||
70 | return s390_cpu_has_int(cpu); | |
8c2e1b00 AF |
71 | } |
72 | ||
29c6157c CB |
73 | #if !defined(CONFIG_USER_ONLY) |
74 | /* S390CPUClass::load_normal() */ | |
75 | static void s390_cpu_load_normal(CPUState *s) | |
76 | { | |
77 | S390CPU *cpu = S390_CPU(s); | |
fdfba1a2 | 78 | cpu->env.psw.addr = ldl_phys(s->as, 4) & PSW_MASK_ESA_ADDR; |
29c6157c | 79 | cpu->env.psw.mask = PSW_MASK_32 | PSW_MASK_64; |
eb24f7c6 | 80 | s390_cpu_set_state(CPU_STATE_OPERATING, cpu); |
29c6157c CB |
81 | } |
82 | #endif | |
83 | ||
f5ae2a4f | 84 | /* S390CPUClass::cpu_reset() */ |
29e4bcb2 AF |
85 | static void s390_cpu_reset(CPUState *s) |
86 | { | |
87 | S390CPU *cpu = S390_CPU(s); | |
88 | S390CPUClass *scc = S390_CPU_GET_CLASS(cpu); | |
89 | CPUS390XState *env = &cpu->env; | |
90 | ||
819bd309 | 91 | env->pfault_token = -1UL; |
f5ae2a4f | 92 | scc->parent_reset(s); |
18ff9494 | 93 | cpu->env.sigp_order = 0; |
eb24f7c6 | 94 | s390_cpu_set_state(CPU_STATE_STOPPED, cpu); |
f5ae2a4f CB |
95 | } |
96 | ||
97 | /* S390CPUClass::initial_reset() */ | |
98 | static void s390_cpu_initial_reset(CPUState *s) | |
99 | { | |
100 | S390CPU *cpu = S390_CPU(s); | |
101 | CPUS390XState *env = &cpu->env; | |
cc0d079d | 102 | int i; |
f5ae2a4f CB |
103 | |
104 | s390_cpu_reset(s); | |
cb4f4bc3 CB |
105 | /* initial reset does not clear everything! */ |
106 | memset(&env->start_initial_reset_fields, 0, | |
107 | offsetof(CPUS390XState, end_reset_fields) - | |
108 | offsetof(CPUS390XState, start_initial_reset_fields)); | |
f5ae2a4f CB |
109 | |
110 | /* architectured initial values for CR 0 and 14 */ | |
111 | env->cregs[0] = CR0_RESET; | |
112 | env->cregs[14] = CR14_RESET; | |
819bd309 | 113 | |
3da0ab35 AJ |
114 | /* architectured initial value for Breaking-Event-Address register */ |
115 | env->gbea = 1; | |
116 | ||
819bd309 | 117 | env->pfault_token = -1UL; |
cc0d079d AJ |
118 | for (i = 0; i < ARRAY_SIZE(env->io_index); i++) { |
119 | env->io_index[i] = -1; | |
120 | } | |
8986db49 | 121 | env->mchk_index = -1; |
49f5c9e9 | 122 | |
4a33565f AJ |
123 | /* tininess for underflow is detected before rounding */ |
124 | set_float_detect_tininess(float_tininess_before_rounding, | |
125 | &env->fpu_status); | |
126 | ||
49f5c9e9 TH |
127 | /* Reset state inside the kernel that we cannot access yet from QEMU. */ |
128 | if (kvm_enabled()) { | |
99607144 | 129 | kvm_s390_reset_vcpu(cpu); |
49f5c9e9 | 130 | } |
f5ae2a4f CB |
131 | } |
132 | ||
133 | /* CPUClass:reset() */ | |
134 | static void s390_cpu_full_reset(CPUState *s) | |
135 | { | |
136 | S390CPU *cpu = S390_CPU(s); | |
137 | S390CPUClass *scc = S390_CPU_GET_CLASS(cpu); | |
138 | CPUS390XState *env = &cpu->env; | |
cc0d079d | 139 | int i; |
f5ae2a4f | 140 | |
29e4bcb2 | 141 | scc->parent_reset(s); |
18ff9494 | 142 | cpu->env.sigp_order = 0; |
eb24f7c6 | 143 | s390_cpu_set_state(CPU_STATE_STOPPED, cpu); |
29e4bcb2 | 144 | |
1f5c00cf | 145 | memset(env, 0, offsetof(CPUS390XState, end_reset_fields)); |
70bada03 JF |
146 | |
147 | /* architectured initial values for CR 0 and 14 */ | |
148 | env->cregs[0] = CR0_RESET; | |
149 | env->cregs[14] = CR14_RESET; | |
819bd309 | 150 | |
3da0ab35 AJ |
151 | /* architectured initial value for Breaking-Event-Address register */ |
152 | env->gbea = 1; | |
153 | ||
819bd309 | 154 | env->pfault_token = -1UL; |
cc0d079d AJ |
155 | for (i = 0; i < ARRAY_SIZE(env->io_index); i++) { |
156 | env->io_index[i] = -1; | |
157 | } | |
8986db49 | 158 | env->mchk_index = -1; |
819bd309 | 159 | |
4a33565f AJ |
160 | /* tininess for underflow is detected before rounding */ |
161 | set_float_detect_tininess(float_tininess_before_rounding, | |
162 | &env->fpu_status); | |
163 | ||
99607144 | 164 | /* Reset state inside the kernel that we cannot access yet from QEMU. */ |
50a2c6e5 PB |
165 | if (kvm_enabled()) { |
166 | kvm_s390_reset_vcpu(cpu); | |
167 | } | |
29e4bcb2 AF |
168 | } |
169 | ||
70bada03 JF |
170 | #if !defined(CONFIG_USER_ONLY) |
171 | static void s390_cpu_machine_reset_cb(void *opaque) | |
172 | { | |
173 | S390CPU *cpu = opaque; | |
174 | ||
14e6fe12 | 175 | run_on_cpu(CPU(cpu), s390_do_cpu_full_reset, RUN_ON_CPU_NULL); |
70bada03 JF |
176 | } |
177 | #endif | |
178 | ||
dbad6b74 PC |
179 | static void s390_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) |
180 | { | |
181 | info->mach = bfd_mach_s390_64; | |
182 | info->print_insn = print_insn_s390; | |
183 | } | |
184 | ||
1f136632 AF |
185 | static void s390_cpu_realizefn(DeviceState *dev, Error **errp) |
186 | { | |
14a10fc3 | 187 | CPUState *cs = CPU(dev); |
1f136632 | 188 | S390CPUClass *scc = S390_CPU_GET_CLASS(dev); |
1e70ba24 | 189 | #if !defined(CONFIG_USER_ONLY) |
c6644fc8 | 190 | S390CPU *cpu = S390_CPU(dev); |
1e70ba24 | 191 | #endif |
c6644fc8 MR |
192 | Error *err = NULL; |
193 | ||
41868f84 DH |
194 | /* the model has to be realized before qemu_init_vcpu() due to kvm */ |
195 | s390_realize_cpu_model(cs, &err); | |
196 | if (err) { | |
197 | goto out; | |
198 | } | |
199 | ||
96b1a8bb | 200 | #if !defined(CONFIG_USER_ONLY) |
ca5c1457 DH |
201 | if (cpu->env.core_id >= max_cpus) { |
202 | error_setg(&err, "Unable to add CPU with core-id: %" PRIu32 | |
203 | ", maximum core-id: %d", cpu->env.core_id, | |
204 | max_cpus - 1); | |
96b1a8bb MR |
205 | goto out; |
206 | } | |
88556edd | 207 | |
ca5c1457 DH |
208 | if (cpu_exists(cpu->env.core_id)) { |
209 | error_setg(&err, "Unable to add CPU with core-id: %" PRIu32 | |
210 | ", it already exists", cpu->env.core_id); | |
96b1a8bb MR |
211 | goto out; |
212 | } | |
96b1a8bb | 213 | |
ca5c1457 | 214 | /* sync cs->cpu_index and env->core_id. The latter is needed for TCG. */ |
1e70ba24 DH |
215 | cs->cpu_index = cpu->env.core_id; |
216 | #endif | |
217 | ||
ce5b1bbf | 218 | cpu_exec_realizefn(cs, &err); |
c6644fc8 | 219 | if (err != NULL) { |
96b1a8bb | 220 | goto out; |
c6644fc8 | 221 | } |
1f136632 | 222 | |
c6644fc8 MR |
223 | #if !defined(CONFIG_USER_ONLY) |
224 | qemu_register_reset(s390_cpu_machine_reset_cb, cpu); | |
225 | #endif | |
73d510c9 | 226 | s390_cpu_gdb_init(cs); |
14a10fc3 | 227 | qemu_init_vcpu(cs); |
159855f0 | 228 | #if !defined(CONFIG_USER_ONLY) |
14e6fe12 | 229 | run_on_cpu(cs, s390_do_cpu_full_reset, RUN_ON_CPU_NULL); |
159855f0 | 230 | #else |
14a10fc3 | 231 | cpu_reset(cs); |
159855f0 | 232 | #endif |
1f136632 | 233 | |
96b1a8bb | 234 | scc->parent_realize(dev, &err); |
96b1a8bb MR |
235 | out: |
236 | error_propagate(errp, err); | |
237 | } | |
238 | ||
8f22e0df AF |
239 | static void s390_cpu_initfn(Object *obj) |
240 | { | |
c05efcb1 | 241 | CPUState *cs = CPU(obj); |
8f22e0df AF |
242 | S390CPU *cpu = S390_CPU(obj); |
243 | CPUS390XState *env = &cpu->env; | |
2b7ac767 | 244 | static bool inited; |
8f22e0df AF |
245 | #if !defined(CONFIG_USER_ONLY) |
246 | struct tm tm; | |
247 | #endif | |
248 | ||
c05efcb1 | 249 | cs->env_ptr = env; |
ef3027af MR |
250 | cs->halted = 1; |
251 | cs->exception_index = EXCP_HLT; | |
0754f604 | 252 | s390_cpu_model_register_props(obj); |
8f22e0df AF |
253 | #if !defined(CONFIG_USER_ONLY) |
254 | qemu_get_timedate(&tm, 0); | |
255 | env->tod_offset = TOD_UNIX_EPOCH + | |
256 | (time2tod(mktimegm(&tm)) * 1000000000ULL); | |
257 | env->tod_basetime = 0; | |
bc72ad67 AB |
258 | env->tod_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_tod_timer, cpu); |
259 | env->cpu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_cpu_timer, cpu); | |
eb24f7c6 | 260 | s390_cpu_set_state(CPU_STATE_STOPPED, cpu); |
8f22e0df | 261 | #endif |
2b7ac767 AF |
262 | |
263 | if (tcg_enabled() && !inited) { | |
264 | inited = true; | |
265 | s390x_translate_init(); | |
266 | } | |
8f22e0df AF |
267 | } |
268 | ||
d5627ce8 AF |
269 | static void s390_cpu_finalize(Object *obj) |
270 | { | |
271 | #if !defined(CONFIG_USER_ONLY) | |
272 | S390CPU *cpu = S390_CPU(obj); | |
273 | ||
274 | qemu_unregister_reset(s390_cpu_machine_reset_cb, cpu); | |
3cda44f7 | 275 | g_free(cpu->irqstate); |
d5627ce8 AF |
276 | #endif |
277 | } | |
278 | ||
75973bfe | 279 | #if !defined(CONFIG_USER_ONLY) |
eb24f7c6 DH |
280 | static bool disabled_wait(CPUState *cpu) |
281 | { | |
282 | return cpu->halted && !(S390_CPU(cpu)->env.psw.mask & | |
283 | (PSW_MASK_IO | PSW_MASK_EXT | PSW_MASK_MCHECK)); | |
284 | } | |
285 | ||
75973bfe DH |
286 | static unsigned s390_count_running_cpus(void) |
287 | { | |
288 | CPUState *cpu; | |
289 | int nr_running = 0; | |
290 | ||
291 | CPU_FOREACH(cpu) { | |
292 | uint8_t state = S390_CPU(cpu)->env.cpu_state; | |
293 | if (state == CPU_STATE_OPERATING || | |
294 | state == CPU_STATE_LOAD) { | |
eb24f7c6 DH |
295 | if (!disabled_wait(cpu)) { |
296 | nr_running++; | |
297 | } | |
75973bfe DH |
298 | } |
299 | } | |
300 | ||
301 | return nr_running; | |
302 | } | |
303 | ||
eb24f7c6 | 304 | unsigned int s390_cpu_halt(S390CPU *cpu) |
75973bfe DH |
305 | { |
306 | CPUState *cs = CPU(cpu); | |
eb24f7c6 | 307 | trace_cpu_halt(cs->cpu_index); |
75973bfe | 308 | |
eb24f7c6 DH |
309 | if (!cs->halted) { |
310 | cs->halted = 1; | |
311 | cs->exception_index = EXCP_HLT; | |
75973bfe | 312 | } |
eb24f7c6 DH |
313 | |
314 | return s390_count_running_cpus(); | |
75973bfe DH |
315 | } |
316 | ||
eb24f7c6 | 317 | void s390_cpu_unhalt(S390CPU *cpu) |
75973bfe DH |
318 | { |
319 | CPUState *cs = CPU(cpu); | |
eb24f7c6 | 320 | trace_cpu_unhalt(cs->cpu_index); |
75973bfe | 321 | |
eb24f7c6 DH |
322 | if (cs->halted) { |
323 | cs->halted = 0; | |
324 | cs->exception_index = -1; | |
325 | } | |
326 | } | |
327 | ||
328 | unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu) | |
329 | { | |
330 | trace_cpu_set_state(CPU(cpu)->cpu_index, cpu_state); | |
331 | ||
332 | switch (cpu_state) { | |
333 | case CPU_STATE_STOPPED: | |
334 | case CPU_STATE_CHECK_STOP: | |
335 | /* halt the cpu for common infrastructure */ | |
336 | s390_cpu_halt(cpu); | |
337 | break; | |
338 | case CPU_STATE_OPERATING: | |
339 | case CPU_STATE_LOAD: | |
741a4ec1 DH |
340 | /* |
341 | * Starting a CPU with a PSW WAIT bit set: | |
342 | * KVM: handles this internally and triggers another WAIT exit. | |
343 | * TCG: will actually try to continue to run. Don't unhalt, will | |
344 | * be done when the CPU actually has work (an interrupt). | |
345 | */ | |
346 | if (!tcg_enabled() || !(cpu->env.psw.mask & PSW_MASK_WAIT)) { | |
347 | s390_cpu_unhalt(cpu); | |
348 | } | |
eb24f7c6 DH |
349 | break; |
350 | default: | |
351 | error_report("Requested CPU state is not a valid S390 CPU state: %u", | |
352 | cpu_state); | |
353 | exit(1); | |
75973bfe | 354 | } |
c9e659c9 DH |
355 | if (kvm_enabled() && cpu->env.cpu_state != cpu_state) { |
356 | kvm_s390_set_cpu_state(cpu, cpu_state); | |
357 | } | |
eb24f7c6 | 358 | cpu->env.cpu_state = cpu_state; |
75973bfe DH |
359 | |
360 | return s390_count_running_cpus(); | |
361 | } | |
b6089b05 DH |
362 | |
363 | int s390_get_clock(uint8_t *tod_high, uint64_t *tod_low) | |
364 | { | |
7edd4a49 CW |
365 | int r = 0; |
366 | ||
b6089b05 | 367 | if (kvm_enabled()) { |
7edd4a49 CW |
368 | r = kvm_s390_get_clock_ext(tod_high, tod_low); |
369 | if (r == -ENXIO) { | |
370 | return kvm_s390_get_clock(tod_high, tod_low); | |
371 | } | |
372 | } else { | |
373 | /* Fixme TCG */ | |
374 | *tod_high = 0; | |
375 | *tod_low = 0; | |
b6089b05 | 376 | } |
7edd4a49 CW |
377 | |
378 | return r; | |
b6089b05 DH |
379 | } |
380 | ||
381 | int s390_set_clock(uint8_t *tod_high, uint64_t *tod_low) | |
382 | { | |
7edd4a49 CW |
383 | int r = 0; |
384 | ||
b6089b05 | 385 | if (kvm_enabled()) { |
7edd4a49 CW |
386 | r = kvm_s390_set_clock_ext(tod_high, tod_low); |
387 | if (r == -ENXIO) { | |
388 | return kvm_s390_set_clock(tod_high, tod_low); | |
389 | } | |
b6089b05 DH |
390 | } |
391 | /* Fixme TCG */ | |
7edd4a49 | 392 | return r; |
b6089b05 DH |
393 | } |
394 | ||
395 | int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit) | |
396 | { | |
397 | if (kvm_enabled()) { | |
398 | return kvm_s390_set_mem_limit(new_limit, hw_limit); | |
399 | } | |
400 | return 0; | |
401 | } | |
402 | ||
403 | void s390_cmma_reset(void) | |
404 | { | |
405 | if (kvm_enabled()) { | |
406 | kvm_s390_cmma_reset(); | |
407 | } | |
408 | } | |
409 | ||
b6089b05 DH |
410 | int s390_get_memslot_count(void) |
411 | { | |
412 | if (kvm_enabled()) { | |
413 | return kvm_s390_get_memslot_count(); | |
414 | } else { | |
415 | return MAX_AVAIL_SLOTS; | |
416 | } | |
417 | } | |
418 | ||
419 | int s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch_id, | |
420 | int vq, bool assign) | |
421 | { | |
422 | if (kvm_enabled()) { | |
423 | return kvm_s390_assign_subch_ioeventfd(notifier, sch_id, vq, assign); | |
424 | } else { | |
425 | return 0; | |
426 | } | |
427 | } | |
428 | ||
429 | void s390_crypto_reset(void) | |
430 | { | |
431 | if (kvm_enabled()) { | |
432 | kvm_s390_crypto_reset(); | |
433 | } | |
434 | } | |
435 | ||
436 | bool s390_get_squash_mcss(void) | |
437 | { | |
438 | if (object_property_get_bool(OBJECT(qdev_get_machine()), "s390-squash-mcss", | |
439 | NULL)) { | |
440 | return true; | |
441 | } | |
442 | ||
443 | return false; | |
444 | } | |
5e7164c5 DH |
445 | |
446 | void s390_enable_css_support(S390CPU *cpu) | |
447 | { | |
448 | if (kvm_enabled()) { | |
449 | kvm_s390_enable_css_support(cpu); | |
450 | } | |
451 | } | |
75973bfe DH |
452 | #endif |
453 | ||
b3820e6c DH |
454 | static gchar *s390_gdb_arch_name(CPUState *cs) |
455 | { | |
456 | return g_strdup("s390:64-bit"); | |
457 | } | |
458 | ||
ca5c1457 | 459 | static Property s390x_cpu_properties[] = { |
1e70ba24 | 460 | #if !defined(CONFIG_USER_ONLY) |
ca5c1457 | 461 | DEFINE_PROP_UINT32("core-id", S390CPU, env.core_id, 0), |
1e70ba24 | 462 | #endif |
ca5c1457 DH |
463 | DEFINE_PROP_END_OF_LIST() |
464 | }; | |
465 | ||
29e4bcb2 AF |
466 | static void s390_cpu_class_init(ObjectClass *oc, void *data) |
467 | { | |
468 | S390CPUClass *scc = S390_CPU_CLASS(oc); | |
469 | CPUClass *cc = CPU_CLASS(scc); | |
c7396bbb | 470 | DeviceClass *dc = DEVICE_CLASS(oc); |
29e4bcb2 | 471 | |
1f136632 AF |
472 | scc->parent_realize = dc->realize; |
473 | dc->realize = s390_cpu_realizefn; | |
ca5c1457 | 474 | dc->props = s390x_cpu_properties; |
0347ab84 | 475 | dc->user_creatable = true; |
1f136632 | 476 | |
29e4bcb2 | 477 | scc->parent_reset = cc->reset; |
29c6157c CB |
478 | #if !defined(CONFIG_USER_ONLY) |
479 | scc->load_normal = s390_cpu_load_normal; | |
480 | #endif | |
f5ae2a4f CB |
481 | scc->cpu_reset = s390_cpu_reset; |
482 | scc->initial_cpu_reset = s390_cpu_initial_reset; | |
483 | cc->reset = s390_cpu_full_reset; | |
41868f84 | 484 | cc->class_by_name = s390_cpu_class_by_name, |
8c2e1b00 | 485 | cc->has_work = s390_cpu_has_work; |
b114588c | 486 | #ifdef CONFIG_TCG |
97a8ea5a | 487 | cc->do_interrupt = s390_cpu_do_interrupt; |
b114588c | 488 | #endif |
878096ee | 489 | cc->dump_state = s390_cpu_dump_state; |
f45748f1 | 490 | cc->set_pc = s390_cpu_set_pc; |
5b50e790 AF |
491 | cc->gdb_read_register = s390_cpu_gdb_read_register; |
492 | cc->gdb_write_register = s390_cpu_gdb_write_register; | |
7510454e AF |
493 | #ifdef CONFIG_USER_ONLY |
494 | cc->handle_mmu_fault = s390_cpu_handle_mmu_fault; | |
495 | #else | |
00b941e5 | 496 | cc->get_phys_page_debug = s390_cpu_get_phys_page_debug; |
ef1df130 | 497 | cc->vmsd = &vmstate_s390_cpu; |
9b4f38e1 | 498 | cc->write_elf64_note = s390_cpu_write_elf64_note; |
b114588c | 499 | #ifdef CONFIG_TCG |
02bb9bbf | 500 | cc->cpu_exec_interrupt = s390_cpu_exec_interrupt; |
311918b9 | 501 | cc->debug_excp_handler = s390x_cpu_debug_excp_handler; |
44977a8f | 502 | cc->do_unaligned_access = s390x_cpu_do_unaligned_access; |
b114588c | 503 | #endif |
00b941e5 | 504 | #endif |
dbad6b74 PC |
505 | cc->disas_set_info = s390_cpu_disas_set_info; |
506 | ||
73d510c9 DH |
507 | cc->gdb_num_core_regs = S390_NUM_CORE_REGS; |
508 | cc->gdb_core_xml_file = "s390x-core64.xml"; | |
b3820e6c | 509 | cc->gdb_arch_name = s390_gdb_arch_name; |
4c315c27 | 510 | |
6efadc90 | 511 | s390_cpu_model_class_register_props(oc); |
29e4bcb2 AF |
512 | } |
513 | ||
514 | static const TypeInfo s390_cpu_type_info = { | |
515 | .name = TYPE_S390_CPU, | |
516 | .parent = TYPE_CPU, | |
517 | .instance_size = sizeof(S390CPU), | |
8f22e0df | 518 | .instance_init = s390_cpu_initfn, |
d5627ce8 | 519 | .instance_finalize = s390_cpu_finalize, |
41868f84 | 520 | .abstract = true, |
29e4bcb2 AF |
521 | .class_size = sizeof(S390CPUClass), |
522 | .class_init = s390_cpu_class_init, | |
523 | }; | |
524 | ||
525 | static void s390_cpu_register_types(void) | |
526 | { | |
527 | type_register_static(&s390_cpu_type_info); | |
528 | } | |
529 | ||
530 | type_init(s390_cpu_register_types) |