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Commit | Line | Data |
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29e4bcb2 AF |
1 | /* |
2 | * QEMU S/390 CPU | |
3 | * | |
1ac1a749 AF |
4 | * Copyright (c) 2009 Ulrich Hecht |
5 | * Copyright (c) 2011 Alexander Graf | |
29e4bcb2 | 6 | * Copyright (c) 2012 SUSE LINUX Products GmbH |
70bada03 | 7 | * Copyright (c) 2012 IBM Corp. |
29e4bcb2 AF |
8 | * |
9 | * This library is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU Lesser General Public | |
11 | * License as published by the Free Software Foundation; either | |
12 | * version 2.1 of the License, or (at your option) any later version. | |
13 | * | |
14 | * This library is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * Lesser General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU Lesser General Public | |
20 | * License along with this library; if not, see | |
21 | * <http://www.gnu.org/licenses/lgpl-2.1.html> | |
70bada03 JF |
22 | * Contributions after 2012-12-11 are licensed under the terms of the |
23 | * GNU GPL, version 2 or (at your option) any later version. | |
29e4bcb2 AF |
24 | */ |
25 | ||
9615495a | 26 | #include "qemu/osdep.h" |
da34e65c | 27 | #include "qapi/error.h" |
564b863d | 28 | #include "cpu.h" |
4e58b838 | 29 | #include "internal.h" |
f16bbb9b DH |
30 | #include "kvm_s390x.h" |
31 | #include "sysemu/kvm.h" | |
29e4bcb2 | 32 | #include "qemu-common.h" |
f348b6d1 | 33 | #include "qemu/cutils.h" |
1de7afc9 | 34 | #include "qemu/timer.h" |
eb24f7c6 | 35 | #include "qemu/error-report.h" |
eb24f7c6 | 36 | #include "trace.h" |
96b1a8bb | 37 | #include "qapi/visitor.h" |
63c91552 | 38 | #include "exec/exec-all.h" |
ca5c1457 | 39 | #include "hw/qdev-properties.h" |
c7396bbb | 40 | #ifndef CONFIG_USER_ONLY |
741da0d3 | 41 | #include "hw/hw.h" |
904e5fd5 | 42 | #include "sysemu/arch_init.h" |
96b1a8bb | 43 | #include "sysemu/sysemu.h" |
a006b67f | 44 | #include "hw/s390x/sclp.h" |
904e5fd5 VM |
45 | #endif |
46 | ||
70bada03 JF |
47 | #define CR0_RESET 0xE0UL |
48 | #define CR14_RESET 0xC2000000UL; | |
49 | ||
f45748f1 AF |
50 | static void s390_cpu_set_pc(CPUState *cs, vaddr value) |
51 | { | |
52 | S390CPU *cpu = S390_CPU(cs); | |
53 | ||
54 | cpu->env.psw.addr = value; | |
55 | } | |
56 | ||
8c2e1b00 AF |
57 | static bool s390_cpu_has_work(CPUState *cs) |
58 | { | |
59 | S390CPU *cpu = S390_CPU(cs); | |
60 | CPUS390XState *env = &cpu->env; | |
61 | ||
62 | return (cs->interrupt_request & CPU_INTERRUPT_HARD) && | |
63 | (env->psw.mask & PSW_MASK_EXT); | |
64 | } | |
65 | ||
29c6157c CB |
66 | #if !defined(CONFIG_USER_ONLY) |
67 | /* S390CPUClass::load_normal() */ | |
68 | static void s390_cpu_load_normal(CPUState *s) | |
69 | { | |
70 | S390CPU *cpu = S390_CPU(s); | |
fdfba1a2 | 71 | cpu->env.psw.addr = ldl_phys(s->as, 4) & PSW_MASK_ESA_ADDR; |
29c6157c | 72 | cpu->env.psw.mask = PSW_MASK_32 | PSW_MASK_64; |
eb24f7c6 | 73 | s390_cpu_set_state(CPU_STATE_OPERATING, cpu); |
29c6157c CB |
74 | } |
75 | #endif | |
76 | ||
f5ae2a4f | 77 | /* S390CPUClass::cpu_reset() */ |
29e4bcb2 AF |
78 | static void s390_cpu_reset(CPUState *s) |
79 | { | |
80 | S390CPU *cpu = S390_CPU(s); | |
81 | S390CPUClass *scc = S390_CPU_GET_CLASS(cpu); | |
82 | CPUS390XState *env = &cpu->env; | |
83 | ||
819bd309 | 84 | env->pfault_token = -1UL; |
f5ae2a4f | 85 | scc->parent_reset(s); |
18ff9494 | 86 | cpu->env.sigp_order = 0; |
eb24f7c6 | 87 | s390_cpu_set_state(CPU_STATE_STOPPED, cpu); |
f5ae2a4f CB |
88 | } |
89 | ||
90 | /* S390CPUClass::initial_reset() */ | |
91 | static void s390_cpu_initial_reset(CPUState *s) | |
92 | { | |
93 | S390CPU *cpu = S390_CPU(s); | |
94 | CPUS390XState *env = &cpu->env; | |
cc0d079d | 95 | int i; |
f5ae2a4f CB |
96 | |
97 | s390_cpu_reset(s); | |
cb4f4bc3 CB |
98 | /* initial reset does not clear everything! */ |
99 | memset(&env->start_initial_reset_fields, 0, | |
100 | offsetof(CPUS390XState, end_reset_fields) - | |
101 | offsetof(CPUS390XState, start_initial_reset_fields)); | |
f5ae2a4f CB |
102 | |
103 | /* architectured initial values for CR 0 and 14 */ | |
104 | env->cregs[0] = CR0_RESET; | |
105 | env->cregs[14] = CR14_RESET; | |
819bd309 | 106 | |
3da0ab35 AJ |
107 | /* architectured initial value for Breaking-Event-Address register */ |
108 | env->gbea = 1; | |
109 | ||
819bd309 | 110 | env->pfault_token = -1UL; |
7107e5a7 | 111 | env->ext_index = -1; |
cc0d079d AJ |
112 | for (i = 0; i < ARRAY_SIZE(env->io_index); i++) { |
113 | env->io_index[i] = -1; | |
114 | } | |
49f5c9e9 | 115 | |
4a33565f AJ |
116 | /* tininess for underflow is detected before rounding */ |
117 | set_float_detect_tininess(float_tininess_before_rounding, | |
118 | &env->fpu_status); | |
119 | ||
49f5c9e9 TH |
120 | /* Reset state inside the kernel that we cannot access yet from QEMU. */ |
121 | if (kvm_enabled()) { | |
99607144 | 122 | kvm_s390_reset_vcpu(cpu); |
49f5c9e9 | 123 | } |
f5ae2a4f CB |
124 | } |
125 | ||
126 | /* CPUClass:reset() */ | |
127 | static void s390_cpu_full_reset(CPUState *s) | |
128 | { | |
129 | S390CPU *cpu = S390_CPU(s); | |
130 | S390CPUClass *scc = S390_CPU_GET_CLASS(cpu); | |
131 | CPUS390XState *env = &cpu->env; | |
cc0d079d | 132 | int i; |
f5ae2a4f | 133 | |
29e4bcb2 | 134 | scc->parent_reset(s); |
18ff9494 | 135 | cpu->env.sigp_order = 0; |
eb24f7c6 | 136 | s390_cpu_set_state(CPU_STATE_STOPPED, cpu); |
29e4bcb2 | 137 | |
1f5c00cf | 138 | memset(env, 0, offsetof(CPUS390XState, end_reset_fields)); |
70bada03 JF |
139 | |
140 | /* architectured initial values for CR 0 and 14 */ | |
141 | env->cregs[0] = CR0_RESET; | |
142 | env->cregs[14] = CR14_RESET; | |
819bd309 | 143 | |
3da0ab35 AJ |
144 | /* architectured initial value for Breaking-Event-Address register */ |
145 | env->gbea = 1; | |
146 | ||
819bd309 | 147 | env->pfault_token = -1UL; |
7107e5a7 | 148 | env->ext_index = -1; |
cc0d079d AJ |
149 | for (i = 0; i < ARRAY_SIZE(env->io_index); i++) { |
150 | env->io_index[i] = -1; | |
151 | } | |
819bd309 | 152 | |
4a33565f AJ |
153 | /* tininess for underflow is detected before rounding */ |
154 | set_float_detect_tininess(float_tininess_before_rounding, | |
155 | &env->fpu_status); | |
156 | ||
99607144 | 157 | /* Reset state inside the kernel that we cannot access yet from QEMU. */ |
50a2c6e5 PB |
158 | if (kvm_enabled()) { |
159 | kvm_s390_reset_vcpu(cpu); | |
160 | } | |
29e4bcb2 AF |
161 | } |
162 | ||
70bada03 JF |
163 | #if !defined(CONFIG_USER_ONLY) |
164 | static void s390_cpu_machine_reset_cb(void *opaque) | |
165 | { | |
166 | S390CPU *cpu = opaque; | |
167 | ||
14e6fe12 | 168 | run_on_cpu(CPU(cpu), s390_do_cpu_full_reset, RUN_ON_CPU_NULL); |
70bada03 JF |
169 | } |
170 | #endif | |
171 | ||
dbad6b74 PC |
172 | static void s390_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) |
173 | { | |
174 | info->mach = bfd_mach_s390_64; | |
175 | info->print_insn = print_insn_s390; | |
176 | } | |
177 | ||
1f136632 AF |
178 | static void s390_cpu_realizefn(DeviceState *dev, Error **errp) |
179 | { | |
14a10fc3 | 180 | CPUState *cs = CPU(dev); |
1f136632 | 181 | S390CPUClass *scc = S390_CPU_GET_CLASS(dev); |
c6644fc8 MR |
182 | S390CPU *cpu = S390_CPU(dev); |
183 | CPUS390XState *env = &cpu->env; | |
184 | Error *err = NULL; | |
185 | ||
41868f84 DH |
186 | /* the model has to be realized before qemu_init_vcpu() due to kvm */ |
187 | s390_realize_cpu_model(cs, &err); | |
188 | if (err) { | |
189 | goto out; | |
190 | } | |
191 | ||
96b1a8bb | 192 | #if !defined(CONFIG_USER_ONLY) |
ca5c1457 DH |
193 | if (cpu->env.core_id >= max_cpus) { |
194 | error_setg(&err, "Unable to add CPU with core-id: %" PRIu32 | |
195 | ", maximum core-id: %d", cpu->env.core_id, | |
196 | max_cpus - 1); | |
96b1a8bb MR |
197 | goto out; |
198 | } | |
88556edd DH |
199 | #else |
200 | /* implicitly set for linux-user only */ | |
b599fef2 | 201 | cpu->env.core_id = scc->next_core_id; |
96b1a8bb | 202 | #endif |
88556edd | 203 | |
ca5c1457 DH |
204 | if (cpu_exists(cpu->env.core_id)) { |
205 | error_setg(&err, "Unable to add CPU with core-id: %" PRIu32 | |
206 | ", it already exists", cpu->env.core_id); | |
96b1a8bb MR |
207 | goto out; |
208 | } | |
b599fef2 | 209 | if (cpu->env.core_id != scc->next_core_id) { |
ca5c1457 | 210 | error_setg(&err, "Unable to add CPU with core-id: %" PRIu32 |
b599fef2 DH |
211 | ", the next available core-id is %" PRIu32, cpu->env.core_id, |
212 | scc->next_core_id); | |
96b1a8bb MR |
213 | goto out; |
214 | } | |
215 | ||
ca5c1457 DH |
216 | /* sync cs->cpu_index and env->core_id. The latter is needed for TCG. */ |
217 | cs->cpu_index = env->core_id; | |
ce5b1bbf | 218 | cpu_exec_realizefn(cs, &err); |
c6644fc8 | 219 | if (err != NULL) { |
96b1a8bb | 220 | goto out; |
c6644fc8 | 221 | } |
b599fef2 | 222 | scc->next_core_id++; |
1f136632 | 223 | |
c6644fc8 MR |
224 | #if !defined(CONFIG_USER_ONLY) |
225 | qemu_register_reset(s390_cpu_machine_reset_cb, cpu); | |
226 | #endif | |
73d510c9 | 227 | s390_cpu_gdb_init(cs); |
14a10fc3 | 228 | qemu_init_vcpu(cs); |
159855f0 | 229 | #if !defined(CONFIG_USER_ONLY) |
14e6fe12 | 230 | run_on_cpu(cs, s390_do_cpu_full_reset, RUN_ON_CPU_NULL); |
159855f0 | 231 | #else |
14a10fc3 | 232 | cpu_reset(cs); |
159855f0 | 233 | #endif |
1f136632 | 234 | |
96b1a8bb MR |
235 | scc->parent_realize(dev, &err); |
236 | ||
a006b67f MR |
237 | #if !defined(CONFIG_USER_ONLY) |
238 | if (dev->hotplugged) { | |
239 | raise_irq_cpu_hotplug(); | |
240 | } | |
241 | #endif | |
242 | ||
96b1a8bb MR |
243 | out: |
244 | error_propagate(errp, err); | |
245 | } | |
246 | ||
8f22e0df AF |
247 | static void s390_cpu_initfn(Object *obj) |
248 | { | |
c05efcb1 | 249 | CPUState *cs = CPU(obj); |
8f22e0df AF |
250 | S390CPU *cpu = S390_CPU(obj); |
251 | CPUS390XState *env = &cpu->env; | |
2b7ac767 | 252 | static bool inited; |
8f22e0df AF |
253 | #if !defined(CONFIG_USER_ONLY) |
254 | struct tm tm; | |
255 | #endif | |
256 | ||
c05efcb1 | 257 | cs->env_ptr = env; |
ef3027af MR |
258 | cs->halted = 1; |
259 | cs->exception_index = EXCP_HLT; | |
0754f604 | 260 | s390_cpu_model_register_props(obj); |
8f22e0df AF |
261 | #if !defined(CONFIG_USER_ONLY) |
262 | qemu_get_timedate(&tm, 0); | |
263 | env->tod_offset = TOD_UNIX_EPOCH + | |
264 | (time2tod(mktimegm(&tm)) * 1000000000ULL); | |
265 | env->tod_basetime = 0; | |
bc72ad67 AB |
266 | env->tod_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_tod_timer, cpu); |
267 | env->cpu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_cpu_timer, cpu); | |
eb24f7c6 | 268 | s390_cpu_set_state(CPU_STATE_STOPPED, cpu); |
8f22e0df | 269 | #endif |
2b7ac767 AF |
270 | |
271 | if (tcg_enabled() && !inited) { | |
272 | inited = true; | |
273 | s390x_translate_init(); | |
274 | } | |
8f22e0df AF |
275 | } |
276 | ||
d5627ce8 AF |
277 | static void s390_cpu_finalize(Object *obj) |
278 | { | |
279 | #if !defined(CONFIG_USER_ONLY) | |
280 | S390CPU *cpu = S390_CPU(obj); | |
281 | ||
282 | qemu_unregister_reset(s390_cpu_machine_reset_cb, cpu); | |
3cda44f7 | 283 | g_free(cpu->irqstate); |
d5627ce8 AF |
284 | #endif |
285 | } | |
286 | ||
75973bfe | 287 | #if !defined(CONFIG_USER_ONLY) |
eb24f7c6 DH |
288 | static bool disabled_wait(CPUState *cpu) |
289 | { | |
290 | return cpu->halted && !(S390_CPU(cpu)->env.psw.mask & | |
291 | (PSW_MASK_IO | PSW_MASK_EXT | PSW_MASK_MCHECK)); | |
292 | } | |
293 | ||
75973bfe DH |
294 | static unsigned s390_count_running_cpus(void) |
295 | { | |
296 | CPUState *cpu; | |
297 | int nr_running = 0; | |
298 | ||
299 | CPU_FOREACH(cpu) { | |
300 | uint8_t state = S390_CPU(cpu)->env.cpu_state; | |
301 | if (state == CPU_STATE_OPERATING || | |
302 | state == CPU_STATE_LOAD) { | |
eb24f7c6 DH |
303 | if (!disabled_wait(cpu)) { |
304 | nr_running++; | |
305 | } | |
75973bfe DH |
306 | } |
307 | } | |
308 | ||
309 | return nr_running; | |
310 | } | |
311 | ||
eb24f7c6 | 312 | unsigned int s390_cpu_halt(S390CPU *cpu) |
75973bfe DH |
313 | { |
314 | CPUState *cs = CPU(cpu); | |
eb24f7c6 | 315 | trace_cpu_halt(cs->cpu_index); |
75973bfe | 316 | |
eb24f7c6 DH |
317 | if (!cs->halted) { |
318 | cs->halted = 1; | |
319 | cs->exception_index = EXCP_HLT; | |
75973bfe | 320 | } |
eb24f7c6 DH |
321 | |
322 | return s390_count_running_cpus(); | |
75973bfe DH |
323 | } |
324 | ||
eb24f7c6 | 325 | void s390_cpu_unhalt(S390CPU *cpu) |
75973bfe DH |
326 | { |
327 | CPUState *cs = CPU(cpu); | |
eb24f7c6 | 328 | trace_cpu_unhalt(cs->cpu_index); |
75973bfe | 329 | |
eb24f7c6 DH |
330 | if (cs->halted) { |
331 | cs->halted = 0; | |
332 | cs->exception_index = -1; | |
333 | } | |
334 | } | |
335 | ||
336 | unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu) | |
337 | { | |
338 | trace_cpu_set_state(CPU(cpu)->cpu_index, cpu_state); | |
339 | ||
340 | switch (cpu_state) { | |
341 | case CPU_STATE_STOPPED: | |
342 | case CPU_STATE_CHECK_STOP: | |
343 | /* halt the cpu for common infrastructure */ | |
344 | s390_cpu_halt(cpu); | |
345 | break; | |
346 | case CPU_STATE_OPERATING: | |
347 | case CPU_STATE_LOAD: | |
348 | /* unhalt the cpu for common infrastructure */ | |
349 | s390_cpu_unhalt(cpu); | |
350 | break; | |
351 | default: | |
352 | error_report("Requested CPU state is not a valid S390 CPU state: %u", | |
353 | cpu_state); | |
354 | exit(1); | |
75973bfe | 355 | } |
c9e659c9 DH |
356 | if (kvm_enabled() && cpu->env.cpu_state != cpu_state) { |
357 | kvm_s390_set_cpu_state(cpu, cpu_state); | |
358 | } | |
eb24f7c6 | 359 | cpu->env.cpu_state = cpu_state; |
75973bfe DH |
360 | |
361 | return s390_count_running_cpus(); | |
362 | } | |
b6089b05 DH |
363 | |
364 | int s390_get_clock(uint8_t *tod_high, uint64_t *tod_low) | |
365 | { | |
366 | if (kvm_enabled()) { | |
367 | return kvm_s390_get_clock(tod_high, tod_low); | |
368 | } | |
369 | /* Fixme TCG */ | |
370 | *tod_high = 0; | |
371 | *tod_low = 0; | |
372 | return 0; | |
373 | } | |
374 | ||
375 | int s390_set_clock(uint8_t *tod_high, uint64_t *tod_low) | |
376 | { | |
377 | if (kvm_enabled()) { | |
378 | return kvm_s390_set_clock(tod_high, tod_low); | |
379 | } | |
380 | /* Fixme TCG */ | |
381 | return 0; | |
382 | } | |
383 | ||
384 | int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit) | |
385 | { | |
386 | if (kvm_enabled()) { | |
387 | return kvm_s390_set_mem_limit(new_limit, hw_limit); | |
388 | } | |
389 | return 0; | |
390 | } | |
391 | ||
392 | void s390_cmma_reset(void) | |
393 | { | |
394 | if (kvm_enabled()) { | |
395 | kvm_s390_cmma_reset(); | |
396 | } | |
397 | } | |
398 | ||
399 | int s390_cpu_restart(S390CPU *cpu) | |
400 | { | |
401 | if (kvm_enabled()) { | |
402 | return kvm_s390_cpu_restart(cpu); | |
403 | } | |
404 | return -ENOSYS; | |
405 | } | |
406 | ||
407 | int s390_get_memslot_count(void) | |
408 | { | |
409 | if (kvm_enabled()) { | |
410 | return kvm_s390_get_memslot_count(); | |
411 | } else { | |
412 | return MAX_AVAIL_SLOTS; | |
413 | } | |
414 | } | |
415 | ||
416 | int s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch_id, | |
417 | int vq, bool assign) | |
418 | { | |
419 | if (kvm_enabled()) { | |
420 | return kvm_s390_assign_subch_ioeventfd(notifier, sch_id, vq, assign); | |
421 | } else { | |
422 | return 0; | |
423 | } | |
424 | } | |
425 | ||
426 | void s390_crypto_reset(void) | |
427 | { | |
428 | if (kvm_enabled()) { | |
429 | kvm_s390_crypto_reset(); | |
430 | } | |
431 | } | |
432 | ||
433 | bool s390_get_squash_mcss(void) | |
434 | { | |
435 | if (object_property_get_bool(OBJECT(qdev_get_machine()), "s390-squash-mcss", | |
436 | NULL)) { | |
437 | return true; | |
438 | } | |
439 | ||
440 | return false; | |
441 | } | |
5e7164c5 DH |
442 | |
443 | void s390_enable_css_support(S390CPU *cpu) | |
444 | { | |
445 | if (kvm_enabled()) { | |
446 | kvm_s390_enable_css_support(cpu); | |
447 | } | |
448 | } | |
75973bfe DH |
449 | #endif |
450 | ||
b3820e6c DH |
451 | static gchar *s390_gdb_arch_name(CPUState *cs) |
452 | { | |
453 | return g_strdup("s390:64-bit"); | |
454 | } | |
455 | ||
ca5c1457 DH |
456 | static Property s390x_cpu_properties[] = { |
457 | DEFINE_PROP_UINT32("core-id", S390CPU, env.core_id, 0), | |
458 | DEFINE_PROP_END_OF_LIST() | |
459 | }; | |
460 | ||
29e4bcb2 AF |
461 | static void s390_cpu_class_init(ObjectClass *oc, void *data) |
462 | { | |
463 | S390CPUClass *scc = S390_CPU_CLASS(oc); | |
464 | CPUClass *cc = CPU_CLASS(scc); | |
c7396bbb | 465 | DeviceClass *dc = DEVICE_CLASS(oc); |
29e4bcb2 | 466 | |
1f136632 AF |
467 | scc->parent_realize = dc->realize; |
468 | dc->realize = s390_cpu_realizefn; | |
ca5c1457 | 469 | dc->props = s390x_cpu_properties; |
1f136632 | 470 | |
29e4bcb2 | 471 | scc->parent_reset = cc->reset; |
29c6157c CB |
472 | #if !defined(CONFIG_USER_ONLY) |
473 | scc->load_normal = s390_cpu_load_normal; | |
474 | #endif | |
f5ae2a4f CB |
475 | scc->cpu_reset = s390_cpu_reset; |
476 | scc->initial_cpu_reset = s390_cpu_initial_reset; | |
477 | cc->reset = s390_cpu_full_reset; | |
41868f84 | 478 | cc->class_by_name = s390_cpu_class_by_name, |
8c2e1b00 | 479 | cc->has_work = s390_cpu_has_work; |
b114588c | 480 | #ifdef CONFIG_TCG |
97a8ea5a | 481 | cc->do_interrupt = s390_cpu_do_interrupt; |
b114588c | 482 | #endif |
878096ee | 483 | cc->dump_state = s390_cpu_dump_state; |
f45748f1 | 484 | cc->set_pc = s390_cpu_set_pc; |
5b50e790 AF |
485 | cc->gdb_read_register = s390_cpu_gdb_read_register; |
486 | cc->gdb_write_register = s390_cpu_gdb_write_register; | |
7510454e AF |
487 | #ifdef CONFIG_USER_ONLY |
488 | cc->handle_mmu_fault = s390_cpu_handle_mmu_fault; | |
489 | #else | |
00b941e5 | 490 | cc->get_phys_page_debug = s390_cpu_get_phys_page_debug; |
ef1df130 | 491 | cc->vmsd = &vmstate_s390_cpu; |
9b4f38e1 | 492 | cc->write_elf64_note = s390_cpu_write_elf64_note; |
b114588c | 493 | #ifdef CONFIG_TCG |
02bb9bbf | 494 | cc->cpu_exec_interrupt = s390_cpu_exec_interrupt; |
311918b9 | 495 | cc->debug_excp_handler = s390x_cpu_debug_excp_handler; |
44977a8f | 496 | cc->do_unaligned_access = s390x_cpu_do_unaligned_access; |
b114588c | 497 | #endif |
00b941e5 | 498 | #endif |
dbad6b74 PC |
499 | cc->disas_set_info = s390_cpu_disas_set_info; |
500 | ||
73d510c9 DH |
501 | cc->gdb_num_core_regs = S390_NUM_CORE_REGS; |
502 | cc->gdb_core_xml_file = "s390x-core64.xml"; | |
b3820e6c | 503 | cc->gdb_arch_name = s390_gdb_arch_name; |
4c315c27 | 504 | |
6efadc90 | 505 | s390_cpu_model_class_register_props(oc); |
29e4bcb2 AF |
506 | } |
507 | ||
508 | static const TypeInfo s390_cpu_type_info = { | |
509 | .name = TYPE_S390_CPU, | |
510 | .parent = TYPE_CPU, | |
511 | .instance_size = sizeof(S390CPU), | |
8f22e0df | 512 | .instance_init = s390_cpu_initfn, |
d5627ce8 | 513 | .instance_finalize = s390_cpu_finalize, |
41868f84 | 514 | .abstract = true, |
29e4bcb2 AF |
515 | .class_size = sizeof(S390CPUClass), |
516 | .class_init = s390_cpu_class_init, | |
517 | }; | |
518 | ||
519 | static void s390_cpu_register_types(void) | |
520 | { | |
521 | type_register_static(&s390_cpu_type_info); | |
522 | } | |
523 | ||
524 | type_init(s390_cpu_register_types) |