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Commit | Line | Data |
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fdf9b3e8 FB |
1 | /* |
2 | * SH4 emulation | |
5fafdf24 | 3 | * |
fdf9b3e8 FB |
4 | * Copyright (c) 2005 Samuel Tardieu |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
6faf2b6c | 9 | * version 2.1 of the License, or (at your option) any later version. |
fdf9b3e8 FB |
10 | * |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
fdf9b3e8 | 18 | */ |
07f5a258 MA |
19 | |
20 | #ifndef SH4_CPU_H | |
21 | #define SH4_CPU_H | |
fdf9b3e8 | 22 | |
e6005f66 | 23 | #include "cpu-qom.h" |
74433bf0 | 24 | #include "exec/cpu-defs.h" |
69242e7e | 25 | #include "qemu/cpu-float.h" |
fdf9b3e8 | 26 | |
0fd3ca30 AJ |
27 | /* CPU Subtypes */ |
28 | #define SH_CPU_SH7750 (1 << 0) | |
29 | #define SH_CPU_SH7750S (1 << 1) | |
30 | #define SH_CPU_SH7750R (1 << 2) | |
31 | #define SH_CPU_SH7751 (1 << 3) | |
32 | #define SH_CPU_SH7751R (1 << 4) | |
a9c43f8e | 33 | #define SH_CPU_SH7785 (1 << 5) |
0fd3ca30 AJ |
34 | #define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R) |
35 | #define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R) | |
36 | ||
5ed9a259 AJ |
37 | #define SR_MD 30 |
38 | #define SR_RB 29 | |
39 | #define SR_BL 28 | |
40 | #define SR_FD 15 | |
41 | #define SR_M 9 | |
42 | #define SR_Q 8 | |
43 | #define SR_I3 7 | |
44 | #define SR_I2 6 | |
45 | #define SR_I1 5 | |
46 | #define SR_I0 4 | |
47 | #define SR_S 1 | |
48 | #define SR_T 0 | |
fdf9b3e8 | 49 | |
26ac1ea5 AJ |
50 | #define FPSCR_MASK (0x003fffff) |
51 | #define FPSCR_FR (1 << 21) | |
52 | #define FPSCR_SZ (1 << 20) | |
53 | #define FPSCR_PR (1 << 19) | |
54 | #define FPSCR_DN (1 << 18) | |
55 | #define FPSCR_CAUSE_MASK (0x3f << 12) | |
56 | #define FPSCR_CAUSE_SHIFT (12) | |
57 | #define FPSCR_CAUSE_E (1 << 17) | |
58 | #define FPSCR_CAUSE_V (1 << 16) | |
59 | #define FPSCR_CAUSE_Z (1 << 15) | |
60 | #define FPSCR_CAUSE_O (1 << 14) | |
61 | #define FPSCR_CAUSE_U (1 << 13) | |
62 | #define FPSCR_CAUSE_I (1 << 12) | |
63 | #define FPSCR_ENABLE_MASK (0x1f << 7) | |
64 | #define FPSCR_ENABLE_SHIFT (7) | |
65 | #define FPSCR_ENABLE_V (1 << 11) | |
66 | #define FPSCR_ENABLE_Z (1 << 10) | |
67 | #define FPSCR_ENABLE_O (1 << 9) | |
68 | #define FPSCR_ENABLE_U (1 << 8) | |
69 | #define FPSCR_ENABLE_I (1 << 7) | |
70 | #define FPSCR_FLAG_MASK (0x1f << 2) | |
71 | #define FPSCR_FLAG_SHIFT (2) | |
72 | #define FPSCR_FLAG_V (1 << 6) | |
73 | #define FPSCR_FLAG_Z (1 << 5) | |
74 | #define FPSCR_FLAG_O (1 << 4) | |
75 | #define FPSCR_FLAG_U (1 << 3) | |
76 | #define FPSCR_FLAG_I (1 << 2) | |
77 | #define FPSCR_RM_MASK (0x03 << 0) | |
78 | #define FPSCR_RM_NEAREST (0 << 0) | |
79 | #define FPSCR_RM_ZERO (1 << 0) | |
80 | ||
ab419fd8 RH |
81 | #define TB_FLAG_DELAY_SLOT (1 << 0) |
82 | #define TB_FLAG_DELAY_SLOT_COND (1 << 1) | |
83 | #define TB_FLAG_DELAY_SLOT_RTE (1 << 2) | |
84 | #define TB_FLAG_PENDING_MOVCA (1 << 3) | |
85 | #define TB_FLAG_GUSA_SHIFT 4 /* [11:4] */ | |
86 | #define TB_FLAG_GUSA_EXCLUSIVE (1 << 12) | |
87 | #define TB_FLAG_UNALIGN (1 << 13) | |
88 | #define TB_FLAG_SR_FD (1 << SR_FD) /* 15 */ | |
89 | #define TB_FLAG_FPSCR_PR FPSCR_PR /* 19 */ | |
90 | #define TB_FLAG_FPSCR_SZ FPSCR_SZ /* 20 */ | |
91 | #define TB_FLAG_FPSCR_FR FPSCR_FR /* 21 */ | |
92 | #define TB_FLAG_SR_RB (1 << SR_RB) /* 29 */ | |
93 | #define TB_FLAG_SR_MD (1 << SR_MD) /* 30 */ | |
94 | ||
95 | #define TB_FLAG_DELAY_SLOT_MASK (TB_FLAG_DELAY_SLOT | \ | |
96 | TB_FLAG_DELAY_SLOT_COND | \ | |
97 | TB_FLAG_DELAY_SLOT_RTE) | |
98 | #define TB_FLAG_GUSA_MASK ((0xff << TB_FLAG_GUSA_SHIFT) | \ | |
99 | TB_FLAG_GUSA_EXCLUSIVE) | |
100 | #define TB_FLAG_FPSCR_MASK (TB_FLAG_FPSCR_PR | \ | |
101 | TB_FLAG_FPSCR_SZ | \ | |
102 | TB_FLAG_FPSCR_FR) | |
103 | #define TB_FLAG_SR_MASK (TB_FLAG_SR_FD | \ | |
104 | TB_FLAG_SR_RB | \ | |
105 | TB_FLAG_SR_MD) | |
106 | #define TB_FLAG_ENVFLAGS_MASK (TB_FLAG_DELAY_SLOT_MASK | \ | |
107 | TB_FLAG_GUSA_MASK) | |
e1933d14 | 108 | |
fdf9b3e8 | 109 | typedef struct tlb_t { |
fdf9b3e8 | 110 | uint32_t vpn; /* virtual page number */ |
fdf9b3e8 | 111 | uint32_t ppn; /* physical page number */ |
af090497 AJ |
112 | uint32_t size; /* mapped page size in bytes */ |
113 | uint8_t asid; /* address space identifier */ | |
114 | uint8_t v:1; /* validity */ | |
115 | uint8_t sz:2; /* page size */ | |
116 | uint8_t sh:1; /* share status */ | |
117 | uint8_t c:1; /* cacheability */ | |
118 | uint8_t pr:2; /* protection key */ | |
119 | uint8_t d:1; /* dirty */ | |
120 | uint8_t wt:1; /* write through */ | |
121 | uint8_t sa:3; /* space attribute (PCMCIA) */ | |
122 | uint8_t tc:1; /* timing control */ | |
fdf9b3e8 FB |
123 | } tlb_t; |
124 | ||
125 | #define UTLB_SIZE 64 | |
126 | #define ITLB_SIZE 4 | |
127 | ||
07f3c16c | 128 | #define TARGET_INSN_START_EXTRA_WORDS 1 |
6ebbf390 | 129 | |
71968fa6 AJ |
130 | enum sh_features { |
131 | SH_FEATURE_SH4A = 1, | |
c2432a42 | 132 | SH_FEATURE_BCR3_AND_BCR4 = 2, |
71968fa6 AJ |
133 | }; |
134 | ||
852d481f EI |
135 | typedef struct memory_content { |
136 | uint32_t address; | |
137 | uint32_t value; | |
138 | struct memory_content *next; | |
139 | } memory_content; | |
140 | ||
1ea4a06a | 141 | typedef struct CPUArchState { |
fdf9b3e8 FB |
142 | uint32_t flags; /* general execution flags */ |
143 | uint32_t gregs[24]; /* general registers */ | |
e04ea3dc | 144 | float32 fregs[32]; /* floating point registers */ |
34086945 | 145 | uint32_t sr; /* status register (with T split out) */ |
1d565b21 AJ |
146 | uint32_t sr_m; /* M bit of status register */ |
147 | uint32_t sr_q; /* Q bit of status register */ | |
34086945 | 148 | uint32_t sr_t; /* T bit of status register */ |
fdf9b3e8 FB |
149 | uint32_t ssr; /* saved status register */ |
150 | uint32_t spc; /* saved program counter */ | |
151 | uint32_t gbr; /* global base register */ | |
152 | uint32_t vbr; /* vector base register */ | |
153 | uint32_t sgr; /* saved global register 15 */ | |
154 | uint32_t dbr; /* debug base register */ | |
155 | uint32_t pc; /* program counter */ | |
47b9f4d5 AJ |
156 | uint32_t delayed_pc; /* target of delayed branch */ |
157 | uint32_t delayed_cond; /* condition of delayed branch */ | |
fdf9b3e8 FB |
158 | uint32_t mach; /* multiply and accumulate high */ |
159 | uint32_t macl; /* multiply and accumulate low */ | |
160 | uint32_t pr; /* procedure register */ | |
161 | uint32_t fpscr; /* floating point status/control register */ | |
162 | uint32_t fpul; /* floating point communication register */ | |
163 | ||
17b086f7 | 164 | /* float point status register */ |
ea6cf6be | 165 | float_status fp_status; |
eda9b09b | 166 | |
fdf9b3e8 FB |
167 | /* Those belong to the specific unit (SH7750) but are handled here */ |
168 | uint32_t mmucr; /* MMU control register */ | |
169 | uint32_t pteh; /* page table entry high register */ | |
170 | uint32_t ptel; /* page table entry low register */ | |
171 | uint32_t ptea; /* page table entry assistance register */ | |
23b5d9fa | 172 | uint32_t ttb; /* translation table base register */ |
fdf9b3e8 FB |
173 | uint32_t tea; /* TLB exception address register */ |
174 | uint32_t tra; /* TRAPA exception register */ | |
175 | uint32_t expevt; /* exception event register */ | |
176 | uint32_t intevt; /* interrupt event register */ | |
177 | ||
4f6493ff AJ |
178 | tlb_t itlb[ITLB_SIZE]; /* instruction translation table */ |
179 | tlb_t utlb[UTLB_SIZE]; /* unified translation table */ | |
180 | ||
f85da308 RH |
181 | /* LDST = LOCK_ADDR != -1. */ |
182 | uint32_t lock_addr; | |
183 | uint32_t lock_value; | |
4f6493ff | 184 | |
1f5c00cf AB |
185 | /* Fields up to this point are cleared by a CPU reset */ |
186 | struct {} end_reset_fields; | |
187 | ||
f0c3c505 | 188 | /* Fields from here on are preserved over CPU reset. */ |
4f6493ff | 189 | int id; /* CPU model */ |
0fd3ca30 | 190 | |
21c04611 BB |
191 | /* The features that we should emulate. See sh_features above. */ |
192 | uint32_t features; | |
193 | ||
e96e2044 | 194 | void *intc_handle; |
efac4154 | 195 | int in_sleep; /* SR_BL ignored during sleep */ |
852d481f EI |
196 | memory_content *movcal_backup; |
197 | memory_content **movcal_backup_tail; | |
fdf9b3e8 FB |
198 | } CPUSH4State; |
199 | ||
e6005f66 PB |
200 | /** |
201 | * SuperHCPU: | |
202 | * @env: #CPUSH4State | |
203 | * | |
204 | * A SuperH CPU. | |
205 | */ | |
b36e239e | 206 | struct ArchCPU { |
e6005f66 PB |
207 | /*< private >*/ |
208 | CPUState parent_obj; | |
209 | /*< public >*/ | |
210 | ||
211 | CPUSH4State env; | |
212 | }; | |
213 | ||
e6005f66 | 214 | |
90c84c56 | 215 | void superh_cpu_dump_state(CPUState *cpu, FILE *f, int flags); |
a010bdbe | 216 | int superh_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); |
e6005f66 | 217 | int superh_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); |
8905770b MAL |
218 | G_NORETURN void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, |
219 | MMUAccessType access_type, int mmu_idx, | |
220 | uintptr_t retaddr); | |
339894be | 221 | |
aa7408ec | 222 | void sh4_translate_init(void); |
cac720ec RH |
223 | void sh4_cpu_list(void); |
224 | ||
225 | #if !defined(CONFIG_USER_ONLY) | |
6d2d454a | 226 | hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); |
f98bce2b RH |
227 | bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
228 | MMUAccessType access_type, int mmu_idx, | |
229 | bool probe, uintptr_t retaddr); | |
73166ca3 PMD |
230 | void superh_cpu_do_interrupt(CPUState *cpu); |
231 | bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req); | |
e0bcb9ca | 232 | void cpu_sh4_invalidate_tlb(CPUSH4State *s); |
bc656a29 | 233 | uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s, |
a8170e5e AK |
234 | hwaddr addr); |
235 | void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr, | |
9f97309a | 236 | uint32_t mem_value); |
bc656a29 | 237 | uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s, |
a8170e5e AK |
238 | hwaddr addr); |
239 | void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr, | |
9f97309a | 240 | uint32_t mem_value); |
bc656a29 | 241 | uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s, |
a8170e5e AK |
242 | hwaddr addr); |
243 | void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr, | |
9f97309a | 244 | uint32_t mem_value); |
bc656a29 | 245 | uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s, |
a8170e5e AK |
246 | hwaddr addr); |
247 | void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr, | |
9f97309a | 248 | uint32_t mem_value); |
3c7b48b7 | 249 | #endif |
fdf9b3e8 | 250 | |
852d481f EI |
251 | int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr); |
252 | ||
ef7ec1c1 AJ |
253 | void cpu_load_tlb(CPUSH4State * env); |
254 | ||
974e58d2 IM |
255 | #define SUPERH_CPU_TYPE_SUFFIX "-" TYPE_SUPERH_CPU |
256 | #define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX | |
0dacec87 | 257 | #define CPU_RESOLVING_TYPE TYPE_SUPERH_CPU |
974e58d2 | 258 | |
0fd3ca30 | 259 | #define cpu_list sh4_cpu_list |
9467d44c | 260 | |
6ebbf390 | 261 | /* MMU modes definitions */ |
6ebbf390 | 262 | #define MMU_USER_IDX 1 |
97ed5ccd | 263 | static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch) |
6ebbf390 | 264 | { |
be53081a AJ |
265 | /* The instruction in a RTE delay slot is fetched in privileged |
266 | mode, but executed in user mode. */ | |
ab419fd8 | 267 | if (ifetch && (env->flags & TB_FLAG_DELAY_SLOT_RTE)) { |
be53081a AJ |
268 | return 0; |
269 | } else { | |
270 | return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0; | |
271 | } | |
6ebbf390 JM |
272 | } |
273 | ||
022c62cb | 274 | #include "exec/cpu-all.h" |
fdf9b3e8 | 275 | |
fdf9b3e8 FB |
276 | /* MMU control register */ |
277 | #define MMUCR 0x1F000010 | |
278 | #define MMUCR_AT (1<<0) | |
e0bcb9ca | 279 | #define MMUCR_TI (1<<2) |
fdf9b3e8 | 280 | #define MMUCR_SV (1<<8) |
ea2b542a AJ |
281 | #define MMUCR_URC_BITS (6) |
282 | #define MMUCR_URC_OFFSET (10) | |
283 | #define MMUCR_URC_SIZE (1 << MMUCR_URC_BITS) | |
284 | #define MMUCR_URC_MASK (((MMUCR_URC_SIZE) - 1) << MMUCR_URC_OFFSET) | |
285 | static inline int cpu_mmucr_urc (uint32_t mmucr) | |
286 | { | |
287 | return ((mmucr & MMUCR_URC_MASK) >> MMUCR_URC_OFFSET); | |
288 | } | |
289 | ||
290 | /* PTEH : Page Translation Entry High register */ | |
291 | #define PTEH_ASID_BITS (8) | |
292 | #define PTEH_ASID_SIZE (1 << PTEH_ASID_BITS) | |
293 | #define PTEH_ASID_MASK (PTEH_ASID_SIZE - 1) | |
294 | #define cpu_pteh_asid(pteh) ((pteh) & PTEH_ASID_MASK) | |
295 | #define PTEH_VPN_BITS (22) | |
296 | #define PTEH_VPN_OFFSET (10) | |
297 | #define PTEH_VPN_SIZE (1 << PTEH_VPN_BITS) | |
298 | #define PTEH_VPN_MASK (((PTEH_VPN_SIZE) - 1) << PTEH_VPN_OFFSET) | |
299 | static inline int cpu_pteh_vpn (uint32_t pteh) | |
300 | { | |
301 | return ((pteh & PTEH_VPN_MASK) >> PTEH_VPN_OFFSET); | |
302 | } | |
303 | ||
304 | /* PTEL : Page Translation Entry Low register */ | |
305 | #define PTEL_V (1 << 8) | |
306 | #define cpu_ptel_v(ptel) (((ptel) & PTEL_V) >> 8) | |
307 | #define PTEL_C (1 << 3) | |
308 | #define cpu_ptel_c(ptel) (((ptel) & PTEL_C) >> 3) | |
309 | #define PTEL_D (1 << 2) | |
310 | #define cpu_ptel_d(ptel) (((ptel) & PTEL_D) >> 2) | |
311 | #define PTEL_SH (1 << 1) | |
312 | #define cpu_ptel_sh(ptel)(((ptel) & PTEL_SH) >> 1) | |
313 | #define PTEL_WT (1 << 0) | |
314 | #define cpu_ptel_wt(ptel) ((ptel) & PTEL_WT) | |
315 | ||
316 | #define PTEL_SZ_HIGH_OFFSET (7) | |
317 | #define PTEL_SZ_HIGH (1 << PTEL_SZ_HIGH_OFFSET) | |
318 | #define PTEL_SZ_LOW_OFFSET (4) | |
319 | #define PTEL_SZ_LOW (1 << PTEL_SZ_LOW_OFFSET) | |
320 | static inline int cpu_ptel_sz (uint32_t ptel) | |
321 | { | |
322 | int sz; | |
323 | sz = (ptel & PTEL_SZ_HIGH) >> PTEL_SZ_HIGH_OFFSET; | |
324 | sz <<= 1; | |
325 | sz |= (ptel & PTEL_SZ_LOW) >> PTEL_SZ_LOW_OFFSET; | |
326 | return sz; | |
327 | } | |
328 | ||
329 | #define PTEL_PPN_BITS (19) | |
330 | #define PTEL_PPN_OFFSET (10) | |
331 | #define PTEL_PPN_SIZE (1 << PTEL_PPN_BITS) | |
332 | #define PTEL_PPN_MASK (((PTEL_PPN_SIZE) - 1) << PTEL_PPN_OFFSET) | |
333 | static inline int cpu_ptel_ppn (uint32_t ptel) | |
334 | { | |
335 | return ((ptel & PTEL_PPN_MASK) >> PTEL_PPN_OFFSET); | |
336 | } | |
337 | ||
338 | #define PTEL_PR_BITS (2) | |
339 | #define PTEL_PR_OFFSET (5) | |
340 | #define PTEL_PR_SIZE (1 << PTEL_PR_BITS) | |
341 | #define PTEL_PR_MASK (((PTEL_PR_SIZE) - 1) << PTEL_PR_OFFSET) | |
342 | static inline int cpu_ptel_pr (uint32_t ptel) | |
343 | { | |
344 | return ((ptel & PTEL_PR_MASK) >> PTEL_PR_OFFSET); | |
345 | } | |
346 | ||
347 | /* PTEA : Page Translation Entry Assistance register */ | |
348 | #define PTEA_SA_BITS (3) | |
349 | #define PTEA_SA_SIZE (1 << PTEA_SA_BITS) | |
350 | #define PTEA_SA_MASK (PTEA_SA_SIZE - 1) | |
351 | #define cpu_ptea_sa(ptea) ((ptea) & PTEA_SA_MASK) | |
352 | #define PTEA_TC (1 << 3) | |
353 | #define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3) | |
fdf9b3e8 | 354 | |
34086945 AJ |
355 | static inline target_ulong cpu_read_sr(CPUSH4State *env) |
356 | { | |
1d565b21 AJ |
357 | return env->sr | (env->sr_m << SR_M) | |
358 | (env->sr_q << SR_Q) | | |
359 | (env->sr_t << SR_T); | |
34086945 AJ |
360 | } |
361 | ||
362 | static inline void cpu_write_sr(CPUSH4State *env, target_ulong sr) | |
363 | { | |
1d565b21 AJ |
364 | env->sr_m = (sr >> SR_M) & 1; |
365 | env->sr_q = (sr >> SR_Q) & 1; | |
366 | env->sr_t = (sr >> SR_T) & 1; | |
367 | env->sr = sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T)); | |
34086945 AJ |
368 | } |
369 | ||
bb5de525 AJ |
370 | static inline void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc, |
371 | uint64_t *cs_base, uint32_t *flags) | |
6b917547 AL |
372 | { |
373 | *pc = env->pc; | |
4bfa602b | 374 | /* For a gUSA region, notice the end of the region. */ |
ab419fd8 RH |
375 | *cs_base = env->flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0; |
376 | *flags = env->flags | |
377 | | (env->fpscr & TB_FLAG_FPSCR_MASK) | |
378 | | (env->sr & TB_FLAG_SR_MASK) | |
1516184d | 379 | | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */ |
4da06fb3 RH |
380 | #ifdef CONFIG_USER_ONLY |
381 | *flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; | |
382 | #endif | |
6b917547 AL |
383 | } |
384 | ||
07f5a258 | 385 | #endif /* SH4_CPU_H */ |