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target-sparc: implement UA2005 GL register
[mirror_qemu.git] / target / sparc / translate.c
CommitLineData
7a3f1944
FB		 1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
3475187d 5 Copyright (C) 2003-2005 Fabrice Bellard
7a3f1944
FB		 6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
8167ee88 18 License along with this library; if not, see <http://www.gnu.org/licenses/>.
7a3f1944
FB		 19 */
20
db5ebe5f 21#include "qemu/osdep.h"
7a3f1944
FB		 22
23#include "cpu.h"
76cad711 24#include "disas/disas.h"
2ef6175a 25#include "exec/helper-proto.h"
63c91552 26#include "exec/exec-all.h"
57fec1fe 27#include "tcg-op.h"
f08b6170 28#include "exec/cpu_ldst.h"
7a3f1944 29
2ef6175a 30#include "exec/helper-gen.h"
a7812ae4 31
a7e30d84 32#include "trace-tcg.h"
508127e2 33#include "exec/log.h"
0cc1f4bf 34#include "asi.h"
a7e30d84
LV		 35
36
7a3f1944
FB		 37#define DEBUG_DISAS
38
72cbca10
FB		 39#define DYNAMIC_PC 1 /* dynamic pc value */
40#define JUMP_PC 2 /* dynamic pc value which takes only two values
41 according to jump_pc[T2] */
42
1a2fb1c0 43/* global register indexes */
1bcea73e
LV		 44static TCGv_env cpu_env;
45static TCGv_ptr cpu_regwptr;
25517f99
PB		 46static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
47static TCGv_i32 cpu_cc_op;
a7812ae4 48static TCGv_i32 cpu_psr;
d2dc4069
RH		 49static TCGv cpu_fsr, cpu_pc, cpu_npc;
50static TCGv cpu_regs[32];
255e1fcb
BS		 51static TCGv cpu_y;
52#ifndef CONFIG_USER_ONLY
53static TCGv cpu_tbr;
54#endif
5793f2a4 55static TCGv cpu_cond;
dc99a3f2 56#ifdef TARGET_SPARC64
a6d567e5 57static TCGv_i32 cpu_xcc, cpu_fprs;
a7812ae4 58static TCGv cpu_gsr;
255e1fcb 59static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr;
a7812ae4 60static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver;
255e1fcb
BS		 61#else
62static TCGv cpu_wim;
dc99a3f2 63#endif
714547bb 64/* Floating point registers */
30038fd8 65static TCGv_i64 cpu_fpr[TARGET_DPREGS];
1a2fb1c0 66
022c62cb 67#include "exec/gen-icount.h"
2e70f6ef 68
7a3f1944 69typedef struct DisasContext {
0f8a249a
BS		 70 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
71 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
72cbca10 72 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
cf495bcf 73 int is_br;
e8af50a3 74 int mem_idx;
c9b459aa
AT		 75 bool fpu_enabled;
76 bool address_mask_32bit;
77 bool singlestep;
78#ifndef CONFIG_USER_ONLY
79 bool supervisor;
80#ifdef TARGET_SPARC64
81 bool hypervisor;
82#endif
83#endif
84
8393617c 85 uint32_t cc_op; /* current CC operation */
cf495bcf 86 struct TranslationBlock *tb;
5578ceab 87 sparc_def_t *def;
30038fd8 88 TCGv_i32 t32[3];
88023616 89 TCGv ttl[5];
30038fd8 90 int n_t32;
88023616 91 int n_ttl;
a6d567e5 92#ifdef TARGET_SPARC64
f9c816c0 93 int fprs_dirty;
a6d567e5
RH		 94 int asi;
95#endif
7a3f1944
FB		 96} DisasContext;
97
416fcaea
RH		 98typedef struct {
99 TCGCond cond;
100 bool is_bool;
101 bool g1, g2;
102 TCGv c1, c2;
103} DisasCompare;
104
3475187d 105// This function uses non-native bit order
dc1a6971
BS		 106#define GET_FIELD(X, FROM, TO) \
107 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
7a3f1944 108
3475187d 109// This function uses the order in the manuals, i.e. bit 0 is 2^0
dc1a6971 110#define GET_FIELD_SP(X, FROM, TO) \
3475187d
FB		 111 GET_FIELD(X, 31 - (TO), 31 - (FROM))
112
113#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
46d38ba8 114#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
3475187d
FB		 115
116#ifdef TARGET_SPARC64
0387d928 117#define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
1f587329 118#define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
3475187d 119#else
c185970a 120#define DFPREG(r) (r & 0x1e)
1f587329 121#define QFPREG(r) (r & 0x1c)
3475187d
FB		 122#endif
123
b158a785
BS		 124#define UA2005_HTRAP_MASK 0xff
125#define V8_TRAP_MASK 0x7f
126
3475187d
FB		 127static int sign_extend(int x, int len)
128{
129 len = 32 - len;
130 return (x << len) >> len;
131}
132
7a3f1944
FB		 133#define IS_IMM (insn & (1<<13))
134
2ae23e17
RH		 135static inline TCGv_i32 get_temp_i32(DisasContext *dc)
136{
137 TCGv_i32 t;
138 assert(dc->n_t32 < ARRAY_SIZE(dc->t32));
139 dc->t32[dc->n_t32++] = t = tcg_temp_new_i32();
140 return t;
141}
142
143static inline TCGv get_temp_tl(DisasContext *dc)
144{
145 TCGv t;
146 assert(dc->n_ttl < ARRAY_SIZE(dc->ttl));
147 dc->ttl[dc->n_ttl++] = t = tcg_temp_new();
148 return t;
149}
150
f9c816c0 151static inline void gen_update_fprs_dirty(DisasContext *dc, int rd)
141ae5c1
RH		 152{
153#if defined(TARGET_SPARC64)
f9c816c0
RH		 154 int bit = (rd < 32) ? 1 : 2;
155 /* If we know we've already set this bit within the TB,
156 we can avoid setting it again. */
157 if (!(dc->fprs_dirty & bit)) {
158 dc->fprs_dirty |= bit;
159 tcg_gen_ori_i32(cpu_fprs, cpu_fprs, bit);
160 }
141ae5c1
RH		 161#endif
162}
163
ff07ec83 164/* floating point registers moves */
208ae657
RH		 165static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src)
166{
30038fd8
RH		 167#if TCG_TARGET_REG_BITS == 32
168 if (src & 1) {
169 return TCGV_LOW(cpu_fpr[src / 2]);
170 } else {
171 return TCGV_HIGH(cpu_fpr[src / 2]);
172 }
173#else
174 if (src & 1) {
175 return MAKE_TCGV_I32(GET_TCGV_I64(cpu_fpr[src / 2]));
176 } else {
2ae23e17 177 TCGv_i32 ret = get_temp_i32(dc);
30038fd8
RH		 178 TCGv_i64 t = tcg_temp_new_i64();
179
180 tcg_gen_shri_i64(t, cpu_fpr[src / 2], 32);
ecc7b3aa 181 tcg_gen_extrl_i64_i32(ret, t);
30038fd8
RH		 182 tcg_temp_free_i64(t);
183
30038fd8
RH		 184 return ret;
185 }
186#endif
208ae657
RH		 187}
188
189static void gen_store_fpr_F(DisasContext *dc, unsigned int dst, TCGv_i32 v)
190{
30038fd8
RH		 191#if TCG_TARGET_REG_BITS == 32
192 if (dst & 1) {
193 tcg_gen_mov_i32(TCGV_LOW(cpu_fpr[dst / 2]), v);
194 } else {
195 tcg_gen_mov_i32(TCGV_HIGH(cpu_fpr[dst / 2]), v);
196 }
197#else
198 TCGv_i64 t = MAKE_TCGV_I64(GET_TCGV_I32(v));
199 tcg_gen_deposit_i64(cpu_fpr[dst / 2], cpu_fpr[dst / 2], t,
200 (dst & 1 ? 0 : 32), 32);
201#endif
f9c816c0 202 gen_update_fprs_dirty(dc, dst);
208ae657
RH		 203}
204
ba5f5179 205static TCGv_i32 gen_dest_fpr_F(DisasContext *dc)
208ae657 206{
ba5f5179 207 return get_temp_i32(dc);
208ae657
RH		 208}
209
96eda024
RH		 210static TCGv_i64 gen_load_fpr_D(DisasContext *dc, unsigned int src)
211{
96eda024 212 src = DFPREG(src);
30038fd8 213 return cpu_fpr[src / 2];
96eda024
RH		 214}
215
216static void gen_store_fpr_D(DisasContext *dc, unsigned int dst, TCGv_i64 v)
217{
218 dst = DFPREG(dst);
30038fd8 219 tcg_gen_mov_i64(cpu_fpr[dst / 2], v);
f9c816c0 220 gen_update_fprs_dirty(dc, dst);
96eda024
RH		 221}
222
3886b8a3 223static TCGv_i64 gen_dest_fpr_D(DisasContext *dc, unsigned int dst)
96eda024 224{
3886b8a3 225 return cpu_fpr[DFPREG(dst) / 2];
96eda024
RH		 226}
227
ff07ec83
BS		 228static void gen_op_load_fpr_QT0(unsigned int src)
229{
30038fd8
RH		 230 tcg_gen_st_i64(cpu_fpr[src / 2], cpu_env, offsetof(CPUSPARCState, qt0) +
231 offsetof(CPU_QuadU, ll.upper));
232 tcg_gen_st_i64(cpu_fpr[src/2 + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
233 offsetof(CPU_QuadU, ll.lower));
ff07ec83
BS		 234}
235
236static void gen_op_load_fpr_QT1(unsigned int src)
237{
30038fd8
RH		 238 tcg_gen_st_i64(cpu_fpr[src / 2], cpu_env, offsetof(CPUSPARCState, qt1) +
239 offsetof(CPU_QuadU, ll.upper));
240 tcg_gen_st_i64(cpu_fpr[src/2 + 1], cpu_env, offsetof(CPUSPARCState, qt1) +
241 offsetof(CPU_QuadU, ll.lower));
ff07ec83
BS		 242}
243
244static void gen_op_store_QT0_fpr(unsigned int dst)
245{
30038fd8
RH		 246 tcg_gen_ld_i64(cpu_fpr[dst / 2], cpu_env, offsetof(CPUSPARCState, qt0) +
247 offsetof(CPU_QuadU, ll.upper));
248 tcg_gen_ld_i64(cpu_fpr[dst/2 + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
249 offsetof(CPU_QuadU, ll.lower));
ff07ec83 250}
1f587329 251
f939ffe5
RH		 252static void gen_store_fpr_Q(DisasContext *dc, unsigned int dst,
253 TCGv_i64 v1, TCGv_i64 v2)
254{
255 dst = QFPREG(dst);
256
257 tcg_gen_mov_i64(cpu_fpr[dst / 2], v1);
258 tcg_gen_mov_i64(cpu_fpr[dst / 2 + 1], v2);
259 gen_update_fprs_dirty(dc, dst);
260}
261
ac11f776 262#ifdef TARGET_SPARC64
f939ffe5
RH		 263static TCGv_i64 gen_load_fpr_Q0(DisasContext *dc, unsigned int src)
264{
265 src = QFPREG(src);
266 return cpu_fpr[src / 2];
267}
268
269static TCGv_i64 gen_load_fpr_Q1(DisasContext *dc, unsigned int src)
270{
271 src = QFPREG(src);
272 return cpu_fpr[src / 2 + 1];
273}
274
f9c816c0 275static void gen_move_Q(DisasContext *dc, unsigned int rd, unsigned int rs)
ac11f776
RH		 276{
277 rd = QFPREG(rd);
278 rs = QFPREG(rs);
279
30038fd8
RH		 280 tcg_gen_mov_i64(cpu_fpr[rd / 2], cpu_fpr[rs / 2]);
281 tcg_gen_mov_i64(cpu_fpr[rd / 2 + 1], cpu_fpr[rs / 2 + 1]);
f9c816c0 282 gen_update_fprs_dirty(dc, rd);
ac11f776
RH		 283}
284#endif
285
81ad8ba2
BS		 286/* moves */
287#ifdef CONFIG_USER_ONLY
3475187d 288#define supervisor(dc) 0
81ad8ba2 289#ifdef TARGET_SPARC64
e9ebed4d 290#define hypervisor(dc) 0
81ad8ba2 291#endif
3475187d 292#else
81ad8ba2 293#ifdef TARGET_SPARC64
c9b459aa
AT		 294#define hypervisor(dc) (dc->hypervisor)
295#define supervisor(dc) (dc->supervisor | dc->hypervisor)
6f27aba6 296#else
c9b459aa 297#define supervisor(dc) (dc->supervisor)
3475187d 298#endif
81ad8ba2
BS		 299#endif
300
2cade6a3
BS		 301#ifdef TARGET_SPARC64
302#ifndef TARGET_ABI32
303#define AM_CHECK(dc) ((dc)->address_mask_32bit)
1a2fb1c0 304#else
2cade6a3
BS		 305#define AM_CHECK(dc) (1)
306#endif
1a2fb1c0 307#endif
3391c818 308
2cade6a3
BS		 309static inline void gen_address_mask(DisasContext *dc, TCGv addr)
310{
311#ifdef TARGET_SPARC64
312 if (AM_CHECK(dc))
313 tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
314#endif
315}
316
88023616
RH		 317static inline TCGv gen_load_gpr(DisasContext *dc, int reg)
318{
d2dc4069
RH		 319 if (reg > 0) {
320 assert(reg < 32);
321 return cpu_regs[reg];
322 } else {
88023616 323 TCGv t = get_temp_tl(dc);
d2dc4069 324 tcg_gen_movi_tl(t, 0);
88023616 325 return t;
88023616
RH		 326 }
327}
328
329static inline void gen_store_gpr(DisasContext *dc, int reg, TCGv v)
330{
331 if (reg > 0) {
d2dc4069
RH		 332 assert(reg < 32);
333 tcg_gen_mov_tl(cpu_regs[reg], v);
88023616
RH		 334 }
335}
336
337static inline TCGv gen_dest_gpr(DisasContext *dc, int reg)
338{
d2dc4069
RH		 339 if (reg > 0) {
340 assert(reg < 32);
341 return cpu_regs[reg];
88023616 342 } else {
d2dc4069 343 return get_temp_tl(dc);
88023616
RH		 344 }
345}
346
90aa39a1
SF		 347static inline bool use_goto_tb(DisasContext *s, target_ulong pc,
348 target_ulong npc)
349{
350 if (unlikely(s->singlestep)) {
351 return false;
352 }
353
354#ifndef CONFIG_USER_ONLY
355 return (pc & TARGET_PAGE_MASK) == (s->tb->pc & TARGET_PAGE_MASK) &&
356 (npc & TARGET_PAGE_MASK) == (s->tb->pc & TARGET_PAGE_MASK);
357#else
358 return true;
359#endif
360}
361
5fafdf24 362static inline void gen_goto_tb(DisasContext *s, int tb_num,
6e256c93
FB		 363 target_ulong pc, target_ulong npc)
364{
90aa39a1 365 if (use_goto_tb(s, pc, npc)) {
6e256c93 366 /* jump to same page: we can use a direct jump */
57fec1fe 367 tcg_gen_goto_tb(tb_num);
2f5680ee
BS		 368 tcg_gen_movi_tl(cpu_pc, pc);
369 tcg_gen_movi_tl(cpu_npc, npc);
90aa39a1 370 tcg_gen_exit_tb((uintptr_t)s->tb + tb_num);
6e256c93
FB		 371 } else {
372 /* jump to another page: currently not optimized */
2f5680ee
BS		 373 tcg_gen_movi_tl(cpu_pc, pc);
374 tcg_gen_movi_tl(cpu_npc, npc);
57fec1fe 375 tcg_gen_exit_tb(0);
6e256c93
FB		 376 }
377}
378
19f329ad 379// XXX suboptimal
a7812ae4 380static inline void gen_mov_reg_N(TCGv reg, TCGv_i32 src)
19f329ad 381{
8911f501 382 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 383 tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);
19f329ad
BS		 384 tcg_gen_andi_tl(reg, reg, 0x1);
385}
386
a7812ae4 387static inline void gen_mov_reg_Z(TCGv reg, TCGv_i32 src)
19f329ad 388{
8911f501 389 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 390 tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);
19f329ad
BS		 391 tcg_gen_andi_tl(reg, reg, 0x1);
392}
393
a7812ae4 394static inline void gen_mov_reg_V(TCGv reg, TCGv_i32 src)
19f329ad 395{
8911f501 396 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 397 tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);
19f329ad
BS		 398 tcg_gen_andi_tl(reg, reg, 0x1);
399}
400
a7812ae4 401static inline void gen_mov_reg_C(TCGv reg, TCGv_i32 src)
19f329ad 402{
8911f501 403 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 404 tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);
19f329ad
BS		 405 tcg_gen_andi_tl(reg, reg, 0x1);
406}
407
4af984a7 408static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 409{
4af984a7 410 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 411 tcg_gen_mov_tl(cpu_cc_src2, src2);
5c6a0628 412 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
bdf9f35d 413 tcg_gen_mov_tl(dst, cpu_cc_dst);
41d72852
BS		 414}
415
70c48285 416static TCGv_i32 gen_add32_carry32(void)
dc99a3f2 417{
70c48285
RH		 418 TCGv_i32 carry_32, cc_src1_32, cc_src2_32;
419
420 /* Carry is computed from a previous add: (dst < src) */
421#if TARGET_LONG_BITS == 64
422 cc_src1_32 = tcg_temp_new_i32();
423 cc_src2_32 = tcg_temp_new_i32();
ecc7b3aa
RH		 424 tcg_gen_extrl_i64_i32(cc_src1_32, cpu_cc_dst);
425 tcg_gen_extrl_i64_i32(cc_src2_32, cpu_cc_src);
70c48285
RH		 426#else
427 cc_src1_32 = cpu_cc_dst;
428 cc_src2_32 = cpu_cc_src;
429#endif
430
431 carry_32 = tcg_temp_new_i32();
432 tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);
433
434#if TARGET_LONG_BITS == 64
435 tcg_temp_free_i32(cc_src1_32);
436 tcg_temp_free_i32(cc_src2_32);
437#endif
438
439 return carry_32;
41d72852
BS		 440}
441
70c48285 442static TCGv_i32 gen_sub32_carry32(void)
41d72852 443{
70c48285
RH		 444 TCGv_i32 carry_32, cc_src1_32, cc_src2_32;
445
446 /* Carry is computed from a previous borrow: (src1 < src2) */
447#if TARGET_LONG_BITS == 64
448 cc_src1_32 = tcg_temp_new_i32();
449 cc_src2_32 = tcg_temp_new_i32();
ecc7b3aa
RH		 450 tcg_gen_extrl_i64_i32(cc_src1_32, cpu_cc_src);
451 tcg_gen_extrl_i64_i32(cc_src2_32, cpu_cc_src2);
70c48285
RH		 452#else
453 cc_src1_32 = cpu_cc_src;
454 cc_src2_32 = cpu_cc_src2;
455#endif
456
457 carry_32 = tcg_temp_new_i32();
458 tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);
459
460#if TARGET_LONG_BITS == 64
461 tcg_temp_free_i32(cc_src1_32);
462 tcg_temp_free_i32(cc_src2_32);
463#endif
464
465 return carry_32;
466}
467
468static void gen_op_addx_int(DisasContext *dc, TCGv dst, TCGv src1,
469 TCGv src2, int update_cc)
470{
471 TCGv_i32 carry_32;
472 TCGv carry;
473
474 switch (dc->cc_op) {
475 case CC_OP_DIV:
476 case CC_OP_LOGIC:
477 /* Carry is known to be zero. Fall back to plain ADD. */
478 if (update_cc) {
479 gen_op_add_cc(dst, src1, src2);
480 } else {
481 tcg_gen_add_tl(dst, src1, src2);
482 }
483 return;
484
485 case CC_OP_ADD:
486 case CC_OP_TADD:
487 case CC_OP_TADDTV:
15fe216f
RH		 488 if (TARGET_LONG_BITS == 32) {
489 /* We can re-use the host's hardware carry generation by using
490 an ADD2 opcode. We discard the low part of the output.
491 Ideally we'd combine this operation with the add that
492 generated the carry in the first place. */
493 carry = tcg_temp_new();
494 tcg_gen_add2_tl(carry, dst, cpu_cc_src, src1, cpu_cc_src2, src2);
495 tcg_temp_free(carry);
70c48285
RH		 496 goto add_done;
497 }
70c48285
RH		 498 carry_32 = gen_add32_carry32();
499 break;
500
501 case CC_OP_SUB:
502 case CC_OP_TSUB:
503 case CC_OP_TSUBTV:
504 carry_32 = gen_sub32_carry32();
505 break;
506
507 default:
508 /* We need external help to produce the carry. */
509 carry_32 = tcg_temp_new_i32();
2ffd9176 510 gen_helper_compute_C_icc(carry_32, cpu_env);
70c48285
RH		 511 break;
512 }
513
514#if TARGET_LONG_BITS == 64
515 carry = tcg_temp_new();
516 tcg_gen_extu_i32_i64(carry, carry_32);
517#else
518 carry = carry_32;
519#endif
520
521 tcg_gen_add_tl(dst, src1, src2);
522 tcg_gen_add_tl(dst, dst, carry);
523
524 tcg_temp_free_i32(carry_32);
525#if TARGET_LONG_BITS == 64
526 tcg_temp_free(carry);
527#endif
528
70c48285 529 add_done:
70c48285
RH		 530 if (update_cc) {
531 tcg_gen_mov_tl(cpu_cc_src, src1);
532 tcg_gen_mov_tl(cpu_cc_src2, src2);
533 tcg_gen_mov_tl(cpu_cc_dst, dst);
534 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADDX);
535 dc->cc_op = CC_OP_ADDX;
536 }
dc99a3f2
BS		 537}
538
41d72852 539static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 540{
4af984a7 541 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 542 tcg_gen_mov_tl(cpu_cc_src2, src2);
41d72852 543 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
d4b0d468 544 tcg_gen_mov_tl(dst, cpu_cc_dst);
41d72852
BS		 545}
546
70c48285
RH		 547static void gen_op_subx_int(DisasContext *dc, TCGv dst, TCGv src1,
548 TCGv src2, int update_cc)
41d72852 549{
70c48285
RH		 550 TCGv_i32 carry_32;
551 TCGv carry;
41d72852 552
70c48285
RH		 553 switch (dc->cc_op) {
554 case CC_OP_DIV:
555 case CC_OP_LOGIC:
556 /* Carry is known to be zero. Fall back to plain SUB. */
557 if (update_cc) {
558 gen_op_sub_cc(dst, src1, src2);
559 } else {
560 tcg_gen_sub_tl(dst, src1, src2);
561 }
562 return;
563
564 case CC_OP_ADD:
565 case CC_OP_TADD:
566 case CC_OP_TADDTV:
567 carry_32 = gen_add32_carry32();
568 break;
569
570 case CC_OP_SUB:
571 case CC_OP_TSUB:
572 case CC_OP_TSUBTV:
15fe216f
RH		 573 if (TARGET_LONG_BITS == 32) {
574 /* We can re-use the host's hardware carry generation by using
575 a SUB2 opcode. We discard the low part of the output.
576 Ideally we'd combine this operation with the add that
577 generated the carry in the first place. */
578 carry = tcg_temp_new();
579 tcg_gen_sub2_tl(carry, dst, cpu_cc_src, src1, cpu_cc_src2, src2);
580 tcg_temp_free(carry);
70c48285
RH		 581 goto sub_done;
582 }
70c48285
RH		 583 carry_32 = gen_sub32_carry32();
584 break;
585
586 default:
587 /* We need external help to produce the carry. */
588 carry_32 = tcg_temp_new_i32();
2ffd9176 589 gen_helper_compute_C_icc(carry_32, cpu_env);
70c48285
RH		 590 break;
591 }
592
593#if TARGET_LONG_BITS == 64
594 carry = tcg_temp_new();
595 tcg_gen_extu_i32_i64(carry, carry_32);
596#else
597 carry = carry_32;
598#endif
599
600 tcg_gen_sub_tl(dst, src1, src2);
601 tcg_gen_sub_tl(dst, dst, carry);
602
603 tcg_temp_free_i32(carry_32);
604#if TARGET_LONG_BITS == 64
605 tcg_temp_free(carry);
606#endif
607
70c48285 608 sub_done:
70c48285
RH		 609 if (update_cc) {
610 tcg_gen_mov_tl(cpu_cc_src, src1);
611 tcg_gen_mov_tl(cpu_cc_src2, src2);
612 tcg_gen_mov_tl(cpu_cc_dst, dst);
613 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX);
614 dc->cc_op = CC_OP_SUBX;
615 }
dc99a3f2
BS		 616}
617
4af984a7 618static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
d9bdab86 619{
de9e9d9f 620 TCGv r_temp, zero, t0;
d9bdab86 621
a7812ae4 622 r_temp = tcg_temp_new();
de9e9d9f 623 t0 = tcg_temp_new();
d9bdab86
BS		 624
625 /* old op:
626 if (!(env->y & 1))
627 T1 = 0;
628 */
6cb675b0 629 zero = tcg_const_tl(0);
72ccba79 630 tcg_gen_andi_tl(cpu_cc_src, src1, 0xffffffff);
255e1fcb 631 tcg_gen_andi_tl(r_temp, cpu_y, 0x1);
72ccba79 632 tcg_gen_andi_tl(cpu_cc_src2, src2, 0xffffffff);
6cb675b0
RH		 633 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_cc_src2, r_temp, zero,
634 zero, cpu_cc_src2);
635 tcg_temp_free(zero);
d9bdab86
BS		 636
637 // b2 = T0 & 1;
638 // env->y = (b2 << 31) | (env->y >> 1);
105a1f04
BS		 639 tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);
640 tcg_gen_shli_tl(r_temp, r_temp, 31);
de9e9d9f
RH		 641 tcg_gen_shri_tl(t0, cpu_y, 1);
642 tcg_gen_andi_tl(t0, t0, 0x7fffffff);
643 tcg_gen_or_tl(t0, t0, r_temp);
644 tcg_gen_andi_tl(cpu_y, t0, 0xffffffff);
d9bdab86
BS		 645
646 // b1 = N ^ V;
de9e9d9f 647 gen_mov_reg_N(t0, cpu_psr);
d9bdab86 648 gen_mov_reg_V(r_temp, cpu_psr);
de9e9d9f 649 tcg_gen_xor_tl(t0, t0, r_temp);
2ea815ca 650 tcg_temp_free(r_temp);
d9bdab86
BS		 651
652 // T0 = (b1 << 31) | (T0 >> 1);
653 // src1 = T0;
de9e9d9f 654 tcg_gen_shli_tl(t0, t0, 31);
6f551262 655 tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
de9e9d9f
RH		 656 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
657 tcg_temp_free(t0);
d9bdab86 658
5c6a0628 659 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
d9bdab86 660
5c6a0628 661 tcg_gen_mov_tl(dst, cpu_cc_dst);
d9bdab86
BS		 662}
663
fb170183 664static inline void gen_op_multiply(TCGv dst, TCGv src1, TCGv src2, int sign_ext)
8879d139 665{
528692a8 666#if TARGET_LONG_BITS == 32
fb170183 667 if (sign_ext) {
528692a8 668 tcg_gen_muls2_tl(dst, cpu_y, src1, src2);
fb170183 669 } else {
528692a8 670 tcg_gen_mulu2_tl(dst, cpu_y, src1, src2);
fb170183 671 }
528692a8
RH		 672#else
673 TCGv t0 = tcg_temp_new_i64();
674 TCGv t1 = tcg_temp_new_i64();
fb170183 675
528692a8
RH		 676 if (sign_ext) {
677 tcg_gen_ext32s_i64(t0, src1);
678 tcg_gen_ext32s_i64(t1, src2);
679 } else {
680 tcg_gen_ext32u_i64(t0, src1);
681 tcg_gen_ext32u_i64(t1, src2);
682 }
fb170183 683
528692a8
RH		 684 tcg_gen_mul_i64(dst, t0, t1);
685 tcg_temp_free(t0);
686 tcg_temp_free(t1);
fb170183 687
528692a8
RH		 688 tcg_gen_shri_i64(cpu_y, dst, 32);
689#endif
8879d139
BS		 690}
691
fb170183 692static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
8879d139 693{
fb170183
IK		 694 /* zero-extend truncated operands before multiplication */
695 gen_op_multiply(dst, src1, src2, 0);
696}
8879d139 697
fb170183
IK		 698static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
699{
700 /* sign-extend truncated operands before multiplication */
701 gen_op_multiply(dst, src1, src2, 1);
8879d139
BS		 702}
703
19f329ad
BS		 704// 1
705static inline void gen_op_eval_ba(TCGv dst)
706{
707 tcg_gen_movi_tl(dst, 1);
708}
709
710// Z
a7812ae4 711static inline void gen_op_eval_be(TCGv dst, TCGv_i32 src)
19f329ad
BS		 712{
713 gen_mov_reg_Z(dst, src);
714}
715
716// Z | (N ^ V)
a7812ae4 717static inline void gen_op_eval_ble(TCGv dst, TCGv_i32 src)
19f329ad 718{
de9e9d9f
RH		 719 TCGv t0 = tcg_temp_new();
720 gen_mov_reg_N(t0, src);
19f329ad 721 gen_mov_reg_V(dst, src);
de9e9d9f
RH		 722 tcg_gen_xor_tl(dst, dst, t0);
723 gen_mov_reg_Z(t0, src);
724 tcg_gen_or_tl(dst, dst, t0);
725 tcg_temp_free(t0);
19f329ad
BS		 726}
727
728// N ^ V
a7812ae4 729static inline void gen_op_eval_bl(TCGv dst, TCGv_i32 src)
19f329ad 730{
de9e9d9f
RH		 731 TCGv t0 = tcg_temp_new();
732 gen_mov_reg_V(t0, src);
19f329ad 733 gen_mov_reg_N(dst, src);
de9e9d9f
RH		 734 tcg_gen_xor_tl(dst, dst, t0);
735 tcg_temp_free(t0);
19f329ad
BS		 736}
737
738// C | Z
a7812ae4 739static inline void gen_op_eval_bleu(TCGv dst, TCGv_i32 src)
19f329ad 740{
de9e9d9f
RH		 741 TCGv t0 = tcg_temp_new();
742 gen_mov_reg_Z(t0, src);
19f329ad 743 gen_mov_reg_C(dst, src);
de9e9d9f
RH		 744 tcg_gen_or_tl(dst, dst, t0);
745 tcg_temp_free(t0);
19f329ad
BS		 746}
747
748// C
a7812ae4 749static inline void gen_op_eval_bcs(TCGv dst, TCGv_i32 src)
19f329ad
BS		 750{
751 gen_mov_reg_C(dst, src);
752}
753
754// V
a7812ae4 755static inline void gen_op_eval_bvs(TCGv dst, TCGv_i32 src)
19f329ad
BS		 756{
757 gen_mov_reg_V(dst, src);
758}
759
760// 0
761static inline void gen_op_eval_bn(TCGv dst)
762{
763 tcg_gen_movi_tl(dst, 0);
764}
765
766// N
a7812ae4 767static inline void gen_op_eval_bneg(TCGv dst, TCGv_i32 src)
19f329ad
BS		 768{
769 gen_mov_reg_N(dst, src);
770}
771
772// !Z
a7812ae4 773static inline void gen_op_eval_bne(TCGv dst, TCGv_i32 src)
19f329ad
BS		 774{
775 gen_mov_reg_Z(dst, src);
776 tcg_gen_xori_tl(dst, dst, 0x1);
777}
778
779// !(Z | (N ^ V))
a7812ae4 780static inline void gen_op_eval_bg(TCGv dst, TCGv_i32 src)
19f329ad 781{
de9e9d9f 782 gen_op_eval_ble(dst, src);
19f329ad
BS		 783 tcg_gen_xori_tl(dst, dst, 0x1);
784}
785
786// !(N ^ V)
a7812ae4 787static inline void gen_op_eval_bge(TCGv dst, TCGv_i32 src)
19f329ad 788{
de9e9d9f 789 gen_op_eval_bl(dst, src);
19f329ad
BS		 790 tcg_gen_xori_tl(dst, dst, 0x1);
791}
792
793// !(C | Z)
a7812ae4 794static inline void gen_op_eval_bgu(TCGv dst, TCGv_i32 src)
19f329ad 795{
de9e9d9f 796 gen_op_eval_bleu(dst, src);
19f329ad
BS		 797 tcg_gen_xori_tl(dst, dst, 0x1);
798}
799
800// !C
a7812ae4 801static inline void gen_op_eval_bcc(TCGv dst, TCGv_i32 src)
19f329ad
BS		 802{
803 gen_mov_reg_C(dst, src);
804 tcg_gen_xori_tl(dst, dst, 0x1);
805}
806
807// !N
a7812ae4 808static inline void gen_op_eval_bpos(TCGv dst, TCGv_i32 src)
19f329ad
BS		 809{
810 gen_mov_reg_N(dst, src);
811 tcg_gen_xori_tl(dst, dst, 0x1);
812}
813
814// !V
a7812ae4 815static inline void gen_op_eval_bvc(TCGv dst, TCGv_i32 src)
19f329ad
BS		 816{
817 gen_mov_reg_V(dst, src);
818 tcg_gen_xori_tl(dst, dst, 0x1);
819}
820
821/*
822 FPSR bit field FCC1 | FCC0:
823 0 =
824 1 <
825 2 >
826 3 unordered
827*/
828static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
829 unsigned int fcc_offset)
830{
ba6a9d8c 831 tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset);
19f329ad
BS		 832 tcg_gen_andi_tl(reg, reg, 0x1);
833}
834
835static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
836 unsigned int fcc_offset)
837{
ba6a9d8c 838 tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset);
19f329ad
BS		 839 tcg_gen_andi_tl(reg, reg, 0x1);
840}
841
842// !0: FCC0 | FCC1
843static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
844 unsigned int fcc_offset)
845{
de9e9d9f 846 TCGv t0 = tcg_temp_new();
19f329ad 847 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 848 gen_mov_reg_FCC1(t0, src, fcc_offset);
849 tcg_gen_or_tl(dst, dst, t0);
850 tcg_temp_free(t0);
19f329ad
BS		 851}
852
853// 1 or 2: FCC0 ^ FCC1
854static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
855 unsigned int fcc_offset)
856{
de9e9d9f 857 TCGv t0 = tcg_temp_new();
19f329ad 858 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 859 gen_mov_reg_FCC1(t0, src, fcc_offset);
860 tcg_gen_xor_tl(dst, dst, t0);
861 tcg_temp_free(t0);
19f329ad
BS		 862}
863
864// 1 or 3: FCC0
865static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
866 unsigned int fcc_offset)
867{
868 gen_mov_reg_FCC0(dst, src, fcc_offset);
869}
870
871// 1: FCC0 & !FCC1
872static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
873 unsigned int fcc_offset)
874{
de9e9d9f 875 TCGv t0 = tcg_temp_new();
19f329ad 876 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 877 gen_mov_reg_FCC1(t0, src, fcc_offset);
878 tcg_gen_andc_tl(dst, dst, t0);
879 tcg_temp_free(t0);
19f329ad
BS		 880}
881
882// 2 or 3: FCC1
883static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
884 unsigned int fcc_offset)
885{
886 gen_mov_reg_FCC1(dst, src, fcc_offset);
887}
888
889// 2: !FCC0 & FCC1
890static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
891 unsigned int fcc_offset)
892{
de9e9d9f 893 TCGv t0 = tcg_temp_new();
19f329ad 894 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 895 gen_mov_reg_FCC1(t0, src, fcc_offset);
896 tcg_gen_andc_tl(dst, t0, dst);
897 tcg_temp_free(t0);
19f329ad
BS		 898}
899
900// 3: FCC0 & FCC1
901static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
902 unsigned int fcc_offset)
903{
de9e9d9f 904 TCGv t0 = tcg_temp_new();
19f329ad 905 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 906 gen_mov_reg_FCC1(t0, src, fcc_offset);
907 tcg_gen_and_tl(dst, dst, t0);
908 tcg_temp_free(t0);
19f329ad
BS		 909}
910
911// 0: !(FCC0 | FCC1)
912static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
913 unsigned int fcc_offset)
914{
de9e9d9f 915 TCGv t0 = tcg_temp_new();
19f329ad 916 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 917 gen_mov_reg_FCC1(t0, src, fcc_offset);
918 tcg_gen_or_tl(dst, dst, t0);
19f329ad 919 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 920 tcg_temp_free(t0);
19f329ad
BS		 921}
922
923// 0 or 3: !(FCC0 ^ FCC1)
924static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
925 unsigned int fcc_offset)
926{
de9e9d9f 927 TCGv t0 = tcg_temp_new();
19f329ad 928 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 929 gen_mov_reg_FCC1(t0, src, fcc_offset);
930 tcg_gen_xor_tl(dst, dst, t0);
19f329ad 931 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 932 tcg_temp_free(t0);
19f329ad
BS		 933}
934
935// 0 or 2: !FCC0
936static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
937 unsigned int fcc_offset)
938{
939 gen_mov_reg_FCC0(dst, src, fcc_offset);
940 tcg_gen_xori_tl(dst, dst, 0x1);
941}
942
943// !1: !(FCC0 & !FCC1)
944static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
945 unsigned int fcc_offset)
946{
de9e9d9f 947 TCGv t0 = tcg_temp_new();
19f329ad 948 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 949 gen_mov_reg_FCC1(t0, src, fcc_offset);
950 tcg_gen_andc_tl(dst, dst, t0);
19f329ad 951 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 952 tcg_temp_free(t0);
19f329ad
BS		 953}
954
955// 0 or 1: !FCC1
956static inline void gen_op_eval_fble(TCGv dst, TCGv src,
957 unsigned int fcc_offset)
958{
959 gen_mov_reg_FCC1(dst, src, fcc_offset);
960 tcg_gen_xori_tl(dst, dst, 0x1);
961}
962
963// !2: !(!FCC0 & FCC1)
964static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
965 unsigned int fcc_offset)
966{
de9e9d9f 967 TCGv t0 = tcg_temp_new();
19f329ad 968 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 969 gen_mov_reg_FCC1(t0, src, fcc_offset);
970 tcg_gen_andc_tl(dst, t0, dst);
19f329ad 971 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 972 tcg_temp_free(t0);
19f329ad
BS		 973}
974
975// !3: !(FCC0 & FCC1)
976static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
977 unsigned int fcc_offset)
978{
de9e9d9f 979 TCGv t0 = tcg_temp_new();
19f329ad 980 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 981 gen_mov_reg_FCC1(t0, src, fcc_offset);
982 tcg_gen_and_tl(dst, dst, t0);
19f329ad 983 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 984 tcg_temp_free(t0);
19f329ad
BS		 985}
986
46525e1f 987static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
19f329ad 988 target_ulong pc2, TCGv r_cond)
83469015 989{
42a268c2 990 TCGLabel *l1 = gen_new_label();
83469015 991
cb63669a 992 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
83469015 993
6e256c93 994 gen_goto_tb(dc, 0, pc1, pc1 + 4);
83469015
FB		 995
996 gen_set_label(l1);
6e256c93 997 gen_goto_tb(dc, 1, pc2, pc2 + 4);
83469015
FB		 998}
999
bfa31b76 1000static void gen_branch_a(DisasContext *dc, target_ulong pc1)
83469015 1001{
42a268c2 1002 TCGLabel *l1 = gen_new_label();
bfa31b76 1003 target_ulong npc = dc->npc;
83469015 1004
bfa31b76 1005 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cond, 0, l1);
83469015 1006
bfa31b76 1007 gen_goto_tb(dc, 0, npc, pc1);
83469015
FB		 1008
1009 gen_set_label(l1);
bfa31b76
RH		 1010 gen_goto_tb(dc, 1, npc + 4, npc + 8);
1011
1012 dc->is_br = 1;
83469015
FB		 1013}
1014
2bf2e019
RH		 1015static void gen_branch_n(DisasContext *dc, target_ulong pc1)
1016{
1017 target_ulong npc = dc->npc;
1018
1019 if (likely(npc != DYNAMIC_PC)) {
1020 dc->pc = npc;
1021 dc->jump_pc[0] = pc1;
1022 dc->jump_pc[1] = npc + 4;
1023 dc->npc = JUMP_PC;
1024 } else {
1025 TCGv t, z;
1026
1027 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1028
1029 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
1030 t = tcg_const_tl(pc1);
1031 z = tcg_const_tl(0);
1032 tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, z, t, cpu_npc);
1033 tcg_temp_free(t);
1034 tcg_temp_free(z);
1035
1036 dc->pc = DYNAMIC_PC;
1037 }
1038}
1039
2e655fe7 1040static inline void gen_generic_branch(DisasContext *dc)
83469015 1041{
61316742
RH		 1042 TCGv npc0 = tcg_const_tl(dc->jump_pc[0]);
1043 TCGv npc1 = tcg_const_tl(dc->jump_pc[1]);
1044 TCGv zero = tcg_const_tl(0);
19f329ad 1045
61316742 1046 tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, zero, npc0, npc1);
83469015 1047
61316742
RH		 1048 tcg_temp_free(npc0);
1049 tcg_temp_free(npc1);
1050 tcg_temp_free(zero);
83469015
FB		 1051}
1052
4af984a7
BS		 1053/* call this function before using the condition register as it may
1054 have been set for a jump */
dee8913c 1055static inline void flush_cond(DisasContext *dc)
83469015
FB		 1056{
1057 if (dc->npc == JUMP_PC) {
2e655fe7 1058 gen_generic_branch(dc);
83469015
FB		 1059 dc->npc = DYNAMIC_PC;
1060 }
1061}
1062
934da7ee 1063static inline void save_npc(DisasContext *dc)
72cbca10
FB		 1064{
1065 if (dc->npc == JUMP_PC) {
2e655fe7 1066 gen_generic_branch(dc);
72cbca10
FB		 1067 dc->npc = DYNAMIC_PC;
1068 } else if (dc->npc != DYNAMIC_PC) {
2f5680ee 1069 tcg_gen_movi_tl(cpu_npc, dc->npc);
72cbca10
FB		 1070 }
1071}
1072
20132b96 1073static inline void update_psr(DisasContext *dc)
72cbca10 1074{
cfa90513
BS		 1075 if (dc->cc_op != CC_OP_FLAGS) {
1076 dc->cc_op = CC_OP_FLAGS;
2ffd9176 1077 gen_helper_compute_psr(cpu_env);
cfa90513 1078 }
20132b96
RH		 1079}
1080
1081static inline void save_state(DisasContext *dc)
1082{
1083 tcg_gen_movi_tl(cpu_pc, dc->pc);
934da7ee 1084 save_npc(dc);
72cbca10
FB		 1085}
1086
4fbe0067
RH		 1087static void gen_exception(DisasContext *dc, int which)
1088{
1089 TCGv_i32 t;
1090
1091 save_state(dc);
1092 t = tcg_const_i32(which);
1093 gen_helper_raise_exception(cpu_env, t);
1094 tcg_temp_free_i32(t);
1095 dc->is_br = 1;
1096}
1097
35e94905
RH		 1098static void gen_check_align(TCGv addr, int mask)
1099{
1100 TCGv_i32 r_mask = tcg_const_i32(mask);
1101 gen_helper_check_align(cpu_env, addr, r_mask);
1102 tcg_temp_free_i32(r_mask);
1103}
1104
13a6dd00 1105static inline void gen_mov_pc_npc(DisasContext *dc)
0bee699e
FB		 1106{
1107 if (dc->npc == JUMP_PC) {
2e655fe7 1108 gen_generic_branch(dc);
48d5c82b 1109 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0bee699e
FB		 1110 dc->pc = DYNAMIC_PC;
1111 } else if (dc->npc == DYNAMIC_PC) {
48d5c82b 1112 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0bee699e
FB		 1113 dc->pc = DYNAMIC_PC;
1114 } else {
1115 dc->pc = dc->npc;
1116 }
1117}
1118
38bc628b
BS		 1119static inline void gen_op_next_insn(void)
1120{
48d5c82b
BS		 1121 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1122 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
38bc628b
BS		 1123}
1124
416fcaea
RH		 1125static void free_compare(DisasCompare *cmp)
1126{
1127 if (!cmp->g1) {
1128 tcg_temp_free(cmp->c1);
1129 }
1130 if (!cmp->g2) {
1131 tcg_temp_free(cmp->c2);
1132 }
1133}
1134
2a484ecf 1135static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond,
416fcaea 1136 DisasContext *dc)
19f329ad 1137{
2a484ecf 1138 static int subcc_cond[16] = {
96b5a3d3 1139 TCG_COND_NEVER,
2a484ecf
RH		 1140 TCG_COND_EQ,
1141 TCG_COND_LE,
1142 TCG_COND_LT,
1143 TCG_COND_LEU,
1144 TCG_COND_LTU,
1145 -1, /* neg */
1146 -1, /* overflow */
96b5a3d3 1147 TCG_COND_ALWAYS,
2a484ecf
RH		 1148 TCG_COND_NE,
1149 TCG_COND_GT,
1150 TCG_COND_GE,
1151 TCG_COND_GTU,
1152 TCG_COND_GEU,
1153 -1, /* pos */
1154 -1, /* no overflow */
1155 };
1156
96b5a3d3
RH		 1157 static int logic_cond[16] = {
1158 TCG_COND_NEVER,
1159 TCG_COND_EQ, /* eq: Z */
1160 TCG_COND_LE, /* le: Z | (N ^ V) -> Z | N */
1161 TCG_COND_LT, /* lt: N ^ V -> N */
1162 TCG_COND_EQ, /* leu: C | Z -> Z */
1163 TCG_COND_NEVER, /* ltu: C -> 0 */
1164 TCG_COND_LT, /* neg: N */
1165 TCG_COND_NEVER, /* vs: V -> 0 */
1166 TCG_COND_ALWAYS,
1167 TCG_COND_NE, /* ne: !Z */
1168 TCG_COND_GT, /* gt: !(Z | (N ^ V)) -> !(Z | N) */
1169 TCG_COND_GE, /* ge: !(N ^ V) -> !N */
1170 TCG_COND_NE, /* gtu: !(C | Z) -> !Z */
1171 TCG_COND_ALWAYS, /* geu: !C -> 1 */
1172 TCG_COND_GE, /* pos: !N */
1173 TCG_COND_ALWAYS, /* vc: !V -> 1 */
1174 };
1175
a7812ae4 1176 TCGv_i32 r_src;
416fcaea
RH		 1177 TCGv r_dst;
1178
3475187d 1179#ifdef TARGET_SPARC64
2a484ecf 1180 if (xcc) {
dc99a3f2 1181 r_src = cpu_xcc;
2a484ecf 1182 } else {
dc99a3f2 1183 r_src = cpu_psr;
2a484ecf 1184 }
3475187d 1185#else
dc99a3f2 1186 r_src = cpu_psr;
3475187d 1187#endif
2a484ecf 1188
8393617c 1189 switch (dc->cc_op) {
96b5a3d3
RH		 1190 case CC_OP_LOGIC:
1191 cmp->cond = logic_cond[cond];
1192 do_compare_dst_0:
1193 cmp->is_bool = false;
1194 cmp->g2 = false;
1195 cmp->c2 = tcg_const_tl(0);
1196#ifdef TARGET_SPARC64
1197 if (!xcc) {
1198 cmp->g1 = false;
1199 cmp->c1 = tcg_temp_new();
1200 tcg_gen_ext32s_tl(cmp->c1, cpu_cc_dst);
1201 break;
1202 }
1203#endif
1204 cmp->g1 = true;
1205 cmp->c1 = cpu_cc_dst;
1206 break;
1207
2a484ecf
RH		 1208 case CC_OP_SUB:
1209 switch (cond) {
1210 case 6: /* neg */
1211 case 14: /* pos */
1212 cmp->cond = (cond == 6 ? TCG_COND_LT : TCG_COND_GE);
96b5a3d3 1213 goto do_compare_dst_0;
2a484ecf 1214
2a484ecf
RH		 1215 case 7: /* overflow */
1216 case 15: /* !overflow */
1217 goto do_dynamic;
1218
1219 default:
1220 cmp->cond = subcc_cond[cond];
1221 cmp->is_bool = false;
1222#ifdef TARGET_SPARC64
1223 if (!xcc) {
1224 /* Note that sign-extension works for unsigned compares as
1225 long as both operands are sign-extended. */
1226 cmp->g1 = cmp->g2 = false;
1227 cmp->c1 = tcg_temp_new();
1228 cmp->c2 = tcg_temp_new();
1229 tcg_gen_ext32s_tl(cmp->c1, cpu_cc_src);
1230 tcg_gen_ext32s_tl(cmp->c2, cpu_cc_src2);
0fa2a066 1231 break;
2a484ecf
RH		 1232 }
1233#endif
1234 cmp->g1 = cmp->g2 = true;
1235 cmp->c1 = cpu_cc_src;
1236 cmp->c2 = cpu_cc_src2;
1237 break;
1238 }
8393617c 1239 break;
2a484ecf 1240
8393617c 1241 default:
2a484ecf 1242 do_dynamic:
2ffd9176 1243 gen_helper_compute_psr(cpu_env);
8393617c 1244 dc->cc_op = CC_OP_FLAGS;
2a484ecf
RH		 1245 /* FALLTHRU */
1246
1247 case CC_OP_FLAGS:
1248 /* We're going to generate a boolean result. */
1249 cmp->cond = TCG_COND_NE;
1250 cmp->is_bool = true;
1251 cmp->g1 = cmp->g2 = false;
1252 cmp->c1 = r_dst = tcg_temp_new();
1253 cmp->c2 = tcg_const_tl(0);
1254
1255 switch (cond) {
1256 case 0x0:
1257 gen_op_eval_bn(r_dst);
1258 break;
1259 case 0x1:
1260 gen_op_eval_be(r_dst, r_src);
1261 break;
1262 case 0x2:
1263 gen_op_eval_ble(r_dst, r_src);
1264 break;
1265 case 0x3:
1266 gen_op_eval_bl(r_dst, r_src);
1267 break;
1268 case 0x4:
1269 gen_op_eval_bleu(r_dst, r_src);
1270 break;
1271 case 0x5:
1272 gen_op_eval_bcs(r_dst, r_src);
1273 break;
1274 case 0x6:
1275 gen_op_eval_bneg(r_dst, r_src);
1276 break;
1277 case 0x7:
1278 gen_op_eval_bvs(r_dst, r_src);
1279 break;
1280 case 0x8:
1281 gen_op_eval_ba(r_dst);
1282 break;
1283 case 0x9:
1284 gen_op_eval_bne(r_dst, r_src);
1285 break;
1286 case 0xa:
1287 gen_op_eval_bg(r_dst, r_src);
1288 break;
1289 case 0xb:
1290 gen_op_eval_bge(r_dst, r_src);
1291 break;
1292 case 0xc:
1293 gen_op_eval_bgu(r_dst, r_src);
1294 break;
1295 case 0xd:
1296 gen_op_eval_bcc(r_dst, r_src);
1297 break;
1298 case 0xe:
1299 gen_op_eval_bpos(r_dst, r_src);
1300 break;
1301 case 0xf:
1302 gen_op_eval_bvc(r_dst, r_src);
1303 break;
1304 }
19f329ad
BS		 1305 break;
1306 }
1307}
7a3f1944 1308
416fcaea 1309static void gen_fcompare(DisasCompare *cmp, unsigned int cc, unsigned int cond)
e8af50a3 1310{
19f329ad 1311 unsigned int offset;
416fcaea
RH		 1312 TCGv r_dst;
1313
1314 /* For now we still generate a straight boolean result. */
1315 cmp->cond = TCG_COND_NE;
1316 cmp->is_bool = true;
1317 cmp->g1 = cmp->g2 = false;
1318 cmp->c1 = r_dst = tcg_temp_new();
1319 cmp->c2 = tcg_const_tl(0);
19f329ad 1320
19f329ad
BS		 1321 switch (cc) {
1322 default:
1323 case 0x0:
1324 offset = 0;
1325 break;
1326 case 0x1:
1327 offset = 32 - 10;
1328 break;
1329 case 0x2:
1330 offset = 34 - 10;
1331 break;
1332 case 0x3:
1333 offset = 36 - 10;
1334 break;
1335 }
1336
1337 switch (cond) {
1338 case 0x0:
1339 gen_op_eval_bn(r_dst);
1340 break;
1341 case 0x1:
87e92502 1342 gen_op_eval_fbne(r_dst, cpu_fsr, offset);
19f329ad
BS		 1343 break;
1344 case 0x2:
87e92502 1345 gen_op_eval_fblg(r_dst, cpu_fsr, offset);
19f329ad
BS		 1346 break;
1347 case 0x3:
87e92502 1348 gen_op_eval_fbul(r_dst, cpu_fsr, offset);
19f329ad
BS		 1349 break;
1350 case 0x4:
87e92502 1351 gen_op_eval_fbl(r_dst, cpu_fsr, offset);
19f329ad
BS		 1352 break;
1353 case 0x5:
87e92502 1354 gen_op_eval_fbug(r_dst, cpu_fsr, offset);
19f329ad
BS		 1355 break;
1356 case 0x6:
87e92502 1357 gen_op_eval_fbg(r_dst, cpu_fsr, offset);
19f329ad
BS		 1358 break;
1359 case 0x7:
87e92502 1360 gen_op_eval_fbu(r_dst, cpu_fsr, offset);
19f329ad
BS		 1361 break;
1362 case 0x8:
1363 gen_op_eval_ba(r_dst);
1364 break;
1365 case 0x9:
87e92502 1366 gen_op_eval_fbe(r_dst, cpu_fsr, offset);
19f329ad
BS		 1367 break;
1368 case 0xa:
87e92502 1369 gen_op_eval_fbue(r_dst, cpu_fsr, offset);
19f329ad
BS		 1370 break;
1371 case 0xb:
87e92502 1372 gen_op_eval_fbge(r_dst, cpu_fsr, offset);
19f329ad
BS		 1373 break;
1374 case 0xc:
87e92502 1375 gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
19f329ad
BS		 1376 break;
1377 case 0xd:
87e92502 1378 gen_op_eval_fble(r_dst, cpu_fsr, offset);
19f329ad
BS		 1379 break;
1380 case 0xe:
87e92502 1381 gen_op_eval_fbule(r_dst, cpu_fsr, offset);
19f329ad
BS		 1382 break;
1383 case 0xf:
87e92502 1384 gen_op_eval_fbo(r_dst, cpu_fsr, offset);
19f329ad
BS		 1385 break;
1386 }
e8af50a3 1387}
00f219bf 1388
416fcaea
RH		 1389static void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond,
1390 DisasContext *dc)
1391{
1392 DisasCompare cmp;
1393 gen_compare(&cmp, cc, cond, dc);
1394
1395 /* The interface is to return a boolean in r_dst. */
1396 if (cmp.is_bool) {
1397 tcg_gen_mov_tl(r_dst, cmp.c1);
1398 } else {
1399 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1400 }
1401
1402 free_compare(&cmp);
1403}
1404
1405static void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
1406{
1407 DisasCompare cmp;
1408 gen_fcompare(&cmp, cc, cond);
1409
1410 /* The interface is to return a boolean in r_dst. */
1411 if (cmp.is_bool) {
1412 tcg_gen_mov_tl(r_dst, cmp.c1);
1413 } else {
1414 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1415 }
1416
1417 free_compare(&cmp);
1418}
1419
19f329ad 1420#ifdef TARGET_SPARC64
00f219bf
BS		 1421// Inverted logic
1422static const int gen_tcg_cond_reg[8] = {
1423 -1,
1424 TCG_COND_NE,
1425 TCG_COND_GT,
1426 TCG_COND_GE,
1427 -1,
1428 TCG_COND_EQ,
1429 TCG_COND_LE,
1430 TCG_COND_LT,
1431};
19f329ad 1432
416fcaea
RH		 1433static void gen_compare_reg(DisasCompare *cmp, int cond, TCGv r_src)
1434{
1435 cmp->cond = tcg_invert_cond(gen_tcg_cond_reg[cond]);
1436 cmp->is_bool = false;
1437 cmp->g1 = true;
1438 cmp->g2 = false;
1439 cmp->c1 = r_src;
1440 cmp->c2 = tcg_const_tl(0);
1441}
1442
4af984a7 1443static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
19f329ad 1444{
416fcaea
RH		 1445 DisasCompare cmp;
1446 gen_compare_reg(&cmp, cond, r_src);
19f329ad 1447
416fcaea
RH		 1448 /* The interface is to return a boolean in r_dst. */
1449 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1450
1451 free_compare(&cmp);
19f329ad 1452}
3475187d 1453#endif
cf495bcf 1454
d4a288ef 1455static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc)
7a3f1944 1456{
cf495bcf 1457 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b 1458 target_ulong target = dc->pc + offset;
5fafdf24 1459
22036a49
AT		 1460#ifdef TARGET_SPARC64
1461 if (unlikely(AM_CHECK(dc))) {
1462 target &= 0xffffffffULL;
1463 }
1464#endif
cf495bcf 1465 if (cond == 0x0) {
0f8a249a
BS		 1466 /* unconditional not taken */
1467 if (a) {
1468 dc->pc = dc->npc + 4;
1469 dc->npc = dc->pc + 4;
1470 } else {
1471 dc->pc = dc->npc;
1472 dc->npc = dc->pc + 4;
1473 }
cf495bcf 1474 } else if (cond == 0x8) {
0f8a249a
BS		 1475 /* unconditional taken */
1476 if (a) {
1477 dc->pc = target;
1478 dc->npc = dc->pc + 4;
1479 } else {
1480 dc->pc = dc->npc;
1481 dc->npc = target;
c27e2752 1482 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0f8a249a 1483 }
cf495bcf 1484 } else {
dee8913c 1485 flush_cond(dc);
d4a288ef 1486 gen_cond(cpu_cond, cc, cond, dc);
0f8a249a 1487 if (a) {
bfa31b76 1488 gen_branch_a(dc, target);
0f8a249a 1489 } else {
2bf2e019 1490 gen_branch_n(dc, target);
0f8a249a 1491 }
cf495bcf 1492 }
7a3f1944
FB		 1493}
1494
d4a288ef 1495static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc)
e8af50a3
FB		 1496{
1497 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b
FB		 1498 target_ulong target = dc->pc + offset;
1499
22036a49
AT		 1500#ifdef TARGET_SPARC64
1501 if (unlikely(AM_CHECK(dc))) {
1502 target &= 0xffffffffULL;
1503 }
1504#endif
e8af50a3 1505 if (cond == 0x0) {
0f8a249a
BS		 1506 /* unconditional not taken */
1507 if (a) {
1508 dc->pc = dc->npc + 4;
1509 dc->npc = dc->pc + 4;
1510 } else {
1511 dc->pc = dc->npc;
1512 dc->npc = dc->pc + 4;
1513 }
e8af50a3 1514 } else if (cond == 0x8) {
0f8a249a
BS		 1515 /* unconditional taken */
1516 if (a) {
1517 dc->pc = target;
1518 dc->npc = dc->pc + 4;
1519 } else {
1520 dc->pc = dc->npc;
1521 dc->npc = target;
c27e2752 1522 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0f8a249a 1523 }
e8af50a3 1524 } else {
dee8913c 1525 flush_cond(dc);
d4a288ef 1526 gen_fcond(cpu_cond, cc, cond);
0f8a249a 1527 if (a) {
bfa31b76 1528 gen_branch_a(dc, target);
0f8a249a 1529 } else {
2bf2e019 1530 gen_branch_n(dc, target);
0f8a249a 1531 }
e8af50a3
FB		 1532 }
1533}
1534
3475187d 1535#ifdef TARGET_SPARC64
4af984a7 1536static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
d4a288ef 1537 TCGv r_reg)
7a3f1944 1538{
3475187d
FB		 1539 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1540 target_ulong target = dc->pc + offset;
1541
22036a49
AT		 1542 if (unlikely(AM_CHECK(dc))) {
1543 target &= 0xffffffffULL;
1544 }
dee8913c 1545 flush_cond(dc);
d4a288ef 1546 gen_cond_reg(cpu_cond, cond, r_reg);
3475187d 1547 if (a) {
bfa31b76 1548 gen_branch_a(dc, target);
3475187d 1549 } else {
2bf2e019 1550 gen_branch_n(dc, target);
3475187d 1551 }
7a3f1944
FB		 1552}
1553
a7812ae4 1554static inline void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
7e8c2b6c 1555{
714547bb
BS		 1556 switch (fccno) {
1557 case 0:
7385aed2 1558 gen_helper_fcmps(cpu_fsr, cpu_env, r_rs1, r_rs2);
714547bb
BS		 1559 break;
1560 case 1:
7385aed2 1561 gen_helper_fcmps_fcc1(cpu_fsr, cpu_env, r_rs1, r_rs2);
714547bb
BS		 1562 break;
1563 case 2:
7385aed2 1564 gen_helper_fcmps_fcc2(cpu_fsr, cpu_env, r_rs1, r_rs2);
714547bb
BS		 1565 break;
1566 case 3:
7385aed2 1567 gen_helper_fcmps_fcc3(cpu_fsr, cpu_env, r_rs1, r_rs2);
714547bb
BS		 1568 break;
1569 }
7e8c2b6c
BS		 1570}
1571
03fb8cfc 1572static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1573{
a7812ae4
PB		 1574 switch (fccno) {
1575 case 0:
7385aed2 1576 gen_helper_fcmpd(cpu_fsr, cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1577 break;
1578 case 1:
7385aed2 1579 gen_helper_fcmpd_fcc1(cpu_fsr, cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1580 break;
1581 case 2:
7385aed2 1582 gen_helper_fcmpd_fcc2(cpu_fsr, cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1583 break;
1584 case 3:
7385aed2 1585 gen_helper_fcmpd_fcc3(cpu_fsr, cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1586 break;
1587 }
7e8c2b6c
BS		 1588}
1589
7e8c2b6c
BS		 1590static inline void gen_op_fcmpq(int fccno)
1591{
a7812ae4
PB		 1592 switch (fccno) {
1593 case 0:
7385aed2 1594 gen_helper_fcmpq(cpu_fsr, cpu_env);
a7812ae4
PB		 1595 break;
1596 case 1:
7385aed2 1597 gen_helper_fcmpq_fcc1(cpu_fsr, cpu_env);
a7812ae4
PB		 1598 break;
1599 case 2:
7385aed2 1600 gen_helper_fcmpq_fcc2(cpu_fsr, cpu_env);
a7812ae4
PB		 1601 break;
1602 case 3:
7385aed2 1603 gen_helper_fcmpq_fcc3(cpu_fsr, cpu_env);
a7812ae4
PB		 1604 break;
1605 }
7e8c2b6c 1606}
7e8c2b6c 1607
a7812ae4 1608static inline void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
7e8c2b6c 1609{
714547bb
BS		 1610 switch (fccno) {
1611 case 0:
7385aed2 1612 gen_helper_fcmpes(cpu_fsr, cpu_env, r_rs1, r_rs2);
714547bb
BS		 1613 break;
1614 case 1:
7385aed2 1615 gen_helper_fcmpes_fcc1(cpu_fsr, cpu_env, r_rs1, r_rs2);
714547bb
BS		 1616 break;
1617 case 2:
7385aed2 1618 gen_helper_fcmpes_fcc2(cpu_fsr, cpu_env, r_rs1, r_rs2);
714547bb
BS		 1619 break;
1620 case 3:
7385aed2 1621 gen_helper_fcmpes_fcc3(cpu_fsr, cpu_env, r_rs1, r_rs2);
714547bb
BS		 1622 break;
1623 }
7e8c2b6c
BS		 1624}
1625
03fb8cfc 1626static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1627{
a7812ae4
PB		 1628 switch (fccno) {
1629 case 0:
7385aed2 1630 gen_helper_fcmped(cpu_fsr, cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1631 break;
1632 case 1:
7385aed2 1633 gen_helper_fcmped_fcc1(cpu_fsr, cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1634 break;
1635 case 2:
7385aed2 1636 gen_helper_fcmped_fcc2(cpu_fsr, cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1637 break;
1638 case 3:
7385aed2 1639 gen_helper_fcmped_fcc3(cpu_fsr, cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1640 break;
1641 }
7e8c2b6c
BS		 1642}
1643
7e8c2b6c
BS		 1644static inline void gen_op_fcmpeq(int fccno)
1645{
a7812ae4
PB		 1646 switch (fccno) {
1647 case 0:
7385aed2 1648 gen_helper_fcmpeq(cpu_fsr, cpu_env);
a7812ae4
PB		 1649 break;
1650 case 1:
7385aed2 1651 gen_helper_fcmpeq_fcc1(cpu_fsr, cpu_env);
a7812ae4
PB		 1652 break;
1653 case 2:
7385aed2 1654 gen_helper_fcmpeq_fcc2(cpu_fsr, cpu_env);
a7812ae4
PB		 1655 break;
1656 case 3:
7385aed2 1657 gen_helper_fcmpeq_fcc3(cpu_fsr, cpu_env);
a7812ae4
PB		 1658 break;
1659 }
7e8c2b6c 1660}
7e8c2b6c
BS		 1661
1662#else
1663
714547bb 1664static inline void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2)
7e8c2b6c 1665{
7385aed2 1666 gen_helper_fcmps(cpu_fsr, cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1667}
1668
03fb8cfc 1669static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1670{
7385aed2 1671 gen_helper_fcmpd(cpu_fsr, cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1672}
1673
7e8c2b6c
BS		 1674static inline void gen_op_fcmpq(int fccno)
1675{
7385aed2 1676 gen_helper_fcmpq(cpu_fsr, cpu_env);
7e8c2b6c 1677}
7e8c2b6c 1678
714547bb 1679static inline void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2)
7e8c2b6c 1680{
7385aed2 1681 gen_helper_fcmpes(cpu_fsr, cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1682}
1683
03fb8cfc 1684static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1685{
7385aed2 1686 gen_helper_fcmped(cpu_fsr, cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1687}
1688
7e8c2b6c
BS		 1689static inline void gen_op_fcmpeq(int fccno)
1690{
7385aed2 1691 gen_helper_fcmpeq(cpu_fsr, cpu_env);
7e8c2b6c
BS		 1692}
1693#endif
1694
4fbe0067 1695static void gen_op_fpexception_im(DisasContext *dc, int fsr_flags)
134d77a1 1696{
47ad35f1 1697 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_NMASK);
87e92502 1698 tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
4fbe0067 1699 gen_exception(dc, TT_FP_EXCP);
134d77a1
BS		 1700}
1701
5b12f1e8 1702static int gen_trap_ifnofpu(DisasContext *dc)
a80dde08
FB		 1703{
1704#if !defined(CONFIG_USER_ONLY)
1705 if (!dc->fpu_enabled) {
4fbe0067 1706 gen_exception(dc, TT_NFPU_INSN);
a80dde08
FB		 1707 return 1;
1708 }
1709#endif
1710 return 0;
1711}
1712
7e8c2b6c
BS		 1713static inline void gen_op_clear_ieee_excp_and_FTT(void)
1714{
47ad35f1 1715 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK);
7e8c2b6c
BS		 1716}
1717
61f17f6e
RH		 1718static inline void gen_fop_FF(DisasContext *dc, int rd, int rs,
1719 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32))
1720{
1721 TCGv_i32 dst, src;
1722
61f17f6e 1723 src = gen_load_fpr_F(dc, rs);
ba5f5179 1724 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1725
1726 gen(dst, cpu_env, src);
7385aed2 1727 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1728
61f17f6e
RH		 1729 gen_store_fpr_F(dc, rd, dst);
1730}
1731
1732static inline void gen_ne_fop_FF(DisasContext *dc, int rd, int rs,
1733 void (*gen)(TCGv_i32, TCGv_i32))
1734{
1735 TCGv_i32 dst, src;
1736
1737 src = gen_load_fpr_F(dc, rs);
ba5f5179 1738 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1739
1740 gen(dst, src);
1741
1742 gen_store_fpr_F(dc, rd, dst);
1743}
1744
1745static inline void gen_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
1746 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32))
1747{
1748 TCGv_i32 dst, src1, src2;
1749
61f17f6e
RH		 1750 src1 = gen_load_fpr_F(dc, rs1);
1751 src2 = gen_load_fpr_F(dc, rs2);
ba5f5179 1752 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1753
1754 gen(dst, cpu_env, src1, src2);
7385aed2 1755 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1756
61f17f6e
RH		 1757 gen_store_fpr_F(dc, rd, dst);
1758}
1759
1760#ifdef TARGET_SPARC64
1761static inline void gen_ne_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
1762 void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32))
1763{
1764 TCGv_i32 dst, src1, src2;
1765
1766 src1 = gen_load_fpr_F(dc, rs1);
1767 src2 = gen_load_fpr_F(dc, rs2);
ba5f5179 1768 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1769
1770 gen(dst, src1, src2);
1771
1772 gen_store_fpr_F(dc, rd, dst);
1773}
1774#endif
1775
1776static inline void gen_fop_DD(DisasContext *dc, int rd, int rs,
1777 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64))
1778{
1779 TCGv_i64 dst, src;
1780
61f17f6e 1781 src = gen_load_fpr_D(dc, rs);
3886b8a3 1782 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1783
1784 gen(dst, cpu_env, src);
7385aed2 1785 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1786
61f17f6e
RH		 1787 gen_store_fpr_D(dc, rd, dst);
1788}
1789
1790#ifdef TARGET_SPARC64
1791static inline void gen_ne_fop_DD(DisasContext *dc, int rd, int rs,
1792 void (*gen)(TCGv_i64, TCGv_i64))
1793{
1794 TCGv_i64 dst, src;
1795
1796 src = gen_load_fpr_D(dc, rs);
3886b8a3 1797 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1798
1799 gen(dst, src);
1800
1801 gen_store_fpr_D(dc, rd, dst);
1802}
1803#endif
1804
1805static inline void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1806 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64))
1807{
1808 TCGv_i64 dst, src1, src2;
1809
61f17f6e
RH		 1810 src1 = gen_load_fpr_D(dc, rs1);
1811 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1812 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1813
1814 gen(dst, cpu_env, src1, src2);
7385aed2 1815 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1816
61f17f6e
RH		 1817 gen_store_fpr_D(dc, rd, dst);
1818}
1819
1820#ifdef TARGET_SPARC64
1821static inline void gen_ne_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1822 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64))
1823{
1824 TCGv_i64 dst, src1, src2;
1825
1826 src1 = gen_load_fpr_D(dc, rs1);
1827 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1828 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1829
1830 gen(dst, src1, src2);
1831
1832 gen_store_fpr_D(dc, rd, dst);
1833}
f888300b 1834
2dedf314
RH		 1835static inline void gen_gsr_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1836 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
1837{
1838 TCGv_i64 dst, src1, src2;
1839
1840 src1 = gen_load_fpr_D(dc, rs1);
1841 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1842 dst = gen_dest_fpr_D(dc, rd);
2dedf314
RH		 1843
1844 gen(dst, cpu_gsr, src1, src2);
1845
1846 gen_store_fpr_D(dc, rd, dst);
1847}
1848
f888300b
RH		 1849static inline void gen_ne_fop_DDDD(DisasContext *dc, int rd, int rs1, int rs2,
1850 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
1851{
1852 TCGv_i64 dst, src0, src1, src2;
1853
1854 src1 = gen_load_fpr_D(dc, rs1);
1855 src2 = gen_load_fpr_D(dc, rs2);
1856 src0 = gen_load_fpr_D(dc, rd);
3886b8a3 1857 dst = gen_dest_fpr_D(dc, rd);
f888300b
RH		 1858
1859 gen(dst, src0, src1, src2);
1860
1861 gen_store_fpr_D(dc, rd, dst);
1862}
61f17f6e
RH		 1863#endif
1864
1865static inline void gen_fop_QQ(DisasContext *dc, int rd, int rs,
1866 void (*gen)(TCGv_ptr))
1867{
61f17f6e
RH		 1868 gen_op_load_fpr_QT1(QFPREG(rs));
1869
1870 gen(cpu_env);
7385aed2 1871 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1872
61f17f6e 1873 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 1874 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 1875}
1876
1877#ifdef TARGET_SPARC64
1878static inline void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs,
1879 void (*gen)(TCGv_ptr))
1880{
1881 gen_op_load_fpr_QT1(QFPREG(rs));
1882
1883 gen(cpu_env);
1884
1885 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 1886 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 1887}
1888#endif
1889
1890static inline void gen_fop_QQQ(DisasContext *dc, int rd, int rs1, int rs2,
1891 void (*gen)(TCGv_ptr))
1892{
61f17f6e
RH		 1893 gen_op_load_fpr_QT0(QFPREG(rs1));
1894 gen_op_load_fpr_QT1(QFPREG(rs2));
1895
1896 gen(cpu_env);
7385aed2 1897 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1898
61f17f6e 1899 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 1900 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 1901}
1902
1903static inline void gen_fop_DFF(DisasContext *dc, int rd, int rs1, int rs2,
1904 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32, TCGv_i32))
1905{
1906 TCGv_i64 dst;
1907 TCGv_i32 src1, src2;
1908
61f17f6e
RH		 1909 src1 = gen_load_fpr_F(dc, rs1);
1910 src2 = gen_load_fpr_F(dc, rs2);
3886b8a3 1911 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1912
1913 gen(dst, cpu_env, src1, src2);
7385aed2 1914 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1915
61f17f6e
RH		 1916 gen_store_fpr_D(dc, rd, dst);
1917}
1918
1919static inline void gen_fop_QDD(DisasContext *dc, int rd, int rs1, int rs2,
1920 void (*gen)(TCGv_ptr, TCGv_i64, TCGv_i64))
1921{
1922 TCGv_i64 src1, src2;
1923
61f17f6e
RH		 1924 src1 = gen_load_fpr_D(dc, rs1);
1925 src2 = gen_load_fpr_D(dc, rs2);
1926
1927 gen(cpu_env, src1, src2);
7385aed2 1928 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1929
61f17f6e 1930 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 1931 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 1932}
1933
1934#ifdef TARGET_SPARC64
1935static inline void gen_fop_DF(DisasContext *dc, int rd, int rs,
1936 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32))
1937{
1938 TCGv_i64 dst;
1939 TCGv_i32 src;
1940
61f17f6e 1941 src = gen_load_fpr_F(dc, rs);
3886b8a3 1942 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1943
1944 gen(dst, cpu_env, src);
7385aed2 1945 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1946
61f17f6e
RH		 1947 gen_store_fpr_D(dc, rd, dst);
1948}
1949#endif
1950
1951static inline void gen_ne_fop_DF(DisasContext *dc, int rd, int rs,
1952 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32))
1953{
1954 TCGv_i64 dst;
1955 TCGv_i32 src;
1956
1957 src = gen_load_fpr_F(dc, rs);
3886b8a3 1958 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1959
1960 gen(dst, cpu_env, src);
1961
1962 gen_store_fpr_D(dc, rd, dst);
1963}
1964
1965static inline void gen_fop_FD(DisasContext *dc, int rd, int rs,
1966 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i64))
1967{
1968 TCGv_i32 dst;
1969 TCGv_i64 src;
1970
61f17f6e 1971 src = gen_load_fpr_D(dc, rs);
ba5f5179 1972 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1973
1974 gen(dst, cpu_env, src);
7385aed2 1975 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1976
61f17f6e
RH		 1977 gen_store_fpr_F(dc, rd, dst);
1978}
1979
1980static inline void gen_fop_FQ(DisasContext *dc, int rd, int rs,
1981 void (*gen)(TCGv_i32, TCGv_ptr))
1982{
1983 TCGv_i32 dst;
1984
61f17f6e 1985 gen_op_load_fpr_QT1(QFPREG(rs));
ba5f5179 1986 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1987
1988 gen(dst, cpu_env);
7385aed2 1989 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1990
61f17f6e
RH		 1991 gen_store_fpr_F(dc, rd, dst);
1992}
1993
1994static inline void gen_fop_DQ(DisasContext *dc, int rd, int rs,
1995 void (*gen)(TCGv_i64, TCGv_ptr))
1996{
1997 TCGv_i64 dst;
1998
61f17f6e 1999 gen_op_load_fpr_QT1(QFPREG(rs));
3886b8a3 2000 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 2001
2002 gen(dst, cpu_env);
7385aed2 2003 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 2004
61f17f6e
RH		 2005 gen_store_fpr_D(dc, rd, dst);
2006}
2007
2008static inline void gen_ne_fop_QF(DisasContext *dc, int rd, int rs,
2009 void (*gen)(TCGv_ptr, TCGv_i32))
2010{
2011 TCGv_i32 src;
2012
2013 src = gen_load_fpr_F(dc, rs);
2014
2015 gen(cpu_env, src);
2016
2017 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 2018 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 2019}
2020
2021static inline void gen_ne_fop_QD(DisasContext *dc, int rd, int rs,
2022 void (*gen)(TCGv_ptr, TCGv_i64))
2023{
2024 TCGv_i64 src;
2025
2026 src = gen_load_fpr_D(dc, rs);
2027
2028 gen(cpu_env, src);
2029
2030 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 2031 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 2032}
2033
4fb554bc
RH		 2034static void gen_swap(DisasContext *dc, TCGv dst, TCGv src,
2035 TCGv addr, int mmu_idx, TCGMemOp memop)
2036{
4fb554bc 2037 gen_address_mask(dc, addr);
da1bcae6 2038 tcg_gen_atomic_xchg_tl(dst, addr, src, mmu_idx, memop);
4fb554bc
RH		 2039}
2040
fbb4bbb6
RH		 2041static void gen_ldstub(DisasContext *dc, TCGv dst, TCGv addr, int mmu_idx)
2042{
da1bcae6 2043 TCGv m1 = tcg_const_tl(0xff);
fbb4bbb6 2044 gen_address_mask(dc, addr);
da1bcae6
RH		 2045 tcg_gen_atomic_xchg_tl(dst, addr, m1, mmu_idx, MO_UB);
2046 tcg_temp_free(m1);
fbb4bbb6
RH		 2047}
2048
1a2fb1c0 2049/* asi moves */
22e70060 2050#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
7ec1e5ea
RH		 2051typedef enum {
2052 GET_ASI_HELPER,
2053 GET_ASI_EXCP,
f0913be0 2054 GET_ASI_DIRECT,
e4dc0052 2055 GET_ASI_DTWINX,
ca5ce572
RH		 2056 GET_ASI_BLOCK,
2057 GET_ASI_SHORT,
34810610
RH		 2058 GET_ASI_BCOPY,
2059 GET_ASI_BFILL,
7ec1e5ea
RH		 2060} ASIType;
2061
2062typedef struct {
2063 ASIType type;
a6d567e5 2064 int asi;
f0913be0
RH		 2065 int mem_idx;
2066 TCGMemOp memop;
7ec1e5ea 2067} DisasASI;
1a2fb1c0 2068
f0913be0 2069static DisasASI get_asi(DisasContext *dc, int insn, TCGMemOp memop)
7ec1e5ea
RH		 2070{
2071 int asi = GET_FIELD(insn, 19, 26);
2072 ASIType type = GET_ASI_HELPER;
f0913be0 2073 int mem_idx = dc->mem_idx;
7ec1e5ea
RH		 2074
2075#ifndef TARGET_SPARC64
2076 /* Before v9, all asis are immediate and privileged. */
1a2fb1c0 2077 if (IS_IMM) {
22e70060 2078 gen_exception(dc, TT_ILL_INSN);
7ec1e5ea
RH		 2079 type = GET_ASI_EXCP;
2080 } else if (supervisor(dc)
2081 /* Note that LEON accepts ASI_USERDATA in user mode, for
2082 use with CASA. Also note that previous versions of
0cc1f4bf
RH		 2083 QEMU allowed (and old versions of gcc emitted) ASI_P
2084 for LEON, which is incorrect. */
2085 || (asi == ASI_USERDATA
7ec1e5ea 2086 && (dc->def->features & CPU_FEATURE_CASA))) {
f0913be0
RH		 2087 switch (asi) {
2088 case ASI_USERDATA: /* User data access */
2089 mem_idx = MMU_USER_IDX;
2090 type = GET_ASI_DIRECT;
2091 break;
2092 case ASI_KERNELDATA: /* Supervisor data access */
2093 mem_idx = MMU_KERNEL_IDX;
2094 type = GET_ASI_DIRECT;
2095 break;
7f87c905
RH		 2096 case ASI_M_BYPASS: /* MMU passthrough */
2097 case ASI_LEON_BYPASS: /* LEON MMU passthrough */
2098 mem_idx = MMU_PHYS_IDX;
2099 type = GET_ASI_DIRECT;
2100 break;
34810610
RH		 2101 case ASI_M_BCOPY: /* Block copy, sta access */
2102 mem_idx = MMU_KERNEL_IDX;
2103 type = GET_ASI_BCOPY;
2104 break;
2105 case ASI_M_BFILL: /* Block fill, stda access */
2106 mem_idx = MMU_KERNEL_IDX;
2107 type = GET_ASI_BFILL;
2108 break;
f0913be0 2109 }
1a2fb1c0 2110 } else {
7ec1e5ea
RH		 2111 gen_exception(dc, TT_PRIV_INSN);
2112 type = GET_ASI_EXCP;
2113 }
2114#else
2115 if (IS_IMM) {
2116 asi = dc->asi;
1a2fb1c0 2117 }
f0913be0
RH		 2118 /* With v9, all asis below 0x80 are privileged. */
2119 /* ??? We ought to check cpu_has_hypervisor, but we didn't copy
2120 down that bit into DisasContext. For the moment that's ok,
2121 since the direct implementations below doesn't have any ASIs
2122 in the restricted [0x30, 0x7f] range, and the check will be
2123 done properly in the helper. */
2124 if (!supervisor(dc) && asi < 0x80) {
2125 gen_exception(dc, TT_PRIV_ACT);
2126 type = GET_ASI_EXCP;
2127 } else {
2128 switch (asi) {
7f87c905
RH		 2129 case ASI_REAL: /* Bypass */
2130 case ASI_REAL_IO: /* Bypass, non-cacheable */
2131 case ASI_REAL_L: /* Bypass LE */
2132 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */
2133 case ASI_TWINX_REAL: /* Real address, twinx */
2134 case ASI_TWINX_REAL_L: /* Real address, twinx, LE */
34a6e13d
RH		 2135 case ASI_QUAD_LDD_PHYS:
2136 case ASI_QUAD_LDD_PHYS_L:
7f87c905
RH		 2137 mem_idx = MMU_PHYS_IDX;
2138 break;
f0913be0
RH		 2139 case ASI_N: /* Nucleus */
2140 case ASI_NL: /* Nucleus LE */
e4dc0052
RH		 2141 case ASI_TWINX_N:
2142 case ASI_TWINX_NL:
34a6e13d
RH		 2143 case ASI_NUCLEUS_QUAD_LDD:
2144 case ASI_NUCLEUS_QUAD_LDD_L:
9a10756d
AT		 2145 if (hypervisor(dc)) {
2146 mem_idx = MMU_HYPV_IDX;
2147 } else {
2148 mem_idx = MMU_NUCLEUS_IDX;
2149 }
f0913be0
RH		 2150 break;
2151 case ASI_AIUP: /* As if user primary */
2152 case ASI_AIUPL: /* As if user primary LE */
e4dc0052
RH		 2153 case ASI_TWINX_AIUP:
2154 case ASI_TWINX_AIUP_L:
ca5ce572
RH		 2155 case ASI_BLK_AIUP_4V:
2156 case ASI_BLK_AIUP_L_4V:
2157 case ASI_BLK_AIUP:
2158 case ASI_BLK_AIUPL:
f0913be0
RH		 2159 mem_idx = MMU_USER_IDX;
2160 break;
2161 case ASI_AIUS: /* As if user secondary */
2162 case ASI_AIUSL: /* As if user secondary LE */
e4dc0052
RH		 2163 case ASI_TWINX_AIUS:
2164 case ASI_TWINX_AIUS_L:
ca5ce572
RH		 2165 case ASI_BLK_AIUS_4V:
2166 case ASI_BLK_AIUS_L_4V:
2167 case ASI_BLK_AIUS:
2168 case ASI_BLK_AIUSL:
f0913be0
RH		 2169 mem_idx = MMU_USER_SECONDARY_IDX;
2170 break;
2171 case ASI_S: /* Secondary */
2172 case ASI_SL: /* Secondary LE */
e4dc0052
RH		 2173 case ASI_TWINX_S:
2174 case ASI_TWINX_SL:
ca5ce572
RH		 2175 case ASI_BLK_COMMIT_S:
2176 case ASI_BLK_S:
2177 case ASI_BLK_SL:
2178 case ASI_FL8_S:
2179 case ASI_FL8_SL:
2180 case ASI_FL16_S:
2181 case ASI_FL16_SL:
f0913be0
RH		 2182 if (mem_idx == MMU_USER_IDX) {
2183 mem_idx = MMU_USER_SECONDARY_IDX;
2184 } else if (mem_idx == MMU_KERNEL_IDX) {
2185 mem_idx = MMU_KERNEL_SECONDARY_IDX;
2186 }
2187 break;
2188 case ASI_P: /* Primary */
2189 case ASI_PL: /* Primary LE */
e4dc0052
RH		 2190 case ASI_TWINX_P:
2191 case ASI_TWINX_PL:
ca5ce572
RH		 2192 case ASI_BLK_COMMIT_P:
2193 case ASI_BLK_P:
2194 case ASI_BLK_PL:
2195 case ASI_FL8_P:
2196 case ASI_FL8_PL:
2197 case ASI_FL16_P:
2198 case ASI_FL16_PL:
f0913be0
RH		 2199 break;
2200 }
2201 switch (asi) {
7f87c905
RH		 2202 case ASI_REAL:
2203 case ASI_REAL_IO:
2204 case ASI_REAL_L:
2205 case ASI_REAL_IO_L:
f0913be0
RH		 2206 case ASI_N:
2207 case ASI_NL:
2208 case ASI_AIUP:
2209 case ASI_AIUPL:
2210 case ASI_AIUS:
2211 case ASI_AIUSL:
2212 case ASI_S:
2213 case ASI_SL:
2214 case ASI_P:
2215 case ASI_PL:
2216 type = GET_ASI_DIRECT;
2217 break;
7f87c905
RH		 2218 case ASI_TWINX_REAL:
2219 case ASI_TWINX_REAL_L:
e4dc0052
RH		 2220 case ASI_TWINX_N:
2221 case ASI_TWINX_NL:
2222 case ASI_TWINX_AIUP:
2223 case ASI_TWINX_AIUP_L:
2224 case ASI_TWINX_AIUS:
2225 case ASI_TWINX_AIUS_L:
2226 case ASI_TWINX_P:
2227 case ASI_TWINX_PL:
2228 case ASI_TWINX_S:
2229 case ASI_TWINX_SL:
34a6e13d
RH		 2230 case ASI_QUAD_LDD_PHYS:
2231 case ASI_QUAD_LDD_PHYS_L:
2232 case ASI_NUCLEUS_QUAD_LDD:
2233 case ASI_NUCLEUS_QUAD_LDD_L:
e4dc0052
RH		 2234 type = GET_ASI_DTWINX;
2235 break;
ca5ce572
RH		 2236 case ASI_BLK_COMMIT_P:
2237 case ASI_BLK_COMMIT_S:
2238 case ASI_BLK_AIUP_4V:
2239 case ASI_BLK_AIUP_L_4V:
2240 case ASI_BLK_AIUP:
2241 case ASI_BLK_AIUPL:
2242 case ASI_BLK_AIUS_4V:
2243 case ASI_BLK_AIUS_L_4V:
2244 case ASI_BLK_AIUS:
2245 case ASI_BLK_AIUSL:
2246 case ASI_BLK_S:
2247 case ASI_BLK_SL:
2248 case ASI_BLK_P:
2249 case ASI_BLK_PL:
2250 type = GET_ASI_BLOCK;
2251 break;
2252 case ASI_FL8_S:
2253 case ASI_FL8_SL:
2254 case ASI_FL8_P:
2255 case ASI_FL8_PL:
2256 memop = MO_UB;
2257 type = GET_ASI_SHORT;
2258 break;
2259 case ASI_FL16_S:
2260 case ASI_FL16_SL:
2261 case ASI_FL16_P:
2262 case ASI_FL16_PL:
2263 memop = MO_TEUW;
2264 type = GET_ASI_SHORT;
2265 break;
f0913be0
RH		 2266 }
2267 /* The little-endian asis all have bit 3 set. */
2268 if (asi & 8) {
2269 memop ^= MO_BSWAP;
2270 }
2271 }
7ec1e5ea
RH		 2272#endif
2273
f0913be0 2274 return (DisasASI){ type, asi, mem_idx, memop };
0425bee5
BS		 2275}
2276
22e70060 2277static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr,
1d65b0f5 2278 int insn, TCGMemOp memop)
0425bee5 2279{
f0913be0 2280 DisasASI da = get_asi(dc, insn, memop);
0425bee5 2281
7ec1e5ea
RH		 2282 switch (da.type) {
2283 case GET_ASI_EXCP:
2284 break;
e4dc0052
RH		 2285 case GET_ASI_DTWINX: /* Reserved for ldda. */
2286 gen_exception(dc, TT_ILL_INSN);
2287 break;
f0913be0
RH		 2288 case GET_ASI_DIRECT:
2289 gen_address_mask(dc, addr);
2290 tcg_gen_qemu_ld_tl(dst, addr, da.mem_idx, da.memop);
2291 break;
7ec1e5ea
RH		 2292 default:
2293 {
2294 TCGv_i32 r_asi = tcg_const_i32(da.asi);
6850811e 2295 TCGv_i32 r_mop = tcg_const_i32(memop);
7ec1e5ea
RH		 2296
2297 save_state(dc);
22e70060 2298#ifdef TARGET_SPARC64
6850811e 2299 gen_helper_ld_asi(dst, cpu_env, addr, r_asi, r_mop);
22e70060 2300#else
7ec1e5ea
RH		 2301 {
2302 TCGv_i64 t64 = tcg_temp_new_i64();
6850811e 2303 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop);
7ec1e5ea
RH		 2304 tcg_gen_trunc_i64_tl(dst, t64);
2305 tcg_temp_free_i64(t64);
2306 }
22e70060 2307#endif
6850811e 2308 tcg_temp_free_i32(r_mop);
7ec1e5ea
RH		 2309 tcg_temp_free_i32(r_asi);
2310 }
2311 break;
2312 }
1a2fb1c0
BS		 2313}
2314
22e70060 2315static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr,
1d65b0f5 2316 int insn, TCGMemOp memop)
1a2fb1c0 2317{
f0913be0 2318 DisasASI da = get_asi(dc, insn, memop);
1a2fb1c0 2319
7ec1e5ea
RH		 2320 switch (da.type) {
2321 case GET_ASI_EXCP:
2322 break;
e4dc0052
RH		 2323 case GET_ASI_DTWINX: /* Reserved for stda. */
2324 gen_exception(dc, TT_ILL_INSN);
2325 break;
f0913be0
RH		 2326 case GET_ASI_DIRECT:
2327 gen_address_mask(dc, addr);
2328 tcg_gen_qemu_st_tl(src, addr, da.mem_idx, da.memop);
2329 break;
34810610
RH		 2330#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
2331 case GET_ASI_BCOPY:
2332 /* Copy 32 bytes from the address in SRC to ADDR. */
2333 /* ??? The original qemu code suggests 4-byte alignment, dropping
2334 the low bits, but the only place I can see this used is in the
2335 Linux kernel with 32 byte alignment, which would make more sense
2336 as a cacheline-style operation. */
2337 {
2338 TCGv saddr = tcg_temp_new();
2339 TCGv daddr = tcg_temp_new();
2340 TCGv four = tcg_const_tl(4);
2341 TCGv_i32 tmp = tcg_temp_new_i32();
2342 int i;
2343
2344 tcg_gen_andi_tl(saddr, src, -4);
2345 tcg_gen_andi_tl(daddr, addr, -4);
2346 for (i = 0; i < 32; i += 4) {
2347 /* Since the loads and stores are paired, allow the
2348 copy to happen in the host endianness. */
2349 tcg_gen_qemu_ld_i32(tmp, saddr, da.mem_idx, MO_UL);
2350 tcg_gen_qemu_st_i32(tmp, daddr, da.mem_idx, MO_UL);
2351 tcg_gen_add_tl(saddr, saddr, four);
2352 tcg_gen_add_tl(daddr, daddr, four);
2353 }
2354
2355 tcg_temp_free(saddr);
2356 tcg_temp_free(daddr);
2357 tcg_temp_free(four);
2358 tcg_temp_free_i32(tmp);
2359 }
2360 break;
2361#endif
7ec1e5ea
RH		 2362 default:
2363 {
2364 TCGv_i32 r_asi = tcg_const_i32(da.asi);
6850811e 2365 TCGv_i32 r_mop = tcg_const_i32(memop & MO_SIZE);
7ec1e5ea
RH		 2366
2367 save_state(dc);
22e70060 2368#ifdef TARGET_SPARC64
6850811e 2369 gen_helper_st_asi(cpu_env, addr, src, r_asi, r_mop);
22e70060 2370#else
7ec1e5ea
RH		 2371 {
2372 TCGv_i64 t64 = tcg_temp_new_i64();
2373 tcg_gen_extu_tl_i64(t64, src);
6850811e 2374 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_mop);
7ec1e5ea
RH		 2375 tcg_temp_free_i64(t64);
2376 }
22e70060 2377#endif
6850811e 2378 tcg_temp_free_i32(r_mop);
7ec1e5ea
RH		 2379 tcg_temp_free_i32(r_asi);
2380
2381 /* A write to a TLB register may alter page maps. End the TB. */
2382 dc->npc = DYNAMIC_PC;
2383 }
2384 break;
2385 }
1a2fb1c0
BS		 2386}
2387
22e70060
RH		 2388static void gen_swap_asi(DisasContext *dc, TCGv dst, TCGv src,
2389 TCGv addr, int insn)
1a2fb1c0 2390{
f0913be0 2391 DisasASI da = get_asi(dc, insn, MO_TEUL);
22e70060 2392
7ec1e5ea
RH		 2393 switch (da.type) {
2394 case GET_ASI_EXCP:
2395 break;
4fb554bc
RH		 2396 case GET_ASI_DIRECT:
2397 gen_swap(dc, dst, src, addr, da.mem_idx, da.memop);
2398 break;
7ec1e5ea 2399 default:
4fb554bc
RH		 2400 /* ??? Should be DAE_invalid_asi. */
2401 gen_exception(dc, TT_DATA_ACCESS);
7ec1e5ea
RH		 2402 break;
2403 }
1a2fb1c0
BS		 2404}
2405
5a7267b6 2406static void gen_cas_asi(DisasContext *dc, TCGv addr, TCGv cmpv,
22e70060
RH		 2407 int insn, int rd)
2408{
f0913be0 2409 DisasASI da = get_asi(dc, insn, MO_TEUL);
5a7267b6 2410 TCGv oldv;
22e70060 2411
7268adeb
RH		 2412 switch (da.type) {
2413 case GET_ASI_EXCP:
7ec1e5ea 2414 return;
7268adeb 2415 case GET_ASI_DIRECT:
7268adeb 2416 oldv = tcg_temp_new();
5a7267b6
RH		 2417 tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, gen_load_gpr(dc, rd),
2418 da.mem_idx, da.memop);
7268adeb 2419 gen_store_gpr(dc, rd, oldv);
7268adeb 2420 tcg_temp_free(oldv);
7268adeb
RH		 2421 break;
2422 default:
2423 /* ??? Should be DAE_invalid_asi. */
2424 gen_exception(dc, TT_DATA_ACCESS);
2425 break;
7ec1e5ea 2426 }
22e70060
RH		 2427}
2428
2429static void gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn)
2430{
f0913be0 2431 DisasASI da = get_asi(dc, insn, MO_UB);
22e70060 2432
7ec1e5ea
RH		 2433 switch (da.type) {
2434 case GET_ASI_EXCP:
2435 break;
fbb4bbb6
RH		 2436 case GET_ASI_DIRECT:
2437 gen_ldstub(dc, dst, addr, da.mem_idx);
2438 break;
7ec1e5ea 2439 default:
fbb4bbb6
RH		 2440 /* ??? Should be DAE_invalid_asi. */
2441 gen_exception(dc, TT_DATA_ACCESS);
7ec1e5ea
RH		 2442 break;
2443 }
22e70060
RH		 2444}
2445#endif
2446
2447#ifdef TARGET_SPARC64
2448static void gen_ldf_asi(DisasContext *dc, TCGv addr,
2449 int insn, int size, int rd)
1a2fb1c0 2450{
f0913be0 2451 DisasASI da = get_asi(dc, insn, (size == 4 ? MO_TEUL : MO_TEQ));
7705091c 2452 TCGv_i32 d32;
cb21b4da 2453 TCGv_i64 d64;
1a2fb1c0 2454
7ec1e5ea
RH		 2455 switch (da.type) {
2456 case GET_ASI_EXCP:
2457 break;
7705091c
RH		 2458
2459 case GET_ASI_DIRECT:
2460 gen_address_mask(dc, addr);
2461 switch (size) {
2462 case 4:
2463 d32 = gen_dest_fpr_F(dc);
2464 tcg_gen_qemu_ld_i32(d32, addr, da.mem_idx, da.memop);
2465 gen_store_fpr_F(dc, rd, d32);
2466 break;
2467 case 8:
cb21b4da
RH		 2468 tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da.mem_idx,
2469 da.memop | MO_ALIGN_4);
7705091c
RH		 2470 break;
2471 case 16:
cb21b4da
RH		 2472 d64 = tcg_temp_new_i64();
2473 tcg_gen_qemu_ld_i64(d64, addr, da.mem_idx, da.memop | MO_ALIGN_4);
7705091c 2474 tcg_gen_addi_tl(addr, addr, 8);
cb21b4da
RH		 2475 tcg_gen_qemu_ld_i64(cpu_fpr[rd/2+1], addr, da.mem_idx,
2476 da.memop | MO_ALIGN_4);
2477 tcg_gen_mov_i64(cpu_fpr[rd / 2], d64);
2478 tcg_temp_free_i64(d64);
7705091c
RH		 2479 break;
2480 default:
2481 g_assert_not_reached();
2482 }
2483 break;
2484
ca5ce572
RH		 2485 case GET_ASI_BLOCK:
2486 /* Valid for lddfa on aligned registers only. */
2487 if (size == 8 && (rd & 7) == 0) {
80883227 2488 TCGMemOp memop;
ca5ce572
RH		 2489 TCGv eight;
2490 int i;
2491
ca5ce572
RH		 2492 gen_address_mask(dc, addr);
2493
80883227
RH		 2494 /* The first operation checks required alignment. */
2495 memop = da.memop | MO_ALIGN_64;
ca5ce572
RH		 2496 eight = tcg_const_tl(8);
2497 for (i = 0; ; ++i) {
2498 tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + i], addr,
80883227 2499 da.mem_idx, memop);
ca5ce572
RH		 2500 if (i == 7) {
2501 break;
2502 }
2503 tcg_gen_add_tl(addr, addr, eight);
80883227 2504 memop = da.memop;
ca5ce572
RH		 2505 }
2506 tcg_temp_free(eight);
2507 } else {
2508 gen_exception(dc, TT_ILL_INSN);
2509 }
2510 break;
2511
2512 case GET_ASI_SHORT:
2513 /* Valid for lddfa only. */
2514 if (size == 8) {
2515 gen_address_mask(dc, addr);
2516 tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da.mem_idx, da.memop);
2517 } else {
2518 gen_exception(dc, TT_ILL_INSN);
2519 }
2520 break;
2521
7ec1e5ea
RH		 2522 default:
2523 {
2524 TCGv_i32 r_asi = tcg_const_i32(da.asi);
f2fe396f 2525 TCGv_i32 r_mop = tcg_const_i32(da.memop);
7ec1e5ea
RH		 2526
2527 save_state(dc);
f2fe396f
RH		 2528 /* According to the table in the UA2011 manual, the only
2529 other asis that are valid for ldfa/lddfa/ldqfa are
2530 the NO_FAULT asis. We still need a helper for these,
2531 but we can just use the integer asi helper for them. */
2532 switch (size) {
2533 case 4:
cb21b4da
RH		 2534 d64 = tcg_temp_new_i64();
2535 gen_helper_ld_asi(d64, cpu_env, addr, r_asi, r_mop);
2536 d32 = gen_dest_fpr_F(dc);
2537 tcg_gen_extrl_i64_i32(d32, d64);
2538 tcg_temp_free_i64(d64);
2539 gen_store_fpr_F(dc, rd, d32);
f2fe396f
RH		 2540 break;
2541 case 8:
2542 gen_helper_ld_asi(cpu_fpr[rd / 2], cpu_env, addr, r_asi, r_mop);
2543 break;
2544 case 16:
cb21b4da
RH		 2545 d64 = tcg_temp_new_i64();
2546 gen_helper_ld_asi(d64, cpu_env, addr, r_asi, r_mop);
f2fe396f
RH		 2547 tcg_gen_addi_tl(addr, addr, 8);
2548 gen_helper_ld_asi(cpu_fpr[rd/2+1], cpu_env, addr, r_asi, r_mop);
cb21b4da
RH		 2549 tcg_gen_mov_i64(cpu_fpr[rd / 2], d64);
2550 tcg_temp_free_i64(d64);
f2fe396f
RH		 2551 break;
2552 default:
2553 g_assert_not_reached();
2554 }
2555 tcg_temp_free_i32(r_mop);
7ec1e5ea
RH		 2556 tcg_temp_free_i32(r_asi);
2557 }
2558 break;
2559 }
1a2fb1c0
BS		 2560}
2561
22e70060
RH		 2562static void gen_stf_asi(DisasContext *dc, TCGv addr,
2563 int insn, int size, int rd)
1a2fb1c0 2564{
f0913be0 2565 DisasASI da = get_asi(dc, insn, (size == 4 ? MO_TEUL : MO_TEQ));
7705091c 2566 TCGv_i32 d32;
1a2fb1c0 2567
7ec1e5ea
RH		 2568 switch (da.type) {
2569 case GET_ASI_EXCP:
2570 break;
7705091c
RH		 2571
2572 case GET_ASI_DIRECT:
2573 gen_address_mask(dc, addr);
2574 switch (size) {
2575 case 4:
2576 d32 = gen_load_fpr_F(dc, rd);
2577 tcg_gen_qemu_st_i32(d32, addr, da.mem_idx, da.memop);
2578 break;
2579 case 8:
cb21b4da
RH		 2580 tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx,
2581 da.memop | MO_ALIGN_4);
7705091c
RH		 2582 break;
2583 case 16:
cb21b4da
RH		 2584 /* Only 4-byte alignment required. However, it is legal for the
2585 cpu to signal the alignment fault, and the OS trap handler is
2586 required to fix it up. Requiring 16-byte alignment here avoids
2587 having to probe the second page before performing the first
2588 write. */
f939ffe5
RH		 2589 tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx,
2590 da.memop | MO_ALIGN_16);
7705091c
RH		 2591 tcg_gen_addi_tl(addr, addr, 8);
2592 tcg_gen_qemu_st_i64(cpu_fpr[rd/2+1], addr, da.mem_idx, da.memop);
2593 break;
2594 default:
2595 g_assert_not_reached();
2596 }
2597 break;
2598
ca5ce572
RH		 2599 case GET_ASI_BLOCK:
2600 /* Valid for stdfa on aligned registers only. */
2601 if (size == 8 && (rd & 7) == 0) {
80883227 2602 TCGMemOp memop;
ca5ce572
RH		 2603 TCGv eight;
2604 int i;
2605
ca5ce572
RH		 2606 gen_address_mask(dc, addr);
2607
80883227
RH		 2608 /* The first operation checks required alignment. */
2609 memop = da.memop | MO_ALIGN_64;
ca5ce572
RH		 2610 eight = tcg_const_tl(8);
2611 for (i = 0; ; ++i) {
2612 tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + i], addr,
80883227 2613 da.mem_idx, memop);
ca5ce572
RH		 2614 if (i == 7) {
2615 break;
2616 }
2617 tcg_gen_add_tl(addr, addr, eight);
80883227 2618 memop = da.memop;
ca5ce572
RH		 2619 }
2620 tcg_temp_free(eight);
2621 } else {
2622 gen_exception(dc, TT_ILL_INSN);
2623 }
2624 break;
2625
2626 case GET_ASI_SHORT:
2627 /* Valid for stdfa only. */
2628 if (size == 8) {
2629 gen_address_mask(dc, addr);
2630 tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx, da.memop);
2631 } else {
2632 gen_exception(dc, TT_ILL_INSN);
2633 }
2634 break;
2635
7ec1e5ea 2636 default:
f2fe396f
RH		 2637 /* According to the table in the UA2011 manual, the only
2638 other asis that are valid for ldfa/lddfa/ldqfa are
2639 the PST* asis, which aren't currently handled. */
2640 gen_exception(dc, TT_ILL_INSN);
7ec1e5ea
RH		 2641 break;
2642 }
1a2fb1c0
BS		 2643}
2644
e4dc0052 2645static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
1a2fb1c0 2646{
f0913be0 2647 DisasASI da = get_asi(dc, insn, MO_TEQ);
e4dc0052
RH		 2648 TCGv_i64 hi = gen_dest_gpr(dc, rd);
2649 TCGv_i64 lo = gen_dest_gpr(dc, rd + 1);
1a2fb1c0 2650
7ec1e5ea
RH		 2651 switch (da.type) {
2652 case GET_ASI_EXCP:
e4dc0052
RH		 2653 return;
2654
2655 case GET_ASI_DTWINX:
e4dc0052 2656 gen_address_mask(dc, addr);
80883227 2657 tcg_gen_qemu_ld_i64(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16);
e4dc0052
RH		 2658 tcg_gen_addi_tl(addr, addr, 8);
2659 tcg_gen_qemu_ld_i64(lo, addr, da.mem_idx, da.memop);
7ec1e5ea 2660 break;
e4dc0052
RH		 2661
2662 case GET_ASI_DIRECT:
2663 {
2664 TCGv_i64 tmp = tcg_temp_new_i64();
2665
2666 gen_address_mask(dc, addr);
2667 tcg_gen_qemu_ld_i64(tmp, addr, da.mem_idx, da.memop);
2668
2669 /* Note that LE ldda acts as if each 32-bit register
2670 result is byte swapped. Having just performed one
2671 64-bit bswap, we need now to swap the writebacks. */
2672 if ((da.memop & MO_BSWAP) == MO_TE) {
2673 tcg_gen_extr32_i64(lo, hi, tmp);
2674 } else {
2675 tcg_gen_extr32_i64(hi, lo, tmp);
2676 }
2677 tcg_temp_free_i64(tmp);
2678 }
2679 break;
2680
7ec1e5ea 2681 default:
918d9a2c
RH		 2682 /* ??? In theory we've handled all of the ASIs that are valid
2683 for ldda, and this should raise DAE_invalid_asi. However,
2684 real hardware allows others. This can be seen with e.g.
2685 FreeBSD 10.3 wrt ASI_IC_TAG. */
7ec1e5ea
RH		 2686 {
2687 TCGv_i32 r_asi = tcg_const_i32(da.asi);
918d9a2c
RH		 2688 TCGv_i32 r_mop = tcg_const_i32(da.memop);
2689 TCGv_i64 tmp = tcg_temp_new_i64();
7ec1e5ea
RH		 2690
2691 save_state(dc);
918d9a2c 2692 gen_helper_ld_asi(tmp, cpu_env, addr, r_asi, r_mop);
7ec1e5ea 2693 tcg_temp_free_i32(r_asi);
918d9a2c 2694 tcg_temp_free_i32(r_mop);
3f4288eb 2695
918d9a2c
RH		 2696 /* See above. */
2697 if ((da.memop & MO_BSWAP) == MO_TE) {
2698 tcg_gen_extr32_i64(lo, hi, tmp);
2699 } else {
2700 tcg_gen_extr32_i64(hi, lo, tmp);
2701 }
2702 tcg_temp_free_i64(tmp);
7ec1e5ea
RH		 2703 }
2704 break;
2705 }
e4dc0052
RH		 2706
2707 gen_store_gpr(dc, rd, hi);
2708 gen_store_gpr(dc, rd + 1, lo);
0425bee5
BS		 2709}
2710
22e70060
RH		 2711static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2712 int insn, int rd)
0425bee5 2713{
f0913be0 2714 DisasASI da = get_asi(dc, insn, MO_TEQ);
c7785e16 2715 TCGv lo = gen_load_gpr(dc, rd + 1);
a7ec4229 2716
7ec1e5ea
RH		 2717 switch (da.type) {
2718 case GET_ASI_EXCP:
2719 break;
e4dc0052
RH		 2720
2721 case GET_ASI_DTWINX:
e4dc0052 2722 gen_address_mask(dc, addr);
80883227 2723 tcg_gen_qemu_st_i64(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16);
e4dc0052
RH		 2724 tcg_gen_addi_tl(addr, addr, 8);
2725 tcg_gen_qemu_st_i64(lo, addr, da.mem_idx, da.memop);
2726 break;
2727
2728 case GET_ASI_DIRECT:
2729 {
2730 TCGv_i64 t64 = tcg_temp_new_i64();
2731
2732 /* Note that LE stda acts as if each 32-bit register result is
2733 byte swapped. We will perform one 64-bit LE store, so now
2734 we must swap the order of the construction. */
2735 if ((da.memop & MO_BSWAP) == MO_TE) {
2736 tcg_gen_concat32_i64(t64, lo, hi);
2737 } else {
2738 tcg_gen_concat32_i64(t64, hi, lo);
2739 }
2740 gen_address_mask(dc, addr);
2741 tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop);
2742 tcg_temp_free_i64(t64);
2743 }
2744 break;
2745
7ec1e5ea 2746 default:
918d9a2c
RH		 2747 /* ??? In theory we've handled all of the ASIs that are valid
2748 for stda, and this should raise DAE_invalid_asi. */
7ec1e5ea
RH		 2749 {
2750 TCGv_i32 r_asi = tcg_const_i32(da.asi);
918d9a2c
RH		 2751 TCGv_i32 r_mop = tcg_const_i32(da.memop);
2752 TCGv_i64 t64 = tcg_temp_new_i64();
7ec1e5ea 2753
918d9a2c
RH		 2754 /* See above. */
2755 if ((da.memop & MO_BSWAP) == MO_TE) {
2756 tcg_gen_concat32_i64(t64, lo, hi);
2757 } else {
2758 tcg_gen_concat32_i64(t64, hi, lo);
2759 }
7ec1e5ea 2760
918d9a2c 2761 save_state(dc);
6850811e
RH		 2762 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_mop);
2763 tcg_temp_free_i32(r_mop);
7ec1e5ea
RH		 2764 tcg_temp_free_i32(r_asi);
2765 tcg_temp_free_i64(t64);
2766 }
2767 break;
2768 }
1a2fb1c0
BS		 2769}
2770
7268adeb 2771static void gen_casx_asi(DisasContext *dc, TCGv addr, TCGv cmpv,
22e70060 2772 int insn, int rd)
1a2fb1c0 2773{
f0913be0 2774 DisasASI da = get_asi(dc, insn, MO_TEQ);
5a7267b6 2775 TCGv oldv;
1a2fb1c0 2776
7268adeb
RH		 2777 switch (da.type) {
2778 case GET_ASI_EXCP:
7ec1e5ea 2779 return;
7268adeb
RH		 2780 case GET_ASI_DIRECT:
2781 oldv = tcg_temp_new();
5a7267b6
RH		 2782 tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, gen_load_gpr(dc, rd),
2783 da.mem_idx, da.memop);
7268adeb
RH		 2784 gen_store_gpr(dc, rd, oldv);
2785 tcg_temp_free(oldv);
7268adeb
RH		 2786 break;
2787 default:
2788 /* ??? Should be DAE_invalid_asi. */
2789 gen_exception(dc, TT_DATA_ACCESS);
2790 break;
2791 }
1a2fb1c0
BS		 2792}
2793
2794#elif !defined(CONFIG_USER_ONLY)
e4dc0052 2795static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
1a2fb1c0 2796{
d2dc4069
RH		 2797 /* ??? Work around an apparent bug in Ubuntu gcc 4.8.2-10ubuntu2+12,
2798 whereby "rd + 1" elicits "error: array subscript is above array".
2799 Since we have already asserted that rd is even, the semantics
2800 are unchanged. */
7ec1e5ea 2801 TCGv lo = gen_dest_gpr(dc, rd | 1);
e4dc0052 2802 TCGv hi = gen_dest_gpr(dc, rd);
7ec1e5ea 2803 TCGv_i64 t64 = tcg_temp_new_i64();
f0913be0 2804 DisasASI da = get_asi(dc, insn, MO_TEQ);
7ec1e5ea
RH		 2805
2806 switch (da.type) {
2807 case GET_ASI_EXCP:
2808 tcg_temp_free_i64(t64);
2809 return;
e4dc0052
RH		 2810 case GET_ASI_DIRECT:
2811 gen_address_mask(dc, addr);
2812 tcg_gen_qemu_ld_i64(t64, addr, da.mem_idx, da.memop);
2813 break;
7ec1e5ea
RH		 2814 default:
2815 {
2816 TCGv_i32 r_asi = tcg_const_i32(da.asi);
6850811e 2817 TCGv_i32 r_mop = tcg_const_i32(MO_Q);
7ec1e5ea
RH		 2818
2819 save_state(dc);
6850811e
RH		 2820 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop);
2821 tcg_temp_free_i32(r_mop);
7ec1e5ea
RH		 2822 tcg_temp_free_i32(r_asi);
2823 }
2824 break;
2825 }
c7785e16 2826
7ec1e5ea 2827 tcg_gen_extr_i64_i32(lo, hi, t64);
1ec789ab 2828 tcg_temp_free_i64(t64);
7ec1e5ea 2829 gen_store_gpr(dc, rd | 1, lo);
c7785e16 2830 gen_store_gpr(dc, rd, hi);
0425bee5
BS		 2831}
2832
22e70060
RH		 2833static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2834 int insn, int rd)
0425bee5 2835{
f0913be0 2836 DisasASI da = get_asi(dc, insn, MO_TEQ);
c7785e16 2837 TCGv lo = gen_load_gpr(dc, rd + 1);
1ec789ab 2838 TCGv_i64 t64 = tcg_temp_new_i64();
a7ec4229 2839
1ec789ab 2840 tcg_gen_concat_tl_i64(t64, lo, hi);
7ec1e5ea
RH		 2841
2842 switch (da.type) {
2843 case GET_ASI_EXCP:
2844 break;
e4dc0052
RH		 2845 case GET_ASI_DIRECT:
2846 gen_address_mask(dc, addr);
2847 tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop);
2848 break;
34810610
RH		 2849 case GET_ASI_BFILL:
2850 /* Store 32 bytes of T64 to ADDR. */
2851 /* ??? The original qemu code suggests 8-byte alignment, dropping
2852 the low bits, but the only place I can see this used is in the
2853 Linux kernel with 32 byte alignment, which would make more sense
2854 as a cacheline-style operation. */
2855 {
2856 TCGv d_addr = tcg_temp_new();
2857 TCGv eight = tcg_const_tl(8);
2858 int i;
2859
2860 tcg_gen_andi_tl(d_addr, addr, -8);
2861 for (i = 0; i < 32; i += 8) {
2862 tcg_gen_qemu_st_i64(t64, d_addr, da.mem_idx, da.memop);
2863 tcg_gen_add_tl(d_addr, d_addr, eight);
2864 }
2865
2866 tcg_temp_free(d_addr);
2867 tcg_temp_free(eight);
2868 }
2869 break;
7ec1e5ea
RH		 2870 default:
2871 {
2872 TCGv_i32 r_asi = tcg_const_i32(da.asi);
6850811e 2873 TCGv_i32 r_mop = tcg_const_i32(MO_Q);
7ec1e5ea
RH		 2874
2875 save_state(dc);
6850811e
RH		 2876 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_mop);
2877 tcg_temp_free_i32(r_mop);
7ec1e5ea
RH		 2878 tcg_temp_free_i32(r_asi);
2879 }
2880 break;
2881 }
2882
1ec789ab 2883 tcg_temp_free_i64(t64);
1a2fb1c0
BS		 2884}
2885#endif
2886
9d1d4e34 2887static TCGv get_src1(DisasContext *dc, unsigned int insn)
9322a4bf 2888{
9d1d4e34
RH		 2889 unsigned int rs1 = GET_FIELD(insn, 13, 17);
2890 return gen_load_gpr(dc, rs1);
9322a4bf
BS		 2891}
2892
9d1d4e34 2893static TCGv get_src2(DisasContext *dc, unsigned int insn)
a49d9390 2894{
a49d9390 2895 if (IS_IMM) { /* immediate */
42a8aa83 2896 target_long simm = GET_FIELDs(insn, 19, 31);
9d1d4e34
RH		 2897 TCGv t = get_temp_tl(dc);
2898 tcg_gen_movi_tl(t, simm);
2899 return t;
2900 } else { /* register */
42a8aa83 2901 unsigned int rs2 = GET_FIELD(insn, 27, 31);
9d1d4e34 2902 return gen_load_gpr(dc, rs2);
a49d9390 2903 }
a49d9390
BS		 2904}
2905
8194f35a 2906#ifdef TARGET_SPARC64
7e480893
RH		 2907static void gen_fmovs(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2908{
2909 TCGv_i32 c32, zero, dst, s1, s2;
2910
2911 /* We have two choices here: extend the 32 bit data and use movcond_i64,
2912 or fold the comparison down to 32 bits and use movcond_i32. Choose
2913 the later. */
2914 c32 = tcg_temp_new_i32();
2915 if (cmp->is_bool) {
ecc7b3aa 2916 tcg_gen_extrl_i64_i32(c32, cmp->c1);
7e480893
RH		 2917 } else {
2918 TCGv_i64 c64 = tcg_temp_new_i64();
2919 tcg_gen_setcond_i64(cmp->cond, c64, cmp->c1, cmp->c2);
ecc7b3aa 2920 tcg_gen_extrl_i64_i32(c32, c64);
7e480893
RH		 2921 tcg_temp_free_i64(c64);
2922 }
2923
2924 s1 = gen_load_fpr_F(dc, rs);
2925 s2 = gen_load_fpr_F(dc, rd);
ba5f5179 2926 dst = gen_dest_fpr_F(dc);
7e480893
RH		 2927 zero = tcg_const_i32(0);
2928
2929 tcg_gen_movcond_i32(TCG_COND_NE, dst, c32, zero, s1, s2);
2930
2931 tcg_temp_free_i32(c32);
2932 tcg_temp_free_i32(zero);
2933 gen_store_fpr_F(dc, rd, dst);
2934}
2935
2936static void gen_fmovd(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2937{
3886b8a3 2938 TCGv_i64 dst = gen_dest_fpr_D(dc, rd);
7e480893
RH		 2939 tcg_gen_movcond_i64(cmp->cond, dst, cmp->c1, cmp->c2,
2940 gen_load_fpr_D(dc, rs),
2941 gen_load_fpr_D(dc, rd));
2942 gen_store_fpr_D(dc, rd, dst);
2943}
2944
2945static void gen_fmovq(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2946{
2947 int qd = QFPREG(rd);
2948 int qs = QFPREG(rs);
2949
2950 tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2], cmp->c1, cmp->c2,
2951 cpu_fpr[qs / 2], cpu_fpr[qd / 2]);
2952 tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2 + 1], cmp->c1, cmp->c2,
2953 cpu_fpr[qs / 2 + 1], cpu_fpr[qd / 2 + 1]);
2954
f9c816c0 2955 gen_update_fprs_dirty(dc, qd);
7e480893
RH		 2956}
2957
a2035e83 2958#ifndef CONFIG_USER_ONLY
1bcea73e 2959static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_env cpu_env)
8194f35a 2960{
b551ec04 2961 TCGv_i32 r_tl = tcg_temp_new_i32();
8194f35a
IK		 2962
2963 /* load env->tl into r_tl */
b551ec04 2964 tcg_gen_ld_i32(r_tl, cpu_env, offsetof(CPUSPARCState, tl));
8194f35a
IK		 2965
2966 /* tl = [0 ... MAXTL_MASK] where MAXTL_MASK must be power of 2 */
b551ec04 2967 tcg_gen_andi_i32(r_tl, r_tl, MAXTL_MASK);
8194f35a
IK		 2968
2969 /* calculate offset to current trap state from env->ts, reuse r_tl */
b551ec04 2970 tcg_gen_muli_i32(r_tl, r_tl, sizeof (trap_state));
c5f9864e 2971 tcg_gen_addi_ptr(r_tsptr, cpu_env, offsetof(CPUSPARCState, ts));
8194f35a
IK		 2972
2973 /* tsptr = env->ts[env->tl & MAXTL_MASK] */
b551ec04
JF		 2974 {
2975 TCGv_ptr r_tl_tmp = tcg_temp_new_ptr();
2976 tcg_gen_ext_i32_ptr(r_tl_tmp, r_tl);
2977 tcg_gen_add_ptr(r_tsptr, r_tsptr, r_tl_tmp);
bc57c114 2978 tcg_temp_free_ptr(r_tl_tmp);
b551ec04 2979 }
8194f35a 2980
b551ec04 2981 tcg_temp_free_i32(r_tl);
8194f35a 2982}
a2035e83 2983#endif
6c073553
RH		 2984
2985static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2,
2986 int width, bool cc, bool left)
2987{
2988 TCGv lo1, lo2, t1, t2;
2989 uint64_t amask, tabl, tabr;
2990 int shift, imask, omask;
2991
2992 if (cc) {
2993 tcg_gen_mov_tl(cpu_cc_src, s1);
2994 tcg_gen_mov_tl(cpu_cc_src2, s2);
2995 tcg_gen_sub_tl(cpu_cc_dst, s1, s2);
2996 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
2997 dc->cc_op = CC_OP_SUB;
2998 }
2999
3000 /* Theory of operation: there are two tables, left and right (not to
3001 be confused with the left and right versions of the opcode). These
3002 are indexed by the low 3 bits of the inputs. To make things "easy",
3003 these tables are loaded into two constants, TABL and TABR below.
3004 The operation index = (input & imask) << shift calculates the index
3005 into the constant, while val = (table >> index) & omask calculates
3006 the value we're looking for. */
3007 switch (width) {
3008 case 8:
3009 imask = 0x7;
3010 shift = 3;
3011 omask = 0xff;
3012 if (left) {
3013 tabl = 0x80c0e0f0f8fcfeffULL;
3014 tabr = 0xff7f3f1f0f070301ULL;
3015 } else {
3016 tabl = 0x0103070f1f3f7fffULL;
3017 tabr = 0xfffefcf8f0e0c080ULL;
3018 }
3019 break;
3020 case 16:
3021 imask = 0x6;
3022 shift = 1;
3023 omask = 0xf;
3024 if (left) {
3025 tabl = 0x8cef;
3026 tabr = 0xf731;
3027 } else {
3028 tabl = 0x137f;
3029 tabr = 0xfec8;
3030 }
3031 break;
3032 case 32:
3033 imask = 0x4;
3034 shift = 0;
3035 omask = 0x3;
3036 if (left) {
3037 tabl = (2 << 2) | 3;
3038 tabr = (3 << 2) | 1;
3039 } else {
3040 tabl = (1 << 2) | 3;
3041 tabr = (3 << 2) | 2;
3042 }
3043 break;
3044 default:
3045 abort();
3046 }
3047
3048 lo1 = tcg_temp_new();
3049 lo2 = tcg_temp_new();
3050 tcg_gen_andi_tl(lo1, s1, imask);
3051 tcg_gen_andi_tl(lo2, s2, imask);
3052 tcg_gen_shli_tl(lo1, lo1, shift);
3053 tcg_gen_shli_tl(lo2, lo2, shift);
3054
3055 t1 = tcg_const_tl(tabl);
3056 t2 = tcg_const_tl(tabr);
3057 tcg_gen_shr_tl(lo1, t1, lo1);
3058 tcg_gen_shr_tl(lo2, t2, lo2);
3059 tcg_gen_andi_tl(dst, lo1, omask);
3060 tcg_gen_andi_tl(lo2, lo2, omask);
3061
3062 amask = -8;
3063 if (AM_CHECK(dc)) {
3064 amask &= 0xffffffffULL;
3065 }
3066 tcg_gen_andi_tl(s1, s1, amask);
3067 tcg_gen_andi_tl(s2, s2, amask);
3068
3069 /* We want to compute
3070 dst = (s1 == s2 ? lo1 : lo1 & lo2).
3071 We've already done dst = lo1, so this reduces to
3072 dst &= (s1 == s2 ? -1 : lo2)
3073 Which we perform by
3074 lo2 |= -(s1 == s2)
3075 dst &= lo2
3076 */
3077 tcg_gen_setcond_tl(TCG_COND_EQ, t1, s1, s2);
3078 tcg_gen_neg_tl(t1, t1);
3079 tcg_gen_or_tl(lo2, lo2, t1);
3080 tcg_gen_and_tl(dst, dst, lo2);
3081
3082 tcg_temp_free(lo1);
3083 tcg_temp_free(lo2);
3084 tcg_temp_free(t1);
3085 tcg_temp_free(t2);
3086}
add545ab
RH		 3087
3088static void gen_alignaddr(TCGv dst, TCGv s1, TCGv s2, bool left)
3089{
3090 TCGv tmp = tcg_temp_new();
3091
3092 tcg_gen_add_tl(tmp, s1, s2);
3093 tcg_gen_andi_tl(dst, tmp, -8);
3094 if (left) {
3095 tcg_gen_neg_tl(tmp, tmp);
3096 }
3097 tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, tmp, 0, 3);
3098
3099 tcg_temp_free(tmp);
3100}
50c796f9
RH		 3101
3102static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2)
3103{
3104 TCGv t1, t2, shift;
3105
3106 t1 = tcg_temp_new();
3107 t2 = tcg_temp_new();
3108 shift = tcg_temp_new();
3109
3110 tcg_gen_andi_tl(shift, gsr, 7);
3111 tcg_gen_shli_tl(shift, shift, 3);
3112 tcg_gen_shl_tl(t1, s1, shift);
3113
3114 /* A shift of 64 does not produce 0 in TCG. Divide this into a
3115 shift of (up to 63) followed by a constant shift of 1. */
3116 tcg_gen_xori_tl(shift, shift, 63);
3117 tcg_gen_shr_tl(t2, s2, shift);
3118 tcg_gen_shri_tl(t2, t2, 1);
3119
3120 tcg_gen_or_tl(dst, t1, t2);
3121
3122 tcg_temp_free(t1);
3123 tcg_temp_free(t2);
3124 tcg_temp_free(shift);
3125}
8194f35a
IK		 3126#endif
3127
64a88d5d 3128#define CHECK_IU_FEATURE(dc, FEATURE) \
5578ceab 3129 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
64a88d5d
BS		 3130 goto illegal_insn;
3131#define CHECK_FPU_FEATURE(dc, FEATURE) \
5578ceab 3132 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
64a88d5d
BS		 3133 goto nfpu_insn;
3134
0bee699e 3135/* before an instruction, dc->pc must be static */
0184e266 3136static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
cf495bcf 3137{
0184e266 3138 unsigned int opc, rs1, rs2, rd;
a4273524 3139 TCGv cpu_src1, cpu_src2;
208ae657 3140 TCGv_i32 cpu_src1_32, cpu_src2_32, cpu_dst_32;
96eda024 3141 TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64;
67526b20 3142 target_long simm;
7a3f1944 3143
cf495bcf 3144 opc = GET_FIELD(insn, 0, 1);
cf495bcf 3145 rd = GET_FIELD(insn, 2, 6);
6ae20372 3146
cf495bcf 3147 switch (opc) {
0f8a249a
BS		 3148 case 0: /* branches/sethi */
3149 {
3150 unsigned int xop = GET_FIELD(insn, 7, 9);
3151 int32_t target;
3152 switch (xop) {
3475187d 3153#ifdef TARGET_SPARC64
0f8a249a
BS		 3154 case 0x1: /* V9 BPcc */
3155 {
3156 int cc;
3157
3158 target = GET_FIELD_SP(insn, 0, 18);
86f1f2ae 3159 target = sign_extend(target, 19);
0f8a249a
BS		 3160 target <<= 2;
3161 cc = GET_FIELD_SP(insn, 20, 21);
3162 if (cc == 0)
d4a288ef 3163 do_branch(dc, target, insn, 0);
0f8a249a 3164 else if (cc == 2)
d4a288ef 3165 do_branch(dc, target, insn, 1);
0f8a249a
BS		 3166 else
3167 goto illegal_insn;
3168 goto jmp_insn;
3169 }
3170 case 0x3: /* V9 BPr */
3171 {
3172 target = GET_FIELD_SP(insn, 0, 13) |
13846e70 3173 (GET_FIELD_SP(insn, 20, 21) << 14);
0f8a249a
BS		 3174 target = sign_extend(target, 16);
3175 target <<= 2;
9d1d4e34 3176 cpu_src1 = get_src1(dc, insn);
d4a288ef 3177 do_branch_reg(dc, target, insn, cpu_src1);
0f8a249a
BS		 3178 goto jmp_insn;
3179 }
3180 case 0x5: /* V9 FBPcc */
3181 {
3182 int cc = GET_FIELD_SP(insn, 20, 21);
5b12f1e8 3183 if (gen_trap_ifnofpu(dc)) {
a80dde08 3184 goto jmp_insn;
5b12f1e8 3185 }
0f8a249a
BS		 3186 target = GET_FIELD_SP(insn, 0, 18);
3187 target = sign_extend(target, 19);
3188 target <<= 2;
d4a288ef 3189 do_fbranch(dc, target, insn, cc);
0f8a249a
BS		 3190 goto jmp_insn;
3191 }
a4d17f19 3192#else
0f8a249a
BS		 3193 case 0x7: /* CBN+x */
3194 {
3195 goto ncp_insn;
3196 }
3197#endif
3198 case 0x2: /* BN+x */
3199 {
3200 target = GET_FIELD(insn, 10, 31);
3201 target = sign_extend(target, 22);
3202 target <<= 2;
d4a288ef 3203 do_branch(dc, target, insn, 0);
0f8a249a
BS		 3204 goto jmp_insn;
3205 }
3206 case 0x6: /* FBN+x */
3207 {
5b12f1e8 3208 if (gen_trap_ifnofpu(dc)) {
a80dde08 3209 goto jmp_insn;
5b12f1e8 3210 }
0f8a249a
BS		 3211 target = GET_FIELD(insn, 10, 31);
3212 target = sign_extend(target, 22);
3213 target <<= 2;
d4a288ef 3214 do_fbranch(dc, target, insn, 0);
0f8a249a
BS		 3215 goto jmp_insn;
3216 }
3217 case 0x4: /* SETHI */
97ea2859
RH		 3218 /* Special-case %g0 because that's the canonical nop. */
3219 if (rd) {
0f8a249a 3220 uint32_t value = GET_FIELD(insn, 10, 31);
97ea2859
RH		 3221 TCGv t = gen_dest_gpr(dc, rd);
3222 tcg_gen_movi_tl(t, value << 10);
3223 gen_store_gpr(dc, rd, t);
0f8a249a 3224 }
0f8a249a
BS		 3225 break;
3226 case 0x0: /* UNIMPL */
3227 default:
3475187d 3228 goto illegal_insn;
0f8a249a
BS		 3229 }
3230 break;
3231 }
3232 break;
dc1a6971
BS		 3233 case 1: /*CALL*/
3234 {
0f8a249a 3235 target_long target = GET_FIELDs(insn, 2, 31) << 2;
97ea2859 3236 TCGv o7 = gen_dest_gpr(dc, 15);
cf495bcf 3237
97ea2859
RH		 3238 tcg_gen_movi_tl(o7, dc->pc);
3239 gen_store_gpr(dc, 15, o7);
0f8a249a 3240 target += dc->pc;
13a6dd00 3241 gen_mov_pc_npc(dc);
22036a49
AT		 3242#ifdef TARGET_SPARC64
3243 if (unlikely(AM_CHECK(dc))) {
3244 target &= 0xffffffffULL;
3245 }
3246#endif
0f8a249a
BS		 3247 dc->npc = target;
3248 }
3249 goto jmp_insn;
3250 case 2: /* FPU & Logical Operations */
3251 {
3252 unsigned int xop = GET_FIELD(insn, 7, 12);
e7d51b34 3253 TCGv cpu_dst = get_temp_tl(dc);
de9e9d9f 3254 TCGv cpu_tmp0;
5793f2a4 3255
0f8a249a 3256 if (xop == 0x3a) { /* generate trap */
bd49ed41
RH		 3257 int cond = GET_FIELD(insn, 3, 6);
3258 TCGv_i32 trap;
42a268c2
RH		 3259 TCGLabel *l1 = NULL;
3260 int mask;
3475187d 3261
bd49ed41
RH		 3262 if (cond == 0) {
3263 /* Trap never. */
3264 break;
cf495bcf 3265 }
b04d9890 3266
bd49ed41 3267 save_state(dc);
b04d9890 3268
bd49ed41
RH		 3269 if (cond != 8) {
3270 /* Conditional trap. */
3a49e759 3271 DisasCompare cmp;
3475187d 3272#ifdef TARGET_SPARC64
0f8a249a
BS		 3273 /* V9 icc/xcc */
3274 int cc = GET_FIELD_SP(insn, 11, 12);
3a49e759
RH		 3275 if (cc == 0) {
3276 gen_compare(&cmp, 0, cond, dc);
3277 } else if (cc == 2) {
3278 gen_compare(&cmp, 1, cond, dc);
3279 } else {
0f8a249a 3280 goto illegal_insn;
3a49e759 3281 }
3475187d 3282#else
3a49e759 3283 gen_compare(&cmp, 0, cond, dc);
3475187d 3284#endif
b158a785 3285 l1 = gen_new_label();
3a49e759
RH		 3286 tcg_gen_brcond_tl(tcg_invert_cond(cmp.cond),
3287 cmp.c1, cmp.c2, l1);
3288 free_compare(&cmp);
bd49ed41 3289 }
b158a785 3290
bd49ed41
RH		 3291 mask = ((dc->def->features & CPU_FEATURE_HYPV) && supervisor(dc)
3292 ? UA2005_HTRAP_MASK : V8_TRAP_MASK);
3293
3294 /* Don't use the normal temporaries, as they may well have
3295 gone out of scope with the branch above. While we're
3296 doing that we might as well pre-truncate to 32-bit. */
3297 trap = tcg_temp_new_i32();
3298
3299 rs1 = GET_FIELD_SP(insn, 14, 18);
3300 if (IS_IMM) {
3301 rs2 = GET_FIELD_SP(insn, 0, 6);
3302 if (rs1 == 0) {
3303 tcg_gen_movi_i32(trap, (rs2 & mask) + TT_TRAP);
3304 /* Signal that the trap value is fully constant. */
3305 mask = 0;
3306 } else {
97ea2859 3307 TCGv t1 = gen_load_gpr(dc, rs1);
bd49ed41 3308 tcg_gen_trunc_tl_i32(trap, t1);
bd49ed41
RH		 3309 tcg_gen_addi_i32(trap, trap, rs2);
3310 }
3311 } else {
97ea2859 3312 TCGv t1, t2;
bd49ed41 3313 rs2 = GET_FIELD_SP(insn, 0, 4);
97ea2859
RH		 3314 t1 = gen_load_gpr(dc, rs1);
3315 t2 = gen_load_gpr(dc, rs2);
bd49ed41
RH		 3316 tcg_gen_add_tl(t1, t1, t2);
3317 tcg_gen_trunc_tl_i32(trap, t1);
bd49ed41
RH		 3318 }
3319 if (mask != 0) {
3320 tcg_gen_andi_i32(trap, trap, mask);
3321 tcg_gen_addi_i32(trap, trap, TT_TRAP);
3322 }
3323
3324 gen_helper_raise_exception(cpu_env, trap);
3325 tcg_temp_free_i32(trap);
b158a785 3326
fe1755cb
RH		 3327 if (cond == 8) {
3328 /* An unconditional trap ends the TB. */
3329 dc->is_br = 1;
3330 goto jmp_insn;
3331 } else {
3332 /* A conditional trap falls through to the next insn. */
b158a785 3333 gen_set_label(l1);
fe1755cb 3334 break;
cf495bcf
FB		 3335 }
3336 } else if (xop == 0x28) {
3337 rs1 = GET_FIELD(insn, 13, 17);
3338 switch(rs1) {
3339 case 0: /* rdy */
65fe7b09
BS		 3340#ifndef TARGET_SPARC64
3341 case 0x01 ... 0x0e: /* undefined in the SPARCv8
3342 manual, rdy on the microSPARC
3343 II */
3344 case 0x0f: /* stbar in the SPARCv8 manual,
3345 rdy on the microSPARC II */
3346 case 0x10 ... 0x1f: /* implementation-dependent in the
3347 SPARCv8 manual, rdy on the
3348 microSPARC II */
4a2ba232
FC		 3349 /* Read Asr17 */
3350 if (rs1 == 0x11 && dc->def->features & CPU_FEATURE_ASR17) {
97ea2859 3351 TCGv t = gen_dest_gpr(dc, rd);
4a2ba232 3352 /* Read Asr17 for a Leon3 monoprocessor */
97ea2859
RH		 3353 tcg_gen_movi_tl(t, (1 << 8) | (dc->def->nwindows - 1));
3354 gen_store_gpr(dc, rd, t);
4a2ba232
FC		 3355 break;
3356 }
65fe7b09 3357#endif
97ea2859 3358 gen_store_gpr(dc, rd, cpu_y);
cf495bcf 3359 break;
3475187d 3360#ifdef TARGET_SPARC64
0f8a249a 3361 case 0x2: /* V9 rdccr */
20132b96 3362 update_psr(dc);
063c3675 3363 gen_helper_rdccr(cpu_dst, cpu_env);
97ea2859 3364 gen_store_gpr(dc, rd, cpu_dst);
3475187d 3365 break;
0f8a249a 3366 case 0x3: /* V9 rdasi */
a6d567e5 3367 tcg_gen_movi_tl(cpu_dst, dc->asi);
97ea2859 3368 gen_store_gpr(dc, rd, cpu_dst);
3475187d 3369 break;
0f8a249a 3370 case 0x4: /* V9 rdtick */
ccd4a219 3371 {
a7812ae4 3372 TCGv_ptr r_tickptr;
c9a46442 3373 TCGv_i32 r_const;
ccd4a219 3374
a7812ae4 3375 r_tickptr = tcg_temp_new_ptr();
c9a46442 3376 r_const = tcg_const_i32(dc->mem_idx);
ccd4a219 3377 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3378 offsetof(CPUSPARCState, tick));
c9a46442
MCA		 3379 gen_helper_tick_get_count(cpu_dst, cpu_env, r_tickptr,
3380 r_const);
a7812ae4 3381 tcg_temp_free_ptr(r_tickptr);
c9a46442 3382 tcg_temp_free_i32(r_const);
97ea2859 3383 gen_store_gpr(dc, rd, cpu_dst);
ccd4a219 3384 }
3475187d 3385 break;
0f8a249a 3386 case 0x5: /* V9 rdpc */
2ea815ca 3387 {
97ea2859 3388 TCGv t = gen_dest_gpr(dc, rd);
22036a49 3389 if (unlikely(AM_CHECK(dc))) {
97ea2859 3390 tcg_gen_movi_tl(t, dc->pc & 0xffffffffULL);
22036a49 3391 } else {
97ea2859 3392 tcg_gen_movi_tl(t, dc->pc);
22036a49 3393 }
97ea2859 3394 gen_store_gpr(dc, rd, t);
2ea815ca 3395 }
0f8a249a
BS		 3396 break;
3397 case 0x6: /* V9 rdfprs */
255e1fcb 3398 tcg_gen_ext_i32_tl(cpu_dst, cpu_fprs);
97ea2859 3399 gen_store_gpr(dc, rd, cpu_dst);
3475187d 3400 break;
65fe7b09
BS		 3401 case 0xf: /* V9 membar */
3402 break; /* no effect */
0f8a249a 3403 case 0x13: /* Graphics Status */
5b12f1e8 3404 if (gen_trap_ifnofpu(dc)) {
725cb90b 3405 goto jmp_insn;
5b12f1e8 3406 }
97ea2859 3407 gen_store_gpr(dc, rd, cpu_gsr);
725cb90b 3408 break;
9d926598 3409 case 0x16: /* Softint */
e86ceb0d
RH		 3410 tcg_gen_ld32s_tl(cpu_dst, cpu_env,
3411 offsetof(CPUSPARCState, softint));
97ea2859 3412 gen_store_gpr(dc, rd, cpu_dst);
9d926598 3413 break;
0f8a249a 3414 case 0x17: /* Tick compare */
97ea2859 3415 gen_store_gpr(dc, rd, cpu_tick_cmpr);
83469015 3416 break;
0f8a249a 3417 case 0x18: /* System tick */
ccd4a219 3418 {
a7812ae4 3419 TCGv_ptr r_tickptr;
c9a46442 3420 TCGv_i32 r_const;
ccd4a219 3421
a7812ae4 3422 r_tickptr = tcg_temp_new_ptr();
c9a46442 3423 r_const = tcg_const_i32(dc->mem_idx);
ccd4a219 3424 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3425 offsetof(CPUSPARCState, stick));
c9a46442
MCA		 3426 gen_helper_tick_get_count(cpu_dst, cpu_env, r_tickptr,
3427 r_const);
a7812ae4 3428 tcg_temp_free_ptr(r_tickptr);
c9a46442 3429 tcg_temp_free_i32(r_const);
97ea2859 3430 gen_store_gpr(dc, rd, cpu_dst);
ccd4a219 3431 }
83469015 3432 break;
0f8a249a 3433 case 0x19: /* System tick compare */
97ea2859 3434 gen_store_gpr(dc, rd, cpu_stick_cmpr);
83469015 3435 break;
b8e31b3c
AT		 3436 case 0x1a: /* UltraSPARC-T1 Strand status */
3437 /* XXX HYPV check maybe not enough, UA2005 & UA2007 describe
3438 * this ASR as impl. dep
3439 */
3440 CHECK_IU_FEATURE(dc, HYPV);
3441 {
3442 TCGv t = gen_dest_gpr(dc, rd);
3443 tcg_gen_movi_tl(t, 1UL);
3444 gen_store_gpr(dc, rd, t);
3445 }
3446 break;
0f8a249a
BS		 3447 case 0x10: /* Performance Control */
3448 case 0x11: /* Performance Instrumentation Counter */
3449 case 0x12: /* Dispatch Control */
3450 case 0x14: /* Softint set, WO */
3451 case 0x15: /* Softint clear, WO */
3475187d
FB		 3452#endif
3453 default:
cf495bcf
FB		 3454 goto illegal_insn;
3455 }
e8af50a3 3456#if !defined(CONFIG_USER_ONLY)
e9ebed4d 3457 } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
3475187d 3458#ifndef TARGET_SPARC64
20132b96 3459 if (!supervisor(dc)) {
0f8a249a 3460 goto priv_insn;
20132b96
RH		 3461 }
3462 update_psr(dc);
063c3675 3463 gen_helper_rdpsr(cpu_dst, cpu_env);
e9ebed4d 3464#else
fb79ceb9 3465 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 3466 if (!hypervisor(dc))
3467 goto priv_insn;
3468 rs1 = GET_FIELD(insn, 13, 17);
3469 switch (rs1) {
3470 case 0: // hpstate
3471 // gen_op_rdhpstate();
3472 break;
3473 case 1: // htstate
3474 // gen_op_rdhtstate();
3475 break;
3476 case 3: // hintp
255e1fcb 3477 tcg_gen_mov_tl(cpu_dst, cpu_hintp);
e9ebed4d
BS		 3478 break;
3479 case 5: // htba
255e1fcb 3480 tcg_gen_mov_tl(cpu_dst, cpu_htba);
e9ebed4d
BS		 3481 break;
3482 case 6: // hver
255e1fcb 3483 tcg_gen_mov_tl(cpu_dst, cpu_hver);
e9ebed4d
BS		 3484 break;
3485 case 31: // hstick_cmpr
255e1fcb 3486 tcg_gen_mov_tl(cpu_dst, cpu_hstick_cmpr);
e9ebed4d
BS		 3487 break;
3488 default:
3489 goto illegal_insn;
3490 }
3491#endif
97ea2859 3492 gen_store_gpr(dc, rd, cpu_dst);
e8af50a3 3493 break;
3475187d 3494 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
de9e9d9f 3495 if (!supervisor(dc)) {
0f8a249a 3496 goto priv_insn;
de9e9d9f
RH		 3497 }
3498 cpu_tmp0 = get_temp_tl(dc);
3475187d
FB		 3499#ifdef TARGET_SPARC64
3500 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 3501 switch (rs1) {
3502 case 0: // tpc
375ee38b 3503 {
a7812ae4 3504 TCGv_ptr r_tsptr;
375ee38b 3505
a7812ae4 3506 r_tsptr = tcg_temp_new_ptr();
8194f35a 3507 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
a7812ae4 3508 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 3509 offsetof(trap_state, tpc));
a7812ae4 3510 tcg_temp_free_ptr(r_tsptr);
375ee38b 3511 }
0f8a249a
BS		 3512 break;
3513 case 1: // tnpc
375ee38b 3514 {
a7812ae4 3515 TCGv_ptr r_tsptr;
375ee38b 3516
a7812ae4 3517 r_tsptr = tcg_temp_new_ptr();
8194f35a 3518 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 3519 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 3520 offsetof(trap_state, tnpc));
a7812ae4 3521 tcg_temp_free_ptr(r_tsptr);
375ee38b 3522 }
0f8a249a
BS		 3523 break;
3524 case 2: // tstate
375ee38b 3525 {
a7812ae4 3526 TCGv_ptr r_tsptr;
375ee38b 3527
a7812ae4 3528 r_tsptr = tcg_temp_new_ptr();
8194f35a 3529 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 3530 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 3531 offsetof(trap_state, tstate));
a7812ae4 3532 tcg_temp_free_ptr(r_tsptr);
375ee38b 3533 }
0f8a249a
BS		 3534 break;
3535 case 3: // tt
375ee38b 3536 {
45778f99 3537 TCGv_ptr r_tsptr = tcg_temp_new_ptr();
375ee38b 3538
8194f35a 3539 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
45778f99
RH		 3540 tcg_gen_ld32s_tl(cpu_tmp0, r_tsptr,
3541 offsetof(trap_state, tt));
a7812ae4 3542 tcg_temp_free_ptr(r_tsptr);
375ee38b 3543 }
0f8a249a
BS		 3544 break;
3545 case 4: // tick
ccd4a219 3546 {
a7812ae4 3547 TCGv_ptr r_tickptr;
c9a46442 3548 TCGv_i32 r_const;
ccd4a219 3549
a7812ae4 3550 r_tickptr = tcg_temp_new_ptr();
c9a46442 3551 r_const = tcg_const_i32(dc->mem_idx);
ccd4a219 3552 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3553 offsetof(CPUSPARCState, tick));
c9a46442
MCA		 3554 gen_helper_tick_get_count(cpu_tmp0, cpu_env,
3555 r_tickptr, r_const);
a7812ae4 3556 tcg_temp_free_ptr(r_tickptr);
c9a46442 3557 tcg_temp_free_i32(r_const);
ccd4a219 3558 }
0f8a249a
BS		 3559 break;
3560 case 5: // tba
255e1fcb 3561 tcg_gen_mov_tl(cpu_tmp0, cpu_tbr);
0f8a249a
BS		 3562 break;
3563 case 6: // pstate
45778f99
RH		 3564 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3565 offsetof(CPUSPARCState, pstate));
0f8a249a
BS		 3566 break;
3567 case 7: // tl
45778f99
RH		 3568 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3569 offsetof(CPUSPARCState, tl));
0f8a249a
BS		 3570 break;
3571 case 8: // pil
45778f99
RH		 3572 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3573 offsetof(CPUSPARCState, psrpil));
0f8a249a
BS		 3574 break;
3575 case 9: // cwp
063c3675 3576 gen_helper_rdcwp(cpu_tmp0, cpu_env);
0f8a249a
BS		 3577 break;
3578 case 10: // cansave
45778f99
RH		 3579 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3580 offsetof(CPUSPARCState, cansave));
0f8a249a
BS		 3581 break;
3582 case 11: // canrestore
45778f99
RH		 3583 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3584 offsetof(CPUSPARCState, canrestore));
0f8a249a
BS		 3585 break;
3586 case 12: // cleanwin
45778f99
RH		 3587 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3588 offsetof(CPUSPARCState, cleanwin));
0f8a249a
BS		 3589 break;
3590 case 13: // otherwin
45778f99
RH		 3591 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3592 offsetof(CPUSPARCState, otherwin));
0f8a249a
BS		 3593 break;
3594 case 14: // wstate
45778f99
RH		 3595 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3596 offsetof(CPUSPARCState, wstate));
0f8a249a 3597 break;
e9ebed4d 3598 case 16: // UA2005 gl
fb79ceb9 3599 CHECK_IU_FEATURE(dc, GL);
45778f99
RH		 3600 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3601 offsetof(CPUSPARCState, gl));
e9ebed4d
BS		 3602 break;
3603 case 26: // UA2005 strand status
fb79ceb9 3604 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 3605 if (!hypervisor(dc))
3606 goto priv_insn;
527067d8 3607 tcg_gen_mov_tl(cpu_tmp0, cpu_ssr);
e9ebed4d 3608 break;
0f8a249a 3609 case 31: // ver
255e1fcb 3610 tcg_gen_mov_tl(cpu_tmp0, cpu_ver);
0f8a249a
BS		 3611 break;
3612 case 15: // fq
3613 default:
3614 goto illegal_insn;
3615 }
3475187d 3616#else
255e1fcb 3617 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_wim);
3475187d 3618#endif
97ea2859 3619 gen_store_gpr(dc, rd, cpu_tmp0);
e8af50a3 3620 break;
3475187d
FB		 3621 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
3622#ifdef TARGET_SPARC64
063c3675 3623 gen_helper_flushw(cpu_env);
3475187d 3624#else
0f8a249a
BS		 3625 if (!supervisor(dc))
3626 goto priv_insn;
97ea2859 3627 gen_store_gpr(dc, rd, cpu_tbr);
3475187d 3628#endif
e8af50a3
FB		 3629 break;
3630#endif
0f8a249a 3631 } else if (xop == 0x34) { /* FPU Operations */
5b12f1e8 3632 if (gen_trap_ifnofpu(dc)) {
a80dde08 3633 goto jmp_insn;
5b12f1e8 3634 }
0f8a249a 3635 gen_op_clear_ieee_excp_and_FTT();
e8af50a3 3636 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 3637 rs2 = GET_FIELD(insn, 27, 31);
3638 xop = GET_FIELD(insn, 18, 26);
02c79d78 3639
0f8a249a 3640 switch (xop) {
dc1a6971 3641 case 0x1: /* fmovs */
208ae657
RH		 3642 cpu_src1_32 = gen_load_fpr_F(dc, rs2);
3643 gen_store_fpr_F(dc, rd, cpu_src1_32);
dc1a6971
BS		 3644 break;
3645 case 0x5: /* fnegs */
61f17f6e 3646 gen_ne_fop_FF(dc, rd, rs2, gen_helper_fnegs);
dc1a6971
BS		 3647 break;
3648 case 0x9: /* fabss */
61f17f6e 3649 gen_ne_fop_FF(dc, rd, rs2, gen_helper_fabss);
dc1a6971
BS		 3650 break;
3651 case 0x29: /* fsqrts */
3652 CHECK_FPU_FEATURE(dc, FSQRT);
61f17f6e 3653 gen_fop_FF(dc, rd, rs2, gen_helper_fsqrts);
dc1a6971
BS		 3654 break;
3655 case 0x2a: /* fsqrtd */
3656 CHECK_FPU_FEATURE(dc, FSQRT);
61f17f6e 3657 gen_fop_DD(dc, rd, rs2, gen_helper_fsqrtd);
dc1a6971
BS		 3658 break;
3659 case 0x2b: /* fsqrtq */
3660 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3661 gen_fop_QQ(dc, rd, rs2, gen_helper_fsqrtq);
dc1a6971
BS		 3662 break;
3663 case 0x41: /* fadds */
61f17f6e 3664 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fadds);
dc1a6971
BS		 3665 break;
3666 case 0x42: /* faddd */
61f17f6e 3667 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_faddd);
dc1a6971
BS		 3668 break;
3669 case 0x43: /* faddq */
3670 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3671 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_faddq);
dc1a6971
BS		 3672 break;
3673 case 0x45: /* fsubs */
61f17f6e 3674 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fsubs);
dc1a6971
BS		 3675 break;
3676 case 0x46: /* fsubd */
61f17f6e 3677 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fsubd);
dc1a6971
BS		 3678 break;
3679 case 0x47: /* fsubq */
3680 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3681 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fsubq);
dc1a6971
BS		 3682 break;
3683 case 0x49: /* fmuls */
3684 CHECK_FPU_FEATURE(dc, FMUL);
61f17f6e 3685 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fmuls);
dc1a6971
BS		 3686 break;
3687 case 0x4a: /* fmuld */
3688 CHECK_FPU_FEATURE(dc, FMUL);
61f17f6e 3689 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld);
dc1a6971
BS		 3690 break;
3691 case 0x4b: /* fmulq */
3692 CHECK_FPU_FEATURE(dc, FLOAT128);
3693 CHECK_FPU_FEATURE(dc, FMUL);
61f17f6e 3694 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fmulq);
dc1a6971
BS		 3695 break;
3696 case 0x4d: /* fdivs */
61f17f6e 3697 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fdivs);
dc1a6971
BS		 3698 break;
3699 case 0x4e: /* fdivd */
61f17f6e 3700 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fdivd);
dc1a6971
BS		 3701 break;
3702 case 0x4f: /* fdivq */
3703 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3704 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fdivq);
dc1a6971
BS		 3705 break;
3706 case 0x69: /* fsmuld */
3707 CHECK_FPU_FEATURE(dc, FSMULD);
61f17f6e 3708 gen_fop_DFF(dc, rd, rs1, rs2, gen_helper_fsmuld);
dc1a6971
BS		 3709 break;
3710 case 0x6e: /* fdmulq */
3711 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3712 gen_fop_QDD(dc, rd, rs1, rs2, gen_helper_fdmulq);
dc1a6971
BS		 3713 break;
3714 case 0xc4: /* fitos */
61f17f6e 3715 gen_fop_FF(dc, rd, rs2, gen_helper_fitos);
dc1a6971
BS		 3716 break;
3717 case 0xc6: /* fdtos */
61f17f6e 3718 gen_fop_FD(dc, rd, rs2, gen_helper_fdtos);
dc1a6971
BS		 3719 break;
3720 case 0xc7: /* fqtos */
3721 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3722 gen_fop_FQ(dc, rd, rs2, gen_helper_fqtos);
dc1a6971
BS		 3723 break;
3724 case 0xc8: /* fitod */
61f17f6e 3725 gen_ne_fop_DF(dc, rd, rs2, gen_helper_fitod);
dc1a6971
BS		 3726 break;
3727 case 0xc9: /* fstod */
61f17f6e 3728 gen_ne_fop_DF(dc, rd, rs2, gen_helper_fstod);
dc1a6971
BS		 3729 break;
3730 case 0xcb: /* fqtod */
3731 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3732 gen_fop_DQ(dc, rd, rs2, gen_helper_fqtod);
dc1a6971
BS		 3733 break;
3734 case 0xcc: /* fitoq */
3735 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3736 gen_ne_fop_QF(dc, rd, rs2, gen_helper_fitoq);
dc1a6971
BS		 3737 break;
3738 case 0xcd: /* fstoq */
3739 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3740 gen_ne_fop_QF(dc, rd, rs2, gen_helper_fstoq);
dc1a6971
BS		 3741 break;
3742 case 0xce: /* fdtoq */
3743 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3744 gen_ne_fop_QD(dc, rd, rs2, gen_helper_fdtoq);
dc1a6971
BS		 3745 break;
3746 case 0xd1: /* fstoi */
61f17f6e 3747 gen_fop_FF(dc, rd, rs2, gen_helper_fstoi);
dc1a6971
BS		 3748 break;
3749 case 0xd2: /* fdtoi */
61f17f6e 3750 gen_fop_FD(dc, rd, rs2, gen_helper_fdtoi);
dc1a6971
BS		 3751 break;
3752 case 0xd3: /* fqtoi */
3753 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3754 gen_fop_FQ(dc, rd, rs2, gen_helper_fqtoi);
dc1a6971 3755 break;
3475187d 3756#ifdef TARGET_SPARC64
dc1a6971 3757 case 0x2: /* V9 fmovd */
96eda024
RH		 3758 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
3759 gen_store_fpr_D(dc, rd, cpu_src1_64);
dc1a6971
BS		 3760 break;
3761 case 0x3: /* V9 fmovq */
3762 CHECK_FPU_FEATURE(dc, FLOAT128);
f9c816c0 3763 gen_move_Q(dc, rd, rs2);
dc1a6971
BS		 3764 break;
3765 case 0x6: /* V9 fnegd */
61f17f6e 3766 gen_ne_fop_DD(dc, rd, rs2, gen_helper_fnegd);
dc1a6971
BS		 3767 break;
3768 case 0x7: /* V9 fnegq */
3769 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3770 gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fnegq);
dc1a6971
BS		 3771 break;
3772 case 0xa: /* V9 fabsd */
61f17f6e 3773 gen_ne_fop_DD(dc, rd, rs2, gen_helper_fabsd);
dc1a6971
BS		 3774 break;
3775 case 0xb: /* V9 fabsq */
3776 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3777 gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fabsq);
dc1a6971
BS		 3778 break;
3779 case 0x81: /* V9 fstox */
61f17f6e 3780 gen_fop_DF(dc, rd, rs2, gen_helper_fstox);
dc1a6971
BS		 3781 break;
3782 case 0x82: /* V9 fdtox */
61f17f6e 3783 gen_fop_DD(dc, rd, rs2, gen_helper_fdtox);
dc1a6971
BS		 3784 break;
3785 case 0x83: /* V9 fqtox */
3786 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3787 gen_fop_DQ(dc, rd, rs2, gen_helper_fqtox);
dc1a6971
BS		 3788 break;
3789 case 0x84: /* V9 fxtos */
61f17f6e 3790 gen_fop_FD(dc, rd, rs2, gen_helper_fxtos);
dc1a6971
BS		 3791 break;
3792 case 0x88: /* V9 fxtod */
61f17f6e 3793 gen_fop_DD(dc, rd, rs2, gen_helper_fxtod);
dc1a6971
BS		 3794 break;
3795 case 0x8c: /* V9 fxtoq */
3796 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3797 gen_ne_fop_QD(dc, rd, rs2, gen_helper_fxtoq);
dc1a6971 3798 break;
0f8a249a 3799#endif
dc1a6971
BS		 3800 default:
3801 goto illegal_insn;
0f8a249a
BS		 3802 }
3803 } else if (xop == 0x35) { /* FPU Operations */
3475187d 3804#ifdef TARGET_SPARC64
0f8a249a 3805 int cond;
3475187d 3806#endif
5b12f1e8 3807 if (gen_trap_ifnofpu(dc)) {
a80dde08 3808 goto jmp_insn;
5b12f1e8 3809 }
0f8a249a 3810 gen_op_clear_ieee_excp_and_FTT();
cf495bcf 3811 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 3812 rs2 = GET_FIELD(insn, 27, 31);
3813 xop = GET_FIELD(insn, 18, 26);
dcf24905 3814
690995a6
RH		 3815#ifdef TARGET_SPARC64
3816#define FMOVR(sz) \
3817 do { \
3818 DisasCompare cmp; \
e7c8afb9 3819 cond = GET_FIELD_SP(insn, 10, 12); \
9d1d4e34 3820 cpu_src1 = get_src1(dc, insn); \
690995a6
RH		 3821 gen_compare_reg(&cmp, cond, cpu_src1); \
3822 gen_fmov##sz(dc, &cmp, rd, rs2); \
3823 free_compare(&cmp); \
3824 } while (0)
3825
3826 if ((xop & 0x11f) == 0x005) { /* V9 fmovsr */
3827 FMOVR(s);
0f8a249a
BS		 3828 break;
3829 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
690995a6 3830 FMOVR(d);
0f8a249a
BS		 3831 break;
3832 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
64a88d5d 3833 CHECK_FPU_FEATURE(dc, FLOAT128);
690995a6 3834 FMOVR(q);
1f587329 3835 break;
0f8a249a 3836 }
690995a6 3837#undef FMOVR
0f8a249a
BS		 3838#endif
3839 switch (xop) {
3475187d 3840#ifdef TARGET_SPARC64
7e480893
RH		 3841#define FMOVCC(fcc, sz) \
3842 do { \
3843 DisasCompare cmp; \
714547bb 3844 cond = GET_FIELD_SP(insn, 14, 17); \
7e480893
RH		 3845 gen_fcompare(&cmp, fcc, cond); \
3846 gen_fmov##sz(dc, &cmp, rd, rs2); \
3847 free_compare(&cmp); \
3848 } while (0)
3849
0f8a249a 3850 case 0x001: /* V9 fmovscc %fcc0 */
7e480893 3851 FMOVCC(0, s);
0f8a249a
BS		 3852 break;
3853 case 0x002: /* V9 fmovdcc %fcc0 */
7e480893 3854 FMOVCC(0, d);
0f8a249a
BS		 3855 break;
3856 case 0x003: /* V9 fmovqcc %fcc0 */
64a88d5d 3857 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3858 FMOVCC(0, q);
1f587329 3859 break;
0f8a249a 3860 case 0x041: /* V9 fmovscc %fcc1 */
7e480893 3861 FMOVCC(1, s);
0f8a249a
BS		 3862 break;
3863 case 0x042: /* V9 fmovdcc %fcc1 */
7e480893 3864 FMOVCC(1, d);
0f8a249a
BS		 3865 break;
3866 case 0x043: /* V9 fmovqcc %fcc1 */
64a88d5d 3867 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3868 FMOVCC(1, q);
1f587329 3869 break;
0f8a249a 3870 case 0x081: /* V9 fmovscc %fcc2 */
7e480893 3871 FMOVCC(2, s);
0f8a249a
BS		 3872 break;
3873 case 0x082: /* V9 fmovdcc %fcc2 */
7e480893 3874 FMOVCC(2, d);
0f8a249a
BS		 3875 break;
3876 case 0x083: /* V9 fmovqcc %fcc2 */
64a88d5d 3877 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3878 FMOVCC(2, q);
1f587329 3879 break;
0f8a249a 3880 case 0x0c1: /* V9 fmovscc %fcc3 */
7e480893 3881 FMOVCC(3, s);
0f8a249a
BS		 3882 break;
3883 case 0x0c2: /* V9 fmovdcc %fcc3 */
7e480893 3884 FMOVCC(3, d);
0f8a249a
BS		 3885 break;
3886 case 0x0c3: /* V9 fmovqcc %fcc3 */
64a88d5d 3887 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3888 FMOVCC(3, q);
1f587329 3889 break;
7e480893
RH		 3890#undef FMOVCC
3891#define FMOVCC(xcc, sz) \
3892 do { \
3893 DisasCompare cmp; \
714547bb 3894 cond = GET_FIELD_SP(insn, 14, 17); \
7e480893
RH		 3895 gen_compare(&cmp, xcc, cond, dc); \
3896 gen_fmov##sz(dc, &cmp, rd, rs2); \
3897 free_compare(&cmp); \
3898 } while (0)
19f329ad 3899
0f8a249a 3900 case 0x101: /* V9 fmovscc %icc */
7e480893 3901 FMOVCC(0, s);
0f8a249a
BS		 3902 break;
3903 case 0x102: /* V9 fmovdcc %icc */
7e480893 3904 FMOVCC(0, d);
b7d69dc2 3905 break;
0f8a249a 3906 case 0x103: /* V9 fmovqcc %icc */
64a88d5d 3907 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3908 FMOVCC(0, q);
1f587329 3909 break;
0f8a249a 3910 case 0x181: /* V9 fmovscc %xcc */
7e480893 3911 FMOVCC(1, s);
0f8a249a
BS		 3912 break;
3913 case 0x182: /* V9 fmovdcc %xcc */
7e480893 3914 FMOVCC(1, d);
0f8a249a
BS		 3915 break;
3916 case 0x183: /* V9 fmovqcc %xcc */
64a88d5d 3917 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3918 FMOVCC(1, q);
1f587329 3919 break;
7e480893 3920#undef FMOVCC
1f587329
BS		 3921#endif
3922 case 0x51: /* fcmps, V9 %fcc */
208ae657
RH		 3923 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
3924 cpu_src2_32 = gen_load_fpr_F(dc, rs2);
3925 gen_op_fcmps(rd & 3, cpu_src1_32, cpu_src2_32);
0f8a249a 3926 break;
1f587329 3927 case 0x52: /* fcmpd, V9 %fcc */
03fb8cfc
RH		 3928 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
3929 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
3930 gen_op_fcmpd(rd & 3, cpu_src1_64, cpu_src2_64);
0f8a249a 3931 break;
1f587329 3932 case 0x53: /* fcmpq, V9 %fcc */
64a88d5d 3933 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329
BS		 3934 gen_op_load_fpr_QT0(QFPREG(rs1));
3935 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 3936 gen_op_fcmpq(rd & 3);
1f587329 3937 break;
0f8a249a 3938 case 0x55: /* fcmpes, V9 %fcc */
208ae657
RH		 3939 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
3940 cpu_src2_32 = gen_load_fpr_F(dc, rs2);
3941 gen_op_fcmpes(rd & 3, cpu_src1_32, cpu_src2_32);
0f8a249a
BS		 3942 break;
3943 case 0x56: /* fcmped, V9 %fcc */
03fb8cfc
RH		 3944 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
3945 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
3946 gen_op_fcmped(rd & 3, cpu_src1_64, cpu_src2_64);
0f8a249a 3947 break;
1f587329 3948 case 0x57: /* fcmpeq, V9 %fcc */
64a88d5d 3949 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329
BS		 3950 gen_op_load_fpr_QT0(QFPREG(rs1));
3951 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 3952 gen_op_fcmpeq(rd & 3);
1f587329 3953 break;
0f8a249a
BS		 3954 default:
3955 goto illegal_insn;
3956 }
0f8a249a 3957 } else if (xop == 0x2) {
97ea2859 3958 TCGv dst = gen_dest_gpr(dc, rd);
e80cfcfc 3959 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a 3960 if (rs1 == 0) {
97ea2859 3961 /* clr/mov shortcut : or %g0, x, y -> mov x, y */
0f8a249a 3962 if (IS_IMM) { /* immediate */
67526b20 3963 simm = GET_FIELDs(insn, 19, 31);
97ea2859
RH		 3964 tcg_gen_movi_tl(dst, simm);
3965 gen_store_gpr(dc, rd, dst);
0f8a249a
BS		 3966 } else { /* register */
3967 rs2 = GET_FIELD(insn, 27, 31);
97ea2859
RH		 3968 if (rs2 == 0) {
3969 tcg_gen_movi_tl(dst, 0);
3970 gen_store_gpr(dc, rd, dst);
3971 } else {
3972 cpu_src2 = gen_load_gpr(dc, rs2);
3973 gen_store_gpr(dc, rd, cpu_src2);
3974 }
0f8a249a 3975 }
0f8a249a 3976 } else {
9d1d4e34 3977 cpu_src1 = get_src1(dc, insn);
0f8a249a 3978 if (IS_IMM) { /* immediate */
67526b20 3979 simm = GET_FIELDs(insn, 19, 31);
97ea2859
RH		 3980 tcg_gen_ori_tl(dst, cpu_src1, simm);
3981 gen_store_gpr(dc, rd, dst);
0f8a249a 3982 } else { /* register */
0f8a249a 3983 rs2 = GET_FIELD(insn, 27, 31);
97ea2859
RH		 3984 if (rs2 == 0) {
3985 /* mov shortcut: or x, %g0, y -> mov x, y */
3986 gen_store_gpr(dc, rd, cpu_src1);
3987 } else {
3988 cpu_src2 = gen_load_gpr(dc, rs2);
3989 tcg_gen_or_tl(dst, cpu_src1, cpu_src2);
3990 gen_store_gpr(dc, rd, dst);
3991 }
0f8a249a 3992 }
0f8a249a 3993 }
83469015 3994#ifdef TARGET_SPARC64
0f8a249a 3995 } else if (xop == 0x25) { /* sll, V9 sllx */
9d1d4e34 3996 cpu_src1 = get_src1(dc, insn);
0f8a249a 3997 if (IS_IMM) { /* immediate */
67526b20 3998 simm = GET_FIELDs(insn, 20, 31);
1a2fb1c0 3999 if (insn & (1 << 12)) {
67526b20 4000 tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x3f);
1a2fb1c0 4001 } else {
67526b20 4002 tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x1f);
1a2fb1c0 4003 }
0f8a249a 4004 } else { /* register */
83469015 4005 rs2 = GET_FIELD(insn, 27, 31);
97ea2859 4006 cpu_src2 = gen_load_gpr(dc, rs2);
de9e9d9f 4007 cpu_tmp0 = get_temp_tl(dc);
1a2fb1c0 4008 if (insn & (1 << 12)) {
6ae20372 4009 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
1a2fb1c0 4010 } else {
6ae20372 4011 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
1a2fb1c0 4012 }
01b1fa6d 4013 tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
83469015 4014 }
97ea2859 4015 gen_store_gpr(dc, rd, cpu_dst);
0f8a249a 4016 } else if (xop == 0x26) { /* srl, V9 srlx */
9d1d4e34 4017 cpu_src1 = get_src1(dc, insn);
0f8a249a 4018 if (IS_IMM) { /* immediate */
67526b20 4019 simm = GET_FIELDs(insn, 20, 31);
1a2fb1c0 4020 if (insn & (1 << 12)) {
67526b20 4021 tcg_gen_shri_i64(cpu_dst, cpu_src1, simm & 0x3f);
1a2fb1c0 4022 } else {
6ae20372 4023 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
67526b20 4024 tcg_gen_shri_i64(cpu_dst, cpu_dst, simm & 0x1f);
1a2fb1c0 4025 }
0f8a249a 4026 } else { /* register */
83469015 4027 rs2 = GET_FIELD(insn, 27, 31);
97ea2859 4028 cpu_src2 = gen_load_gpr(dc, rs2);
de9e9d9f 4029 cpu_tmp0 = get_temp_tl(dc);
1a2fb1c0 4030 if (insn & (1 << 12)) {
6ae20372
BS		 4031 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
4032 tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
1a2fb1c0 4033 } else {
6ae20372
BS		 4034 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
4035 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
4036 tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
1a2fb1c0 4037 }
83469015 4038 }
97ea2859 4039 gen_store_gpr(dc, rd, cpu_dst);
0f8a249a 4040 } else if (xop == 0x27) { /* sra, V9 srax */
9d1d4e34 4041 cpu_src1 = get_src1(dc, insn);
0f8a249a 4042 if (IS_IMM) { /* immediate */
67526b20 4043 simm = GET_FIELDs(insn, 20, 31);
1a2fb1c0 4044 if (insn & (1 << 12)) {
67526b20 4045 tcg_gen_sari_i64(cpu_dst, cpu_src1, simm & 0x3f);
1a2fb1c0 4046 } else {
97ea2859 4047 tcg_gen_ext32s_i64(cpu_dst, cpu_src1);
67526b20 4048 tcg_gen_sari_i64(cpu_dst, cpu_dst, simm & 0x1f);
1a2fb1c0 4049 }
0f8a249a 4050 } else { /* register */
83469015 4051 rs2 = GET_FIELD(insn, 27, 31);
97ea2859 4052 cpu_src2 = gen_load_gpr(dc, rs2);
de9e9d9f 4053 cpu_tmp0 = get_temp_tl(dc);
1a2fb1c0 4054 if (insn & (1 << 12)) {
6ae20372
BS		 4055 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
4056 tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
1a2fb1c0 4057 } else {
6ae20372 4058 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
97ea2859 4059 tcg_gen_ext32s_i64(cpu_dst, cpu_src1);
6ae20372 4060 tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
1a2fb1c0 4061 }
83469015 4062 }
97ea2859 4063 gen_store_gpr(dc, rd, cpu_dst);
e80cfcfc 4064#endif
fcc72045 4065 } else if (xop < 0x36) {
cf495bcf 4066 if (xop < 0x20) {
9d1d4e34
RH		 4067 cpu_src1 = get_src1(dc, insn);
4068 cpu_src2 = get_src2(dc, insn);
cf495bcf 4069 switch (xop & ~0x10) {
b89e94af 4070 case 0x0: /* add */
97ea2859
RH		 4071 if (xop & 0x10) {
4072 gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
4073 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
4074 dc->cc_op = CC_OP_ADD;
41d72852 4075 } else {
97ea2859 4076 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
41d72852 4077 }
cf495bcf 4078 break;
b89e94af 4079 case 0x1: /* and */
97ea2859 4080 tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
41d72852 4081 if (xop & 0x10) {
38482a77
BS		 4082 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4083 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4084 dc->cc_op = CC_OP_LOGIC;
41d72852 4085 }
cf495bcf 4086 break;
b89e94af 4087 case 0x2: /* or */
97ea2859 4088 tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 4089 if (xop & 0x10) {
38482a77
BS		 4090 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4091 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4092 dc->cc_op = CC_OP_LOGIC;
8393617c 4093 }
0f8a249a 4094 break;
b89e94af 4095 case 0x3: /* xor */
97ea2859 4096 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 4097 if (xop & 0x10) {
38482a77
BS		 4098 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4099 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4100 dc->cc_op = CC_OP_LOGIC;
8393617c 4101 }
cf495bcf 4102 break;
b89e94af 4103 case 0x4: /* sub */
97ea2859
RH		 4104 if (xop & 0x10) {
4105 gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
4106 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
4107 dc->cc_op = CC_OP_SUB;
41d72852 4108 } else {
97ea2859 4109 tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
41d72852 4110 }
cf495bcf 4111 break;
b89e94af 4112 case 0x5: /* andn */
97ea2859 4113 tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 4114 if (xop & 0x10) {
38482a77
BS		 4115 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4116 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4117 dc->cc_op = CC_OP_LOGIC;
8393617c 4118 }
cf495bcf 4119 break;
b89e94af 4120 case 0x6: /* orn */
97ea2859 4121 tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 4122 if (xop & 0x10) {
38482a77
BS		 4123 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4124 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4125 dc->cc_op = CC_OP_LOGIC;
8393617c 4126 }
cf495bcf 4127 break;
b89e94af 4128 case 0x7: /* xorn */
97ea2859 4129 tcg_gen_eqv_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 4130 if (xop & 0x10) {
38482a77
BS		 4131 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4132 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4133 dc->cc_op = CC_OP_LOGIC;
8393617c 4134 }
cf495bcf 4135 break;
b89e94af 4136 case 0x8: /* addx, V9 addc */
70c48285
RH		 4137 gen_op_addx_int(dc, cpu_dst, cpu_src1, cpu_src2,
4138 (xop & 0x10));
cf495bcf 4139 break;
ded3ab80 4140#ifdef TARGET_SPARC64
0f8a249a 4141 case 0x9: /* V9 mulx */
97ea2859 4142 tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
ded3ab80
PB		 4143 break;
4144#endif
b89e94af 4145 case 0xa: /* umul */
64a88d5d 4146 CHECK_IU_FEATURE(dc, MUL);
6ae20372 4147 gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
8393617c 4148 if (xop & 0x10) {
38482a77
BS		 4149 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4150 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4151 dc->cc_op = CC_OP_LOGIC;
8393617c 4152 }
cf495bcf 4153 break;
b89e94af 4154 case 0xb: /* smul */
64a88d5d 4155 CHECK_IU_FEATURE(dc, MUL);
6ae20372 4156 gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
8393617c 4157 if (xop & 0x10) {
38482a77
BS		 4158 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4159 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4160 dc->cc_op = CC_OP_LOGIC;
8393617c 4161 }
cf495bcf 4162 break;
b89e94af 4163 case 0xc: /* subx, V9 subc */
70c48285
RH		 4164 gen_op_subx_int(dc, cpu_dst, cpu_src1, cpu_src2,
4165 (xop & 0x10));
cf495bcf 4166 break;
ded3ab80 4167#ifdef TARGET_SPARC64
0f8a249a 4168 case 0xd: /* V9 udivx */
c28ae41e 4169 gen_helper_udivx(cpu_dst, cpu_env, cpu_src1, cpu_src2);
ded3ab80
PB		 4170 break;
4171#endif
b89e94af 4172 case 0xe: /* udiv */
64a88d5d 4173 CHECK_IU_FEATURE(dc, DIV);
8393617c 4174 if (xop & 0x10) {
7a5e4488
BS		 4175 gen_helper_udiv_cc(cpu_dst, cpu_env, cpu_src1,
4176 cpu_src2);
6c78ea32 4177 dc->cc_op = CC_OP_DIV;
0fcec41e 4178 } else {
7a5e4488
BS		 4179 gen_helper_udiv(cpu_dst, cpu_env, cpu_src1,
4180 cpu_src2);
8393617c 4181 }
cf495bcf 4182 break;
b89e94af 4183 case 0xf: /* sdiv */
64a88d5d 4184 CHECK_IU_FEATURE(dc, DIV);
8393617c 4185 if (xop & 0x10) {
7a5e4488
BS		 4186 gen_helper_sdiv_cc(cpu_dst, cpu_env, cpu_src1,
4187 cpu_src2);
6c78ea32 4188 dc->cc_op = CC_OP_DIV;
0fcec41e 4189 } else {
7a5e4488
BS		 4190 gen_helper_sdiv(cpu_dst, cpu_env, cpu_src1,
4191 cpu_src2);
8393617c 4192 }
cf495bcf
FB		 4193 break;
4194 default:
4195 goto illegal_insn;
4196 }
97ea2859 4197 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 4198 } else {
9d1d4e34
RH		 4199 cpu_src1 = get_src1(dc, insn);
4200 cpu_src2 = get_src2(dc, insn);
cf495bcf 4201 switch (xop) {
0f8a249a 4202 case 0x20: /* taddcc */
a2ea4aa9 4203 gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
97ea2859 4204 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92
BS		 4205 tcg_gen_movi_i32(cpu_cc_op, CC_OP_TADD);
4206 dc->cc_op = CC_OP_TADD;
0f8a249a
BS		 4207 break;
4208 case 0x21: /* tsubcc */
a2ea4aa9 4209 gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
97ea2859 4210 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92
BS		 4211 tcg_gen_movi_i32(cpu_cc_op, CC_OP_TSUB);
4212 dc->cc_op = CC_OP_TSUB;
0f8a249a
BS		 4213 break;
4214 case 0x22: /* taddcctv */
a2ea4aa9
RH		 4215 gen_helper_taddcctv(cpu_dst, cpu_env,
4216 cpu_src1, cpu_src2);
97ea2859 4217 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92 4218 dc->cc_op = CC_OP_TADDTV;
0f8a249a
BS		 4219 break;
4220 case 0x23: /* tsubcctv */
a2ea4aa9
RH		 4221 gen_helper_tsubcctv(cpu_dst, cpu_env,
4222 cpu_src1, cpu_src2);
97ea2859 4223 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92 4224 dc->cc_op = CC_OP_TSUBTV;
0f8a249a 4225 break;
cf495bcf 4226 case 0x24: /* mulscc */
20132b96 4227 update_psr(dc);
6ae20372 4228 gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
97ea2859 4229 gen_store_gpr(dc, rd, cpu_dst);
d084469c
BS		 4230 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
4231 dc->cc_op = CC_OP_ADD;
cf495bcf 4232 break;
83469015 4233#ifndef TARGET_SPARC64
0f8a249a 4234 case 0x25: /* sll */
e35298cd 4235 if (IS_IMM) { /* immediate */
67526b20
BS		 4236 simm = GET_FIELDs(insn, 20, 31);
4237 tcg_gen_shli_tl(cpu_dst, cpu_src1, simm & 0x1f);
e35298cd 4238 } else { /* register */
de9e9d9f 4239 cpu_tmp0 = get_temp_tl(dc);
e35298cd
BS		 4240 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
4241 tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
4242 }
97ea2859 4243 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 4244 break;
83469015 4245 case 0x26: /* srl */
e35298cd 4246 if (IS_IMM) { /* immediate */
67526b20
BS		 4247 simm = GET_FIELDs(insn, 20, 31);
4248 tcg_gen_shri_tl(cpu_dst, cpu_src1, simm & 0x1f);
e35298cd 4249 } else { /* register */
de9e9d9f 4250 cpu_tmp0 = get_temp_tl(dc);
e35298cd
BS		 4251 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
4252 tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
4253 }
97ea2859 4254 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 4255 break;
83469015 4256 case 0x27: /* sra */
e35298cd 4257 if (IS_IMM) { /* immediate */
67526b20
BS		 4258 simm = GET_FIELDs(insn, 20, 31);
4259 tcg_gen_sari_tl(cpu_dst, cpu_src1, simm & 0x1f);
e35298cd 4260 } else { /* register */
de9e9d9f 4261 cpu_tmp0 = get_temp_tl(dc);
e35298cd
BS		 4262 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
4263 tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
4264 }
97ea2859 4265 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 4266 break;
83469015 4267#endif
cf495bcf
FB		 4268 case 0x30:
4269 {
de9e9d9f 4270 cpu_tmp0 = get_temp_tl(dc);
cf495bcf 4271 switch(rd) {
3475187d 4272 case 0: /* wry */
5068cbd9
BS		 4273 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4274 tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
cf495bcf 4275 break;
65fe7b09
BS		 4276#ifndef TARGET_SPARC64
4277 case 0x01 ... 0x0f: /* undefined in the
4278 SPARCv8 manual, nop
4279 on the microSPARC
4280 II */
4281 case 0x10 ... 0x1f: /* implementation-dependent
4282 in the SPARCv8
4283 manual, nop on the
4284 microSPARC II */
d1c36ba7
RH		 4285 if ((rd == 0x13) && (dc->def->features &
4286 CPU_FEATURE_POWERDOWN)) {
4287 /* LEON3 power-down */
1cf892ca 4288 save_state(dc);
d1c36ba7
RH		 4289 gen_helper_power_down(cpu_env);
4290 }
65fe7b09
BS		 4291 break;
4292#else
0f8a249a 4293 case 0x2: /* V9 wrccr */
7b04bd5c
RH		 4294 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4295 gen_helper_wrccr(cpu_env, cpu_tmp0);
8393617c
BS		 4296 tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
4297 dc->cc_op = CC_OP_FLAGS;
0f8a249a
BS		 4298 break;
4299 case 0x3: /* V9 wrasi */
7b04bd5c
RH		 4300 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4301 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xff);
a6d567e5
RH		 4302 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4303 offsetof(CPUSPARCState, asi));
4304 /* End TB to notice changed ASI. */
4305 save_state(dc);
4306 gen_op_next_insn();
4307 tcg_gen_exit_tb(0);
4308 dc->is_br = 1;
0f8a249a
BS		 4309 break;
4310 case 0x6: /* V9 wrfprs */
7b04bd5c
RH		 4311 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4312 tcg_gen_trunc_tl_i32(cpu_fprs, cpu_tmp0);
f9c816c0 4313 dc->fprs_dirty = 0;
66442b07 4314 save_state(dc);
3299908c 4315 gen_op_next_insn();
57fec1fe 4316 tcg_gen_exit_tb(0);
3299908c 4317 dc->is_br = 1;
0f8a249a
BS		 4318 break;
4319 case 0xf: /* V9 sir, nop if user */
3475187d 4320#if !defined(CONFIG_USER_ONLY)
6ad6135d 4321 if (supervisor(dc)) {
1a2fb1c0 4322 ; // XXX
6ad6135d 4323 }
3475187d 4324#endif
0f8a249a
BS		 4325 break;
4326 case 0x13: /* Graphics Status */
5b12f1e8 4327 if (gen_trap_ifnofpu(dc)) {
725cb90b 4328 goto jmp_insn;
5b12f1e8 4329 }
255e1fcb 4330 tcg_gen_xor_tl(cpu_gsr, cpu_src1, cpu_src2);
0f8a249a 4331 break;
9d926598
BS		 4332 case 0x14: /* Softint set */
4333 if (!supervisor(dc))
4334 goto illegal_insn;
aeff993c
RH		 4335 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4336 gen_helper_set_softint(cpu_env, cpu_tmp0);
9d926598
BS		 4337 break;
4338 case 0x15: /* Softint clear */
4339 if (!supervisor(dc))
4340 goto illegal_insn;
aeff993c
RH		 4341 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4342 gen_helper_clear_softint(cpu_env, cpu_tmp0);
9d926598
BS		 4343 break;
4344 case 0x16: /* Softint write */
4345 if (!supervisor(dc))
4346 goto illegal_insn;
aeff993c
RH		 4347 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4348 gen_helper_write_softint(cpu_env, cpu_tmp0);
9d926598 4349 break;
0f8a249a 4350 case 0x17: /* Tick compare */
83469015 4351#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 4352 if (!supervisor(dc))
4353 goto illegal_insn;
83469015 4354#endif
ccd4a219 4355 {
a7812ae4 4356 TCGv_ptr r_tickptr;
ccd4a219 4357
255e1fcb 4358 tcg_gen_xor_tl(cpu_tick_cmpr, cpu_src1,
6ae20372 4359 cpu_src2);
a7812ae4 4360 r_tickptr = tcg_temp_new_ptr();
ccd4a219 4361 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 4362 offsetof(CPUSPARCState, tick));
a7812ae4
PB		 4363 gen_helper_tick_set_limit(r_tickptr,
4364 cpu_tick_cmpr);
4365 tcg_temp_free_ptr(r_tickptr);
ccd4a219 4366 }
0f8a249a
BS		 4367 break;
4368 case 0x18: /* System tick */
83469015 4369#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 4370 if (!supervisor(dc))
4371 goto illegal_insn;
83469015 4372#endif
ccd4a219 4373 {
a7812ae4 4374 TCGv_ptr r_tickptr;
ccd4a219 4375
7b04bd5c 4376 tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
6ae20372 4377 cpu_src2);
a7812ae4 4378 r_tickptr = tcg_temp_new_ptr();
ccd4a219 4379 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 4380 offsetof(CPUSPARCState, stick));
a7812ae4 4381 gen_helper_tick_set_count(r_tickptr,
7b04bd5c 4382 cpu_tmp0);
a7812ae4 4383 tcg_temp_free_ptr(r_tickptr);
ccd4a219 4384 }
0f8a249a
BS		 4385 break;
4386 case 0x19: /* System tick compare */
83469015 4387#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 4388 if (!supervisor(dc))
4389 goto illegal_insn;
3475187d 4390#endif
ccd4a219 4391 {
a7812ae4 4392 TCGv_ptr r_tickptr;
ccd4a219 4393
255e1fcb 4394 tcg_gen_xor_tl(cpu_stick_cmpr, cpu_src1,
6ae20372 4395 cpu_src2);
a7812ae4 4396 r_tickptr = tcg_temp_new_ptr();
ccd4a219 4397 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 4398 offsetof(CPUSPARCState, stick));
a7812ae4
PB		 4399 gen_helper_tick_set_limit(r_tickptr,
4400 cpu_stick_cmpr);
4401 tcg_temp_free_ptr(r_tickptr);
ccd4a219 4402 }
0f8a249a 4403 break;
83469015 4404
0f8a249a 4405 case 0x10: /* Performance Control */
77f193da
BS		 4406 case 0x11: /* Performance Instrumentation
4407 Counter */
0f8a249a 4408 case 0x12: /* Dispatch Control */
83469015 4409#endif
3475187d 4410 default:
cf495bcf
FB		 4411 goto illegal_insn;
4412 }
4413 }
4414 break;
e8af50a3 4415#if !defined(CONFIG_USER_ONLY)
af7bf89b 4416 case 0x31: /* wrpsr, V9 saved, restored */
e8af50a3 4417 {
0f8a249a
BS		 4418 if (!supervisor(dc))
4419 goto priv_insn;
3475187d 4420#ifdef TARGET_SPARC64
0f8a249a
BS		 4421 switch (rd) {
4422 case 0:
063c3675 4423 gen_helper_saved(cpu_env);
0f8a249a
BS		 4424 break;
4425 case 1:
063c3675 4426 gen_helper_restored(cpu_env);
0f8a249a 4427 break;
e9ebed4d
BS		 4428 case 2: /* UA2005 allclean */
4429 case 3: /* UA2005 otherw */
4430 case 4: /* UA2005 normalw */
4431 case 5: /* UA2005 invalw */
4432 // XXX
0f8a249a 4433 default:
3475187d
FB		 4434 goto illegal_insn;
4435 }
4436#else
de9e9d9f 4437 cpu_tmp0 = get_temp_tl(dc);
7b04bd5c
RH		 4438 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4439 gen_helper_wrpsr(cpu_env, cpu_tmp0);
8393617c
BS		 4440 tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
4441 dc->cc_op = CC_OP_FLAGS;
66442b07 4442 save_state(dc);
9e61bde5 4443 gen_op_next_insn();
57fec1fe 4444 tcg_gen_exit_tb(0);
0f8a249a 4445 dc->is_br = 1;
3475187d 4446#endif
e8af50a3
FB		 4447 }
4448 break;
af7bf89b 4449 case 0x32: /* wrwim, V9 wrpr */
e8af50a3 4450 {
0f8a249a
BS		 4451 if (!supervisor(dc))
4452 goto priv_insn;
de9e9d9f 4453 cpu_tmp0 = get_temp_tl(dc);
ece43b8d 4454 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3475187d 4455#ifdef TARGET_SPARC64
0f8a249a
BS		 4456 switch (rd) {
4457 case 0: // tpc
375ee38b 4458 {
a7812ae4 4459 TCGv_ptr r_tsptr;
375ee38b 4460
a7812ae4 4461 r_tsptr = tcg_temp_new_ptr();
8194f35a 4462 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 4463 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
375ee38b 4464 offsetof(trap_state, tpc));
a7812ae4 4465 tcg_temp_free_ptr(r_tsptr);
375ee38b 4466 }
0f8a249a
BS		 4467 break;
4468 case 1: // tnpc
375ee38b 4469 {
a7812ae4 4470 TCGv_ptr r_tsptr;
375ee38b 4471
a7812ae4 4472 r_tsptr = tcg_temp_new_ptr();
8194f35a 4473 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 4474 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
375ee38b 4475 offsetof(trap_state, tnpc));
a7812ae4 4476 tcg_temp_free_ptr(r_tsptr);
375ee38b 4477 }
0f8a249a
BS		 4478 break;
4479 case 2: // tstate
375ee38b 4480 {
a7812ae4 4481 TCGv_ptr r_tsptr;
375ee38b 4482
a7812ae4 4483 r_tsptr = tcg_temp_new_ptr();
8194f35a 4484 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 4485 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
77f193da
BS		 4486 offsetof(trap_state,
4487 tstate));
a7812ae4 4488 tcg_temp_free_ptr(r_tsptr);
375ee38b 4489 }
0f8a249a
BS		 4490 break;
4491 case 3: // tt
375ee38b 4492 {
a7812ae4 4493 TCGv_ptr r_tsptr;
375ee38b 4494
a7812ae4 4495 r_tsptr = tcg_temp_new_ptr();
8194f35a 4496 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
7b9e066b
RH		 4497 tcg_gen_st32_tl(cpu_tmp0, r_tsptr,
4498 offsetof(trap_state, tt));
a7812ae4 4499 tcg_temp_free_ptr(r_tsptr);
375ee38b 4500 }
0f8a249a
BS		 4501 break;
4502 case 4: // tick
ccd4a219 4503 {
a7812ae4 4504 TCGv_ptr r_tickptr;
ccd4a219 4505
a7812ae4 4506 r_tickptr = tcg_temp_new_ptr();
ccd4a219 4507 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 4508 offsetof(CPUSPARCState, tick));
a7812ae4
PB		 4509 gen_helper_tick_set_count(r_tickptr,
4510 cpu_tmp0);
4511 tcg_temp_free_ptr(r_tickptr);
ccd4a219 4512 }
0f8a249a
BS		 4513 break;
4514 case 5: // tba
255e1fcb 4515 tcg_gen_mov_tl(cpu_tbr, cpu_tmp0);
0f8a249a
BS		 4516 break;
4517 case 6: // pstate
6234ac09
RH		 4518 save_state(dc);
4519 gen_helper_wrpstate(cpu_env, cpu_tmp0);
4520 dc->npc = DYNAMIC_PC;
0f8a249a
BS		 4521 break;
4522 case 7: // tl
6234ac09 4523 save_state(dc);
7b9e066b 4524 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
6234ac09
RH		 4525 offsetof(CPUSPARCState, tl));
4526 dc->npc = DYNAMIC_PC;
0f8a249a
BS		 4527 break;
4528 case 8: // pil
063c3675 4529 gen_helper_wrpil(cpu_env, cpu_tmp0);
0f8a249a
BS		 4530 break;
4531 case 9: // cwp
063c3675 4532 gen_helper_wrcwp(cpu_env, cpu_tmp0);
0f8a249a
BS		 4533 break;
4534 case 10: // cansave
7b9e066b
RH		 4535 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4536 offsetof(CPUSPARCState,
4537 cansave));
0f8a249a
BS		 4538 break;
4539 case 11: // canrestore
7b9e066b
RH		 4540 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4541 offsetof(CPUSPARCState,
4542 canrestore));
0f8a249a
BS		 4543 break;
4544 case 12: // cleanwin
7b9e066b
RH		 4545 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4546 offsetof(CPUSPARCState,
4547 cleanwin));
0f8a249a
BS		 4548 break;
4549 case 13: // otherwin
7b9e066b
RH		 4550 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4551 offsetof(CPUSPARCState,
4552 otherwin));
0f8a249a
BS		 4553 break;
4554 case 14: // wstate
7b9e066b
RH		 4555 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4556 offsetof(CPUSPARCState,
4557 wstate));
0f8a249a 4558 break;
e9ebed4d 4559 case 16: // UA2005 gl
fb79ceb9 4560 CHECK_IU_FEATURE(dc, GL);
cbc3a6a4 4561 gen_helper_wrgl(cpu_env, cpu_tmp0);
e9ebed4d
BS		 4562 break;
4563 case 26: // UA2005 strand status
fb79ceb9 4564 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 4565 if (!hypervisor(dc))
4566 goto priv_insn;
527067d8 4567 tcg_gen_mov_tl(cpu_ssr, cpu_tmp0);
e9ebed4d 4568 break;
0f8a249a
BS		 4569 default:
4570 goto illegal_insn;
4571 }
3475187d 4572#else
7b9e066b
RH		 4573 tcg_gen_trunc_tl_i32(cpu_wim, cpu_tmp0);
4574 if (dc->def->nwindows != 32) {
4575 tcg_gen_andi_tl(cpu_wim, cpu_wim,
c93e7817 4576 (1 << dc->def->nwindows) - 1);
7b9e066b 4577 }
3475187d 4578#endif
e8af50a3
FB		 4579 }
4580 break;
e9ebed4d 4581 case 0x33: /* wrtbr, UA2005 wrhpr */
e8af50a3 4582 {
e9ebed4d 4583#ifndef TARGET_SPARC64
0f8a249a
BS		 4584 if (!supervisor(dc))
4585 goto priv_insn;
255e1fcb 4586 tcg_gen_xor_tl(cpu_tbr, cpu_src1, cpu_src2);
e9ebed4d 4587#else
fb79ceb9 4588 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 4589 if (!hypervisor(dc))
4590 goto priv_insn;
de9e9d9f 4591 cpu_tmp0 = get_temp_tl(dc);
ece43b8d 4592 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
e9ebed4d
BS		 4593 switch (rd) {
4594 case 0: // hpstate
4595 // XXX gen_op_wrhpstate();
66442b07 4596 save_state(dc);
e9ebed4d 4597 gen_op_next_insn();
57fec1fe 4598 tcg_gen_exit_tb(0);
e9ebed4d
BS		 4599 dc->is_br = 1;
4600 break;
4601 case 1: // htstate
4602 // XXX gen_op_wrhtstate();
4603 break;
4604 case 3: // hintp
255e1fcb 4605 tcg_gen_mov_tl(cpu_hintp, cpu_tmp0);
e9ebed4d
BS		 4606 break;
4607 case 5: // htba
255e1fcb 4608 tcg_gen_mov_tl(cpu_htba, cpu_tmp0);
e9ebed4d
BS		 4609 break;
4610 case 31: // hstick_cmpr
ccd4a219 4611 {
a7812ae4 4612 TCGv_ptr r_tickptr;
ccd4a219 4613
255e1fcb 4614 tcg_gen_mov_tl(cpu_hstick_cmpr, cpu_tmp0);
a7812ae4 4615 r_tickptr = tcg_temp_new_ptr();
ccd4a219 4616 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 4617 offsetof(CPUSPARCState, hstick));
a7812ae4
PB		 4618 gen_helper_tick_set_limit(r_tickptr,
4619 cpu_hstick_cmpr);
4620 tcg_temp_free_ptr(r_tickptr);
ccd4a219 4621 }
e9ebed4d
BS		 4622 break;
4623 case 6: // hver readonly
4624 default:
4625 goto illegal_insn;
4626 }
4627#endif
e8af50a3
FB		 4628 }
4629 break;
4630#endif
3475187d 4631#ifdef TARGET_SPARC64
0f8a249a
BS		 4632 case 0x2c: /* V9 movcc */
4633 {
4634 int cc = GET_FIELD_SP(insn, 11, 12);
4635 int cond = GET_FIELD_SP(insn, 14, 17);
f52879b4 4636 DisasCompare cmp;
97ea2859 4637 TCGv dst;
00f219bf 4638
0f8a249a 4639 if (insn & (1 << 18)) {
f52879b4
RH		 4640 if (cc == 0) {
4641 gen_compare(&cmp, 0, cond, dc);
4642 } else if (cc == 2) {
4643 gen_compare(&cmp, 1, cond, dc);
4644 } else {
0f8a249a 4645 goto illegal_insn;
f52879b4 4646 }
0f8a249a 4647 } else {
f52879b4 4648 gen_fcompare(&cmp, cc, cond);
0f8a249a 4649 }
00f219bf 4650
f52879b4
RH		 4651 /* The get_src2 above loaded the normal 13-bit
4652 immediate field, not the 11-bit field we have
4653 in movcc. But it did handle the reg case. */
4654 if (IS_IMM) {
67526b20 4655 simm = GET_FIELD_SPs(insn, 0, 10);
f52879b4 4656 tcg_gen_movi_tl(cpu_src2, simm);
00f219bf 4657 }
f52879b4 4658
97ea2859
RH		 4659 dst = gen_load_gpr(dc, rd);
4660 tcg_gen_movcond_tl(cmp.cond, dst,
f52879b4 4661 cmp.c1, cmp.c2,
97ea2859 4662 cpu_src2, dst);
f52879b4 4663 free_compare(&cmp);
97ea2859 4664 gen_store_gpr(dc, rd, dst);
0f8a249a
BS		 4665 break;
4666 }
4667 case 0x2d: /* V9 sdivx */
c28ae41e 4668 gen_helper_sdivx(cpu_dst, cpu_env, cpu_src1, cpu_src2);
97ea2859 4669 gen_store_gpr(dc, rd, cpu_dst);
0f8a249a
BS		 4670 break;
4671 case 0x2e: /* V9 popc */
08da3180 4672 tcg_gen_ctpop_tl(cpu_dst, cpu_src2);
97ea2859
RH		 4673 gen_store_gpr(dc, rd, cpu_dst);
4674 break;
0f8a249a
BS		 4675 case 0x2f: /* V9 movr */
4676 {
4677 int cond = GET_FIELD_SP(insn, 10, 12);
c33f80f5 4678 DisasCompare cmp;
97ea2859 4679 TCGv dst;
00f219bf 4680
c33f80f5 4681 gen_compare_reg(&cmp, cond, cpu_src1);
2ea815ca 4682
c33f80f5
RH		 4683 /* The get_src2 above loaded the normal 13-bit
4684 immediate field, not the 10-bit field we have
4685 in movr. But it did handle the reg case. */
4686 if (IS_IMM) {
67526b20 4687 simm = GET_FIELD_SPs(insn, 0, 9);
c33f80f5 4688 tcg_gen_movi_tl(cpu_src2, simm);
0f8a249a 4689 }
c33f80f5 4690
97ea2859
RH		 4691 dst = gen_load_gpr(dc, rd);
4692 tcg_gen_movcond_tl(cmp.cond, dst,
c33f80f5 4693 cmp.c1, cmp.c2,
97ea2859 4694 cpu_src2, dst);
c33f80f5 4695 free_compare(&cmp);
97ea2859 4696 gen_store_gpr(dc, rd, dst);
0f8a249a
BS		 4697 break;
4698 }
4699#endif
4700 default:
4701 goto illegal_insn;
4702 }
4703 }
3299908c
BS		 4704 } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
4705#ifdef TARGET_SPARC64
4706 int opf = GET_FIELD_SP(insn, 5, 13);
4707 rs1 = GET_FIELD(insn, 13, 17);
4708 rs2 = GET_FIELD(insn, 27, 31);
5b12f1e8 4709 if (gen_trap_ifnofpu(dc)) {
e9ebed4d 4710 goto jmp_insn;
5b12f1e8 4711 }
3299908c
BS		 4712
4713 switch (opf) {
e9ebed4d 4714 case 0x000: /* VIS I edge8cc */
6c073553 4715 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4716 cpu_src1 = gen_load_gpr(dc, rs1);
4717 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4718 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 0);
97ea2859 4719 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4720 break;
e9ebed4d 4721 case 0x001: /* VIS II edge8n */
6c073553 4722 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4723 cpu_src1 = gen_load_gpr(dc, rs1);
4724 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4725 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 0);
97ea2859 4726 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4727 break;
e9ebed4d 4728 case 0x002: /* VIS I edge8lcc */
6c073553 4729 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4730 cpu_src1 = gen_load_gpr(dc, rs1);
4731 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4732 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 1);
97ea2859 4733 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4734 break;
e9ebed4d 4735 case 0x003: /* VIS II edge8ln */
6c073553 4736 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4737 cpu_src1 = gen_load_gpr(dc, rs1);
4738 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4739 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 1);
97ea2859 4740 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4741 break;
e9ebed4d 4742 case 0x004: /* VIS I edge16cc */
6c073553 4743 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4744 cpu_src1 = gen_load_gpr(dc, rs1);
4745 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4746 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 0);
97ea2859 4747 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4748 break;
e9ebed4d 4749 case 0x005: /* VIS II edge16n */
6c073553 4750 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4751 cpu_src1 = gen_load_gpr(dc, rs1);
4752 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4753 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 0);
97ea2859 4754 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4755 break;
e9ebed4d 4756 case 0x006: /* VIS I edge16lcc */
6c073553 4757 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4758 cpu_src1 = gen_load_gpr(dc, rs1);
4759 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4760 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 1);
97ea2859 4761 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4762 break;
e9ebed4d 4763 case 0x007: /* VIS II edge16ln */
6c073553 4764 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4765 cpu_src1 = gen_load_gpr(dc, rs1);
4766 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4767 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 1);
97ea2859 4768 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4769 break;
e9ebed4d 4770 case 0x008: /* VIS I edge32cc */
6c073553 4771 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4772 cpu_src1 = gen_load_gpr(dc, rs1);
4773 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4774 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 0);
97ea2859 4775 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4776 break;
e9ebed4d 4777 case 0x009: /* VIS II edge32n */
6c073553 4778 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4779 cpu_src1 = gen_load_gpr(dc, rs1);
4780 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4781 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 0);
97ea2859 4782 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4783 break;
e9ebed4d 4784 case 0x00a: /* VIS I edge32lcc */
6c073553 4785 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4786 cpu_src1 = gen_load_gpr(dc, rs1);
4787 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4788 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 1);
97ea2859 4789 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4790 break;
e9ebed4d 4791 case 0x00b: /* VIS II edge32ln */
6c073553 4792 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4793 cpu_src1 = gen_load_gpr(dc, rs1);
4794 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4795 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 1);
97ea2859 4796 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4797 break;
e9ebed4d 4798 case 0x010: /* VIS I array8 */
64a88d5d 4799 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4800 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4801 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4802 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
97ea2859 4803 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4804 break;
4805 case 0x012: /* VIS I array16 */
64a88d5d 4806 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4807 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4808 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4809 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
6ae20372 4810 tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
97ea2859 4811 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4812 break;
4813 case 0x014: /* VIS I array32 */
64a88d5d 4814 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4815 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4816 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4817 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
6ae20372 4818 tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
97ea2859 4819 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d 4820 break;
3299908c 4821 case 0x018: /* VIS I alignaddr */
64a88d5d 4822 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4823 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4824 cpu_src2 = gen_load_gpr(dc, rs2);
add545ab 4825 gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 0);
97ea2859 4826 gen_store_gpr(dc, rd, cpu_dst);
3299908c
BS		 4827 break;
4828 case 0x01a: /* VIS I alignaddrl */
add545ab 4829 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4830 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4831 cpu_src2 = gen_load_gpr(dc, rs2);
add545ab 4832 gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 1);
97ea2859 4833 gen_store_gpr(dc, rd, cpu_dst);
add545ab
RH		 4834 break;
4835 case 0x019: /* VIS II bmask */
793a137a 4836 CHECK_FPU_FEATURE(dc, VIS2);
9d1d4e34
RH		 4837 cpu_src1 = gen_load_gpr(dc, rs1);
4838 cpu_src2 = gen_load_gpr(dc, rs2);
793a137a
RH		 4839 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4840 tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, cpu_dst, 32, 32);
97ea2859 4841 gen_store_gpr(dc, rd, cpu_dst);
793a137a 4842 break;
e9ebed4d 4843 case 0x020: /* VIS I fcmple16 */
64a88d5d 4844 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4845 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4846 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4847 gen_helper_fcmple16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4848 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4849 break;
4850 case 0x022: /* VIS I fcmpne16 */
64a88d5d 4851 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4852 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4853 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4854 gen_helper_fcmpne16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4855 gen_store_gpr(dc, rd, cpu_dst);
3299908c 4856 break;
e9ebed4d 4857 case 0x024: /* VIS I fcmple32 */
64a88d5d 4858 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4859 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4860 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4861 gen_helper_fcmple32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4862 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4863 break;
4864 case 0x026: /* VIS I fcmpne32 */
64a88d5d 4865 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4866 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4867 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4868 gen_helper_fcmpne32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4869 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4870 break;
4871 case 0x028: /* VIS I fcmpgt16 */
64a88d5d 4872 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4873 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4874 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4875 gen_helper_fcmpgt16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4876 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4877 break;
4878 case 0x02a: /* VIS I fcmpeq16 */
64a88d5d 4879 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4880 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4881 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4882 gen_helper_fcmpeq16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4883 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4884 break;
4885 case 0x02c: /* VIS I fcmpgt32 */
64a88d5d 4886 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4887 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4888 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4889 gen_helper_fcmpgt32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4890 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4891 break;
4892 case 0x02e: /* VIS I fcmpeq32 */
64a88d5d 4893 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4894 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4895 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4896 gen_helper_fcmpeq32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4897 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4898 break;
4899 case 0x031: /* VIS I fmul8x16 */
64a88d5d 4900 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4901 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16);
e9ebed4d
BS		 4902 break;
4903 case 0x033: /* VIS I fmul8x16au */
64a88d5d 4904 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4905 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16au);
e9ebed4d
BS		 4906 break;
4907 case 0x035: /* VIS I fmul8x16al */
64a88d5d 4908 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4909 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16al);
e9ebed4d
BS		 4910 break;
4911 case 0x036: /* VIS I fmul8sux16 */
64a88d5d 4912 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4913 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8sux16);
e9ebed4d
BS		 4914 break;
4915 case 0x037: /* VIS I fmul8ulx16 */
64a88d5d 4916 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4917 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8ulx16);
e9ebed4d
BS		 4918 break;
4919 case 0x038: /* VIS I fmuld8sux16 */
64a88d5d 4920 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4921 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8sux16);
e9ebed4d
BS		 4922 break;
4923 case 0x039: /* VIS I fmuld8ulx16 */
64a88d5d 4924 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4925 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8ulx16);
e9ebed4d
BS		 4926 break;
4927 case 0x03a: /* VIS I fpack32 */
2dedf314
RH		 4928 CHECK_FPU_FEATURE(dc, VIS1);
4929 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpack32);
4930 break;
e9ebed4d 4931 case 0x03b: /* VIS I fpack16 */
2dedf314
RH		 4932 CHECK_FPU_FEATURE(dc, VIS1);
4933 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
ba5f5179 4934 cpu_dst_32 = gen_dest_fpr_F(dc);
2dedf314
RH		 4935 gen_helper_fpack16(cpu_dst_32, cpu_gsr, cpu_src1_64);
4936 gen_store_fpr_F(dc, rd, cpu_dst_32);
4937 break;
e9ebed4d 4938 case 0x03d: /* VIS I fpackfix */
2dedf314
RH		 4939 CHECK_FPU_FEATURE(dc, VIS1);
4940 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
ba5f5179 4941 cpu_dst_32 = gen_dest_fpr_F(dc);
2dedf314
RH		 4942 gen_helper_fpackfix(cpu_dst_32, cpu_gsr, cpu_src1_64);
4943 gen_store_fpr_F(dc, rd, cpu_dst_32);
4944 break;
f888300b
RH		 4945 case 0x03e: /* VIS I pdist */
4946 CHECK_FPU_FEATURE(dc, VIS1);
4947 gen_ne_fop_DDDD(dc, rd, rs1, rs2, gen_helper_pdist);
4948 break;
3299908c 4949 case 0x048: /* VIS I faligndata */
64a88d5d 4950 CHECK_FPU_FEATURE(dc, VIS1);
50c796f9 4951 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_faligndata);
3299908c 4952 break;
e9ebed4d 4953 case 0x04b: /* VIS I fpmerge */
64a88d5d 4954 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4955 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpmerge);
e9ebed4d
BS		 4956 break;
4957 case 0x04c: /* VIS II bshuffle */
793a137a
RH		 4958 CHECK_FPU_FEATURE(dc, VIS2);
4959 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_bshuffle);
4960 break;
e9ebed4d 4961 case 0x04d: /* VIS I fexpand */
64a88d5d 4962 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4963 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fexpand);
e9ebed4d
BS		 4964 break;
4965 case 0x050: /* VIS I fpadd16 */
64a88d5d 4966 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4967 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd16);
e9ebed4d
BS		 4968 break;
4969 case 0x051: /* VIS I fpadd16s */
64a88d5d 4970 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4971 gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpadd16s);
e9ebed4d
BS		 4972 break;
4973 case 0x052: /* VIS I fpadd32 */
64a88d5d 4974 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4975 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd32);
e9ebed4d
BS		 4976 break;
4977 case 0x053: /* VIS I fpadd32s */
64a88d5d 4978 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4979 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_add_i32);
e9ebed4d
BS		 4980 break;
4981 case 0x054: /* VIS I fpsub16 */
64a88d5d 4982 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4983 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub16);
e9ebed4d
BS		 4984 break;
4985 case 0x055: /* VIS I fpsub16s */
64a88d5d 4986 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4987 gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpsub16s);
e9ebed4d
BS		 4988 break;
4989 case 0x056: /* VIS I fpsub32 */
64a88d5d 4990 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4991 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub32);
e9ebed4d
BS		 4992 break;
4993 case 0x057: /* VIS I fpsub32s */
64a88d5d 4994 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4995 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_sub_i32);
e9ebed4d 4996 break;
3299908c 4997 case 0x060: /* VIS I fzero */
64a88d5d 4998 CHECK_FPU_FEATURE(dc, VIS1);
3886b8a3 4999 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
96eda024
RH		 5000 tcg_gen_movi_i64(cpu_dst_64, 0);
5001 gen_store_fpr_D(dc, rd, cpu_dst_64);
3299908c
BS		 5002 break;
5003 case 0x061: /* VIS I fzeros */
64a88d5d 5004 CHECK_FPU_FEATURE(dc, VIS1);
ba5f5179 5005 cpu_dst_32 = gen_dest_fpr_F(dc);
208ae657
RH		 5006 tcg_gen_movi_i32(cpu_dst_32, 0);
5007 gen_store_fpr_F(dc, rd, cpu_dst_32);
3299908c 5008 break;
e9ebed4d 5009 case 0x062: /* VIS I fnor */
64a88d5d 5010 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5011 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nor_i64);
e9ebed4d
BS		 5012 break;
5013 case 0x063: /* VIS I fnors */
64a88d5d 5014 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5015 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nor_i32);
e9ebed4d
BS		 5016 break;
5017 case 0x064: /* VIS I fandnot2 */
64a88d5d 5018 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5019 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_andc_i64);
e9ebed4d
BS		 5020 break;
5021 case 0x065: /* VIS I fandnot2s */
64a88d5d 5022 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5023 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_andc_i32);
e9ebed4d
BS		 5024 break;
5025 case 0x066: /* VIS I fnot2 */
64a88d5d 5026 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5027 gen_ne_fop_DD(dc, rd, rs2, tcg_gen_not_i64);
e9ebed4d
BS		 5028 break;
5029 case 0x067: /* VIS I fnot2s */
64a88d5d 5030 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5031 gen_ne_fop_FF(dc, rd, rs2, tcg_gen_not_i32);
e9ebed4d
BS		 5032 break;
5033 case 0x068: /* VIS I fandnot1 */
64a88d5d 5034 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5035 gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_andc_i64);
e9ebed4d
BS		 5036 break;
5037 case 0x069: /* VIS I fandnot1s */
64a88d5d 5038 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5039 gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_andc_i32);
e9ebed4d
BS		 5040 break;
5041 case 0x06a: /* VIS I fnot1 */
64a88d5d 5042 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5043 gen_ne_fop_DD(dc, rd, rs1, tcg_gen_not_i64);
e9ebed4d
BS		 5044 break;
5045 case 0x06b: /* VIS I fnot1s */
64a88d5d 5046 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5047 gen_ne_fop_FF(dc, rd, rs1, tcg_gen_not_i32);
e9ebed4d
BS		 5048 break;
5049 case 0x06c: /* VIS I fxor */
64a88d5d 5050 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5051 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_xor_i64);
e9ebed4d
BS		 5052 break;
5053 case 0x06d: /* VIS I fxors */
64a88d5d 5054 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5055 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_xor_i32);
e9ebed4d
BS		 5056 break;
5057 case 0x06e: /* VIS I fnand */
64a88d5d 5058 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5059 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nand_i64);
e9ebed4d
BS		 5060 break;
5061 case 0x06f: /* VIS I fnands */
64a88d5d 5062 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5063 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nand_i32);
e9ebed4d
BS		 5064 break;
5065 case 0x070: /* VIS I fand */
64a88d5d 5066 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5067 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_and_i64);
e9ebed4d
BS		 5068 break;
5069 case 0x071: /* VIS I fands */
64a88d5d 5070 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5071 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_and_i32);
e9ebed4d
BS		 5072 break;
5073 case 0x072: /* VIS I fxnor */
64a88d5d 5074 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5075 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_eqv_i64);
e9ebed4d
BS		 5076 break;
5077 case 0x073: /* VIS I fxnors */
64a88d5d 5078 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5079 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_eqv_i32);
e9ebed4d 5080 break;
3299908c 5081 case 0x074: /* VIS I fsrc1 */
64a88d5d 5082 CHECK_FPU_FEATURE(dc, VIS1);
96eda024
RH		 5083 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
5084 gen_store_fpr_D(dc, rd, cpu_src1_64);
3299908c
BS		 5085 break;
5086 case 0x075: /* VIS I fsrc1s */
64a88d5d 5087 CHECK_FPU_FEATURE(dc, VIS1);
208ae657
RH		 5088 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
5089 gen_store_fpr_F(dc, rd, cpu_src1_32);
3299908c 5090 break;
e9ebed4d 5091 case 0x076: /* VIS I fornot2 */
64a88d5d 5092 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5093 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_orc_i64);
e9ebed4d
BS		 5094 break;
5095 case 0x077: /* VIS I fornot2s */
64a88d5d 5096 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5097 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_orc_i32);
e9ebed4d 5098 break;
3299908c 5099 case 0x078: /* VIS I fsrc2 */
64a88d5d 5100 CHECK_FPU_FEATURE(dc, VIS1);
96eda024
RH		 5101 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
5102 gen_store_fpr_D(dc, rd, cpu_src1_64);
3299908c
BS		 5103 break;
5104 case 0x079: /* VIS I fsrc2s */
64a88d5d 5105 CHECK_FPU_FEATURE(dc, VIS1);
208ae657
RH		 5106 cpu_src1_32 = gen_load_fpr_F(dc, rs2);
5107 gen_store_fpr_F(dc, rd, cpu_src1_32);
3299908c 5108 break;
e9ebed4d 5109 case 0x07a: /* VIS I fornot1 */
64a88d5d 5110 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5111 gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_orc_i64);
e9ebed4d
BS		 5112 break;
5113 case 0x07b: /* VIS I fornot1s */
64a88d5d 5114 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5115 gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_orc_i32);
e9ebed4d
BS		 5116 break;
5117 case 0x07c: /* VIS I for */
64a88d5d 5118 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5119 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_or_i64);
e9ebed4d
BS		 5120 break;
5121 case 0x07d: /* VIS I fors */
64a88d5d 5122 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5123 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_or_i32);
e9ebed4d 5124 break;
3299908c 5125 case 0x07e: /* VIS I fone */
64a88d5d 5126 CHECK_FPU_FEATURE(dc, VIS1);
3886b8a3 5127 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
96eda024
RH		 5128 tcg_gen_movi_i64(cpu_dst_64, -1);
5129 gen_store_fpr_D(dc, rd, cpu_dst_64);
3299908c
BS		 5130 break;
5131 case 0x07f: /* VIS I fones */
64a88d5d 5132 CHECK_FPU_FEATURE(dc, VIS1);
ba5f5179 5133 cpu_dst_32 = gen_dest_fpr_F(dc);
208ae657
RH		 5134 tcg_gen_movi_i32(cpu_dst_32, -1);
5135 gen_store_fpr_F(dc, rd, cpu_dst_32);
3299908c 5136 break;
e9ebed4d
BS		 5137 case 0x080: /* VIS I shutdown */
5138 case 0x081: /* VIS II siam */
5139 // XXX
5140 goto illegal_insn;
3299908c
BS		 5141 default:
5142 goto illegal_insn;
5143 }
5144#else
0f8a249a 5145 goto ncp_insn;
3299908c
BS		 5146#endif
5147 } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
fcc72045 5148#ifdef TARGET_SPARC64
0f8a249a 5149 goto illegal_insn;
fcc72045 5150#else
0f8a249a 5151 goto ncp_insn;
fcc72045 5152#endif
3475187d 5153#ifdef TARGET_SPARC64
0f8a249a 5154 } else if (xop == 0x39) { /* V9 return */
66442b07 5155 save_state(dc);
9d1d4e34 5156 cpu_src1 = get_src1(dc, insn);
de9e9d9f 5157 cpu_tmp0 = get_temp_tl(dc);
0f8a249a 5158 if (IS_IMM) { /* immediate */
67526b20 5159 simm = GET_FIELDs(insn, 19, 31);
7b04bd5c 5160 tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm);
0f8a249a 5161 } else { /* register */
3475187d 5162 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 5163 if (rs2) {
97ea2859 5164 cpu_src2 = gen_load_gpr(dc, rs2);
7b04bd5c 5165 tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2);
97ea2859 5166 } else {
7b04bd5c 5167 tcg_gen_mov_tl(cpu_tmp0, cpu_src1);
97ea2859 5168 }
3475187d 5169 }
063c3675 5170 gen_helper_restore(cpu_env);
13a6dd00 5171 gen_mov_pc_npc(dc);
35e94905 5172 gen_check_align(cpu_tmp0, 3);
7b04bd5c 5173 tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
0f8a249a
BS		 5174 dc->npc = DYNAMIC_PC;
5175 goto jmp_insn;
3475187d 5176#endif
0f8a249a 5177 } else {
9d1d4e34 5178 cpu_src1 = get_src1(dc, insn);
de9e9d9f 5179 cpu_tmp0 = get_temp_tl(dc);
0f8a249a 5180 if (IS_IMM) { /* immediate */
67526b20 5181 simm = GET_FIELDs(insn, 19, 31);
7b04bd5c 5182 tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm);
0f8a249a 5183 } else { /* register */
e80cfcfc 5184 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 5185 if (rs2) {
97ea2859 5186 cpu_src2 = gen_load_gpr(dc, rs2);
7b04bd5c 5187 tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2);
97ea2859 5188 } else {
7b04bd5c 5189 tcg_gen_mov_tl(cpu_tmp0, cpu_src1);
97ea2859 5190 }
cf495bcf 5191 }
0f8a249a
BS		 5192 switch (xop) {
5193 case 0x38: /* jmpl */
5194 {
35e94905 5195 TCGv t = gen_dest_gpr(dc, rd);
97ea2859
RH		 5196 tcg_gen_movi_tl(t, dc->pc);
5197 gen_store_gpr(dc, rd, t);
35e94905 5198
13a6dd00 5199 gen_mov_pc_npc(dc);
35e94905 5200 gen_check_align(cpu_tmp0, 3);
7b04bd5c
RH		 5201 gen_address_mask(dc, cpu_tmp0);
5202 tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
0f8a249a
BS		 5203 dc->npc = DYNAMIC_PC;
5204 }
5205 goto jmp_insn;
3475187d 5206#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
0f8a249a
BS		 5207 case 0x39: /* rett, V9 return */
5208 {
5209 if (!supervisor(dc))
5210 goto priv_insn;
13a6dd00 5211 gen_mov_pc_npc(dc);
35e94905 5212 gen_check_align(cpu_tmp0, 3);
7b04bd5c 5213 tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
0f8a249a 5214 dc->npc = DYNAMIC_PC;
063c3675 5215 gen_helper_rett(cpu_env);
0f8a249a
BS		 5216 }
5217 goto jmp_insn;
5218#endif
5219 case 0x3b: /* flush */
5578ceab 5220 if (!((dc)->def->features & CPU_FEATURE_FLUSH))
64a88d5d 5221 goto unimp_flush;
dcfd14b3 5222 /* nop */
0f8a249a
BS		 5223 break;
5224 case 0x3c: /* save */
063c3675 5225 gen_helper_save(cpu_env);
7b04bd5c 5226 gen_store_gpr(dc, rd, cpu_tmp0);
0f8a249a
BS		 5227 break;
5228 case 0x3d: /* restore */
063c3675 5229 gen_helper_restore(cpu_env);
7b04bd5c 5230 gen_store_gpr(dc, rd, cpu_tmp0);
0f8a249a 5231 break;
3475187d 5232#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
0f8a249a
BS		 5233 case 0x3e: /* V9 done/retry */
5234 {
5235 switch (rd) {
5236 case 0:
5237 if (!supervisor(dc))
5238 goto priv_insn;
5239 dc->npc = DYNAMIC_PC;
5240 dc->pc = DYNAMIC_PC;
063c3675 5241 gen_helper_done(cpu_env);
0f8a249a
BS		 5242 goto jmp_insn;
5243 case 1:
5244 if (!supervisor(dc))
5245 goto priv_insn;
5246 dc->npc = DYNAMIC_PC;
5247 dc->pc = DYNAMIC_PC;
063c3675 5248 gen_helper_retry(cpu_env);
0f8a249a
BS		 5249 goto jmp_insn;
5250 default:
5251 goto illegal_insn;
5252 }
5253 }
5254 break;
5255#endif
5256 default:
5257 goto illegal_insn;
5258 }
cf495bcf 5259 }
0f8a249a
BS		 5260 break;
5261 }
5262 break;
5263 case 3: /* load/store instructions */
5264 {
5265 unsigned int xop = GET_FIELD(insn, 7, 12);
5e6ed439
RH		 5266 /* ??? gen_address_mask prevents us from using a source
5267 register directly. Always generate a temporary. */
5268 TCGv cpu_addr = get_temp_tl(dc);
9322a4bf 5269
5e6ed439
RH		 5270 tcg_gen_mov_tl(cpu_addr, get_src1(dc, insn));
5271 if (xop == 0x3c || xop == 0x3e) {
5272 /* V9 casa/casxa : no offset */
71817e48 5273 } else if (IS_IMM) { /* immediate */
67526b20 5274 simm = GET_FIELDs(insn, 19, 31);
5e6ed439
RH		 5275 if (simm != 0) {
5276 tcg_gen_addi_tl(cpu_addr, cpu_addr, simm);
5277 }
0f8a249a
BS		 5278 } else { /* register */
5279 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 5280 if (rs2 != 0) {
5e6ed439 5281 tcg_gen_add_tl(cpu_addr, cpu_addr, gen_load_gpr(dc, rs2));
97ea2859 5282 }
0f8a249a 5283 }
2f2ecb83
BS		 5284 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
5285 (xop > 0x17 && xop <= 0x1d ) ||
5286 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
81634eea
RH		 5287 TCGv cpu_val = gen_dest_gpr(dc, rd);
5288
0f8a249a 5289 switch (xop) {
b89e94af 5290 case 0x0: /* ld, V9 lduw, load unsigned word */
2cade6a3 5291 gen_address_mask(dc, cpu_addr);
6ae20372 5292 tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5293 break;
b89e94af 5294 case 0x1: /* ldub, load unsigned byte */
2cade6a3 5295 gen_address_mask(dc, cpu_addr);
6ae20372 5296 tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5297 break;
b89e94af 5298 case 0x2: /* lduh, load unsigned halfword */
2cade6a3 5299 gen_address_mask(dc, cpu_addr);
6ae20372 5300 tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5301 break;
b89e94af 5302 case 0x3: /* ldd, load double word */
0f8a249a 5303 if (rd & 1)
d4218d99 5304 goto illegal_insn;
1a2fb1c0 5305 else {
abcc7191 5306 TCGv_i64 t64;
2ea815ca 5307
2cade6a3 5308 gen_address_mask(dc, cpu_addr);
abcc7191
RH		 5309 t64 = tcg_temp_new_i64();
5310 tcg_gen_qemu_ld64(t64, cpu_addr, dc->mem_idx);
de9e9d9f
RH		 5311 tcg_gen_trunc_i64_tl(cpu_val, t64);
5312 tcg_gen_ext32u_tl(cpu_val, cpu_val);
5313 gen_store_gpr(dc, rd + 1, cpu_val);
abcc7191
RH		 5314 tcg_gen_shri_i64(t64, t64, 32);
5315 tcg_gen_trunc_i64_tl(cpu_val, t64);
5316 tcg_temp_free_i64(t64);
de9e9d9f 5317 tcg_gen_ext32u_tl(cpu_val, cpu_val);
1a2fb1c0 5318 }
0f8a249a 5319 break;
b89e94af 5320 case 0x9: /* ldsb, load signed byte */
2cade6a3 5321 gen_address_mask(dc, cpu_addr);
6ae20372 5322 tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5323 break;
b89e94af 5324 case 0xa: /* ldsh, load signed halfword */
2cade6a3 5325 gen_address_mask(dc, cpu_addr);
6ae20372 5326 tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5327 break;
fbb4bbb6
RH		 5328 case 0xd: /* ldstub */
5329 gen_ldstub(dc, cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5330 break;
de9e9d9f
RH		 5331 case 0x0f:
5332 /* swap, swap register with memory. Also atomically */
4fb554bc
RH		 5333 CHECK_IU_FEATURE(dc, SWAP);
5334 cpu_src1 = gen_load_gpr(dc, rd);
5335 gen_swap(dc, cpu_val, cpu_src1, cpu_addr,
5336 dc->mem_idx, MO_TEUL);
0f8a249a 5337 break;
3475187d 5338#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
b89e94af 5339 case 0x10: /* lda, V9 lduwa, load word alternate */
1d65b0f5 5340 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEUL);
0f8a249a 5341 break;
b89e94af 5342 case 0x11: /* lduba, load unsigned byte alternate */
1d65b0f5 5343 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_UB);
0f8a249a 5344 break;
b89e94af 5345 case 0x12: /* lduha, load unsigned halfword alternate */
1d65b0f5 5346 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEUW);
0f8a249a 5347 break;
b89e94af 5348 case 0x13: /* ldda, load double word alternate */
7ec1e5ea 5349 if (rd & 1) {
d4218d99 5350 goto illegal_insn;
7ec1e5ea 5351 }
e4dc0052 5352 gen_ldda_asi(dc, cpu_addr, insn, rd);
db166940 5353 goto skip_move;
b89e94af 5354 case 0x19: /* ldsba, load signed byte alternate */
1d65b0f5 5355 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_SB);
0f8a249a 5356 break;
b89e94af 5357 case 0x1a: /* ldsha, load signed halfword alternate */
1d65b0f5 5358 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESW);
0f8a249a
BS		 5359 break;
5360 case 0x1d: /* ldstuba -- XXX: should be atomically */
22e70060 5361 gen_ldstub_asi(dc, cpu_val, cpu_addr, insn);
0f8a249a 5362 break;
b89e94af 5363 case 0x1f: /* swapa, swap reg with alt. memory. Also
77f193da 5364 atomically */
64a88d5d 5365 CHECK_IU_FEATURE(dc, SWAP);
06828032 5366 cpu_src1 = gen_load_gpr(dc, rd);
22e70060 5367 gen_swap_asi(dc, cpu_val, cpu_src1, cpu_addr, insn);
0f8a249a 5368 break;
3475187d
FB		 5369
5370#ifndef TARGET_SPARC64
0f8a249a
BS		 5371 case 0x30: /* ldc */
5372 case 0x31: /* ldcsr */
5373 case 0x33: /* lddc */
5374 goto ncp_insn;
3475187d
FB		 5375#endif
5376#endif
5377#ifdef TARGET_SPARC64
0f8a249a 5378 case 0x08: /* V9 ldsw */
2cade6a3 5379 gen_address_mask(dc, cpu_addr);
6ae20372 5380 tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 5381 break;
5382 case 0x0b: /* V9 ldx */
2cade6a3 5383 gen_address_mask(dc, cpu_addr);
6ae20372 5384 tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 5385 break;
5386 case 0x18: /* V9 ldswa */
1d65b0f5 5387 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESL);
0f8a249a
BS		 5388 break;
5389 case 0x1b: /* V9 ldxa */
1d65b0f5 5390 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEQ);
0f8a249a
BS		 5391 break;
5392 case 0x2d: /* V9 prefetch, no effect */
5393 goto skip_move;
5394 case 0x30: /* V9 ldfa */
5b12f1e8 5395 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 5396 goto jmp_insn;
5397 }
22e70060 5398 gen_ldf_asi(dc, cpu_addr, insn, 4, rd);
f9c816c0 5399 gen_update_fprs_dirty(dc, rd);
81ad8ba2 5400 goto skip_move;
0f8a249a 5401 case 0x33: /* V9 lddfa */
5b12f1e8 5402 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 5403 goto jmp_insn;
5404 }
22e70060 5405 gen_ldf_asi(dc, cpu_addr, insn, 8, DFPREG(rd));
f9c816c0 5406 gen_update_fprs_dirty(dc, DFPREG(rd));
81ad8ba2 5407 goto skip_move;
0f8a249a
BS		 5408 case 0x3d: /* V9 prefetcha, no effect */
5409 goto skip_move;
5410 case 0x32: /* V9 ldqfa */
64a88d5d 5411 CHECK_FPU_FEATURE(dc, FLOAT128);
5b12f1e8 5412 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 5413 goto jmp_insn;
5414 }
22e70060 5415 gen_ldf_asi(dc, cpu_addr, insn, 16, QFPREG(rd));
f9c816c0 5416 gen_update_fprs_dirty(dc, QFPREG(rd));
1f587329 5417 goto skip_move;
0f8a249a
BS		 5418#endif
5419 default:
5420 goto illegal_insn;
5421 }
97ea2859 5422 gen_store_gpr(dc, rd, cpu_val);
db166940 5423#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
0f8a249a 5424 skip_move: ;
3475187d 5425#endif
0f8a249a 5426 } else if (xop >= 0x20 && xop < 0x24) {
5b12f1e8 5427 if (gen_trap_ifnofpu(dc)) {
a80dde08 5428 goto jmp_insn;
5b12f1e8 5429 }
0f8a249a 5430 switch (xop) {
b89e94af 5431 case 0x20: /* ldf, load fpreg */
2cade6a3 5432 gen_address_mask(dc, cpu_addr);
ba5f5179 5433 cpu_dst_32 = gen_dest_fpr_F(dc);
cb21b4da
RH		 5434 tcg_gen_qemu_ld_i32(cpu_dst_32, cpu_addr,
5435 dc->mem_idx, MO_TEUL);
208ae657 5436 gen_store_fpr_F(dc, rd, cpu_dst_32);
0f8a249a 5437 break;
3a3b925d
BS		 5438 case 0x21: /* ldfsr, V9 ldxfsr */
5439#ifdef TARGET_SPARC64
2cade6a3 5440 gen_address_mask(dc, cpu_addr);
3a3b925d 5441 if (rd == 1) {
abcc7191 5442 TCGv_i64 t64 = tcg_temp_new_i64();
cb21b4da
RH		 5443 tcg_gen_qemu_ld_i64(t64, cpu_addr,
5444 dc->mem_idx, MO_TEQ);
7385aed2 5445 gen_helper_ldxfsr(cpu_fsr, cpu_env, cpu_fsr, t64);
abcc7191 5446 tcg_temp_free_i64(t64);
f8641947 5447 break;
fe987e23 5448 }
f8641947 5449#endif
de9e9d9f 5450 cpu_dst_32 = get_temp_i32(dc);
cb21b4da
RH		 5451 tcg_gen_qemu_ld_i32(cpu_dst_32, cpu_addr,
5452 dc->mem_idx, MO_TEUL);
7385aed2 5453 gen_helper_ldfsr(cpu_fsr, cpu_env, cpu_fsr, cpu_dst_32);
0f8a249a 5454 break;
b89e94af 5455 case 0x22: /* ldqf, load quad fpreg */
f939ffe5
RH		 5456 CHECK_FPU_FEATURE(dc, FLOAT128);
5457 gen_address_mask(dc, cpu_addr);
5458 cpu_src1_64 = tcg_temp_new_i64();
cb21b4da
RH		 5459 tcg_gen_qemu_ld_i64(cpu_src1_64, cpu_addr, dc->mem_idx,
5460 MO_TEQ | MO_ALIGN_4);
f939ffe5
RH		 5461 tcg_gen_addi_tl(cpu_addr, cpu_addr, 8);
5462 cpu_src2_64 = tcg_temp_new_i64();
cb21b4da
RH		 5463 tcg_gen_qemu_ld_i64(cpu_src2_64, cpu_addr, dc->mem_idx,
5464 MO_TEQ | MO_ALIGN_4);
f939ffe5
RH		 5465 gen_store_fpr_Q(dc, rd, cpu_src1_64, cpu_src2_64);
5466 tcg_temp_free_i64(cpu_src1_64);
5467 tcg_temp_free_i64(cpu_src2_64);
1f587329 5468 break;
b89e94af 5469 case 0x23: /* lddf, load double fpreg */
03fb8cfc 5470 gen_address_mask(dc, cpu_addr);
3886b8a3 5471 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
cb21b4da
RH		 5472 tcg_gen_qemu_ld_i64(cpu_dst_64, cpu_addr, dc->mem_idx,
5473 MO_TEQ | MO_ALIGN_4);
03fb8cfc 5474 gen_store_fpr_D(dc, rd, cpu_dst_64);
0f8a249a
BS		 5475 break;
5476 default:
5477 goto illegal_insn;
5478 }
dc1a6971 5479 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) ||
0f8a249a 5480 xop == 0xe || xop == 0x1e) {
81634eea
RH		 5481 TCGv cpu_val = gen_load_gpr(dc, rd);
5482
0f8a249a 5483 switch (xop) {
b89e94af 5484 case 0x4: /* st, store word */
2cade6a3 5485 gen_address_mask(dc, cpu_addr);
6ae20372 5486 tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5487 break;
b89e94af 5488 case 0x5: /* stb, store byte */
2cade6a3 5489 gen_address_mask(dc, cpu_addr);
6ae20372 5490 tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5491 break;
b89e94af 5492 case 0x6: /* sth, store halfword */
2cade6a3 5493 gen_address_mask(dc, cpu_addr);
6ae20372 5494 tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5495 break;
b89e94af 5496 case 0x7: /* std, store double word */
0f8a249a 5497 if (rd & 1)
d4218d99 5498 goto illegal_insn;
1a2fb1c0 5499 else {
abcc7191 5500 TCGv_i64 t64;
81634eea 5501 TCGv lo;
1a2fb1c0 5502
2cade6a3 5503 gen_address_mask(dc, cpu_addr);
81634eea 5504 lo = gen_load_gpr(dc, rd + 1);
abcc7191
RH		 5505 t64 = tcg_temp_new_i64();
5506 tcg_gen_concat_tl_i64(t64, lo, cpu_val);
5507 tcg_gen_qemu_st64(t64, cpu_addr, dc->mem_idx);
5508 tcg_temp_free_i64(t64);
7fa76c0b 5509 }
0f8a249a 5510 break;
3475187d 5511#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
b89e94af 5512 case 0x14: /* sta, V9 stwa, store word alternate */
1d65b0f5 5513 gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUL);
d39c0b99 5514 break;
b89e94af 5515 case 0x15: /* stba, store byte alternate */
1d65b0f5 5516 gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_UB);
d39c0b99 5517 break;
b89e94af 5518 case 0x16: /* stha, store halfword alternate */
1d65b0f5 5519 gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUW);
d39c0b99 5520 break;
b89e94af 5521 case 0x17: /* stda, store double word alternate */
7ec1e5ea 5522 if (rd & 1) {
0f8a249a 5523 goto illegal_insn;
1a2fb1c0 5524 }
7ec1e5ea 5525 gen_stda_asi(dc, cpu_val, cpu_addr, insn, rd);
d39c0b99 5526 break;
e80cfcfc 5527#endif
3475187d 5528#ifdef TARGET_SPARC64
0f8a249a 5529 case 0x0e: /* V9 stx */
2cade6a3 5530 gen_address_mask(dc, cpu_addr);
6ae20372 5531 tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 5532 break;
5533 case 0x1e: /* V9 stxa */
1d65b0f5 5534 gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEQ);
0f8a249a 5535 break;
3475187d 5536#endif
0f8a249a
BS		 5537 default:
5538 goto illegal_insn;
5539 }
5540 } else if (xop > 0x23 && xop < 0x28) {
5b12f1e8 5541 if (gen_trap_ifnofpu(dc)) {
a80dde08 5542 goto jmp_insn;
5b12f1e8 5543 }
0f8a249a 5544 switch (xop) {
b89e94af 5545 case 0x24: /* stf, store fpreg */
cb21b4da
RH		 5546 gen_address_mask(dc, cpu_addr);
5547 cpu_src1_32 = gen_load_fpr_F(dc, rd);
5548 tcg_gen_qemu_st_i32(cpu_src1_32, cpu_addr,
5549 dc->mem_idx, MO_TEUL);
0f8a249a
BS		 5550 break;
5551 case 0x25: /* stfsr, V9 stxfsr */
f8641947 5552 {
3a3b925d 5553#ifdef TARGET_SPARC64
f8641947
RH		 5554 gen_address_mask(dc, cpu_addr);
5555 if (rd == 1) {
ba2397d1 5556 tcg_gen_qemu_st64(cpu_fsr, cpu_addr, dc->mem_idx);
f8641947
RH		 5557 break;
5558 }
3a3b925d 5559#endif
ba2397d1 5560 tcg_gen_qemu_st32(cpu_fsr, cpu_addr, dc->mem_idx);
f8641947 5561 }
0f8a249a 5562 break;
1f587329
BS		 5563 case 0x26:
5564#ifdef TARGET_SPARC64
1f587329 5565 /* V9 stqf, store quad fpreg */
f939ffe5
RH		 5566 CHECK_FPU_FEATURE(dc, FLOAT128);
5567 gen_address_mask(dc, cpu_addr);
5568 /* ??? While stqf only requires 4-byte alignment, it is
5569 legal for the cpu to signal the unaligned exception.
5570 The OS trap handler is then required to fix it up.
5571 For qemu, this avoids having to probe the second page
5572 before performing the first write. */
5573 cpu_src1_64 = gen_load_fpr_Q0(dc, rd);
5574 tcg_gen_qemu_st_i64(cpu_src1_64, cpu_addr,
5575 dc->mem_idx, MO_TEQ | MO_ALIGN_16);
5576 tcg_gen_addi_tl(cpu_addr, cpu_addr, 8);
5577 cpu_src2_64 = gen_load_fpr_Q1(dc, rd);
5578 tcg_gen_qemu_st_i64(cpu_src1_64, cpu_addr,
5579 dc->mem_idx, MO_TEQ);
1f587329 5580 break;
1f587329
BS		 5581#else /* !TARGET_SPARC64 */
5582 /* stdfq, store floating point queue */
5583#if defined(CONFIG_USER_ONLY)
5584 goto illegal_insn;
5585#else
0f8a249a
BS		 5586 if (!supervisor(dc))
5587 goto priv_insn;
5b12f1e8 5588 if (gen_trap_ifnofpu(dc)) {
0f8a249a 5589 goto jmp_insn;
5b12f1e8 5590 }
0f8a249a 5591 goto nfq_insn;
1f587329 5592#endif
0f8a249a 5593#endif
b89e94af 5594 case 0x27: /* stdf, store double fpreg */
03fb8cfc
RH		 5595 gen_address_mask(dc, cpu_addr);
5596 cpu_src1_64 = gen_load_fpr_D(dc, rd);
cb21b4da
RH		 5597 tcg_gen_qemu_st_i64(cpu_src1_64, cpu_addr, dc->mem_idx,
5598 MO_TEQ | MO_ALIGN_4);
0f8a249a
BS		 5599 break;
5600 default:
5601 goto illegal_insn;
5602 }
5603 } else if (xop > 0x33 && xop < 0x3f) {
5604 switch (xop) {
a4d17f19 5605#ifdef TARGET_SPARC64
0f8a249a 5606 case 0x34: /* V9 stfa */
5b12f1e8 5607 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5608 goto jmp_insn;
5609 }
22e70060 5610 gen_stf_asi(dc, cpu_addr, insn, 4, rd);
0f8a249a 5611 break;
1f587329 5612 case 0x36: /* V9 stqfa */
2ea815ca 5613 {
2ea815ca 5614 CHECK_FPU_FEATURE(dc, FLOAT128);
5b12f1e8 5615 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5616 goto jmp_insn;
5617 }
22e70060 5618 gen_stf_asi(dc, cpu_addr, insn, 16, QFPREG(rd));
2ea815ca 5619 }
1f587329 5620 break;
0f8a249a 5621 case 0x37: /* V9 stdfa */
5b12f1e8 5622 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5623 goto jmp_insn;
5624 }
22e70060 5625 gen_stf_asi(dc, cpu_addr, insn, 8, DFPREG(rd));
0f8a249a 5626 break;
0f8a249a 5627 case 0x3e: /* V9 casxa */
a4273524
RH		 5628 rs2 = GET_FIELD(insn, 27, 31);
5629 cpu_src2 = gen_load_gpr(dc, rs2);
81634eea 5630 gen_casx_asi(dc, cpu_addr, cpu_src2, insn, rd);
0f8a249a 5631 break;
a4d17f19 5632#else
0f8a249a
BS		 5633 case 0x34: /* stc */
5634 case 0x35: /* stcsr */
5635 case 0x36: /* stdcq */
5636 case 0x37: /* stdc */
5637 goto ncp_insn;
16c358e9
SH		 5638#endif
5639#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
5640 case 0x3c: /* V9 or LEON3 casa */
5641#ifndef TARGET_SPARC64
5642 CHECK_IU_FEATURE(dc, CASA);
16c358e9
SH		 5643#endif
5644 rs2 = GET_FIELD(insn, 27, 31);
5645 cpu_src2 = gen_load_gpr(dc, rs2);
5646 gen_cas_asi(dc, cpu_addr, cpu_src2, insn, rd);
5647 break;
0f8a249a
BS		 5648#endif
5649 default:
5650 goto illegal_insn;
5651 }
a4273524 5652 } else {
0f8a249a 5653 goto illegal_insn;
a4273524 5654 }
0f8a249a
BS		 5655 }
5656 break;
cf495bcf
FB		 5657 }
5658 /* default case for non jump instructions */
72cbca10 5659 if (dc->npc == DYNAMIC_PC) {
0f8a249a
BS		 5660 dc->pc = DYNAMIC_PC;
5661 gen_op_next_insn();
72cbca10
FB		 5662 } else if (dc->npc == JUMP_PC) {
5663 /* we can do a static jump */
6ae20372 5664 gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
72cbca10
FB		 5665 dc->is_br = 1;
5666 } else {
0f8a249a
BS		 5667 dc->pc = dc->npc;
5668 dc->npc = dc->npc + 4;
cf495bcf 5669 }
e80cfcfc 5670 jmp_insn:
42a8aa83 5671 goto egress;
cf495bcf 5672 illegal_insn:
4fbe0067 5673 gen_exception(dc, TT_ILL_INSN);
42a8aa83 5674 goto egress;
64a88d5d 5675 unimp_flush:
4fbe0067 5676 gen_exception(dc, TT_UNIMP_FLUSH);
42a8aa83 5677 goto egress;
e80cfcfc 5678#if !defined(CONFIG_USER_ONLY)
e8af50a3 5679 priv_insn:
4fbe0067 5680 gen_exception(dc, TT_PRIV_INSN);
42a8aa83 5681 goto egress;
64a88d5d 5682#endif
e80cfcfc 5683 nfpu_insn:
4fbe0067 5684 gen_op_fpexception_im(dc, FSR_FTT_UNIMPFPOP);
42a8aa83 5685 goto egress;
64a88d5d 5686#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
9143e598 5687 nfq_insn:
4fbe0067 5688 gen_op_fpexception_im(dc, FSR_FTT_SEQ_ERROR);
42a8aa83 5689 goto egress;
9143e598 5690#endif
fcc72045
BS		 5691#ifndef TARGET_SPARC64
5692 ncp_insn:
4fbe0067 5693 gen_exception(dc, TT_NCP_INSN);
42a8aa83 5694 goto egress;
fcc72045 5695#endif
42a8aa83 5696 egress:
30038fd8
RH		 5697 if (dc->n_t32 != 0) {
5698 int i;
5699 for (i = dc->n_t32 - 1; i >= 0; --i) {
5700 tcg_temp_free_i32(dc->t32[i]);
5701 }
5702 dc->n_t32 = 0;
5703 }
88023616
RH		 5704 if (dc->n_ttl != 0) {
5705 int i;
5706 for (i = dc->n_ttl - 1; i >= 0; --i) {
5707 tcg_temp_free(dc->ttl[i]);
5708 }
5709 dc->n_ttl = 0;
5710 }
7a3f1944
FB		 5711}
5712
4e5e1215 5713void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 5714{
4e5e1215 5715 SPARCCPU *cpu = sparc_env_get_cpu(env);
ed2803da 5716 CPUState *cs = CPU(cpu);
72cbca10 5717 target_ulong pc_start, last_pc;
cf495bcf 5718 DisasContext dc1, *dc = &dc1;
2e70f6ef
PB		 5719 int num_insns;
5720 int max_insns;
0184e266 5721 unsigned int insn;
cf495bcf
FB		 5722
5723 memset(dc, 0, sizeof(DisasContext));
cf495bcf 5724 dc->tb = tb;
72cbca10 5725 pc_start = tb->pc;
cf495bcf 5726 dc->pc = pc_start;
e80cfcfc 5727 last_pc = dc->pc;
72cbca10 5728 dc->npc = (target_ulong) tb->cs_base;
8393617c 5729 dc->cc_op = CC_OP_DYNAMIC;
99a23063 5730 dc->mem_idx = tb->flags & TB_FLAG_MMU_MASK;
5578ceab 5731 dc->def = env->def;
f838e2c5
BS		 5732 dc->fpu_enabled = tb_fpu_enabled(tb->flags);
5733 dc->address_mask_32bit = tb_am_enabled(tb->flags);
ed2803da 5734 dc->singlestep = (cs->singlestep_enabled || singlestep);
c9b459aa
AT		 5735#ifndef CONFIG_USER_ONLY
5736 dc->supervisor = (tb->flags & TB_FLAG_SUPER) != 0;
5737#endif
a6d567e5 5738#ifdef TARGET_SPARC64
f9c816c0 5739 dc->fprs_dirty = 0;
a6d567e5 5740 dc->asi = (tb->flags >> TB_FLAG_ASI_SHIFT) & 0xff;
c9b459aa
AT		 5741#ifndef CONFIG_USER_ONLY
5742 dc->hypervisor = (tb->flags & TB_FLAG_HYPER) != 0;
5743#endif
a6d567e5 5744#endif
cf495bcf 5745
2e70f6ef
PB		 5746 num_insns = 0;
5747 max_insns = tb->cflags & CF_COUNT_MASK;
190ce7fb 5748 if (max_insns == 0) {
2e70f6ef 5749 max_insns = CF_COUNT_MASK;
190ce7fb
RH		 5750 }
5751 if (max_insns > TCG_MAX_INSNS) {
5752 max_insns = TCG_MAX_INSNS;
5753 }
5754
cd42d5b2 5755 gen_tb_start(tb);
cf495bcf 5756 do {
a3d5ad76
RH		 5757 if (dc->npc & JUMP_PC) {
5758 assert(dc->jump_pc[1] == dc->pc + 4);
5759 tcg_gen_insn_start(dc->pc, dc->jump_pc[0] | JUMP_PC);
5760 } else {
5761 tcg_gen_insn_start(dc->pc, dc->npc);
5762 }
959082fc 5763 num_insns++;
522a0d4e 5764 last_pc = dc->pc;
667b8e29 5765
b933066a
RH		 5766 if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
5767 if (dc->pc != pc_start) {
5768 save_state(dc);
5769 }
5770 gen_helper_debug(cpu_env);
5771 tcg_gen_exit_tb(0);
5772 dc->is_br = 1;
5773 goto exit_gen_loop;
5774 }
5775
959082fc 5776 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
2e70f6ef 5777 gen_io_start();
667b8e29
RH		 5778 }
5779
0184e266 5780 insn = cpu_ldl_code(env, dc->pc);
b09b2fd3 5781
0184e266 5782 disas_sparc_insn(dc, insn);
0f8a249a
BS		 5783
5784 if (dc->is_br)
5785 break;
5786 /* if the next PC is different, we abort now */
5787 if (dc->pc != (last_pc + 4))
5788 break;
d39c0b99
FB		 5789 /* if we reach a page boundary, we stop generation so that the
5790 PC of a TT_TFAULT exception is always in the right page */
5791 if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
5792 break;
e80cfcfc
FB		 5793 /* if single step mode, we generate only one instruction and
5794 generate an exception */
060718c1 5795 if (dc->singlestep) {
e80cfcfc
FB		 5796 break;
5797 }
fe700adb 5798 } while (!tcg_op_buf_full() &&
2e70f6ef
PB		 5799 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) &&
5800 num_insns < max_insns);
e80cfcfc
FB		 5801
5802 exit_gen_loop:
b09b2fd3 5803 if (tb->cflags & CF_LAST_IO) {
2e70f6ef 5804 gen_io_end();
b09b2fd3 5805 }
72cbca10 5806 if (!dc->is_br) {
5fafdf24 5807 if (dc->pc != DYNAMIC_PC &&
72cbca10
FB		 5808 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
5809 /* static PC and NPC: we can use direct chaining */
2f5680ee 5810 gen_goto_tb(dc, 0, dc->pc, dc->npc);
72cbca10 5811 } else {
b09b2fd3 5812 if (dc->pc != DYNAMIC_PC) {
2f5680ee 5813 tcg_gen_movi_tl(cpu_pc, dc->pc);
b09b2fd3 5814 }
934da7ee 5815 save_npc(dc);
57fec1fe 5816 tcg_gen_exit_tb(0);
72cbca10
FB		 5817 }
5818 }
806f352d 5819 gen_tb_end(tb, num_insns);
0a7df5da 5820
4e5e1215
RH		 5821 tb->size = last_pc + 4 - pc_start;
5822 tb->icount = num_insns;
5823
7a3f1944 5824#ifdef DEBUG_DISAS
4910e6e4
RH		 5825 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
5826 && qemu_log_in_addr_range(pc_start)) {
1ee73216 5827 qemu_log_lock();
93fcfe39
AL		 5828 qemu_log("--------------\n");
5829 qemu_log("IN: %s\n", lookup_symbol(pc_start));
d49190c4 5830 log_target_disas(cs, pc_start, last_pc + 4 - pc_start, 0);
93fcfe39 5831 qemu_log("\n");
1ee73216 5832 qemu_log_unlock();
cf495bcf 5833 }
7a3f1944 5834#endif
7a3f1944
FB		 5835}
5836
c48fcb47 5837void gen_intermediate_code_init(CPUSPARCState *env)
e80cfcfc 5838{
c48fcb47 5839 static int inited;
d2dc4069 5840 static const char gregnames[32][4] = {
0ea63844 5841 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
d2dc4069
RH		 5842 "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7",
5843 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
5844 "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
f5069b26 5845 };
0ea63844 5846 static const char fregnames[32][4] = {
30038fd8
RH		 5847 "f0", "f2", "f4", "f6", "f8", "f10", "f12", "f14",
5848 "f16", "f18", "f20", "f22", "f24", "f26", "f28", "f30",
5849 "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",
5850 "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",
714547bb 5851 };
aaed909a 5852
0ea63844 5853 static const struct { TCGv_i32 *ptr; int off; const char *name; } r32[] = {
1a2fb1c0 5854#ifdef TARGET_SPARC64
0ea63844 5855 { &cpu_xcc, offsetof(CPUSPARCState, xcc), "xcc" },
0ea63844 5856 { &cpu_fprs, offsetof(CPUSPARCState, fprs), "fprs" },
255e1fcb 5857#else
0ea63844
RH		 5858 { &cpu_wim, offsetof(CPUSPARCState, wim), "wim" },
5859#endif
5860 { &cpu_cc_op, offsetof(CPUSPARCState, cc_op), "cc_op" },
5861 { &cpu_psr, offsetof(CPUSPARCState, psr), "psr" },
5862 };
5863
5864 static const struct { TCGv *ptr; int off; const char *name; } rtl[] = {
5865#ifdef TARGET_SPARC64
5866 { &cpu_gsr, offsetof(CPUSPARCState, gsr), "gsr" },
5867 { &cpu_tick_cmpr, offsetof(CPUSPARCState, tick_cmpr), "tick_cmpr" },
5868 { &cpu_stick_cmpr, offsetof(CPUSPARCState, stick_cmpr), "stick_cmpr" },
5869 { &cpu_hstick_cmpr, offsetof(CPUSPARCState, hstick_cmpr),
5870 "hstick_cmpr" },
5871 { &cpu_hintp, offsetof(CPUSPARCState, hintp), "hintp" },
5872 { &cpu_htba, offsetof(CPUSPARCState, htba), "htba" },
5873 { &cpu_hver, offsetof(CPUSPARCState, hver), "hver" },
5874 { &cpu_ssr, offsetof(CPUSPARCState, ssr), "ssr" },
5875 { &cpu_ver, offsetof(CPUSPARCState, version), "ver" },
1a2fb1c0 5876#endif
0ea63844
RH		 5877 { &cpu_cond, offsetof(CPUSPARCState, cond), "cond" },
5878 { &cpu_cc_src, offsetof(CPUSPARCState, cc_src), "cc_src" },
5879 { &cpu_cc_src2, offsetof(CPUSPARCState, cc_src2), "cc_src2" },
5880 { &cpu_cc_dst, offsetof(CPUSPARCState, cc_dst), "cc_dst" },
5881 { &cpu_fsr, offsetof(CPUSPARCState, fsr), "fsr" },
5882 { &cpu_pc, offsetof(CPUSPARCState, pc), "pc" },
5883 { &cpu_npc, offsetof(CPUSPARCState, npc), "npc" },
5884 { &cpu_y, offsetof(CPUSPARCState, y), "y" },
255e1fcb 5885#ifndef CONFIG_USER_ONLY
0ea63844 5886 { &cpu_tbr, offsetof(CPUSPARCState, tbr), "tbr" },
255e1fcb 5887#endif
0ea63844
RH		 5888 };
5889
5890 unsigned int i;
5891
5892 /* init various static tables */
5893 if (inited) {
5894 return;
5895 }
5896 inited = 1;
5897
5898 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
7c255043 5899 tcg_ctx.tcg_env = cpu_env;
0ea63844
RH		 5900
5901 cpu_regwptr = tcg_global_mem_new_ptr(cpu_env,
5902 offsetof(CPUSPARCState, regwptr),
5903 "regwptr");
5904
5905 for (i = 0; i < ARRAY_SIZE(r32); ++i) {
5906 *r32[i].ptr = tcg_global_mem_new_i32(cpu_env, r32[i].off, r32[i].name);
5907 }
5908
5909 for (i = 0; i < ARRAY_SIZE(rtl); ++i) {
5910 *rtl[i].ptr = tcg_global_mem_new(cpu_env, rtl[i].off, rtl[i].name);
5911 }
5912
d2dc4069 5913 TCGV_UNUSED(cpu_regs[0]);
0ea63844 5914 for (i = 1; i < 8; ++i) {
d2dc4069
RH		 5915 cpu_regs[i] = tcg_global_mem_new(cpu_env,
5916 offsetof(CPUSPARCState, gregs[i]),
5917 gregnames[i]);
5918 }
5919
5920 for (i = 8; i < 32; ++i) {
5921 cpu_regs[i] = tcg_global_mem_new(cpu_regwptr,
5922 (i - 8) * sizeof(target_ulong),
5923 gregnames[i]);
0ea63844
RH		 5924 }
5925
5926 for (i = 0; i < TARGET_DPREGS; i++) {
5927 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
5928 offsetof(CPUSPARCState, fpr[i]),
5929 fregnames[i]);
1a2fb1c0 5930 }
658138bc 5931}
d2856f1a 5932
bad729e2
RH		 5933void restore_state_to_opc(CPUSPARCState *env, TranslationBlock *tb,
5934 target_ulong *data)
d2856f1a 5935{
bad729e2
RH		 5936 target_ulong pc = data[0];
5937 target_ulong npc = data[1];
5938
5939 env->pc = pc;
6c42444f 5940 if (npc == DYNAMIC_PC) {
d2856f1a 5941 /* dynamic NPC: already stored */
6c42444f 5942 } else if (npc & JUMP_PC) {
d7da2a10
BS		 5943 /* jump PC: use 'cond' and the jump targets of the translation */
5944 if (env->cond) {
6c42444f 5945 env->npc = npc & ~3;
d7da2a10 5946 } else {
6c42444f 5947 env->npc = pc + 4;
d7da2a10 5948 }
d2856f1a
AJ		 5949 } else {
5950 env->npc = npc;
5951 }
5952}
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