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2328826b MF |
1 | /* |
2 | * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. | |
3 | * All rights reserved. | |
4 | * | |
5 | * Redistribution and use in source and binary forms, with or without | |
6 | * modification, are permitted provided that the following conditions are met: | |
7 | * * Redistributions of source code must retain the above copyright | |
8 | * notice, this list of conditions and the following disclaimer. | |
9 | * * Redistributions in binary form must reproduce the above copyright | |
10 | * notice, this list of conditions and the following disclaimer in the | |
11 | * documentation and/or other materials provided with the distribution. | |
12 | * * Neither the name of the Open Source and Linux Lab nor the | |
13 | * names of its contributors may be used to endorse or promote products | |
14 | * derived from this software without specific prior written permission. | |
15 | * | |
16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
20 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
21 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
22 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
23 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
24 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
25 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
26 | */ | |
27 | ||
07f5a258 MA |
28 | #ifndef XTENSA_CPU_H |
29 | #define XTENSA_CPU_H | |
2328826b | 30 | |
d94f0a8e | 31 | #define ALIGNED_ONLY |
2328826b | 32 | #define TARGET_LONG_BITS 32 |
2328826b | 33 | |
9fb40342 MF |
34 | /* Xtensa processors have a weak memory model */ |
35 | #define TCG_GUEST_DEFAULT_MO (0) | |
36 | ||
9349b4f9 | 37 | #define CPUArchState struct CPUXtensaState |
2328826b | 38 | |
2328826b | 39 | #include "qemu-common.h" |
da374261 | 40 | #include "cpu-qom.h" |
022c62cb | 41 | #include "exec/cpu-defs.h" |
168c12b0 | 42 | #include "xtensa-isa.h" |
2328826b | 43 | |
2328826b MF |
44 | #define NB_MMU_MODES 4 |
45 | ||
46 | #define TARGET_PHYS_ADDR_SPACE_BITS 32 | |
ba7651fb MF |
47 | #ifdef CONFIG_USER_ONLY |
48 | #define TARGET_VIRT_ADDR_SPACE_BITS 30 | |
49 | #else | |
2328826b | 50 | #define TARGET_VIRT_ADDR_SPACE_BITS 32 |
ba7651fb | 51 | #endif |
2328826b MF |
52 | #define TARGET_PAGE_BITS 12 |
53 | ||
dedc5eae MF |
54 | enum { |
55 | /* Additional instructions */ | |
56 | XTENSA_OPTION_CODE_DENSITY, | |
57 | XTENSA_OPTION_LOOP, | |
58 | XTENSA_OPTION_EXTENDED_L32R, | |
59 | XTENSA_OPTION_16_BIT_IMUL, | |
60 | XTENSA_OPTION_32_BIT_IMUL, | |
7f65f4b0 | 61 | XTENSA_OPTION_32_BIT_IMUL_HIGH, |
dedc5eae MF |
62 | XTENSA_OPTION_32_BIT_IDIV, |
63 | XTENSA_OPTION_MAC16, | |
7f65f4b0 MF |
64 | XTENSA_OPTION_MISC_OP_NSA, |
65 | XTENSA_OPTION_MISC_OP_MINMAX, | |
66 | XTENSA_OPTION_MISC_OP_SEXT, | |
67 | XTENSA_OPTION_MISC_OP_CLAMPS, | |
dedc5eae MF |
68 | XTENSA_OPTION_COPROCESSOR, |
69 | XTENSA_OPTION_BOOLEAN, | |
70 | XTENSA_OPTION_FP_COPROCESSOR, | |
71 | XTENSA_OPTION_MP_SYNCHRO, | |
72 | XTENSA_OPTION_CONDITIONAL_STORE, | |
fcc803d1 | 73 | XTENSA_OPTION_ATOMCTL, |
5eeb40c5 | 74 | XTENSA_OPTION_DEPBITS, |
dedc5eae MF |
75 | |
76 | /* Interrupts and exceptions */ | |
77 | XTENSA_OPTION_EXCEPTION, | |
78 | XTENSA_OPTION_RELOCATABLE_VECTOR, | |
79 | XTENSA_OPTION_UNALIGNED_EXCEPTION, | |
80 | XTENSA_OPTION_INTERRUPT, | |
81 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, | |
82 | XTENSA_OPTION_TIMER_INTERRUPT, | |
83 | ||
84 | /* Local memory */ | |
85 | XTENSA_OPTION_ICACHE, | |
86 | XTENSA_OPTION_ICACHE_TEST, | |
87 | XTENSA_OPTION_ICACHE_INDEX_LOCK, | |
88 | XTENSA_OPTION_DCACHE, | |
89 | XTENSA_OPTION_DCACHE_TEST, | |
90 | XTENSA_OPTION_DCACHE_INDEX_LOCK, | |
91 | XTENSA_OPTION_IRAM, | |
92 | XTENSA_OPTION_IROM, | |
93 | XTENSA_OPTION_DRAM, | |
94 | XTENSA_OPTION_DROM, | |
95 | XTENSA_OPTION_XLMI, | |
96 | XTENSA_OPTION_HW_ALIGNMENT, | |
97 | XTENSA_OPTION_MEMORY_ECC_PARITY, | |
98 | ||
99 | /* Memory protection and translation */ | |
100 | XTENSA_OPTION_REGION_PROTECTION, | |
101 | XTENSA_OPTION_REGION_TRANSLATION, | |
102 | XTENSA_OPTION_MMU, | |
4e41d2f5 | 103 | XTENSA_OPTION_CACHEATTR, |
dedc5eae MF |
104 | |
105 | /* Other */ | |
106 | XTENSA_OPTION_WINDOWED_REGISTER, | |
107 | XTENSA_OPTION_PROCESSOR_INTERFACE, | |
108 | XTENSA_OPTION_MISC_SR, | |
109 | XTENSA_OPTION_THREAD_POINTER, | |
110 | XTENSA_OPTION_PROCESSOR_ID, | |
111 | XTENSA_OPTION_DEBUG, | |
112 | XTENSA_OPTION_TRACE_PORT, | |
3a3c9dc4 | 113 | XTENSA_OPTION_EXTERN_REGS, |
dedc5eae MF |
114 | }; |
115 | ||
2af3da91 | 116 | enum { |
e9872741 | 117 | EXPSTATE = 230, |
2af3da91 MF |
118 | THREADPTR = 231, |
119 | FCR = 232, | |
120 | FSR = 233, | |
121 | }; | |
122 | ||
3580ecad | 123 | enum { |
797d780b MF |
124 | LBEG = 0, |
125 | LEND = 1, | |
126 | LCOUNT = 2, | |
3580ecad | 127 | SAR = 3, |
4dd85b6b | 128 | BR = 4, |
6ad6dbf7 | 129 | LITBASE = 5, |
809377aa | 130 | SCOMPARE1 = 12, |
6825b6c3 MF |
131 | ACCLO = 16, |
132 | ACCHI = 17, | |
133 | MR = 32, | |
553e44f9 MF |
134 | WINDOW_BASE = 72, |
135 | WINDOW_START = 73, | |
b67ea0cd | 136 | PTEVADDR = 83, |
13f6a7cd | 137 | MMID = 89, |
b67ea0cd MF |
138 | RASID = 90, |
139 | ITLBCFG = 91, | |
140 | DTLBCFG = 92, | |
e61dc8f7 | 141 | IBREAKENABLE = 96, |
9e03ade4 | 142 | MEMCTL = 97, |
4e41d2f5 | 143 | CACHEATTR = 98, |
fcc803d1 | 144 | ATOMCTL = 99, |
13f6a7cd | 145 | DDR = 104, |
e61dc8f7 | 146 | IBREAKA = 128, |
f14c4b5f MF |
147 | DBREAKA = 144, |
148 | DBREAKC = 160, | |
604e1f9c | 149 | CONFIGID0 = 176, |
40643d7c MF |
150 | EPC1 = 177, |
151 | DEPC = 192, | |
b994e91b | 152 | EPS2 = 194, |
604e1f9c | 153 | CONFIGID1 = 208, |
40643d7c | 154 | EXCSAVE1 = 209, |
f3df4c04 | 155 | CPENABLE = 224, |
b994e91b MF |
156 | INTSET = 226, |
157 | INTCLEAR = 227, | |
158 | INTENABLE = 228, | |
f0a548b9 | 159 | PS = 230, |
97836cee | 160 | VECBASE = 231, |
40643d7c | 161 | EXCCAUSE = 232, |
ab58c5b4 | 162 | DEBUGCAUSE = 233, |
b994e91b | 163 | CCOUNT = 234, |
f3df4c04 | 164 | PRID = 235, |
35b5c044 MF |
165 | ICOUNT = 236, |
166 | ICOUNTLEVEL = 237, | |
40643d7c | 167 | EXCVADDR = 238, |
b994e91b | 168 | CCOMPARE = 240, |
b7909d81 | 169 | MISC = 244, |
3580ecad MF |
170 | }; |
171 | ||
f0a548b9 MF |
172 | #define PS_INTLEVEL 0xf |
173 | #define PS_INTLEVEL_SHIFT 0 | |
174 | ||
175 | #define PS_EXCM 0x10 | |
176 | #define PS_UM 0x20 | |
177 | ||
178 | #define PS_RING 0xc0 | |
179 | #define PS_RING_SHIFT 6 | |
180 | ||
181 | #define PS_OWB 0xf00 | |
182 | #define PS_OWB_SHIFT 8 | |
ba7651fb | 183 | #define PS_OWB_LEN 4 |
f0a548b9 MF |
184 | |
185 | #define PS_CALLINC 0x30000 | |
186 | #define PS_CALLINC_SHIFT 16 | |
187 | #define PS_CALLINC_LEN 2 | |
188 | ||
189 | #define PS_WOE 0x40000 | |
190 | ||
ab58c5b4 MF |
191 | #define DEBUGCAUSE_IC 0x1 |
192 | #define DEBUGCAUSE_IB 0x2 | |
193 | #define DEBUGCAUSE_DB 0x4 | |
194 | #define DEBUGCAUSE_BI 0x8 | |
195 | #define DEBUGCAUSE_BN 0x10 | |
196 | #define DEBUGCAUSE_DI 0x20 | |
197 | #define DEBUGCAUSE_DBNUM 0xf00 | |
198 | #define DEBUGCAUSE_DBNUM_SHIFT 8 | |
199 | ||
f14c4b5f MF |
200 | #define DBREAKC_SB 0x80000000 |
201 | #define DBREAKC_LB 0x40000000 | |
202 | #define DBREAKC_SB_LB (DBREAKC_SB | DBREAKC_LB) | |
203 | #define DBREAKC_MASK 0x3f | |
204 | ||
9e03ade4 MF |
205 | #define MEMCTL_INIT 0x00800000 |
206 | #define MEMCTL_IUSEWAYS_SHIFT 18 | |
207 | #define MEMCTL_IUSEWAYS_LEN 5 | |
208 | #define MEMCTL_IUSEWAYS_MASK 0x007c0000 | |
209 | #define MEMCTL_DALLOCWAYS_SHIFT 13 | |
210 | #define MEMCTL_DALLOCWAYS_LEN 5 | |
211 | #define MEMCTL_DALLOCWAYS_MASK 0x0003e000 | |
212 | #define MEMCTL_DUSEWAYS_SHIFT 8 | |
213 | #define MEMCTL_DUSEWAYS_LEN 5 | |
214 | #define MEMCTL_DUSEWAYS_MASK 0x00001f00 | |
215 | #define MEMCTL_ISNP 0x4 | |
216 | #define MEMCTL_DSNP 0x2 | |
217 | #define MEMCTL_IL0EN 0x1 | |
218 | ||
168c12b0 MF |
219 | #define MAX_INSN_LENGTH 64 |
220 | #define MAX_OPCODE_ARGS 16 | |
553e44f9 | 221 | #define MAX_NAREG 64 |
b994e91b MF |
222 | #define MAX_NINTERRUPT 32 |
223 | #define MAX_NLEVEL 6 | |
224 | #define MAX_NNMI 1 | |
225 | #define MAX_NCCOMPARE 3 | |
b67ea0cd | 226 | #define MAX_TLB_WAY_SIZE 8 |
f14c4b5f | 227 | #define MAX_NDBREAK 2 |
b68755c1 | 228 | #define MAX_NMEMORY 4 |
b67ea0cd MF |
229 | |
230 | #define REGION_PAGE_MASK 0xe0000000 | |
553e44f9 | 231 | |
fcc803d1 MF |
232 | #define PAGE_CACHE_MASK 0x700 |
233 | #define PAGE_CACHE_SHIFT 8 | |
234 | #define PAGE_CACHE_INVALID 0x000 | |
235 | #define PAGE_CACHE_BYPASS 0x100 | |
236 | #define PAGE_CACHE_WT 0x200 | |
237 | #define PAGE_CACHE_WB 0x400 | |
238 | #define PAGE_CACHE_ISOLATE 0x600 | |
239 | ||
40643d7c MF |
240 | enum { |
241 | /* Static vectors */ | |
17ab14ac MF |
242 | EXC_RESET0, |
243 | EXC_RESET1, | |
40643d7c MF |
244 | EXC_MEMORY_ERROR, |
245 | ||
246 | /* Dynamic vectors */ | |
247 | EXC_WINDOW_OVERFLOW4, | |
248 | EXC_WINDOW_UNDERFLOW4, | |
249 | EXC_WINDOW_OVERFLOW8, | |
250 | EXC_WINDOW_UNDERFLOW8, | |
251 | EXC_WINDOW_OVERFLOW12, | |
252 | EXC_WINDOW_UNDERFLOW12, | |
253 | EXC_IRQ, | |
254 | EXC_KERNEL, | |
255 | EXC_USER, | |
256 | EXC_DOUBLE, | |
e61dc8f7 | 257 | EXC_DEBUG, |
40643d7c MF |
258 | EXC_MAX |
259 | }; | |
260 | ||
261 | enum { | |
262 | ILLEGAL_INSTRUCTION_CAUSE = 0, | |
263 | SYSCALL_CAUSE, | |
264 | INSTRUCTION_FETCH_ERROR_CAUSE, | |
265 | LOAD_STORE_ERROR_CAUSE, | |
266 | LEVEL1_INTERRUPT_CAUSE, | |
267 | ALLOCA_CAUSE, | |
268 | INTEGER_DIVIDE_BY_ZERO_CAUSE, | |
269 | PRIVILEGED_CAUSE = 8, | |
270 | LOAD_STORE_ALIGNMENT_CAUSE, | |
271 | ||
272 | INSTR_PIF_DATA_ERROR_CAUSE = 12, | |
273 | LOAD_STORE_PIF_DATA_ERROR_CAUSE, | |
274 | INSTR_PIF_ADDR_ERROR_CAUSE, | |
275 | LOAD_STORE_PIF_ADDR_ERROR_CAUSE, | |
276 | ||
277 | INST_TLB_MISS_CAUSE, | |
278 | INST_TLB_MULTI_HIT_CAUSE, | |
279 | INST_FETCH_PRIVILEGE_CAUSE, | |
280 | INST_FETCH_PROHIBITED_CAUSE = 20, | |
281 | LOAD_STORE_TLB_MISS_CAUSE = 24, | |
282 | LOAD_STORE_TLB_MULTI_HIT_CAUSE, | |
283 | LOAD_STORE_PRIVILEGE_CAUSE, | |
284 | LOAD_PROHIBITED_CAUSE = 28, | |
285 | STORE_PROHIBITED_CAUSE, | |
286 | ||
287 | COPROCESSOR0_DISABLED = 32, | |
288 | }; | |
289 | ||
b994e91b MF |
290 | typedef enum { |
291 | INTTYPE_LEVEL, | |
292 | INTTYPE_EDGE, | |
293 | INTTYPE_NMI, | |
294 | INTTYPE_SOFTWARE, | |
295 | INTTYPE_TIMER, | |
296 | INTTYPE_DEBUG, | |
297 | INTTYPE_WRITE_ERR, | |
dec71d2d | 298 | INTTYPE_PROFILING, |
b994e91b MF |
299 | INTTYPE_MAX |
300 | } interrupt_type; | |
301 | ||
59a71f75 MF |
302 | struct CPUXtensaState; |
303 | ||
b67ea0cd MF |
304 | typedef struct xtensa_tlb_entry { |
305 | uint32_t vaddr; | |
306 | uint32_t paddr; | |
307 | uint8_t asid; | |
308 | uint8_t attr; | |
309 | bool variable; | |
310 | } xtensa_tlb_entry; | |
311 | ||
312 | typedef struct xtensa_tlb { | |
313 | unsigned nways; | |
314 | const unsigned way_size[10]; | |
315 | bool varway56; | |
316 | unsigned nrefillentries; | |
317 | } xtensa_tlb; | |
318 | ||
ccfcaba6 MF |
319 | typedef struct XtensaGdbReg { |
320 | int targno; | |
1b7b26e4 | 321 | unsigned flags; |
ccfcaba6 MF |
322 | int type; |
323 | int group; | |
ddd44279 | 324 | unsigned size; |
ccfcaba6 MF |
325 | } XtensaGdbReg; |
326 | ||
327 | typedef struct XtensaGdbRegmap { | |
328 | int num_regs; | |
329 | int num_core_regs; | |
330 | /* PC + a + ar + sr + ur */ | |
331 | XtensaGdbReg reg[1 + 16 + 64 + 256 + 256]; | |
332 | } XtensaGdbRegmap; | |
333 | ||
59a71f75 MF |
334 | typedef struct XtensaCcompareTimer { |
335 | struct CPUXtensaState *env; | |
336 | QEMUTimer *timer; | |
337 | } XtensaCcompareTimer; | |
338 | ||
b68755c1 MF |
339 | typedef struct XtensaMemory { |
340 | unsigned num; | |
341 | struct XtensaMemoryRegion { | |
342 | uint32_t addr; | |
343 | uint32_t size; | |
344 | } location[MAX_NMEMORY]; | |
345 | } XtensaMemory; | |
346 | ||
168c12b0 MF |
347 | typedef struct DisasContext DisasContext; |
348 | typedef void (*XtensaOpcodeOp)(DisasContext *dc, const uint32_t arg[], | |
349 | const uint32_t par[]); | |
350 | ||
351 | typedef struct XtensaOpcodeOps { | |
352 | const char *name; | |
353 | XtensaOpcodeOp translate; | |
354 | const uint32_t *par; | |
355 | } XtensaOpcodeOps; | |
356 | ||
357 | typedef struct XtensaOpcodeTranslators { | |
358 | unsigned num_opcodes; | |
359 | const XtensaOpcodeOps *opcode; | |
360 | } XtensaOpcodeTranslators; | |
361 | ||
362 | extern const XtensaOpcodeTranslators xtensa_core_opcodes; | |
c04e1692 | 363 | extern const XtensaOpcodeTranslators xtensa_fpu2000_opcodes; |
168c12b0 | 364 | |
da374261 | 365 | struct XtensaConfig { |
dedc5eae MF |
366 | const char *name; |
367 | uint64_t options; | |
ccfcaba6 | 368 | XtensaGdbRegmap gdb_regmap; |
553e44f9 | 369 | unsigned nareg; |
40643d7c MF |
370 | int excm_level; |
371 | int ndepc; | |
97836cee | 372 | uint32_t vecbase; |
40643d7c | 373 | uint32_t exception_vector[EXC_MAX]; |
b994e91b MF |
374 | unsigned ninterrupt; |
375 | unsigned nlevel; | |
376 | uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1]; | |
377 | uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1]; | |
378 | uint32_t inttype_mask[INTTYPE_MAX]; | |
379 | struct { | |
380 | uint32_t level; | |
381 | interrupt_type inttype; | |
382 | } interrupt[MAX_NINTERRUPT]; | |
383 | unsigned nccompare; | |
384 | uint32_t timerint[MAX_NCCOMPARE]; | |
b8929a54 MF |
385 | unsigned nextint; |
386 | unsigned extint[MAX_NINTERRUPT]; | |
ab58c5b4 MF |
387 | |
388 | unsigned debug_level; | |
389 | unsigned nibreak; | |
390 | unsigned ndbreak; | |
391 | ||
9e03ade4 MF |
392 | unsigned icache_ways; |
393 | unsigned dcache_ways; | |
394 | uint32_t memctl_mask; | |
395 | ||
b68755c1 MF |
396 | XtensaMemory instrom; |
397 | XtensaMemory instram; | |
398 | XtensaMemory datarom; | |
399 | XtensaMemory dataram; | |
400 | XtensaMemory sysrom; | |
401 | XtensaMemory sysram; | |
402 | ||
604e1f9c MF |
403 | uint32_t configid[2]; |
404 | ||
168c12b0 | 405 | void *isa_internal; |
33071f68 MF |
406 | xtensa_isa isa; |
407 | XtensaOpcodeOps **opcode_ops; | |
408 | const XtensaOpcodeTranslators **opcode_translators; | |
168c12b0 | 409 | |
b994e91b | 410 | uint32_t clock_freq_khz; |
b67ea0cd MF |
411 | |
412 | xtensa_tlb itlb; | |
413 | xtensa_tlb dtlb; | |
da374261 | 414 | }; |
dedc5eae | 415 | |
ac8b7db4 MF |
416 | typedef struct XtensaConfigList { |
417 | const XtensaConfig *config; | |
418 | struct XtensaConfigList *next; | |
419 | } XtensaConfigList; | |
420 | ||
ddd44279 MF |
421 | #ifdef HOST_WORDS_BIGENDIAN |
422 | enum { | |
423 | FP_F32_HIGH, | |
424 | FP_F32_LOW, | |
425 | }; | |
426 | #else | |
427 | enum { | |
428 | FP_F32_LOW, | |
429 | FP_F32_HIGH, | |
430 | }; | |
431 | #endif | |
432 | ||
2328826b | 433 | typedef struct CPUXtensaState { |
dedc5eae | 434 | const XtensaConfig *config; |
2328826b MF |
435 | uint32_t regs[16]; |
436 | uint32_t pc; | |
437 | uint32_t sregs[256]; | |
2af3da91 | 438 | uint32_t uregs[256]; |
553e44f9 | 439 | uint32_t phys_regs[MAX_NAREG]; |
ddd44279 MF |
440 | union { |
441 | float32 f32[2]; | |
442 | float64 f64; | |
443 | } fregs[16]; | |
dd519cbe | 444 | float_status fp_status; |
2328826b | 445 | |
ba7651fb | 446 | #ifndef CONFIG_USER_ONLY |
b67ea0cd MF |
447 | xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE]; |
448 | xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE]; | |
449 | unsigned autorefill_idx; | |
bd527a83 | 450 | bool runstall; |
3a3c9dc4 MF |
451 | AddressSpace *address_space_er; |
452 | MemoryRegion *system_er; | |
b994e91b MF |
453 | int pending_irq_level; /* level of last raised IRQ */ |
454 | void **irq_inputs; | |
59a71f75 MF |
455 | XtensaCcompareTimer ccompare[MAX_NCCOMPARE]; |
456 | uint64_t time_base; | |
457 | uint64_t ccount_time; | |
458 | uint32_t ccount_base; | |
ba7651fb | 459 | #endif |
b994e91b | 460 | |
40643d7c | 461 | int exception_taken; |
d2132510 | 462 | int yield_needed; |
17ab14ac | 463 | unsigned static_vectors; |
40643d7c | 464 | |
f14c4b5f | 465 | /* Watchpoints for DBREAK registers */ |
ff4700b0 | 466 | struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK]; |
f14c4b5f | 467 | |
2328826b MF |
468 | CPU_COMMON |
469 | } CPUXtensaState; | |
470 | ||
da374261 PB |
471 | /** |
472 | * XtensaCPU: | |
473 | * @env: #CPUXtensaState | |
474 | * | |
475 | * An Xtensa CPU. | |
476 | */ | |
477 | struct XtensaCPU { | |
478 | /*< private >*/ | |
479 | CPUState parent_obj; | |
480 | /*< public >*/ | |
481 | ||
482 | CPUXtensaState env; | |
483 | }; | |
484 | ||
485 | static inline XtensaCPU *xtensa_env_get_cpu(const CPUXtensaState *env) | |
486 | { | |
487 | return container_of(env, XtensaCPU, env); | |
488 | } | |
489 | ||
490 | #define ENV_GET_CPU(e) CPU(xtensa_env_get_cpu(e)) | |
491 | ||
492 | #define ENV_OFFSET offsetof(XtensaCPU, env) | |
493 | ||
ba7651fb MF |
494 | |
495 | int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int size, | |
496 | int mmu_idx); | |
da374261 PB |
497 | void xtensa_cpu_do_interrupt(CPUState *cpu); |
498 | bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request); | |
499 | void xtensa_cpu_do_unassigned_access(CPUState *cpu, hwaddr addr, | |
500 | bool is_write, bool is_exec, int opaque, | |
501 | unsigned size); | |
502 | void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, | |
503 | fprintf_function cpu_fprintf, int flags); | |
504 | hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); | |
505 | int xtensa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); | |
506 | int xtensa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); | |
507 | void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, | |
b35399bb SS |
508 | MMUAccessType access_type, |
509 | int mmu_idx, uintptr_t retaddr); | |
15be3171 | 510 | |
2328826b MF |
511 | #define cpu_signal_handler cpu_xtensa_signal_handler |
512 | #define cpu_list xtensa_cpu_list | |
513 | ||
a5247d76 IM |
514 | #define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU |
515 | #define XTENSA_CPU_TYPE_NAME(model) model XTENSA_CPU_TYPE_SUFFIX | |
0dacec87 | 516 | #define CPU_RESOLVING_TYPE TYPE_XTENSA_CPU |
a5247d76 | 517 | |
e38077ff MF |
518 | #ifdef TARGET_WORDS_BIGENDIAN |
519 | #define XTENSA_DEFAULT_CPU_MODEL "fsf" | |
a3c5e49d | 520 | #define XTENSA_DEFAULT_CPU_NOMMU_MODEL "fsf" |
e38077ff MF |
521 | #else |
522 | #define XTENSA_DEFAULT_CPU_MODEL "dc232b" | |
a3c5e49d | 523 | #define XTENSA_DEFAULT_CPU_NOMMU_MODEL "de212" |
e38077ff | 524 | #endif |
a3c5e49d MF |
525 | #define XTENSA_DEFAULT_CPU_TYPE \ |
526 | XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_MODEL) | |
527 | #define XTENSA_DEFAULT_CPU_NOMMU_TYPE \ | |
528 | XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_NOMMU_MODEL) | |
e38077ff | 529 | |
2328826b | 530 | void xtensa_translate_init(void); |
86025ee4 | 531 | void xtensa_breakpoint_handler(CPUState *cs); |
1479073b | 532 | void xtensa_finalize_config(XtensaConfig *config); |
ac8b7db4 | 533 | void xtensa_register_core(XtensaConfigList *node); |
8128b3e0 | 534 | void xtensa_sim_open_console(Chardev *chr); |
b994e91b | 535 | void check_interrupts(CPUXtensaState *s); |
97129ac8 AF |
536 | void xtensa_irq_init(CPUXtensaState *env); |
537 | void *xtensa_get_extint(CPUXtensaState *env, unsigned extint); | |
97129ac8 | 538 | void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active); |
2328826b MF |
539 | int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc); |
540 | void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf); | |
97129ac8 AF |
541 | void xtensa_sync_window_from_phys(CPUXtensaState *env); |
542 | void xtensa_sync_phys_from_window(CPUXtensaState *env); | |
ba7651fb MF |
543 | void xtensa_rotate_window(CPUXtensaState *env, uint32_t delta); |
544 | void xtensa_restore_owb(CPUXtensaState *env); | |
97129ac8 | 545 | void debug_exception_env(CPUXtensaState *new_env, uint32_t cause); |
b67ea0cd | 546 | |
17ab14ac MF |
547 | static inline void xtensa_select_static_vectors(CPUXtensaState *env, |
548 | unsigned n) | |
549 | { | |
550 | assert(n < 2); | |
551 | env->static_vectors = n; | |
552 | } | |
bd527a83 | 553 | void xtensa_runstall(CPUXtensaState *env, bool runstall); |
168c12b0 MF |
554 | XtensaOpcodeOps *xtensa_find_opcode_ops(const XtensaOpcodeTranslators *t, |
555 | const char *opcode); | |
2328826b | 556 | |
dedc5eae | 557 | #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt)) |
fe0bd475 | 558 | #define XTENSA_OPTION_ALL (~(uint64_t)0) |
dedc5eae | 559 | |
b67ea0cd MF |
560 | static inline bool xtensa_option_bits_enabled(const XtensaConfig *config, |
561 | uint64_t opt) | |
562 | { | |
563 | return (config->options & opt) != 0; | |
564 | } | |
565 | ||
dedc5eae MF |
566 | static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt) |
567 | { | |
b67ea0cd | 568 | return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt)); |
dedc5eae MF |
569 | } |
570 | ||
97129ac8 | 571 | static inline int xtensa_get_cintlevel(const CPUXtensaState *env) |
40643d7c MF |
572 | { |
573 | int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT; | |
574 | if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) { | |
575 | level = env->config->excm_level; | |
576 | } | |
577 | return level; | |
578 | } | |
579 | ||
97129ac8 | 580 | static inline int xtensa_get_ring(const CPUXtensaState *env) |
f0a548b9 MF |
581 | { |
582 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { | |
583 | return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT; | |
584 | } else { | |
585 | return 0; | |
586 | } | |
587 | } | |
588 | ||
97129ac8 | 589 | static inline int xtensa_get_cring(const CPUXtensaState *env) |
f0a548b9 MF |
590 | { |
591 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) && | |
592 | (env->sregs[PS] & PS_EXCM) == 0) { | |
593 | return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT; | |
594 | } else { | |
595 | return 0; | |
596 | } | |
597 | } | |
598 | ||
ba7651fb MF |
599 | #ifndef CONFIG_USER_ONLY |
600 | uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, | |
601 | bool dtlb, uint32_t way); | |
602 | void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb, | |
603 | uint32_t *vpn, uint32_t wi, uint32_t *ei); | |
604 | int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb, | |
605 | uint32_t *pwi, uint32_t *pei, uint8_t *pring); | |
606 | void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env, | |
607 | xtensa_tlb_entry *entry, bool dtlb, | |
608 | unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte); | |
609 | void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb, | |
610 | unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte); | |
611 | int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb, | |
612 | uint32_t vaddr, int is_write, int mmu_idx, | |
613 | uint32_t *paddr, uint32_t *page_size, unsigned *access); | |
614 | void reset_mmu(CPUXtensaState *env); | |
615 | void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env); | |
616 | ||
617 | static inline MemoryRegion *xtensa_get_er_region(CPUXtensaState *env) | |
618 | { | |
619 | return env->system_er; | |
620 | } | |
621 | ||
97129ac8 | 622 | static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env, |
b67ea0cd MF |
623 | bool dtlb, unsigned wi, unsigned ei) |
624 | { | |
625 | return dtlb ? | |
626 | env->dtlb[wi] + ei : | |
627 | env->itlb[wi] + ei; | |
628 | } | |
ba7651fb | 629 | #endif |
b67ea0cd | 630 | |
1b3e71f8 MF |
631 | static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env) |
632 | { | |
633 | return env->sregs[WINDOW_START] | | |
634 | (env->sregs[WINDOW_START] << env->config->nareg / 4); | |
635 | } | |
636 | ||
f0a548b9 MF |
637 | /* MMU modes definitions */ |
638 | #define MMU_MODE0_SUFFIX _ring0 | |
639 | #define MMU_MODE1_SUFFIX _ring1 | |
640 | #define MMU_MODE2_SUFFIX _ring2 | |
641 | #define MMU_MODE3_SUFFIX _ring3 | |
ba7651fb | 642 | #define MMU_USER_IDX 3 |
f0a548b9 | 643 | |
97ed5ccd | 644 | static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch) |
2328826b | 645 | { |
f0a548b9 | 646 | return xtensa_get_cring(env); |
2328826b MF |
647 | } |
648 | ||
f0a548b9 MF |
649 | #define XTENSA_TBFLAG_RING_MASK 0x3 |
650 | #define XTENSA_TBFLAG_EXCM 0x4 | |
6ad6dbf7 | 651 | #define XTENSA_TBFLAG_LITBASE 0x8 |
e61dc8f7 | 652 | #define XTENSA_TBFLAG_DEBUG 0x10 |
35b5c044 | 653 | #define XTENSA_TBFLAG_ICOUNT 0x20 |
ef04a846 MF |
654 | #define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0 |
655 | #define XTENSA_TBFLAG_CPENABLE_SHIFT 6 | |
a00817cc | 656 | #define XTENSA_TBFLAG_EXCEPTION 0x4000 |
2db59a76 MF |
657 | #define XTENSA_TBFLAG_WINDOW_MASK 0x18000 |
658 | #define XTENSA_TBFLAG_WINDOW_SHIFT 15 | |
d2132510 | 659 | #define XTENSA_TBFLAG_YIELD 0x20000 |
f0a548b9 | 660 | |
97129ac8 | 661 | static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc, |
89fee74a | 662 | target_ulong *cs_base, uint32_t *flags) |
2328826b | 663 | { |
1cf5ccbc AF |
664 | CPUState *cs = CPU(xtensa_env_get_cpu(env)); |
665 | ||
2328826b MF |
666 | *pc = env->pc; |
667 | *cs_base = 0; | |
668 | *flags = 0; | |
f0a548b9 MF |
669 | *flags |= xtensa_get_ring(env); |
670 | if (env->sregs[PS] & PS_EXCM) { | |
671 | *flags |= XTENSA_TBFLAG_EXCM; | |
672 | } | |
6ad6dbf7 MF |
673 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) && |
674 | (env->sregs[LITBASE] & 1)) { | |
675 | *flags |= XTENSA_TBFLAG_LITBASE; | |
676 | } | |
e61dc8f7 MF |
677 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) { |
678 | if (xtensa_get_cintlevel(env) < env->config->debug_level) { | |
679 | *flags |= XTENSA_TBFLAG_DEBUG; | |
680 | } | |
35b5c044 MF |
681 | if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) { |
682 | *flags |= XTENSA_TBFLAG_ICOUNT; | |
683 | } | |
e61dc8f7 | 684 | } |
ef04a846 MF |
685 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) { |
686 | *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT; | |
687 | } | |
1cf5ccbc | 688 | if (cs->singlestep_enabled && env->exception_taken) { |
a00817cc MF |
689 | *flags |= XTENSA_TBFLAG_EXCEPTION; |
690 | } | |
2db59a76 MF |
691 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) && |
692 | (env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) { | |
693 | uint32_t windowstart = xtensa_replicate_windowstart(env) >> | |
694 | (env->sregs[WINDOW_BASE] + 1); | |
695 | uint32_t w = ctz32(windowstart | 0x8); | |
696 | ||
697 | *flags |= w << XTENSA_TBFLAG_WINDOW_SHIFT; | |
698 | } else { | |
699 | *flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT; | |
700 | } | |
d2132510 MF |
701 | if (env->yield_needed) { |
702 | *flags |= XTENSA_TBFLAG_YIELD; | |
703 | } | |
2328826b MF |
704 | } |
705 | ||
022c62cb | 706 | #include "exec/cpu-all.h" |
2328826b | 707 | |
2328826b | 708 | #endif |