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dec9c2d4 AF |
1 | /* |
2 | * QEMU ARM CPU | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | ||
778c3a06 | 21 | #include "cpu.h" |
dec9c2d4 | 22 | #include "qemu-common.h" |
3c30dd5a PM |
23 | #if !defined(CONFIG_USER_ONLY) |
24 | #include "hw/loader.h" | |
25 | #endif | |
7c1840b6 | 26 | #include "hw/arm/arm.h" |
9c17d615 | 27 | #include "sysemu/sysemu.h" |
7c1840b6 | 28 | #include "sysemu/kvm.h" |
dec9c2d4 | 29 | |
f45748f1 AF |
30 | static void arm_cpu_set_pc(CPUState *cs, vaddr value) |
31 | { | |
32 | ARMCPU *cpu = ARM_CPU(cs); | |
33 | ||
34 | cpu->env.regs[15] = value; | |
35 | } | |
36 | ||
4b6a83fb PM |
37 | static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) |
38 | { | |
39 | /* Reset a single ARMCPRegInfo register */ | |
40 | ARMCPRegInfo *ri = value; | |
41 | ARMCPU *cpu = opaque; | |
42 | ||
43 | if (ri->type & ARM_CP_SPECIAL) { | |
44 | return; | |
45 | } | |
46 | ||
47 | if (ri->resetfn) { | |
48 | ri->resetfn(&cpu->env, ri); | |
49 | return; | |
50 | } | |
51 | ||
52 | /* A zero offset is never possible as it would be regs[0] | |
53 | * so we use it to indicate that reset is being handled elsewhere. | |
54 | * This is basically only used for fields in non-core coprocessors | |
55 | * (like the pxa2xx ones). | |
56 | */ | |
57 | if (!ri->fieldoffset) { | |
58 | return; | |
59 | } | |
60 | ||
61 | if (ri->type & ARM_CP_64BIT) { | |
62 | CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; | |
63 | } else { | |
64 | CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; | |
65 | } | |
66 | } | |
67 | ||
dec9c2d4 AF |
68 | /* CPUClass::reset() */ |
69 | static void arm_cpu_reset(CPUState *s) | |
70 | { | |
71 | ARMCPU *cpu = ARM_CPU(s); | |
72 | ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); | |
3c30dd5a | 73 | CPUARMState *env = &cpu->env; |
3c30dd5a | 74 | |
dec9c2d4 AF |
75 | acc->parent_reset(s); |
76 | ||
3c30dd5a | 77 | memset(env, 0, offsetof(CPUARMState, breakpoints)); |
4b6a83fb | 78 | g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); |
3c30dd5a PM |
79 | env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; |
80 | env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; | |
81 | env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; | |
3c30dd5a PM |
82 | |
83 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | |
84 | env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; | |
85 | } | |
86 | ||
3926cc84 AG |
87 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
88 | /* 64 bit CPUs always start in 64 bit mode */ | |
89 | env->aarch64 = 1; | |
90 | } | |
91 | ||
3c30dd5a PM |
92 | #if defined(CONFIG_USER_ONLY) |
93 | env->uncached_cpsr = ARM_CPU_MODE_USR; | |
94 | /* For user mode we must enable access to coprocessors */ | |
95 | env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; | |
96 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | |
97 | env->cp15.c15_cpar = 3; | |
98 | } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
99 | env->cp15.c15_cpar = 1; | |
100 | } | |
101 | #else | |
102 | /* SVC mode with interrupts disabled. */ | |
103 | env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I; | |
104 | /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is | |
105 | clear at reset. Initial SP and PC are loaded from ROM. */ | |
106 | if (IS_M(env)) { | |
107 | uint32_t pc; | |
108 | uint8_t *rom; | |
109 | env->uncached_cpsr &= ~CPSR_I; | |
110 | rom = rom_ptr(0); | |
111 | if (rom) { | |
112 | /* We should really use ldl_phys here, in case the guest | |
113 | modified flash and reset itself. However images | |
114 | loaded via -kernel have not been copied yet, so load the | |
115 | values directly from there. */ | |
f62cafd4 | 116 | env->regs[13] = ldl_p(rom) & 0xFFFFFFFC; |
3c30dd5a PM |
117 | pc = ldl_p(rom + 4); |
118 | env->thumb = pc & 1; | |
119 | env->regs[15] = pc & ~1; | |
120 | } | |
121 | } | |
122 | env->vfp.xregs[ARM_VFP_FPEXC] = 0; | |
3c30dd5a PM |
123 | #endif |
124 | set_flush_to_zero(1, &env->vfp.standard_fp_status); | |
125 | set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); | |
126 | set_default_nan_mode(1, &env->vfp.standard_fp_status); | |
127 | set_float_detect_tininess(float_tininess_before_rounding, | |
128 | &env->vfp.fp_status); | |
129 | set_float_detect_tininess(float_tininess_before_rounding, | |
130 | &env->vfp.standard_fp_status); | |
131 | tlb_flush(env, 1); | |
132 | /* Reset is a state change for some CPUARMState fields which we | |
133 | * bake assumptions about into translated code, so we need to | |
134 | * tb_flush(). | |
135 | */ | |
136 | tb_flush(env); | |
dec9c2d4 AF |
137 | } |
138 | ||
7c1840b6 PM |
139 | #ifndef CONFIG_USER_ONLY |
140 | static void arm_cpu_set_irq(void *opaque, int irq, int level) | |
141 | { | |
142 | ARMCPU *cpu = opaque; | |
143 | CPUState *cs = CPU(cpu); | |
144 | ||
145 | switch (irq) { | |
146 | case ARM_CPU_IRQ: | |
147 | if (level) { | |
148 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); | |
149 | } else { | |
150 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); | |
151 | } | |
152 | break; | |
153 | case ARM_CPU_FIQ: | |
154 | if (level) { | |
155 | cpu_interrupt(cs, CPU_INTERRUPT_FIQ); | |
156 | } else { | |
157 | cpu_reset_interrupt(cs, CPU_INTERRUPT_FIQ); | |
158 | } | |
159 | break; | |
160 | default: | |
161 | hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq); | |
162 | } | |
163 | } | |
164 | ||
165 | static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) | |
166 | { | |
167 | #ifdef CONFIG_KVM | |
168 | ARMCPU *cpu = opaque; | |
169 | CPUState *cs = CPU(cpu); | |
170 | int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; | |
171 | ||
172 | switch (irq) { | |
173 | case ARM_CPU_IRQ: | |
174 | kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; | |
175 | break; | |
176 | case ARM_CPU_FIQ: | |
177 | kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; | |
178 | break; | |
179 | default: | |
180 | hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq); | |
181 | } | |
182 | kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; | |
183 | kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); | |
184 | #endif | |
185 | } | |
186 | #endif | |
187 | ||
581be094 PM |
188 | static inline void set_feature(CPUARMState *env, int feature) |
189 | { | |
918f5dca | 190 | env->features |= 1ULL << feature; |
581be094 PM |
191 | } |
192 | ||
777dc784 PM |
193 | static void arm_cpu_initfn(Object *obj) |
194 | { | |
c05efcb1 | 195 | CPUState *cs = CPU(obj); |
777dc784 | 196 | ARMCPU *cpu = ARM_CPU(obj); |
79614b78 | 197 | static bool inited; |
777dc784 | 198 | |
c05efcb1 | 199 | cs->env_ptr = &cpu->env; |
777dc784 | 200 | cpu_exec_init(&cpu->env); |
4b6a83fb PM |
201 | cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, |
202 | g_free, g_free); | |
79614b78 | 203 | |
7c1840b6 PM |
204 | #ifndef CONFIG_USER_ONLY |
205 | /* Our inbound IRQ and FIQ lines */ | |
206 | if (kvm_enabled()) { | |
207 | qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 2); | |
208 | } else { | |
209 | qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 2); | |
210 | } | |
55d284af | 211 | |
bc72ad67 | 212 | cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, |
55d284af | 213 | arm_gt_ptimer_cb, cpu); |
bc72ad67 | 214 | cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, |
55d284af PM |
215 | arm_gt_vtimer_cb, cpu); |
216 | qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, | |
217 | ARRAY_SIZE(cpu->gt_timer_outputs)); | |
7c1840b6 PM |
218 | #endif |
219 | ||
79614b78 AF |
220 | if (tcg_enabled() && !inited) { |
221 | inited = true; | |
222 | arm_translate_init(); | |
223 | } | |
4b6a83fb PM |
224 | } |
225 | ||
226 | static void arm_cpu_finalizefn(Object *obj) | |
227 | { | |
228 | ARMCPU *cpu = ARM_CPU(obj); | |
229 | g_hash_table_destroy(cpu->cp_regs); | |
777dc784 PM |
230 | } |
231 | ||
14969266 | 232 | static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
581be094 | 233 | { |
14a10fc3 | 234 | CPUState *cs = CPU(dev); |
14969266 AF |
235 | ARMCPU *cpu = ARM_CPU(dev); |
236 | ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); | |
581be094 | 237 | CPUARMState *env = &cpu->env; |
14969266 | 238 | |
581be094 | 239 | /* Some features automatically imply others: */ |
81e69fb0 MR |
240 | if (arm_feature(env, ARM_FEATURE_V8)) { |
241 | set_feature(env, ARM_FEATURE_V7); | |
242 | set_feature(env, ARM_FEATURE_ARM_DIV); | |
243 | set_feature(env, ARM_FEATURE_LPAE); | |
244 | } | |
581be094 PM |
245 | if (arm_feature(env, ARM_FEATURE_V7)) { |
246 | set_feature(env, ARM_FEATURE_VAPA); | |
247 | set_feature(env, ARM_FEATURE_THUMB2); | |
81bdde9d | 248 | set_feature(env, ARM_FEATURE_MPIDR); |
581be094 PM |
249 | if (!arm_feature(env, ARM_FEATURE_M)) { |
250 | set_feature(env, ARM_FEATURE_V6K); | |
251 | } else { | |
252 | set_feature(env, ARM_FEATURE_V6); | |
253 | } | |
254 | } | |
255 | if (arm_feature(env, ARM_FEATURE_V6K)) { | |
256 | set_feature(env, ARM_FEATURE_V6); | |
257 | set_feature(env, ARM_FEATURE_MVFR); | |
258 | } | |
259 | if (arm_feature(env, ARM_FEATURE_V6)) { | |
260 | set_feature(env, ARM_FEATURE_V5); | |
261 | if (!arm_feature(env, ARM_FEATURE_M)) { | |
262 | set_feature(env, ARM_FEATURE_AUXCR); | |
263 | } | |
264 | } | |
265 | if (arm_feature(env, ARM_FEATURE_V5)) { | |
266 | set_feature(env, ARM_FEATURE_V4T); | |
267 | } | |
268 | if (arm_feature(env, ARM_FEATURE_M)) { | |
269 | set_feature(env, ARM_FEATURE_THUMB_DIV); | |
270 | } | |
271 | if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { | |
272 | set_feature(env, ARM_FEATURE_THUMB_DIV); | |
273 | } | |
274 | if (arm_feature(env, ARM_FEATURE_VFP4)) { | |
275 | set_feature(env, ARM_FEATURE_VFP3); | |
276 | } | |
277 | if (arm_feature(env, ARM_FEATURE_VFP3)) { | |
278 | set_feature(env, ARM_FEATURE_VFP); | |
279 | } | |
de9b05b8 | 280 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
bdcc150d | 281 | set_feature(env, ARM_FEATURE_V7MP); |
de9b05b8 PM |
282 | set_feature(env, ARM_FEATURE_PXN); |
283 | } | |
2ceb98c0 PM |
284 | |
285 | register_cp_regs_for_features(cpu); | |
14969266 AF |
286 | arm_cpu_register_gdb_regs_for_features(cpu); |
287 | ||
721fae12 PM |
288 | init_cpreg_list(cpu); |
289 | ||
14a10fc3 AF |
290 | cpu_reset(cs); |
291 | qemu_init_vcpu(cs); | |
14969266 AF |
292 | |
293 | acc->parent_realize(dev, errp); | |
581be094 PM |
294 | } |
295 | ||
5900d6b2 AF |
296 | static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) |
297 | { | |
298 | ObjectClass *oc; | |
51492fd1 | 299 | char *typename; |
5900d6b2 AF |
300 | |
301 | if (!cpu_model) { | |
302 | return NULL; | |
303 | } | |
304 | ||
51492fd1 AF |
305 | typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model); |
306 | oc = object_class_by_name(typename); | |
307 | g_free(typename); | |
245fb54d AF |
308 | if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || |
309 | object_class_is_abstract(oc)) { | |
5900d6b2 AF |
310 | return NULL; |
311 | } | |
312 | return oc; | |
313 | } | |
314 | ||
15ee776b PM |
315 | /* CPU models. These are not needed for the AArch64 linux-user build. */ |
316 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) | |
317 | ||
777dc784 PM |
318 | static void arm926_initfn(Object *obj) |
319 | { | |
320 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
321 | set_feature(&cpu->env, ARM_FEATURE_V5); |
322 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
c4804214 PM |
323 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
324 | set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); | |
b2d06f96 | 325 | cpu->midr = 0x41069265; |
325b3cef | 326 | cpu->reset_fpsid = 0x41011090; |
64e1671f | 327 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 328 | cpu->reset_sctlr = 0x00090078; |
777dc784 PM |
329 | } |
330 | ||
331 | static void arm946_initfn(Object *obj) | |
332 | { | |
333 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
334 | set_feature(&cpu->env, ARM_FEATURE_V5); |
335 | set_feature(&cpu->env, ARM_FEATURE_MPU); | |
c4804214 | 336 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 337 | cpu->midr = 0x41059461; |
64e1671f | 338 | cpu->ctr = 0x0f004006; |
0ca7e01c | 339 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
340 | } |
341 | ||
342 | static void arm1026_initfn(Object *obj) | |
343 | { | |
344 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
345 | set_feature(&cpu->env, ARM_FEATURE_V5); |
346 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
347 | set_feature(&cpu->env, ARM_FEATURE_AUXCR); | |
c4804214 PM |
348 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
349 | set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); | |
b2d06f96 | 350 | cpu->midr = 0x4106a262; |
325b3cef | 351 | cpu->reset_fpsid = 0x410110a0; |
64e1671f | 352 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 353 | cpu->reset_sctlr = 0x00090078; |
2771db27 | 354 | cpu->reset_auxcr = 1; |
06d76f31 PM |
355 | { |
356 | /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ | |
357 | ARMCPRegInfo ifar = { | |
358 | .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, | |
359 | .access = PL1_RW, | |
360 | .fieldoffset = offsetof(CPUARMState, cp15.c6_insn), | |
361 | .resetvalue = 0 | |
362 | }; | |
363 | define_one_arm_cp_reg(cpu, &ifar); | |
364 | } | |
777dc784 PM |
365 | } |
366 | ||
367 | static void arm1136_r2_initfn(Object *obj) | |
368 | { | |
369 | ARMCPU *cpu = ARM_CPU(obj); | |
2e4d7e3e PM |
370 | /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an |
371 | * older core than plain "arm1136". In particular this does not | |
372 | * have the v6K features. | |
373 | * These ID register values are correct for 1136 but may be wrong | |
374 | * for 1136_r2 (in particular r0p2 does not actually implement most | |
375 | * of the ID registers). | |
376 | */ | |
581be094 PM |
377 | set_feature(&cpu->env, ARM_FEATURE_V6); |
378 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
c4804214 PM |
379 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
380 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | |
381 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | |
b2d06f96 | 382 | cpu->midr = 0x4107b362; |
325b3cef | 383 | cpu->reset_fpsid = 0x410120b4; |
bd35c355 PM |
384 | cpu->mvfr0 = 0x11111111; |
385 | cpu->mvfr1 = 0x00000000; | |
64e1671f | 386 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 387 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
388 | cpu->id_pfr0 = 0x111; |
389 | cpu->id_pfr1 = 0x1; | |
390 | cpu->id_dfr0 = 0x2; | |
391 | cpu->id_afr0 = 0x3; | |
392 | cpu->id_mmfr0 = 0x01130003; | |
393 | cpu->id_mmfr1 = 0x10030302; | |
394 | cpu->id_mmfr2 = 0x01222110; | |
395 | cpu->id_isar0 = 0x00140011; | |
396 | cpu->id_isar1 = 0x12002111; | |
397 | cpu->id_isar2 = 0x11231111; | |
398 | cpu->id_isar3 = 0x01102131; | |
399 | cpu->id_isar4 = 0x141; | |
2771db27 | 400 | cpu->reset_auxcr = 7; |
777dc784 PM |
401 | } |
402 | ||
403 | static void arm1136_initfn(Object *obj) | |
404 | { | |
405 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
406 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
407 | set_feature(&cpu->env, ARM_FEATURE_V6); | |
408 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
c4804214 PM |
409 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
410 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | |
411 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | |
b2d06f96 | 412 | cpu->midr = 0x4117b363; |
325b3cef | 413 | cpu->reset_fpsid = 0x410120b4; |
bd35c355 PM |
414 | cpu->mvfr0 = 0x11111111; |
415 | cpu->mvfr1 = 0x00000000; | |
64e1671f | 416 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 417 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
418 | cpu->id_pfr0 = 0x111; |
419 | cpu->id_pfr1 = 0x1; | |
420 | cpu->id_dfr0 = 0x2; | |
421 | cpu->id_afr0 = 0x3; | |
422 | cpu->id_mmfr0 = 0x01130003; | |
423 | cpu->id_mmfr1 = 0x10030302; | |
424 | cpu->id_mmfr2 = 0x01222110; | |
425 | cpu->id_isar0 = 0x00140011; | |
426 | cpu->id_isar1 = 0x12002111; | |
427 | cpu->id_isar2 = 0x11231111; | |
428 | cpu->id_isar3 = 0x01102131; | |
429 | cpu->id_isar4 = 0x141; | |
2771db27 | 430 | cpu->reset_auxcr = 7; |
777dc784 PM |
431 | } |
432 | ||
433 | static void arm1176_initfn(Object *obj) | |
434 | { | |
435 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
436 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
437 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
438 | set_feature(&cpu->env, ARM_FEATURE_VAPA); | |
c4804214 PM |
439 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
440 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | |
441 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | |
b2d06f96 | 442 | cpu->midr = 0x410fb767; |
325b3cef | 443 | cpu->reset_fpsid = 0x410120b5; |
bd35c355 PM |
444 | cpu->mvfr0 = 0x11111111; |
445 | cpu->mvfr1 = 0x00000000; | |
64e1671f | 446 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 447 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
448 | cpu->id_pfr0 = 0x111; |
449 | cpu->id_pfr1 = 0x11; | |
450 | cpu->id_dfr0 = 0x33; | |
451 | cpu->id_afr0 = 0; | |
452 | cpu->id_mmfr0 = 0x01130003; | |
453 | cpu->id_mmfr1 = 0x10030302; | |
454 | cpu->id_mmfr2 = 0x01222100; | |
455 | cpu->id_isar0 = 0x0140011; | |
456 | cpu->id_isar1 = 0x12002111; | |
457 | cpu->id_isar2 = 0x11231121; | |
458 | cpu->id_isar3 = 0x01102131; | |
459 | cpu->id_isar4 = 0x01141; | |
2771db27 | 460 | cpu->reset_auxcr = 7; |
777dc784 PM |
461 | } |
462 | ||
463 | static void arm11mpcore_initfn(Object *obj) | |
464 | { | |
465 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
466 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
467 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
468 | set_feature(&cpu->env, ARM_FEATURE_VAPA); | |
81bdde9d | 469 | set_feature(&cpu->env, ARM_FEATURE_MPIDR); |
c4804214 | 470 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 471 | cpu->midr = 0x410fb022; |
325b3cef | 472 | cpu->reset_fpsid = 0x410120b4; |
bd35c355 PM |
473 | cpu->mvfr0 = 0x11111111; |
474 | cpu->mvfr1 = 0x00000000; | |
200bf596 | 475 | cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ |
2e4d7e3e PM |
476 | cpu->id_pfr0 = 0x111; |
477 | cpu->id_pfr1 = 0x1; | |
478 | cpu->id_dfr0 = 0; | |
479 | cpu->id_afr0 = 0x2; | |
480 | cpu->id_mmfr0 = 0x01100103; | |
481 | cpu->id_mmfr1 = 0x10020302; | |
482 | cpu->id_mmfr2 = 0x01222000; | |
483 | cpu->id_isar0 = 0x00100011; | |
484 | cpu->id_isar1 = 0x12002111; | |
485 | cpu->id_isar2 = 0x11221011; | |
486 | cpu->id_isar3 = 0x01102131; | |
487 | cpu->id_isar4 = 0x141; | |
2771db27 | 488 | cpu->reset_auxcr = 1; |
777dc784 PM |
489 | } |
490 | ||
491 | static void cortex_m3_initfn(Object *obj) | |
492 | { | |
493 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
494 | set_feature(&cpu->env, ARM_FEATURE_V7); |
495 | set_feature(&cpu->env, ARM_FEATURE_M); | |
b2d06f96 | 496 | cpu->midr = 0x410fc231; |
777dc784 PM |
497 | } |
498 | ||
e6f010cc AF |
499 | static void arm_v7m_class_init(ObjectClass *oc, void *data) |
500 | { | |
501 | #ifndef CONFIG_USER_ONLY | |
502 | CPUClass *cc = CPU_CLASS(oc); | |
503 | ||
504 | cc->do_interrupt = arm_v7m_cpu_do_interrupt; | |
505 | #endif | |
506 | } | |
507 | ||
34f90529 PM |
508 | static const ARMCPRegInfo cortexa8_cp_reginfo[] = { |
509 | { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, | |
510 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
511 | { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, | |
512 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
513 | REGINFO_SENTINEL | |
514 | }; | |
515 | ||
777dc784 PM |
516 | static void cortex_a8_initfn(Object *obj) |
517 | { | |
518 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
519 | set_feature(&cpu->env, ARM_FEATURE_V7); |
520 | set_feature(&cpu->env, ARM_FEATURE_VFP3); | |
521 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
522 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
c4804214 | 523 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 524 | cpu->midr = 0x410fc080; |
325b3cef | 525 | cpu->reset_fpsid = 0x410330c0; |
bd35c355 PM |
526 | cpu->mvfr0 = 0x11110222; |
527 | cpu->mvfr1 = 0x00011100; | |
64e1671f | 528 | cpu->ctr = 0x82048004; |
0ca7e01c | 529 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
530 | cpu->id_pfr0 = 0x1031; |
531 | cpu->id_pfr1 = 0x11; | |
532 | cpu->id_dfr0 = 0x400; | |
533 | cpu->id_afr0 = 0; | |
534 | cpu->id_mmfr0 = 0x31100003; | |
535 | cpu->id_mmfr1 = 0x20000000; | |
536 | cpu->id_mmfr2 = 0x01202000; | |
537 | cpu->id_mmfr3 = 0x11; | |
538 | cpu->id_isar0 = 0x00101111; | |
539 | cpu->id_isar1 = 0x12112111; | |
540 | cpu->id_isar2 = 0x21232031; | |
541 | cpu->id_isar3 = 0x11112131; | |
542 | cpu->id_isar4 = 0x00111142; | |
85df3786 PM |
543 | cpu->clidr = (1 << 27) | (2 << 24) | 3; |
544 | cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ | |
545 | cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ | |
546 | cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ | |
2771db27 | 547 | cpu->reset_auxcr = 2; |
34f90529 | 548 | define_arm_cp_regs(cpu, cortexa8_cp_reginfo); |
777dc784 PM |
549 | } |
550 | ||
1047b9d7 PM |
551 | static const ARMCPRegInfo cortexa9_cp_reginfo[] = { |
552 | /* power_control should be set to maximum latency. Again, | |
553 | * default to 0 and set by private hook | |
554 | */ | |
555 | { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, | |
556 | .access = PL1_RW, .resetvalue = 0, | |
557 | .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, | |
558 | { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, | |
559 | .access = PL1_RW, .resetvalue = 0, | |
560 | .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, | |
561 | { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, | |
562 | .access = PL1_RW, .resetvalue = 0, | |
563 | .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, | |
564 | { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, | |
565 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
566 | /* TLB lockdown control */ | |
567 | { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, | |
568 | .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, | |
569 | { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, | |
570 | .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, | |
571 | { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, | |
572 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
573 | { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, | |
574 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
575 | { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, | |
576 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
577 | REGINFO_SENTINEL | |
578 | }; | |
579 | ||
777dc784 PM |
580 | static void cortex_a9_initfn(Object *obj) |
581 | { | |
582 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
583 | set_feature(&cpu->env, ARM_FEATURE_V7); |
584 | set_feature(&cpu->env, ARM_FEATURE_VFP3); | |
585 | set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); | |
586 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
587 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
588 | /* Note that A9 supports the MP extensions even for | |
589 | * A9UP and single-core A9MP (which are both different | |
590 | * and valid configurations; we don't model A9UP). | |
591 | */ | |
592 | set_feature(&cpu->env, ARM_FEATURE_V7MP); | |
b2d06f96 | 593 | cpu->midr = 0x410fc090; |
325b3cef | 594 | cpu->reset_fpsid = 0x41033090; |
bd35c355 PM |
595 | cpu->mvfr0 = 0x11110222; |
596 | cpu->mvfr1 = 0x01111111; | |
64e1671f | 597 | cpu->ctr = 0x80038003; |
0ca7e01c | 598 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
599 | cpu->id_pfr0 = 0x1031; |
600 | cpu->id_pfr1 = 0x11; | |
601 | cpu->id_dfr0 = 0x000; | |
602 | cpu->id_afr0 = 0; | |
603 | cpu->id_mmfr0 = 0x00100103; | |
604 | cpu->id_mmfr1 = 0x20000000; | |
605 | cpu->id_mmfr2 = 0x01230000; | |
606 | cpu->id_mmfr3 = 0x00002111; | |
607 | cpu->id_isar0 = 0x00101111; | |
608 | cpu->id_isar1 = 0x13112111; | |
609 | cpu->id_isar2 = 0x21232041; | |
610 | cpu->id_isar3 = 0x11112131; | |
611 | cpu->id_isar4 = 0x00111142; | |
85df3786 PM |
612 | cpu->clidr = (1 << 27) | (1 << 24) | 3; |
613 | cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */ | |
614 | cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */ | |
1047b9d7 PM |
615 | { |
616 | ARMCPRegInfo cbar = { | |
617 | .name = "CBAR", .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, | |
618 | .opc2 = 0, .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar, | |
619 | .fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address) | |
620 | }; | |
621 | define_one_arm_cp_reg(cpu, &cbar); | |
622 | define_arm_cp_regs(cpu, cortexa9_cp_reginfo); | |
623 | } | |
777dc784 PM |
624 | } |
625 | ||
34f90529 PM |
626 | #ifndef CONFIG_USER_ONLY |
627 | static int a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri, | |
628 | uint64_t *value) | |
629 | { | |
630 | /* Linux wants the number of processors from here. | |
631 | * Might as well set the interrupt-controller bit too. | |
632 | */ | |
633 | *value = ((smp_cpus - 1) << 24) | (1 << 23); | |
634 | return 0; | |
635 | } | |
636 | #endif | |
637 | ||
638 | static const ARMCPRegInfo cortexa15_cp_reginfo[] = { | |
639 | #ifndef CONFIG_USER_ONLY | |
640 | { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, | |
641 | .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, | |
642 | .writefn = arm_cp_write_ignore, }, | |
643 | #endif | |
644 | { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, | |
645 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
646 | REGINFO_SENTINEL | |
647 | }; | |
648 | ||
777dc784 PM |
649 | static void cortex_a15_initfn(Object *obj) |
650 | { | |
651 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
652 | set_feature(&cpu->env, ARM_FEATURE_V7); |
653 | set_feature(&cpu->env, ARM_FEATURE_VFP4); | |
654 | set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); | |
655 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
656 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
657 | set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); | |
581be094 | 658 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); |
c4804214 | 659 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
de9b05b8 | 660 | set_feature(&cpu->env, ARM_FEATURE_LPAE); |
b2d06f96 | 661 | cpu->midr = 0x412fc0f1; |
325b3cef | 662 | cpu->reset_fpsid = 0x410430f0; |
bd35c355 PM |
663 | cpu->mvfr0 = 0x10110222; |
664 | cpu->mvfr1 = 0x11111111; | |
64e1671f | 665 | cpu->ctr = 0x8444c004; |
0ca7e01c | 666 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
667 | cpu->id_pfr0 = 0x00001131; |
668 | cpu->id_pfr1 = 0x00011011; | |
669 | cpu->id_dfr0 = 0x02010555; | |
670 | cpu->id_afr0 = 0x00000000; | |
671 | cpu->id_mmfr0 = 0x10201105; | |
672 | cpu->id_mmfr1 = 0x20000000; | |
673 | cpu->id_mmfr2 = 0x01240000; | |
674 | cpu->id_mmfr3 = 0x02102211; | |
675 | cpu->id_isar0 = 0x02101110; | |
676 | cpu->id_isar1 = 0x13112111; | |
677 | cpu->id_isar2 = 0x21232041; | |
678 | cpu->id_isar3 = 0x11112131; | |
679 | cpu->id_isar4 = 0x10011142; | |
85df3786 PM |
680 | cpu->clidr = 0x0a200023; |
681 | cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ | |
682 | cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ | |
683 | cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ | |
34f90529 | 684 | define_arm_cp_regs(cpu, cortexa15_cp_reginfo); |
777dc784 PM |
685 | } |
686 | ||
687 | static void ti925t_initfn(Object *obj) | |
688 | { | |
689 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
690 | set_feature(&cpu->env, ARM_FEATURE_V4T); |
691 | set_feature(&cpu->env, ARM_FEATURE_OMAPCP); | |
777dc784 | 692 | cpu->midr = ARM_CPUID_TI925T; |
64e1671f | 693 | cpu->ctr = 0x5109149; |
0ca7e01c | 694 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
695 | } |
696 | ||
697 | static void sa1100_initfn(Object *obj) | |
698 | { | |
699 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 | 700 | set_feature(&cpu->env, ARM_FEATURE_STRONGARM); |
c4804214 | 701 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 702 | cpu->midr = 0x4401A11B; |
0ca7e01c | 703 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
704 | } |
705 | ||
706 | static void sa1110_initfn(Object *obj) | |
707 | { | |
708 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 | 709 | set_feature(&cpu->env, ARM_FEATURE_STRONGARM); |
c4804214 | 710 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 711 | cpu->midr = 0x6901B119; |
0ca7e01c | 712 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
713 | } |
714 | ||
715 | static void pxa250_initfn(Object *obj) | |
716 | { | |
717 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
718 | set_feature(&cpu->env, ARM_FEATURE_V5); |
719 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 720 | cpu->midr = 0x69052100; |
64e1671f | 721 | cpu->ctr = 0xd172172; |
0ca7e01c | 722 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
723 | } |
724 | ||
725 | static void pxa255_initfn(Object *obj) | |
726 | { | |
727 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
728 | set_feature(&cpu->env, ARM_FEATURE_V5); |
729 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 730 | cpu->midr = 0x69052d00; |
64e1671f | 731 | cpu->ctr = 0xd172172; |
0ca7e01c | 732 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
733 | } |
734 | ||
735 | static void pxa260_initfn(Object *obj) | |
736 | { | |
737 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
738 | set_feature(&cpu->env, ARM_FEATURE_V5); |
739 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 740 | cpu->midr = 0x69052903; |
64e1671f | 741 | cpu->ctr = 0xd172172; |
0ca7e01c | 742 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
743 | } |
744 | ||
745 | static void pxa261_initfn(Object *obj) | |
746 | { | |
747 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
748 | set_feature(&cpu->env, ARM_FEATURE_V5); |
749 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 750 | cpu->midr = 0x69052d05; |
64e1671f | 751 | cpu->ctr = 0xd172172; |
0ca7e01c | 752 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
753 | } |
754 | ||
755 | static void pxa262_initfn(Object *obj) | |
756 | { | |
757 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
758 | set_feature(&cpu->env, ARM_FEATURE_V5); |
759 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 760 | cpu->midr = 0x69052d06; |
64e1671f | 761 | cpu->ctr = 0xd172172; |
0ca7e01c | 762 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
763 | } |
764 | ||
765 | static void pxa270a0_initfn(Object *obj) | |
766 | { | |
767 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
768 | set_feature(&cpu->env, ARM_FEATURE_V5); |
769 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
770 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 771 | cpu->midr = 0x69054110; |
64e1671f | 772 | cpu->ctr = 0xd172172; |
0ca7e01c | 773 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
774 | } |
775 | ||
776 | static void pxa270a1_initfn(Object *obj) | |
777 | { | |
778 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
779 | set_feature(&cpu->env, ARM_FEATURE_V5); |
780 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
781 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 782 | cpu->midr = 0x69054111; |
64e1671f | 783 | cpu->ctr = 0xd172172; |
0ca7e01c | 784 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
785 | } |
786 | ||
787 | static void pxa270b0_initfn(Object *obj) | |
788 | { | |
789 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
790 | set_feature(&cpu->env, ARM_FEATURE_V5); |
791 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
792 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 793 | cpu->midr = 0x69054112; |
64e1671f | 794 | cpu->ctr = 0xd172172; |
0ca7e01c | 795 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
796 | } |
797 | ||
798 | static void pxa270b1_initfn(Object *obj) | |
799 | { | |
800 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
801 | set_feature(&cpu->env, ARM_FEATURE_V5); |
802 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
803 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 804 | cpu->midr = 0x69054113; |
64e1671f | 805 | cpu->ctr = 0xd172172; |
0ca7e01c | 806 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
807 | } |
808 | ||
809 | static void pxa270c0_initfn(Object *obj) | |
810 | { | |
811 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
812 | set_feature(&cpu->env, ARM_FEATURE_V5); |
813 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
814 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 815 | cpu->midr = 0x69054114; |
64e1671f | 816 | cpu->ctr = 0xd172172; |
0ca7e01c | 817 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
818 | } |
819 | ||
820 | static void pxa270c5_initfn(Object *obj) | |
821 | { | |
822 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
823 | set_feature(&cpu->env, ARM_FEATURE_V5); |
824 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
825 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 826 | cpu->midr = 0x69054117; |
64e1671f | 827 | cpu->ctr = 0xd172172; |
0ca7e01c | 828 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
829 | } |
830 | ||
f5f6d38b | 831 | #ifdef CONFIG_USER_ONLY |
777dc784 PM |
832 | static void arm_any_initfn(Object *obj) |
833 | { | |
834 | ARMCPU *cpu = ARM_CPU(obj); | |
81e69fb0 | 835 | set_feature(&cpu->env, ARM_FEATURE_V8); |
581be094 PM |
836 | set_feature(&cpu->env, ARM_FEATURE_VFP4); |
837 | set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); | |
838 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
839 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
840 | set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); | |
841 | set_feature(&cpu->env, ARM_FEATURE_V7MP); | |
3926cc84 AG |
842 | #ifdef TARGET_AARCH64 |
843 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); | |
844 | #endif | |
b2d06f96 | 845 | cpu->midr = 0xffffffff; |
777dc784 | 846 | } |
f5f6d38b | 847 | #endif |
777dc784 | 848 | |
15ee776b PM |
849 | #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ |
850 | ||
777dc784 PM |
851 | typedef struct ARMCPUInfo { |
852 | const char *name; | |
853 | void (*initfn)(Object *obj); | |
e6f010cc | 854 | void (*class_init)(ObjectClass *oc, void *data); |
777dc784 PM |
855 | } ARMCPUInfo; |
856 | ||
857 | static const ARMCPUInfo arm_cpus[] = { | |
15ee776b | 858 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) |
777dc784 PM |
859 | { .name = "arm926", .initfn = arm926_initfn }, |
860 | { .name = "arm946", .initfn = arm946_initfn }, | |
861 | { .name = "arm1026", .initfn = arm1026_initfn }, | |
862 | /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an | |
863 | * older core than plain "arm1136". In particular this does not | |
864 | * have the v6K features. | |
865 | */ | |
866 | { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, | |
867 | { .name = "arm1136", .initfn = arm1136_initfn }, | |
868 | { .name = "arm1176", .initfn = arm1176_initfn }, | |
869 | { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, | |
e6f010cc AF |
870 | { .name = "cortex-m3", .initfn = cortex_m3_initfn, |
871 | .class_init = arm_v7m_class_init }, | |
777dc784 PM |
872 | { .name = "cortex-a8", .initfn = cortex_a8_initfn }, |
873 | { .name = "cortex-a9", .initfn = cortex_a9_initfn }, | |
874 | { .name = "cortex-a15", .initfn = cortex_a15_initfn }, | |
875 | { .name = "ti925t", .initfn = ti925t_initfn }, | |
876 | { .name = "sa1100", .initfn = sa1100_initfn }, | |
877 | { .name = "sa1110", .initfn = sa1110_initfn }, | |
878 | { .name = "pxa250", .initfn = pxa250_initfn }, | |
879 | { .name = "pxa255", .initfn = pxa255_initfn }, | |
880 | { .name = "pxa260", .initfn = pxa260_initfn }, | |
881 | { .name = "pxa261", .initfn = pxa261_initfn }, | |
882 | { .name = "pxa262", .initfn = pxa262_initfn }, | |
883 | /* "pxa270" is an alias for "pxa270-a0" */ | |
884 | { .name = "pxa270", .initfn = pxa270a0_initfn }, | |
885 | { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, | |
886 | { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, | |
887 | { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, | |
888 | { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, | |
889 | { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, | |
890 | { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, | |
f5f6d38b | 891 | #ifdef CONFIG_USER_ONLY |
777dc784 | 892 | { .name = "any", .initfn = arm_any_initfn }, |
f5f6d38b | 893 | #endif |
15ee776b | 894 | #endif |
777dc784 PM |
895 | }; |
896 | ||
dec9c2d4 AF |
897 | static void arm_cpu_class_init(ObjectClass *oc, void *data) |
898 | { | |
899 | ARMCPUClass *acc = ARM_CPU_CLASS(oc); | |
900 | CPUClass *cc = CPU_CLASS(acc); | |
14969266 AF |
901 | DeviceClass *dc = DEVICE_CLASS(oc); |
902 | ||
903 | acc->parent_realize = dc->realize; | |
904 | dc->realize = arm_cpu_realizefn; | |
dec9c2d4 AF |
905 | |
906 | acc->parent_reset = cc->reset; | |
907 | cc->reset = arm_cpu_reset; | |
5900d6b2 AF |
908 | |
909 | cc->class_by_name = arm_cpu_class_by_name; | |
97a8ea5a | 910 | cc->do_interrupt = arm_cpu_do_interrupt; |
878096ee | 911 | cc->dump_state = arm_cpu_dump_state; |
f45748f1 | 912 | cc->set_pc = arm_cpu_set_pc; |
5b50e790 AF |
913 | cc->gdb_read_register = arm_cpu_gdb_read_register; |
914 | cc->gdb_write_register = arm_cpu_gdb_write_register; | |
00b941e5 AF |
915 | #ifndef CONFIG_USER_ONLY |
916 | cc->get_phys_page_debug = arm_cpu_get_phys_page_debug; | |
917 | cc->vmsd = &vmstate_arm_cpu; | |
918 | #endif | |
a0e372f0 | 919 | cc->gdb_num_core_regs = 26; |
5b24c641 | 920 | cc->gdb_core_xml_file = "arm-core.xml"; |
dec9c2d4 AF |
921 | } |
922 | ||
777dc784 PM |
923 | static void cpu_register(const ARMCPUInfo *info) |
924 | { | |
925 | TypeInfo type_info = { | |
777dc784 PM |
926 | .parent = TYPE_ARM_CPU, |
927 | .instance_size = sizeof(ARMCPU), | |
928 | .instance_init = info->initfn, | |
929 | .class_size = sizeof(ARMCPUClass), | |
e6f010cc | 930 | .class_init = info->class_init, |
777dc784 PM |
931 | }; |
932 | ||
51492fd1 | 933 | type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); |
918fd083 | 934 | type_register(&type_info); |
51492fd1 | 935 | g_free((void *)type_info.name); |
777dc784 PM |
936 | } |
937 | ||
dec9c2d4 AF |
938 | static const TypeInfo arm_cpu_type_info = { |
939 | .name = TYPE_ARM_CPU, | |
940 | .parent = TYPE_CPU, | |
941 | .instance_size = sizeof(ARMCPU), | |
777dc784 | 942 | .instance_init = arm_cpu_initfn, |
4b6a83fb | 943 | .instance_finalize = arm_cpu_finalizefn, |
777dc784 | 944 | .abstract = true, |
dec9c2d4 AF |
945 | .class_size = sizeof(ARMCPUClass), |
946 | .class_init = arm_cpu_class_init, | |
947 | }; | |
948 | ||
949 | static void arm_cpu_register_types(void) | |
950 | { | |
777dc784 PM |
951 | int i; |
952 | ||
dec9c2d4 | 953 | type_register_static(&arm_cpu_type_info); |
777dc784 PM |
954 | for (i = 0; i < ARRAY_SIZE(arm_cpus); i++) { |
955 | cpu_register(&arm_cpus[i]); | |
956 | } | |
dec9c2d4 AF |
957 | } |
958 | ||
959 | type_init(arm_cpu_register_types) |