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d14d42f1 PM |
1 | /* |
2 | * QEMU AArch64 CPU | |
3 | * | |
4 | * Copyright (c) 2013 Linaro Ltd | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | ||
21 | #include "cpu.h" | |
22 | #include "qemu-common.h" | |
23 | #if !defined(CONFIG_USER_ONLY) | |
24 | #include "hw/loader.h" | |
25 | #endif | |
26 | #include "hw/arm/arm.h" | |
27 | #include "sysemu/sysemu.h" | |
28 | #include "sysemu/kvm.h" | |
29 | ||
30 | static inline void set_feature(CPUARMState *env, int feature) | |
31 | { | |
32 | env->features |= 1ULL << feature; | |
33 | } | |
34 | ||
fb8d6c24 GB |
35 | static inline void unset_feature(CPUARMState *env, int feature) |
36 | { | |
37 | env->features &= ~(1ULL << feature); | |
38 | } | |
39 | ||
377a44ec | 40 | #ifndef CONFIG_USER_ONLY |
ee804264 | 41 | static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
377a44ec PM |
42 | { |
43 | /* Number of processors is in [25:24]; otherwise we RAZ */ | |
44 | return (smp_cpus - 1) << 24; | |
45 | } | |
46 | #endif | |
47 | ||
ee804264 | 48 | static const ARMCPRegInfo cortex_a57_a53_cp_reginfo[] = { |
377a44ec PM |
49 | #ifndef CONFIG_USER_ONLY |
50 | { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64, | |
51 | .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2, | |
ee804264 | 52 | .access = PL1_RW, .readfn = a57_a53_l2ctlr_read, |
377a44ec PM |
53 | .writefn = arm_cp_write_ignore }, |
54 | { .name = "L2CTLR", | |
55 | .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2, | |
ee804264 | 56 | .access = PL1_RW, .readfn = a57_a53_l2ctlr_read, |
377a44ec PM |
57 | .writefn = arm_cp_write_ignore }, |
58 | #endif | |
59 | { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64, | |
60 | .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3, | |
61 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
62 | { .name = "L2ECTLR", | |
63 | .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3, | |
64 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
65 | { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH, | |
66 | .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0, | |
67 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
68 | { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64, | |
69 | .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0, | |
70 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
71 | { .name = "CPUACTLR", | |
72 | .cp = 15, .opc1 = 0, .crm = 15, | |
73 | .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | |
74 | { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64, | |
75 | .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1, | |
76 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
77 | { .name = "CPUECTLR", | |
78 | .cp = 15, .opc1 = 1, .crm = 15, | |
79 | .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | |
80 | { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64, | |
81 | .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2, | |
82 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
83 | { .name = "CPUMERRSR", | |
84 | .cp = 15, .opc1 = 2, .crm = 15, | |
85 | .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | |
86 | { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64, | |
87 | .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3, | |
88 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
89 | { .name = "L2MERRSR", | |
90 | .cp = 15, .opc1 = 3, .crm = 15, | |
91 | .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | |
92 | REGINFO_SENTINEL | |
93 | }; | |
94 | ||
cb1fa941 PM |
95 | static void aarch64_a57_initfn(Object *obj) |
96 | { | |
97 | ARMCPU *cpu = ARM_CPU(obj); | |
98 | ||
0458b7b5 | 99 | cpu->dtb_compatible = "arm,cortex-a57"; |
cb1fa941 PM |
100 | set_feature(&cpu->env, ARM_FEATURE_V8); |
101 | set_feature(&cpu->env, ARM_FEATURE_VFP4); | |
cb1fa941 PM |
102 | set_feature(&cpu->env, ARM_FEATURE_NEON); |
103 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | |
104 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); | |
f318cec6 | 105 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); |
25f748e3 PM |
106 | set_feature(&cpu->env, ARM_FEATURE_V8_AES); |
107 | set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); | |
108 | set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); | |
109 | set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); | |
110 | set_feature(&cpu->env, ARM_FEATURE_CRC); | |
cb1fa941 PM |
111 | cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57; |
112 | cpu->midr = 0x411fd070; | |
13b72b2b | 113 | cpu->revidr = 0x00000000; |
cb1fa941 PM |
114 | cpu->reset_fpsid = 0x41034070; |
115 | cpu->mvfr0 = 0x10110222; | |
116 | cpu->mvfr1 = 0x12111111; | |
117 | cpu->mvfr2 = 0x00000043; | |
118 | cpu->ctr = 0x8444c004; | |
119 | cpu->reset_sctlr = 0x00c50838; | |
120 | cpu->id_pfr0 = 0x00000131; | |
121 | cpu->id_pfr1 = 0x00011011; | |
122 | cpu->id_dfr0 = 0x03010066; | |
123 | cpu->id_afr0 = 0x00000000; | |
124 | cpu->id_mmfr0 = 0x10101105; | |
125 | cpu->id_mmfr1 = 0x40000000; | |
126 | cpu->id_mmfr2 = 0x01260000; | |
127 | cpu->id_mmfr3 = 0x02102211; | |
128 | cpu->id_isar0 = 0x02101110; | |
129 | cpu->id_isar1 = 0x13112111; | |
130 | cpu->id_isar2 = 0x21232042; | |
131 | cpu->id_isar3 = 0x01112131; | |
132 | cpu->id_isar4 = 0x00011142; | |
c3796214 | 133 | cpu->id_isar5 = 0x00011121; |
cb1fa941 PM |
134 | cpu->id_aa64pfr0 = 0x00002222; |
135 | cpu->id_aa64dfr0 = 0x10305106; | |
c3796214 | 136 | cpu->id_aa64isar0 = 0x00011120; |
cb1fa941 | 137 | cpu->id_aa64mmfr0 = 0x00001124; |
48eb3ae6 | 138 | cpu->dbgdidr = 0x3516d000; |
cb1fa941 PM |
139 | cpu->clidr = 0x0a200023; |
140 | cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ | |
141 | cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ | |
142 | cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */ | |
143 | cpu->dcz_blocksize = 4; /* 64 bytes */ | |
ee804264 | 144 | define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo); |
cb1fa941 PM |
145 | } |
146 | ||
e3531026 PC |
147 | static void aarch64_a53_initfn(Object *obj) |
148 | { | |
149 | ARMCPU *cpu = ARM_CPU(obj); | |
150 | ||
151 | cpu->dtb_compatible = "arm,cortex-a53"; | |
152 | set_feature(&cpu->env, ARM_FEATURE_V8); | |
153 | set_feature(&cpu->env, ARM_FEATURE_VFP4); | |
154 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
155 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | |
156 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); | |
157 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | |
158 | set_feature(&cpu->env, ARM_FEATURE_V8_AES); | |
159 | set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); | |
160 | set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); | |
161 | set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); | |
162 | set_feature(&cpu->env, ARM_FEATURE_CRC); | |
7525465e | 163 | cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53; |
e3531026 | 164 | cpu->midr = 0x410fd034; |
13b72b2b | 165 | cpu->revidr = 0x00000000; |
e3531026 PC |
166 | cpu->reset_fpsid = 0x41034070; |
167 | cpu->mvfr0 = 0x10110222; | |
168 | cpu->mvfr1 = 0x12111111; | |
169 | cpu->mvfr2 = 0x00000043; | |
170 | cpu->ctr = 0x84448004; /* L1Ip = VIPT */ | |
171 | cpu->reset_sctlr = 0x00c50838; | |
172 | cpu->id_pfr0 = 0x00000131; | |
173 | cpu->id_pfr1 = 0x00011011; | |
174 | cpu->id_dfr0 = 0x03010066; | |
175 | cpu->id_afr0 = 0x00000000; | |
176 | cpu->id_mmfr0 = 0x10101105; | |
177 | cpu->id_mmfr1 = 0x40000000; | |
178 | cpu->id_mmfr2 = 0x01260000; | |
179 | cpu->id_mmfr3 = 0x02102211; | |
180 | cpu->id_isar0 = 0x02101110; | |
181 | cpu->id_isar1 = 0x13112111; | |
182 | cpu->id_isar2 = 0x21232042; | |
183 | cpu->id_isar3 = 0x01112131; | |
184 | cpu->id_isar4 = 0x00011142; | |
185 | cpu->id_isar5 = 0x00011121; | |
186 | cpu->id_aa64pfr0 = 0x00002222; | |
187 | cpu->id_aa64dfr0 = 0x10305106; | |
188 | cpu->id_aa64isar0 = 0x00011120; | |
189 | cpu->id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */ | |
190 | cpu->dbgdidr = 0x3516d000; | |
191 | cpu->clidr = 0x0a200023; | |
192 | cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ | |
193 | cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */ | |
194 | cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */ | |
195 | cpu->dcz_blocksize = 4; /* 64 bytes */ | |
196 | define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo); | |
197 | } | |
198 | ||
d14d42f1 PM |
199 | #ifdef CONFIG_USER_ONLY |
200 | static void aarch64_any_initfn(Object *obj) | |
201 | { | |
202 | ARMCPU *cpu = ARM_CPU(obj); | |
203 | ||
204 | set_feature(&cpu->env, ARM_FEATURE_V8); | |
205 | set_feature(&cpu->env, ARM_FEATURE_VFP4); | |
d14d42f1 | 206 | set_feature(&cpu->env, ARM_FEATURE_NEON); |
d14d42f1 | 207 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); |
25f748e3 PM |
208 | set_feature(&cpu->env, ARM_FEATURE_V8_AES); |
209 | set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); | |
210 | set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); | |
211 | set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); | |
212 | set_feature(&cpu->env, ARM_FEATURE_CRC); | |
0e7b176a | 213 | cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ |
aca3f40b | 214 | cpu->dcz_blocksize = 7; /* 512 bytes */ |
d14d42f1 PM |
215 | } |
216 | #endif | |
217 | ||
218 | typedef struct ARMCPUInfo { | |
219 | const char *name; | |
220 | void (*initfn)(Object *obj); | |
221 | void (*class_init)(ObjectClass *oc, void *data); | |
222 | } ARMCPUInfo; | |
223 | ||
224 | static const ARMCPUInfo aarch64_cpus[] = { | |
cb1fa941 | 225 | { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, |
e3531026 | 226 | { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, |
d14d42f1 PM |
227 | #ifdef CONFIG_USER_ONLY |
228 | { .name = "any", .initfn = aarch64_any_initfn }, | |
229 | #endif | |
83e6813a | 230 | { .name = NULL } |
d14d42f1 PM |
231 | }; |
232 | ||
fb8d6c24 GB |
233 | static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) |
234 | { | |
235 | ARMCPU *cpu = ARM_CPU(obj); | |
236 | ||
237 | return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); | |
238 | } | |
239 | ||
240 | static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp) | |
241 | { | |
242 | ARMCPU *cpu = ARM_CPU(obj); | |
243 | ||
244 | /* At this time, this property is only allowed if KVM is enabled. This | |
245 | * restriction allows us to avoid fixing up functionality that assumes a | |
246 | * uniform execution state like do_interrupt. | |
247 | */ | |
248 | if (!kvm_enabled()) { | |
249 | error_setg(errp, "'aarch64' feature cannot be disabled " | |
250 | "unless KVM is enabled"); | |
251 | return; | |
252 | } | |
253 | ||
254 | if (value == false) { | |
255 | unset_feature(&cpu->env, ARM_FEATURE_AARCH64); | |
256 | } else { | |
257 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); | |
258 | } | |
259 | } | |
260 | ||
d14d42f1 PM |
261 | static void aarch64_cpu_initfn(Object *obj) |
262 | { | |
fb8d6c24 GB |
263 | object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64, |
264 | aarch64_cpu_set_aarch64, NULL); | |
265 | object_property_set_description(obj, "aarch64", | |
266 | "Set on/off to enable/disable aarch64 " | |
267 | "execution state ", | |
268 | NULL); | |
d14d42f1 PM |
269 | } |
270 | ||
271 | static void aarch64_cpu_finalizefn(Object *obj) | |
272 | { | |
273 | } | |
274 | ||
5ce4f357 AG |
275 | static void aarch64_cpu_set_pc(CPUState *cs, vaddr value) |
276 | { | |
277 | ARMCPU *cpu = ARM_CPU(cs); | |
7633378d PM |
278 | /* It's OK to look at env for the current mode here, because it's |
279 | * never possible for an AArch64 TB to chain to an AArch32 TB. | |
280 | * (Otherwise we would need to use synchronize_from_tb instead.) | |
5ce4f357 | 281 | */ |
7633378d PM |
282 | if (is_a64(&cpu->env)) { |
283 | cpu->env.pc = value; | |
284 | } else { | |
285 | cpu->env.regs[15] = value; | |
286 | } | |
5ce4f357 AG |
287 | } |
288 | ||
d14d42f1 PM |
289 | static void aarch64_cpu_class_init(ObjectClass *oc, void *data) |
290 | { | |
14ade10f AG |
291 | CPUClass *cc = CPU_CLASS(oc); |
292 | ||
0adf7d3c | 293 | #if !defined(CONFIG_USER_ONLY) |
52e60cdd | 294 | cc->do_interrupt = aarch64_cpu_do_interrupt; |
0adf7d3c | 295 | #endif |
e8925712 | 296 | cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; |
5ce4f357 | 297 | cc->set_pc = aarch64_cpu_set_pc; |
96c04212 AG |
298 | cc->gdb_read_register = aarch64_cpu_gdb_read_register; |
299 | cc->gdb_write_register = aarch64_cpu_gdb_write_register; | |
300 | cc->gdb_num_core_regs = 34; | |
301 | cc->gdb_core_xml_file = "aarch64-core.xml"; | |
d14d42f1 PM |
302 | } |
303 | ||
304 | static void aarch64_cpu_register(const ARMCPUInfo *info) | |
305 | { | |
306 | TypeInfo type_info = { | |
307 | .parent = TYPE_AARCH64_CPU, | |
308 | .instance_size = sizeof(ARMCPU), | |
309 | .instance_init = info->initfn, | |
310 | .class_size = sizeof(ARMCPUClass), | |
311 | .class_init = info->class_init, | |
312 | }; | |
313 | ||
314 | type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); | |
315 | type_register(&type_info); | |
316 | g_free((void *)type_info.name); | |
317 | } | |
318 | ||
319 | static const TypeInfo aarch64_cpu_type_info = { | |
320 | .name = TYPE_AARCH64_CPU, | |
321 | .parent = TYPE_ARM_CPU, | |
322 | .instance_size = sizeof(ARMCPU), | |
323 | .instance_init = aarch64_cpu_initfn, | |
324 | .instance_finalize = aarch64_cpu_finalizefn, | |
325 | .abstract = true, | |
326 | .class_size = sizeof(AArch64CPUClass), | |
327 | .class_init = aarch64_cpu_class_init, | |
328 | }; | |
329 | ||
330 | static void aarch64_cpu_register_types(void) | |
331 | { | |
83e6813a | 332 | const ARMCPUInfo *info = aarch64_cpus; |
d14d42f1 PM |
333 | |
334 | type_register_static(&aarch64_cpu_type_info); | |
83e6813a PM |
335 | |
336 | while (info->name) { | |
337 | aarch64_cpu_register(info); | |
338 | info++; | |
d14d42f1 PM |
339 | } |
340 | } | |
341 | ||
342 | type_init(aarch64_cpu_register_types) |