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14ade10f AG |
1 | /* |
2 | * AArch64 translation | |
3 | * | |
4 | * Copyright (c) 2013 Alexander Graf <agraf@suse.de> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | #include <stdarg.h> | |
20 | #include <stdlib.h> | |
21 | #include <stdio.h> | |
22 | #include <string.h> | |
23 | #include <inttypes.h> | |
24 | ||
25 | #include "cpu.h" | |
26 | #include "tcg-op.h" | |
27 | #include "qemu/log.h" | |
1d854765 | 28 | #include "arm_ldst.h" |
14ade10f | 29 | #include "translate.h" |
ccd38087 | 30 | #include "internals.h" |
14ade10f AG |
31 | #include "qemu/host-utils.h" |
32 | ||
40f860cd PM |
33 | #include "exec/gen-icount.h" |
34 | ||
2ef6175a RH |
35 | #include "exec/helper-proto.h" |
36 | #include "exec/helper-gen.h" | |
14ade10f AG |
37 | |
38 | static TCGv_i64 cpu_X[32]; | |
39 | static TCGv_i64 cpu_pc; | |
832ffa1c | 40 | static TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF; |
14ade10f | 41 | |
fa2ef212 MM |
42 | /* Load/store exclusive handling */ |
43 | static TCGv_i64 cpu_exclusive_addr; | |
44 | static TCGv_i64 cpu_exclusive_val; | |
45 | static TCGv_i64 cpu_exclusive_high; | |
46 | #ifdef CONFIG_USER_ONLY | |
47 | static TCGv_i64 cpu_exclusive_test; | |
48 | static TCGv_i32 cpu_exclusive_info; | |
49 | #endif | |
50 | ||
14ade10f AG |
51 | static const char *regnames[] = { |
52 | "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", | |
53 | "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", | |
54 | "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", | |
55 | "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp" | |
56 | }; | |
57 | ||
832ffa1c AG |
58 | enum a64_shift_type { |
59 | A64_SHIFT_TYPE_LSL = 0, | |
60 | A64_SHIFT_TYPE_LSR = 1, | |
61 | A64_SHIFT_TYPE_ASR = 2, | |
62 | A64_SHIFT_TYPE_ROR = 3 | |
63 | }; | |
64 | ||
384b26fb AB |
65 | /* Table based decoder typedefs - used when the relevant bits for decode |
66 | * are too awkwardly scattered across the instruction (eg SIMD). | |
67 | */ | |
68 | typedef void AArch64DecodeFn(DisasContext *s, uint32_t insn); | |
69 | ||
70 | typedef struct AArch64DecodeTable { | |
71 | uint32_t pattern; | |
72 | uint32_t mask; | |
73 | AArch64DecodeFn *disas_fn; | |
74 | } AArch64DecodeTable; | |
75 | ||
1f8a73af | 76 | /* Function prototype for gen_ functions for calling Neon helpers */ |
0a79bc87 | 77 | typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32); |
1f8a73af | 78 | typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32); |
6d9571f7 | 79 | typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32); |
70d7f984 | 80 | typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64); |
a847f32c | 81 | typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64); |
d980fd59 PM |
82 | typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64); |
83 | typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64); | |
70d7f984 | 84 | typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32); |
8908f4d1 AB |
85 | typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); |
86 | typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr); | |
6781fa11 | 87 | typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64); |
f6fe04d5 | 88 | typedef void CryptoTwoOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32); |
5acc765c | 89 | typedef void CryptoThreeOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32); |
1f8a73af | 90 | |
14ade10f AG |
91 | /* initialize TCG globals. */ |
92 | void a64_translate_init(void) | |
93 | { | |
94 | int i; | |
95 | ||
96 | cpu_pc = tcg_global_mem_new_i64(TCG_AREG0, | |
97 | offsetof(CPUARMState, pc), | |
98 | "pc"); | |
99 | for (i = 0; i < 32; i++) { | |
100 | cpu_X[i] = tcg_global_mem_new_i64(TCG_AREG0, | |
101 | offsetof(CPUARMState, xregs[i]), | |
102 | regnames[i]); | |
103 | } | |
104 | ||
832ffa1c AG |
105 | cpu_NF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, NF), "NF"); |
106 | cpu_ZF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, ZF), "ZF"); | |
107 | cpu_CF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, CF), "CF"); | |
108 | cpu_VF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, VF), "VF"); | |
fa2ef212 MM |
109 | |
110 | cpu_exclusive_addr = tcg_global_mem_new_i64(TCG_AREG0, | |
111 | offsetof(CPUARMState, exclusive_addr), "exclusive_addr"); | |
112 | cpu_exclusive_val = tcg_global_mem_new_i64(TCG_AREG0, | |
113 | offsetof(CPUARMState, exclusive_val), "exclusive_val"); | |
114 | cpu_exclusive_high = tcg_global_mem_new_i64(TCG_AREG0, | |
115 | offsetof(CPUARMState, exclusive_high), "exclusive_high"); | |
116 | #ifdef CONFIG_USER_ONLY | |
117 | cpu_exclusive_test = tcg_global_mem_new_i64(TCG_AREG0, | |
118 | offsetof(CPUARMState, exclusive_test), "exclusive_test"); | |
119 | cpu_exclusive_info = tcg_global_mem_new_i32(TCG_AREG0, | |
120 | offsetof(CPUARMState, exclusive_info), "exclusive_info"); | |
121 | #endif | |
14ade10f AG |
122 | } |
123 | ||
124 | void aarch64_cpu_dump_state(CPUState *cs, FILE *f, | |
125 | fprintf_function cpu_fprintf, int flags) | |
126 | { | |
127 | ARMCPU *cpu = ARM_CPU(cs); | |
128 | CPUARMState *env = &cpu->env; | |
d356312f | 129 | uint32_t psr = pstate_read(env); |
14ade10f AG |
130 | int i; |
131 | ||
132 | cpu_fprintf(f, "PC=%016"PRIx64" SP=%016"PRIx64"\n", | |
133 | env->pc, env->xregs[31]); | |
134 | for (i = 0; i < 31; i++) { | |
135 | cpu_fprintf(f, "X%02d=%016"PRIx64, i, env->xregs[i]); | |
136 | if ((i % 4) == 3) { | |
137 | cpu_fprintf(f, "\n"); | |
138 | } else { | |
139 | cpu_fprintf(f, " "); | |
140 | } | |
141 | } | |
d356312f PM |
142 | cpu_fprintf(f, "PSTATE=%08x (flags %c%c%c%c)\n", |
143 | psr, | |
144 | psr & PSTATE_N ? 'N' : '-', | |
145 | psr & PSTATE_Z ? 'Z' : '-', | |
146 | psr & PSTATE_C ? 'C' : '-', | |
147 | psr & PSTATE_V ? 'V' : '-'); | |
14ade10f | 148 | cpu_fprintf(f, "\n"); |
f6d8a314 AG |
149 | |
150 | if (flags & CPU_DUMP_FPU) { | |
151 | int numvfpregs = 32; | |
152 | for (i = 0; i < numvfpregs; i += 2) { | |
153 | uint64_t vlo = float64_val(env->vfp.regs[i * 2]); | |
154 | uint64_t vhi = float64_val(env->vfp.regs[(i * 2) + 1]); | |
155 | cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 " ", | |
156 | i, vhi, vlo); | |
157 | vlo = float64_val(env->vfp.regs[(i + 1) * 2]); | |
158 | vhi = float64_val(env->vfp.regs[((i + 1) * 2) + 1]); | |
159 | cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 "\n", | |
160 | i + 1, vhi, vlo); | |
161 | } | |
162 | cpu_fprintf(f, "FPCR: %08x FPSR: %08x\n", | |
163 | vfp_get_fpcr(env), vfp_get_fpsr(env)); | |
164 | } | |
14ade10f AG |
165 | } |
166 | ||
167 | void gen_a64_set_pc_im(uint64_t val) | |
168 | { | |
169 | tcg_gen_movi_i64(cpu_pc, val); | |
170 | } | |
171 | ||
d4a2dc67 | 172 | static void gen_exception_internal(int excp) |
14ade10f | 173 | { |
d4a2dc67 PM |
174 | TCGv_i32 tcg_excp = tcg_const_i32(excp); |
175 | ||
176 | assert(excp_is_internal(excp)); | |
177 | gen_helper_exception_internal(cpu_env, tcg_excp); | |
178 | tcg_temp_free_i32(tcg_excp); | |
179 | } | |
180 | ||
181 | static void gen_exception(int excp, uint32_t syndrome) | |
182 | { | |
183 | TCGv_i32 tcg_excp = tcg_const_i32(excp); | |
184 | TCGv_i32 tcg_syn = tcg_const_i32(syndrome); | |
185 | ||
186 | gen_helper_exception_with_syndrome(cpu_env, tcg_excp, tcg_syn); | |
187 | tcg_temp_free_i32(tcg_syn); | |
188 | tcg_temp_free_i32(tcg_excp); | |
189 | } | |
190 | ||
191 | static void gen_exception_internal_insn(DisasContext *s, int offset, int excp) | |
192 | { | |
193 | gen_a64_set_pc_im(s->pc - offset); | |
194 | gen_exception_internal(excp); | |
195 | s->is_jmp = DISAS_EXC; | |
14ade10f AG |
196 | } |
197 | ||
d4a2dc67 PM |
198 | static void gen_exception_insn(DisasContext *s, int offset, int excp, |
199 | uint32_t syndrome) | |
14ade10f AG |
200 | { |
201 | gen_a64_set_pc_im(s->pc - offset); | |
d4a2dc67 | 202 | gen_exception(excp, syndrome); |
40f860cd PM |
203 | s->is_jmp = DISAS_EXC; |
204 | } | |
205 | ||
206 | static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest) | |
207 | { | |
208 | /* No direct tb linking with singlestep or deterministic io */ | |
209 | if (s->singlestep_enabled || (s->tb->cflags & CF_LAST_IO)) { | |
210 | return false; | |
211 | } | |
212 | ||
213 | /* Only link tbs from inside the same guest page */ | |
214 | if ((s->tb->pc & TARGET_PAGE_MASK) != (dest & TARGET_PAGE_MASK)) { | |
215 | return false; | |
216 | } | |
217 | ||
218 | return true; | |
219 | } | |
220 | ||
221 | static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest) | |
222 | { | |
223 | TranslationBlock *tb; | |
224 | ||
225 | tb = s->tb; | |
226 | if (use_goto_tb(s, n, dest)) { | |
227 | tcg_gen_goto_tb(n); | |
228 | gen_a64_set_pc_im(dest); | |
0624976f | 229 | tcg_gen_exit_tb((intptr_t)tb + n); |
40f860cd PM |
230 | s->is_jmp = DISAS_TB_JUMP; |
231 | } else { | |
232 | gen_a64_set_pc_im(dest); | |
233 | if (s->singlestep_enabled) { | |
d4a2dc67 | 234 | gen_exception_internal(EXCP_DEBUG); |
40f860cd PM |
235 | } |
236 | tcg_gen_exit_tb(0); | |
237 | s->is_jmp = DISAS_JUMP; | |
238 | } | |
14ade10f AG |
239 | } |
240 | ||
ad7ee8a2 | 241 | static void unallocated_encoding(DisasContext *s) |
14ade10f | 242 | { |
d4a2dc67 PM |
243 | /* Unallocated and reserved encodings are uncategorized */ |
244 | gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized()); | |
14ade10f AG |
245 | } |
246 | ||
ad7ee8a2 CF |
247 | #define unsupported_encoding(s, insn) \ |
248 | do { \ | |
249 | qemu_log_mask(LOG_UNIMP, \ | |
250 | "%s:%d: unsupported instruction encoding 0x%08x " \ | |
251 | "at pc=%016" PRIx64 "\n", \ | |
252 | __FILE__, __LINE__, insn, s->pc - 4); \ | |
253 | unallocated_encoding(s); \ | |
254 | } while (0); | |
14ade10f | 255 | |
11e169de AG |
256 | static void init_tmp_a64_array(DisasContext *s) |
257 | { | |
258 | #ifdef CONFIG_DEBUG_TCG | |
259 | int i; | |
260 | for (i = 0; i < ARRAY_SIZE(s->tmp_a64); i++) { | |
261 | TCGV_UNUSED_I64(s->tmp_a64[i]); | |
262 | } | |
263 | #endif | |
264 | s->tmp_a64_count = 0; | |
265 | } | |
266 | ||
267 | static void free_tmp_a64(DisasContext *s) | |
268 | { | |
269 | int i; | |
270 | for (i = 0; i < s->tmp_a64_count; i++) { | |
271 | tcg_temp_free_i64(s->tmp_a64[i]); | |
272 | } | |
273 | init_tmp_a64_array(s); | |
274 | } | |
275 | ||
276 | static TCGv_i64 new_tmp_a64(DisasContext *s) | |
277 | { | |
278 | assert(s->tmp_a64_count < TMP_A64_MAX); | |
279 | return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_new_i64(); | |
280 | } | |
281 | ||
282 | static TCGv_i64 new_tmp_a64_zero(DisasContext *s) | |
283 | { | |
284 | TCGv_i64 t = new_tmp_a64(s); | |
285 | tcg_gen_movi_i64(t, 0); | |
286 | return t; | |
287 | } | |
288 | ||
71b46089 AG |
289 | /* |
290 | * Register access functions | |
291 | * | |
292 | * These functions are used for directly accessing a register in where | |
293 | * changes to the final register value are likely to be made. If you | |
294 | * need to use a register for temporary calculation (e.g. index type | |
295 | * operations) use the read_* form. | |
296 | * | |
297 | * B1.2.1 Register mappings | |
298 | * | |
299 | * In instruction register encoding 31 can refer to ZR (zero register) or | |
300 | * the SP (stack pointer) depending on context. In QEMU's case we map SP | |
301 | * to cpu_X[31] and ZR accesses to a temporary which can be discarded. | |
302 | * This is the point of the _sp forms. | |
303 | */ | |
11e169de AG |
304 | static TCGv_i64 cpu_reg(DisasContext *s, int reg) |
305 | { | |
306 | if (reg == 31) { | |
307 | return new_tmp_a64_zero(s); | |
308 | } else { | |
309 | return cpu_X[reg]; | |
310 | } | |
311 | } | |
312 | ||
71b46089 AG |
313 | /* register access for when 31 == SP */ |
314 | static TCGv_i64 cpu_reg_sp(DisasContext *s, int reg) | |
315 | { | |
316 | return cpu_X[reg]; | |
317 | } | |
318 | ||
60e53388 AG |
319 | /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64 |
320 | * representing the register contents. This TCGv is an auto-freed | |
321 | * temporary so it need not be explicitly freed, and may be modified. | |
322 | */ | |
323 | static TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf) | |
324 | { | |
325 | TCGv_i64 v = new_tmp_a64(s); | |
326 | if (reg != 31) { | |
327 | if (sf) { | |
328 | tcg_gen_mov_i64(v, cpu_X[reg]); | |
329 | } else { | |
330 | tcg_gen_ext32u_i64(v, cpu_X[reg]); | |
331 | } | |
332 | } else { | |
333 | tcg_gen_movi_i64(v, 0); | |
334 | } | |
335 | return v; | |
336 | } | |
337 | ||
4a08d475 PM |
338 | static TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf) |
339 | { | |
340 | TCGv_i64 v = new_tmp_a64(s); | |
341 | if (sf) { | |
342 | tcg_gen_mov_i64(v, cpu_X[reg]); | |
343 | } else { | |
344 | tcg_gen_ext32u_i64(v, cpu_X[reg]); | |
345 | } | |
346 | return v; | |
347 | } | |
348 | ||
90e49638 PM |
349 | /* We should have at some point before trying to access an FP register |
350 | * done the necessary access check, so assert that | |
351 | * (a) we did the check and | |
352 | * (b) we didn't then just plough ahead anyway if it failed. | |
353 | * Print the instruction pattern in the abort message so we can figure | |
354 | * out what we need to fix if a user encounters this problem in the wild. | |
355 | */ | |
356 | static inline void assert_fp_access_checked(DisasContext *s) | |
357 | { | |
358 | #ifdef CONFIG_DEBUG_TCG | |
359 | if (unlikely(!s->fp_access_checked || !s->cpacr_fpen)) { | |
360 | fprintf(stderr, "target-arm: FP access check missing for " | |
361 | "instruction 0x%08x\n", s->insn); | |
362 | abort(); | |
363 | } | |
364 | #endif | |
365 | } | |
366 | ||
72430bf5 AB |
367 | /* Return the offset into CPUARMState of an element of specified |
368 | * size, 'element' places in from the least significant end of | |
369 | * the FP/vector register Qn. | |
370 | */ | |
90e49638 PM |
371 | static inline int vec_reg_offset(DisasContext *s, int regno, |
372 | int element, TCGMemOp size) | |
72430bf5 AB |
373 | { |
374 | int offs = offsetof(CPUARMState, vfp.regs[regno * 2]); | |
375 | #ifdef HOST_WORDS_BIGENDIAN | |
376 | /* This is complicated slightly because vfp.regs[2n] is | |
377 | * still the low half and vfp.regs[2n+1] the high half | |
378 | * of the 128 bit vector, even on big endian systems. | |
379 | * Calculate the offset assuming a fully bigendian 128 bits, | |
380 | * then XOR to account for the order of the two 64 bit halves. | |
381 | */ | |
382 | offs += (16 - ((element + 1) * (1 << size))); | |
383 | offs ^= 8; | |
384 | #else | |
385 | offs += element * (1 << size); | |
386 | #endif | |
90e49638 | 387 | assert_fp_access_checked(s); |
72430bf5 AB |
388 | return offs; |
389 | } | |
390 | ||
e2f90565 PM |
391 | /* Return the offset into CPUARMState of a slice (from |
392 | * the least significant end) of FP register Qn (ie | |
393 | * Dn, Sn, Hn or Bn). | |
394 | * (Note that this is not the same mapping as for A32; see cpu.h) | |
395 | */ | |
90e49638 | 396 | static inline int fp_reg_offset(DisasContext *s, int regno, TCGMemOp size) |
e2f90565 PM |
397 | { |
398 | int offs = offsetof(CPUARMState, vfp.regs[regno * 2]); | |
399 | #ifdef HOST_WORDS_BIGENDIAN | |
400 | offs += (8 - (1 << size)); | |
401 | #endif | |
90e49638 | 402 | assert_fp_access_checked(s); |
e2f90565 PM |
403 | return offs; |
404 | } | |
405 | ||
406 | /* Offset of the high half of the 128 bit vector Qn */ | |
90e49638 | 407 | static inline int fp_reg_hi_offset(DisasContext *s, int regno) |
e2f90565 | 408 | { |
90e49638 | 409 | assert_fp_access_checked(s); |
e2f90565 PM |
410 | return offsetof(CPUARMState, vfp.regs[regno * 2 + 1]); |
411 | } | |
412 | ||
ec73d2e0 AG |
413 | /* Convenience accessors for reading and writing single and double |
414 | * FP registers. Writing clears the upper parts of the associated | |
415 | * 128 bit vector register, as required by the architecture. | |
416 | * Note that unlike the GP register accessors, the values returned | |
417 | * by the read functions must be manually freed. | |
418 | */ | |
419 | static TCGv_i64 read_fp_dreg(DisasContext *s, int reg) | |
420 | { | |
421 | TCGv_i64 v = tcg_temp_new_i64(); | |
422 | ||
90e49638 | 423 | tcg_gen_ld_i64(v, cpu_env, fp_reg_offset(s, reg, MO_64)); |
ec73d2e0 AG |
424 | return v; |
425 | } | |
426 | ||
427 | static TCGv_i32 read_fp_sreg(DisasContext *s, int reg) | |
428 | { | |
429 | TCGv_i32 v = tcg_temp_new_i32(); | |
430 | ||
90e49638 | 431 | tcg_gen_ld_i32(v, cpu_env, fp_reg_offset(s, reg, MO_32)); |
ec73d2e0 AG |
432 | return v; |
433 | } | |
434 | ||
435 | static void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v) | |
436 | { | |
437 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
438 | ||
90e49638 PM |
439 | tcg_gen_st_i64(v, cpu_env, fp_reg_offset(s, reg, MO_64)); |
440 | tcg_gen_st_i64(tcg_zero, cpu_env, fp_reg_hi_offset(s, reg)); | |
ec73d2e0 AG |
441 | tcg_temp_free_i64(tcg_zero); |
442 | } | |
443 | ||
444 | static void write_fp_sreg(DisasContext *s, int reg, TCGv_i32 v) | |
445 | { | |
446 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
447 | ||
448 | tcg_gen_extu_i32_i64(tmp, v); | |
449 | write_fp_dreg(s, reg, tmp); | |
450 | tcg_temp_free_i64(tmp); | |
451 | } | |
452 | ||
453 | static TCGv_ptr get_fpstatus_ptr(void) | |
454 | { | |
455 | TCGv_ptr statusptr = tcg_temp_new_ptr(); | |
456 | int offset; | |
457 | ||
458 | /* In A64 all instructions (both FP and Neon) use the FPCR; | |
459 | * there is no equivalent of the A32 Neon "standard FPSCR value" | |
460 | * and all operations use vfp.fp_status. | |
461 | */ | |
462 | offset = offsetof(CPUARMState, vfp.fp_status); | |
463 | tcg_gen_addi_ptr(statusptr, cpu_env, offset); | |
464 | return statusptr; | |
465 | } | |
466 | ||
832ffa1c AG |
467 | /* Set ZF and NF based on a 64 bit result. This is alas fiddlier |
468 | * than the 32 bit equivalent. | |
469 | */ | |
470 | static inline void gen_set_NZ64(TCGv_i64 result) | |
471 | { | |
472 | TCGv_i64 flag = tcg_temp_new_i64(); | |
473 | ||
474 | tcg_gen_setcondi_i64(TCG_COND_NE, flag, result, 0); | |
475 | tcg_gen_trunc_i64_i32(cpu_ZF, flag); | |
476 | tcg_gen_shri_i64(flag, result, 32); | |
477 | tcg_gen_trunc_i64_i32(cpu_NF, flag); | |
478 | tcg_temp_free_i64(flag); | |
479 | } | |
480 | ||
481 | /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */ | |
482 | static inline void gen_logic_CC(int sf, TCGv_i64 result) | |
483 | { | |
484 | if (sf) { | |
485 | gen_set_NZ64(result); | |
486 | } else { | |
487 | tcg_gen_trunc_i64_i32(cpu_ZF, result); | |
488 | tcg_gen_trunc_i64_i32(cpu_NF, result); | |
489 | } | |
490 | tcg_gen_movi_i32(cpu_CF, 0); | |
491 | tcg_gen_movi_i32(cpu_VF, 0); | |
492 | } | |
493 | ||
b0ff21b4 AB |
494 | /* dest = T0 + T1; compute C, N, V and Z flags */ |
495 | static void gen_add_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | |
496 | { | |
497 | if (sf) { | |
498 | TCGv_i64 result, flag, tmp; | |
499 | result = tcg_temp_new_i64(); | |
500 | flag = tcg_temp_new_i64(); | |
501 | tmp = tcg_temp_new_i64(); | |
502 | ||
503 | tcg_gen_movi_i64(tmp, 0); | |
504 | tcg_gen_add2_i64(result, flag, t0, tmp, t1, tmp); | |
505 | ||
506 | tcg_gen_trunc_i64_i32(cpu_CF, flag); | |
507 | ||
508 | gen_set_NZ64(result); | |
509 | ||
510 | tcg_gen_xor_i64(flag, result, t0); | |
511 | tcg_gen_xor_i64(tmp, t0, t1); | |
512 | tcg_gen_andc_i64(flag, flag, tmp); | |
513 | tcg_temp_free_i64(tmp); | |
514 | tcg_gen_shri_i64(flag, flag, 32); | |
515 | tcg_gen_trunc_i64_i32(cpu_VF, flag); | |
516 | ||
517 | tcg_gen_mov_i64(dest, result); | |
518 | tcg_temp_free_i64(result); | |
519 | tcg_temp_free_i64(flag); | |
520 | } else { | |
521 | /* 32 bit arithmetic */ | |
522 | TCGv_i32 t0_32 = tcg_temp_new_i32(); | |
523 | TCGv_i32 t1_32 = tcg_temp_new_i32(); | |
524 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
525 | ||
526 | tcg_gen_movi_i32(tmp, 0); | |
527 | tcg_gen_trunc_i64_i32(t0_32, t0); | |
528 | tcg_gen_trunc_i64_i32(t1_32, t1); | |
529 | tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, t1_32, tmp); | |
530 | tcg_gen_mov_i32(cpu_ZF, cpu_NF); | |
531 | tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); | |
532 | tcg_gen_xor_i32(tmp, t0_32, t1_32); | |
533 | tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp); | |
534 | tcg_gen_extu_i32_i64(dest, cpu_NF); | |
535 | ||
536 | tcg_temp_free_i32(tmp); | |
537 | tcg_temp_free_i32(t0_32); | |
538 | tcg_temp_free_i32(t1_32); | |
539 | } | |
540 | } | |
541 | ||
542 | /* dest = T0 - T1; compute C, N, V and Z flags */ | |
543 | static void gen_sub_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | |
544 | { | |
545 | if (sf) { | |
546 | /* 64 bit arithmetic */ | |
547 | TCGv_i64 result, flag, tmp; | |
548 | ||
549 | result = tcg_temp_new_i64(); | |
550 | flag = tcg_temp_new_i64(); | |
551 | tcg_gen_sub_i64(result, t0, t1); | |
552 | ||
553 | gen_set_NZ64(result); | |
554 | ||
555 | tcg_gen_setcond_i64(TCG_COND_GEU, flag, t0, t1); | |
556 | tcg_gen_trunc_i64_i32(cpu_CF, flag); | |
557 | ||
558 | tcg_gen_xor_i64(flag, result, t0); | |
559 | tmp = tcg_temp_new_i64(); | |
560 | tcg_gen_xor_i64(tmp, t0, t1); | |
561 | tcg_gen_and_i64(flag, flag, tmp); | |
562 | tcg_temp_free_i64(tmp); | |
563 | tcg_gen_shri_i64(flag, flag, 32); | |
564 | tcg_gen_trunc_i64_i32(cpu_VF, flag); | |
565 | tcg_gen_mov_i64(dest, result); | |
566 | tcg_temp_free_i64(flag); | |
567 | tcg_temp_free_i64(result); | |
568 | } else { | |
569 | /* 32 bit arithmetic */ | |
570 | TCGv_i32 t0_32 = tcg_temp_new_i32(); | |
571 | TCGv_i32 t1_32 = tcg_temp_new_i32(); | |
572 | TCGv_i32 tmp; | |
573 | ||
574 | tcg_gen_trunc_i64_i32(t0_32, t0); | |
575 | tcg_gen_trunc_i64_i32(t1_32, t1); | |
576 | tcg_gen_sub_i32(cpu_NF, t0_32, t1_32); | |
577 | tcg_gen_mov_i32(cpu_ZF, cpu_NF); | |
578 | tcg_gen_setcond_i32(TCG_COND_GEU, cpu_CF, t0_32, t1_32); | |
579 | tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); | |
580 | tmp = tcg_temp_new_i32(); | |
581 | tcg_gen_xor_i32(tmp, t0_32, t1_32); | |
582 | tcg_temp_free_i32(t0_32); | |
583 | tcg_temp_free_i32(t1_32); | |
584 | tcg_gen_and_i32(cpu_VF, cpu_VF, tmp); | |
585 | tcg_temp_free_i32(tmp); | |
586 | tcg_gen_extu_i32_i64(dest, cpu_NF); | |
587 | } | |
588 | } | |
589 | ||
643dbb07 CF |
590 | /* dest = T0 + T1 + CF; do not compute flags. */ |
591 | static void gen_adc(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | |
592 | { | |
593 | TCGv_i64 flag = tcg_temp_new_i64(); | |
594 | tcg_gen_extu_i32_i64(flag, cpu_CF); | |
595 | tcg_gen_add_i64(dest, t0, t1); | |
596 | tcg_gen_add_i64(dest, dest, flag); | |
597 | tcg_temp_free_i64(flag); | |
598 | ||
599 | if (!sf) { | |
600 | tcg_gen_ext32u_i64(dest, dest); | |
601 | } | |
602 | } | |
603 | ||
604 | /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */ | |
605 | static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | |
606 | { | |
607 | if (sf) { | |
608 | TCGv_i64 result, cf_64, vf_64, tmp; | |
609 | result = tcg_temp_new_i64(); | |
610 | cf_64 = tcg_temp_new_i64(); | |
611 | vf_64 = tcg_temp_new_i64(); | |
612 | tmp = tcg_const_i64(0); | |
613 | ||
614 | tcg_gen_extu_i32_i64(cf_64, cpu_CF); | |
615 | tcg_gen_add2_i64(result, cf_64, t0, tmp, cf_64, tmp); | |
616 | tcg_gen_add2_i64(result, cf_64, result, cf_64, t1, tmp); | |
617 | tcg_gen_trunc_i64_i32(cpu_CF, cf_64); | |
618 | gen_set_NZ64(result); | |
619 | ||
620 | tcg_gen_xor_i64(vf_64, result, t0); | |
621 | tcg_gen_xor_i64(tmp, t0, t1); | |
622 | tcg_gen_andc_i64(vf_64, vf_64, tmp); | |
623 | tcg_gen_shri_i64(vf_64, vf_64, 32); | |
624 | tcg_gen_trunc_i64_i32(cpu_VF, vf_64); | |
625 | ||
626 | tcg_gen_mov_i64(dest, result); | |
627 | ||
628 | tcg_temp_free_i64(tmp); | |
629 | tcg_temp_free_i64(vf_64); | |
630 | tcg_temp_free_i64(cf_64); | |
631 | tcg_temp_free_i64(result); | |
632 | } else { | |
633 | TCGv_i32 t0_32, t1_32, tmp; | |
634 | t0_32 = tcg_temp_new_i32(); | |
635 | t1_32 = tcg_temp_new_i32(); | |
636 | tmp = tcg_const_i32(0); | |
637 | ||
638 | tcg_gen_trunc_i64_i32(t0_32, t0); | |
639 | tcg_gen_trunc_i64_i32(t1_32, t1); | |
640 | tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, cpu_CF, tmp); | |
641 | tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1_32, tmp); | |
642 | ||
643 | tcg_gen_mov_i32(cpu_ZF, cpu_NF); | |
644 | tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); | |
645 | tcg_gen_xor_i32(tmp, t0_32, t1_32); | |
646 | tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp); | |
647 | tcg_gen_extu_i32_i64(dest, cpu_NF); | |
648 | ||
649 | tcg_temp_free_i32(tmp); | |
650 | tcg_temp_free_i32(t1_32); | |
651 | tcg_temp_free_i32(t0_32); | |
652 | } | |
653 | } | |
654 | ||
4a08d475 PM |
655 | /* |
656 | * Load/Store generators | |
657 | */ | |
658 | ||
659 | /* | |
60510aed | 660 | * Store from GPR register to memory. |
4a08d475 | 661 | */ |
60510aed PM |
662 | static void do_gpr_st_memidx(DisasContext *s, TCGv_i64 source, |
663 | TCGv_i64 tcg_addr, int size, int memidx) | |
664 | { | |
665 | g_assert(size <= 3); | |
666 | tcg_gen_qemu_st_i64(source, tcg_addr, memidx, MO_TE + size); | |
667 | } | |
668 | ||
4a08d475 PM |
669 | static void do_gpr_st(DisasContext *s, TCGv_i64 source, |
670 | TCGv_i64 tcg_addr, int size) | |
671 | { | |
60510aed | 672 | do_gpr_st_memidx(s, source, tcg_addr, size, get_mem_index(s)); |
4a08d475 PM |
673 | } |
674 | ||
675 | /* | |
676 | * Load from memory to GPR register | |
677 | */ | |
60510aed PM |
678 | static void do_gpr_ld_memidx(DisasContext *s, TCGv_i64 dest, TCGv_i64 tcg_addr, |
679 | int size, bool is_signed, bool extend, int memidx) | |
4a08d475 PM |
680 | { |
681 | TCGMemOp memop = MO_TE + size; | |
682 | ||
683 | g_assert(size <= 3); | |
684 | ||
685 | if (is_signed) { | |
686 | memop += MO_SIGN; | |
687 | } | |
688 | ||
60510aed | 689 | tcg_gen_qemu_ld_i64(dest, tcg_addr, memidx, memop); |
4a08d475 PM |
690 | |
691 | if (extend && is_signed) { | |
692 | g_assert(size < 3); | |
693 | tcg_gen_ext32u_i64(dest, dest); | |
694 | } | |
695 | } | |
696 | ||
60510aed PM |
697 | static void do_gpr_ld(DisasContext *s, TCGv_i64 dest, TCGv_i64 tcg_addr, |
698 | int size, bool is_signed, bool extend) | |
699 | { | |
700 | do_gpr_ld_memidx(s, dest, tcg_addr, size, is_signed, extend, | |
701 | get_mem_index(s)); | |
702 | } | |
703 | ||
4a08d475 PM |
704 | /* |
705 | * Store from FP register to memory | |
706 | */ | |
707 | static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, int size) | |
708 | { | |
709 | /* This writes the bottom N bits of a 128 bit wide vector to memory */ | |
4a08d475 | 710 | TCGv_i64 tmp = tcg_temp_new_i64(); |
90e49638 | 711 | tcg_gen_ld_i64(tmp, cpu_env, fp_reg_offset(s, srcidx, MO_64)); |
4a08d475 | 712 | if (size < 4) { |
4a08d475 PM |
713 | tcg_gen_qemu_st_i64(tmp, tcg_addr, get_mem_index(s), MO_TE + size); |
714 | } else { | |
715 | TCGv_i64 tcg_hiaddr = tcg_temp_new_i64(); | |
4a08d475 PM |
716 | tcg_gen_qemu_st_i64(tmp, tcg_addr, get_mem_index(s), MO_TEQ); |
717 | tcg_gen_qemu_st64(tmp, tcg_addr, get_mem_index(s)); | |
90e49638 | 718 | tcg_gen_ld_i64(tmp, cpu_env, fp_reg_hi_offset(s, srcidx)); |
4a08d475 PM |
719 | tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8); |
720 | tcg_gen_qemu_st_i64(tmp, tcg_hiaddr, get_mem_index(s), MO_TEQ); | |
721 | tcg_temp_free_i64(tcg_hiaddr); | |
722 | } | |
723 | ||
724 | tcg_temp_free_i64(tmp); | |
725 | } | |
726 | ||
727 | /* | |
728 | * Load from memory to FP register | |
729 | */ | |
730 | static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size) | |
731 | { | |
732 | /* This always zero-extends and writes to a full 128 bit wide vector */ | |
4a08d475 PM |
733 | TCGv_i64 tmplo = tcg_temp_new_i64(); |
734 | TCGv_i64 tmphi; | |
735 | ||
736 | if (size < 4) { | |
737 | TCGMemOp memop = MO_TE + size; | |
738 | tmphi = tcg_const_i64(0); | |
739 | tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), memop); | |
740 | } else { | |
741 | TCGv_i64 tcg_hiaddr; | |
742 | tmphi = tcg_temp_new_i64(); | |
743 | tcg_hiaddr = tcg_temp_new_i64(); | |
744 | ||
745 | tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), MO_TEQ); | |
746 | tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8); | |
747 | tcg_gen_qemu_ld_i64(tmphi, tcg_hiaddr, get_mem_index(s), MO_TEQ); | |
748 | tcg_temp_free_i64(tcg_hiaddr); | |
749 | } | |
750 | ||
90e49638 PM |
751 | tcg_gen_st_i64(tmplo, cpu_env, fp_reg_offset(s, destidx, MO_64)); |
752 | tcg_gen_st_i64(tmphi, cpu_env, fp_reg_hi_offset(s, destidx)); | |
4a08d475 PM |
753 | |
754 | tcg_temp_free_i64(tmplo); | |
755 | tcg_temp_free_i64(tmphi); | |
756 | } | |
757 | ||
72430bf5 AB |
758 | /* |
759 | * Vector load/store helpers. | |
760 | * | |
761 | * The principal difference between this and a FP load is that we don't | |
762 | * zero extend as we are filling a partial chunk of the vector register. | |
763 | * These functions don't support 128 bit loads/stores, which would be | |
764 | * normal load/store operations. | |
a08582f4 PM |
765 | * |
766 | * The _i32 versions are useful when operating on 32 bit quantities | |
767 | * (eg for floating point single or using Neon helper functions). | |
72430bf5 AB |
768 | */ |
769 | ||
770 | /* Get value of an element within a vector register */ | |
771 | static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx, | |
772 | int element, TCGMemOp memop) | |
773 | { | |
90e49638 | 774 | int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE); |
72430bf5 AB |
775 | switch (memop) { |
776 | case MO_8: | |
777 | tcg_gen_ld8u_i64(tcg_dest, cpu_env, vect_off); | |
778 | break; | |
779 | case MO_16: | |
780 | tcg_gen_ld16u_i64(tcg_dest, cpu_env, vect_off); | |
781 | break; | |
782 | case MO_32: | |
783 | tcg_gen_ld32u_i64(tcg_dest, cpu_env, vect_off); | |
784 | break; | |
785 | case MO_8|MO_SIGN: | |
786 | tcg_gen_ld8s_i64(tcg_dest, cpu_env, vect_off); | |
787 | break; | |
788 | case MO_16|MO_SIGN: | |
789 | tcg_gen_ld16s_i64(tcg_dest, cpu_env, vect_off); | |
790 | break; | |
791 | case MO_32|MO_SIGN: | |
792 | tcg_gen_ld32s_i64(tcg_dest, cpu_env, vect_off); | |
793 | break; | |
794 | case MO_64: | |
795 | case MO_64|MO_SIGN: | |
796 | tcg_gen_ld_i64(tcg_dest, cpu_env, vect_off); | |
797 | break; | |
798 | default: | |
799 | g_assert_not_reached(); | |
800 | } | |
801 | } | |
802 | ||
a08582f4 PM |
803 | static void read_vec_element_i32(DisasContext *s, TCGv_i32 tcg_dest, int srcidx, |
804 | int element, TCGMemOp memop) | |
805 | { | |
90e49638 | 806 | int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE); |
a08582f4 PM |
807 | switch (memop) { |
808 | case MO_8: | |
809 | tcg_gen_ld8u_i32(tcg_dest, cpu_env, vect_off); | |
810 | break; | |
811 | case MO_16: | |
812 | tcg_gen_ld16u_i32(tcg_dest, cpu_env, vect_off); | |
813 | break; | |
814 | case MO_8|MO_SIGN: | |
815 | tcg_gen_ld8s_i32(tcg_dest, cpu_env, vect_off); | |
816 | break; | |
817 | case MO_16|MO_SIGN: | |
818 | tcg_gen_ld16s_i32(tcg_dest, cpu_env, vect_off); | |
819 | break; | |
820 | case MO_32: | |
821 | case MO_32|MO_SIGN: | |
822 | tcg_gen_ld_i32(tcg_dest, cpu_env, vect_off); | |
823 | break; | |
824 | default: | |
825 | g_assert_not_reached(); | |
826 | } | |
827 | } | |
828 | ||
72430bf5 AB |
829 | /* Set value of an element within a vector register */ |
830 | static void write_vec_element(DisasContext *s, TCGv_i64 tcg_src, int destidx, | |
831 | int element, TCGMemOp memop) | |
832 | { | |
90e49638 | 833 | int vect_off = vec_reg_offset(s, destidx, element, memop & MO_SIZE); |
72430bf5 AB |
834 | switch (memop) { |
835 | case MO_8: | |
836 | tcg_gen_st8_i64(tcg_src, cpu_env, vect_off); | |
837 | break; | |
838 | case MO_16: | |
839 | tcg_gen_st16_i64(tcg_src, cpu_env, vect_off); | |
840 | break; | |
841 | case MO_32: | |
842 | tcg_gen_st32_i64(tcg_src, cpu_env, vect_off); | |
843 | break; | |
844 | case MO_64: | |
845 | tcg_gen_st_i64(tcg_src, cpu_env, vect_off); | |
846 | break; | |
847 | default: | |
848 | g_assert_not_reached(); | |
849 | } | |
850 | } | |
851 | ||
1f8a73af PM |
852 | static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src, |
853 | int destidx, int element, TCGMemOp memop) | |
854 | { | |
90e49638 | 855 | int vect_off = vec_reg_offset(s, destidx, element, memop & MO_SIZE); |
1f8a73af PM |
856 | switch (memop) { |
857 | case MO_8: | |
858 | tcg_gen_st8_i32(tcg_src, cpu_env, vect_off); | |
859 | break; | |
860 | case MO_16: | |
861 | tcg_gen_st16_i32(tcg_src, cpu_env, vect_off); | |
862 | break; | |
863 | case MO_32: | |
864 | tcg_gen_st_i32(tcg_src, cpu_env, vect_off); | |
865 | break; | |
866 | default: | |
867 | g_assert_not_reached(); | |
868 | } | |
869 | } | |
870 | ||
72430bf5 AB |
871 | /* Clear the high 64 bits of a 128 bit vector (in general non-quad |
872 | * vector ops all need to do this). | |
873 | */ | |
874 | static void clear_vec_high(DisasContext *s, int rd) | |
875 | { | |
876 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
877 | ||
878 | write_vec_element(s, tcg_zero, rd, 1, MO_64); | |
879 | tcg_temp_free_i64(tcg_zero); | |
880 | } | |
881 | ||
882 | /* Store from vector register to memory */ | |
883 | static void do_vec_st(DisasContext *s, int srcidx, int element, | |
884 | TCGv_i64 tcg_addr, int size) | |
885 | { | |
886 | TCGMemOp memop = MO_TE + size; | |
887 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
888 | ||
889 | read_vec_element(s, tcg_tmp, srcidx, element, size); | |
890 | tcg_gen_qemu_st_i64(tcg_tmp, tcg_addr, get_mem_index(s), memop); | |
891 | ||
892 | tcg_temp_free_i64(tcg_tmp); | |
893 | } | |
894 | ||
895 | /* Load from memory to vector register */ | |
896 | static void do_vec_ld(DisasContext *s, int destidx, int element, | |
897 | TCGv_i64 tcg_addr, int size) | |
898 | { | |
899 | TCGMemOp memop = MO_TE + size; | |
900 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
901 | ||
902 | tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr, get_mem_index(s), memop); | |
903 | write_vec_element(s, tcg_tmp, destidx, element, size); | |
904 | ||
905 | tcg_temp_free_i64(tcg_tmp); | |
906 | } | |
907 | ||
8c6afa6a PM |
908 | /* Check that FP/Neon access is enabled. If it is, return |
909 | * true. If not, emit code to generate an appropriate exception, | |
910 | * and return false; the caller should not emit any code for | |
911 | * the instruction. Note that this check must happen after all | |
912 | * unallocated-encoding checks (otherwise the syndrome information | |
913 | * for the resulting exception will be incorrect). | |
914 | */ | |
915 | static inline bool fp_access_check(DisasContext *s) | |
916 | { | |
90e49638 PM |
917 | assert(!s->fp_access_checked); |
918 | s->fp_access_checked = true; | |
919 | ||
8c6afa6a PM |
920 | if (s->cpacr_fpen) { |
921 | return true; | |
922 | } | |
923 | ||
924 | gen_exception_insn(s, 4, EXCP_UDEF, syn_fp_access_trap(1, 0xe, false)); | |
925 | return false; | |
926 | } | |
927 | ||
229b7a05 AB |
928 | /* |
929 | * This utility function is for doing register extension with an | |
930 | * optional shift. You will likely want to pass a temporary for the | |
931 | * destination register. See DecodeRegExtend() in the ARM ARM. | |
932 | */ | |
933 | static void ext_and_shift_reg(TCGv_i64 tcg_out, TCGv_i64 tcg_in, | |
934 | int option, unsigned int shift) | |
935 | { | |
936 | int extsize = extract32(option, 0, 2); | |
937 | bool is_signed = extract32(option, 2, 1); | |
938 | ||
939 | if (is_signed) { | |
940 | switch (extsize) { | |
941 | case 0: | |
942 | tcg_gen_ext8s_i64(tcg_out, tcg_in); | |
943 | break; | |
944 | case 1: | |
945 | tcg_gen_ext16s_i64(tcg_out, tcg_in); | |
946 | break; | |
947 | case 2: | |
948 | tcg_gen_ext32s_i64(tcg_out, tcg_in); | |
949 | break; | |
950 | case 3: | |
951 | tcg_gen_mov_i64(tcg_out, tcg_in); | |
952 | break; | |
953 | } | |
954 | } else { | |
955 | switch (extsize) { | |
956 | case 0: | |
957 | tcg_gen_ext8u_i64(tcg_out, tcg_in); | |
958 | break; | |
959 | case 1: | |
960 | tcg_gen_ext16u_i64(tcg_out, tcg_in); | |
961 | break; | |
962 | case 2: | |
963 | tcg_gen_ext32u_i64(tcg_out, tcg_in); | |
964 | break; | |
965 | case 3: | |
966 | tcg_gen_mov_i64(tcg_out, tcg_in); | |
967 | break; | |
968 | } | |
969 | } | |
970 | ||
971 | if (shift) { | |
972 | tcg_gen_shli_i64(tcg_out, tcg_out, shift); | |
973 | } | |
974 | } | |
975 | ||
4a08d475 PM |
976 | static inline void gen_check_sp_alignment(DisasContext *s) |
977 | { | |
978 | /* The AArch64 architecture mandates that (if enabled via PSTATE | |
979 | * or SCTLR bits) there is a check that SP is 16-aligned on every | |
980 | * SP-relative load or store (with an exception generated if it is not). | |
981 | * In line with general QEMU practice regarding misaligned accesses, | |
982 | * we omit these checks for the sake of guest program performance. | |
983 | * This function is provided as a hook so we can more easily add these | |
984 | * checks in future (possibly as a "favour catching guest program bugs | |
985 | * over speed" user selectable option). | |
986 | */ | |
987 | } | |
988 | ||
384b26fb AB |
989 | /* |
990 | * This provides a simple table based table lookup decoder. It is | |
991 | * intended to be used when the relevant bits for decode are too | |
992 | * awkwardly placed and switch/if based logic would be confusing and | |
993 | * deeply nested. Since it's a linear search through the table, tables | |
994 | * should be kept small. | |
995 | * | |
996 | * It returns the first handler where insn & mask == pattern, or | |
997 | * NULL if there is no match. | |
998 | * The table is terminated by an empty mask (i.e. 0) | |
999 | */ | |
1000 | static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table, | |
1001 | uint32_t insn) | |
1002 | { | |
1003 | const AArch64DecodeTable *tptr = table; | |
1004 | ||
1005 | while (tptr->mask) { | |
1006 | if ((insn & tptr->mask) == tptr->pattern) { | |
1007 | return tptr->disas_fn; | |
1008 | } | |
1009 | tptr++; | |
1010 | } | |
1011 | return NULL; | |
1012 | } | |
1013 | ||
ad7ee8a2 CF |
1014 | /* |
1015 | * the instruction disassembly implemented here matches | |
1016 | * the instruction encoding classifications in chapter 3 (C3) | |
1017 | * of the ARM Architecture Reference Manual (DDI0487A_a) | |
1018 | */ | |
1019 | ||
11e169de AG |
1020 | /* C3.2.7 Unconditional branch (immediate) |
1021 | * 31 30 26 25 0 | |
1022 | * +----+-----------+-------------------------------------+ | |
1023 | * | op | 0 0 1 0 1 | imm26 | | |
1024 | * +----+-----------+-------------------------------------+ | |
1025 | */ | |
ad7ee8a2 CF |
1026 | static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) |
1027 | { | |
11e169de AG |
1028 | uint64_t addr = s->pc + sextract32(insn, 0, 26) * 4 - 4; |
1029 | ||
1030 | if (insn & (1 << 31)) { | |
1031 | /* C5.6.26 BL Branch with link */ | |
1032 | tcg_gen_movi_i64(cpu_reg(s, 30), s->pc); | |
1033 | } | |
1034 | ||
1035 | /* C5.6.20 B Branch / C5.6.26 BL Branch with link */ | |
1036 | gen_goto_tb(s, 0, addr); | |
ad7ee8a2 CF |
1037 | } |
1038 | ||
60e53388 AG |
1039 | /* C3.2.1 Compare & branch (immediate) |
1040 | * 31 30 25 24 23 5 4 0 | |
1041 | * +----+-------------+----+---------------------+--------+ | |
1042 | * | sf | 0 1 1 0 1 0 | op | imm19 | Rt | | |
1043 | * +----+-------------+----+---------------------+--------+ | |
1044 | */ | |
ad7ee8a2 CF |
1045 | static void disas_comp_b_imm(DisasContext *s, uint32_t insn) |
1046 | { | |
60e53388 AG |
1047 | unsigned int sf, op, rt; |
1048 | uint64_t addr; | |
1049 | int label_match; | |
1050 | TCGv_i64 tcg_cmp; | |
1051 | ||
1052 | sf = extract32(insn, 31, 1); | |
1053 | op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */ | |
1054 | rt = extract32(insn, 0, 5); | |
1055 | addr = s->pc + sextract32(insn, 5, 19) * 4 - 4; | |
1056 | ||
1057 | tcg_cmp = read_cpu_reg(s, rt, sf); | |
1058 | label_match = gen_new_label(); | |
1059 | ||
1060 | tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, | |
1061 | tcg_cmp, 0, label_match); | |
1062 | ||
1063 | gen_goto_tb(s, 0, s->pc); | |
1064 | gen_set_label(label_match); | |
1065 | gen_goto_tb(s, 1, addr); | |
ad7ee8a2 CF |
1066 | } |
1067 | ||
db0f7958 AG |
1068 | /* C3.2.5 Test & branch (immediate) |
1069 | * 31 30 25 24 23 19 18 5 4 0 | |
1070 | * +----+-------------+----+-------+-------------+------+ | |
1071 | * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt | | |
1072 | * +----+-------------+----+-------+-------------+------+ | |
1073 | */ | |
ad7ee8a2 CF |
1074 | static void disas_test_b_imm(DisasContext *s, uint32_t insn) |
1075 | { | |
db0f7958 AG |
1076 | unsigned int bit_pos, op, rt; |
1077 | uint64_t addr; | |
1078 | int label_match; | |
1079 | TCGv_i64 tcg_cmp; | |
1080 | ||
1081 | bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5); | |
1082 | op = extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */ | |
1083 | addr = s->pc + sextract32(insn, 5, 14) * 4 - 4; | |
1084 | rt = extract32(insn, 0, 5); | |
1085 | ||
1086 | tcg_cmp = tcg_temp_new_i64(); | |
1087 | tcg_gen_andi_i64(tcg_cmp, cpu_reg(s, rt), (1ULL << bit_pos)); | |
1088 | label_match = gen_new_label(); | |
1089 | tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, | |
1090 | tcg_cmp, 0, label_match); | |
1091 | tcg_temp_free_i64(tcg_cmp); | |
1092 | gen_goto_tb(s, 0, s->pc); | |
1093 | gen_set_label(label_match); | |
1094 | gen_goto_tb(s, 1, addr); | |
ad7ee8a2 CF |
1095 | } |
1096 | ||
39fb730a AG |
1097 | /* C3.2.2 / C5.6.19 Conditional branch (immediate) |
1098 | * 31 25 24 23 5 4 3 0 | |
1099 | * +---------------+----+---------------------+----+------+ | |
1100 | * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond | | |
1101 | * +---------------+----+---------------------+----+------+ | |
1102 | */ | |
ad7ee8a2 CF |
1103 | static void disas_cond_b_imm(DisasContext *s, uint32_t insn) |
1104 | { | |
39fb730a AG |
1105 | unsigned int cond; |
1106 | uint64_t addr; | |
1107 | ||
1108 | if ((insn & (1 << 4)) || (insn & (1 << 24))) { | |
1109 | unallocated_encoding(s); | |
1110 | return; | |
1111 | } | |
1112 | addr = s->pc + sextract32(insn, 5, 19) * 4 - 4; | |
1113 | cond = extract32(insn, 0, 4); | |
1114 | ||
1115 | if (cond < 0x0e) { | |
1116 | /* genuinely conditional branches */ | |
1117 | int label_match = gen_new_label(); | |
1118 | arm_gen_test_cc(cond, label_match); | |
1119 | gen_goto_tb(s, 0, s->pc); | |
1120 | gen_set_label(label_match); | |
1121 | gen_goto_tb(s, 1, addr); | |
1122 | } else { | |
1123 | /* 0xe and 0xf are both "always" conditions */ | |
1124 | gen_goto_tb(s, 0, addr); | |
1125 | } | |
ad7ee8a2 CF |
1126 | } |
1127 | ||
87462e0f CF |
1128 | /* C5.6.68 HINT */ |
1129 | static void handle_hint(DisasContext *s, uint32_t insn, | |
1130 | unsigned int op1, unsigned int op2, unsigned int crm) | |
1131 | { | |
1132 | unsigned int selector = crm << 3 | op2; | |
1133 | ||
1134 | if (op1 != 3) { | |
1135 | unallocated_encoding(s); | |
1136 | return; | |
1137 | } | |
1138 | ||
1139 | switch (selector) { | |
1140 | case 0: /* NOP */ | |
1141 | return; | |
1ed69e82 PM |
1142 | case 3: /* WFI */ |
1143 | s->is_jmp = DISAS_WFI; | |
1144 | return; | |
87462e0f CF |
1145 | case 1: /* YIELD */ |
1146 | case 2: /* WFE */ | |
252ec405 RH |
1147 | s->is_jmp = DISAS_WFE; |
1148 | return; | |
87462e0f CF |
1149 | case 4: /* SEV */ |
1150 | case 5: /* SEVL */ | |
1151 | /* we treat all as NOP at least for now */ | |
1152 | return; | |
1153 | default: | |
1154 | /* default specified as NOP equivalent */ | |
1155 | return; | |
1156 | } | |
1157 | } | |
1158 | ||
fa2ef212 MM |
1159 | static void gen_clrex(DisasContext *s, uint32_t insn) |
1160 | { | |
1161 | tcg_gen_movi_i64(cpu_exclusive_addr, -1); | |
1162 | } | |
1163 | ||
87462e0f CF |
1164 | /* CLREX, DSB, DMB, ISB */ |
1165 | static void handle_sync(DisasContext *s, uint32_t insn, | |
1166 | unsigned int op1, unsigned int op2, unsigned int crm) | |
1167 | { | |
1168 | if (op1 != 3) { | |
1169 | unallocated_encoding(s); | |
1170 | return; | |
1171 | } | |
1172 | ||
1173 | switch (op2) { | |
1174 | case 2: /* CLREX */ | |
fa2ef212 | 1175 | gen_clrex(s, insn); |
87462e0f CF |
1176 | return; |
1177 | case 4: /* DSB */ | |
1178 | case 5: /* DMB */ | |
1179 | case 6: /* ISB */ | |
1180 | /* We don't emulate caches so barriers are no-ops */ | |
1181 | return; | |
1182 | default: | |
1183 | unallocated_encoding(s); | |
1184 | return; | |
1185 | } | |
1186 | } | |
1187 | ||
1188 | /* C5.6.130 MSR (immediate) - move immediate to processor state field */ | |
1189 | static void handle_msr_i(DisasContext *s, uint32_t insn, | |
1190 | unsigned int op1, unsigned int op2, unsigned int crm) | |
1191 | { | |
9cfa0b4e PM |
1192 | int op = op1 << 3 | op2; |
1193 | switch (op) { | |
1194 | case 0x05: /* SPSel */ | |
1195 | if (s->current_pl == 0) { | |
1196 | unallocated_encoding(s); | |
1197 | return; | |
1198 | } | |
1199 | /* fall through */ | |
1200 | case 0x1e: /* DAIFSet */ | |
1201 | case 0x1f: /* DAIFClear */ | |
1202 | { | |
1203 | TCGv_i32 tcg_imm = tcg_const_i32(crm); | |
1204 | TCGv_i32 tcg_op = tcg_const_i32(op); | |
1205 | gen_a64_set_pc_im(s->pc - 4); | |
1206 | gen_helper_msr_i_pstate(cpu_env, tcg_op, tcg_imm); | |
1207 | tcg_temp_free_i32(tcg_imm); | |
1208 | tcg_temp_free_i32(tcg_op); | |
1209 | s->is_jmp = DISAS_UPDATE; | |
1210 | break; | |
1211 | } | |
1212 | default: | |
1213 | unallocated_encoding(s); | |
1214 | return; | |
1215 | } | |
87462e0f CF |
1216 | } |
1217 | ||
b0d2b7d0 PM |
1218 | static void gen_get_nzcv(TCGv_i64 tcg_rt) |
1219 | { | |
1220 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
1221 | TCGv_i32 nzcv = tcg_temp_new_i32(); | |
1222 | ||
1223 | /* build bit 31, N */ | |
1224 | tcg_gen_andi_i32(nzcv, cpu_NF, (1 << 31)); | |
1225 | /* build bit 30, Z */ | |
1226 | tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_ZF, 0); | |
1227 | tcg_gen_deposit_i32(nzcv, nzcv, tmp, 30, 1); | |
1228 | /* build bit 29, C */ | |
1229 | tcg_gen_deposit_i32(nzcv, nzcv, cpu_CF, 29, 1); | |
1230 | /* build bit 28, V */ | |
1231 | tcg_gen_shri_i32(tmp, cpu_VF, 31); | |
1232 | tcg_gen_deposit_i32(nzcv, nzcv, tmp, 28, 1); | |
1233 | /* generate result */ | |
1234 | tcg_gen_extu_i32_i64(tcg_rt, nzcv); | |
1235 | ||
1236 | tcg_temp_free_i32(nzcv); | |
1237 | tcg_temp_free_i32(tmp); | |
1238 | } | |
1239 | ||
1240 | static void gen_set_nzcv(TCGv_i64 tcg_rt) | |
1241 | ||
1242 | { | |
1243 | TCGv_i32 nzcv = tcg_temp_new_i32(); | |
1244 | ||
1245 | /* take NZCV from R[t] */ | |
1246 | tcg_gen_trunc_i64_i32(nzcv, tcg_rt); | |
1247 | ||
1248 | /* bit 31, N */ | |
1249 | tcg_gen_andi_i32(cpu_NF, nzcv, (1 << 31)); | |
1250 | /* bit 30, Z */ | |
1251 | tcg_gen_andi_i32(cpu_ZF, nzcv, (1 << 30)); | |
1252 | tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_ZF, cpu_ZF, 0); | |
1253 | /* bit 29, C */ | |
1254 | tcg_gen_andi_i32(cpu_CF, nzcv, (1 << 29)); | |
1255 | tcg_gen_shri_i32(cpu_CF, cpu_CF, 29); | |
1256 | /* bit 28, V */ | |
1257 | tcg_gen_andi_i32(cpu_VF, nzcv, (1 << 28)); | |
1258 | tcg_gen_shli_i32(cpu_VF, cpu_VF, 3); | |
1259 | tcg_temp_free_i32(nzcv); | |
1260 | } | |
1261 | ||
fea50522 PM |
1262 | /* C5.6.129 MRS - move from system register |
1263 | * C5.6.131 MSR (register) - move to system register | |
1264 | * C5.6.204 SYS | |
1265 | * C5.6.205 SYSL | |
1266 | * These are all essentially the same insn in 'read' and 'write' | |
1267 | * versions, with varying op0 fields. | |
1268 | */ | |
1269 | static void handle_sys(DisasContext *s, uint32_t insn, bool isread, | |
1270 | unsigned int op0, unsigned int op1, unsigned int op2, | |
87462e0f CF |
1271 | unsigned int crn, unsigned int crm, unsigned int rt) |
1272 | { | |
fea50522 PM |
1273 | const ARMCPRegInfo *ri; |
1274 | TCGv_i64 tcg_rt; | |
87462e0f | 1275 | |
fea50522 PM |
1276 | ri = get_arm_cp_reginfo(s->cp_regs, |
1277 | ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, | |
1278 | crn, crm, op0, op1, op2)); | |
87462e0f | 1279 | |
fea50522 | 1280 | if (!ri) { |
626187d8 PM |
1281 | /* Unknown register; this might be a guest error or a QEMU |
1282 | * unimplemented feature. | |
1283 | */ | |
1284 | qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch64 " | |
1285 | "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n", | |
1286 | isread ? "read" : "write", op0, op1, crn, crm, op2); | |
fea50522 PM |
1287 | unallocated_encoding(s); |
1288 | return; | |
1289 | } | |
1290 | ||
1291 | /* Check access permissions */ | |
1292 | if (!cp_access_ok(s->current_pl, ri, isread)) { | |
1293 | unallocated_encoding(s); | |
1294 | return; | |
1295 | } | |
1296 | ||
f59df3f2 PM |
1297 | if (ri->accessfn) { |
1298 | /* Emit code to perform further access permissions checks at | |
1299 | * runtime; this may result in an exception. | |
1300 | */ | |
1301 | TCGv_ptr tmpptr; | |
8bcbf37c PM |
1302 | TCGv_i32 tcg_syn; |
1303 | uint32_t syndrome; | |
1304 | ||
f59df3f2 PM |
1305 | gen_a64_set_pc_im(s->pc - 4); |
1306 | tmpptr = tcg_const_ptr(ri); | |
8bcbf37c PM |
1307 | syndrome = syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isread); |
1308 | tcg_syn = tcg_const_i32(syndrome); | |
1309 | gen_helper_access_check_cp_reg(cpu_env, tmpptr, tcg_syn); | |
f59df3f2 | 1310 | tcg_temp_free_ptr(tmpptr); |
8bcbf37c | 1311 | tcg_temp_free_i32(tcg_syn); |
f59df3f2 PM |
1312 | } |
1313 | ||
fea50522 PM |
1314 | /* Handle special cases first */ |
1315 | switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) { | |
1316 | case ARM_CP_NOP: | |
1317 | return; | |
b0d2b7d0 PM |
1318 | case ARM_CP_NZCV: |
1319 | tcg_rt = cpu_reg(s, rt); | |
1320 | if (isread) { | |
1321 | gen_get_nzcv(tcg_rt); | |
1322 | } else { | |
1323 | gen_set_nzcv(tcg_rt); | |
1324 | } | |
1325 | return; | |
0eef9d98 PM |
1326 | case ARM_CP_CURRENTEL: |
1327 | /* Reads as current EL value from pstate, which is | |
1328 | * guaranteed to be constant by the tb flags. | |
1329 | */ | |
1330 | tcg_rt = cpu_reg(s, rt); | |
1331 | tcg_gen_movi_i64(tcg_rt, s->current_pl << 2); | |
1332 | return; | |
aca3f40b PM |
1333 | case ARM_CP_DC_ZVA: |
1334 | /* Writes clear the aligned block of memory which rt points into. */ | |
1335 | tcg_rt = cpu_reg(s, rt); | |
1336 | gen_helper_dc_zva(cpu_env, tcg_rt); | |
1337 | return; | |
fea50522 PM |
1338 | default: |
1339 | break; | |
1340 | } | |
1341 | ||
1342 | if (use_icount && (ri->type & ARM_CP_IO)) { | |
1343 | gen_io_start(); | |
1344 | } | |
1345 | ||
1346 | tcg_rt = cpu_reg(s, rt); | |
1347 | ||
1348 | if (isread) { | |
1349 | if (ri->type & ARM_CP_CONST) { | |
1350 | tcg_gen_movi_i64(tcg_rt, ri->resetvalue); | |
1351 | } else if (ri->readfn) { | |
1352 | TCGv_ptr tmpptr; | |
fea50522 PM |
1353 | tmpptr = tcg_const_ptr(ri); |
1354 | gen_helper_get_cp_reg64(tcg_rt, cpu_env, tmpptr); | |
1355 | tcg_temp_free_ptr(tmpptr); | |
1356 | } else { | |
1357 | tcg_gen_ld_i64(tcg_rt, cpu_env, ri->fieldoffset); | |
1358 | } | |
1359 | } else { | |
1360 | if (ri->type & ARM_CP_CONST) { | |
1361 | /* If not forbidden by access permissions, treat as WI */ | |
1362 | return; | |
1363 | } else if (ri->writefn) { | |
1364 | TCGv_ptr tmpptr; | |
fea50522 PM |
1365 | tmpptr = tcg_const_ptr(ri); |
1366 | gen_helper_set_cp_reg64(cpu_env, tmpptr, tcg_rt); | |
1367 | tcg_temp_free_ptr(tmpptr); | |
1368 | } else { | |
1369 | tcg_gen_st_i64(tcg_rt, cpu_env, ri->fieldoffset); | |
1370 | } | |
1371 | } | |
1372 | ||
1373 | if (use_icount && (ri->type & ARM_CP_IO)) { | |
1374 | /* I/O operations must end the TB here (whether read or write) */ | |
1375 | gen_io_end(); | |
1376 | s->is_jmp = DISAS_UPDATE; | |
1377 | } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { | |
1378 | /* We default to ending the TB on a coprocessor register write, | |
1379 | * but allow this to be suppressed by the register definition | |
1380 | * (usually only necessary to work around guest bugs). | |
1381 | */ | |
1382 | s->is_jmp = DISAS_UPDATE; | |
1383 | } | |
ad7ee8a2 CF |
1384 | } |
1385 | ||
87462e0f CF |
1386 | /* C3.2.4 System |
1387 | * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0 | |
1388 | * +---------------------+---+-----+-----+-------+-------+-----+------+ | |
1389 | * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt | | |
1390 | * +---------------------+---+-----+-----+-------+-------+-----+------+ | |
1391 | */ | |
1392 | static void disas_system(DisasContext *s, uint32_t insn) | |
1393 | { | |
1394 | unsigned int l, op0, op1, crn, crm, op2, rt; | |
1395 | l = extract32(insn, 21, 1); | |
1396 | op0 = extract32(insn, 19, 2); | |
1397 | op1 = extract32(insn, 16, 3); | |
1398 | crn = extract32(insn, 12, 4); | |
1399 | crm = extract32(insn, 8, 4); | |
1400 | op2 = extract32(insn, 5, 3); | |
1401 | rt = extract32(insn, 0, 5); | |
1402 | ||
1403 | if (op0 == 0) { | |
1404 | if (l || rt != 31) { | |
1405 | unallocated_encoding(s); | |
1406 | return; | |
1407 | } | |
1408 | switch (crn) { | |
1409 | case 2: /* C5.6.68 HINT */ | |
1410 | handle_hint(s, insn, op1, op2, crm); | |
1411 | break; | |
1412 | case 3: /* CLREX, DSB, DMB, ISB */ | |
1413 | handle_sync(s, insn, op1, op2, crm); | |
1414 | break; | |
1415 | case 4: /* C5.6.130 MSR (immediate) */ | |
1416 | handle_msr_i(s, insn, op1, op2, crm); | |
1417 | break; | |
1418 | default: | |
1419 | unallocated_encoding(s); | |
1420 | break; | |
1421 | } | |
1422 | return; | |
1423 | } | |
fea50522 | 1424 | handle_sys(s, insn, l, op0, op1, op2, crn, crm, rt); |
87462e0f CF |
1425 | } |
1426 | ||
9618e809 AG |
1427 | /* C3.2.3 Exception generation |
1428 | * | |
1429 | * 31 24 23 21 20 5 4 2 1 0 | |
1430 | * +-----------------+-----+------------------------+-----+----+ | |
1431 | * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL | | |
1432 | * +-----------------------+------------------------+----------+ | |
1433 | */ | |
ad7ee8a2 CF |
1434 | static void disas_exc(DisasContext *s, uint32_t insn) |
1435 | { | |
9618e809 AG |
1436 | int opc = extract32(insn, 21, 3); |
1437 | int op2_ll = extract32(insn, 0, 5); | |
d4a2dc67 | 1438 | int imm16 = extract32(insn, 5, 16); |
9618e809 AG |
1439 | |
1440 | switch (opc) { | |
1441 | case 0: | |
1442 | /* SVC, HVC, SMC; since we don't support the Virtualization | |
1443 | * or TrustZone extensions these all UNDEF except SVC. | |
1444 | */ | |
1445 | if (op2_ll != 1) { | |
1446 | unallocated_encoding(s); | |
1447 | break; | |
1448 | } | |
d4a2dc67 | 1449 | gen_exception_insn(s, 0, EXCP_SWI, syn_aa64_svc(imm16)); |
9618e809 AG |
1450 | break; |
1451 | case 1: | |
1452 | if (op2_ll != 0) { | |
1453 | unallocated_encoding(s); | |
1454 | break; | |
1455 | } | |
1456 | /* BRK */ | |
d4a2dc67 | 1457 | gen_exception_insn(s, 0, EXCP_BKPT, syn_aa64_bkpt(imm16)); |
9618e809 AG |
1458 | break; |
1459 | case 2: | |
1460 | if (op2_ll != 0) { | |
1461 | unallocated_encoding(s); | |
1462 | break; | |
1463 | } | |
1464 | /* HLT */ | |
1465 | unsupported_encoding(s, insn); | |
1466 | break; | |
1467 | case 5: | |
1468 | if (op2_ll < 1 || op2_ll > 3) { | |
1469 | unallocated_encoding(s); | |
1470 | break; | |
1471 | } | |
1472 | /* DCPS1, DCPS2, DCPS3 */ | |
1473 | unsupported_encoding(s, insn); | |
1474 | break; | |
1475 | default: | |
1476 | unallocated_encoding(s); | |
1477 | break; | |
1478 | } | |
ad7ee8a2 CF |
1479 | } |
1480 | ||
b001c8c3 AG |
1481 | /* C3.2.7 Unconditional branch (register) |
1482 | * 31 25 24 21 20 16 15 10 9 5 4 0 | |
1483 | * +---------------+-------+-------+-------+------+-------+ | |
1484 | * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 | | |
1485 | * +---------------+-------+-------+-------+------+-------+ | |
1486 | */ | |
ad7ee8a2 CF |
1487 | static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) |
1488 | { | |
b001c8c3 AG |
1489 | unsigned int opc, op2, op3, rn, op4; |
1490 | ||
1491 | opc = extract32(insn, 21, 4); | |
1492 | op2 = extract32(insn, 16, 5); | |
1493 | op3 = extract32(insn, 10, 6); | |
1494 | rn = extract32(insn, 5, 5); | |
1495 | op4 = extract32(insn, 0, 5); | |
1496 | ||
1497 | if (op4 != 0x0 || op3 != 0x0 || op2 != 0x1f) { | |
1498 | unallocated_encoding(s); | |
1499 | return; | |
1500 | } | |
1501 | ||
1502 | switch (opc) { | |
1503 | case 0: /* BR */ | |
1504 | case 2: /* RET */ | |
1b505f93 | 1505 | tcg_gen_mov_i64(cpu_pc, cpu_reg(s, rn)); |
b001c8c3 AG |
1506 | break; |
1507 | case 1: /* BLR */ | |
1b505f93 | 1508 | tcg_gen_mov_i64(cpu_pc, cpu_reg(s, rn)); |
b001c8c3 AG |
1509 | tcg_gen_movi_i64(cpu_reg(s, 30), s->pc); |
1510 | break; | |
1511 | case 4: /* ERET */ | |
14c521d4 EI |
1512 | if (s->current_pl == 0) { |
1513 | unallocated_encoding(s); | |
1514 | return; | |
1515 | } | |
52e60cdd RH |
1516 | gen_helper_exception_return(cpu_env); |
1517 | s->is_jmp = DISAS_JUMP; | |
1518 | return; | |
b001c8c3 AG |
1519 | case 5: /* DRPS */ |
1520 | if (rn != 0x1f) { | |
1521 | unallocated_encoding(s); | |
1522 | } else { | |
1523 | unsupported_encoding(s, insn); | |
1524 | } | |
1525 | return; | |
1526 | default: | |
1527 | unallocated_encoding(s); | |
1528 | return; | |
1529 | } | |
1530 | ||
b001c8c3 | 1531 | s->is_jmp = DISAS_JUMP; |
ad7ee8a2 CF |
1532 | } |
1533 | ||
1534 | /* C3.2 Branches, exception generating and system instructions */ | |
1535 | static void disas_b_exc_sys(DisasContext *s, uint32_t insn) | |
1536 | { | |
1537 | switch (extract32(insn, 25, 7)) { | |
1538 | case 0x0a: case 0x0b: | |
1539 | case 0x4a: case 0x4b: /* Unconditional branch (immediate) */ | |
1540 | disas_uncond_b_imm(s, insn); | |
1541 | break; | |
1542 | case 0x1a: case 0x5a: /* Compare & branch (immediate) */ | |
1543 | disas_comp_b_imm(s, insn); | |
1544 | break; | |
1545 | case 0x1b: case 0x5b: /* Test & branch (immediate) */ | |
1546 | disas_test_b_imm(s, insn); | |
1547 | break; | |
1548 | case 0x2a: /* Conditional branch (immediate) */ | |
1549 | disas_cond_b_imm(s, insn); | |
1550 | break; | |
1551 | case 0x6a: /* Exception generation / System */ | |
1552 | if (insn & (1 << 24)) { | |
1553 | disas_system(s, insn); | |
1554 | } else { | |
1555 | disas_exc(s, insn); | |
1556 | } | |
1557 | break; | |
1558 | case 0x6b: /* Unconditional branch (register) */ | |
1559 | disas_uncond_b_reg(s, insn); | |
1560 | break; | |
1561 | default: | |
1562 | unallocated_encoding(s); | |
1563 | break; | |
1564 | } | |
1565 | } | |
1566 | ||
fa2ef212 MM |
1567 | /* |
1568 | * Load/Store exclusive instructions are implemented by remembering | |
1569 | * the value/address loaded, and seeing if these are the same | |
1570 | * when the store is performed. This is not actually the architecturally | |
1571 | * mandated semantics, but it works for typical guest code sequences | |
1572 | * and avoids having to monitor regular stores. | |
1573 | * | |
1574 | * In system emulation mode only one CPU will be running at once, so | |
1575 | * this sequence is effectively atomic. In user emulation mode we | |
1576 | * throw an exception and handle the atomic operation elsewhere. | |
1577 | */ | |
1578 | static void gen_load_exclusive(DisasContext *s, int rt, int rt2, | |
1579 | TCGv_i64 addr, int size, bool is_pair) | |
1580 | { | |
1581 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
1582 | TCGMemOp memop = MO_TE + size; | |
1583 | ||
1584 | g_assert(size <= 3); | |
1585 | tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s), memop); | |
1586 | ||
1587 | if (is_pair) { | |
1588 | TCGv_i64 addr2 = tcg_temp_new_i64(); | |
1589 | TCGv_i64 hitmp = tcg_temp_new_i64(); | |
1590 | ||
1591 | g_assert(size >= 2); | |
1592 | tcg_gen_addi_i64(addr2, addr, 1 << size); | |
1593 | tcg_gen_qemu_ld_i64(hitmp, addr2, get_mem_index(s), memop); | |
1594 | tcg_temp_free_i64(addr2); | |
1595 | tcg_gen_mov_i64(cpu_exclusive_high, hitmp); | |
1596 | tcg_gen_mov_i64(cpu_reg(s, rt2), hitmp); | |
1597 | tcg_temp_free_i64(hitmp); | |
1598 | } | |
1599 | ||
1600 | tcg_gen_mov_i64(cpu_exclusive_val, tmp); | |
1601 | tcg_gen_mov_i64(cpu_reg(s, rt), tmp); | |
1602 | ||
1603 | tcg_temp_free_i64(tmp); | |
1604 | tcg_gen_mov_i64(cpu_exclusive_addr, addr); | |
1605 | } | |
1606 | ||
1607 | #ifdef CONFIG_USER_ONLY | |
1608 | static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, | |
1609 | TCGv_i64 addr, int size, int is_pair) | |
1610 | { | |
1611 | tcg_gen_mov_i64(cpu_exclusive_test, addr); | |
1612 | tcg_gen_movi_i32(cpu_exclusive_info, | |
1613 | size | is_pair << 2 | (rd << 4) | (rt << 9) | (rt2 << 14)); | |
d4a2dc67 | 1614 | gen_exception_internal_insn(s, 4, EXCP_STREX); |
fa2ef212 MM |
1615 | } |
1616 | #else | |
1617 | static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, | |
d324b36a | 1618 | TCGv_i64 inaddr, int size, int is_pair) |
fa2ef212 | 1619 | { |
d324b36a PM |
1620 | /* if (env->exclusive_addr == addr && env->exclusive_val == [addr] |
1621 | * && (!is_pair || env->exclusive_high == [addr + datasize])) { | |
1622 | * [addr] = {Rt}; | |
1623 | * if (is_pair) { | |
1624 | * [addr + datasize] = {Rt2}; | |
1625 | * } | |
1626 | * {Rd} = 0; | |
1627 | * } else { | |
1628 | * {Rd} = 1; | |
1629 | * } | |
1630 | * env->exclusive_addr = -1; | |
1631 | */ | |
1632 | int fail_label = gen_new_label(); | |
1633 | int done_label = gen_new_label(); | |
1634 | TCGv_i64 addr = tcg_temp_local_new_i64(); | |
1635 | TCGv_i64 tmp; | |
1636 | ||
1637 | /* Copy input into a local temp so it is not trashed when the | |
1638 | * basic block ends at the branch insn. | |
1639 | */ | |
1640 | tcg_gen_mov_i64(addr, inaddr); | |
1641 | tcg_gen_brcond_i64(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label); | |
1642 | ||
1643 | tmp = tcg_temp_new_i64(); | |
1644 | tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s), MO_TE + size); | |
1645 | tcg_gen_brcond_i64(TCG_COND_NE, tmp, cpu_exclusive_val, fail_label); | |
1646 | tcg_temp_free_i64(tmp); | |
1647 | ||
1648 | if (is_pair) { | |
1649 | TCGv_i64 addrhi = tcg_temp_new_i64(); | |
1650 | TCGv_i64 tmphi = tcg_temp_new_i64(); | |
1651 | ||
1652 | tcg_gen_addi_i64(addrhi, addr, 1 << size); | |
1653 | tcg_gen_qemu_ld_i64(tmphi, addrhi, get_mem_index(s), MO_TE + size); | |
1654 | tcg_gen_brcond_i64(TCG_COND_NE, tmphi, cpu_exclusive_high, fail_label); | |
1655 | ||
1656 | tcg_temp_free_i64(tmphi); | |
1657 | tcg_temp_free_i64(addrhi); | |
1658 | } | |
1659 | ||
1660 | /* We seem to still have the exclusive monitor, so do the store */ | |
1661 | tcg_gen_qemu_st_i64(cpu_reg(s, rt), addr, get_mem_index(s), MO_TE + size); | |
1662 | if (is_pair) { | |
1663 | TCGv_i64 addrhi = tcg_temp_new_i64(); | |
1664 | ||
1665 | tcg_gen_addi_i64(addrhi, addr, 1 << size); | |
1666 | tcg_gen_qemu_st_i64(cpu_reg(s, rt2), addrhi, | |
1667 | get_mem_index(s), MO_TE + size); | |
1668 | tcg_temp_free_i64(addrhi); | |
1669 | } | |
1670 | ||
1671 | tcg_temp_free_i64(addr); | |
1672 | ||
1673 | tcg_gen_movi_i64(cpu_reg(s, rd), 0); | |
1674 | tcg_gen_br(done_label); | |
1675 | gen_set_label(fail_label); | |
1676 | tcg_gen_movi_i64(cpu_reg(s, rd), 1); | |
1677 | gen_set_label(done_label); | |
1678 | tcg_gen_movi_i64(cpu_exclusive_addr, -1); | |
1679 | ||
fa2ef212 MM |
1680 | } |
1681 | #endif | |
1682 | ||
1683 | /* C3.3.6 Load/store exclusive | |
1684 | * | |
1685 | * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0 | |
1686 | * +-----+-------------+----+---+----+------+----+-------+------+------+ | |
1687 | * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt | | |
1688 | * +-----+-------------+----+---+----+------+----+-------+------+------+ | |
1689 | * | |
1690 | * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit | |
1691 | * L: 0 -> store, 1 -> load | |
1692 | * o2: 0 -> exclusive, 1 -> not | |
1693 | * o1: 0 -> single register, 1 -> register pair | |
1694 | * o0: 1 -> load-acquire/store-release, 0 -> not | |
1695 | * | |
1696 | * o0 == 0 AND o2 == 1 is un-allocated | |
1697 | * o1 == 1 is un-allocated except for 32 and 64 bit sizes | |
1698 | */ | |
ad7ee8a2 CF |
1699 | static void disas_ldst_excl(DisasContext *s, uint32_t insn) |
1700 | { | |
fa2ef212 MM |
1701 | int rt = extract32(insn, 0, 5); |
1702 | int rn = extract32(insn, 5, 5); | |
1703 | int rt2 = extract32(insn, 10, 5); | |
1704 | int is_lasr = extract32(insn, 15, 1); | |
1705 | int rs = extract32(insn, 16, 5); | |
1706 | int is_pair = extract32(insn, 21, 1); | |
1707 | int is_store = !extract32(insn, 22, 1); | |
1708 | int is_excl = !extract32(insn, 23, 1); | |
1709 | int size = extract32(insn, 30, 2); | |
1710 | TCGv_i64 tcg_addr; | |
1711 | ||
1712 | if ((!is_excl && !is_lasr) || | |
1713 | (is_pair && size < 2)) { | |
1714 | unallocated_encoding(s); | |
1715 | return; | |
1716 | } | |
1717 | ||
1718 | if (rn == 31) { | |
1719 | gen_check_sp_alignment(s); | |
1720 | } | |
1721 | tcg_addr = read_cpu_reg_sp(s, rn, 1); | |
1722 | ||
1723 | /* Note that since TCG is single threaded load-acquire/store-release | |
1724 | * semantics require no extra if (is_lasr) { ... } handling. | |
1725 | */ | |
1726 | ||
1727 | if (is_excl) { | |
1728 | if (!is_store) { | |
1729 | gen_load_exclusive(s, rt, rt2, tcg_addr, size, is_pair); | |
1730 | } else { | |
1731 | gen_store_exclusive(s, rs, rt, rt2, tcg_addr, size, is_pair); | |
1732 | } | |
1733 | } else { | |
1734 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | |
1735 | if (is_store) { | |
1736 | do_gpr_st(s, tcg_rt, tcg_addr, size); | |
1737 | } else { | |
1738 | do_gpr_ld(s, tcg_rt, tcg_addr, size, false, false); | |
1739 | } | |
1740 | if (is_pair) { | |
1741 | TCGv_i64 tcg_rt2 = cpu_reg(s, rt); | |
1742 | tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size); | |
1743 | if (is_store) { | |
1744 | do_gpr_st(s, tcg_rt2, tcg_addr, size); | |
1745 | } else { | |
1746 | do_gpr_ld(s, tcg_rt2, tcg_addr, size, false, false); | |
1747 | } | |
1748 | } | |
1749 | } | |
ad7ee8a2 CF |
1750 | } |
1751 | ||
32b64e86 AG |
1752 | /* |
1753 | * C3.3.5 Load register (literal) | |
1754 | * | |
1755 | * 31 30 29 27 26 25 24 23 5 4 0 | |
1756 | * +-----+-------+---+-----+-------------------+-------+ | |
1757 | * | opc | 0 1 1 | V | 0 0 | imm19 | Rt | | |
1758 | * +-----+-------+---+-----+-------------------+-------+ | |
1759 | * | |
1760 | * V: 1 -> vector (simd/fp) | |
1761 | * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit, | |
1762 | * 10-> 32 bit signed, 11 -> prefetch | |
1763 | * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated) | |
1764 | */ | |
ad7ee8a2 CF |
1765 | static void disas_ld_lit(DisasContext *s, uint32_t insn) |
1766 | { | |
32b64e86 AG |
1767 | int rt = extract32(insn, 0, 5); |
1768 | int64_t imm = sextract32(insn, 5, 19) << 2; | |
1769 | bool is_vector = extract32(insn, 26, 1); | |
1770 | int opc = extract32(insn, 30, 2); | |
1771 | bool is_signed = false; | |
1772 | int size = 2; | |
1773 | TCGv_i64 tcg_rt, tcg_addr; | |
1774 | ||
1775 | if (is_vector) { | |
1776 | if (opc == 3) { | |
1777 | unallocated_encoding(s); | |
1778 | return; | |
1779 | } | |
1780 | size = 2 + opc; | |
8c6afa6a PM |
1781 | if (!fp_access_check(s)) { |
1782 | return; | |
1783 | } | |
32b64e86 AG |
1784 | } else { |
1785 | if (opc == 3) { | |
1786 | /* PRFM (literal) : prefetch */ | |
1787 | return; | |
1788 | } | |
1789 | size = 2 + extract32(opc, 0, 1); | |
1790 | is_signed = extract32(opc, 1, 1); | |
1791 | } | |
1792 | ||
1793 | tcg_rt = cpu_reg(s, rt); | |
1794 | ||
1795 | tcg_addr = tcg_const_i64((s->pc - 4) + imm); | |
1796 | if (is_vector) { | |
1797 | do_fp_ld(s, rt, tcg_addr, size); | |
1798 | } else { | |
1799 | do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false); | |
1800 | } | |
1801 | tcg_temp_free_i64(tcg_addr); | |
ad7ee8a2 CF |
1802 | } |
1803 | ||
4a08d475 PM |
1804 | /* |
1805 | * C5.6.80 LDNP (Load Pair - non-temporal hint) | |
1806 | * C5.6.81 LDP (Load Pair - non vector) | |
1807 | * C5.6.82 LDPSW (Load Pair Signed Word - non vector) | |
1808 | * C5.6.176 STNP (Store Pair - non-temporal hint) | |
1809 | * C5.6.177 STP (Store Pair - non vector) | |
1810 | * C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint) | |
1811 | * C6.3.165 LDP (Load Pair of SIMD&FP) | |
1812 | * C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint) | |
1813 | * C6.3.284 STP (Store Pair of SIMD&FP) | |
1814 | * | |
1815 | * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0 | |
1816 | * +-----+-------+---+---+-------+---+-----------------------------+ | |
1817 | * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt | | |
1818 | * +-----+-------+---+---+-------+---+-------+-------+------+------+ | |
1819 | * | |
1820 | * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit | |
1821 | * LDPSW 01 | |
1822 | * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit | |
1823 | * V: 0 -> GPR, 1 -> Vector | |
1824 | * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index, | |
1825 | * 10 -> signed offset, 11 -> pre-index | |
1826 | * L: 0 -> Store 1 -> Load | |
1827 | * | |
1828 | * Rt, Rt2 = GPR or SIMD registers to be stored | |
1829 | * Rn = general purpose register containing address | |
1830 | * imm7 = signed offset (multiple of 4 or 8 depending on size) | |
1831 | */ | |
ad7ee8a2 CF |
1832 | static void disas_ldst_pair(DisasContext *s, uint32_t insn) |
1833 | { | |
4a08d475 PM |
1834 | int rt = extract32(insn, 0, 5); |
1835 | int rn = extract32(insn, 5, 5); | |
1836 | int rt2 = extract32(insn, 10, 5); | |
1837 | int64_t offset = sextract32(insn, 15, 7); | |
1838 | int index = extract32(insn, 23, 2); | |
1839 | bool is_vector = extract32(insn, 26, 1); | |
1840 | bool is_load = extract32(insn, 22, 1); | |
1841 | int opc = extract32(insn, 30, 2); | |
1842 | ||
1843 | bool is_signed = false; | |
1844 | bool postindex = false; | |
1845 | bool wback = false; | |
1846 | ||
1847 | TCGv_i64 tcg_addr; /* calculated address */ | |
1848 | int size; | |
1849 | ||
1850 | if (opc == 3) { | |
1851 | unallocated_encoding(s); | |
1852 | return; | |
1853 | } | |
1854 | ||
1855 | if (is_vector) { | |
1856 | size = 2 + opc; | |
1857 | } else { | |
1858 | size = 2 + extract32(opc, 1, 1); | |
1859 | is_signed = extract32(opc, 0, 1); | |
1860 | if (!is_load && is_signed) { | |
1861 | unallocated_encoding(s); | |
1862 | return; | |
1863 | } | |
1864 | } | |
1865 | ||
1866 | switch (index) { | |
1867 | case 1: /* post-index */ | |
1868 | postindex = true; | |
1869 | wback = true; | |
1870 | break; | |
1871 | case 0: | |
1872 | /* signed offset with "non-temporal" hint. Since we don't emulate | |
1873 | * caches we don't care about hints to the cache system about | |
1874 | * data access patterns, and handle this identically to plain | |
1875 | * signed offset. | |
1876 | */ | |
1877 | if (is_signed) { | |
1878 | /* There is no non-temporal-hint version of LDPSW */ | |
1879 | unallocated_encoding(s); | |
1880 | return; | |
1881 | } | |
1882 | postindex = false; | |
1883 | break; | |
1884 | case 2: /* signed offset, rn not updated */ | |
1885 | postindex = false; | |
1886 | break; | |
1887 | case 3: /* pre-index */ | |
1888 | postindex = false; | |
1889 | wback = true; | |
1890 | break; | |
1891 | } | |
1892 | ||
8c6afa6a PM |
1893 | if (is_vector && !fp_access_check(s)) { |
1894 | return; | |
1895 | } | |
1896 | ||
4a08d475 PM |
1897 | offset <<= size; |
1898 | ||
1899 | if (rn == 31) { | |
1900 | gen_check_sp_alignment(s); | |
1901 | } | |
1902 | ||
1903 | tcg_addr = read_cpu_reg_sp(s, rn, 1); | |
1904 | ||
1905 | if (!postindex) { | |
1906 | tcg_gen_addi_i64(tcg_addr, tcg_addr, offset); | |
1907 | } | |
1908 | ||
1909 | if (is_vector) { | |
1910 | if (is_load) { | |
1911 | do_fp_ld(s, rt, tcg_addr, size); | |
1912 | } else { | |
1913 | do_fp_st(s, rt, tcg_addr, size); | |
1914 | } | |
1915 | } else { | |
1916 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | |
1917 | if (is_load) { | |
1918 | do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false); | |
1919 | } else { | |
1920 | do_gpr_st(s, tcg_rt, tcg_addr, size); | |
1921 | } | |
1922 | } | |
1923 | tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size); | |
1924 | if (is_vector) { | |
1925 | if (is_load) { | |
1926 | do_fp_ld(s, rt2, tcg_addr, size); | |
1927 | } else { | |
1928 | do_fp_st(s, rt2, tcg_addr, size); | |
1929 | } | |
1930 | } else { | |
1931 | TCGv_i64 tcg_rt2 = cpu_reg(s, rt2); | |
1932 | if (is_load) { | |
1933 | do_gpr_ld(s, tcg_rt2, tcg_addr, size, is_signed, false); | |
1934 | } else { | |
1935 | do_gpr_st(s, tcg_rt2, tcg_addr, size); | |
1936 | } | |
1937 | } | |
1938 | ||
1939 | if (wback) { | |
1940 | if (postindex) { | |
1941 | tcg_gen_addi_i64(tcg_addr, tcg_addr, offset - (1 << size)); | |
1942 | } else { | |
1943 | tcg_gen_subi_i64(tcg_addr, tcg_addr, 1 << size); | |
1944 | } | |
1945 | tcg_gen_mov_i64(cpu_reg_sp(s, rn), tcg_addr); | |
1946 | } | |
ad7ee8a2 CF |
1947 | } |
1948 | ||
a5e94a9d AB |
1949 | /* |
1950 | * C3.3.8 Load/store (immediate post-indexed) | |
1951 | * C3.3.9 Load/store (immediate pre-indexed) | |
1952 | * C3.3.12 Load/store (unscaled immediate) | |
1953 | * | |
1954 | * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0 | |
1955 | * +----+-------+---+-----+-----+---+--------+-----+------+------+ | |
1956 | * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt | | |
1957 | * +----+-------+---+-----+-----+---+--------+-----+------+------+ | |
1958 | * | |
1959 | * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback) | |
60510aed | 1960 | 10 -> unprivileged |
a5e94a9d AB |
1961 | * V = 0 -> non-vector |
1962 | * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit | |
1963 | * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 | |
1964 | */ | |
1965 | static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn) | |
1966 | { | |
1967 | int rt = extract32(insn, 0, 5); | |
1968 | int rn = extract32(insn, 5, 5); | |
1969 | int imm9 = sextract32(insn, 12, 9); | |
1970 | int opc = extract32(insn, 22, 2); | |
1971 | int size = extract32(insn, 30, 2); | |
1972 | int idx = extract32(insn, 10, 2); | |
1973 | bool is_signed = false; | |
1974 | bool is_store = false; | |
1975 | bool is_extended = false; | |
60510aed | 1976 | bool is_unpriv = (idx == 2); |
a5e94a9d AB |
1977 | bool is_vector = extract32(insn, 26, 1); |
1978 | bool post_index; | |
1979 | bool writeback; | |
1980 | ||
1981 | TCGv_i64 tcg_addr; | |
1982 | ||
1983 | if (is_vector) { | |
1984 | size |= (opc & 2) << 1; | |
60510aed | 1985 | if (size > 4 || is_unpriv) { |
a5e94a9d AB |
1986 | unallocated_encoding(s); |
1987 | return; | |
1988 | } | |
1989 | is_store = ((opc & 1) == 0); | |
8c6afa6a PM |
1990 | if (!fp_access_check(s)) { |
1991 | return; | |
1992 | } | |
a5e94a9d AB |
1993 | } else { |
1994 | if (size == 3 && opc == 2) { | |
1995 | /* PRFM - prefetch */ | |
60510aed PM |
1996 | if (is_unpriv) { |
1997 | unallocated_encoding(s); | |
1998 | return; | |
1999 | } | |
a5e94a9d AB |
2000 | return; |
2001 | } | |
2002 | if (opc == 3 && size > 1) { | |
2003 | unallocated_encoding(s); | |
2004 | return; | |
2005 | } | |
2006 | is_store = (opc == 0); | |
2007 | is_signed = opc & (1<<1); | |
2008 | is_extended = (size < 3) && (opc & 1); | |
2009 | } | |
2010 | ||
2011 | switch (idx) { | |
2012 | case 0: | |
60510aed | 2013 | case 2: |
a5e94a9d AB |
2014 | post_index = false; |
2015 | writeback = false; | |
2016 | break; | |
2017 | case 1: | |
2018 | post_index = true; | |
2019 | writeback = true; | |
2020 | break; | |
2021 | case 3: | |
2022 | post_index = false; | |
2023 | writeback = true; | |
2024 | break; | |
a5e94a9d AB |
2025 | } |
2026 | ||
2027 | if (rn == 31) { | |
2028 | gen_check_sp_alignment(s); | |
2029 | } | |
2030 | tcg_addr = read_cpu_reg_sp(s, rn, 1); | |
2031 | ||
2032 | if (!post_index) { | |
2033 | tcg_gen_addi_i64(tcg_addr, tcg_addr, imm9); | |
2034 | } | |
2035 | ||
2036 | if (is_vector) { | |
2037 | if (is_store) { | |
2038 | do_fp_st(s, rt, tcg_addr, size); | |
2039 | } else { | |
2040 | do_fp_ld(s, rt, tcg_addr, size); | |
2041 | } | |
2042 | } else { | |
2043 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | |
60510aed PM |
2044 | int memidx = is_unpriv ? 1 : get_mem_index(s); |
2045 | ||
a5e94a9d | 2046 | if (is_store) { |
60510aed | 2047 | do_gpr_st_memidx(s, tcg_rt, tcg_addr, size, memidx); |
a5e94a9d | 2048 | } else { |
60510aed PM |
2049 | do_gpr_ld_memidx(s, tcg_rt, tcg_addr, size, |
2050 | is_signed, is_extended, memidx); | |
a5e94a9d AB |
2051 | } |
2052 | } | |
2053 | ||
2054 | if (writeback) { | |
2055 | TCGv_i64 tcg_rn = cpu_reg_sp(s, rn); | |
2056 | if (post_index) { | |
2057 | tcg_gen_addi_i64(tcg_addr, tcg_addr, imm9); | |
2058 | } | |
2059 | tcg_gen_mov_i64(tcg_rn, tcg_addr); | |
2060 | } | |
2061 | } | |
2062 | ||
229b7a05 AB |
2063 | /* |
2064 | * C3.3.10 Load/store (register offset) | |
2065 | * | |
2066 | * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0 | |
2067 | * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+ | |
2068 | * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt | | |
2069 | * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+ | |
2070 | * | |
2071 | * For non-vector: | |
2072 | * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit | |
2073 | * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 | |
2074 | * For vector: | |
2075 | * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated | |
2076 | * opc<0>: 0 -> store, 1 -> load | |
2077 | * V: 1 -> vector/simd | |
2078 | * opt: extend encoding (see DecodeRegExtend) | |
2079 | * S: if S=1 then scale (essentially index by sizeof(size)) | |
2080 | * Rt: register to transfer into/out of | |
2081 | * Rn: address register or SP for base | |
2082 | * Rm: offset register or ZR for offset | |
2083 | */ | |
2084 | static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn) | |
2085 | { | |
2086 | int rt = extract32(insn, 0, 5); | |
2087 | int rn = extract32(insn, 5, 5); | |
2088 | int shift = extract32(insn, 12, 1); | |
2089 | int rm = extract32(insn, 16, 5); | |
2090 | int opc = extract32(insn, 22, 2); | |
2091 | int opt = extract32(insn, 13, 3); | |
2092 | int size = extract32(insn, 30, 2); | |
2093 | bool is_signed = false; | |
2094 | bool is_store = false; | |
2095 | bool is_extended = false; | |
2096 | bool is_vector = extract32(insn, 26, 1); | |
2097 | ||
2098 | TCGv_i64 tcg_rm; | |
2099 | TCGv_i64 tcg_addr; | |
2100 | ||
2101 | if (extract32(opt, 1, 1) == 0) { | |
2102 | unallocated_encoding(s); | |
2103 | return; | |
2104 | } | |
2105 | ||
2106 | if (is_vector) { | |
2107 | size |= (opc & 2) << 1; | |
2108 | if (size > 4) { | |
2109 | unallocated_encoding(s); | |
2110 | return; | |
2111 | } | |
2112 | is_store = !extract32(opc, 0, 1); | |
8c6afa6a PM |
2113 | if (!fp_access_check(s)) { |
2114 | return; | |
2115 | } | |
229b7a05 AB |
2116 | } else { |
2117 | if (size == 3 && opc == 2) { | |
2118 | /* PRFM - prefetch */ | |
2119 | return; | |
2120 | } | |
2121 | if (opc == 3 && size > 1) { | |
2122 | unallocated_encoding(s); | |
2123 | return; | |
2124 | } | |
2125 | is_store = (opc == 0); | |
2126 | is_signed = extract32(opc, 1, 1); | |
2127 | is_extended = (size < 3) && extract32(opc, 0, 1); | |
2128 | } | |
2129 | ||
2130 | if (rn == 31) { | |
2131 | gen_check_sp_alignment(s); | |
2132 | } | |
2133 | tcg_addr = read_cpu_reg_sp(s, rn, 1); | |
2134 | ||
2135 | tcg_rm = read_cpu_reg(s, rm, 1); | |
2136 | ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0); | |
2137 | ||
2138 | tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_rm); | |
2139 | ||
2140 | if (is_vector) { | |
2141 | if (is_store) { | |
2142 | do_fp_st(s, rt, tcg_addr, size); | |
2143 | } else { | |
2144 | do_fp_ld(s, rt, tcg_addr, size); | |
2145 | } | |
2146 | } else { | |
2147 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | |
2148 | if (is_store) { | |
2149 | do_gpr_st(s, tcg_rt, tcg_addr, size); | |
2150 | } else { | |
2151 | do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, is_extended); | |
2152 | } | |
2153 | } | |
2154 | } | |
2155 | ||
d5612f10 AB |
2156 | /* |
2157 | * C3.3.13 Load/store (unsigned immediate) | |
2158 | * | |
2159 | * 31 30 29 27 26 25 24 23 22 21 10 9 5 | |
2160 | * +----+-------+---+-----+-----+------------+-------+------+ | |
2161 | * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt | | |
2162 | * +----+-------+---+-----+-----+------------+-------+------+ | |
2163 | * | |
2164 | * For non-vector: | |
2165 | * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit | |
2166 | * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 | |
2167 | * For vector: | |
2168 | * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated | |
2169 | * opc<0>: 0 -> store, 1 -> load | |
2170 | * Rn: base address register (inc SP) | |
2171 | * Rt: target register | |
2172 | */ | |
2173 | static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn) | |
2174 | { | |
2175 | int rt = extract32(insn, 0, 5); | |
2176 | int rn = extract32(insn, 5, 5); | |
2177 | unsigned int imm12 = extract32(insn, 10, 12); | |
2178 | bool is_vector = extract32(insn, 26, 1); | |
2179 | int size = extract32(insn, 30, 2); | |
2180 | int opc = extract32(insn, 22, 2); | |
2181 | unsigned int offset; | |
2182 | ||
2183 | TCGv_i64 tcg_addr; | |
2184 | ||
2185 | bool is_store; | |
2186 | bool is_signed = false; | |
2187 | bool is_extended = false; | |
2188 | ||
2189 | if (is_vector) { | |
2190 | size |= (opc & 2) << 1; | |
2191 | if (size > 4) { | |
2192 | unallocated_encoding(s); | |
2193 | return; | |
2194 | } | |
2195 | is_store = !extract32(opc, 0, 1); | |
8c6afa6a PM |
2196 | if (!fp_access_check(s)) { |
2197 | return; | |
2198 | } | |
d5612f10 AB |
2199 | } else { |
2200 | if (size == 3 && opc == 2) { | |
2201 | /* PRFM - prefetch */ | |
2202 | return; | |
2203 | } | |
2204 | if (opc == 3 && size > 1) { | |
2205 | unallocated_encoding(s); | |
2206 | return; | |
2207 | } | |
2208 | is_store = (opc == 0); | |
2209 | is_signed = extract32(opc, 1, 1); | |
2210 | is_extended = (size < 3) && extract32(opc, 0, 1); | |
2211 | } | |
2212 | ||
2213 | if (rn == 31) { | |
2214 | gen_check_sp_alignment(s); | |
2215 | } | |
2216 | tcg_addr = read_cpu_reg_sp(s, rn, 1); | |
2217 | offset = imm12 << size; | |
2218 | tcg_gen_addi_i64(tcg_addr, tcg_addr, offset); | |
2219 | ||
2220 | if (is_vector) { | |
2221 | if (is_store) { | |
2222 | do_fp_st(s, rt, tcg_addr, size); | |
2223 | } else { | |
2224 | do_fp_ld(s, rt, tcg_addr, size); | |
2225 | } | |
2226 | } else { | |
2227 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | |
2228 | if (is_store) { | |
2229 | do_gpr_st(s, tcg_rt, tcg_addr, size); | |
2230 | } else { | |
2231 | do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, is_extended); | |
2232 | } | |
2233 | } | |
2234 | } | |
2235 | ||
ad7ee8a2 CF |
2236 | /* Load/store register (all forms) */ |
2237 | static void disas_ldst_reg(DisasContext *s, uint32_t insn) | |
2238 | { | |
d5612f10 AB |
2239 | switch (extract32(insn, 24, 2)) { |
2240 | case 0: | |
229b7a05 AB |
2241 | if (extract32(insn, 21, 1) == 1 && extract32(insn, 10, 2) == 2) { |
2242 | disas_ldst_reg_roffset(s, insn); | |
2243 | } else { | |
60510aed PM |
2244 | /* Load/store register (unscaled immediate) |
2245 | * Load/store immediate pre/post-indexed | |
2246 | * Load/store register unprivileged | |
2247 | */ | |
2248 | disas_ldst_reg_imm9(s, insn); | |
229b7a05 | 2249 | } |
d5612f10 AB |
2250 | break; |
2251 | case 1: | |
2252 | disas_ldst_reg_unsigned_imm(s, insn); | |
2253 | break; | |
2254 | default: | |
2255 | unallocated_encoding(s); | |
2256 | break; | |
2257 | } | |
ad7ee8a2 CF |
2258 | } |
2259 | ||
72430bf5 AB |
2260 | /* C3.3.1 AdvSIMD load/store multiple structures |
2261 | * | |
2262 | * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0 | |
2263 | * +---+---+---------------+---+-------------+--------+------+------+------+ | |
2264 | * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt | | |
2265 | * +---+---+---------------+---+-------------+--------+------+------+------+ | |
2266 | * | |
2267 | * C3.3.2 AdvSIMD load/store multiple structures (post-indexed) | |
2268 | * | |
2269 | * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0 | |
2270 | * +---+---+---------------+---+---+---------+--------+------+------+------+ | |
2271 | * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt | | |
2272 | * +---+---+---------------+---+---+---------+--------+------+------+------+ | |
2273 | * | |
2274 | * Rt: first (or only) SIMD&FP register to be transferred | |
2275 | * Rn: base address or SP | |
2276 | * Rm (post-index only): post-index register (when !31) or size dependent #imm | |
2277 | */ | |
ad7ee8a2 CF |
2278 | static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) |
2279 | { | |
72430bf5 AB |
2280 | int rt = extract32(insn, 0, 5); |
2281 | int rn = extract32(insn, 5, 5); | |
2282 | int size = extract32(insn, 10, 2); | |
2283 | int opcode = extract32(insn, 12, 4); | |
2284 | bool is_store = !extract32(insn, 22, 1); | |
2285 | bool is_postidx = extract32(insn, 23, 1); | |
2286 | bool is_q = extract32(insn, 30, 1); | |
2287 | TCGv_i64 tcg_addr, tcg_rn; | |
2288 | ||
2289 | int ebytes = 1 << size; | |
2290 | int elements = (is_q ? 128 : 64) / (8 << size); | |
2291 | int rpt; /* num iterations */ | |
2292 | int selem; /* structure elements */ | |
2293 | int r; | |
2294 | ||
2295 | if (extract32(insn, 31, 1) || extract32(insn, 21, 1)) { | |
2296 | unallocated_encoding(s); | |
2297 | return; | |
2298 | } | |
2299 | ||
2300 | /* From the shared decode logic */ | |
2301 | switch (opcode) { | |
2302 | case 0x0: | |
2303 | rpt = 1; | |
2304 | selem = 4; | |
2305 | break; | |
2306 | case 0x2: | |
2307 | rpt = 4; | |
2308 | selem = 1; | |
2309 | break; | |
2310 | case 0x4: | |
2311 | rpt = 1; | |
2312 | selem = 3; | |
2313 | break; | |
2314 | case 0x6: | |
2315 | rpt = 3; | |
2316 | selem = 1; | |
2317 | break; | |
2318 | case 0x7: | |
2319 | rpt = 1; | |
2320 | selem = 1; | |
2321 | break; | |
2322 | case 0x8: | |
2323 | rpt = 1; | |
2324 | selem = 2; | |
2325 | break; | |
2326 | case 0xa: | |
2327 | rpt = 2; | |
2328 | selem = 1; | |
2329 | break; | |
2330 | default: | |
2331 | unallocated_encoding(s); | |
2332 | return; | |
2333 | } | |
2334 | ||
2335 | if (size == 3 && !is_q && selem != 1) { | |
2336 | /* reserved */ | |
2337 | unallocated_encoding(s); | |
2338 | return; | |
2339 | } | |
2340 | ||
8c6afa6a PM |
2341 | if (!fp_access_check(s)) { |
2342 | return; | |
2343 | } | |
2344 | ||
72430bf5 AB |
2345 | if (rn == 31) { |
2346 | gen_check_sp_alignment(s); | |
2347 | } | |
2348 | ||
2349 | tcg_rn = cpu_reg_sp(s, rn); | |
2350 | tcg_addr = tcg_temp_new_i64(); | |
2351 | tcg_gen_mov_i64(tcg_addr, tcg_rn); | |
2352 | ||
2353 | for (r = 0; r < rpt; r++) { | |
2354 | int e; | |
2355 | for (e = 0; e < elements; e++) { | |
2356 | int tt = (rt + r) % 32; | |
2357 | int xs; | |
2358 | for (xs = 0; xs < selem; xs++) { | |
2359 | if (is_store) { | |
2360 | do_vec_st(s, tt, e, tcg_addr, size); | |
2361 | } else { | |
2362 | do_vec_ld(s, tt, e, tcg_addr, size); | |
2363 | ||
2364 | /* For non-quad operations, setting a slice of the low | |
2365 | * 64 bits of the register clears the high 64 bits (in | |
2366 | * the ARM ARM pseudocode this is implicit in the fact | |
2367 | * that 'rval' is a 64 bit wide variable). We optimize | |
2368 | * by noticing that we only need to do this the first | |
2369 | * time we touch a register. | |
2370 | */ | |
2371 | if (!is_q && e == 0 && (r == 0 || xs == selem - 1)) { | |
2372 | clear_vec_high(s, tt); | |
2373 | } | |
2374 | } | |
2375 | tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes); | |
2376 | tt = (tt + 1) % 32; | |
2377 | } | |
2378 | } | |
2379 | } | |
2380 | ||
2381 | if (is_postidx) { | |
2382 | int rm = extract32(insn, 16, 5); | |
2383 | if (rm == 31) { | |
2384 | tcg_gen_mov_i64(tcg_rn, tcg_addr); | |
2385 | } else { | |
2386 | tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); | |
2387 | } | |
2388 | } | |
2389 | tcg_temp_free_i64(tcg_addr); | |
ad7ee8a2 CF |
2390 | } |
2391 | ||
df54e47d PM |
2392 | /* C3.3.3 AdvSIMD load/store single structure |
2393 | * | |
2394 | * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0 | |
2395 | * +---+---+---------------+-----+-----------+-----+---+------+------+------+ | |
2396 | * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt | | |
2397 | * +---+---+---------------+-----+-----------+-----+---+------+------+------+ | |
2398 | * | |
2399 | * C3.3.4 AdvSIMD load/store single structure (post-indexed) | |
2400 | * | |
2401 | * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0 | |
2402 | * +---+---+---------------+-----+-----------+-----+---+------+------+------+ | |
2403 | * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt | | |
2404 | * +---+---+---------------+-----+-----------+-----+---+------+------+------+ | |
2405 | * | |
2406 | * Rt: first (or only) SIMD&FP register to be transferred | |
2407 | * Rn: base address or SP | |
2408 | * Rm (post-index only): post-index register (when !31) or size dependent #imm | |
2409 | * index = encoded in Q:S:size dependent on size | |
2410 | * | |
2411 | * lane_size = encoded in R, opc | |
2412 | * transfer width = encoded in opc, S, size | |
2413 | */ | |
ad7ee8a2 CF |
2414 | static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) |
2415 | { | |
df54e47d PM |
2416 | int rt = extract32(insn, 0, 5); |
2417 | int rn = extract32(insn, 5, 5); | |
2418 | int size = extract32(insn, 10, 2); | |
2419 | int S = extract32(insn, 12, 1); | |
2420 | int opc = extract32(insn, 13, 3); | |
2421 | int R = extract32(insn, 21, 1); | |
2422 | int is_load = extract32(insn, 22, 1); | |
2423 | int is_postidx = extract32(insn, 23, 1); | |
2424 | int is_q = extract32(insn, 30, 1); | |
2425 | ||
2426 | int scale = extract32(opc, 1, 2); | |
2427 | int selem = (extract32(opc, 0, 1) << 1 | R) + 1; | |
2428 | bool replicate = false; | |
2429 | int index = is_q << 3 | S << 2 | size; | |
2430 | int ebytes, xs; | |
2431 | TCGv_i64 tcg_addr, tcg_rn; | |
2432 | ||
2433 | switch (scale) { | |
2434 | case 3: | |
2435 | if (!is_load || S) { | |
2436 | unallocated_encoding(s); | |
2437 | return; | |
2438 | } | |
2439 | scale = size; | |
2440 | replicate = true; | |
2441 | break; | |
2442 | case 0: | |
2443 | break; | |
2444 | case 1: | |
2445 | if (extract32(size, 0, 1)) { | |
2446 | unallocated_encoding(s); | |
2447 | return; | |
2448 | } | |
2449 | index >>= 1; | |
2450 | break; | |
2451 | case 2: | |
2452 | if (extract32(size, 1, 1)) { | |
2453 | unallocated_encoding(s); | |
2454 | return; | |
2455 | } | |
2456 | if (!extract32(size, 0, 1)) { | |
2457 | index >>= 2; | |
2458 | } else { | |
2459 | if (S) { | |
2460 | unallocated_encoding(s); | |
2461 | return; | |
2462 | } | |
2463 | index >>= 3; | |
2464 | scale = 3; | |
2465 | } | |
2466 | break; | |
2467 | default: | |
2468 | g_assert_not_reached(); | |
2469 | } | |
2470 | ||
8c6afa6a PM |
2471 | if (!fp_access_check(s)) { |
2472 | return; | |
2473 | } | |
2474 | ||
df54e47d PM |
2475 | ebytes = 1 << scale; |
2476 | ||
2477 | if (rn == 31) { | |
2478 | gen_check_sp_alignment(s); | |
2479 | } | |
2480 | ||
2481 | tcg_rn = cpu_reg_sp(s, rn); | |
2482 | tcg_addr = tcg_temp_new_i64(); | |
2483 | tcg_gen_mov_i64(tcg_addr, tcg_rn); | |
2484 | ||
2485 | for (xs = 0; xs < selem; xs++) { | |
2486 | if (replicate) { | |
2487 | /* Load and replicate to all elements */ | |
2488 | uint64_t mulconst; | |
2489 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
2490 | ||
2491 | tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr, | |
2492 | get_mem_index(s), MO_TE + scale); | |
2493 | switch (scale) { | |
2494 | case 0: | |
2495 | mulconst = 0x0101010101010101ULL; | |
2496 | break; | |
2497 | case 1: | |
2498 | mulconst = 0x0001000100010001ULL; | |
2499 | break; | |
2500 | case 2: | |
2501 | mulconst = 0x0000000100000001ULL; | |
2502 | break; | |
2503 | case 3: | |
2504 | mulconst = 0; | |
2505 | break; | |
2506 | default: | |
2507 | g_assert_not_reached(); | |
2508 | } | |
2509 | if (mulconst) { | |
2510 | tcg_gen_muli_i64(tcg_tmp, tcg_tmp, mulconst); | |
2511 | } | |
2512 | write_vec_element(s, tcg_tmp, rt, 0, MO_64); | |
2513 | if (is_q) { | |
2514 | write_vec_element(s, tcg_tmp, rt, 1, MO_64); | |
2515 | } else { | |
2516 | clear_vec_high(s, rt); | |
2517 | } | |
2518 | tcg_temp_free_i64(tcg_tmp); | |
2519 | } else { | |
2520 | /* Load/store one element per register */ | |
2521 | if (is_load) { | |
2522 | do_vec_ld(s, rt, index, tcg_addr, MO_TE + scale); | |
2523 | } else { | |
2524 | do_vec_st(s, rt, index, tcg_addr, MO_TE + scale); | |
2525 | } | |
2526 | } | |
2527 | tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes); | |
2528 | rt = (rt + 1) % 32; | |
2529 | } | |
2530 | ||
2531 | if (is_postidx) { | |
2532 | int rm = extract32(insn, 16, 5); | |
2533 | if (rm == 31) { | |
2534 | tcg_gen_mov_i64(tcg_rn, tcg_addr); | |
2535 | } else { | |
2536 | tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); | |
2537 | } | |
2538 | } | |
2539 | tcg_temp_free_i64(tcg_addr); | |
ad7ee8a2 CF |
2540 | } |
2541 | ||
2542 | /* C3.3 Loads and stores */ | |
2543 | static void disas_ldst(DisasContext *s, uint32_t insn) | |
2544 | { | |
2545 | switch (extract32(insn, 24, 6)) { | |
2546 | case 0x08: /* Load/store exclusive */ | |
2547 | disas_ldst_excl(s, insn); | |
2548 | break; | |
2549 | case 0x18: case 0x1c: /* Load register (literal) */ | |
2550 | disas_ld_lit(s, insn); | |
2551 | break; | |
2552 | case 0x28: case 0x29: | |
2553 | case 0x2c: case 0x2d: /* Load/store pair (all forms) */ | |
2554 | disas_ldst_pair(s, insn); | |
2555 | break; | |
2556 | case 0x38: case 0x39: | |
2557 | case 0x3c: case 0x3d: /* Load/store register (all forms) */ | |
2558 | disas_ldst_reg(s, insn); | |
2559 | break; | |
2560 | case 0x0c: /* AdvSIMD load/store multiple structures */ | |
2561 | disas_ldst_multiple_struct(s, insn); | |
2562 | break; | |
2563 | case 0x0d: /* AdvSIMD load/store single structure */ | |
2564 | disas_ldst_single_struct(s, insn); | |
2565 | break; | |
2566 | default: | |
2567 | unallocated_encoding(s); | |
2568 | break; | |
2569 | } | |
2570 | } | |
2571 | ||
15bfe8b6 AG |
2572 | /* C3.4.6 PC-rel. addressing |
2573 | * 31 30 29 28 24 23 5 4 0 | |
2574 | * +----+-------+-----------+-------------------+------+ | |
2575 | * | op | immlo | 1 0 0 0 0 | immhi | Rd | | |
2576 | * +----+-------+-----------+-------------------+------+ | |
2577 | */ | |
ad7ee8a2 CF |
2578 | static void disas_pc_rel_adr(DisasContext *s, uint32_t insn) |
2579 | { | |
15bfe8b6 AG |
2580 | unsigned int page, rd; |
2581 | uint64_t base; | |
2582 | int64_t offset; | |
2583 | ||
2584 | page = extract32(insn, 31, 1); | |
2585 | /* SignExtend(immhi:immlo) -> offset */ | |
2586 | offset = ((int64_t)sextract32(insn, 5, 19) << 2) | extract32(insn, 29, 2); | |
2587 | rd = extract32(insn, 0, 5); | |
2588 | base = s->pc - 4; | |
2589 | ||
2590 | if (page) { | |
2591 | /* ADRP (page based) */ | |
2592 | base &= ~0xfff; | |
2593 | offset <<= 12; | |
2594 | } | |
2595 | ||
2596 | tcg_gen_movi_i64(cpu_reg(s, rd), base + offset); | |
ad7ee8a2 CF |
2597 | } |
2598 | ||
b0ff21b4 AB |
2599 | /* |
2600 | * C3.4.1 Add/subtract (immediate) | |
2601 | * | |
2602 | * 31 30 29 28 24 23 22 21 10 9 5 4 0 | |
2603 | * +--+--+--+-----------+-----+-------------+-----+-----+ | |
2604 | * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd | | |
2605 | * +--+--+--+-----------+-----+-------------+-----+-----+ | |
2606 | * | |
2607 | * sf: 0 -> 32bit, 1 -> 64bit | |
2608 | * op: 0 -> add , 1 -> sub | |
2609 | * S: 1 -> set flags | |
2610 | * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12 | |
2611 | */ | |
ad7ee8a2 CF |
2612 | static void disas_add_sub_imm(DisasContext *s, uint32_t insn) |
2613 | { | |
b0ff21b4 AB |
2614 | int rd = extract32(insn, 0, 5); |
2615 | int rn = extract32(insn, 5, 5); | |
2616 | uint64_t imm = extract32(insn, 10, 12); | |
2617 | int shift = extract32(insn, 22, 2); | |
2618 | bool setflags = extract32(insn, 29, 1); | |
2619 | bool sub_op = extract32(insn, 30, 1); | |
2620 | bool is_64bit = extract32(insn, 31, 1); | |
2621 | ||
2622 | TCGv_i64 tcg_rn = cpu_reg_sp(s, rn); | |
2623 | TCGv_i64 tcg_rd = setflags ? cpu_reg(s, rd) : cpu_reg_sp(s, rd); | |
2624 | TCGv_i64 tcg_result; | |
2625 | ||
2626 | switch (shift) { | |
2627 | case 0x0: | |
2628 | break; | |
2629 | case 0x1: | |
2630 | imm <<= 12; | |
2631 | break; | |
2632 | default: | |
2633 | unallocated_encoding(s); | |
2634 | return; | |
2635 | } | |
2636 | ||
2637 | tcg_result = tcg_temp_new_i64(); | |
2638 | if (!setflags) { | |
2639 | if (sub_op) { | |
2640 | tcg_gen_subi_i64(tcg_result, tcg_rn, imm); | |
2641 | } else { | |
2642 | tcg_gen_addi_i64(tcg_result, tcg_rn, imm); | |
2643 | } | |
2644 | } else { | |
2645 | TCGv_i64 tcg_imm = tcg_const_i64(imm); | |
2646 | if (sub_op) { | |
2647 | gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); | |
2648 | } else { | |
2649 | gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); | |
2650 | } | |
2651 | tcg_temp_free_i64(tcg_imm); | |
2652 | } | |
2653 | ||
2654 | if (is_64bit) { | |
2655 | tcg_gen_mov_i64(tcg_rd, tcg_result); | |
2656 | } else { | |
2657 | tcg_gen_ext32u_i64(tcg_rd, tcg_result); | |
2658 | } | |
2659 | ||
2660 | tcg_temp_free_i64(tcg_result); | |
ad7ee8a2 CF |
2661 | } |
2662 | ||
71b46089 AG |
2663 | /* The input should be a value in the bottom e bits (with higher |
2664 | * bits zero); returns that value replicated into every element | |
2665 | * of size e in a 64 bit integer. | |
2666 | */ | |
2667 | static uint64_t bitfield_replicate(uint64_t mask, unsigned int e) | |
2668 | { | |
2669 | assert(e != 0); | |
2670 | while (e < 64) { | |
2671 | mask |= mask << e; | |
2672 | e *= 2; | |
2673 | } | |
2674 | return mask; | |
2675 | } | |
2676 | ||
2677 | /* Return a value with the bottom len bits set (where 0 < len <= 64) */ | |
2678 | static inline uint64_t bitmask64(unsigned int length) | |
2679 | { | |
2680 | assert(length > 0 && length <= 64); | |
2681 | return ~0ULL >> (64 - length); | |
2682 | } | |
2683 | ||
2684 | /* Simplified variant of pseudocode DecodeBitMasks() for the case where we | |
2685 | * only require the wmask. Returns false if the imms/immr/immn are a reserved | |
2686 | * value (ie should cause a guest UNDEF exception), and true if they are | |
2687 | * valid, in which case the decoded bit pattern is written to result. | |
2688 | */ | |
2689 | static bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, | |
2690 | unsigned int imms, unsigned int immr) | |
2691 | { | |
2692 | uint64_t mask; | |
2693 | unsigned e, levels, s, r; | |
2694 | int len; | |
2695 | ||
2696 | assert(immn < 2 && imms < 64 && immr < 64); | |
2697 | ||
2698 | /* The bit patterns we create here are 64 bit patterns which | |
2699 | * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or | |
2700 | * 64 bits each. Each element contains the same value: a run | |
2701 | * of between 1 and e-1 non-zero bits, rotated within the | |
2702 | * element by between 0 and e-1 bits. | |
2703 | * | |
2704 | * The element size and run length are encoded into immn (1 bit) | |
2705 | * and imms (6 bits) as follows: | |
2706 | * 64 bit elements: immn = 1, imms = <length of run - 1> | |
2707 | * 32 bit elements: immn = 0, imms = 0 : <length of run - 1> | |
2708 | * 16 bit elements: immn = 0, imms = 10 : <length of run - 1> | |
2709 | * 8 bit elements: immn = 0, imms = 110 : <length of run - 1> | |
2710 | * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1> | |
2711 | * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1> | |
2712 | * Notice that immn = 0, imms = 11111x is the only combination | |
2713 | * not covered by one of the above options; this is reserved. | |
2714 | * Further, <length of run - 1> all-ones is a reserved pattern. | |
2715 | * | |
2716 | * In all cases the rotation is by immr % e (and immr is 6 bits). | |
2717 | */ | |
2718 | ||
2719 | /* First determine the element size */ | |
2720 | len = 31 - clz32((immn << 6) | (~imms & 0x3f)); | |
2721 | if (len < 1) { | |
2722 | /* This is the immn == 0, imms == 0x11111x case */ | |
2723 | return false; | |
2724 | } | |
2725 | e = 1 << len; | |
2726 | ||
2727 | levels = e - 1; | |
2728 | s = imms & levels; | |
2729 | r = immr & levels; | |
2730 | ||
2731 | if (s == levels) { | |
2732 | /* <length of run - 1> mustn't be all-ones. */ | |
2733 | return false; | |
2734 | } | |
2735 | ||
2736 | /* Create the value of one element: s+1 set bits rotated | |
2737 | * by r within the element (which is e bits wide)... | |
2738 | */ | |
2739 | mask = bitmask64(s + 1); | |
2740 | mask = (mask >> r) | (mask << (e - r)); | |
2741 | /* ...then replicate the element over the whole 64 bit value */ | |
2742 | mask = bitfield_replicate(mask, e); | |
2743 | *result = mask; | |
2744 | return true; | |
2745 | } | |
2746 | ||
2747 | /* C3.4.4 Logical (immediate) | |
2748 | * 31 30 29 28 23 22 21 16 15 10 9 5 4 0 | |
2749 | * +----+-----+-------------+---+------+------+------+------+ | |
2750 | * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd | | |
2751 | * +----+-----+-------------+---+------+------+------+------+ | |
2752 | */ | |
ad7ee8a2 CF |
2753 | static void disas_logic_imm(DisasContext *s, uint32_t insn) |
2754 | { | |
71b46089 AG |
2755 | unsigned int sf, opc, is_n, immr, imms, rn, rd; |
2756 | TCGv_i64 tcg_rd, tcg_rn; | |
2757 | uint64_t wmask; | |
2758 | bool is_and = false; | |
2759 | ||
2760 | sf = extract32(insn, 31, 1); | |
2761 | opc = extract32(insn, 29, 2); | |
2762 | is_n = extract32(insn, 22, 1); | |
2763 | immr = extract32(insn, 16, 6); | |
2764 | imms = extract32(insn, 10, 6); | |
2765 | rn = extract32(insn, 5, 5); | |
2766 | rd = extract32(insn, 0, 5); | |
2767 | ||
2768 | if (!sf && is_n) { | |
2769 | unallocated_encoding(s); | |
2770 | return; | |
2771 | } | |
2772 | ||
2773 | if (opc == 0x3) { /* ANDS */ | |
2774 | tcg_rd = cpu_reg(s, rd); | |
2775 | } else { | |
2776 | tcg_rd = cpu_reg_sp(s, rd); | |
2777 | } | |
2778 | tcg_rn = cpu_reg(s, rn); | |
2779 | ||
2780 | if (!logic_imm_decode_wmask(&wmask, is_n, imms, immr)) { | |
2781 | /* some immediate field values are reserved */ | |
2782 | unallocated_encoding(s); | |
2783 | return; | |
2784 | } | |
2785 | ||
2786 | if (!sf) { | |
2787 | wmask &= 0xffffffff; | |
2788 | } | |
2789 | ||
2790 | switch (opc) { | |
2791 | case 0x3: /* ANDS */ | |
2792 | case 0x0: /* AND */ | |
2793 | tcg_gen_andi_i64(tcg_rd, tcg_rn, wmask); | |
2794 | is_and = true; | |
2795 | break; | |
2796 | case 0x1: /* ORR */ | |
2797 | tcg_gen_ori_i64(tcg_rd, tcg_rn, wmask); | |
2798 | break; | |
2799 | case 0x2: /* EOR */ | |
2800 | tcg_gen_xori_i64(tcg_rd, tcg_rn, wmask); | |
2801 | break; | |
2802 | default: | |
2803 | assert(FALSE); /* must handle all above */ | |
2804 | break; | |
2805 | } | |
2806 | ||
2807 | if (!sf && !is_and) { | |
2808 | /* zero extend final result; we know we can skip this for AND | |
2809 | * since the immediate had the high 32 bits clear. | |
2810 | */ | |
2811 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
2812 | } | |
2813 | ||
2814 | if (opc == 3) { /* ANDS */ | |
2815 | gen_logic_CC(sf, tcg_rd); | |
2816 | } | |
ad7ee8a2 CF |
2817 | } |
2818 | ||
ed6ec679 AB |
2819 | /* |
2820 | * C3.4.5 Move wide (immediate) | |
2821 | * | |
2822 | * 31 30 29 28 23 22 21 20 5 4 0 | |
2823 | * +--+-----+-------------+-----+----------------+------+ | |
2824 | * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd | | |
2825 | * +--+-----+-------------+-----+----------------+------+ | |
2826 | * | |
2827 | * sf: 0 -> 32 bit, 1 -> 64 bit | |
2828 | * opc: 00 -> N, 10 -> Z, 11 -> K | |
2829 | * hw: shift/16 (0,16, and sf only 32, 48) | |
2830 | */ | |
ad7ee8a2 CF |
2831 | static void disas_movw_imm(DisasContext *s, uint32_t insn) |
2832 | { | |
ed6ec679 AB |
2833 | int rd = extract32(insn, 0, 5); |
2834 | uint64_t imm = extract32(insn, 5, 16); | |
2835 | int sf = extract32(insn, 31, 1); | |
2836 | int opc = extract32(insn, 29, 2); | |
2837 | int pos = extract32(insn, 21, 2) << 4; | |
2838 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
2839 | TCGv_i64 tcg_imm; | |
2840 | ||
2841 | if (!sf && (pos >= 32)) { | |
2842 | unallocated_encoding(s); | |
2843 | return; | |
2844 | } | |
2845 | ||
2846 | switch (opc) { | |
2847 | case 0: /* MOVN */ | |
2848 | case 2: /* MOVZ */ | |
2849 | imm <<= pos; | |
2850 | if (opc == 0) { | |
2851 | imm = ~imm; | |
2852 | } | |
2853 | if (!sf) { | |
2854 | imm &= 0xffffffffu; | |
2855 | } | |
2856 | tcg_gen_movi_i64(tcg_rd, imm); | |
2857 | break; | |
2858 | case 3: /* MOVK */ | |
2859 | tcg_imm = tcg_const_i64(imm); | |
2860 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_imm, pos, 16); | |
2861 | tcg_temp_free_i64(tcg_imm); | |
2862 | if (!sf) { | |
2863 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
2864 | } | |
2865 | break; | |
2866 | default: | |
2867 | unallocated_encoding(s); | |
2868 | break; | |
2869 | } | |
ad7ee8a2 CF |
2870 | } |
2871 | ||
88077742 CF |
2872 | /* C3.4.2 Bitfield |
2873 | * 31 30 29 28 23 22 21 16 15 10 9 5 4 0 | |
2874 | * +----+-----+-------------+---+------+------+------+------+ | |
2875 | * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd | | |
2876 | * +----+-----+-------------+---+------+------+------+------+ | |
2877 | */ | |
ad7ee8a2 CF |
2878 | static void disas_bitfield(DisasContext *s, uint32_t insn) |
2879 | { | |
88077742 CF |
2880 | unsigned int sf, n, opc, ri, si, rn, rd, bitsize, pos, len; |
2881 | TCGv_i64 tcg_rd, tcg_tmp; | |
2882 | ||
2883 | sf = extract32(insn, 31, 1); | |
2884 | opc = extract32(insn, 29, 2); | |
2885 | n = extract32(insn, 22, 1); | |
2886 | ri = extract32(insn, 16, 6); | |
2887 | si = extract32(insn, 10, 6); | |
2888 | rn = extract32(insn, 5, 5); | |
2889 | rd = extract32(insn, 0, 5); | |
2890 | bitsize = sf ? 64 : 32; | |
2891 | ||
2892 | if (sf != n || ri >= bitsize || si >= bitsize || opc > 2) { | |
2893 | unallocated_encoding(s); | |
2894 | return; | |
2895 | } | |
2896 | ||
2897 | tcg_rd = cpu_reg(s, rd); | |
2898 | tcg_tmp = read_cpu_reg(s, rn, sf); | |
2899 | ||
2900 | /* OPTME: probably worth recognizing common cases of ext{8,16,32}{u,s} */ | |
2901 | ||
2902 | if (opc != 1) { /* SBFM or UBFM */ | |
2903 | tcg_gen_movi_i64(tcg_rd, 0); | |
2904 | } | |
2905 | ||
2906 | /* do the bit move operation */ | |
2907 | if (si >= ri) { | |
2908 | /* Wd<s-r:0> = Wn<s:r> */ | |
2909 | tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri); | |
2910 | pos = 0; | |
2911 | len = (si - ri) + 1; | |
2912 | } else { | |
2913 | /* Wd<32+s-r,32-r> = Wn<s:0> */ | |
2914 | pos = bitsize - ri; | |
2915 | len = si + 1; | |
2916 | } | |
2917 | ||
2918 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len); | |
2919 | ||
2920 | if (opc == 0) { /* SBFM - sign extend the destination field */ | |
2921 | tcg_gen_shli_i64(tcg_rd, tcg_rd, 64 - (pos + len)); | |
2922 | tcg_gen_sari_i64(tcg_rd, tcg_rd, 64 - (pos + len)); | |
2923 | } | |
2924 | ||
2925 | if (!sf) { /* zero extend final result */ | |
2926 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
2927 | } | |
ad7ee8a2 CF |
2928 | } |
2929 | ||
e801de93 AG |
2930 | /* C3.4.3 Extract |
2931 | * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0 | |
2932 | * +----+------+-------------+---+----+------+--------+------+------+ | |
2933 | * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd | | |
2934 | * +----+------+-------------+---+----+------+--------+------+------+ | |
2935 | */ | |
ad7ee8a2 CF |
2936 | static void disas_extract(DisasContext *s, uint32_t insn) |
2937 | { | |
e801de93 AG |
2938 | unsigned int sf, n, rm, imm, rn, rd, bitsize, op21, op0; |
2939 | ||
2940 | sf = extract32(insn, 31, 1); | |
2941 | n = extract32(insn, 22, 1); | |
2942 | rm = extract32(insn, 16, 5); | |
2943 | imm = extract32(insn, 10, 6); | |
2944 | rn = extract32(insn, 5, 5); | |
2945 | rd = extract32(insn, 0, 5); | |
2946 | op21 = extract32(insn, 29, 2); | |
2947 | op0 = extract32(insn, 21, 1); | |
2948 | bitsize = sf ? 64 : 32; | |
2949 | ||
2950 | if (sf != n || op21 || op0 || imm >= bitsize) { | |
2951 | unallocated_encoding(s); | |
2952 | } else { | |
2953 | TCGv_i64 tcg_rd, tcg_rm, tcg_rn; | |
2954 | ||
2955 | tcg_rd = cpu_reg(s, rd); | |
2956 | ||
2957 | if (imm) { | |
2958 | /* OPTME: we can special case rm==rn as a rotate */ | |
2959 | tcg_rm = read_cpu_reg(s, rm, sf); | |
2960 | tcg_rn = read_cpu_reg(s, rn, sf); | |
2961 | tcg_gen_shri_i64(tcg_rm, tcg_rm, imm); | |
2962 | tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm); | |
2963 | tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn); | |
2964 | if (!sf) { | |
2965 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
2966 | } | |
2967 | } else { | |
2968 | /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts, | |
2969 | * so an extract from bit 0 is a special case. | |
2970 | */ | |
2971 | if (sf) { | |
2972 | tcg_gen_mov_i64(tcg_rd, cpu_reg(s, rm)); | |
2973 | } else { | |
2974 | tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm)); | |
2975 | } | |
2976 | } | |
2977 | ||
2978 | } | |
ad7ee8a2 CF |
2979 | } |
2980 | ||
2981 | /* C3.4 Data processing - immediate */ | |
2982 | static void disas_data_proc_imm(DisasContext *s, uint32_t insn) | |
2983 | { | |
2984 | switch (extract32(insn, 23, 6)) { | |
2985 | case 0x20: case 0x21: /* PC-rel. addressing */ | |
2986 | disas_pc_rel_adr(s, insn); | |
2987 | break; | |
2988 | case 0x22: case 0x23: /* Add/subtract (immediate) */ | |
2989 | disas_add_sub_imm(s, insn); | |
2990 | break; | |
2991 | case 0x24: /* Logical (immediate) */ | |
2992 | disas_logic_imm(s, insn); | |
2993 | break; | |
2994 | case 0x25: /* Move wide (immediate) */ | |
2995 | disas_movw_imm(s, insn); | |
2996 | break; | |
2997 | case 0x26: /* Bitfield */ | |
2998 | disas_bitfield(s, insn); | |
2999 | break; | |
3000 | case 0x27: /* Extract */ | |
3001 | disas_extract(s, insn); | |
3002 | break; | |
3003 | default: | |
3004 | unallocated_encoding(s); | |
3005 | break; | |
3006 | } | |
3007 | } | |
3008 | ||
832ffa1c AG |
3009 | /* Shift a TCGv src by TCGv shift_amount, put result in dst. |
3010 | * Note that it is the caller's responsibility to ensure that the | |
3011 | * shift amount is in range (ie 0..31 or 0..63) and provide the ARM | |
3012 | * mandated semantics for out of range shifts. | |
3013 | */ | |
3014 | static void shift_reg(TCGv_i64 dst, TCGv_i64 src, int sf, | |
3015 | enum a64_shift_type shift_type, TCGv_i64 shift_amount) | |
3016 | { | |
3017 | switch (shift_type) { | |
3018 | case A64_SHIFT_TYPE_LSL: | |
3019 | tcg_gen_shl_i64(dst, src, shift_amount); | |
3020 | break; | |
3021 | case A64_SHIFT_TYPE_LSR: | |
3022 | tcg_gen_shr_i64(dst, src, shift_amount); | |
3023 | break; | |
3024 | case A64_SHIFT_TYPE_ASR: | |
3025 | if (!sf) { | |
3026 | tcg_gen_ext32s_i64(dst, src); | |
3027 | } | |
3028 | tcg_gen_sar_i64(dst, sf ? src : dst, shift_amount); | |
3029 | break; | |
3030 | case A64_SHIFT_TYPE_ROR: | |
3031 | if (sf) { | |
3032 | tcg_gen_rotr_i64(dst, src, shift_amount); | |
3033 | } else { | |
3034 | TCGv_i32 t0, t1; | |
3035 | t0 = tcg_temp_new_i32(); | |
3036 | t1 = tcg_temp_new_i32(); | |
3037 | tcg_gen_trunc_i64_i32(t0, src); | |
3038 | tcg_gen_trunc_i64_i32(t1, shift_amount); | |
3039 | tcg_gen_rotr_i32(t0, t0, t1); | |
3040 | tcg_gen_extu_i32_i64(dst, t0); | |
3041 | tcg_temp_free_i32(t0); | |
3042 | tcg_temp_free_i32(t1); | |
3043 | } | |
3044 | break; | |
3045 | default: | |
3046 | assert(FALSE); /* all shift types should be handled */ | |
3047 | break; | |
3048 | } | |
3049 | ||
3050 | if (!sf) { /* zero extend final result */ | |
3051 | tcg_gen_ext32u_i64(dst, dst); | |
3052 | } | |
3053 | } | |
3054 | ||
3055 | /* Shift a TCGv src by immediate, put result in dst. | |
3056 | * The shift amount must be in range (this should always be true as the | |
3057 | * relevant instructions will UNDEF on bad shift immediates). | |
3058 | */ | |
3059 | static void shift_reg_imm(TCGv_i64 dst, TCGv_i64 src, int sf, | |
3060 | enum a64_shift_type shift_type, unsigned int shift_i) | |
3061 | { | |
3062 | assert(shift_i < (sf ? 64 : 32)); | |
3063 | ||
3064 | if (shift_i == 0) { | |
3065 | tcg_gen_mov_i64(dst, src); | |
3066 | } else { | |
3067 | TCGv_i64 shift_const; | |
3068 | ||
3069 | shift_const = tcg_const_i64(shift_i); | |
3070 | shift_reg(dst, src, sf, shift_type, shift_const); | |
3071 | tcg_temp_free_i64(shift_const); | |
3072 | } | |
3073 | } | |
3074 | ||
3075 | /* C3.5.10 Logical (shifted register) | |
3076 | * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0 | |
3077 | * +----+-----+-----------+-------+---+------+--------+------+------+ | |
3078 | * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd | | |
3079 | * +----+-----+-----------+-------+---+------+--------+------+------+ | |
3080 | */ | |
ad7ee8a2 CF |
3081 | static void disas_logic_reg(DisasContext *s, uint32_t insn) |
3082 | { | |
832ffa1c AG |
3083 | TCGv_i64 tcg_rd, tcg_rn, tcg_rm; |
3084 | unsigned int sf, opc, shift_type, invert, rm, shift_amount, rn, rd; | |
3085 | ||
3086 | sf = extract32(insn, 31, 1); | |
3087 | opc = extract32(insn, 29, 2); | |
3088 | shift_type = extract32(insn, 22, 2); | |
3089 | invert = extract32(insn, 21, 1); | |
3090 | rm = extract32(insn, 16, 5); | |
3091 | shift_amount = extract32(insn, 10, 6); | |
3092 | rn = extract32(insn, 5, 5); | |
3093 | rd = extract32(insn, 0, 5); | |
3094 | ||
3095 | if (!sf && (shift_amount & (1 << 5))) { | |
3096 | unallocated_encoding(s); | |
3097 | return; | |
3098 | } | |
3099 | ||
3100 | tcg_rd = cpu_reg(s, rd); | |
3101 | ||
3102 | if (opc == 1 && shift_amount == 0 && shift_type == 0 && rn == 31) { | |
3103 | /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for | |
3104 | * register-register MOV and MVN, so it is worth special casing. | |
3105 | */ | |
3106 | tcg_rm = cpu_reg(s, rm); | |
3107 | if (invert) { | |
3108 | tcg_gen_not_i64(tcg_rd, tcg_rm); | |
3109 | if (!sf) { | |
3110 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
3111 | } | |
3112 | } else { | |
3113 | if (sf) { | |
3114 | tcg_gen_mov_i64(tcg_rd, tcg_rm); | |
3115 | } else { | |
3116 | tcg_gen_ext32u_i64(tcg_rd, tcg_rm); | |
3117 | } | |
3118 | } | |
3119 | return; | |
3120 | } | |
3121 | ||
3122 | tcg_rm = read_cpu_reg(s, rm, sf); | |
3123 | ||
3124 | if (shift_amount) { | |
3125 | shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, shift_amount); | |
3126 | } | |
3127 | ||
3128 | tcg_rn = cpu_reg(s, rn); | |
3129 | ||
3130 | switch (opc | (invert << 2)) { | |
3131 | case 0: /* AND */ | |
3132 | case 3: /* ANDS */ | |
3133 | tcg_gen_and_i64(tcg_rd, tcg_rn, tcg_rm); | |
3134 | break; | |
3135 | case 1: /* ORR */ | |
3136 | tcg_gen_or_i64(tcg_rd, tcg_rn, tcg_rm); | |
3137 | break; | |
3138 | case 2: /* EOR */ | |
3139 | tcg_gen_xor_i64(tcg_rd, tcg_rn, tcg_rm); | |
3140 | break; | |
3141 | case 4: /* BIC */ | |
3142 | case 7: /* BICS */ | |
3143 | tcg_gen_andc_i64(tcg_rd, tcg_rn, tcg_rm); | |
3144 | break; | |
3145 | case 5: /* ORN */ | |
3146 | tcg_gen_orc_i64(tcg_rd, tcg_rn, tcg_rm); | |
3147 | break; | |
3148 | case 6: /* EON */ | |
3149 | tcg_gen_eqv_i64(tcg_rd, tcg_rn, tcg_rm); | |
3150 | break; | |
3151 | default: | |
3152 | assert(FALSE); | |
3153 | break; | |
3154 | } | |
3155 | ||
3156 | if (!sf) { | |
3157 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
3158 | } | |
3159 | ||
3160 | if (opc == 3) { | |
3161 | gen_logic_CC(sf, tcg_rd); | |
3162 | } | |
ad7ee8a2 CF |
3163 | } |
3164 | ||
b0ff21b4 AB |
3165 | /* |
3166 | * C3.5.1 Add/subtract (extended register) | |
3167 | * | |
3168 | * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0| | |
3169 | * +--+--+--+-----------+-----+--+-------+------+------+----+----+ | |
3170 | * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd | | |
3171 | * +--+--+--+-----------+-----+--+-------+------+------+----+----+ | |
3172 | * | |
3173 | * sf: 0 -> 32bit, 1 -> 64bit | |
3174 | * op: 0 -> add , 1 -> sub | |
3175 | * S: 1 -> set flags | |
3176 | * opt: 00 | |
3177 | * option: extension type (see DecodeRegExtend) | |
3178 | * imm3: optional shift to Rm | |
3179 | * | |
3180 | * Rd = Rn + LSL(extend(Rm), amount) | |
3181 | */ | |
ad7ee8a2 CF |
3182 | static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn) |
3183 | { | |
b0ff21b4 AB |
3184 | int rd = extract32(insn, 0, 5); |
3185 | int rn = extract32(insn, 5, 5); | |
3186 | int imm3 = extract32(insn, 10, 3); | |
3187 | int option = extract32(insn, 13, 3); | |
3188 | int rm = extract32(insn, 16, 5); | |
3189 | bool setflags = extract32(insn, 29, 1); | |
3190 | bool sub_op = extract32(insn, 30, 1); | |
3191 | bool sf = extract32(insn, 31, 1); | |
3192 | ||
3193 | TCGv_i64 tcg_rm, tcg_rn; /* temps */ | |
3194 | TCGv_i64 tcg_rd; | |
3195 | TCGv_i64 tcg_result; | |
3196 | ||
3197 | if (imm3 > 4) { | |
3198 | unallocated_encoding(s); | |
3199 | return; | |
3200 | } | |
3201 | ||
3202 | /* non-flag setting ops may use SP */ | |
3203 | if (!setflags) { | |
b0ff21b4 AB |
3204 | tcg_rd = cpu_reg_sp(s, rd); |
3205 | } else { | |
b0ff21b4 AB |
3206 | tcg_rd = cpu_reg(s, rd); |
3207 | } | |
cf4ab1af | 3208 | tcg_rn = read_cpu_reg_sp(s, rn, sf); |
b0ff21b4 AB |
3209 | |
3210 | tcg_rm = read_cpu_reg(s, rm, sf); | |
3211 | ext_and_shift_reg(tcg_rm, tcg_rm, option, imm3); | |
3212 | ||
3213 | tcg_result = tcg_temp_new_i64(); | |
3214 | ||
3215 | if (!setflags) { | |
3216 | if (sub_op) { | |
3217 | tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm); | |
3218 | } else { | |
3219 | tcg_gen_add_i64(tcg_result, tcg_rn, tcg_rm); | |
3220 | } | |
3221 | } else { | |
3222 | if (sub_op) { | |
3223 | gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm); | |
3224 | } else { | |
3225 | gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm); | |
3226 | } | |
3227 | } | |
3228 | ||
3229 | if (sf) { | |
3230 | tcg_gen_mov_i64(tcg_rd, tcg_result); | |
3231 | } else { | |
3232 | tcg_gen_ext32u_i64(tcg_rd, tcg_result); | |
3233 | } | |
3234 | ||
3235 | tcg_temp_free_i64(tcg_result); | |
ad7ee8a2 CF |
3236 | } |
3237 | ||
b0ff21b4 AB |
3238 | /* |
3239 | * C3.5.2 Add/subtract (shifted register) | |
3240 | * | |
3241 | * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0 | |
3242 | * +--+--+--+-----------+-----+--+-------+---------+------+------+ | |
3243 | * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd | | |
3244 | * +--+--+--+-----------+-----+--+-------+---------+------+------+ | |
3245 | * | |
3246 | * sf: 0 -> 32bit, 1 -> 64bit | |
3247 | * op: 0 -> add , 1 -> sub | |
3248 | * S: 1 -> set flags | |
3249 | * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED | |
3250 | * imm6: Shift amount to apply to Rm before the add/sub | |
3251 | */ | |
ad7ee8a2 CF |
3252 | static void disas_add_sub_reg(DisasContext *s, uint32_t insn) |
3253 | { | |
b0ff21b4 AB |
3254 | int rd = extract32(insn, 0, 5); |
3255 | int rn = extract32(insn, 5, 5); | |
3256 | int imm6 = extract32(insn, 10, 6); | |
3257 | int rm = extract32(insn, 16, 5); | |
3258 | int shift_type = extract32(insn, 22, 2); | |
3259 | bool setflags = extract32(insn, 29, 1); | |
3260 | bool sub_op = extract32(insn, 30, 1); | |
3261 | bool sf = extract32(insn, 31, 1); | |
3262 | ||
3263 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
3264 | TCGv_i64 tcg_rn, tcg_rm; | |
3265 | TCGv_i64 tcg_result; | |
3266 | ||
3267 | if ((shift_type == 3) || (!sf && (imm6 > 31))) { | |
3268 | unallocated_encoding(s); | |
3269 | return; | |
3270 | } | |
3271 | ||
3272 | tcg_rn = read_cpu_reg(s, rn, sf); | |
3273 | tcg_rm = read_cpu_reg(s, rm, sf); | |
3274 | ||
3275 | shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, imm6); | |
3276 | ||
3277 | tcg_result = tcg_temp_new_i64(); | |
3278 | ||
3279 | if (!setflags) { | |
3280 | if (sub_op) { | |
3281 | tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm); | |
3282 | } else { | |
3283 | tcg_gen_add_i64(tcg_result, tcg_rn, tcg_rm); | |
3284 | } | |
3285 | } else { | |
3286 | if (sub_op) { | |
3287 | gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm); | |
3288 | } else { | |
3289 | gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm); | |
3290 | } | |
3291 | } | |
3292 | ||
3293 | if (sf) { | |
3294 | tcg_gen_mov_i64(tcg_rd, tcg_result); | |
3295 | } else { | |
3296 | tcg_gen_ext32u_i64(tcg_rd, tcg_result); | |
3297 | } | |
3298 | ||
3299 | tcg_temp_free_i64(tcg_result); | |
ad7ee8a2 CF |
3300 | } |
3301 | ||
52c8b9af AG |
3302 | /* C3.5.9 Data-processing (3 source) |
3303 | ||
3304 | 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0 | |
3305 | +--+------+-----------+------+------+----+------+------+------+ | |
3306 | |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd | | |
3307 | +--+------+-----------+------+------+----+------+------+------+ | |
3308 | ||
3309 | */ | |
ad7ee8a2 CF |
3310 | static void disas_data_proc_3src(DisasContext *s, uint32_t insn) |
3311 | { | |
52c8b9af AG |
3312 | int rd = extract32(insn, 0, 5); |
3313 | int rn = extract32(insn, 5, 5); | |
3314 | int ra = extract32(insn, 10, 5); | |
3315 | int rm = extract32(insn, 16, 5); | |
3316 | int op_id = (extract32(insn, 29, 3) << 4) | | |
3317 | (extract32(insn, 21, 3) << 1) | | |
3318 | extract32(insn, 15, 1); | |
3319 | bool sf = extract32(insn, 31, 1); | |
3320 | bool is_sub = extract32(op_id, 0, 1); | |
3321 | bool is_high = extract32(op_id, 2, 1); | |
3322 | bool is_signed = false; | |
3323 | TCGv_i64 tcg_op1; | |
3324 | TCGv_i64 tcg_op2; | |
3325 | TCGv_i64 tcg_tmp; | |
3326 | ||
3327 | /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */ | |
3328 | switch (op_id) { | |
3329 | case 0x42: /* SMADDL */ | |
3330 | case 0x43: /* SMSUBL */ | |
3331 | case 0x44: /* SMULH */ | |
3332 | is_signed = true; | |
3333 | break; | |
3334 | case 0x0: /* MADD (32bit) */ | |
3335 | case 0x1: /* MSUB (32bit) */ | |
3336 | case 0x40: /* MADD (64bit) */ | |
3337 | case 0x41: /* MSUB (64bit) */ | |
3338 | case 0x4a: /* UMADDL */ | |
3339 | case 0x4b: /* UMSUBL */ | |
3340 | case 0x4c: /* UMULH */ | |
3341 | break; | |
3342 | default: | |
3343 | unallocated_encoding(s); | |
3344 | return; | |
3345 | } | |
3346 | ||
3347 | if (is_high) { | |
3348 | TCGv_i64 low_bits = tcg_temp_new_i64(); /* low bits discarded */ | |
3349 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
3350 | TCGv_i64 tcg_rn = cpu_reg(s, rn); | |
3351 | TCGv_i64 tcg_rm = cpu_reg(s, rm); | |
3352 | ||
3353 | if (is_signed) { | |
3354 | tcg_gen_muls2_i64(low_bits, tcg_rd, tcg_rn, tcg_rm); | |
3355 | } else { | |
3356 | tcg_gen_mulu2_i64(low_bits, tcg_rd, tcg_rn, tcg_rm); | |
3357 | } | |
3358 | ||
3359 | tcg_temp_free_i64(low_bits); | |
3360 | return; | |
3361 | } | |
3362 | ||
3363 | tcg_op1 = tcg_temp_new_i64(); | |
3364 | tcg_op2 = tcg_temp_new_i64(); | |
3365 | tcg_tmp = tcg_temp_new_i64(); | |
3366 | ||
3367 | if (op_id < 0x42) { | |
3368 | tcg_gen_mov_i64(tcg_op1, cpu_reg(s, rn)); | |
3369 | tcg_gen_mov_i64(tcg_op2, cpu_reg(s, rm)); | |
3370 | } else { | |
3371 | if (is_signed) { | |
3372 | tcg_gen_ext32s_i64(tcg_op1, cpu_reg(s, rn)); | |
3373 | tcg_gen_ext32s_i64(tcg_op2, cpu_reg(s, rm)); | |
3374 | } else { | |
3375 | tcg_gen_ext32u_i64(tcg_op1, cpu_reg(s, rn)); | |
3376 | tcg_gen_ext32u_i64(tcg_op2, cpu_reg(s, rm)); | |
3377 | } | |
3378 | } | |
3379 | ||
3380 | if (ra == 31 && !is_sub) { | |
3381 | /* Special-case MADD with rA == XZR; it is the standard MUL alias */ | |
3382 | tcg_gen_mul_i64(cpu_reg(s, rd), tcg_op1, tcg_op2); | |
3383 | } else { | |
3384 | tcg_gen_mul_i64(tcg_tmp, tcg_op1, tcg_op2); | |
3385 | if (is_sub) { | |
3386 | tcg_gen_sub_i64(cpu_reg(s, rd), cpu_reg(s, ra), tcg_tmp); | |
3387 | } else { | |
3388 | tcg_gen_add_i64(cpu_reg(s, rd), cpu_reg(s, ra), tcg_tmp); | |
3389 | } | |
3390 | } | |
3391 | ||
3392 | if (!sf) { | |
3393 | tcg_gen_ext32u_i64(cpu_reg(s, rd), cpu_reg(s, rd)); | |
3394 | } | |
3395 | ||
3396 | tcg_temp_free_i64(tcg_op1); | |
3397 | tcg_temp_free_i64(tcg_op2); | |
3398 | tcg_temp_free_i64(tcg_tmp); | |
ad7ee8a2 CF |
3399 | } |
3400 | ||
643dbb07 CF |
3401 | /* C3.5.3 - Add/subtract (with carry) |
3402 | * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0 | |
3403 | * +--+--+--+------------------------+------+---------+------+-----+ | |
3404 | * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd | | |
3405 | * +--+--+--+------------------------+------+---------+------+-----+ | |
3406 | * [000000] | |
3407 | */ | |
3408 | ||
ad7ee8a2 CF |
3409 | static void disas_adc_sbc(DisasContext *s, uint32_t insn) |
3410 | { | |
643dbb07 CF |
3411 | unsigned int sf, op, setflags, rm, rn, rd; |
3412 | TCGv_i64 tcg_y, tcg_rn, tcg_rd; | |
3413 | ||
3414 | if (extract32(insn, 10, 6) != 0) { | |
3415 | unallocated_encoding(s); | |
3416 | return; | |
3417 | } | |
3418 | ||
3419 | sf = extract32(insn, 31, 1); | |
3420 | op = extract32(insn, 30, 1); | |
3421 | setflags = extract32(insn, 29, 1); | |
3422 | rm = extract32(insn, 16, 5); | |
3423 | rn = extract32(insn, 5, 5); | |
3424 | rd = extract32(insn, 0, 5); | |
3425 | ||
3426 | tcg_rd = cpu_reg(s, rd); | |
3427 | tcg_rn = cpu_reg(s, rn); | |
3428 | ||
3429 | if (op) { | |
3430 | tcg_y = new_tmp_a64(s); | |
3431 | tcg_gen_not_i64(tcg_y, cpu_reg(s, rm)); | |
3432 | } else { | |
3433 | tcg_y = cpu_reg(s, rm); | |
3434 | } | |
3435 | ||
3436 | if (setflags) { | |
3437 | gen_adc_CC(sf, tcg_rd, tcg_rn, tcg_y); | |
3438 | } else { | |
3439 | gen_adc(sf, tcg_rd, tcg_rn, tcg_y); | |
3440 | } | |
ad7ee8a2 CF |
3441 | } |
3442 | ||
750813cf CF |
3443 | /* C3.5.4 - C3.5.5 Conditional compare (immediate / register) |
3444 | * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0 | |
3445 | * +--+--+--+------------------------+--------+------+----+--+------+--+-----+ | |
3446 | * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv | | |
3447 | * +--+--+--+------------------------+--------+------+----+--+------+--+-----+ | |
3448 | * [1] y [0] [0] | |
3449 | */ | |
3450 | static void disas_cc(DisasContext *s, uint32_t insn) | |
ad7ee8a2 | 3451 | { |
750813cf CF |
3452 | unsigned int sf, op, y, cond, rn, nzcv, is_imm; |
3453 | int label_continue = -1; | |
3454 | TCGv_i64 tcg_tmp, tcg_y, tcg_rn; | |
ad7ee8a2 | 3455 | |
750813cf CF |
3456 | if (!extract32(insn, 29, 1)) { |
3457 | unallocated_encoding(s); | |
3458 | return; | |
3459 | } | |
3460 | if (insn & (1 << 10 | 1 << 4)) { | |
3461 | unallocated_encoding(s); | |
3462 | return; | |
3463 | } | |
3464 | sf = extract32(insn, 31, 1); | |
3465 | op = extract32(insn, 30, 1); | |
3466 | is_imm = extract32(insn, 11, 1); | |
3467 | y = extract32(insn, 16, 5); /* y = rm (reg) or imm5 (imm) */ | |
3468 | cond = extract32(insn, 12, 4); | |
3469 | rn = extract32(insn, 5, 5); | |
3470 | nzcv = extract32(insn, 0, 4); | |
3471 | ||
3472 | if (cond < 0x0e) { /* not always */ | |
3473 | int label_match = gen_new_label(); | |
3474 | label_continue = gen_new_label(); | |
3475 | arm_gen_test_cc(cond, label_match); | |
3476 | /* nomatch: */ | |
3477 | tcg_tmp = tcg_temp_new_i64(); | |
3478 | tcg_gen_movi_i64(tcg_tmp, nzcv << 28); | |
3479 | gen_set_nzcv(tcg_tmp); | |
3480 | tcg_temp_free_i64(tcg_tmp); | |
3481 | tcg_gen_br(label_continue); | |
3482 | gen_set_label(label_match); | |
3483 | } | |
3484 | /* match, or condition is always */ | |
3485 | if (is_imm) { | |
3486 | tcg_y = new_tmp_a64(s); | |
3487 | tcg_gen_movi_i64(tcg_y, y); | |
3488 | } else { | |
3489 | tcg_y = cpu_reg(s, y); | |
3490 | } | |
3491 | tcg_rn = cpu_reg(s, rn); | |
3492 | ||
3493 | tcg_tmp = tcg_temp_new_i64(); | |
3494 | if (op) { | |
3495 | gen_sub_CC(sf, tcg_tmp, tcg_rn, tcg_y); | |
3496 | } else { | |
3497 | gen_add_CC(sf, tcg_tmp, tcg_rn, tcg_y); | |
3498 | } | |
3499 | tcg_temp_free_i64(tcg_tmp); | |
3500 | ||
3501 | if (cond < 0x0e) { /* continue */ | |
3502 | gen_set_label(label_continue); | |
3503 | } | |
ad7ee8a2 CF |
3504 | } |
3505 | ||
e952d8c7 CF |
3506 | /* C3.5.6 Conditional select |
3507 | * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0 | |
3508 | * +----+----+---+-----------------+------+------+-----+------+------+ | |
3509 | * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd | | |
3510 | * +----+----+---+-----------------+------+------+-----+------+------+ | |
3511 | */ | |
ad7ee8a2 CF |
3512 | static void disas_cond_select(DisasContext *s, uint32_t insn) |
3513 | { | |
e952d8c7 CF |
3514 | unsigned int sf, else_inv, rm, cond, else_inc, rn, rd; |
3515 | TCGv_i64 tcg_rd, tcg_src; | |
3516 | ||
3517 | if (extract32(insn, 29, 1) || extract32(insn, 11, 1)) { | |
3518 | /* S == 1 or op2<1> == 1 */ | |
3519 | unallocated_encoding(s); | |
3520 | return; | |
3521 | } | |
3522 | sf = extract32(insn, 31, 1); | |
3523 | else_inv = extract32(insn, 30, 1); | |
3524 | rm = extract32(insn, 16, 5); | |
3525 | cond = extract32(insn, 12, 4); | |
3526 | else_inc = extract32(insn, 10, 1); | |
3527 | rn = extract32(insn, 5, 5); | |
3528 | rd = extract32(insn, 0, 5); | |
3529 | ||
3530 | if (rd == 31) { | |
3531 | /* silly no-op write; until we use movcond we must special-case | |
3532 | * this to avoid a dead temporary across basic blocks. | |
3533 | */ | |
3534 | return; | |
3535 | } | |
3536 | ||
3537 | tcg_rd = cpu_reg(s, rd); | |
3538 | ||
3539 | if (cond >= 0x0e) { /* condition "always" */ | |
3540 | tcg_src = read_cpu_reg(s, rn, sf); | |
3541 | tcg_gen_mov_i64(tcg_rd, tcg_src); | |
3542 | } else { | |
3543 | /* OPTME: we could use movcond here, at the cost of duplicating | |
3544 | * a lot of the arm_gen_test_cc() logic. | |
3545 | */ | |
3546 | int label_match = gen_new_label(); | |
3547 | int label_continue = gen_new_label(); | |
3548 | ||
3549 | arm_gen_test_cc(cond, label_match); | |
3550 | /* nomatch: */ | |
3551 | tcg_src = cpu_reg(s, rm); | |
3552 | ||
3553 | if (else_inv && else_inc) { | |
3554 | tcg_gen_neg_i64(tcg_rd, tcg_src); | |
3555 | } else if (else_inv) { | |
3556 | tcg_gen_not_i64(tcg_rd, tcg_src); | |
3557 | } else if (else_inc) { | |
3558 | tcg_gen_addi_i64(tcg_rd, tcg_src, 1); | |
3559 | } else { | |
3560 | tcg_gen_mov_i64(tcg_rd, tcg_src); | |
3561 | } | |
3562 | if (!sf) { | |
3563 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
3564 | } | |
3565 | tcg_gen_br(label_continue); | |
3566 | /* match: */ | |
3567 | gen_set_label(label_match); | |
3568 | tcg_src = read_cpu_reg(s, rn, sf); | |
3569 | tcg_gen_mov_i64(tcg_rd, tcg_src); | |
3570 | /* continue: */ | |
3571 | gen_set_label(label_continue); | |
3572 | } | |
ad7ee8a2 CF |
3573 | } |
3574 | ||
680ead21 CF |
3575 | static void handle_clz(DisasContext *s, unsigned int sf, |
3576 | unsigned int rn, unsigned int rd) | |
3577 | { | |
3578 | TCGv_i64 tcg_rd, tcg_rn; | |
3579 | tcg_rd = cpu_reg(s, rd); | |
3580 | tcg_rn = cpu_reg(s, rn); | |
3581 | ||
3582 | if (sf) { | |
3583 | gen_helper_clz64(tcg_rd, tcg_rn); | |
3584 | } else { | |
3585 | TCGv_i32 tcg_tmp32 = tcg_temp_new_i32(); | |
3586 | tcg_gen_trunc_i64_i32(tcg_tmp32, tcg_rn); | |
3587 | gen_helper_clz(tcg_tmp32, tcg_tmp32); | |
3588 | tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); | |
3589 | tcg_temp_free_i32(tcg_tmp32); | |
3590 | } | |
3591 | } | |
3592 | ||
e80c5020 CF |
3593 | static void handle_cls(DisasContext *s, unsigned int sf, |
3594 | unsigned int rn, unsigned int rd) | |
3595 | { | |
3596 | TCGv_i64 tcg_rd, tcg_rn; | |
3597 | tcg_rd = cpu_reg(s, rd); | |
3598 | tcg_rn = cpu_reg(s, rn); | |
3599 | ||
3600 | if (sf) { | |
3601 | gen_helper_cls64(tcg_rd, tcg_rn); | |
3602 | } else { | |
3603 | TCGv_i32 tcg_tmp32 = tcg_temp_new_i32(); | |
3604 | tcg_gen_trunc_i64_i32(tcg_tmp32, tcg_rn); | |
3605 | gen_helper_cls32(tcg_tmp32, tcg_tmp32); | |
3606 | tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); | |
3607 | tcg_temp_free_i32(tcg_tmp32); | |
3608 | } | |
3609 | } | |
3610 | ||
82e14b02 AG |
3611 | static void handle_rbit(DisasContext *s, unsigned int sf, |
3612 | unsigned int rn, unsigned int rd) | |
3613 | { | |
3614 | TCGv_i64 tcg_rd, tcg_rn; | |
3615 | tcg_rd = cpu_reg(s, rd); | |
3616 | tcg_rn = cpu_reg(s, rn); | |
3617 | ||
3618 | if (sf) { | |
3619 | gen_helper_rbit64(tcg_rd, tcg_rn); | |
3620 | } else { | |
3621 | TCGv_i32 tcg_tmp32 = tcg_temp_new_i32(); | |
3622 | tcg_gen_trunc_i64_i32(tcg_tmp32, tcg_rn); | |
3623 | gen_helper_rbit(tcg_tmp32, tcg_tmp32); | |
3624 | tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); | |
3625 | tcg_temp_free_i32(tcg_tmp32); | |
3626 | } | |
3627 | } | |
3628 | ||
45323209 CF |
3629 | /* C5.6.149 REV with sf==1, opcode==3 ("REV64") */ |
3630 | static void handle_rev64(DisasContext *s, unsigned int sf, | |
3631 | unsigned int rn, unsigned int rd) | |
3632 | { | |
3633 | if (!sf) { | |
3634 | unallocated_encoding(s); | |
3635 | return; | |
3636 | } | |
3637 | tcg_gen_bswap64_i64(cpu_reg(s, rd), cpu_reg(s, rn)); | |
3638 | } | |
3639 | ||
3640 | /* C5.6.149 REV with sf==0, opcode==2 | |
3641 | * C5.6.151 REV32 (sf==1, opcode==2) | |
3642 | */ | |
3643 | static void handle_rev32(DisasContext *s, unsigned int sf, | |
3644 | unsigned int rn, unsigned int rd) | |
3645 | { | |
3646 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
3647 | ||
3648 | if (sf) { | |
3649 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
3650 | TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf); | |
3651 | ||
3652 | /* bswap32_i64 requires zero high word */ | |
3653 | tcg_gen_ext32u_i64(tcg_tmp, tcg_rn); | |
3654 | tcg_gen_bswap32_i64(tcg_rd, tcg_tmp); | |
3655 | tcg_gen_shri_i64(tcg_tmp, tcg_rn, 32); | |
3656 | tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp); | |
3657 | tcg_gen_concat32_i64(tcg_rd, tcg_rd, tcg_tmp); | |
3658 | ||
3659 | tcg_temp_free_i64(tcg_tmp); | |
3660 | } else { | |
3661 | tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rn)); | |
3662 | tcg_gen_bswap32_i64(tcg_rd, tcg_rd); | |
3663 | } | |
3664 | } | |
3665 | ||
3666 | /* C5.6.150 REV16 (opcode==1) */ | |
3667 | static void handle_rev16(DisasContext *s, unsigned int sf, | |
3668 | unsigned int rn, unsigned int rd) | |
3669 | { | |
3670 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
3671 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
3672 | TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf); | |
3673 | ||
3674 | tcg_gen_andi_i64(tcg_tmp, tcg_rn, 0xffff); | |
3675 | tcg_gen_bswap16_i64(tcg_rd, tcg_tmp); | |
3676 | ||
3677 | tcg_gen_shri_i64(tcg_tmp, tcg_rn, 16); | |
3678 | tcg_gen_andi_i64(tcg_tmp, tcg_tmp, 0xffff); | |
3679 | tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp); | |
3680 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 16, 16); | |
3681 | ||
3682 | if (sf) { | |
3683 | tcg_gen_shri_i64(tcg_tmp, tcg_rn, 32); | |
3684 | tcg_gen_andi_i64(tcg_tmp, tcg_tmp, 0xffff); | |
3685 | tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp); | |
3686 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 32, 16); | |
3687 | ||
3688 | tcg_gen_shri_i64(tcg_tmp, tcg_rn, 48); | |
3689 | tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp); | |
3690 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 48, 16); | |
3691 | } | |
3692 | ||
3693 | tcg_temp_free_i64(tcg_tmp); | |
3694 | } | |
3695 | ||
680ead21 CF |
3696 | /* C3.5.7 Data-processing (1 source) |
3697 | * 31 30 29 28 21 20 16 15 10 9 5 4 0 | |
3698 | * +----+---+---+-----------------+---------+--------+------+------+ | |
3699 | * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd | | |
3700 | * +----+---+---+-----------------+---------+--------+------+------+ | |
3701 | */ | |
ad7ee8a2 CF |
3702 | static void disas_data_proc_1src(DisasContext *s, uint32_t insn) |
3703 | { | |
680ead21 CF |
3704 | unsigned int sf, opcode, rn, rd; |
3705 | ||
3706 | if (extract32(insn, 29, 1) || extract32(insn, 16, 5)) { | |
3707 | unallocated_encoding(s); | |
3708 | return; | |
3709 | } | |
3710 | ||
3711 | sf = extract32(insn, 31, 1); | |
3712 | opcode = extract32(insn, 10, 6); | |
3713 | rn = extract32(insn, 5, 5); | |
3714 | rd = extract32(insn, 0, 5); | |
3715 | ||
3716 | switch (opcode) { | |
3717 | case 0: /* RBIT */ | |
82e14b02 AG |
3718 | handle_rbit(s, sf, rn, rd); |
3719 | break; | |
680ead21 | 3720 | case 1: /* REV16 */ |
45323209 CF |
3721 | handle_rev16(s, sf, rn, rd); |
3722 | break; | |
680ead21 | 3723 | case 2: /* REV32 */ |
45323209 CF |
3724 | handle_rev32(s, sf, rn, rd); |
3725 | break; | |
680ead21 | 3726 | case 3: /* REV64 */ |
45323209 | 3727 | handle_rev64(s, sf, rn, rd); |
680ead21 CF |
3728 | break; |
3729 | case 4: /* CLZ */ | |
3730 | handle_clz(s, sf, rn, rd); | |
3731 | break; | |
3732 | case 5: /* CLS */ | |
e80c5020 | 3733 | handle_cls(s, sf, rn, rd); |
680ead21 CF |
3734 | break; |
3735 | } | |
ad7ee8a2 CF |
3736 | } |
3737 | ||
8220e911 AG |
3738 | static void handle_div(DisasContext *s, bool is_signed, unsigned int sf, |
3739 | unsigned int rm, unsigned int rn, unsigned int rd) | |
3740 | { | |
3741 | TCGv_i64 tcg_n, tcg_m, tcg_rd; | |
3742 | tcg_rd = cpu_reg(s, rd); | |
3743 | ||
3744 | if (!sf && is_signed) { | |
3745 | tcg_n = new_tmp_a64(s); | |
3746 | tcg_m = new_tmp_a64(s); | |
3747 | tcg_gen_ext32s_i64(tcg_n, cpu_reg(s, rn)); | |
3748 | tcg_gen_ext32s_i64(tcg_m, cpu_reg(s, rm)); | |
3749 | } else { | |
3750 | tcg_n = read_cpu_reg(s, rn, sf); | |
3751 | tcg_m = read_cpu_reg(s, rm, sf); | |
3752 | } | |
3753 | ||
3754 | if (is_signed) { | |
3755 | gen_helper_sdiv64(tcg_rd, tcg_n, tcg_m); | |
3756 | } else { | |
3757 | gen_helper_udiv64(tcg_rd, tcg_n, tcg_m); | |
3758 | } | |
3759 | ||
3760 | if (!sf) { /* zero extend final result */ | |
3761 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
3762 | } | |
3763 | } | |
3764 | ||
6c1adc91 AG |
3765 | /* C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV */ |
3766 | static void handle_shift_reg(DisasContext *s, | |
3767 | enum a64_shift_type shift_type, unsigned int sf, | |
3768 | unsigned int rm, unsigned int rn, unsigned int rd) | |
3769 | { | |
3770 | TCGv_i64 tcg_shift = tcg_temp_new_i64(); | |
3771 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
3772 | TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf); | |
3773 | ||
3774 | tcg_gen_andi_i64(tcg_shift, cpu_reg(s, rm), sf ? 63 : 31); | |
3775 | shift_reg(tcg_rd, tcg_rn, sf, shift_type, tcg_shift); | |
3776 | tcg_temp_free_i64(tcg_shift); | |
3777 | } | |
3778 | ||
130f2e7d PM |
3779 | /* CRC32[BHWX], CRC32C[BHWX] */ |
3780 | static void handle_crc32(DisasContext *s, | |
3781 | unsigned int sf, unsigned int sz, bool crc32c, | |
3782 | unsigned int rm, unsigned int rn, unsigned int rd) | |
3783 | { | |
3784 | TCGv_i64 tcg_acc, tcg_val; | |
3785 | TCGv_i32 tcg_bytes; | |
3786 | ||
3787 | if (!arm_dc_feature(s, ARM_FEATURE_CRC) | |
3788 | || (sf == 1 && sz != 3) | |
3789 | || (sf == 0 && sz == 3)) { | |
3790 | unallocated_encoding(s); | |
3791 | return; | |
3792 | } | |
3793 | ||
3794 | if (sz == 3) { | |
3795 | tcg_val = cpu_reg(s, rm); | |
3796 | } else { | |
3797 | uint64_t mask; | |
3798 | switch (sz) { | |
3799 | case 0: | |
3800 | mask = 0xFF; | |
3801 | break; | |
3802 | case 1: | |
3803 | mask = 0xFFFF; | |
3804 | break; | |
3805 | case 2: | |
3806 | mask = 0xFFFFFFFF; | |
3807 | break; | |
3808 | default: | |
3809 | g_assert_not_reached(); | |
3810 | } | |
3811 | tcg_val = new_tmp_a64(s); | |
3812 | tcg_gen_andi_i64(tcg_val, cpu_reg(s, rm), mask); | |
3813 | } | |
3814 | ||
3815 | tcg_acc = cpu_reg(s, rn); | |
3816 | tcg_bytes = tcg_const_i32(1 << sz); | |
3817 | ||
3818 | if (crc32c) { | |
3819 | gen_helper_crc32c_64(cpu_reg(s, rd), tcg_acc, tcg_val, tcg_bytes); | |
3820 | } else { | |
3821 | gen_helper_crc32_64(cpu_reg(s, rd), tcg_acc, tcg_val, tcg_bytes); | |
3822 | } | |
3823 | ||
3824 | tcg_temp_free_i32(tcg_bytes); | |
3825 | } | |
3826 | ||
8220e911 AG |
3827 | /* C3.5.8 Data-processing (2 source) |
3828 | * 31 30 29 28 21 20 16 15 10 9 5 4 0 | |
3829 | * +----+---+---+-----------------+------+--------+------+------+ | |
3830 | * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd | | |
3831 | * +----+---+---+-----------------+------+--------+------+------+ | |
3832 | */ | |
ad7ee8a2 CF |
3833 | static void disas_data_proc_2src(DisasContext *s, uint32_t insn) |
3834 | { | |
8220e911 AG |
3835 | unsigned int sf, rm, opcode, rn, rd; |
3836 | sf = extract32(insn, 31, 1); | |
3837 | rm = extract32(insn, 16, 5); | |
3838 | opcode = extract32(insn, 10, 6); | |
3839 | rn = extract32(insn, 5, 5); | |
3840 | rd = extract32(insn, 0, 5); | |
3841 | ||
3842 | if (extract32(insn, 29, 1)) { | |
3843 | unallocated_encoding(s); | |
3844 | return; | |
3845 | } | |
3846 | ||
3847 | switch (opcode) { | |
3848 | case 2: /* UDIV */ | |
3849 | handle_div(s, false, sf, rm, rn, rd); | |
3850 | break; | |
3851 | case 3: /* SDIV */ | |
3852 | handle_div(s, true, sf, rm, rn, rd); | |
3853 | break; | |
3854 | case 8: /* LSLV */ | |
6c1adc91 AG |
3855 | handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd); |
3856 | break; | |
8220e911 | 3857 | case 9: /* LSRV */ |
6c1adc91 AG |
3858 | handle_shift_reg(s, A64_SHIFT_TYPE_LSR, sf, rm, rn, rd); |
3859 | break; | |
8220e911 | 3860 | case 10: /* ASRV */ |
6c1adc91 AG |
3861 | handle_shift_reg(s, A64_SHIFT_TYPE_ASR, sf, rm, rn, rd); |
3862 | break; | |
8220e911 | 3863 | case 11: /* RORV */ |
6c1adc91 AG |
3864 | handle_shift_reg(s, A64_SHIFT_TYPE_ROR, sf, rm, rn, rd); |
3865 | break; | |
8220e911 AG |
3866 | case 16: |
3867 | case 17: | |
3868 | case 18: | |
3869 | case 19: | |
3870 | case 20: | |
3871 | case 21: | |
3872 | case 22: | |
3873 | case 23: /* CRC32 */ | |
130f2e7d PM |
3874 | { |
3875 | int sz = extract32(opcode, 0, 2); | |
3876 | bool crc32c = extract32(opcode, 2, 1); | |
3877 | handle_crc32(s, sf, sz, crc32c, rm, rn, rd); | |
8220e911 | 3878 | break; |
130f2e7d | 3879 | } |
8220e911 AG |
3880 | default: |
3881 | unallocated_encoding(s); | |
3882 | break; | |
3883 | } | |
ad7ee8a2 CF |
3884 | } |
3885 | ||
3886 | /* C3.5 Data processing - register */ | |
3887 | static void disas_data_proc_reg(DisasContext *s, uint32_t insn) | |
3888 | { | |
3889 | switch (extract32(insn, 24, 5)) { | |
3890 | case 0x0a: /* Logical (shifted register) */ | |
3891 | disas_logic_reg(s, insn); | |
3892 | break; | |
3893 | case 0x0b: /* Add/subtract */ | |
3894 | if (insn & (1 << 21)) { /* (extended register) */ | |
3895 | disas_add_sub_ext_reg(s, insn); | |
3896 | } else { | |
3897 | disas_add_sub_reg(s, insn); | |
3898 | } | |
3899 | break; | |
3900 | case 0x1b: /* Data-processing (3 source) */ | |
3901 | disas_data_proc_3src(s, insn); | |
3902 | break; | |
3903 | case 0x1a: | |
3904 | switch (extract32(insn, 21, 3)) { | |
3905 | case 0x0: /* Add/subtract (with carry) */ | |
3906 | disas_adc_sbc(s, insn); | |
3907 | break; | |
3908 | case 0x2: /* Conditional compare */ | |
750813cf | 3909 | disas_cc(s, insn); /* both imm and reg forms */ |
ad7ee8a2 CF |
3910 | break; |
3911 | case 0x4: /* Conditional select */ | |
3912 | disas_cond_select(s, insn); | |
3913 | break; | |
3914 | case 0x6: /* Data-processing */ | |
3915 | if (insn & (1 << 30)) { /* (1 source) */ | |
3916 | disas_data_proc_1src(s, insn); | |
3917 | } else { /* (2 source) */ | |
3918 | disas_data_proc_2src(s, insn); | |
3919 | } | |
3920 | break; | |
3921 | default: | |
3922 | unallocated_encoding(s); | |
3923 | break; | |
3924 | } | |
3925 | break; | |
3926 | default: | |
3927 | unallocated_encoding(s); | |
3928 | break; | |
3929 | } | |
3930 | } | |
3931 | ||
da7dafe7 CF |
3932 | static void handle_fp_compare(DisasContext *s, bool is_double, |
3933 | unsigned int rn, unsigned int rm, | |
3934 | bool cmp_with_zero, bool signal_all_nans) | |
3935 | { | |
3936 | TCGv_i64 tcg_flags = tcg_temp_new_i64(); | |
3937 | TCGv_ptr fpst = get_fpstatus_ptr(); | |
3938 | ||
3939 | if (is_double) { | |
3940 | TCGv_i64 tcg_vn, tcg_vm; | |
3941 | ||
3942 | tcg_vn = read_fp_dreg(s, rn); | |
3943 | if (cmp_with_zero) { | |
3944 | tcg_vm = tcg_const_i64(0); | |
3945 | } else { | |
3946 | tcg_vm = read_fp_dreg(s, rm); | |
3947 | } | |
3948 | if (signal_all_nans) { | |
3949 | gen_helper_vfp_cmped_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
3950 | } else { | |
3951 | gen_helper_vfp_cmpd_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
3952 | } | |
3953 | tcg_temp_free_i64(tcg_vn); | |
3954 | tcg_temp_free_i64(tcg_vm); | |
3955 | } else { | |
3956 | TCGv_i32 tcg_vn, tcg_vm; | |
3957 | ||
3958 | tcg_vn = read_fp_sreg(s, rn); | |
3959 | if (cmp_with_zero) { | |
3960 | tcg_vm = tcg_const_i32(0); | |
3961 | } else { | |
3962 | tcg_vm = read_fp_sreg(s, rm); | |
3963 | } | |
3964 | if (signal_all_nans) { | |
3965 | gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
3966 | } else { | |
3967 | gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | |
3968 | } | |
3969 | tcg_temp_free_i32(tcg_vn); | |
3970 | tcg_temp_free_i32(tcg_vm); | |
3971 | } | |
3972 | ||
3973 | tcg_temp_free_ptr(fpst); | |
3974 | ||
3975 | gen_set_nzcv(tcg_flags); | |
3976 | ||
3977 | tcg_temp_free_i64(tcg_flags); | |
3978 | } | |
3979 | ||
faa0ba46 PM |
3980 | /* C3.6.22 Floating point compare |
3981 | * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0 | |
3982 | * +---+---+---+-----------+------+---+------+-----+---------+------+-------+ | |
3983 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 | | |
3984 | * +---+---+---+-----------+------+---+------+-----+---------+------+-------+ | |
3985 | */ | |
3986 | static void disas_fp_compare(DisasContext *s, uint32_t insn) | |
3987 | { | |
da7dafe7 CF |
3988 | unsigned int mos, type, rm, op, rn, opc, op2r; |
3989 | ||
3990 | mos = extract32(insn, 29, 3); | |
3991 | type = extract32(insn, 22, 2); /* 0 = single, 1 = double */ | |
3992 | rm = extract32(insn, 16, 5); | |
3993 | op = extract32(insn, 14, 2); | |
3994 | rn = extract32(insn, 5, 5); | |
3995 | opc = extract32(insn, 3, 2); | |
3996 | op2r = extract32(insn, 0, 3); | |
3997 | ||
3998 | if (mos || op || op2r || type > 1) { | |
3999 | unallocated_encoding(s); | |
4000 | return; | |
4001 | } | |
4002 | ||
8c6afa6a PM |
4003 | if (!fp_access_check(s)) { |
4004 | return; | |
4005 | } | |
4006 | ||
da7dafe7 | 4007 | handle_fp_compare(s, type, rn, rm, opc & 1, opc & 2); |
faa0ba46 PM |
4008 | } |
4009 | ||
4010 | /* C3.6.23 Floating point conditional compare | |
4011 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0 | |
4012 | * +---+---+---+-----------+------+---+------+------+-----+------+----+------+ | |
4013 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv | | |
4014 | * +---+---+---+-----------+------+---+------+------+-----+------+----+------+ | |
4015 | */ | |
4016 | static void disas_fp_ccomp(DisasContext *s, uint32_t insn) | |
4017 | { | |
513f1d76 CF |
4018 | unsigned int mos, type, rm, cond, rn, op, nzcv; |
4019 | TCGv_i64 tcg_flags; | |
4020 | int label_continue = -1; | |
4021 | ||
4022 | mos = extract32(insn, 29, 3); | |
4023 | type = extract32(insn, 22, 2); /* 0 = single, 1 = double */ | |
4024 | rm = extract32(insn, 16, 5); | |
4025 | cond = extract32(insn, 12, 4); | |
4026 | rn = extract32(insn, 5, 5); | |
4027 | op = extract32(insn, 4, 1); | |
4028 | nzcv = extract32(insn, 0, 4); | |
4029 | ||
4030 | if (mos || type > 1) { | |
4031 | unallocated_encoding(s); | |
4032 | return; | |
4033 | } | |
4034 | ||
8c6afa6a PM |
4035 | if (!fp_access_check(s)) { |
4036 | return; | |
4037 | } | |
4038 | ||
513f1d76 CF |
4039 | if (cond < 0x0e) { /* not always */ |
4040 | int label_match = gen_new_label(); | |
4041 | label_continue = gen_new_label(); | |
4042 | arm_gen_test_cc(cond, label_match); | |
4043 | /* nomatch: */ | |
4044 | tcg_flags = tcg_const_i64(nzcv << 28); | |
4045 | gen_set_nzcv(tcg_flags); | |
4046 | tcg_temp_free_i64(tcg_flags); | |
4047 | tcg_gen_br(label_continue); | |
4048 | gen_set_label(label_match); | |
4049 | } | |
4050 | ||
4051 | handle_fp_compare(s, type, rn, rm, false, op); | |
4052 | ||
4053 | if (cond < 0x0e) { | |
4054 | gen_set_label(label_continue); | |
4055 | } | |
faa0ba46 PM |
4056 | } |
4057 | ||
5640ff62 CF |
4058 | /* copy src FP register to dst FP register; type specifies single or double */ |
4059 | static void gen_mov_fp2fp(DisasContext *s, int type, int dst, int src) | |
4060 | { | |
4061 | if (type) { | |
4062 | TCGv_i64 v = read_fp_dreg(s, src); | |
4063 | write_fp_dreg(s, dst, v); | |
4064 | tcg_temp_free_i64(v); | |
4065 | } else { | |
4066 | TCGv_i32 v = read_fp_sreg(s, src); | |
4067 | write_fp_sreg(s, dst, v); | |
4068 | tcg_temp_free_i32(v); | |
4069 | } | |
4070 | } | |
4071 | ||
faa0ba46 PM |
4072 | /* C3.6.24 Floating point conditional select |
4073 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 | |
4074 | * +---+---+---+-----------+------+---+------+------+-----+------+------+ | |
4075 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd | | |
4076 | * +---+---+---+-----------+------+---+------+------+-----+------+------+ | |
4077 | */ | |
4078 | static void disas_fp_csel(DisasContext *s, uint32_t insn) | |
4079 | { | |
5640ff62 CF |
4080 | unsigned int mos, type, rm, cond, rn, rd; |
4081 | int label_continue = -1; | |
4082 | ||
4083 | mos = extract32(insn, 29, 3); | |
4084 | type = extract32(insn, 22, 2); /* 0 = single, 1 = double */ | |
4085 | rm = extract32(insn, 16, 5); | |
4086 | cond = extract32(insn, 12, 4); | |
4087 | rn = extract32(insn, 5, 5); | |
4088 | rd = extract32(insn, 0, 5); | |
4089 | ||
4090 | if (mos || type > 1) { | |
4091 | unallocated_encoding(s); | |
4092 | return; | |
4093 | } | |
4094 | ||
8c6afa6a PM |
4095 | if (!fp_access_check(s)) { |
4096 | return; | |
4097 | } | |
4098 | ||
5640ff62 CF |
4099 | if (cond < 0x0e) { /* not always */ |
4100 | int label_match = gen_new_label(); | |
4101 | label_continue = gen_new_label(); | |
4102 | arm_gen_test_cc(cond, label_match); | |
4103 | /* nomatch: */ | |
4104 | gen_mov_fp2fp(s, type, rd, rm); | |
4105 | tcg_gen_br(label_continue); | |
4106 | gen_set_label(label_match); | |
4107 | } | |
4108 | ||
4109 | gen_mov_fp2fp(s, type, rd, rn); | |
4110 | ||
4111 | if (cond < 0x0e) { /* continue */ | |
4112 | gen_set_label(label_continue); | |
4113 | } | |
faa0ba46 PM |
4114 | } |
4115 | ||
d9b0848d PM |
4116 | /* C3.6.25 Floating-point data-processing (1 source) - single precision */ |
4117 | static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn) | |
4118 | { | |
4119 | TCGv_ptr fpst; | |
4120 | TCGv_i32 tcg_op; | |
4121 | TCGv_i32 tcg_res; | |
4122 | ||
4123 | fpst = get_fpstatus_ptr(); | |
4124 | tcg_op = read_fp_sreg(s, rn); | |
4125 | tcg_res = tcg_temp_new_i32(); | |
4126 | ||
4127 | switch (opcode) { | |
4128 | case 0x0: /* FMOV */ | |
4129 | tcg_gen_mov_i32(tcg_res, tcg_op); | |
4130 | break; | |
4131 | case 0x1: /* FABS */ | |
4132 | gen_helper_vfp_abss(tcg_res, tcg_op); | |
4133 | break; | |
4134 | case 0x2: /* FNEG */ | |
4135 | gen_helper_vfp_negs(tcg_res, tcg_op); | |
4136 | break; | |
4137 | case 0x3: /* FSQRT */ | |
4138 | gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env); | |
4139 | break; | |
4140 | case 0x8: /* FRINTN */ | |
4141 | case 0x9: /* FRINTP */ | |
4142 | case 0xa: /* FRINTM */ | |
4143 | case 0xb: /* FRINTZ */ | |
4144 | case 0xc: /* FRINTA */ | |
4145 | { | |
4146 | TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7)); | |
4147 | ||
4148 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); | |
4149 | gen_helper_rints(tcg_res, tcg_op, fpst); | |
4150 | ||
4151 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); | |
4152 | tcg_temp_free_i32(tcg_rmode); | |
4153 | break; | |
4154 | } | |
4155 | case 0xe: /* FRINTX */ | |
4156 | gen_helper_rints_exact(tcg_res, tcg_op, fpst); | |
4157 | break; | |
4158 | case 0xf: /* FRINTI */ | |
4159 | gen_helper_rints(tcg_res, tcg_op, fpst); | |
4160 | break; | |
4161 | default: | |
4162 | abort(); | |
4163 | } | |
4164 | ||
4165 | write_fp_sreg(s, rd, tcg_res); | |
4166 | ||
4167 | tcg_temp_free_ptr(fpst); | |
4168 | tcg_temp_free_i32(tcg_op); | |
4169 | tcg_temp_free_i32(tcg_res); | |
4170 | } | |
4171 | ||
4172 | /* C3.6.25 Floating-point data-processing (1 source) - double precision */ | |
4173 | static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn) | |
4174 | { | |
4175 | TCGv_ptr fpst; | |
4176 | TCGv_i64 tcg_op; | |
4177 | TCGv_i64 tcg_res; | |
4178 | ||
4179 | fpst = get_fpstatus_ptr(); | |
4180 | tcg_op = read_fp_dreg(s, rn); | |
4181 | tcg_res = tcg_temp_new_i64(); | |
4182 | ||
4183 | switch (opcode) { | |
4184 | case 0x0: /* FMOV */ | |
4185 | tcg_gen_mov_i64(tcg_res, tcg_op); | |
4186 | break; | |
4187 | case 0x1: /* FABS */ | |
4188 | gen_helper_vfp_absd(tcg_res, tcg_op); | |
4189 | break; | |
4190 | case 0x2: /* FNEG */ | |
4191 | gen_helper_vfp_negd(tcg_res, tcg_op); | |
4192 | break; | |
4193 | case 0x3: /* FSQRT */ | |
4194 | gen_helper_vfp_sqrtd(tcg_res, tcg_op, cpu_env); | |
4195 | break; | |
4196 | case 0x8: /* FRINTN */ | |
4197 | case 0x9: /* FRINTP */ | |
4198 | case 0xa: /* FRINTM */ | |
4199 | case 0xb: /* FRINTZ */ | |
4200 | case 0xc: /* FRINTA */ | |
4201 | { | |
4202 | TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7)); | |
4203 | ||
4204 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); | |
4205 | gen_helper_rintd(tcg_res, tcg_op, fpst); | |
4206 | ||
4207 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); | |
4208 | tcg_temp_free_i32(tcg_rmode); | |
4209 | break; | |
4210 | } | |
4211 | case 0xe: /* FRINTX */ | |
4212 | gen_helper_rintd_exact(tcg_res, tcg_op, fpst); | |
4213 | break; | |
4214 | case 0xf: /* FRINTI */ | |
4215 | gen_helper_rintd(tcg_res, tcg_op, fpst); | |
4216 | break; | |
4217 | default: | |
4218 | abort(); | |
4219 | } | |
4220 | ||
4221 | write_fp_dreg(s, rd, tcg_res); | |
4222 | ||
4223 | tcg_temp_free_ptr(fpst); | |
4224 | tcg_temp_free_i64(tcg_op); | |
4225 | tcg_temp_free_i64(tcg_res); | |
4226 | } | |
4227 | ||
8900aad2 PM |
4228 | static void handle_fp_fcvt(DisasContext *s, int opcode, |
4229 | int rd, int rn, int dtype, int ntype) | |
4230 | { | |
4231 | switch (ntype) { | |
4232 | case 0x0: | |
4233 | { | |
4234 | TCGv_i32 tcg_rn = read_fp_sreg(s, rn); | |
4235 | if (dtype == 1) { | |
4236 | /* Single to double */ | |
4237 | TCGv_i64 tcg_rd = tcg_temp_new_i64(); | |
4238 | gen_helper_vfp_fcvtds(tcg_rd, tcg_rn, cpu_env); | |
4239 | write_fp_dreg(s, rd, tcg_rd); | |
4240 | tcg_temp_free_i64(tcg_rd); | |
4241 | } else { | |
4242 | /* Single to half */ | |
4243 | TCGv_i32 tcg_rd = tcg_temp_new_i32(); | |
4244 | gen_helper_vfp_fcvt_f32_to_f16(tcg_rd, tcg_rn, cpu_env); | |
4245 | /* write_fp_sreg is OK here because top half of tcg_rd is zero */ | |
4246 | write_fp_sreg(s, rd, tcg_rd); | |
4247 | tcg_temp_free_i32(tcg_rd); | |
4248 | } | |
4249 | tcg_temp_free_i32(tcg_rn); | |
4250 | break; | |
4251 | } | |
4252 | case 0x1: | |
4253 | { | |
4254 | TCGv_i64 tcg_rn = read_fp_dreg(s, rn); | |
4255 | TCGv_i32 tcg_rd = tcg_temp_new_i32(); | |
4256 | if (dtype == 0) { | |
4257 | /* Double to single */ | |
4258 | gen_helper_vfp_fcvtsd(tcg_rd, tcg_rn, cpu_env); | |
4259 | } else { | |
4260 | /* Double to half */ | |
4261 | gen_helper_vfp_fcvt_f64_to_f16(tcg_rd, tcg_rn, cpu_env); | |
4262 | /* write_fp_sreg is OK here because top half of tcg_rd is zero */ | |
4263 | } | |
4264 | write_fp_sreg(s, rd, tcg_rd); | |
4265 | tcg_temp_free_i32(tcg_rd); | |
4266 | tcg_temp_free_i64(tcg_rn); | |
4267 | break; | |
4268 | } | |
4269 | case 0x3: | |
4270 | { | |
4271 | TCGv_i32 tcg_rn = read_fp_sreg(s, rn); | |
4272 | tcg_gen_ext16u_i32(tcg_rn, tcg_rn); | |
4273 | if (dtype == 0) { | |
4274 | /* Half to single */ | |
4275 | TCGv_i32 tcg_rd = tcg_temp_new_i32(); | |
4276 | gen_helper_vfp_fcvt_f16_to_f32(tcg_rd, tcg_rn, cpu_env); | |
4277 | write_fp_sreg(s, rd, tcg_rd); | |
4278 | tcg_temp_free_i32(tcg_rd); | |
4279 | } else { | |
4280 | /* Half to double */ | |
4281 | TCGv_i64 tcg_rd = tcg_temp_new_i64(); | |
4282 | gen_helper_vfp_fcvt_f16_to_f64(tcg_rd, tcg_rn, cpu_env); | |
4283 | write_fp_dreg(s, rd, tcg_rd); | |
4284 | tcg_temp_free_i64(tcg_rd); | |
4285 | } | |
4286 | tcg_temp_free_i32(tcg_rn); | |
4287 | break; | |
4288 | } | |
4289 | default: | |
4290 | abort(); | |
4291 | } | |
4292 | } | |
4293 | ||
faa0ba46 PM |
4294 | /* C3.6.25 Floating point data-processing (1 source) |
4295 | * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0 | |
4296 | * +---+---+---+-----------+------+---+--------+-----------+------+------+ | |
4297 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd | | |
4298 | * +---+---+---+-----------+------+---+--------+-----------+------+------+ | |
4299 | */ | |
4300 | static void disas_fp_1src(DisasContext *s, uint32_t insn) | |
4301 | { | |
d9b0848d PM |
4302 | int type = extract32(insn, 22, 2); |
4303 | int opcode = extract32(insn, 15, 6); | |
4304 | int rn = extract32(insn, 5, 5); | |
4305 | int rd = extract32(insn, 0, 5); | |
4306 | ||
4307 | switch (opcode) { | |
4308 | case 0x4: case 0x5: case 0x7: | |
8900aad2 | 4309 | { |
d9b0848d | 4310 | /* FCVT between half, single and double precision */ |
8900aad2 PM |
4311 | int dtype = extract32(opcode, 0, 2); |
4312 | if (type == 2 || dtype == type) { | |
4313 | unallocated_encoding(s); | |
4314 | return; | |
4315 | } | |
8c6afa6a PM |
4316 | if (!fp_access_check(s)) { |
4317 | return; | |
4318 | } | |
4319 | ||
8900aad2 | 4320 | handle_fp_fcvt(s, opcode, rd, rn, dtype, type); |
d9b0848d | 4321 | break; |
8900aad2 | 4322 | } |
d9b0848d PM |
4323 | case 0x0 ... 0x3: |
4324 | case 0x8 ... 0xc: | |
4325 | case 0xe ... 0xf: | |
4326 | /* 32-to-32 and 64-to-64 ops */ | |
4327 | switch (type) { | |
4328 | case 0: | |
8c6afa6a PM |
4329 | if (!fp_access_check(s)) { |
4330 | return; | |
4331 | } | |
4332 | ||
d9b0848d PM |
4333 | handle_fp_1src_single(s, opcode, rd, rn); |
4334 | break; | |
4335 | case 1: | |
8c6afa6a PM |
4336 | if (!fp_access_check(s)) { |
4337 | return; | |
4338 | } | |
4339 | ||
d9b0848d PM |
4340 | handle_fp_1src_double(s, opcode, rd, rn); |
4341 | break; | |
4342 | default: | |
4343 | unallocated_encoding(s); | |
4344 | } | |
4345 | break; | |
4346 | default: | |
4347 | unallocated_encoding(s); | |
4348 | break; | |
4349 | } | |
faa0ba46 PM |
4350 | } |
4351 | ||
ec73d2e0 AG |
4352 | /* C3.6.26 Floating-point data-processing (2 source) - single precision */ |
4353 | static void handle_fp_2src_single(DisasContext *s, int opcode, | |
4354 | int rd, int rn, int rm) | |
4355 | { | |
4356 | TCGv_i32 tcg_op1; | |
4357 | TCGv_i32 tcg_op2; | |
4358 | TCGv_i32 tcg_res; | |
4359 | TCGv_ptr fpst; | |
4360 | ||
4361 | tcg_res = tcg_temp_new_i32(); | |
4362 | fpst = get_fpstatus_ptr(); | |
4363 | tcg_op1 = read_fp_sreg(s, rn); | |
4364 | tcg_op2 = read_fp_sreg(s, rm); | |
4365 | ||
4366 | switch (opcode) { | |
4367 | case 0x0: /* FMUL */ | |
4368 | gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst); | |
4369 | break; | |
4370 | case 0x1: /* FDIV */ | |
4371 | gen_helper_vfp_divs(tcg_res, tcg_op1, tcg_op2, fpst); | |
4372 | break; | |
4373 | case 0x2: /* FADD */ | |
4374 | gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst); | |
4375 | break; | |
4376 | case 0x3: /* FSUB */ | |
4377 | gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst); | |
4378 | break; | |
4379 | case 0x4: /* FMAX */ | |
4380 | gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst); | |
4381 | break; | |
4382 | case 0x5: /* FMIN */ | |
4383 | gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst); | |
4384 | break; | |
4385 | case 0x6: /* FMAXNM */ | |
4386 | gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
4387 | break; | |
4388 | case 0x7: /* FMINNM */ | |
4389 | gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
4390 | break; | |
4391 | case 0x8: /* FNMUL */ | |
4392 | gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst); | |
4393 | gen_helper_vfp_negs(tcg_res, tcg_res); | |
4394 | break; | |
4395 | } | |
4396 | ||
4397 | write_fp_sreg(s, rd, tcg_res); | |
4398 | ||
4399 | tcg_temp_free_ptr(fpst); | |
4400 | tcg_temp_free_i32(tcg_op1); | |
4401 | tcg_temp_free_i32(tcg_op2); | |
4402 | tcg_temp_free_i32(tcg_res); | |
4403 | } | |
4404 | ||
4405 | /* C3.6.26 Floating-point data-processing (2 source) - double precision */ | |
4406 | static void handle_fp_2src_double(DisasContext *s, int opcode, | |
4407 | int rd, int rn, int rm) | |
4408 | { | |
4409 | TCGv_i64 tcg_op1; | |
4410 | TCGv_i64 tcg_op2; | |
4411 | TCGv_i64 tcg_res; | |
4412 | TCGv_ptr fpst; | |
4413 | ||
4414 | tcg_res = tcg_temp_new_i64(); | |
4415 | fpst = get_fpstatus_ptr(); | |
4416 | tcg_op1 = read_fp_dreg(s, rn); | |
4417 | tcg_op2 = read_fp_dreg(s, rm); | |
4418 | ||
4419 | switch (opcode) { | |
4420 | case 0x0: /* FMUL */ | |
4421 | gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst); | |
4422 | break; | |
4423 | case 0x1: /* FDIV */ | |
4424 | gen_helper_vfp_divd(tcg_res, tcg_op1, tcg_op2, fpst); | |
4425 | break; | |
4426 | case 0x2: /* FADD */ | |
4427 | gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst); | |
4428 | break; | |
4429 | case 0x3: /* FSUB */ | |
4430 | gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst); | |
4431 | break; | |
4432 | case 0x4: /* FMAX */ | |
4433 | gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst); | |
4434 | break; | |
4435 | case 0x5: /* FMIN */ | |
4436 | gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst); | |
4437 | break; | |
4438 | case 0x6: /* FMAXNM */ | |
4439 | gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
4440 | break; | |
4441 | case 0x7: /* FMINNM */ | |
4442 | gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
4443 | break; | |
4444 | case 0x8: /* FNMUL */ | |
4445 | gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst); | |
4446 | gen_helper_vfp_negd(tcg_res, tcg_res); | |
4447 | break; | |
4448 | } | |
4449 | ||
4450 | write_fp_dreg(s, rd, tcg_res); | |
4451 | ||
4452 | tcg_temp_free_ptr(fpst); | |
4453 | tcg_temp_free_i64(tcg_op1); | |
4454 | tcg_temp_free_i64(tcg_op2); | |
4455 | tcg_temp_free_i64(tcg_res); | |
4456 | } | |
4457 | ||
faa0ba46 PM |
4458 | /* C3.6.26 Floating point data-processing (2 source) |
4459 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 | |
4460 | * +---+---+---+-----------+------+---+------+--------+-----+------+------+ | |
4461 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd | | |
4462 | * +---+---+---+-----------+------+---+------+--------+-----+------+------+ | |
4463 | */ | |
4464 | static void disas_fp_2src(DisasContext *s, uint32_t insn) | |
4465 | { | |
ec73d2e0 AG |
4466 | int type = extract32(insn, 22, 2); |
4467 | int rd = extract32(insn, 0, 5); | |
4468 | int rn = extract32(insn, 5, 5); | |
4469 | int rm = extract32(insn, 16, 5); | |
4470 | int opcode = extract32(insn, 12, 4); | |
4471 | ||
4472 | if (opcode > 8) { | |
4473 | unallocated_encoding(s); | |
4474 | return; | |
4475 | } | |
4476 | ||
4477 | switch (type) { | |
4478 | case 0: | |
8c6afa6a PM |
4479 | if (!fp_access_check(s)) { |
4480 | return; | |
4481 | } | |
ec73d2e0 AG |
4482 | handle_fp_2src_single(s, opcode, rd, rn, rm); |
4483 | break; | |
4484 | case 1: | |
8c6afa6a PM |
4485 | if (!fp_access_check(s)) { |
4486 | return; | |
4487 | } | |
ec73d2e0 AG |
4488 | handle_fp_2src_double(s, opcode, rd, rn, rm); |
4489 | break; | |
4490 | default: | |
4491 | unallocated_encoding(s); | |
4492 | } | |
faa0ba46 PM |
4493 | } |
4494 | ||
6a30667f AG |
4495 | /* C3.6.27 Floating-point data-processing (3 source) - single precision */ |
4496 | static void handle_fp_3src_single(DisasContext *s, bool o0, bool o1, | |
4497 | int rd, int rn, int rm, int ra) | |
4498 | { | |
4499 | TCGv_i32 tcg_op1, tcg_op2, tcg_op3; | |
4500 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
4501 | TCGv_ptr fpst = get_fpstatus_ptr(); | |
4502 | ||
4503 | tcg_op1 = read_fp_sreg(s, rn); | |
4504 | tcg_op2 = read_fp_sreg(s, rm); | |
4505 | tcg_op3 = read_fp_sreg(s, ra); | |
4506 | ||
4507 | /* These are fused multiply-add, and must be done as one | |
4508 | * floating point operation with no rounding between the | |
4509 | * multiplication and addition steps. | |
4510 | * NB that doing the negations here as separate steps is | |
4511 | * correct : an input NaN should come out with its sign bit | |
4512 | * flipped if it is a negated-input. | |
4513 | */ | |
4514 | if (o1 == true) { | |
4515 | gen_helper_vfp_negs(tcg_op3, tcg_op3); | |
4516 | } | |
4517 | ||
4518 | if (o0 != o1) { | |
4519 | gen_helper_vfp_negs(tcg_op1, tcg_op1); | |
4520 | } | |
4521 | ||
4522 | gen_helper_vfp_muladds(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst); | |
4523 | ||
4524 | write_fp_sreg(s, rd, tcg_res); | |
4525 | ||
4526 | tcg_temp_free_ptr(fpst); | |
4527 | tcg_temp_free_i32(tcg_op1); | |
4528 | tcg_temp_free_i32(tcg_op2); | |
4529 | tcg_temp_free_i32(tcg_op3); | |
4530 | tcg_temp_free_i32(tcg_res); | |
4531 | } | |
4532 | ||
4533 | /* C3.6.27 Floating-point data-processing (3 source) - double precision */ | |
4534 | static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1, | |
4535 | int rd, int rn, int rm, int ra) | |
4536 | { | |
4537 | TCGv_i64 tcg_op1, tcg_op2, tcg_op3; | |
4538 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
4539 | TCGv_ptr fpst = get_fpstatus_ptr(); | |
4540 | ||
4541 | tcg_op1 = read_fp_dreg(s, rn); | |
4542 | tcg_op2 = read_fp_dreg(s, rm); | |
4543 | tcg_op3 = read_fp_dreg(s, ra); | |
4544 | ||
4545 | /* These are fused multiply-add, and must be done as one | |
4546 | * floating point operation with no rounding between the | |
4547 | * multiplication and addition steps. | |
4548 | * NB that doing the negations here as separate steps is | |
4549 | * correct : an input NaN should come out with its sign bit | |
4550 | * flipped if it is a negated-input. | |
4551 | */ | |
4552 | if (o1 == true) { | |
4553 | gen_helper_vfp_negd(tcg_op3, tcg_op3); | |
4554 | } | |
4555 | ||
4556 | if (o0 != o1) { | |
4557 | gen_helper_vfp_negd(tcg_op1, tcg_op1); | |
4558 | } | |
4559 | ||
4560 | gen_helper_vfp_muladdd(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst); | |
4561 | ||
4562 | write_fp_dreg(s, rd, tcg_res); | |
4563 | ||
4564 | tcg_temp_free_ptr(fpst); | |
4565 | tcg_temp_free_i64(tcg_op1); | |
4566 | tcg_temp_free_i64(tcg_op2); | |
4567 | tcg_temp_free_i64(tcg_op3); | |
4568 | tcg_temp_free_i64(tcg_res); | |
4569 | } | |
4570 | ||
faa0ba46 PM |
4571 | /* C3.6.27 Floating point data-processing (3 source) |
4572 | * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0 | |
4573 | * +---+---+---+-----------+------+----+------+----+------+------+------+ | |
4574 | * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd | | |
4575 | * +---+---+---+-----------+------+----+------+----+------+------+------+ | |
4576 | */ | |
4577 | static void disas_fp_3src(DisasContext *s, uint32_t insn) | |
4578 | { | |
6a30667f AG |
4579 | int type = extract32(insn, 22, 2); |
4580 | int rd = extract32(insn, 0, 5); | |
4581 | int rn = extract32(insn, 5, 5); | |
4582 | int ra = extract32(insn, 10, 5); | |
4583 | int rm = extract32(insn, 16, 5); | |
4584 | bool o0 = extract32(insn, 15, 1); | |
4585 | bool o1 = extract32(insn, 21, 1); | |
4586 | ||
4587 | switch (type) { | |
4588 | case 0: | |
8c6afa6a PM |
4589 | if (!fp_access_check(s)) { |
4590 | return; | |
4591 | } | |
6a30667f AG |
4592 | handle_fp_3src_single(s, o0, o1, rd, rn, rm, ra); |
4593 | break; | |
4594 | case 1: | |
8c6afa6a PM |
4595 | if (!fp_access_check(s)) { |
4596 | return; | |
4597 | } | |
6a30667f AG |
4598 | handle_fp_3src_double(s, o0, o1, rd, rn, rm, ra); |
4599 | break; | |
4600 | default: | |
4601 | unallocated_encoding(s); | |
4602 | } | |
faa0ba46 PM |
4603 | } |
4604 | ||
4605 | /* C3.6.28 Floating point immediate | |
4606 | * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0 | |
4607 | * +---+---+---+-----------+------+---+------------+-------+------+------+ | |
4608 | * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd | | |
4609 | * +---+---+---+-----------+------+---+------------+-------+------+------+ | |
4610 | */ | |
4611 | static void disas_fp_imm(DisasContext *s, uint32_t insn) | |
4612 | { | |
6163f868 AG |
4613 | int rd = extract32(insn, 0, 5); |
4614 | int imm8 = extract32(insn, 13, 8); | |
4615 | int is_double = extract32(insn, 22, 2); | |
4616 | uint64_t imm; | |
4617 | TCGv_i64 tcg_res; | |
4618 | ||
4619 | if (is_double > 1) { | |
4620 | unallocated_encoding(s); | |
4621 | return; | |
4622 | } | |
4623 | ||
8c6afa6a PM |
4624 | if (!fp_access_check(s)) { |
4625 | return; | |
4626 | } | |
4627 | ||
6163f868 AG |
4628 | /* The imm8 encodes the sign bit, enough bits to represent |
4629 | * an exponent in the range 01....1xx to 10....0xx, | |
4630 | * and the most significant 4 bits of the mantissa; see | |
4631 | * VFPExpandImm() in the v8 ARM ARM. | |
4632 | */ | |
4633 | if (is_double) { | |
4634 | imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) | | |
4635 | (extract32(imm8, 6, 1) ? 0x3fc0 : 0x4000) | | |
4636 | extract32(imm8, 0, 6); | |
4637 | imm <<= 48; | |
4638 | } else { | |
4639 | imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) | | |
4640 | (extract32(imm8, 6, 1) ? 0x3e00 : 0x4000) | | |
4641 | (extract32(imm8, 0, 6) << 3); | |
4642 | imm <<= 16; | |
4643 | } | |
4644 | ||
4645 | tcg_res = tcg_const_i64(imm); | |
4646 | write_fp_dreg(s, rd, tcg_res); | |
4647 | tcg_temp_free_i64(tcg_res); | |
faa0ba46 PM |
4648 | } |
4649 | ||
52a1f6a3 AG |
4650 | /* Handle floating point <=> fixed point conversions. Note that we can |
4651 | * also deal with fp <=> integer conversions as a special case (scale == 64) | |
4652 | * OPTME: consider handling that special case specially or at least skipping | |
4653 | * the call to scalbn in the helpers for zero shifts. | |
4654 | */ | |
4655 | static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode, | |
4656 | bool itof, int rmode, int scale, int sf, int type) | |
4657 | { | |
4658 | bool is_signed = !(opcode & 1); | |
4659 | bool is_double = type; | |
4660 | TCGv_ptr tcg_fpstatus; | |
4661 | TCGv_i32 tcg_shift; | |
4662 | ||
4663 | tcg_fpstatus = get_fpstatus_ptr(); | |
4664 | ||
4665 | tcg_shift = tcg_const_i32(64 - scale); | |
4666 | ||
4667 | if (itof) { | |
4668 | TCGv_i64 tcg_int = cpu_reg(s, rn); | |
4669 | if (!sf) { | |
4670 | TCGv_i64 tcg_extend = new_tmp_a64(s); | |
4671 | ||
4672 | if (is_signed) { | |
4673 | tcg_gen_ext32s_i64(tcg_extend, tcg_int); | |
4674 | } else { | |
4675 | tcg_gen_ext32u_i64(tcg_extend, tcg_int); | |
4676 | } | |
4677 | ||
4678 | tcg_int = tcg_extend; | |
4679 | } | |
4680 | ||
4681 | if (is_double) { | |
4682 | TCGv_i64 tcg_double = tcg_temp_new_i64(); | |
4683 | if (is_signed) { | |
4684 | gen_helper_vfp_sqtod(tcg_double, tcg_int, | |
4685 | tcg_shift, tcg_fpstatus); | |
4686 | } else { | |
4687 | gen_helper_vfp_uqtod(tcg_double, tcg_int, | |
4688 | tcg_shift, tcg_fpstatus); | |
4689 | } | |
4690 | write_fp_dreg(s, rd, tcg_double); | |
4691 | tcg_temp_free_i64(tcg_double); | |
4692 | } else { | |
4693 | TCGv_i32 tcg_single = tcg_temp_new_i32(); | |
4694 | if (is_signed) { | |
4695 | gen_helper_vfp_sqtos(tcg_single, tcg_int, | |
4696 | tcg_shift, tcg_fpstatus); | |
4697 | } else { | |
4698 | gen_helper_vfp_uqtos(tcg_single, tcg_int, | |
4699 | tcg_shift, tcg_fpstatus); | |
4700 | } | |
4701 | write_fp_sreg(s, rd, tcg_single); | |
4702 | tcg_temp_free_i32(tcg_single); | |
4703 | } | |
4704 | } else { | |
4705 | TCGv_i64 tcg_int = cpu_reg(s, rd); | |
4706 | TCGv_i32 tcg_rmode; | |
4707 | ||
4708 | if (extract32(opcode, 2, 1)) { | |
4709 | /* There are too many rounding modes to all fit into rmode, | |
4710 | * so FCVTA[US] is a special case. | |
4711 | */ | |
4712 | rmode = FPROUNDING_TIEAWAY; | |
4713 | } | |
4714 | ||
4715 | tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); | |
4716 | ||
4717 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); | |
4718 | ||
4719 | if (is_double) { | |
4720 | TCGv_i64 tcg_double = read_fp_dreg(s, rn); | |
4721 | if (is_signed) { | |
4722 | if (!sf) { | |
4723 | gen_helper_vfp_tosld(tcg_int, tcg_double, | |
4724 | tcg_shift, tcg_fpstatus); | |
4725 | } else { | |
4726 | gen_helper_vfp_tosqd(tcg_int, tcg_double, | |
4727 | tcg_shift, tcg_fpstatus); | |
4728 | } | |
4729 | } else { | |
4730 | if (!sf) { | |
4731 | gen_helper_vfp_tould(tcg_int, tcg_double, | |
4732 | tcg_shift, tcg_fpstatus); | |
4733 | } else { | |
4734 | gen_helper_vfp_touqd(tcg_int, tcg_double, | |
4735 | tcg_shift, tcg_fpstatus); | |
4736 | } | |
4737 | } | |
4738 | tcg_temp_free_i64(tcg_double); | |
4739 | } else { | |
4740 | TCGv_i32 tcg_single = read_fp_sreg(s, rn); | |
4741 | if (sf) { | |
4742 | if (is_signed) { | |
4743 | gen_helper_vfp_tosqs(tcg_int, tcg_single, | |
4744 | tcg_shift, tcg_fpstatus); | |
4745 | } else { | |
4746 | gen_helper_vfp_touqs(tcg_int, tcg_single, | |
4747 | tcg_shift, tcg_fpstatus); | |
4748 | } | |
4749 | } else { | |
4750 | TCGv_i32 tcg_dest = tcg_temp_new_i32(); | |
4751 | if (is_signed) { | |
4752 | gen_helper_vfp_tosls(tcg_dest, tcg_single, | |
4753 | tcg_shift, tcg_fpstatus); | |
4754 | } else { | |
4755 | gen_helper_vfp_touls(tcg_dest, tcg_single, | |
4756 | tcg_shift, tcg_fpstatus); | |
4757 | } | |
4758 | tcg_gen_extu_i32_i64(tcg_int, tcg_dest); | |
4759 | tcg_temp_free_i32(tcg_dest); | |
4760 | } | |
4761 | tcg_temp_free_i32(tcg_single); | |
4762 | } | |
4763 | ||
4764 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); | |
4765 | tcg_temp_free_i32(tcg_rmode); | |
4766 | ||
4767 | if (!sf) { | |
4768 | tcg_gen_ext32u_i64(tcg_int, tcg_int); | |
4769 | } | |
4770 | } | |
4771 | ||
4772 | tcg_temp_free_ptr(tcg_fpstatus); | |
4773 | tcg_temp_free_i32(tcg_shift); | |
4774 | } | |
4775 | ||
faa0ba46 PM |
4776 | /* C3.6.29 Floating point <-> fixed point conversions |
4777 | * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0 | |
4778 | * +----+---+---+-----------+------+---+-------+--------+-------+------+------+ | |
4779 | * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd | | |
4780 | * +----+---+---+-----------+------+---+-------+--------+-------+------+------+ | |
4781 | */ | |
4782 | static void disas_fp_fixed_conv(DisasContext *s, uint32_t insn) | |
4783 | { | |
52a1f6a3 AG |
4784 | int rd = extract32(insn, 0, 5); |
4785 | int rn = extract32(insn, 5, 5); | |
4786 | int scale = extract32(insn, 10, 6); | |
4787 | int opcode = extract32(insn, 16, 3); | |
4788 | int rmode = extract32(insn, 19, 2); | |
4789 | int type = extract32(insn, 22, 2); | |
4790 | bool sbit = extract32(insn, 29, 1); | |
4791 | bool sf = extract32(insn, 31, 1); | |
4792 | bool itof; | |
4793 | ||
4794 | if (sbit || (type > 1) | |
4795 | || (!sf && scale < 32)) { | |
4796 | unallocated_encoding(s); | |
4797 | return; | |
4798 | } | |
4799 | ||
4800 | switch ((rmode << 3) | opcode) { | |
4801 | case 0x2: /* SCVTF */ | |
4802 | case 0x3: /* UCVTF */ | |
4803 | itof = true; | |
4804 | break; | |
4805 | case 0x18: /* FCVTZS */ | |
4806 | case 0x19: /* FCVTZU */ | |
4807 | itof = false; | |
4808 | break; | |
4809 | default: | |
4810 | unallocated_encoding(s); | |
4811 | return; | |
4812 | } | |
4813 | ||
8c6afa6a PM |
4814 | if (!fp_access_check(s)) { |
4815 | return; | |
4816 | } | |
4817 | ||
52a1f6a3 | 4818 | handle_fpfpcvt(s, rd, rn, opcode, itof, FPROUNDING_ZERO, scale, sf, type); |
faa0ba46 PM |
4819 | } |
4820 | ||
ce5458e8 PM |
4821 | static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof) |
4822 | { | |
4823 | /* FMOV: gpr to or from float, double, or top half of quad fp reg, | |
4824 | * without conversion. | |
4825 | */ | |
4826 | ||
4827 | if (itof) { | |
ce5458e8 PM |
4828 | TCGv_i64 tcg_rn = cpu_reg(s, rn); |
4829 | ||
4830 | switch (type) { | |
4831 | case 0: | |
4832 | { | |
4833 | /* 32 bit */ | |
4834 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
4835 | tcg_gen_ext32u_i64(tmp, tcg_rn); | |
90e49638 | 4836 | tcg_gen_st_i64(tmp, cpu_env, fp_reg_offset(s, rd, MO_64)); |
ce5458e8 | 4837 | tcg_gen_movi_i64(tmp, 0); |
90e49638 | 4838 | tcg_gen_st_i64(tmp, cpu_env, fp_reg_hi_offset(s, rd)); |
ce5458e8 PM |
4839 | tcg_temp_free_i64(tmp); |
4840 | break; | |
4841 | } | |
4842 | case 1: | |
4843 | { | |
4844 | /* 64 bit */ | |
4845 | TCGv_i64 tmp = tcg_const_i64(0); | |
90e49638 PM |
4846 | tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_offset(s, rd, MO_64)); |
4847 | tcg_gen_st_i64(tmp, cpu_env, fp_reg_hi_offset(s, rd)); | |
ce5458e8 PM |
4848 | tcg_temp_free_i64(tmp); |
4849 | break; | |
4850 | } | |
4851 | case 2: | |
4852 | /* 64 bit to top half. */ | |
90e49638 | 4853 | tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd)); |
ce5458e8 PM |
4854 | break; |
4855 | } | |
4856 | } else { | |
ce5458e8 PM |
4857 | TCGv_i64 tcg_rd = cpu_reg(s, rd); |
4858 | ||
4859 | switch (type) { | |
4860 | case 0: | |
4861 | /* 32 bit */ | |
90e49638 | 4862 | tcg_gen_ld32u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_32)); |
ce5458e8 | 4863 | break; |
ce5458e8 PM |
4864 | case 1: |
4865 | /* 64 bit */ | |
90e49638 | 4866 | tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_64)); |
e2f90565 PM |
4867 | break; |
4868 | case 2: | |
4869 | /* 64 bits from top half */ | |
90e49638 | 4870 | tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn)); |
ce5458e8 PM |
4871 | break; |
4872 | } | |
4873 | } | |
4874 | } | |
4875 | ||
faa0ba46 PM |
4876 | /* C3.6.30 Floating point <-> integer conversions |
4877 | * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0 | |
4878 | * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+ | |
c436d406 | 4879 | * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd | |
faa0ba46 PM |
4880 | * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+ |
4881 | */ | |
4882 | static void disas_fp_int_conv(DisasContext *s, uint32_t insn) | |
4883 | { | |
ce5458e8 PM |
4884 | int rd = extract32(insn, 0, 5); |
4885 | int rn = extract32(insn, 5, 5); | |
4886 | int opcode = extract32(insn, 16, 3); | |
4887 | int rmode = extract32(insn, 19, 2); | |
4888 | int type = extract32(insn, 22, 2); | |
4889 | bool sbit = extract32(insn, 29, 1); | |
4890 | bool sf = extract32(insn, 31, 1); | |
4891 | ||
c436d406 WN |
4892 | if (sbit) { |
4893 | unallocated_encoding(s); | |
4894 | return; | |
4895 | } | |
4896 | ||
4897 | if (opcode > 5) { | |
ce5458e8 PM |
4898 | /* FMOV */ |
4899 | bool itof = opcode & 1; | |
4900 | ||
c436d406 WN |
4901 | if (rmode >= 2) { |
4902 | unallocated_encoding(s); | |
4903 | return; | |
4904 | } | |
4905 | ||
ce5458e8 PM |
4906 | switch (sf << 3 | type << 1 | rmode) { |
4907 | case 0x0: /* 32 bit */ | |
4908 | case 0xa: /* 64 bit */ | |
4909 | case 0xd: /* 64 bit to top half of quad */ | |
4910 | break; | |
4911 | default: | |
4912 | /* all other sf/type/rmode combinations are invalid */ | |
4913 | unallocated_encoding(s); | |
4914 | break; | |
4915 | } | |
4916 | ||
8c6afa6a PM |
4917 | if (!fp_access_check(s)) { |
4918 | return; | |
4919 | } | |
ce5458e8 PM |
4920 | handle_fmov(s, rd, rn, type, itof); |
4921 | } else { | |
4922 | /* actual FP conversions */ | |
c436d406 WN |
4923 | bool itof = extract32(opcode, 1, 1); |
4924 | ||
4925 | if (type > 1 || (rmode != 0 && opcode > 1)) { | |
4926 | unallocated_encoding(s); | |
4927 | return; | |
4928 | } | |
4929 | ||
8c6afa6a PM |
4930 | if (!fp_access_check(s)) { |
4931 | return; | |
4932 | } | |
c436d406 | 4933 | handle_fpfpcvt(s, rd, rn, opcode, itof, rmode, 64, sf, type); |
ce5458e8 | 4934 | } |
faa0ba46 PM |
4935 | } |
4936 | ||
4937 | /* FP-specific subcases of table C3-6 (SIMD and FP data processing) | |
4938 | * 31 30 29 28 25 24 0 | |
4939 | * +---+---+---+---------+-----------------------------+ | |
4940 | * | | 0 | | 1 1 1 1 | | | |
4941 | * +---+---+---+---------+-----------------------------+ | |
4942 | */ | |
4943 | static void disas_data_proc_fp(DisasContext *s, uint32_t insn) | |
4944 | { | |
4945 | if (extract32(insn, 24, 1)) { | |
4946 | /* Floating point data-processing (3 source) */ | |
4947 | disas_fp_3src(s, insn); | |
4948 | } else if (extract32(insn, 21, 1) == 0) { | |
4949 | /* Floating point to fixed point conversions */ | |
4950 | disas_fp_fixed_conv(s, insn); | |
4951 | } else { | |
4952 | switch (extract32(insn, 10, 2)) { | |
4953 | case 1: | |
4954 | /* Floating point conditional compare */ | |
4955 | disas_fp_ccomp(s, insn); | |
4956 | break; | |
4957 | case 2: | |
4958 | /* Floating point data-processing (2 source) */ | |
4959 | disas_fp_2src(s, insn); | |
4960 | break; | |
4961 | case 3: | |
4962 | /* Floating point conditional select */ | |
4963 | disas_fp_csel(s, insn); | |
4964 | break; | |
4965 | case 0: | |
4966 | switch (ctz32(extract32(insn, 12, 4))) { | |
4967 | case 0: /* [15:12] == xxx1 */ | |
4968 | /* Floating point immediate */ | |
4969 | disas_fp_imm(s, insn); | |
4970 | break; | |
4971 | case 1: /* [15:12] == xx10 */ | |
4972 | /* Floating point compare */ | |
4973 | disas_fp_compare(s, insn); | |
4974 | break; | |
4975 | case 2: /* [15:12] == x100 */ | |
4976 | /* Floating point data-processing (1 source) */ | |
4977 | disas_fp_1src(s, insn); | |
4978 | break; | |
4979 | case 3: /* [15:12] == 1000 */ | |
4980 | unallocated_encoding(s); | |
4981 | break; | |
4982 | default: /* [15:12] == 0000 */ | |
4983 | /* Floating point <-> integer conversions */ | |
4984 | disas_fp_int_conv(s, insn); | |
4985 | break; | |
4986 | } | |
4987 | break; | |
4988 | } | |
4989 | } | |
4990 | } | |
4991 | ||
5c73747f PM |
4992 | static void do_ext64(DisasContext *s, TCGv_i64 tcg_left, TCGv_i64 tcg_right, |
4993 | int pos) | |
4994 | { | |
4995 | /* Extract 64 bits from the middle of two concatenated 64 bit | |
4996 | * vector register slices left:right. The extracted bits start | |
4997 | * at 'pos' bits into the right (least significant) side. | |
4998 | * We return the result in tcg_right, and guarantee not to | |
4999 | * trash tcg_left. | |
5000 | */ | |
5001 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
5002 | assert(pos > 0 && pos < 64); | |
5003 | ||
5004 | tcg_gen_shri_i64(tcg_right, tcg_right, pos); | |
5005 | tcg_gen_shli_i64(tcg_tmp, tcg_left, 64 - pos); | |
5006 | tcg_gen_or_i64(tcg_right, tcg_right, tcg_tmp); | |
5007 | ||
5008 | tcg_temp_free_i64(tcg_tmp); | |
5009 | } | |
5010 | ||
384b26fb AB |
5011 | /* C3.6.1 EXT |
5012 | * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0 | |
5013 | * +---+---+-------------+-----+---+------+---+------+---+------+------+ | |
5014 | * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd | | |
5015 | * +---+---+-------------+-----+---+------+---+------+---+------+------+ | |
5016 | */ | |
5017 | static void disas_simd_ext(DisasContext *s, uint32_t insn) | |
5018 | { | |
5c73747f PM |
5019 | int is_q = extract32(insn, 30, 1); |
5020 | int op2 = extract32(insn, 22, 2); | |
5021 | int imm4 = extract32(insn, 11, 4); | |
5022 | int rm = extract32(insn, 16, 5); | |
5023 | int rn = extract32(insn, 5, 5); | |
5024 | int rd = extract32(insn, 0, 5); | |
5025 | int pos = imm4 << 3; | |
5026 | TCGv_i64 tcg_resl, tcg_resh; | |
5027 | ||
5028 | if (op2 != 0 || (!is_q && extract32(imm4, 3, 1))) { | |
5029 | unallocated_encoding(s); | |
5030 | return; | |
5031 | } | |
5032 | ||
8c6afa6a PM |
5033 | if (!fp_access_check(s)) { |
5034 | return; | |
5035 | } | |
5036 | ||
5c73747f PM |
5037 | tcg_resh = tcg_temp_new_i64(); |
5038 | tcg_resl = tcg_temp_new_i64(); | |
5039 | ||
5040 | /* Vd gets bits starting at pos bits into Vm:Vn. This is | |
5041 | * either extracting 128 bits from a 128:128 concatenation, or | |
5042 | * extracting 64 bits from a 64:64 concatenation. | |
5043 | */ | |
5044 | if (!is_q) { | |
5045 | read_vec_element(s, tcg_resl, rn, 0, MO_64); | |
5046 | if (pos != 0) { | |
5047 | read_vec_element(s, tcg_resh, rm, 0, MO_64); | |
5048 | do_ext64(s, tcg_resh, tcg_resl, pos); | |
5049 | } | |
5050 | tcg_gen_movi_i64(tcg_resh, 0); | |
5051 | } else { | |
5052 | TCGv_i64 tcg_hh; | |
5053 | typedef struct { | |
5054 | int reg; | |
5055 | int elt; | |
5056 | } EltPosns; | |
5057 | EltPosns eltposns[] = { {rn, 0}, {rn, 1}, {rm, 0}, {rm, 1} }; | |
5058 | EltPosns *elt = eltposns; | |
5059 | ||
5060 | if (pos >= 64) { | |
5061 | elt++; | |
5062 | pos -= 64; | |
5063 | } | |
5064 | ||
5065 | read_vec_element(s, tcg_resl, elt->reg, elt->elt, MO_64); | |
5066 | elt++; | |
5067 | read_vec_element(s, tcg_resh, elt->reg, elt->elt, MO_64); | |
5068 | elt++; | |
5069 | if (pos != 0) { | |
5070 | do_ext64(s, tcg_resh, tcg_resl, pos); | |
5071 | tcg_hh = tcg_temp_new_i64(); | |
5072 | read_vec_element(s, tcg_hh, elt->reg, elt->elt, MO_64); | |
5073 | do_ext64(s, tcg_hh, tcg_resh, pos); | |
5074 | tcg_temp_free_i64(tcg_hh); | |
5075 | } | |
5076 | } | |
5077 | ||
5078 | write_vec_element(s, tcg_resl, rd, 0, MO_64); | |
5079 | tcg_temp_free_i64(tcg_resl); | |
5080 | write_vec_element(s, tcg_resh, rd, 1, MO_64); | |
5081 | tcg_temp_free_i64(tcg_resh); | |
384b26fb AB |
5082 | } |
5083 | ||
5084 | /* C3.6.2 TBL/TBX | |
5085 | * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0 | |
5086 | * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+ | |
5087 | * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd | | |
5088 | * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+ | |
5089 | */ | |
5090 | static void disas_simd_tb(DisasContext *s, uint32_t insn) | |
5091 | { | |
7c51048f MM |
5092 | int op2 = extract32(insn, 22, 2); |
5093 | int is_q = extract32(insn, 30, 1); | |
5094 | int rm = extract32(insn, 16, 5); | |
5095 | int rn = extract32(insn, 5, 5); | |
5096 | int rd = extract32(insn, 0, 5); | |
5097 | int is_tblx = extract32(insn, 12, 1); | |
5098 | int len = extract32(insn, 13, 2); | |
5099 | TCGv_i64 tcg_resl, tcg_resh, tcg_idx; | |
5100 | TCGv_i32 tcg_regno, tcg_numregs; | |
5101 | ||
5102 | if (op2 != 0) { | |
5103 | unallocated_encoding(s); | |
5104 | return; | |
5105 | } | |
5106 | ||
8c6afa6a PM |
5107 | if (!fp_access_check(s)) { |
5108 | return; | |
5109 | } | |
5110 | ||
7c51048f MM |
5111 | /* This does a table lookup: for every byte element in the input |
5112 | * we index into a table formed from up to four vector registers, | |
5113 | * and then the output is the result of the lookups. Our helper | |
5114 | * function does the lookup operation for a single 64 bit part of | |
5115 | * the input. | |
5116 | */ | |
5117 | tcg_resl = tcg_temp_new_i64(); | |
5118 | tcg_resh = tcg_temp_new_i64(); | |
5119 | ||
5120 | if (is_tblx) { | |
5121 | read_vec_element(s, tcg_resl, rd, 0, MO_64); | |
5122 | } else { | |
5123 | tcg_gen_movi_i64(tcg_resl, 0); | |
5124 | } | |
5125 | if (is_tblx && is_q) { | |
5126 | read_vec_element(s, tcg_resh, rd, 1, MO_64); | |
5127 | } else { | |
5128 | tcg_gen_movi_i64(tcg_resh, 0); | |
5129 | } | |
5130 | ||
5131 | tcg_idx = tcg_temp_new_i64(); | |
5132 | tcg_regno = tcg_const_i32(rn); | |
5133 | tcg_numregs = tcg_const_i32(len + 1); | |
5134 | read_vec_element(s, tcg_idx, rm, 0, MO_64); | |
5135 | gen_helper_simd_tbl(tcg_resl, cpu_env, tcg_resl, tcg_idx, | |
5136 | tcg_regno, tcg_numregs); | |
5137 | if (is_q) { | |
5138 | read_vec_element(s, tcg_idx, rm, 1, MO_64); | |
5139 | gen_helper_simd_tbl(tcg_resh, cpu_env, tcg_resh, tcg_idx, | |
5140 | tcg_regno, tcg_numregs); | |
5141 | } | |
5142 | tcg_temp_free_i64(tcg_idx); | |
5143 | tcg_temp_free_i32(tcg_regno); | |
5144 | tcg_temp_free_i32(tcg_numregs); | |
5145 | ||
5146 | write_vec_element(s, tcg_resl, rd, 0, MO_64); | |
5147 | tcg_temp_free_i64(tcg_resl); | |
5148 | write_vec_element(s, tcg_resh, rd, 1, MO_64); | |
5149 | tcg_temp_free_i64(tcg_resh); | |
384b26fb AB |
5150 | } |
5151 | ||
5152 | /* C3.6.3 ZIP/UZP/TRN | |
5153 | * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0 | |
5154 | * +---+---+-------------+------+---+------+---+------------------+------+ | |
5155 | * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd | | |
5156 | * +---+---+-------------+------+---+------+---+------------------+------+ | |
5157 | */ | |
5158 | static void disas_simd_zip_trn(DisasContext *s, uint32_t insn) | |
5159 | { | |
5fa5469c MM |
5160 | int rd = extract32(insn, 0, 5); |
5161 | int rn = extract32(insn, 5, 5); | |
5162 | int rm = extract32(insn, 16, 5); | |
5163 | int size = extract32(insn, 22, 2); | |
5164 | /* opc field bits [1:0] indicate ZIP/UZP/TRN; | |
5165 | * bit 2 indicates 1 vs 2 variant of the insn. | |
5166 | */ | |
5167 | int opcode = extract32(insn, 12, 2); | |
5168 | bool part = extract32(insn, 14, 1); | |
5169 | bool is_q = extract32(insn, 30, 1); | |
5170 | int esize = 8 << size; | |
5171 | int i, ofs; | |
5172 | int datasize = is_q ? 128 : 64; | |
5173 | int elements = datasize / esize; | |
5174 | TCGv_i64 tcg_res, tcg_resl, tcg_resh; | |
5175 | ||
5176 | if (opcode == 0 || (size == 3 && !is_q)) { | |
5177 | unallocated_encoding(s); | |
5178 | return; | |
5179 | } | |
5180 | ||
8c6afa6a PM |
5181 | if (!fp_access_check(s)) { |
5182 | return; | |
5183 | } | |
5184 | ||
5fa5469c MM |
5185 | tcg_resl = tcg_const_i64(0); |
5186 | tcg_resh = tcg_const_i64(0); | |
5187 | tcg_res = tcg_temp_new_i64(); | |
5188 | ||
5189 | for (i = 0; i < elements; i++) { | |
5190 | switch (opcode) { | |
5191 | case 1: /* UZP1/2 */ | |
5192 | { | |
5193 | int midpoint = elements / 2; | |
5194 | if (i < midpoint) { | |
5195 | read_vec_element(s, tcg_res, rn, 2 * i + part, size); | |
5196 | } else { | |
5197 | read_vec_element(s, tcg_res, rm, | |
5198 | 2 * (i - midpoint) + part, size); | |
5199 | } | |
5200 | break; | |
5201 | } | |
5202 | case 2: /* TRN1/2 */ | |
5203 | if (i & 1) { | |
5204 | read_vec_element(s, tcg_res, rm, (i & ~1) + part, size); | |
5205 | } else { | |
5206 | read_vec_element(s, tcg_res, rn, (i & ~1) + part, size); | |
5207 | } | |
5208 | break; | |
5209 | case 3: /* ZIP1/2 */ | |
5210 | { | |
5211 | int base = part * elements / 2; | |
5212 | if (i & 1) { | |
5213 | read_vec_element(s, tcg_res, rm, base + (i >> 1), size); | |
5214 | } else { | |
5215 | read_vec_element(s, tcg_res, rn, base + (i >> 1), size); | |
5216 | } | |
5217 | break; | |
5218 | } | |
5219 | default: | |
5220 | g_assert_not_reached(); | |
5221 | } | |
5222 | ||
5223 | ofs = i * esize; | |
5224 | if (ofs < 64) { | |
5225 | tcg_gen_shli_i64(tcg_res, tcg_res, ofs); | |
5226 | tcg_gen_or_i64(tcg_resl, tcg_resl, tcg_res); | |
5227 | } else { | |
5228 | tcg_gen_shli_i64(tcg_res, tcg_res, ofs - 64); | |
5229 | tcg_gen_or_i64(tcg_resh, tcg_resh, tcg_res); | |
5230 | } | |
5231 | } | |
5232 | ||
5233 | tcg_temp_free_i64(tcg_res); | |
5234 | ||
5235 | write_vec_element(s, tcg_resl, rd, 0, MO_64); | |
5236 | tcg_temp_free_i64(tcg_resl); | |
5237 | write_vec_element(s, tcg_resh, rd, 1, MO_64); | |
5238 | tcg_temp_free_i64(tcg_resh); | |
384b26fb AB |
5239 | } |
5240 | ||
4a0ff1ce MM |
5241 | static void do_minmaxop(DisasContext *s, TCGv_i32 tcg_elt1, TCGv_i32 tcg_elt2, |
5242 | int opc, bool is_min, TCGv_ptr fpst) | |
5243 | { | |
5244 | /* Helper function for disas_simd_across_lanes: do a single precision | |
5245 | * min/max operation on the specified two inputs, | |
5246 | * and return the result in tcg_elt1. | |
5247 | */ | |
5248 | if (opc == 0xc) { | |
5249 | if (is_min) { | |
5250 | gen_helper_vfp_minnums(tcg_elt1, tcg_elt1, tcg_elt2, fpst); | |
5251 | } else { | |
5252 | gen_helper_vfp_maxnums(tcg_elt1, tcg_elt1, tcg_elt2, fpst); | |
5253 | } | |
5254 | } else { | |
5255 | assert(opc == 0xf); | |
5256 | if (is_min) { | |
5257 | gen_helper_vfp_mins(tcg_elt1, tcg_elt1, tcg_elt2, fpst); | |
5258 | } else { | |
5259 | gen_helper_vfp_maxs(tcg_elt1, tcg_elt1, tcg_elt2, fpst); | |
5260 | } | |
5261 | } | |
5262 | } | |
5263 | ||
384b26fb AB |
5264 | /* C3.6.4 AdvSIMD across lanes |
5265 | * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 | |
5266 | * +---+---+---+-----------+------+-----------+--------+-----+------+------+ | |
5267 | * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd | | |
5268 | * +---+---+---+-----------+------+-----------+--------+-----+------+------+ | |
5269 | */ | |
5270 | static void disas_simd_across_lanes(DisasContext *s, uint32_t insn) | |
5271 | { | |
4a0ff1ce MM |
5272 | int rd = extract32(insn, 0, 5); |
5273 | int rn = extract32(insn, 5, 5); | |
5274 | int size = extract32(insn, 22, 2); | |
5275 | int opcode = extract32(insn, 12, 5); | |
5276 | bool is_q = extract32(insn, 30, 1); | |
5277 | bool is_u = extract32(insn, 29, 1); | |
5278 | bool is_fp = false; | |
5279 | bool is_min = false; | |
5280 | int esize; | |
5281 | int elements; | |
5282 | int i; | |
5283 | TCGv_i64 tcg_res, tcg_elt; | |
5284 | ||
5285 | switch (opcode) { | |
5286 | case 0x1b: /* ADDV */ | |
5287 | if (is_u) { | |
5288 | unallocated_encoding(s); | |
5289 | return; | |
5290 | } | |
5291 | /* fall through */ | |
5292 | case 0x3: /* SADDLV, UADDLV */ | |
5293 | case 0xa: /* SMAXV, UMAXV */ | |
5294 | case 0x1a: /* SMINV, UMINV */ | |
5295 | if (size == 3 || (size == 2 && !is_q)) { | |
5296 | unallocated_encoding(s); | |
5297 | return; | |
5298 | } | |
5299 | break; | |
5300 | case 0xc: /* FMAXNMV, FMINNMV */ | |
5301 | case 0xf: /* FMAXV, FMINV */ | |
5302 | if (!is_u || !is_q || extract32(size, 0, 1)) { | |
5303 | unallocated_encoding(s); | |
5304 | return; | |
5305 | } | |
5306 | /* Bit 1 of size field encodes min vs max, and actual size is always | |
5307 | * 32 bits: adjust the size variable so following code can rely on it | |
5308 | */ | |
5309 | is_min = extract32(size, 1, 1); | |
5310 | is_fp = true; | |
5311 | size = 2; | |
5312 | break; | |
5313 | default: | |
5314 | unallocated_encoding(s); | |
5315 | return; | |
5316 | } | |
5317 | ||
8c6afa6a PM |
5318 | if (!fp_access_check(s)) { |
5319 | return; | |
5320 | } | |
5321 | ||
4a0ff1ce MM |
5322 | esize = 8 << size; |
5323 | elements = (is_q ? 128 : 64) / esize; | |
5324 | ||
5325 | tcg_res = tcg_temp_new_i64(); | |
5326 | tcg_elt = tcg_temp_new_i64(); | |
5327 | ||
5328 | /* These instructions operate across all lanes of a vector | |
5329 | * to produce a single result. We can guarantee that a 64 | |
5330 | * bit intermediate is sufficient: | |
5331 | * + for [US]ADDLV the maximum element size is 32 bits, and | |
5332 | * the result type is 64 bits | |
5333 | * + for FMAX*V, FMIN*V, ADDV the intermediate type is the | |
5334 | * same as the element size, which is 32 bits at most | |
5335 | * For the integer operations we can choose to work at 64 | |
5336 | * or 32 bits and truncate at the end; for simplicity | |
5337 | * we use 64 bits always. The floating point | |
5338 | * ops do require 32 bit intermediates, though. | |
5339 | */ | |
5340 | if (!is_fp) { | |
5341 | read_vec_element(s, tcg_res, rn, 0, size | (is_u ? 0 : MO_SIGN)); | |
5342 | ||
5343 | for (i = 1; i < elements; i++) { | |
5344 | read_vec_element(s, tcg_elt, rn, i, size | (is_u ? 0 : MO_SIGN)); | |
5345 | ||
5346 | switch (opcode) { | |
5347 | case 0x03: /* SADDLV / UADDLV */ | |
5348 | case 0x1b: /* ADDV */ | |
5349 | tcg_gen_add_i64(tcg_res, tcg_res, tcg_elt); | |
5350 | break; | |
5351 | case 0x0a: /* SMAXV / UMAXV */ | |
5352 | tcg_gen_movcond_i64(is_u ? TCG_COND_GEU : TCG_COND_GE, | |
5353 | tcg_res, | |
5354 | tcg_res, tcg_elt, tcg_res, tcg_elt); | |
5355 | break; | |
5356 | case 0x1a: /* SMINV / UMINV */ | |
5357 | tcg_gen_movcond_i64(is_u ? TCG_COND_LEU : TCG_COND_LE, | |
5358 | tcg_res, | |
5359 | tcg_res, tcg_elt, tcg_res, tcg_elt); | |
5360 | break; | |
5361 | break; | |
5362 | default: | |
5363 | g_assert_not_reached(); | |
5364 | } | |
5365 | ||
5366 | } | |
5367 | } else { | |
5368 | /* Floating point ops which work on 32 bit (single) intermediates. | |
5369 | * Note that correct NaN propagation requires that we do these | |
5370 | * operations in exactly the order specified by the pseudocode. | |
5371 | */ | |
5372 | TCGv_i32 tcg_elt1 = tcg_temp_new_i32(); | |
5373 | TCGv_i32 tcg_elt2 = tcg_temp_new_i32(); | |
5374 | TCGv_i32 tcg_elt3 = tcg_temp_new_i32(); | |
5375 | TCGv_ptr fpst = get_fpstatus_ptr(); | |
5376 | ||
5377 | assert(esize == 32); | |
5378 | assert(elements == 4); | |
5379 | ||
5380 | read_vec_element(s, tcg_elt, rn, 0, MO_32); | |
5381 | tcg_gen_trunc_i64_i32(tcg_elt1, tcg_elt); | |
5382 | read_vec_element(s, tcg_elt, rn, 1, MO_32); | |
5383 | tcg_gen_trunc_i64_i32(tcg_elt2, tcg_elt); | |
5384 | ||
5385 | do_minmaxop(s, tcg_elt1, tcg_elt2, opcode, is_min, fpst); | |
5386 | ||
5387 | read_vec_element(s, tcg_elt, rn, 2, MO_32); | |
5388 | tcg_gen_trunc_i64_i32(tcg_elt2, tcg_elt); | |
5389 | read_vec_element(s, tcg_elt, rn, 3, MO_32); | |
5390 | tcg_gen_trunc_i64_i32(tcg_elt3, tcg_elt); | |
5391 | ||
5392 | do_minmaxop(s, tcg_elt2, tcg_elt3, opcode, is_min, fpst); | |
5393 | ||
5394 | do_minmaxop(s, tcg_elt1, tcg_elt2, opcode, is_min, fpst); | |
5395 | ||
5396 | tcg_gen_extu_i32_i64(tcg_res, tcg_elt1); | |
5397 | tcg_temp_free_i32(tcg_elt1); | |
5398 | tcg_temp_free_i32(tcg_elt2); | |
5399 | tcg_temp_free_i32(tcg_elt3); | |
5400 | tcg_temp_free_ptr(fpst); | |
5401 | } | |
5402 | ||
5403 | tcg_temp_free_i64(tcg_elt); | |
5404 | ||
5405 | /* Now truncate the result to the width required for the final output */ | |
5406 | if (opcode == 0x03) { | |
5407 | /* SADDLV, UADDLV: result is 2*esize */ | |
5408 | size++; | |
5409 | } | |
5410 | ||
5411 | switch (size) { | |
5412 | case 0: | |
5413 | tcg_gen_ext8u_i64(tcg_res, tcg_res); | |
5414 | break; | |
5415 | case 1: | |
5416 | tcg_gen_ext16u_i64(tcg_res, tcg_res); | |
5417 | break; | |
5418 | case 2: | |
5419 | tcg_gen_ext32u_i64(tcg_res, tcg_res); | |
5420 | break; | |
5421 | case 3: | |
5422 | break; | |
5423 | default: | |
5424 | g_assert_not_reached(); | |
5425 | } | |
5426 | ||
5427 | write_fp_dreg(s, rd, tcg_res); | |
5428 | tcg_temp_free_i64(tcg_res); | |
384b26fb AB |
5429 | } |
5430 | ||
67bb9389 AB |
5431 | /* C6.3.31 DUP (Element, Vector) |
5432 | * | |
5433 | * 31 30 29 21 20 16 15 10 9 5 4 0 | |
5434 | * +---+---+-------------------+--------+-------------+------+------+ | |
5435 | * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd | | |
5436 | * +---+---+-------------------+--------+-------------+------+------+ | |
5437 | * | |
5438 | * size: encoded in imm5 (see ARM ARM LowestSetBit()) | |
5439 | */ | |
5440 | static void handle_simd_dupe(DisasContext *s, int is_q, int rd, int rn, | |
5441 | int imm5) | |
5442 | { | |
5443 | int size = ctz32(imm5); | |
5444 | int esize = 8 << size; | |
5445 | int elements = (is_q ? 128 : 64) / esize; | |
5446 | int index, i; | |
5447 | TCGv_i64 tmp; | |
5448 | ||
5449 | if (size > 3 || (size == 3 && !is_q)) { | |
5450 | unallocated_encoding(s); | |
5451 | return; | |
5452 | } | |
5453 | ||
8c6afa6a PM |
5454 | if (!fp_access_check(s)) { |
5455 | return; | |
5456 | } | |
5457 | ||
67bb9389 AB |
5458 | index = imm5 >> (size + 1); |
5459 | ||
5460 | tmp = tcg_temp_new_i64(); | |
5461 | read_vec_element(s, tmp, rn, index, size); | |
5462 | ||
5463 | for (i = 0; i < elements; i++) { | |
5464 | write_vec_element(s, tmp, rd, i, size); | |
5465 | } | |
5466 | ||
5467 | if (!is_q) { | |
5468 | clear_vec_high(s, rd); | |
5469 | } | |
5470 | ||
5471 | tcg_temp_free_i64(tmp); | |
5472 | } | |
5473 | ||
360a6f2d PM |
5474 | /* C6.3.31 DUP (element, scalar) |
5475 | * 31 21 20 16 15 10 9 5 4 0 | |
5476 | * +-----------------------+--------+-------------+------+------+ | |
5477 | * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd | | |
5478 | * +-----------------------+--------+-------------+------+------+ | |
5479 | */ | |
5480 | static void handle_simd_dupes(DisasContext *s, int rd, int rn, | |
5481 | int imm5) | |
5482 | { | |
5483 | int size = ctz32(imm5); | |
5484 | int index; | |
5485 | TCGv_i64 tmp; | |
5486 | ||
5487 | if (size > 3) { | |
5488 | unallocated_encoding(s); | |
5489 | return; | |
5490 | } | |
5491 | ||
8c6afa6a PM |
5492 | if (!fp_access_check(s)) { |
5493 | return; | |
5494 | } | |
5495 | ||
360a6f2d PM |
5496 | index = imm5 >> (size + 1); |
5497 | ||
5498 | /* This instruction just extracts the specified element and | |
5499 | * zero-extends it into the bottom of the destination register. | |
5500 | */ | |
5501 | tmp = tcg_temp_new_i64(); | |
5502 | read_vec_element(s, tmp, rn, index, size); | |
5503 | write_fp_dreg(s, rd, tmp); | |
5504 | tcg_temp_free_i64(tmp); | |
5505 | } | |
5506 | ||
67bb9389 AB |
5507 | /* C6.3.32 DUP (General) |
5508 | * | |
5509 | * 31 30 29 21 20 16 15 10 9 5 4 0 | |
5510 | * +---+---+-------------------+--------+-------------+------+------+ | |
5511 | * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd | | |
5512 | * +---+---+-------------------+--------+-------------+------+------+ | |
5513 | * | |
5514 | * size: encoded in imm5 (see ARM ARM LowestSetBit()) | |
5515 | */ | |
5516 | static void handle_simd_dupg(DisasContext *s, int is_q, int rd, int rn, | |
5517 | int imm5) | |
5518 | { | |
5519 | int size = ctz32(imm5); | |
5520 | int esize = 8 << size; | |
5521 | int elements = (is_q ? 128 : 64)/esize; | |
5522 | int i = 0; | |
5523 | ||
5524 | if (size > 3 || ((size == 3) && !is_q)) { | |
5525 | unallocated_encoding(s); | |
5526 | return; | |
5527 | } | |
8c6afa6a PM |
5528 | |
5529 | if (!fp_access_check(s)) { | |
5530 | return; | |
5531 | } | |
5532 | ||
67bb9389 AB |
5533 | for (i = 0; i < elements; i++) { |
5534 | write_vec_element(s, cpu_reg(s, rn), rd, i, size); | |
5535 | } | |
5536 | if (!is_q) { | |
5537 | clear_vec_high(s, rd); | |
5538 | } | |
5539 | } | |
5540 | ||
5541 | /* C6.3.150 INS (Element) | |
5542 | * | |
5543 | * 31 21 20 16 15 14 11 10 9 5 4 0 | |
5544 | * +-----------------------+--------+------------+---+------+------+ | |
5545 | * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd | | |
5546 | * +-----------------------+--------+------------+---+------+------+ | |
5547 | * | |
5548 | * size: encoded in imm5 (see ARM ARM LowestSetBit()) | |
5549 | * index: encoded in imm5<4:size+1> | |
5550 | */ | |
5551 | static void handle_simd_inse(DisasContext *s, int rd, int rn, | |
5552 | int imm4, int imm5) | |
5553 | { | |
5554 | int size = ctz32(imm5); | |
5555 | int src_index, dst_index; | |
5556 | TCGv_i64 tmp; | |
5557 | ||
5558 | if (size > 3) { | |
5559 | unallocated_encoding(s); | |
5560 | return; | |
5561 | } | |
8c6afa6a PM |
5562 | |
5563 | if (!fp_access_check(s)) { | |
5564 | return; | |
5565 | } | |
5566 | ||
67bb9389 AB |
5567 | dst_index = extract32(imm5, 1+size, 5); |
5568 | src_index = extract32(imm4, size, 4); | |
5569 | ||
5570 | tmp = tcg_temp_new_i64(); | |
5571 | ||
5572 | read_vec_element(s, tmp, rn, src_index, size); | |
5573 | write_vec_element(s, tmp, rd, dst_index, size); | |
5574 | ||
5575 | tcg_temp_free_i64(tmp); | |
5576 | } | |
5577 | ||
5578 | ||
5579 | /* C6.3.151 INS (General) | |
5580 | * | |
5581 | * 31 21 20 16 15 10 9 5 4 0 | |
5582 | * +-----------------------+--------+-------------+------+------+ | |
5583 | * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd | | |
5584 | * +-----------------------+--------+-------------+------+------+ | |
5585 | * | |
5586 | * size: encoded in imm5 (see ARM ARM LowestSetBit()) | |
5587 | * index: encoded in imm5<4:size+1> | |
5588 | */ | |
5589 | static void handle_simd_insg(DisasContext *s, int rd, int rn, int imm5) | |
5590 | { | |
5591 | int size = ctz32(imm5); | |
5592 | int idx; | |
5593 | ||
5594 | if (size > 3) { | |
5595 | unallocated_encoding(s); | |
5596 | return; | |
5597 | } | |
5598 | ||
8c6afa6a PM |
5599 | if (!fp_access_check(s)) { |
5600 | return; | |
5601 | } | |
5602 | ||
67bb9389 AB |
5603 | idx = extract32(imm5, 1 + size, 4 - size); |
5604 | write_vec_element(s, cpu_reg(s, rn), rd, idx, size); | |
5605 | } | |
5606 | ||
5607 | /* | |
5608 | * C6.3.321 UMOV (General) | |
5609 | * C6.3.237 SMOV (General) | |
5610 | * | |
5611 | * 31 30 29 21 20 16 15 12 10 9 5 4 0 | |
5612 | * +---+---+-------------------+--------+-------------+------+------+ | |
5613 | * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd | | |
5614 | * +---+---+-------------------+--------+-------------+------+------+ | |
5615 | * | |
5616 | * U: unsigned when set | |
5617 | * size: encoded in imm5 (see ARM ARM LowestSetBit()) | |
5618 | */ | |
5619 | static void handle_simd_umov_smov(DisasContext *s, int is_q, int is_signed, | |
5620 | int rn, int rd, int imm5) | |
5621 | { | |
5622 | int size = ctz32(imm5); | |
5623 | int element; | |
5624 | TCGv_i64 tcg_rd; | |
5625 | ||
5626 | /* Check for UnallocatedEncodings */ | |
5627 | if (is_signed) { | |
5628 | if (size > 2 || (size == 2 && !is_q)) { | |
5629 | unallocated_encoding(s); | |
5630 | return; | |
5631 | } | |
5632 | } else { | |
5633 | if (size > 3 | |
5634 | || (size < 3 && is_q) | |
5635 | || (size == 3 && !is_q)) { | |
5636 | unallocated_encoding(s); | |
5637 | return; | |
5638 | } | |
5639 | } | |
8c6afa6a PM |
5640 | |
5641 | if (!fp_access_check(s)) { | |
5642 | return; | |
5643 | } | |
5644 | ||
67bb9389 AB |
5645 | element = extract32(imm5, 1+size, 4); |
5646 | ||
5647 | tcg_rd = cpu_reg(s, rd); | |
5648 | read_vec_element(s, tcg_rd, rn, element, size | (is_signed ? MO_SIGN : 0)); | |
5649 | if (is_signed && !is_q) { | |
5650 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
5651 | } | |
5652 | } | |
5653 | ||
384b26fb AB |
5654 | /* C3.6.5 AdvSIMD copy |
5655 | * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0 | |
5656 | * +---+---+----+-----------------+------+---+------+---+------+------+ | |
5657 | * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd | | |
5658 | * +---+---+----+-----------------+------+---+------+---+------+------+ | |
5659 | */ | |
5660 | static void disas_simd_copy(DisasContext *s, uint32_t insn) | |
5661 | { | |
67bb9389 AB |
5662 | int rd = extract32(insn, 0, 5); |
5663 | int rn = extract32(insn, 5, 5); | |
5664 | int imm4 = extract32(insn, 11, 4); | |
5665 | int op = extract32(insn, 29, 1); | |
5666 | int is_q = extract32(insn, 30, 1); | |
5667 | int imm5 = extract32(insn, 16, 5); | |
5668 | ||
5669 | if (op) { | |
5670 | if (is_q) { | |
5671 | /* INS (element) */ | |
5672 | handle_simd_inse(s, rd, rn, imm4, imm5); | |
5673 | } else { | |
5674 | unallocated_encoding(s); | |
5675 | } | |
5676 | } else { | |
5677 | switch (imm4) { | |
5678 | case 0: | |
5679 | /* DUP (element - vector) */ | |
5680 | handle_simd_dupe(s, is_q, rd, rn, imm5); | |
5681 | break; | |
5682 | case 1: | |
5683 | /* DUP (general) */ | |
5684 | handle_simd_dupg(s, is_q, rd, rn, imm5); | |
5685 | break; | |
5686 | case 3: | |
5687 | if (is_q) { | |
5688 | /* INS (general) */ | |
5689 | handle_simd_insg(s, rd, rn, imm5); | |
5690 | } else { | |
5691 | unallocated_encoding(s); | |
5692 | } | |
5693 | break; | |
5694 | case 5: | |
5695 | case 7: | |
5696 | /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */ | |
5697 | handle_simd_umov_smov(s, is_q, (imm4 == 5), rn, rd, imm5); | |
5698 | break; | |
5699 | default: | |
5700 | unallocated_encoding(s); | |
5701 | break; | |
5702 | } | |
5703 | } | |
384b26fb AB |
5704 | } |
5705 | ||
5706 | /* C3.6.6 AdvSIMD modified immediate | |
5707 | * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0 | |
5708 | * +---+---+----+---------------------+-----+-------+----+---+-------+------+ | |
5709 | * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd | | |
5710 | * +---+---+----+---------------------+-----+-------+----+---+-------+------+ | |
f3f8c4f4 AB |
5711 | * |
5712 | * There are a number of operations that can be carried out here: | |
5713 | * MOVI - move (shifted) imm into register | |
5714 | * MVNI - move inverted (shifted) imm into register | |
5715 | * ORR - bitwise OR of (shifted) imm with register | |
5716 | * BIC - bitwise clear of (shifted) imm with register | |
384b26fb AB |
5717 | */ |
5718 | static void disas_simd_mod_imm(DisasContext *s, uint32_t insn) | |
5719 | { | |
f3f8c4f4 AB |
5720 | int rd = extract32(insn, 0, 5); |
5721 | int cmode = extract32(insn, 12, 4); | |
5722 | int cmode_3_1 = extract32(cmode, 1, 3); | |
5723 | int cmode_0 = extract32(cmode, 0, 1); | |
5724 | int o2 = extract32(insn, 11, 1); | |
5725 | uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5); | |
5726 | bool is_neg = extract32(insn, 29, 1); | |
5727 | bool is_q = extract32(insn, 30, 1); | |
5728 | uint64_t imm = 0; | |
5729 | TCGv_i64 tcg_rd, tcg_imm; | |
5730 | int i; | |
5731 | ||
5732 | if (o2 != 0 || ((cmode == 0xf) && is_neg && !is_q)) { | |
5733 | unallocated_encoding(s); | |
5734 | return; | |
5735 | } | |
5736 | ||
8c6afa6a PM |
5737 | if (!fp_access_check(s)) { |
5738 | return; | |
5739 | } | |
5740 | ||
f3f8c4f4 AB |
5741 | /* See AdvSIMDExpandImm() in ARM ARM */ |
5742 | switch (cmode_3_1) { | |
5743 | case 0: /* Replicate(Zeros(24):imm8, 2) */ | |
5744 | case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */ | |
5745 | case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */ | |
5746 | case 3: /* Replicate(imm8:Zeros(24), 2) */ | |
5747 | { | |
5748 | int shift = cmode_3_1 * 8; | |
5749 | imm = bitfield_replicate(abcdefgh << shift, 32); | |
5750 | break; | |
5751 | } | |
5752 | case 4: /* Replicate(Zeros(8):imm8, 4) */ | |
5753 | case 5: /* Replicate(imm8:Zeros(8), 4) */ | |
5754 | { | |
5755 | int shift = (cmode_3_1 & 0x1) * 8; | |
5756 | imm = bitfield_replicate(abcdefgh << shift, 16); | |
5757 | break; | |
5758 | } | |
5759 | case 6: | |
5760 | if (cmode_0) { | |
5761 | /* Replicate(Zeros(8):imm8:Ones(16), 2) */ | |
5762 | imm = (abcdefgh << 16) | 0xffff; | |
5763 | } else { | |
5764 | /* Replicate(Zeros(16):imm8:Ones(8), 2) */ | |
5765 | imm = (abcdefgh << 8) | 0xff; | |
5766 | } | |
5767 | imm = bitfield_replicate(imm, 32); | |
5768 | break; | |
5769 | case 7: | |
5770 | if (!cmode_0 && !is_neg) { | |
5771 | imm = bitfield_replicate(abcdefgh, 8); | |
5772 | } else if (!cmode_0 && is_neg) { | |
5773 | int i; | |
5774 | imm = 0; | |
5775 | for (i = 0; i < 8; i++) { | |
5776 | if ((abcdefgh) & (1 << i)) { | |
5777 | imm |= 0xffULL << (i * 8); | |
5778 | } | |
5779 | } | |
5780 | } else if (cmode_0) { | |
5781 | if (is_neg) { | |
5782 | imm = (abcdefgh & 0x3f) << 48; | |
5783 | if (abcdefgh & 0x80) { | |
5784 | imm |= 0x8000000000000000ULL; | |
5785 | } | |
5786 | if (abcdefgh & 0x40) { | |
5787 | imm |= 0x3fc0000000000000ULL; | |
5788 | } else { | |
5789 | imm |= 0x4000000000000000ULL; | |
5790 | } | |
5791 | } else { | |
5792 | imm = (abcdefgh & 0x3f) << 19; | |
5793 | if (abcdefgh & 0x80) { | |
5794 | imm |= 0x80000000; | |
5795 | } | |
5796 | if (abcdefgh & 0x40) { | |
5797 | imm |= 0x3e000000; | |
5798 | } else { | |
5799 | imm |= 0x40000000; | |
5800 | } | |
5801 | imm |= (imm << 32); | |
5802 | } | |
5803 | } | |
5804 | break; | |
5805 | } | |
5806 | ||
5807 | if (cmode_3_1 != 7 && is_neg) { | |
5808 | imm = ~imm; | |
5809 | } | |
5810 | ||
5811 | tcg_imm = tcg_const_i64(imm); | |
5812 | tcg_rd = new_tmp_a64(s); | |
5813 | ||
5814 | for (i = 0; i < 2; i++) { | |
90e49638 | 5815 | int foffs = i ? fp_reg_hi_offset(s, rd) : fp_reg_offset(s, rd, MO_64); |
f3f8c4f4 AB |
5816 | |
5817 | if (i == 1 && !is_q) { | |
5818 | /* non-quad ops clear high half of vector */ | |
5819 | tcg_gen_movi_i64(tcg_rd, 0); | |
5820 | } else if ((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9) { | |
5821 | tcg_gen_ld_i64(tcg_rd, cpu_env, foffs); | |
5822 | if (is_neg) { | |
5823 | /* AND (BIC) */ | |
5824 | tcg_gen_and_i64(tcg_rd, tcg_rd, tcg_imm); | |
5825 | } else { | |
5826 | /* ORR */ | |
5827 | tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_imm); | |
5828 | } | |
5829 | } else { | |
5830 | /* MOVI */ | |
5831 | tcg_gen_mov_i64(tcg_rd, tcg_imm); | |
5832 | } | |
5833 | tcg_gen_st_i64(tcg_rd, cpu_env, foffs); | |
5834 | } | |
5835 | ||
5836 | tcg_temp_free_i64(tcg_imm); | |
384b26fb AB |
5837 | } |
5838 | ||
5839 | /* C3.6.7 AdvSIMD scalar copy | |
5840 | * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0 | |
5841 | * +-----+----+-----------------+------+---+------+---+------+------+ | |
5842 | * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd | | |
5843 | * +-----+----+-----------------+------+---+------+---+------+------+ | |
5844 | */ | |
5845 | static void disas_simd_scalar_copy(DisasContext *s, uint32_t insn) | |
5846 | { | |
360a6f2d PM |
5847 | int rd = extract32(insn, 0, 5); |
5848 | int rn = extract32(insn, 5, 5); | |
5849 | int imm4 = extract32(insn, 11, 4); | |
5850 | int imm5 = extract32(insn, 16, 5); | |
5851 | int op = extract32(insn, 29, 1); | |
5852 | ||
5853 | if (op != 0 || imm4 != 0) { | |
5854 | unallocated_encoding(s); | |
5855 | return; | |
5856 | } | |
5857 | ||
5858 | /* DUP (element, scalar) */ | |
5859 | handle_simd_dupes(s, rd, rn, imm5); | |
384b26fb AB |
5860 | } |
5861 | ||
5862 | /* C3.6.8 AdvSIMD scalar pairwise | |
5863 | * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 | |
5864 | * +-----+---+-----------+------+-----------+--------+-----+------+------+ | |
5865 | * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd | | |
5866 | * +-----+---+-----------+------+-----------+--------+-----+------+------+ | |
5867 | */ | |
5868 | static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn) | |
5869 | { | |
3720a7ea PM |
5870 | int u = extract32(insn, 29, 1); |
5871 | int size = extract32(insn, 22, 2); | |
5872 | int opcode = extract32(insn, 12, 5); | |
5873 | int rn = extract32(insn, 5, 5); | |
5874 | int rd = extract32(insn, 0, 5); | |
5875 | TCGv_ptr fpst; | |
5876 | ||
5877 | /* For some ops (the FP ones), size[1] is part of the encoding. | |
5878 | * For ADDP strictly it is not but size[1] is always 1 for valid | |
5879 | * encodings. | |
5880 | */ | |
5881 | opcode |= (extract32(size, 1, 1) << 5); | |
5882 | ||
5883 | switch (opcode) { | |
5884 | case 0x3b: /* ADDP */ | |
5885 | if (u || size != 3) { | |
5886 | unallocated_encoding(s); | |
5887 | return; | |
5888 | } | |
8c6afa6a PM |
5889 | if (!fp_access_check(s)) { |
5890 | return; | |
5891 | } | |
5892 | ||
3720a7ea PM |
5893 | TCGV_UNUSED_PTR(fpst); |
5894 | break; | |
5895 | case 0xc: /* FMAXNMP */ | |
5896 | case 0xd: /* FADDP */ | |
5897 | case 0xf: /* FMAXP */ | |
5898 | case 0x2c: /* FMINNMP */ | |
5899 | case 0x2f: /* FMINP */ | |
5900 | /* FP op, size[0] is 32 or 64 bit */ | |
5901 | if (!u) { | |
5902 | unallocated_encoding(s); | |
5903 | return; | |
5904 | } | |
8c6afa6a PM |
5905 | if (!fp_access_check(s)) { |
5906 | return; | |
5907 | } | |
5908 | ||
3720a7ea PM |
5909 | size = extract32(size, 0, 1) ? 3 : 2; |
5910 | fpst = get_fpstatus_ptr(); | |
5911 | break; | |
5912 | default: | |
5913 | unallocated_encoding(s); | |
5914 | return; | |
5915 | } | |
5916 | ||
5917 | if (size == 3) { | |
5918 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
5919 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
5920 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
5921 | ||
5922 | read_vec_element(s, tcg_op1, rn, 0, MO_64); | |
5923 | read_vec_element(s, tcg_op2, rn, 1, MO_64); | |
5924 | ||
5925 | switch (opcode) { | |
5926 | case 0x3b: /* ADDP */ | |
5927 | tcg_gen_add_i64(tcg_res, tcg_op1, tcg_op2); | |
5928 | break; | |
5929 | case 0xc: /* FMAXNMP */ | |
5930 | gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
5931 | break; | |
5932 | case 0xd: /* FADDP */ | |
5933 | gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst); | |
5934 | break; | |
5935 | case 0xf: /* FMAXP */ | |
5936 | gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst); | |
5937 | break; | |
5938 | case 0x2c: /* FMINNMP */ | |
5939 | gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
5940 | break; | |
5941 | case 0x2f: /* FMINP */ | |
5942 | gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst); | |
5943 | break; | |
5944 | default: | |
5945 | g_assert_not_reached(); | |
5946 | } | |
5947 | ||
5948 | write_fp_dreg(s, rd, tcg_res); | |
5949 | ||
5950 | tcg_temp_free_i64(tcg_op1); | |
5951 | tcg_temp_free_i64(tcg_op2); | |
5952 | tcg_temp_free_i64(tcg_res); | |
5953 | } else { | |
5954 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
5955 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
5956 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
5957 | ||
5958 | read_vec_element_i32(s, tcg_op1, rn, 0, MO_32); | |
5959 | read_vec_element_i32(s, tcg_op2, rn, 1, MO_32); | |
5960 | ||
5961 | switch (opcode) { | |
5962 | case 0xc: /* FMAXNMP */ | |
5963 | gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
5964 | break; | |
5965 | case 0xd: /* FADDP */ | |
5966 | gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst); | |
5967 | break; | |
5968 | case 0xf: /* FMAXP */ | |
5969 | gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst); | |
5970 | break; | |
5971 | case 0x2c: /* FMINNMP */ | |
5972 | gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
5973 | break; | |
5974 | case 0x2f: /* FMINP */ | |
5975 | gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst); | |
5976 | break; | |
5977 | default: | |
5978 | g_assert_not_reached(); | |
5979 | } | |
5980 | ||
5981 | write_fp_sreg(s, rd, tcg_res); | |
5982 | ||
5983 | tcg_temp_free_i32(tcg_op1); | |
5984 | tcg_temp_free_i32(tcg_op2); | |
5985 | tcg_temp_free_i32(tcg_res); | |
5986 | } | |
5987 | ||
5988 | if (!TCGV_IS_UNUSED_PTR(fpst)) { | |
5989 | tcg_temp_free_ptr(fpst); | |
5990 | } | |
384b26fb AB |
5991 | } |
5992 | ||
4d1cef84 AB |
5993 | /* |
5994 | * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate) | |
5995 | * | |
5996 | * This code is handles the common shifting code and is used by both | |
5997 | * the vector and scalar code. | |
5998 | */ | |
5999 | static void handle_shri_with_rndacc(TCGv_i64 tcg_res, TCGv_i64 tcg_src, | |
6000 | TCGv_i64 tcg_rnd, bool accumulate, | |
6001 | bool is_u, int size, int shift) | |
6002 | { | |
6003 | bool extended_result = false; | |
6004 | bool round = !TCGV_IS_UNUSED_I64(tcg_rnd); | |
6005 | int ext_lshift = 0; | |
6006 | TCGv_i64 tcg_src_hi; | |
6007 | ||
6008 | if (round && size == 3) { | |
6009 | extended_result = true; | |
6010 | ext_lshift = 64 - shift; | |
6011 | tcg_src_hi = tcg_temp_new_i64(); | |
6012 | } else if (shift == 64) { | |
6013 | if (!accumulate && is_u) { | |
6014 | /* result is zero */ | |
6015 | tcg_gen_movi_i64(tcg_res, 0); | |
6016 | return; | |
6017 | } | |
6018 | } | |
6019 | ||
6020 | /* Deal with the rounding step */ | |
6021 | if (round) { | |
6022 | if (extended_result) { | |
6023 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
6024 | if (!is_u) { | |
6025 | /* take care of sign extending tcg_res */ | |
6026 | tcg_gen_sari_i64(tcg_src_hi, tcg_src, 63); | |
6027 | tcg_gen_add2_i64(tcg_src, tcg_src_hi, | |
6028 | tcg_src, tcg_src_hi, | |
6029 | tcg_rnd, tcg_zero); | |
6030 | } else { | |
6031 | tcg_gen_add2_i64(tcg_src, tcg_src_hi, | |
6032 | tcg_src, tcg_zero, | |
6033 | tcg_rnd, tcg_zero); | |
6034 | } | |
6035 | tcg_temp_free_i64(tcg_zero); | |
6036 | } else { | |
6037 | tcg_gen_add_i64(tcg_src, tcg_src, tcg_rnd); | |
6038 | } | |
6039 | } | |
6040 | ||
6041 | /* Now do the shift right */ | |
6042 | if (round && extended_result) { | |
6043 | /* extended case, >64 bit precision required */ | |
6044 | if (ext_lshift == 0) { | |
6045 | /* special case, only high bits matter */ | |
6046 | tcg_gen_mov_i64(tcg_src, tcg_src_hi); | |
6047 | } else { | |
6048 | tcg_gen_shri_i64(tcg_src, tcg_src, shift); | |
6049 | tcg_gen_shli_i64(tcg_src_hi, tcg_src_hi, ext_lshift); | |
6050 | tcg_gen_or_i64(tcg_src, tcg_src, tcg_src_hi); | |
6051 | } | |
6052 | } else { | |
6053 | if (is_u) { | |
6054 | if (shift == 64) { | |
6055 | /* essentially shifting in 64 zeros */ | |
6056 | tcg_gen_movi_i64(tcg_src, 0); | |
6057 | } else { | |
6058 | tcg_gen_shri_i64(tcg_src, tcg_src, shift); | |
6059 | } | |
6060 | } else { | |
6061 | if (shift == 64) { | |
6062 | /* effectively extending the sign-bit */ | |
6063 | tcg_gen_sari_i64(tcg_src, tcg_src, 63); | |
6064 | } else { | |
6065 | tcg_gen_sari_i64(tcg_src, tcg_src, shift); | |
6066 | } | |
6067 | } | |
6068 | } | |
6069 | ||
6070 | if (accumulate) { | |
6071 | tcg_gen_add_i64(tcg_res, tcg_res, tcg_src); | |
6072 | } else { | |
6073 | tcg_gen_mov_i64(tcg_res, tcg_src); | |
6074 | } | |
6075 | ||
6076 | if (extended_result) { | |
6077 | tcg_temp_free_i64(tcg_src_hi); | |
6078 | } | |
6079 | } | |
6080 | ||
6081 | /* Common SHL/SLI - Shift left with an optional insert */ | |
6082 | static void handle_shli_with_ins(TCGv_i64 tcg_res, TCGv_i64 tcg_src, | |
6083 | bool insert, int shift) | |
6084 | { | |
6085 | if (insert) { /* SLI */ | |
6086 | tcg_gen_deposit_i64(tcg_res, tcg_res, tcg_src, shift, 64 - shift); | |
6087 | } else { /* SHL */ | |
6088 | tcg_gen_shli_i64(tcg_res, tcg_src, shift); | |
6089 | } | |
6090 | } | |
6091 | ||
37a706ad PM |
6092 | /* SRI: shift right with insert */ |
6093 | static void handle_shri_with_ins(TCGv_i64 tcg_res, TCGv_i64 tcg_src, | |
6094 | int size, int shift) | |
6095 | { | |
6096 | int esize = 8 << size; | |
6097 | ||
6098 | /* shift count same as element size is valid but does nothing; | |
6099 | * special case to avoid potential shift by 64. | |
6100 | */ | |
6101 | if (shift != esize) { | |
6102 | tcg_gen_shri_i64(tcg_src, tcg_src, shift); | |
6103 | tcg_gen_deposit_i64(tcg_res, tcg_res, tcg_src, 0, esize - shift); | |
6104 | } | |
6105 | } | |
6106 | ||
4d1cef84 AB |
6107 | /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */ |
6108 | static void handle_scalar_simd_shri(DisasContext *s, | |
6109 | bool is_u, int immh, int immb, | |
6110 | int opcode, int rn, int rd) | |
6111 | { | |
6112 | const int size = 3; | |
6113 | int immhb = immh << 3 | immb; | |
6114 | int shift = 2 * (8 << size) - immhb; | |
6115 | bool accumulate = false; | |
6116 | bool round = false; | |
37a706ad | 6117 | bool insert = false; |
4d1cef84 AB |
6118 | TCGv_i64 tcg_rn; |
6119 | TCGv_i64 tcg_rd; | |
6120 | TCGv_i64 tcg_round; | |
6121 | ||
6122 | if (!extract32(immh, 3, 1)) { | |
6123 | unallocated_encoding(s); | |
6124 | return; | |
6125 | } | |
6126 | ||
8c6afa6a PM |
6127 | if (!fp_access_check(s)) { |
6128 | return; | |
6129 | } | |
6130 | ||
4d1cef84 AB |
6131 | switch (opcode) { |
6132 | case 0x02: /* SSRA / USRA (accumulate) */ | |
6133 | accumulate = true; | |
6134 | break; | |
6135 | case 0x04: /* SRSHR / URSHR (rounding) */ | |
6136 | round = true; | |
6137 | break; | |
6138 | case 0x06: /* SRSRA / URSRA (accum + rounding) */ | |
6139 | accumulate = round = true; | |
6140 | break; | |
37a706ad PM |
6141 | case 0x08: /* SRI */ |
6142 | insert = true; | |
6143 | break; | |
4d1cef84 AB |
6144 | } |
6145 | ||
6146 | if (round) { | |
6147 | uint64_t round_const = 1ULL << (shift - 1); | |
6148 | tcg_round = tcg_const_i64(round_const); | |
6149 | } else { | |
6150 | TCGV_UNUSED_I64(tcg_round); | |
6151 | } | |
6152 | ||
6153 | tcg_rn = read_fp_dreg(s, rn); | |
37a706ad | 6154 | tcg_rd = (accumulate || insert) ? read_fp_dreg(s, rd) : tcg_temp_new_i64(); |
4d1cef84 | 6155 | |
37a706ad PM |
6156 | if (insert) { |
6157 | handle_shri_with_ins(tcg_rd, tcg_rn, size, shift); | |
6158 | } else { | |
6159 | handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round, | |
6160 | accumulate, is_u, size, shift); | |
6161 | } | |
4d1cef84 AB |
6162 | |
6163 | write_fp_dreg(s, rd, tcg_rd); | |
6164 | ||
6165 | tcg_temp_free_i64(tcg_rn); | |
6166 | tcg_temp_free_i64(tcg_rd); | |
6167 | if (round) { | |
6168 | tcg_temp_free_i64(tcg_round); | |
6169 | } | |
6170 | } | |
6171 | ||
6172 | /* SHL/SLI - Scalar shift left */ | |
6173 | static void handle_scalar_simd_shli(DisasContext *s, bool insert, | |
6174 | int immh, int immb, int opcode, | |
6175 | int rn, int rd) | |
6176 | { | |
6177 | int size = 32 - clz32(immh) - 1; | |
6178 | int immhb = immh << 3 | immb; | |
6179 | int shift = immhb - (8 << size); | |
6180 | TCGv_i64 tcg_rn = new_tmp_a64(s); | |
6181 | TCGv_i64 tcg_rd = new_tmp_a64(s); | |
6182 | ||
6183 | if (!extract32(immh, 3, 1)) { | |
6184 | unallocated_encoding(s); | |
6185 | return; | |
6186 | } | |
6187 | ||
8c6afa6a PM |
6188 | if (!fp_access_check(s)) { |
6189 | return; | |
6190 | } | |
6191 | ||
4d1cef84 AB |
6192 | tcg_rn = read_fp_dreg(s, rn); |
6193 | tcg_rd = insert ? read_fp_dreg(s, rd) : tcg_temp_new_i64(); | |
6194 | ||
6195 | handle_shli_with_ins(tcg_rd, tcg_rn, insert, shift); | |
6196 | ||
6197 | write_fp_dreg(s, rd, tcg_rd); | |
6198 | ||
6199 | tcg_temp_free_i64(tcg_rn); | |
6200 | tcg_temp_free_i64(tcg_rd); | |
6201 | } | |
6202 | ||
c1b876b2 AB |
6203 | /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with |
6204 | * (signed/unsigned) narrowing */ | |
6205 | static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q, | |
6206 | bool is_u_shift, bool is_u_narrow, | |
6207 | int immh, int immb, int opcode, | |
6208 | int rn, int rd) | |
6209 | { | |
6210 | int immhb = immh << 3 | immb; | |
6211 | int size = 32 - clz32(immh) - 1; | |
6212 | int esize = 8 << size; | |
6213 | int shift = (2 * esize) - immhb; | |
6214 | int elements = is_scalar ? 1 : (64 / esize); | |
6215 | bool round = extract32(opcode, 0, 1); | |
6216 | TCGMemOp ldop = (size + 1) | (is_u_shift ? 0 : MO_SIGN); | |
6217 | TCGv_i64 tcg_rn, tcg_rd, tcg_round; | |
6218 | TCGv_i32 tcg_rd_narrowed; | |
6219 | TCGv_i64 tcg_final; | |
6220 | ||
6221 | static NeonGenNarrowEnvFn * const signed_narrow_fns[4][2] = { | |
6222 | { gen_helper_neon_narrow_sat_s8, | |
6223 | gen_helper_neon_unarrow_sat8 }, | |
6224 | { gen_helper_neon_narrow_sat_s16, | |
6225 | gen_helper_neon_unarrow_sat16 }, | |
6226 | { gen_helper_neon_narrow_sat_s32, | |
6227 | gen_helper_neon_unarrow_sat32 }, | |
6228 | { NULL, NULL }, | |
6229 | }; | |
6230 | static NeonGenNarrowEnvFn * const unsigned_narrow_fns[4] = { | |
6231 | gen_helper_neon_narrow_sat_u8, | |
6232 | gen_helper_neon_narrow_sat_u16, | |
6233 | gen_helper_neon_narrow_sat_u32, | |
6234 | NULL | |
6235 | }; | |
6236 | NeonGenNarrowEnvFn *narrowfn; | |
6237 | ||
6238 | int i; | |
6239 | ||
6240 | assert(size < 4); | |
6241 | ||
6242 | if (extract32(immh, 3, 1)) { | |
6243 | unallocated_encoding(s); | |
6244 | return; | |
6245 | } | |
6246 | ||
8c6afa6a PM |
6247 | if (!fp_access_check(s)) { |
6248 | return; | |
6249 | } | |
6250 | ||
c1b876b2 AB |
6251 | if (is_u_shift) { |
6252 | narrowfn = unsigned_narrow_fns[size]; | |
6253 | } else { | |
6254 | narrowfn = signed_narrow_fns[size][is_u_narrow ? 1 : 0]; | |
6255 | } | |
6256 | ||
6257 | tcg_rn = tcg_temp_new_i64(); | |
6258 | tcg_rd = tcg_temp_new_i64(); | |
6259 | tcg_rd_narrowed = tcg_temp_new_i32(); | |
6260 | tcg_final = tcg_const_i64(0); | |
6261 | ||
6262 | if (round) { | |
6263 | uint64_t round_const = 1ULL << (shift - 1); | |
6264 | tcg_round = tcg_const_i64(round_const); | |
6265 | } else { | |
6266 | TCGV_UNUSED_I64(tcg_round); | |
6267 | } | |
6268 | ||
6269 | for (i = 0; i < elements; i++) { | |
6270 | read_vec_element(s, tcg_rn, rn, i, ldop); | |
6271 | handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round, | |
6272 | false, is_u_shift, size+1, shift); | |
6273 | narrowfn(tcg_rd_narrowed, cpu_env, tcg_rd); | |
6274 | tcg_gen_extu_i32_i64(tcg_rd, tcg_rd_narrowed); | |
6275 | tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize); | |
6276 | } | |
6277 | ||
6278 | if (!is_q) { | |
6279 | clear_vec_high(s, rd); | |
6280 | write_vec_element(s, tcg_final, rd, 0, MO_64); | |
6281 | } else { | |
6282 | write_vec_element(s, tcg_final, rd, 1, MO_64); | |
6283 | } | |
6284 | ||
6285 | if (round) { | |
6286 | tcg_temp_free_i64(tcg_round); | |
6287 | } | |
6288 | tcg_temp_free_i64(tcg_rn); | |
6289 | tcg_temp_free_i64(tcg_rd); | |
6290 | tcg_temp_free_i32(tcg_rd_narrowed); | |
6291 | tcg_temp_free_i64(tcg_final); | |
6292 | return; | |
6293 | } | |
6294 | ||
a847f32c PM |
6295 | /* SQSHLU, UQSHL, SQSHL: saturating left shifts */ |
6296 | static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q, | |
6297 | bool src_unsigned, bool dst_unsigned, | |
6298 | int immh, int immb, int rn, int rd) | |
6299 | { | |
6300 | int immhb = immh << 3 | immb; | |
6301 | int size = 32 - clz32(immh) - 1; | |
6302 | int shift = immhb - (8 << size); | |
6303 | int pass; | |
6304 | ||
6305 | assert(immh != 0); | |
6306 | assert(!(scalar && is_q)); | |
6307 | ||
6308 | if (!scalar) { | |
6309 | if (!is_q && extract32(immh, 3, 1)) { | |
6310 | unallocated_encoding(s); | |
6311 | return; | |
6312 | } | |
6313 | ||
6314 | /* Since we use the variable-shift helpers we must | |
6315 | * replicate the shift count into each element of | |
6316 | * the tcg_shift value. | |
6317 | */ | |
6318 | switch (size) { | |
6319 | case 0: | |
6320 | shift |= shift << 8; | |
6321 | /* fall through */ | |
6322 | case 1: | |
6323 | shift |= shift << 16; | |
6324 | break; | |
6325 | case 2: | |
6326 | case 3: | |
6327 | break; | |
6328 | default: | |
6329 | g_assert_not_reached(); | |
6330 | } | |
6331 | } | |
6332 | ||
8c6afa6a PM |
6333 | if (!fp_access_check(s)) { |
6334 | return; | |
6335 | } | |
6336 | ||
a847f32c PM |
6337 | if (size == 3) { |
6338 | TCGv_i64 tcg_shift = tcg_const_i64(shift); | |
6339 | static NeonGenTwo64OpEnvFn * const fns[2][2] = { | |
6340 | { gen_helper_neon_qshl_s64, gen_helper_neon_qshlu_s64 }, | |
6341 | { NULL, gen_helper_neon_qshl_u64 }, | |
6342 | }; | |
6343 | NeonGenTwo64OpEnvFn *genfn = fns[src_unsigned][dst_unsigned]; | |
6344 | int maxpass = is_q ? 2 : 1; | |
6345 | ||
6346 | for (pass = 0; pass < maxpass; pass++) { | |
6347 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | |
6348 | ||
6349 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
6350 | genfn(tcg_op, cpu_env, tcg_op, tcg_shift); | |
6351 | write_vec_element(s, tcg_op, rd, pass, MO_64); | |
6352 | ||
6353 | tcg_temp_free_i64(tcg_op); | |
6354 | } | |
6355 | tcg_temp_free_i64(tcg_shift); | |
6356 | ||
6357 | if (!is_q) { | |
6358 | clear_vec_high(s, rd); | |
6359 | } | |
6360 | } else { | |
6361 | TCGv_i32 tcg_shift = tcg_const_i32(shift); | |
6362 | static NeonGenTwoOpEnvFn * const fns[2][2][3] = { | |
6363 | { | |
6364 | { gen_helper_neon_qshl_s8, | |
6365 | gen_helper_neon_qshl_s16, | |
6366 | gen_helper_neon_qshl_s32 }, | |
6367 | { gen_helper_neon_qshlu_s8, | |
6368 | gen_helper_neon_qshlu_s16, | |
6369 | gen_helper_neon_qshlu_s32 } | |
6370 | }, { | |
6371 | { NULL, NULL, NULL }, | |
6372 | { gen_helper_neon_qshl_u8, | |
6373 | gen_helper_neon_qshl_u16, | |
6374 | gen_helper_neon_qshl_u32 } | |
6375 | } | |
6376 | }; | |
6377 | NeonGenTwoOpEnvFn *genfn = fns[src_unsigned][dst_unsigned][size]; | |
6378 | TCGMemOp memop = scalar ? size : MO_32; | |
6379 | int maxpass = scalar ? 1 : is_q ? 4 : 2; | |
6380 | ||
6381 | for (pass = 0; pass < maxpass; pass++) { | |
6382 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
6383 | ||
6384 | read_vec_element_i32(s, tcg_op, rn, pass, memop); | |
6385 | genfn(tcg_op, cpu_env, tcg_op, tcg_shift); | |
6386 | if (scalar) { | |
6387 | switch (size) { | |
6388 | case 0: | |
6389 | tcg_gen_ext8u_i32(tcg_op, tcg_op); | |
6390 | break; | |
6391 | case 1: | |
6392 | tcg_gen_ext16u_i32(tcg_op, tcg_op); | |
6393 | break; | |
6394 | case 2: | |
6395 | break; | |
6396 | default: | |
6397 | g_assert_not_reached(); | |
6398 | } | |
6399 | write_fp_sreg(s, rd, tcg_op); | |
6400 | } else { | |
6401 | write_vec_element_i32(s, tcg_op, rd, pass, MO_32); | |
6402 | } | |
6403 | ||
6404 | tcg_temp_free_i32(tcg_op); | |
6405 | } | |
6406 | tcg_temp_free_i32(tcg_shift); | |
6407 | ||
6408 | if (!is_q && !scalar) { | |
6409 | clear_vec_high(s, rd); | |
6410 | } | |
6411 | } | |
6412 | } | |
6413 | ||
10113b69 AB |
6414 | /* Common vector code for handling integer to FP conversion */ |
6415 | static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn, | |
6416 | int elements, int is_signed, | |
6417 | int fracbits, int size) | |
6418 | { | |
6419 | bool is_double = size == 3 ? true : false; | |
6420 | TCGv_ptr tcg_fpst = get_fpstatus_ptr(); | |
6421 | TCGv_i32 tcg_shift = tcg_const_i32(fracbits); | |
6422 | TCGv_i64 tcg_int = tcg_temp_new_i64(); | |
6423 | TCGMemOp mop = size | (is_signed ? MO_SIGN : 0); | |
6424 | int pass; | |
6425 | ||
6426 | for (pass = 0; pass < elements; pass++) { | |
6427 | read_vec_element(s, tcg_int, rn, pass, mop); | |
6428 | ||
6429 | if (is_double) { | |
6430 | TCGv_i64 tcg_double = tcg_temp_new_i64(); | |
6431 | if (is_signed) { | |
6432 | gen_helper_vfp_sqtod(tcg_double, tcg_int, | |
6433 | tcg_shift, tcg_fpst); | |
6434 | } else { | |
6435 | gen_helper_vfp_uqtod(tcg_double, tcg_int, | |
6436 | tcg_shift, tcg_fpst); | |
6437 | } | |
6438 | if (elements == 1) { | |
6439 | write_fp_dreg(s, rd, tcg_double); | |
6440 | } else { | |
6441 | write_vec_element(s, tcg_double, rd, pass, MO_64); | |
6442 | } | |
6443 | tcg_temp_free_i64(tcg_double); | |
6444 | } else { | |
6445 | TCGv_i32 tcg_single = tcg_temp_new_i32(); | |
6446 | if (is_signed) { | |
6447 | gen_helper_vfp_sqtos(tcg_single, tcg_int, | |
6448 | tcg_shift, tcg_fpst); | |
6449 | } else { | |
6450 | gen_helper_vfp_uqtos(tcg_single, tcg_int, | |
6451 | tcg_shift, tcg_fpst); | |
6452 | } | |
6453 | if (elements == 1) { | |
6454 | write_fp_sreg(s, rd, tcg_single); | |
6455 | } else { | |
6456 | write_vec_element_i32(s, tcg_single, rd, pass, MO_32); | |
6457 | } | |
6458 | tcg_temp_free_i32(tcg_single); | |
6459 | } | |
6460 | } | |
6461 | ||
6462 | if (!is_double && elements == 2) { | |
6463 | clear_vec_high(s, rd); | |
6464 | } | |
6465 | ||
6466 | tcg_temp_free_i64(tcg_int); | |
6467 | tcg_temp_free_ptr(tcg_fpst); | |
6468 | tcg_temp_free_i32(tcg_shift); | |
6469 | } | |
6470 | ||
6471 | /* UCVTF/SCVTF - Integer to FP conversion */ | |
6472 | static void handle_simd_shift_intfp_conv(DisasContext *s, bool is_scalar, | |
6473 | bool is_q, bool is_u, | |
6474 | int immh, int immb, int opcode, | |
6475 | int rn, int rd) | |
6476 | { | |
6477 | bool is_double = extract32(immh, 3, 1); | |
6478 | int size = is_double ? MO_64 : MO_32; | |
6479 | int elements; | |
6480 | int immhb = immh << 3 | immb; | |
6481 | int fracbits = (is_double ? 128 : 64) - immhb; | |
6482 | ||
6483 | if (!extract32(immh, 2, 2)) { | |
6484 | unallocated_encoding(s); | |
6485 | return; | |
6486 | } | |
6487 | ||
6488 | if (is_scalar) { | |
6489 | elements = 1; | |
6490 | } else { | |
6491 | elements = is_double ? 2 : is_q ? 4 : 2; | |
6492 | if (is_double && !is_q) { | |
6493 | unallocated_encoding(s); | |
6494 | return; | |
6495 | } | |
6496 | } | |
8c6afa6a PM |
6497 | |
6498 | if (!fp_access_check(s)) { | |
6499 | return; | |
6500 | } | |
6501 | ||
10113b69 AB |
6502 | /* immh == 0 would be a failure of the decode logic */ |
6503 | g_assert(immh); | |
6504 | ||
6505 | handle_simd_intfp_conv(s, rd, rn, elements, !is_u, fracbits, size); | |
6506 | } | |
6507 | ||
2ed3ea11 PM |
6508 | /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */ |
6509 | static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar, | |
6510 | bool is_q, bool is_u, | |
6511 | int immh, int immb, int rn, int rd) | |
6512 | { | |
6513 | bool is_double = extract32(immh, 3, 1); | |
6514 | int immhb = immh << 3 | immb; | |
6515 | int fracbits = (is_double ? 128 : 64) - immhb; | |
6516 | int pass; | |
6517 | TCGv_ptr tcg_fpstatus; | |
6518 | TCGv_i32 tcg_rmode, tcg_shift; | |
6519 | ||
6520 | if (!extract32(immh, 2, 2)) { | |
6521 | unallocated_encoding(s); | |
6522 | return; | |
6523 | } | |
6524 | ||
6525 | if (!is_scalar && !is_q && is_double) { | |
6526 | unallocated_encoding(s); | |
6527 | return; | |
6528 | } | |
6529 | ||
8c6afa6a PM |
6530 | if (!fp_access_check(s)) { |
6531 | return; | |
6532 | } | |
6533 | ||
2ed3ea11 PM |
6534 | assert(!(is_scalar && is_q)); |
6535 | ||
6536 | tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO)); | |
6537 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); | |
6538 | tcg_fpstatus = get_fpstatus_ptr(); | |
6539 | tcg_shift = tcg_const_i32(fracbits); | |
6540 | ||
6541 | if (is_double) { | |
4063452e | 6542 | int maxpass = is_scalar ? 1 : 2; |
2ed3ea11 PM |
6543 | |
6544 | for (pass = 0; pass < maxpass; pass++) { | |
6545 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | |
6546 | ||
6547 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
6548 | if (is_u) { | |
6549 | gen_helper_vfp_touqd(tcg_op, tcg_op, tcg_shift, tcg_fpstatus); | |
6550 | } else { | |
6551 | gen_helper_vfp_tosqd(tcg_op, tcg_op, tcg_shift, tcg_fpstatus); | |
6552 | } | |
6553 | write_vec_element(s, tcg_op, rd, pass, MO_64); | |
6554 | tcg_temp_free_i64(tcg_op); | |
6555 | } | |
6556 | if (!is_q) { | |
6557 | clear_vec_high(s, rd); | |
6558 | } | |
6559 | } else { | |
6560 | int maxpass = is_scalar ? 1 : is_q ? 4 : 2; | |
6561 | for (pass = 0; pass < maxpass; pass++) { | |
6562 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
6563 | ||
6564 | read_vec_element_i32(s, tcg_op, rn, pass, MO_32); | |
6565 | if (is_u) { | |
6566 | gen_helper_vfp_touls(tcg_op, tcg_op, tcg_shift, tcg_fpstatus); | |
6567 | } else { | |
6568 | gen_helper_vfp_tosls(tcg_op, tcg_op, tcg_shift, tcg_fpstatus); | |
6569 | } | |
6570 | if (is_scalar) { | |
6571 | write_fp_sreg(s, rd, tcg_op); | |
6572 | } else { | |
6573 | write_vec_element_i32(s, tcg_op, rd, pass, MO_32); | |
6574 | } | |
6575 | tcg_temp_free_i32(tcg_op); | |
6576 | } | |
6577 | if (!is_q && !is_scalar) { | |
6578 | clear_vec_high(s, rd); | |
6579 | } | |
6580 | } | |
6581 | ||
6582 | tcg_temp_free_ptr(tcg_fpstatus); | |
6583 | tcg_temp_free_i32(tcg_shift); | |
6584 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); | |
6585 | tcg_temp_free_i32(tcg_rmode); | |
6586 | } | |
6587 | ||
384b26fb AB |
6588 | /* C3.6.9 AdvSIMD scalar shift by immediate |
6589 | * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0 | |
6590 | * +-----+---+-------------+------+------+--------+---+------+------+ | |
6591 | * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd | | |
6592 | * +-----+---+-------------+------+------+--------+---+------+------+ | |
4d1cef84 AB |
6593 | * |
6594 | * This is the scalar version so it works on a fixed sized registers | |
384b26fb AB |
6595 | */ |
6596 | static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn) | |
6597 | { | |
4d1cef84 AB |
6598 | int rd = extract32(insn, 0, 5); |
6599 | int rn = extract32(insn, 5, 5); | |
6600 | int opcode = extract32(insn, 11, 5); | |
6601 | int immb = extract32(insn, 16, 3); | |
6602 | int immh = extract32(insn, 19, 4); | |
6603 | bool is_u = extract32(insn, 29, 1); | |
6604 | ||
c1b876b2 AB |
6605 | if (immh == 0) { |
6606 | unallocated_encoding(s); | |
6607 | return; | |
6608 | } | |
6609 | ||
4d1cef84 | 6610 | switch (opcode) { |
37a706ad PM |
6611 | case 0x08: /* SRI */ |
6612 | if (!is_u) { | |
6613 | unallocated_encoding(s); | |
6614 | return; | |
6615 | } | |
6616 | /* fall through */ | |
4d1cef84 AB |
6617 | case 0x00: /* SSHR / USHR */ |
6618 | case 0x02: /* SSRA / USRA */ | |
6619 | case 0x04: /* SRSHR / URSHR */ | |
6620 | case 0x06: /* SRSRA / URSRA */ | |
6621 | handle_scalar_simd_shri(s, is_u, immh, immb, opcode, rn, rd); | |
6622 | break; | |
6623 | case 0x0a: /* SHL / SLI */ | |
6624 | handle_scalar_simd_shli(s, is_u, immh, immb, opcode, rn, rd); | |
6625 | break; | |
10113b69 AB |
6626 | case 0x1c: /* SCVTF, UCVTF */ |
6627 | handle_simd_shift_intfp_conv(s, true, false, is_u, immh, immb, | |
6628 | opcode, rn, rd); | |
6629 | break; | |
c1b876b2 AB |
6630 | case 0x10: /* SQSHRUN, SQSHRUN2 */ |
6631 | case 0x11: /* SQRSHRUN, SQRSHRUN2 */ | |
6632 | if (!is_u) { | |
6633 | unallocated_encoding(s); | |
6634 | return; | |
6635 | } | |
6636 | handle_vec_simd_sqshrn(s, true, false, false, true, | |
6637 | immh, immb, opcode, rn, rd); | |
6638 | break; | |
6639 | case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */ | |
6640 | case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */ | |
6641 | handle_vec_simd_sqshrn(s, true, false, is_u, is_u, | |
6642 | immh, immb, opcode, rn, rd); | |
6643 | break; | |
a566da1b | 6644 | case 0xc: /* SQSHLU */ |
a847f32c PM |
6645 | if (!is_u) { |
6646 | unallocated_encoding(s); | |
6647 | return; | |
6648 | } | |
6649 | handle_simd_qshl(s, true, false, false, true, immh, immb, rn, rd); | |
6650 | break; | |
a566da1b | 6651 | case 0xe: /* SQSHL, UQSHL */ |
a847f32c PM |
6652 | handle_simd_qshl(s, true, false, is_u, is_u, immh, immb, rn, rd); |
6653 | break; | |
a566da1b | 6654 | case 0x1f: /* FCVTZS, FCVTZU */ |
2ed3ea11 | 6655 | handle_simd_shift_fpint_conv(s, true, false, is_u, immh, immb, rn, rd); |
4d1cef84 | 6656 | break; |
a566da1b PM |
6657 | default: |
6658 | unallocated_encoding(s); | |
6659 | break; | |
4d1cef84 | 6660 | } |
384b26fb AB |
6661 | } |
6662 | ||
6663 | /* C3.6.10 AdvSIMD scalar three different | |
6664 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 | |
6665 | * +-----+---+-----------+------+---+------+--------+-----+------+------+ | |
6666 | * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd | | |
6667 | * +-----+---+-----------+------+---+------+--------+-----+------+------+ | |
6668 | */ | |
6669 | static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn) | |
6670 | { | |
b033cd3d PM |
6671 | bool is_u = extract32(insn, 29, 1); |
6672 | int size = extract32(insn, 22, 2); | |
6673 | int opcode = extract32(insn, 12, 4); | |
6674 | int rm = extract32(insn, 16, 5); | |
6675 | int rn = extract32(insn, 5, 5); | |
6676 | int rd = extract32(insn, 0, 5); | |
6677 | ||
6678 | if (is_u) { | |
6679 | unallocated_encoding(s); | |
6680 | return; | |
6681 | } | |
6682 | ||
6683 | switch (opcode) { | |
6684 | case 0x9: /* SQDMLAL, SQDMLAL2 */ | |
6685 | case 0xb: /* SQDMLSL, SQDMLSL2 */ | |
6686 | case 0xd: /* SQDMULL, SQDMULL2 */ | |
6687 | if (size == 0 || size == 3) { | |
6688 | unallocated_encoding(s); | |
6689 | return; | |
6690 | } | |
6691 | break; | |
6692 | default: | |
6693 | unallocated_encoding(s); | |
6694 | return; | |
6695 | } | |
6696 | ||
8c6afa6a PM |
6697 | if (!fp_access_check(s)) { |
6698 | return; | |
6699 | } | |
6700 | ||
b033cd3d PM |
6701 | if (size == 2) { |
6702 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
6703 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
6704 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
6705 | ||
6706 | read_vec_element(s, tcg_op1, rn, 0, MO_32 | MO_SIGN); | |
6707 | read_vec_element(s, tcg_op2, rm, 0, MO_32 | MO_SIGN); | |
6708 | ||
6709 | tcg_gen_mul_i64(tcg_res, tcg_op1, tcg_op2); | |
6710 | gen_helper_neon_addl_saturate_s64(tcg_res, cpu_env, tcg_res, tcg_res); | |
6711 | ||
6712 | switch (opcode) { | |
6713 | case 0xd: /* SQDMULL, SQDMULL2 */ | |
6714 | break; | |
6715 | case 0xb: /* SQDMLSL, SQDMLSL2 */ | |
6716 | tcg_gen_neg_i64(tcg_res, tcg_res); | |
6717 | /* fall through */ | |
6718 | case 0x9: /* SQDMLAL, SQDMLAL2 */ | |
6719 | read_vec_element(s, tcg_op1, rd, 0, MO_64); | |
6720 | gen_helper_neon_addl_saturate_s64(tcg_res, cpu_env, | |
6721 | tcg_res, tcg_op1); | |
6722 | break; | |
6723 | default: | |
6724 | g_assert_not_reached(); | |
6725 | } | |
6726 | ||
6727 | write_fp_dreg(s, rd, tcg_res); | |
6728 | ||
6729 | tcg_temp_free_i64(tcg_op1); | |
6730 | tcg_temp_free_i64(tcg_op2); | |
6731 | tcg_temp_free_i64(tcg_res); | |
6732 | } else { | |
6733 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
6734 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
6735 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
6736 | ||
6737 | read_vec_element_i32(s, tcg_op1, rn, 0, MO_16); | |
6738 | read_vec_element_i32(s, tcg_op2, rm, 0, MO_16); | |
6739 | ||
6740 | gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2); | |
6741 | gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, tcg_res, tcg_res); | |
6742 | ||
6743 | switch (opcode) { | |
6744 | case 0xd: /* SQDMULL, SQDMULL2 */ | |
6745 | break; | |
6746 | case 0xb: /* SQDMLSL, SQDMLSL2 */ | |
6747 | gen_helper_neon_negl_u32(tcg_res, tcg_res); | |
6748 | /* fall through */ | |
6749 | case 0x9: /* SQDMLAL, SQDMLAL2 */ | |
6750 | { | |
6751 | TCGv_i64 tcg_op3 = tcg_temp_new_i64(); | |
6752 | read_vec_element(s, tcg_op3, rd, 0, MO_32); | |
6753 | gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, | |
6754 | tcg_res, tcg_op3); | |
6755 | tcg_temp_free_i64(tcg_op3); | |
6756 | break; | |
6757 | } | |
6758 | default: | |
6759 | g_assert_not_reached(); | |
6760 | } | |
6761 | ||
6762 | tcg_gen_ext32u_i64(tcg_res, tcg_res); | |
6763 | write_fp_dreg(s, rd, tcg_res); | |
6764 | ||
6765 | tcg_temp_free_i32(tcg_op1); | |
6766 | tcg_temp_free_i32(tcg_op2); | |
6767 | tcg_temp_free_i64(tcg_res); | |
6768 | } | |
384b26fb AB |
6769 | } |
6770 | ||
b305dba6 PM |
6771 | static void handle_3same_64(DisasContext *s, int opcode, bool u, |
6772 | TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, TCGv_i64 tcg_rm) | |
6773 | { | |
6774 | /* Handle 64x64->64 opcodes which are shared between the scalar | |
6775 | * and vector 3-same groups. We cover every opcode where size == 3 | |
6776 | * is valid in either the three-reg-same (integer, not pairwise) | |
6777 | * or scalar-three-reg-same groups. (Some opcodes are not yet | |
6778 | * implemented.) | |
6779 | */ | |
6780 | TCGCond cond; | |
6781 | ||
6782 | switch (opcode) { | |
6d9571f7 PM |
6783 | case 0x1: /* SQADD */ |
6784 | if (u) { | |
6785 | gen_helper_neon_qadd_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
6786 | } else { | |
6787 | gen_helper_neon_qadd_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
6788 | } | |
6789 | break; | |
6790 | case 0x5: /* SQSUB */ | |
6791 | if (u) { | |
6792 | gen_helper_neon_qsub_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
6793 | } else { | |
6794 | gen_helper_neon_qsub_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
6795 | } | |
6796 | break; | |
b305dba6 PM |
6797 | case 0x6: /* CMGT, CMHI */ |
6798 | /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0. | |
6799 | * We implement this using setcond (test) and then negating. | |
6800 | */ | |
6801 | cond = u ? TCG_COND_GTU : TCG_COND_GT; | |
6802 | do_cmop: | |
6803 | tcg_gen_setcond_i64(cond, tcg_rd, tcg_rn, tcg_rm); | |
6804 | tcg_gen_neg_i64(tcg_rd, tcg_rd); | |
6805 | break; | |
6806 | case 0x7: /* CMGE, CMHS */ | |
6807 | cond = u ? TCG_COND_GEU : TCG_COND_GE; | |
6808 | goto do_cmop; | |
6809 | case 0x11: /* CMTST, CMEQ */ | |
6810 | if (u) { | |
6811 | cond = TCG_COND_EQ; | |
6812 | goto do_cmop; | |
6813 | } | |
6814 | /* CMTST : test is "if (X & Y != 0)". */ | |
6815 | tcg_gen_and_i64(tcg_rd, tcg_rn, tcg_rm); | |
6816 | tcg_gen_setcondi_i64(TCG_COND_NE, tcg_rd, tcg_rd, 0); | |
6817 | tcg_gen_neg_i64(tcg_rd, tcg_rd); | |
6818 | break; | |
6d9571f7 | 6819 | case 0x8: /* SSHL, USHL */ |
b305dba6 | 6820 | if (u) { |
6d9571f7 | 6821 | gen_helper_neon_shl_u64(tcg_rd, tcg_rn, tcg_rm); |
b305dba6 | 6822 | } else { |
6d9571f7 | 6823 | gen_helper_neon_shl_s64(tcg_rd, tcg_rn, tcg_rm); |
b305dba6 PM |
6824 | } |
6825 | break; | |
b305dba6 | 6826 | case 0x9: /* SQSHL, UQSHL */ |
6d9571f7 PM |
6827 | if (u) { |
6828 | gen_helper_neon_qshl_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
6829 | } else { | |
6830 | gen_helper_neon_qshl_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
6831 | } | |
6832 | break; | |
b305dba6 | 6833 | case 0xa: /* SRSHL, URSHL */ |
6d9571f7 PM |
6834 | if (u) { |
6835 | gen_helper_neon_rshl_u64(tcg_rd, tcg_rn, tcg_rm); | |
6836 | } else { | |
6837 | gen_helper_neon_rshl_s64(tcg_rd, tcg_rn, tcg_rm); | |
6838 | } | |
6839 | break; | |
b305dba6 | 6840 | case 0xb: /* SQRSHL, UQRSHL */ |
6d9571f7 PM |
6841 | if (u) { |
6842 | gen_helper_neon_qrshl_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
6843 | } else { | |
6844 | gen_helper_neon_qrshl_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm); | |
6845 | } | |
6846 | break; | |
6847 | case 0x10: /* ADD, SUB */ | |
6848 | if (u) { | |
6849 | tcg_gen_sub_i64(tcg_rd, tcg_rn, tcg_rm); | |
6850 | } else { | |
6851 | tcg_gen_add_i64(tcg_rd, tcg_rn, tcg_rm); | |
6852 | } | |
6853 | break; | |
b305dba6 PM |
6854 | default: |
6855 | g_assert_not_reached(); | |
6856 | } | |
6857 | } | |
6858 | ||
845ea09a PM |
6859 | /* Handle the 3-same-operands float operations; shared by the scalar |
6860 | * and vector encodings. The caller must filter out any encodings | |
6861 | * not allocated for the encoding it is dealing with. | |
6862 | */ | |
6863 | static void handle_3same_float(DisasContext *s, int size, int elements, | |
6864 | int fpopcode, int rd, int rn, int rm) | |
6865 | { | |
6866 | int pass; | |
6867 | TCGv_ptr fpst = get_fpstatus_ptr(); | |
6868 | ||
6869 | for (pass = 0; pass < elements; pass++) { | |
6870 | if (size) { | |
6871 | /* Double */ | |
6872 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
6873 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
6874 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
6875 | ||
6876 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
6877 | read_vec_element(s, tcg_op2, rm, pass, MO_64); | |
6878 | ||
6879 | switch (fpopcode) { | |
057d5f62 PM |
6880 | case 0x39: /* FMLS */ |
6881 | /* As usual for ARM, separate negation for fused multiply-add */ | |
6882 | gen_helper_vfp_negd(tcg_op1, tcg_op1); | |
6883 | /* fall through */ | |
6884 | case 0x19: /* FMLA */ | |
6885 | read_vec_element(s, tcg_res, rd, pass, MO_64); | |
6886 | gen_helper_vfp_muladdd(tcg_res, tcg_op1, tcg_op2, | |
6887 | tcg_res, fpst); | |
6888 | break; | |
845ea09a PM |
6889 | case 0x18: /* FMAXNM */ |
6890 | gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6891 | break; | |
6892 | case 0x1a: /* FADD */ | |
6893 | gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6894 | break; | |
057d5f62 PM |
6895 | case 0x1b: /* FMULX */ |
6896 | gen_helper_vfp_mulxd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6897 | break; | |
8908f4d1 AB |
6898 | case 0x1c: /* FCMEQ */ |
6899 | gen_helper_neon_ceq_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
6900 | break; | |
845ea09a PM |
6901 | case 0x1e: /* FMAX */ |
6902 | gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6903 | break; | |
057d5f62 PM |
6904 | case 0x1f: /* FRECPS */ |
6905 | gen_helper_recpsf_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
6906 | break; | |
845ea09a PM |
6907 | case 0x38: /* FMINNM */ |
6908 | gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6909 | break; | |
6910 | case 0x3a: /* FSUB */ | |
6911 | gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6912 | break; | |
6913 | case 0x3e: /* FMIN */ | |
6914 | gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst); | |
6915 | break; | |
057d5f62 PM |
6916 | case 0x3f: /* FRSQRTS */ |
6917 | gen_helper_rsqrtsf_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
6918 | break; | |
845ea09a PM |
6919 | case 0x5b: /* FMUL */ |
6920 | gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst); | |
6921 | break; | |
8908f4d1 AB |
6922 | case 0x5c: /* FCMGE */ |
6923 | gen_helper_neon_cge_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
6924 | break; | |
057d5f62 PM |
6925 | case 0x5d: /* FACGE */ |
6926 | gen_helper_neon_acge_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
6927 | break; | |
845ea09a PM |
6928 | case 0x5f: /* FDIV */ |
6929 | gen_helper_vfp_divd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6930 | break; | |
6931 | case 0x7a: /* FABD */ | |
6932 | gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst); | |
6933 | gen_helper_vfp_absd(tcg_res, tcg_res); | |
6934 | break; | |
8908f4d1 AB |
6935 | case 0x7c: /* FCMGT */ |
6936 | gen_helper_neon_cgt_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
6937 | break; | |
057d5f62 PM |
6938 | case 0x7d: /* FACGT */ |
6939 | gen_helper_neon_acgt_f64(tcg_res, tcg_op1, tcg_op2, fpst); | |
6940 | break; | |
845ea09a PM |
6941 | default: |
6942 | g_assert_not_reached(); | |
6943 | } | |
6944 | ||
6945 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
6946 | ||
6947 | tcg_temp_free_i64(tcg_res); | |
6948 | tcg_temp_free_i64(tcg_op1); | |
6949 | tcg_temp_free_i64(tcg_op2); | |
6950 | } else { | |
6951 | /* Single */ | |
6952 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
6953 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
6954 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
6955 | ||
6956 | read_vec_element_i32(s, tcg_op1, rn, pass, MO_32); | |
6957 | read_vec_element_i32(s, tcg_op2, rm, pass, MO_32); | |
6958 | ||
6959 | switch (fpopcode) { | |
057d5f62 PM |
6960 | case 0x39: /* FMLS */ |
6961 | /* As usual for ARM, separate negation for fused multiply-add */ | |
6962 | gen_helper_vfp_negs(tcg_op1, tcg_op1); | |
6963 | /* fall through */ | |
6964 | case 0x19: /* FMLA */ | |
6965 | read_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
6966 | gen_helper_vfp_muladds(tcg_res, tcg_op1, tcg_op2, | |
6967 | tcg_res, fpst); | |
6968 | break; | |
845ea09a PM |
6969 | case 0x1a: /* FADD */ |
6970 | gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst); | |
6971 | break; | |
057d5f62 PM |
6972 | case 0x1b: /* FMULX */ |
6973 | gen_helper_vfp_mulxs(tcg_res, tcg_op1, tcg_op2, fpst); | |
6974 | break; | |
8908f4d1 AB |
6975 | case 0x1c: /* FCMEQ */ |
6976 | gen_helper_neon_ceq_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
6977 | break; | |
845ea09a PM |
6978 | case 0x1e: /* FMAX */ |
6979 | gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst); | |
6980 | break; | |
057d5f62 PM |
6981 | case 0x1f: /* FRECPS */ |
6982 | gen_helper_recpsf_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
6983 | break; | |
845ea09a PM |
6984 | case 0x18: /* FMAXNM */ |
6985 | gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
6986 | break; | |
6987 | case 0x38: /* FMINNM */ | |
6988 | gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst); | |
6989 | break; | |
6990 | case 0x3a: /* FSUB */ | |
6991 | gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst); | |
6992 | break; | |
6993 | case 0x3e: /* FMIN */ | |
6994 | gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst); | |
6995 | break; | |
057d5f62 PM |
6996 | case 0x3f: /* FRSQRTS */ |
6997 | gen_helper_rsqrtsf_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
6998 | break; | |
845ea09a PM |
6999 | case 0x5b: /* FMUL */ |
7000 | gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst); | |
7001 | break; | |
8908f4d1 AB |
7002 | case 0x5c: /* FCMGE */ |
7003 | gen_helper_neon_cge_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
7004 | break; | |
057d5f62 PM |
7005 | case 0x5d: /* FACGE */ |
7006 | gen_helper_neon_acge_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
7007 | break; | |
845ea09a PM |
7008 | case 0x5f: /* FDIV */ |
7009 | gen_helper_vfp_divs(tcg_res, tcg_op1, tcg_op2, fpst); | |
7010 | break; | |
7011 | case 0x7a: /* FABD */ | |
7012 | gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst); | |
7013 | gen_helper_vfp_abss(tcg_res, tcg_res); | |
7014 | break; | |
8908f4d1 AB |
7015 | case 0x7c: /* FCMGT */ |
7016 | gen_helper_neon_cgt_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
7017 | break; | |
057d5f62 PM |
7018 | case 0x7d: /* FACGT */ |
7019 | gen_helper_neon_acgt_f32(tcg_res, tcg_op1, tcg_op2, fpst); | |
7020 | break; | |
845ea09a PM |
7021 | default: |
7022 | g_assert_not_reached(); | |
7023 | } | |
7024 | ||
7025 | if (elements == 1) { | |
7026 | /* scalar single so clear high part */ | |
7027 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
7028 | ||
7029 | tcg_gen_extu_i32_i64(tcg_tmp, tcg_res); | |
7030 | write_vec_element(s, tcg_tmp, rd, pass, MO_64); | |
7031 | tcg_temp_free_i64(tcg_tmp); | |
7032 | } else { | |
7033 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
7034 | } | |
7035 | ||
7036 | tcg_temp_free_i32(tcg_res); | |
7037 | tcg_temp_free_i32(tcg_op1); | |
7038 | tcg_temp_free_i32(tcg_op2); | |
7039 | } | |
7040 | } | |
7041 | ||
7042 | tcg_temp_free_ptr(fpst); | |
7043 | ||
7044 | if ((elements << size) < 4) { | |
7045 | /* scalar, or non-quad vector op */ | |
7046 | clear_vec_high(s, rd); | |
7047 | } | |
7048 | } | |
7049 | ||
384b26fb AB |
7050 | /* C3.6.11 AdvSIMD scalar three same |
7051 | * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0 | |
7052 | * +-----+---+-----------+------+---+------+--------+---+------+------+ | |
7053 | * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd | | |
7054 | * +-----+---+-----------+------+---+------+--------+---+------+------+ | |
7055 | */ | |
7056 | static void disas_simd_scalar_three_reg_same(DisasContext *s, uint32_t insn) | |
7057 | { | |
b305dba6 PM |
7058 | int rd = extract32(insn, 0, 5); |
7059 | int rn = extract32(insn, 5, 5); | |
7060 | int opcode = extract32(insn, 11, 5); | |
7061 | int rm = extract32(insn, 16, 5); | |
7062 | int size = extract32(insn, 22, 2); | |
7063 | bool u = extract32(insn, 29, 1); | |
b305dba6 PM |
7064 | TCGv_i64 tcg_rd; |
7065 | ||
7066 | if (opcode >= 0x18) { | |
7067 | /* Floating point: U, size[1] and opcode indicate operation */ | |
7068 | int fpopcode = opcode | (extract32(size, 1, 1) << 5) | (u << 6); | |
7069 | switch (fpopcode) { | |
7070 | case 0x1b: /* FMULX */ | |
b305dba6 PM |
7071 | case 0x1f: /* FRECPS */ |
7072 | case 0x3f: /* FRSQRTS */ | |
b305dba6 | 7073 | case 0x5d: /* FACGE */ |
b305dba6 | 7074 | case 0x7d: /* FACGT */ |
8908f4d1 AB |
7075 | case 0x1c: /* FCMEQ */ |
7076 | case 0x5c: /* FCMGE */ | |
7077 | case 0x7c: /* FCMGT */ | |
845ea09a PM |
7078 | case 0x7a: /* FABD */ |
7079 | break; | |
b305dba6 PM |
7080 | default: |
7081 | unallocated_encoding(s); | |
7082 | return; | |
7083 | } | |
845ea09a | 7084 | |
8c6afa6a PM |
7085 | if (!fp_access_check(s)) { |
7086 | return; | |
7087 | } | |
7088 | ||
845ea09a PM |
7089 | handle_3same_float(s, extract32(size, 0, 1), 1, fpopcode, rd, rn, rm); |
7090 | return; | |
b305dba6 PM |
7091 | } |
7092 | ||
7093 | switch (opcode) { | |
7094 | case 0x1: /* SQADD, UQADD */ | |
7095 | case 0x5: /* SQSUB, UQSUB */ | |
c0b2b5fa PM |
7096 | case 0x9: /* SQSHL, UQSHL */ |
7097 | case 0xb: /* SQRSHL, UQRSHL */ | |
7098 | break; | |
6d9571f7 PM |
7099 | case 0x8: /* SSHL, USHL */ |
7100 | case 0xa: /* SRSHL, URSHL */ | |
b305dba6 PM |
7101 | case 0x6: /* CMGT, CMHI */ |
7102 | case 0x7: /* CMGE, CMHS */ | |
7103 | case 0x11: /* CMTST, CMEQ */ | |
7104 | case 0x10: /* ADD, SUB (vector) */ | |
7105 | if (size != 3) { | |
7106 | unallocated_encoding(s); | |
7107 | return; | |
7108 | } | |
7109 | break; | |
b305dba6 PM |
7110 | case 0x16: /* SQDMULH, SQRDMULH (vector) */ |
7111 | if (size != 1 && size != 2) { | |
7112 | unallocated_encoding(s); | |
7113 | return; | |
7114 | } | |
c0b2b5fa | 7115 | break; |
b305dba6 PM |
7116 | default: |
7117 | unallocated_encoding(s); | |
7118 | return; | |
7119 | } | |
7120 | ||
8c6afa6a PM |
7121 | if (!fp_access_check(s)) { |
7122 | return; | |
7123 | } | |
7124 | ||
b305dba6 PM |
7125 | tcg_rd = tcg_temp_new_i64(); |
7126 | ||
c0b2b5fa PM |
7127 | if (size == 3) { |
7128 | TCGv_i64 tcg_rn = read_fp_dreg(s, rn); | |
7129 | TCGv_i64 tcg_rm = read_fp_dreg(s, rm); | |
7130 | ||
7131 | handle_3same_64(s, opcode, u, tcg_rd, tcg_rn, tcg_rm); | |
7132 | tcg_temp_free_i64(tcg_rn); | |
7133 | tcg_temp_free_i64(tcg_rm); | |
7134 | } else { | |
7135 | /* Do a single operation on the lowest element in the vector. | |
7136 | * We use the standard Neon helpers and rely on 0 OP 0 == 0 with | |
7137 | * no side effects for all these operations. | |
7138 | * OPTME: special-purpose helpers would avoid doing some | |
7139 | * unnecessary work in the helper for the 8 and 16 bit cases. | |
7140 | */ | |
7141 | NeonGenTwoOpEnvFn *genenvfn; | |
7142 | TCGv_i32 tcg_rn = tcg_temp_new_i32(); | |
7143 | TCGv_i32 tcg_rm = tcg_temp_new_i32(); | |
7144 | TCGv_i32 tcg_rd32 = tcg_temp_new_i32(); | |
7145 | ||
7146 | read_vec_element_i32(s, tcg_rn, rn, 0, size); | |
7147 | read_vec_element_i32(s, tcg_rm, rm, 0, size); | |
7148 | ||
7149 | switch (opcode) { | |
7150 | case 0x1: /* SQADD, UQADD */ | |
7151 | { | |
7152 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
7153 | { gen_helper_neon_qadd_s8, gen_helper_neon_qadd_u8 }, | |
7154 | { gen_helper_neon_qadd_s16, gen_helper_neon_qadd_u16 }, | |
7155 | { gen_helper_neon_qadd_s32, gen_helper_neon_qadd_u32 }, | |
7156 | }; | |
7157 | genenvfn = fns[size][u]; | |
7158 | break; | |
7159 | } | |
7160 | case 0x5: /* SQSUB, UQSUB */ | |
7161 | { | |
7162 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
7163 | { gen_helper_neon_qsub_s8, gen_helper_neon_qsub_u8 }, | |
7164 | { gen_helper_neon_qsub_s16, gen_helper_neon_qsub_u16 }, | |
7165 | { gen_helper_neon_qsub_s32, gen_helper_neon_qsub_u32 }, | |
7166 | }; | |
7167 | genenvfn = fns[size][u]; | |
7168 | break; | |
7169 | } | |
7170 | case 0x9: /* SQSHL, UQSHL */ | |
7171 | { | |
7172 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
7173 | { gen_helper_neon_qshl_s8, gen_helper_neon_qshl_u8 }, | |
7174 | { gen_helper_neon_qshl_s16, gen_helper_neon_qshl_u16 }, | |
7175 | { gen_helper_neon_qshl_s32, gen_helper_neon_qshl_u32 }, | |
7176 | }; | |
7177 | genenvfn = fns[size][u]; | |
7178 | break; | |
7179 | } | |
7180 | case 0xb: /* SQRSHL, UQRSHL */ | |
7181 | { | |
7182 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
7183 | { gen_helper_neon_qrshl_s8, gen_helper_neon_qrshl_u8 }, | |
7184 | { gen_helper_neon_qrshl_s16, gen_helper_neon_qrshl_u16 }, | |
7185 | { gen_helper_neon_qrshl_s32, gen_helper_neon_qrshl_u32 }, | |
7186 | }; | |
7187 | genenvfn = fns[size][u]; | |
7188 | break; | |
7189 | } | |
7190 | case 0x16: /* SQDMULH, SQRDMULH */ | |
7191 | { | |
7192 | static NeonGenTwoOpEnvFn * const fns[2][2] = { | |
7193 | { gen_helper_neon_qdmulh_s16, gen_helper_neon_qrdmulh_s16 }, | |
7194 | { gen_helper_neon_qdmulh_s32, gen_helper_neon_qrdmulh_s32 }, | |
7195 | }; | |
7196 | assert(size == 1 || size == 2); | |
7197 | genenvfn = fns[size - 1][u]; | |
7198 | break; | |
7199 | } | |
7200 | default: | |
7201 | g_assert_not_reached(); | |
7202 | } | |
7203 | ||
7204 | genenvfn(tcg_rd32, cpu_env, tcg_rn, tcg_rm); | |
7205 | tcg_gen_extu_i32_i64(tcg_rd, tcg_rd32); | |
7206 | tcg_temp_free_i32(tcg_rd32); | |
7207 | tcg_temp_free_i32(tcg_rn); | |
7208 | tcg_temp_free_i32(tcg_rm); | |
7209 | } | |
b305dba6 PM |
7210 | |
7211 | write_fp_dreg(s, rd, tcg_rd); | |
7212 | ||
b305dba6 | 7213 | tcg_temp_free_i64(tcg_rd); |
384b26fb AB |
7214 | } |
7215 | ||
effa8e06 | 7216 | static void handle_2misc_64(DisasContext *s, int opcode, bool u, |
04c7c6c2 PM |
7217 | TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, |
7218 | TCGv_i32 tcg_rmode, TCGv_ptr tcg_fpstatus) | |
effa8e06 PM |
7219 | { |
7220 | /* Handle 64->64 opcodes which are shared between the scalar and | |
7221 | * vector 2-reg-misc groups. We cover every integer opcode where size == 3 | |
f93d0138 | 7222 | * is valid in either group and also the double-precision fp ops. |
04c7c6c2 PM |
7223 | * The caller only need provide tcg_rmode and tcg_fpstatus if the op |
7224 | * requires them. | |
effa8e06 PM |
7225 | */ |
7226 | TCGCond cond; | |
7227 | ||
7228 | switch (opcode) { | |
b05c3068 AB |
7229 | case 0x4: /* CLS, CLZ */ |
7230 | if (u) { | |
7231 | gen_helper_clz64(tcg_rd, tcg_rn); | |
7232 | } else { | |
7233 | gen_helper_cls64(tcg_rd, tcg_rn); | |
7234 | } | |
7235 | break; | |
86cbc418 PM |
7236 | case 0x5: /* NOT */ |
7237 | /* This opcode is shared with CNT and RBIT but we have earlier | |
7238 | * enforced that size == 3 if and only if this is the NOT insn. | |
7239 | */ | |
7240 | tcg_gen_not_i64(tcg_rd, tcg_rn); | |
7241 | break; | |
0a79bc87 AB |
7242 | case 0x7: /* SQABS, SQNEG */ |
7243 | if (u) { | |
7244 | gen_helper_neon_qneg_s64(tcg_rd, cpu_env, tcg_rn); | |
7245 | } else { | |
7246 | gen_helper_neon_qabs_s64(tcg_rd, cpu_env, tcg_rn); | |
7247 | } | |
7248 | break; | |
effa8e06 PM |
7249 | case 0xa: /* CMLT */ |
7250 | /* 64 bit integer comparison against zero, result is | |
7251 | * test ? (2^64 - 1) : 0. We implement via setcond(!test) and | |
7252 | * subtracting 1. | |
7253 | */ | |
7254 | cond = TCG_COND_LT; | |
7255 | do_cmop: | |
7256 | tcg_gen_setcondi_i64(cond, tcg_rd, tcg_rn, 0); | |
7257 | tcg_gen_neg_i64(tcg_rd, tcg_rd); | |
7258 | break; | |
7259 | case 0x8: /* CMGT, CMGE */ | |
7260 | cond = u ? TCG_COND_GE : TCG_COND_GT; | |
7261 | goto do_cmop; | |
7262 | case 0x9: /* CMEQ, CMLE */ | |
7263 | cond = u ? TCG_COND_LE : TCG_COND_EQ; | |
7264 | goto do_cmop; | |
7265 | case 0xb: /* ABS, NEG */ | |
7266 | if (u) { | |
7267 | tcg_gen_neg_i64(tcg_rd, tcg_rn); | |
7268 | } else { | |
7269 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
7270 | tcg_gen_neg_i64(tcg_rd, tcg_rn); | |
7271 | tcg_gen_movcond_i64(TCG_COND_GT, tcg_rd, tcg_rn, tcg_zero, | |
7272 | tcg_rn, tcg_rd); | |
7273 | tcg_temp_free_i64(tcg_zero); | |
7274 | } | |
7275 | break; | |
f93d0138 PM |
7276 | case 0x2f: /* FABS */ |
7277 | gen_helper_vfp_absd(tcg_rd, tcg_rn); | |
7278 | break; | |
7279 | case 0x6f: /* FNEG */ | |
7280 | gen_helper_vfp_negd(tcg_rd, tcg_rn); | |
7281 | break; | |
f612537e AB |
7282 | case 0x7f: /* FSQRT */ |
7283 | gen_helper_vfp_sqrtd(tcg_rd, tcg_rn, cpu_env); | |
7284 | break; | |
04c7c6c2 PM |
7285 | case 0x1a: /* FCVTNS */ |
7286 | case 0x1b: /* FCVTMS */ | |
7287 | case 0x1c: /* FCVTAS */ | |
7288 | case 0x3a: /* FCVTPS */ | |
7289 | case 0x3b: /* FCVTZS */ | |
7290 | { | |
7291 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
7292 | gen_helper_vfp_tosqd(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus); | |
7293 | tcg_temp_free_i32(tcg_shift); | |
7294 | break; | |
7295 | } | |
7296 | case 0x5a: /* FCVTNU */ | |
7297 | case 0x5b: /* FCVTMU */ | |
7298 | case 0x5c: /* FCVTAU */ | |
7299 | case 0x7a: /* FCVTPU */ | |
7300 | case 0x7b: /* FCVTZU */ | |
7301 | { | |
7302 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
7303 | gen_helper_vfp_touqd(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus); | |
7304 | tcg_temp_free_i32(tcg_shift); | |
7305 | break; | |
7306 | } | |
03df01ed PM |
7307 | case 0x18: /* FRINTN */ |
7308 | case 0x19: /* FRINTM */ | |
7309 | case 0x38: /* FRINTP */ | |
7310 | case 0x39: /* FRINTZ */ | |
7311 | case 0x58: /* FRINTA */ | |
7312 | case 0x79: /* FRINTI */ | |
7313 | gen_helper_rintd(tcg_rd, tcg_rn, tcg_fpstatus); | |
7314 | break; | |
7315 | case 0x59: /* FRINTX */ | |
7316 | gen_helper_rintd_exact(tcg_rd, tcg_rn, tcg_fpstatus); | |
7317 | break; | |
effa8e06 PM |
7318 | default: |
7319 | g_assert_not_reached(); | |
7320 | } | |
7321 | } | |
7322 | ||
8908f4d1 AB |
7323 | static void handle_2misc_fcmp_zero(DisasContext *s, int opcode, |
7324 | bool is_scalar, bool is_u, bool is_q, | |
7325 | int size, int rn, int rd) | |
7326 | { | |
7327 | bool is_double = (size == 3); | |
8c6afa6a PM |
7328 | TCGv_ptr fpst; |
7329 | ||
7330 | if (!fp_access_check(s)) { | |
7331 | return; | |
7332 | } | |
7333 | ||
7334 | fpst = get_fpstatus_ptr(); | |
8908f4d1 AB |
7335 | |
7336 | if (is_double) { | |
7337 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | |
7338 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
7339 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
7340 | NeonGenTwoDoubleOPFn *genfn; | |
7341 | bool swap = false; | |
7342 | int pass; | |
7343 | ||
7344 | switch (opcode) { | |
7345 | case 0x2e: /* FCMLT (zero) */ | |
7346 | swap = true; | |
7347 | /* fallthrough */ | |
7348 | case 0x2c: /* FCMGT (zero) */ | |
7349 | genfn = gen_helper_neon_cgt_f64; | |
7350 | break; | |
7351 | case 0x2d: /* FCMEQ (zero) */ | |
7352 | genfn = gen_helper_neon_ceq_f64; | |
7353 | break; | |
7354 | case 0x6d: /* FCMLE (zero) */ | |
7355 | swap = true; | |
7356 | /* fall through */ | |
7357 | case 0x6c: /* FCMGE (zero) */ | |
7358 | genfn = gen_helper_neon_cge_f64; | |
7359 | break; | |
7360 | default: | |
7361 | g_assert_not_reached(); | |
7362 | } | |
7363 | ||
7364 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { | |
7365 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
7366 | if (swap) { | |
7367 | genfn(tcg_res, tcg_zero, tcg_op, fpst); | |
7368 | } else { | |
7369 | genfn(tcg_res, tcg_op, tcg_zero, fpst); | |
7370 | } | |
7371 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
7372 | } | |
7373 | if (is_scalar) { | |
7374 | clear_vec_high(s, rd); | |
7375 | } | |
7376 | ||
7377 | tcg_temp_free_i64(tcg_res); | |
7378 | tcg_temp_free_i64(tcg_zero); | |
7379 | tcg_temp_free_i64(tcg_op); | |
7380 | } else { | |
7381 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
7382 | TCGv_i32 tcg_zero = tcg_const_i32(0); | |
7383 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
7384 | NeonGenTwoSingleOPFn *genfn; | |
7385 | bool swap = false; | |
7386 | int pass, maxpasses; | |
7387 | ||
7388 | switch (opcode) { | |
7389 | case 0x2e: /* FCMLT (zero) */ | |
7390 | swap = true; | |
7391 | /* fall through */ | |
7392 | case 0x2c: /* FCMGT (zero) */ | |
7393 | genfn = gen_helper_neon_cgt_f32; | |
7394 | break; | |
7395 | case 0x2d: /* FCMEQ (zero) */ | |
7396 | genfn = gen_helper_neon_ceq_f32; | |
7397 | break; | |
7398 | case 0x6d: /* FCMLE (zero) */ | |
7399 | swap = true; | |
7400 | /* fall through */ | |
7401 | case 0x6c: /* FCMGE (zero) */ | |
7402 | genfn = gen_helper_neon_cge_f32; | |
7403 | break; | |
7404 | default: | |
7405 | g_assert_not_reached(); | |
7406 | } | |
7407 | ||
7408 | if (is_scalar) { | |
7409 | maxpasses = 1; | |
7410 | } else { | |
7411 | maxpasses = is_q ? 4 : 2; | |
7412 | } | |
7413 | ||
7414 | for (pass = 0; pass < maxpasses; pass++) { | |
7415 | read_vec_element_i32(s, tcg_op, rn, pass, MO_32); | |
7416 | if (swap) { | |
7417 | genfn(tcg_res, tcg_zero, tcg_op, fpst); | |
7418 | } else { | |
7419 | genfn(tcg_res, tcg_op, tcg_zero, fpst); | |
7420 | } | |
7421 | if (is_scalar) { | |
7422 | write_fp_sreg(s, rd, tcg_res); | |
7423 | } else { | |
7424 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
7425 | } | |
7426 | } | |
7427 | tcg_temp_free_i32(tcg_res); | |
7428 | tcg_temp_free_i32(tcg_zero); | |
7429 | tcg_temp_free_i32(tcg_op); | |
7430 | if (!is_q && !is_scalar) { | |
7431 | clear_vec_high(s, rd); | |
7432 | } | |
7433 | } | |
7434 | ||
7435 | tcg_temp_free_ptr(fpst); | |
7436 | } | |
7437 | ||
8f0c6758 AB |
7438 | static void handle_2misc_reciprocal(DisasContext *s, int opcode, |
7439 | bool is_scalar, bool is_u, bool is_q, | |
7440 | int size, int rn, int rd) | |
7441 | { | |
7442 | bool is_double = (size == 3); | |
7443 | TCGv_ptr fpst = get_fpstatus_ptr(); | |
7444 | ||
7445 | if (is_double) { | |
7446 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | |
7447 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
7448 | int pass; | |
7449 | ||
7450 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { | |
7451 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
7452 | switch (opcode) { | |
b6d4443a AB |
7453 | case 0x3d: /* FRECPE */ |
7454 | gen_helper_recpe_f64(tcg_res, tcg_op, fpst); | |
7455 | break; | |
8f0c6758 AB |
7456 | case 0x3f: /* FRECPX */ |
7457 | gen_helper_frecpx_f64(tcg_res, tcg_op, fpst); | |
7458 | break; | |
c2fb418e AB |
7459 | case 0x7d: /* FRSQRTE */ |
7460 | gen_helper_rsqrte_f64(tcg_res, tcg_op, fpst); | |
7461 | break; | |
8f0c6758 AB |
7462 | default: |
7463 | g_assert_not_reached(); | |
7464 | } | |
7465 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
7466 | } | |
7467 | if (is_scalar) { | |
7468 | clear_vec_high(s, rd); | |
7469 | } | |
7470 | ||
7471 | tcg_temp_free_i64(tcg_res); | |
7472 | tcg_temp_free_i64(tcg_op); | |
7473 | } else { | |
7474 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
7475 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
7476 | int pass, maxpasses; | |
7477 | ||
7478 | if (is_scalar) { | |
7479 | maxpasses = 1; | |
7480 | } else { | |
7481 | maxpasses = is_q ? 4 : 2; | |
7482 | } | |
7483 | ||
7484 | for (pass = 0; pass < maxpasses; pass++) { | |
7485 | read_vec_element_i32(s, tcg_op, rn, pass, MO_32); | |
7486 | ||
7487 | switch (opcode) { | |
b6d4443a AB |
7488 | case 0x3c: /* URECPE */ |
7489 | gen_helper_recpe_u32(tcg_res, tcg_op, fpst); | |
7490 | break; | |
7491 | case 0x3d: /* FRECPE */ | |
7492 | gen_helper_recpe_f32(tcg_res, tcg_op, fpst); | |
7493 | break; | |
8f0c6758 AB |
7494 | case 0x3f: /* FRECPX */ |
7495 | gen_helper_frecpx_f32(tcg_res, tcg_op, fpst); | |
7496 | break; | |
c2fb418e AB |
7497 | case 0x7d: /* FRSQRTE */ |
7498 | gen_helper_rsqrte_f32(tcg_res, tcg_op, fpst); | |
7499 | break; | |
8f0c6758 AB |
7500 | default: |
7501 | g_assert_not_reached(); | |
7502 | } | |
7503 | ||
7504 | if (is_scalar) { | |
7505 | write_fp_sreg(s, rd, tcg_res); | |
7506 | } else { | |
7507 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
7508 | } | |
7509 | } | |
7510 | tcg_temp_free_i32(tcg_res); | |
7511 | tcg_temp_free_i32(tcg_op); | |
7512 | if (!is_q && !is_scalar) { | |
7513 | clear_vec_high(s, rd); | |
7514 | } | |
7515 | } | |
7516 | tcg_temp_free_ptr(fpst); | |
7517 | } | |
7518 | ||
5201c136 AB |
7519 | static void handle_2misc_narrow(DisasContext *s, bool scalar, |
7520 | int opcode, bool u, bool is_q, | |
8b092ca9 AB |
7521 | int size, int rn, int rd) |
7522 | { | |
7523 | /* Handle 2-reg-misc ops which are narrowing (so each 2*size element | |
7524 | * in the source becomes a size element in the destination). | |
7525 | */ | |
7526 | int pass; | |
7527 | TCGv_i32 tcg_res[2]; | |
7528 | int destelt = is_q ? 2 : 0; | |
5201c136 | 7529 | int passes = scalar ? 1 : 2; |
8b092ca9 | 7530 | |
5201c136 AB |
7531 | if (scalar) { |
7532 | tcg_res[1] = tcg_const_i32(0); | |
7533 | } | |
7534 | ||
7535 | for (pass = 0; pass < passes; pass++) { | |
8b092ca9 AB |
7536 | TCGv_i64 tcg_op = tcg_temp_new_i64(); |
7537 | NeonGenNarrowFn *genfn = NULL; | |
7538 | NeonGenNarrowEnvFn *genenvfn = NULL; | |
7539 | ||
5201c136 AB |
7540 | if (scalar) { |
7541 | read_vec_element(s, tcg_op, rn, pass, size + 1); | |
7542 | } else { | |
7543 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
7544 | } | |
8b092ca9 AB |
7545 | tcg_res[pass] = tcg_temp_new_i32(); |
7546 | ||
7547 | switch (opcode) { | |
7548 | case 0x12: /* XTN, SQXTUN */ | |
7549 | { | |
7550 | static NeonGenNarrowFn * const xtnfns[3] = { | |
7551 | gen_helper_neon_narrow_u8, | |
7552 | gen_helper_neon_narrow_u16, | |
7553 | tcg_gen_trunc_i64_i32, | |
7554 | }; | |
7555 | static NeonGenNarrowEnvFn * const sqxtunfns[3] = { | |
7556 | gen_helper_neon_unarrow_sat8, | |
7557 | gen_helper_neon_unarrow_sat16, | |
7558 | gen_helper_neon_unarrow_sat32, | |
7559 | }; | |
7560 | if (u) { | |
7561 | genenvfn = sqxtunfns[size]; | |
7562 | } else { | |
7563 | genfn = xtnfns[size]; | |
7564 | } | |
7565 | break; | |
7566 | } | |
7567 | case 0x14: /* SQXTN, UQXTN */ | |
7568 | { | |
7569 | static NeonGenNarrowEnvFn * const fns[3][2] = { | |
7570 | { gen_helper_neon_narrow_sat_s8, | |
7571 | gen_helper_neon_narrow_sat_u8 }, | |
7572 | { gen_helper_neon_narrow_sat_s16, | |
7573 | gen_helper_neon_narrow_sat_u16 }, | |
7574 | { gen_helper_neon_narrow_sat_s32, | |
7575 | gen_helper_neon_narrow_sat_u32 }, | |
7576 | }; | |
7577 | genenvfn = fns[size][u]; | |
7578 | break; | |
7579 | } | |
7580 | case 0x16: /* FCVTN, FCVTN2 */ | |
7581 | /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */ | |
7582 | if (size == 2) { | |
7583 | gen_helper_vfp_fcvtsd(tcg_res[pass], tcg_op, cpu_env); | |
7584 | } else { | |
7585 | TCGv_i32 tcg_lo = tcg_temp_new_i32(); | |
7586 | TCGv_i32 tcg_hi = tcg_temp_new_i32(); | |
7587 | tcg_gen_trunc_i64_i32(tcg_lo, tcg_op); | |
7588 | gen_helper_vfp_fcvt_f32_to_f16(tcg_lo, tcg_lo, cpu_env); | |
7589 | tcg_gen_shri_i64(tcg_op, tcg_op, 32); | |
7590 | tcg_gen_trunc_i64_i32(tcg_hi, tcg_op); | |
7591 | gen_helper_vfp_fcvt_f32_to_f16(tcg_hi, tcg_hi, cpu_env); | |
7592 | tcg_gen_deposit_i32(tcg_res[pass], tcg_lo, tcg_hi, 16, 16); | |
7593 | tcg_temp_free_i32(tcg_lo); | |
7594 | tcg_temp_free_i32(tcg_hi); | |
7595 | } | |
7596 | break; | |
5553955e PM |
7597 | case 0x56: /* FCVTXN, FCVTXN2 */ |
7598 | /* 64 bit to 32 bit float conversion | |
7599 | * with von Neumann rounding (round to odd) | |
7600 | */ | |
7601 | assert(size == 2); | |
7602 | gen_helper_fcvtx_f64_to_f32(tcg_res[pass], tcg_op, cpu_env); | |
7603 | break; | |
8b092ca9 AB |
7604 | default: |
7605 | g_assert_not_reached(); | |
7606 | } | |
7607 | ||
7608 | if (genfn) { | |
7609 | genfn(tcg_res[pass], tcg_op); | |
7610 | } else if (genenvfn) { | |
7611 | genenvfn(tcg_res[pass], cpu_env, tcg_op); | |
7612 | } | |
7613 | ||
7614 | tcg_temp_free_i64(tcg_op); | |
7615 | } | |
7616 | ||
7617 | for (pass = 0; pass < 2; pass++) { | |
7618 | write_vec_element_i32(s, tcg_res[pass], rd, destelt + pass, MO_32); | |
7619 | tcg_temp_free_i32(tcg_res[pass]); | |
7620 | } | |
7621 | if (!is_q) { | |
7622 | clear_vec_high(s, rd); | |
7623 | } | |
7624 | } | |
7625 | ||
09e03735 AB |
7626 | /* Remaining saturating accumulating ops */ |
7627 | static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u, | |
7628 | bool is_q, int size, int rn, int rd) | |
7629 | { | |
7630 | bool is_double = (size == 3); | |
7631 | ||
7632 | if (is_double) { | |
7633 | TCGv_i64 tcg_rn = tcg_temp_new_i64(); | |
7634 | TCGv_i64 tcg_rd = tcg_temp_new_i64(); | |
7635 | int pass; | |
7636 | ||
7637 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { | |
7638 | read_vec_element(s, tcg_rn, rn, pass, MO_64); | |
7639 | read_vec_element(s, tcg_rd, rd, pass, MO_64); | |
7640 | ||
7641 | if (is_u) { /* USQADD */ | |
7642 | gen_helper_neon_uqadd_s64(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
7643 | } else { /* SUQADD */ | |
7644 | gen_helper_neon_sqadd_u64(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
7645 | } | |
7646 | write_vec_element(s, tcg_rd, rd, pass, MO_64); | |
7647 | } | |
7648 | if (is_scalar) { | |
7649 | clear_vec_high(s, rd); | |
7650 | } | |
7651 | ||
7652 | tcg_temp_free_i64(tcg_rd); | |
7653 | tcg_temp_free_i64(tcg_rn); | |
7654 | } else { | |
7655 | TCGv_i32 tcg_rn = tcg_temp_new_i32(); | |
7656 | TCGv_i32 tcg_rd = tcg_temp_new_i32(); | |
7657 | int pass, maxpasses; | |
7658 | ||
7659 | if (is_scalar) { | |
7660 | maxpasses = 1; | |
7661 | } else { | |
7662 | maxpasses = is_q ? 4 : 2; | |
7663 | } | |
7664 | ||
7665 | for (pass = 0; pass < maxpasses; pass++) { | |
7666 | if (is_scalar) { | |
7667 | read_vec_element_i32(s, tcg_rn, rn, pass, size); | |
7668 | read_vec_element_i32(s, tcg_rd, rd, pass, size); | |
7669 | } else { | |
7670 | read_vec_element_i32(s, tcg_rn, rn, pass, MO_32); | |
7671 | read_vec_element_i32(s, tcg_rd, rd, pass, MO_32); | |
7672 | } | |
7673 | ||
7674 | if (is_u) { /* USQADD */ | |
7675 | switch (size) { | |
7676 | case 0: | |
7677 | gen_helper_neon_uqadd_s8(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
7678 | break; | |
7679 | case 1: | |
7680 | gen_helper_neon_uqadd_s16(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
7681 | break; | |
7682 | case 2: | |
7683 | gen_helper_neon_uqadd_s32(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
7684 | break; | |
7685 | default: | |
7686 | g_assert_not_reached(); | |
7687 | } | |
7688 | } else { /* SUQADD */ | |
7689 | switch (size) { | |
7690 | case 0: | |
7691 | gen_helper_neon_sqadd_u8(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
7692 | break; | |
7693 | case 1: | |
7694 | gen_helper_neon_sqadd_u16(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
7695 | break; | |
7696 | case 2: | |
7697 | gen_helper_neon_sqadd_u32(tcg_rd, cpu_env, tcg_rn, tcg_rd); | |
7698 | break; | |
7699 | default: | |
7700 | g_assert_not_reached(); | |
7701 | } | |
7702 | } | |
7703 | ||
7704 | if (is_scalar) { | |
7705 | TCGv_i64 tcg_zero = tcg_const_i64(0); | |
7706 | write_vec_element(s, tcg_zero, rd, 0, MO_64); | |
7707 | tcg_temp_free_i64(tcg_zero); | |
7708 | } | |
7709 | write_vec_element_i32(s, tcg_rd, rd, pass, MO_32); | |
7710 | } | |
7711 | ||
7712 | if (!is_q) { | |
7713 | clear_vec_high(s, rd); | |
7714 | } | |
7715 | ||
7716 | tcg_temp_free_i32(tcg_rd); | |
7717 | tcg_temp_free_i32(tcg_rn); | |
7718 | } | |
7719 | } | |
7720 | ||
384b26fb AB |
7721 | /* C3.6.12 AdvSIMD scalar two reg misc |
7722 | * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 | |
7723 | * +-----+---+-----------+------+-----------+--------+-----+------+------+ | |
7724 | * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd | | |
7725 | * +-----+---+-----------+------+-----------+--------+-----+------+------+ | |
7726 | */ | |
7727 | static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn) | |
7728 | { | |
effa8e06 PM |
7729 | int rd = extract32(insn, 0, 5); |
7730 | int rn = extract32(insn, 5, 5); | |
7731 | int opcode = extract32(insn, 12, 5); | |
7732 | int size = extract32(insn, 22, 2); | |
7733 | bool u = extract32(insn, 29, 1); | |
04c7c6c2 PM |
7734 | bool is_fcvt = false; |
7735 | int rmode; | |
7736 | TCGv_i32 tcg_rmode; | |
7737 | TCGv_ptr tcg_fpstatus; | |
effa8e06 PM |
7738 | |
7739 | switch (opcode) { | |
09e03735 | 7740 | case 0x3: /* USQADD / SUQADD*/ |
8c6afa6a PM |
7741 | if (!fp_access_check(s)) { |
7742 | return; | |
7743 | } | |
09e03735 AB |
7744 | handle_2misc_satacc(s, true, u, false, size, rn, rd); |
7745 | return; | |
0a79bc87 AB |
7746 | case 0x7: /* SQABS / SQNEG */ |
7747 | break; | |
effa8e06 PM |
7748 | case 0xa: /* CMLT */ |
7749 | if (u) { | |
7750 | unallocated_encoding(s); | |
7751 | return; | |
7752 | } | |
7753 | /* fall through */ | |
7754 | case 0x8: /* CMGT, CMGE */ | |
7755 | case 0x9: /* CMEQ, CMLE */ | |
7756 | case 0xb: /* ABS, NEG */ | |
7757 | if (size != 3) { | |
7758 | unallocated_encoding(s); | |
7759 | return; | |
7760 | } | |
7761 | break; | |
5201c136 | 7762 | case 0x12: /* SQXTUN */ |
e44a90c5 | 7763 | if (!u) { |
5201c136 AB |
7764 | unallocated_encoding(s); |
7765 | return; | |
7766 | } | |
7767 | /* fall through */ | |
7768 | case 0x14: /* SQXTN, UQXTN */ | |
7769 | if (size == 3) { | |
7770 | unallocated_encoding(s); | |
7771 | return; | |
7772 | } | |
8c6afa6a PM |
7773 | if (!fp_access_check(s)) { |
7774 | return; | |
7775 | } | |
5201c136 AB |
7776 | handle_2misc_narrow(s, true, opcode, u, false, size, rn, rd); |
7777 | return; | |
8908f4d1 AB |
7778 | case 0xc ... 0xf: |
7779 | case 0x16 ... 0x1d: | |
7780 | case 0x1f: | |
7781 | /* Floating point: U, size[1] and opcode indicate operation; | |
7782 | * size[0] indicates single or double precision. | |
7783 | */ | |
7784 | opcode |= (extract32(size, 1, 1) << 5) | (u << 6); | |
7785 | size = extract32(size, 0, 1) ? 3 : 2; | |
7786 | switch (opcode) { | |
7787 | case 0x2c: /* FCMGT (zero) */ | |
7788 | case 0x2d: /* FCMEQ (zero) */ | |
7789 | case 0x2e: /* FCMLT (zero) */ | |
7790 | case 0x6c: /* FCMGE (zero) */ | |
7791 | case 0x6d: /* FCMLE (zero) */ | |
7792 | handle_2misc_fcmp_zero(s, opcode, true, u, true, size, rn, rd); | |
7793 | return; | |
10113b69 AB |
7794 | case 0x1d: /* SCVTF */ |
7795 | case 0x5d: /* UCVTF */ | |
7796 | { | |
7797 | bool is_signed = (opcode == 0x1d); | |
8c6afa6a PM |
7798 | if (!fp_access_check(s)) { |
7799 | return; | |
7800 | } | |
10113b69 AB |
7801 | handle_simd_intfp_conv(s, rd, rn, 1, is_signed, 0, size); |
7802 | return; | |
7803 | } | |
b6d4443a | 7804 | case 0x3d: /* FRECPE */ |
8f0c6758 | 7805 | case 0x3f: /* FRECPX */ |
c2fb418e | 7806 | case 0x7d: /* FRSQRTE */ |
8c6afa6a PM |
7807 | if (!fp_access_check(s)) { |
7808 | return; | |
7809 | } | |
8f0c6758 AB |
7810 | handle_2misc_reciprocal(s, opcode, true, u, true, size, rn, rd); |
7811 | return; | |
8908f4d1 AB |
7812 | case 0x1a: /* FCVTNS */ |
7813 | case 0x1b: /* FCVTMS */ | |
8908f4d1 AB |
7814 | case 0x3a: /* FCVTPS */ |
7815 | case 0x3b: /* FCVTZS */ | |
8908f4d1 AB |
7816 | case 0x5a: /* FCVTNU */ |
7817 | case 0x5b: /* FCVTMU */ | |
8908f4d1 AB |
7818 | case 0x7a: /* FCVTPU */ |
7819 | case 0x7b: /* FCVTZU */ | |
04c7c6c2 PM |
7820 | is_fcvt = true; |
7821 | rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1); | |
7822 | break; | |
7823 | case 0x1c: /* FCVTAS */ | |
7824 | case 0x5c: /* FCVTAU */ | |
7825 | /* TIEAWAY doesn't fit in the usual rounding mode encoding */ | |
7826 | is_fcvt = true; | |
7827 | rmode = FPROUNDING_TIEAWAY; | |
7828 | break; | |
04c7c6c2 | 7829 | case 0x56: /* FCVTXN, FCVTXN2 */ |
5553955e PM |
7830 | if (size == 2) { |
7831 | unallocated_encoding(s); | |
7832 | return; | |
7833 | } | |
8c6afa6a PM |
7834 | if (!fp_access_check(s)) { |
7835 | return; | |
7836 | } | |
5553955e PM |
7837 | handle_2misc_narrow(s, true, opcode, u, false, size - 1, rn, rd); |
7838 | return; | |
8908f4d1 AB |
7839 | default: |
7840 | unallocated_encoding(s); | |
7841 | return; | |
7842 | } | |
7843 | break; | |
effa8e06 | 7844 | default: |
09e03735 | 7845 | unallocated_encoding(s); |
effa8e06 PM |
7846 | return; |
7847 | } | |
7848 | ||
8c6afa6a PM |
7849 | if (!fp_access_check(s)) { |
7850 | return; | |
7851 | } | |
7852 | ||
04c7c6c2 PM |
7853 | if (is_fcvt) { |
7854 | tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); | |
7855 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); | |
7856 | tcg_fpstatus = get_fpstatus_ptr(); | |
7857 | } else { | |
7858 | TCGV_UNUSED_I32(tcg_rmode); | |
7859 | TCGV_UNUSED_PTR(tcg_fpstatus); | |
7860 | } | |
7861 | ||
effa8e06 PM |
7862 | if (size == 3) { |
7863 | TCGv_i64 tcg_rn = read_fp_dreg(s, rn); | |
7864 | TCGv_i64 tcg_rd = tcg_temp_new_i64(); | |
7865 | ||
04c7c6c2 | 7866 | handle_2misc_64(s, opcode, u, tcg_rd, tcg_rn, tcg_rmode, tcg_fpstatus); |
effa8e06 PM |
7867 | write_fp_dreg(s, rd, tcg_rd); |
7868 | tcg_temp_free_i64(tcg_rd); | |
7869 | tcg_temp_free_i64(tcg_rn); | |
0a79bc87 AB |
7870 | } else { |
7871 | TCGv_i32 tcg_rn = tcg_temp_new_i32(); | |
04c7c6c2 PM |
7872 | TCGv_i32 tcg_rd = tcg_temp_new_i32(); |
7873 | ||
0a79bc87 AB |
7874 | read_vec_element_i32(s, tcg_rn, rn, 0, size); |
7875 | ||
04c7c6c2 | 7876 | switch (opcode) { |
0a79bc87 AB |
7877 | case 0x7: /* SQABS, SQNEG */ |
7878 | { | |
7879 | NeonGenOneOpEnvFn *genfn; | |
7880 | static NeonGenOneOpEnvFn * const fns[3][2] = { | |
7881 | { gen_helper_neon_qabs_s8, gen_helper_neon_qneg_s8 }, | |
7882 | { gen_helper_neon_qabs_s16, gen_helper_neon_qneg_s16 }, | |
7883 | { gen_helper_neon_qabs_s32, gen_helper_neon_qneg_s32 }, | |
7884 | }; | |
7885 | genfn = fns[size][u]; | |
7886 | genfn(tcg_rd, cpu_env, tcg_rn); | |
7887 | break; | |
7888 | } | |
04c7c6c2 PM |
7889 | case 0x1a: /* FCVTNS */ |
7890 | case 0x1b: /* FCVTMS */ | |
7891 | case 0x1c: /* FCVTAS */ | |
7892 | case 0x3a: /* FCVTPS */ | |
7893 | case 0x3b: /* FCVTZS */ | |
7894 | { | |
7895 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
7896 | gen_helper_vfp_tosls(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus); | |
7897 | tcg_temp_free_i32(tcg_shift); | |
7898 | break; | |
7899 | } | |
7900 | case 0x5a: /* FCVTNU */ | |
7901 | case 0x5b: /* FCVTMU */ | |
7902 | case 0x5c: /* FCVTAU */ | |
7903 | case 0x7a: /* FCVTPU */ | |
7904 | case 0x7b: /* FCVTZU */ | |
7905 | { | |
7906 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
7907 | gen_helper_vfp_touls(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus); | |
7908 | tcg_temp_free_i32(tcg_shift); | |
7909 | break; | |
7910 | } | |
7911 | default: | |
7912 | g_assert_not_reached(); | |
7913 | } | |
7914 | ||
7915 | write_fp_sreg(s, rd, tcg_rd); | |
7916 | tcg_temp_free_i32(tcg_rd); | |
7917 | tcg_temp_free_i32(tcg_rn); | |
effa8e06 | 7918 | } |
04c7c6c2 PM |
7919 | |
7920 | if (is_fcvt) { | |
7921 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); | |
7922 | tcg_temp_free_i32(tcg_rmode); | |
7923 | tcg_temp_free_ptr(tcg_fpstatus); | |
7924 | } | |
384b26fb AB |
7925 | } |
7926 | ||
4d1cef84 AB |
7927 | /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */ |
7928 | static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u, | |
7929 | int immh, int immb, int opcode, int rn, int rd) | |
7930 | { | |
7931 | int size = 32 - clz32(immh) - 1; | |
7932 | int immhb = immh << 3 | immb; | |
7933 | int shift = 2 * (8 << size) - immhb; | |
7934 | bool accumulate = false; | |
7935 | bool round = false; | |
37a706ad | 7936 | bool insert = false; |
4d1cef84 AB |
7937 | int dsize = is_q ? 128 : 64; |
7938 | int esize = 8 << size; | |
7939 | int elements = dsize/esize; | |
7940 | TCGMemOp memop = size | (is_u ? 0 : MO_SIGN); | |
7941 | TCGv_i64 tcg_rn = new_tmp_a64(s); | |
7942 | TCGv_i64 tcg_rd = new_tmp_a64(s); | |
7943 | TCGv_i64 tcg_round; | |
7944 | int i; | |
7945 | ||
7946 | if (extract32(immh, 3, 1) && !is_q) { | |
7947 | unallocated_encoding(s); | |
7948 | return; | |
7949 | } | |
7950 | ||
7951 | if (size > 3 && !is_q) { | |
7952 | unallocated_encoding(s); | |
7953 | return; | |
7954 | } | |
7955 | ||
8c6afa6a PM |
7956 | if (!fp_access_check(s)) { |
7957 | return; | |
7958 | } | |
7959 | ||
4d1cef84 AB |
7960 | switch (opcode) { |
7961 | case 0x02: /* SSRA / USRA (accumulate) */ | |
7962 | accumulate = true; | |
7963 | break; | |
7964 | case 0x04: /* SRSHR / URSHR (rounding) */ | |
7965 | round = true; | |
7966 | break; | |
7967 | case 0x06: /* SRSRA / URSRA (accum + rounding) */ | |
7968 | accumulate = round = true; | |
7969 | break; | |
37a706ad PM |
7970 | case 0x08: /* SRI */ |
7971 | insert = true; | |
7972 | break; | |
4d1cef84 AB |
7973 | } |
7974 | ||
7975 | if (round) { | |
7976 | uint64_t round_const = 1ULL << (shift - 1); | |
7977 | tcg_round = tcg_const_i64(round_const); | |
7978 | } else { | |
7979 | TCGV_UNUSED_I64(tcg_round); | |
7980 | } | |
7981 | ||
7982 | for (i = 0; i < elements; i++) { | |
7983 | read_vec_element(s, tcg_rn, rn, i, memop); | |
37a706ad | 7984 | if (accumulate || insert) { |
4d1cef84 AB |
7985 | read_vec_element(s, tcg_rd, rd, i, memop); |
7986 | } | |
7987 | ||
37a706ad PM |
7988 | if (insert) { |
7989 | handle_shri_with_ins(tcg_rd, tcg_rn, size, shift); | |
7990 | } else { | |
7991 | handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round, | |
7992 | accumulate, is_u, size, shift); | |
7993 | } | |
4d1cef84 AB |
7994 | |
7995 | write_vec_element(s, tcg_rd, rd, i, size); | |
7996 | } | |
7997 | ||
7998 | if (!is_q) { | |
7999 | clear_vec_high(s, rd); | |
8000 | } | |
8001 | ||
8002 | if (round) { | |
8003 | tcg_temp_free_i64(tcg_round); | |
8004 | } | |
8005 | } | |
8006 | ||
8007 | /* SHL/SLI - Vector shift left */ | |
8008 | static void handle_vec_simd_shli(DisasContext *s, bool is_q, bool insert, | |
8009 | int immh, int immb, int opcode, int rn, int rd) | |
8010 | { | |
8011 | int size = 32 - clz32(immh) - 1; | |
8012 | int immhb = immh << 3 | immb; | |
8013 | int shift = immhb - (8 << size); | |
8014 | int dsize = is_q ? 128 : 64; | |
8015 | int esize = 8 << size; | |
8016 | int elements = dsize/esize; | |
8017 | TCGv_i64 tcg_rn = new_tmp_a64(s); | |
8018 | TCGv_i64 tcg_rd = new_tmp_a64(s); | |
8019 | int i; | |
8020 | ||
8021 | if (extract32(immh, 3, 1) && !is_q) { | |
8022 | unallocated_encoding(s); | |
8023 | return; | |
8024 | } | |
8025 | ||
8026 | if (size > 3 && !is_q) { | |
8027 | unallocated_encoding(s); | |
8028 | return; | |
8029 | } | |
8030 | ||
8c6afa6a PM |
8031 | if (!fp_access_check(s)) { |
8032 | return; | |
8033 | } | |
8034 | ||
4d1cef84 AB |
8035 | for (i = 0; i < elements; i++) { |
8036 | read_vec_element(s, tcg_rn, rn, i, size); | |
8037 | if (insert) { | |
8038 | read_vec_element(s, tcg_rd, rd, i, size); | |
8039 | } | |
8040 | ||
8041 | handle_shli_with_ins(tcg_rd, tcg_rn, insert, shift); | |
8042 | ||
8043 | write_vec_element(s, tcg_rd, rd, i, size); | |
8044 | } | |
8045 | ||
8046 | if (!is_q) { | |
8047 | clear_vec_high(s, rd); | |
8048 | } | |
8049 | } | |
8050 | ||
8051 | /* USHLL/SHLL - Vector shift left with widening */ | |
8052 | static void handle_vec_simd_wshli(DisasContext *s, bool is_q, bool is_u, | |
8053 | int immh, int immb, int opcode, int rn, int rd) | |
8054 | { | |
8055 | int size = 32 - clz32(immh) - 1; | |
8056 | int immhb = immh << 3 | immb; | |
8057 | int shift = immhb - (8 << size); | |
8058 | int dsize = 64; | |
8059 | int esize = 8 << size; | |
8060 | int elements = dsize/esize; | |
8061 | TCGv_i64 tcg_rn = new_tmp_a64(s); | |
8062 | TCGv_i64 tcg_rd = new_tmp_a64(s); | |
8063 | int i; | |
8064 | ||
8065 | if (size >= 3) { | |
8066 | unallocated_encoding(s); | |
8067 | return; | |
8068 | } | |
8069 | ||
8c6afa6a PM |
8070 | if (!fp_access_check(s)) { |
8071 | return; | |
8072 | } | |
8073 | ||
4d1cef84 AB |
8074 | /* For the LL variants the store is larger than the load, |
8075 | * so if rd == rn we would overwrite parts of our input. | |
8076 | * So load everything right now and use shifts in the main loop. | |
8077 | */ | |
8078 | read_vec_element(s, tcg_rn, rn, is_q ? 1 : 0, MO_64); | |
8079 | ||
8080 | for (i = 0; i < elements; i++) { | |
8081 | tcg_gen_shri_i64(tcg_rd, tcg_rn, i * esize); | |
8082 | ext_and_shift_reg(tcg_rd, tcg_rd, size | (!is_u << 2), 0); | |
8083 | tcg_gen_shli_i64(tcg_rd, tcg_rd, shift); | |
8084 | write_vec_element(s, tcg_rd, rd, i, size + 1); | |
8085 | } | |
8086 | } | |
8087 | ||
c1b876b2 AB |
8088 | /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */ |
8089 | static void handle_vec_simd_shrn(DisasContext *s, bool is_q, | |
8090 | int immh, int immb, int opcode, int rn, int rd) | |
8091 | { | |
8092 | int immhb = immh << 3 | immb; | |
8093 | int size = 32 - clz32(immh) - 1; | |
8094 | int dsize = 64; | |
8095 | int esize = 8 << size; | |
8096 | int elements = dsize/esize; | |
8097 | int shift = (2 * esize) - immhb; | |
8098 | bool round = extract32(opcode, 0, 1); | |
8099 | TCGv_i64 tcg_rn, tcg_rd, tcg_final; | |
8100 | TCGv_i64 tcg_round; | |
8101 | int i; | |
8102 | ||
8103 | if (extract32(immh, 3, 1)) { | |
8104 | unallocated_encoding(s); | |
8105 | return; | |
8106 | } | |
8107 | ||
8c6afa6a PM |
8108 | if (!fp_access_check(s)) { |
8109 | return; | |
8110 | } | |
8111 | ||
c1b876b2 AB |
8112 | tcg_rn = tcg_temp_new_i64(); |
8113 | tcg_rd = tcg_temp_new_i64(); | |
8114 | tcg_final = tcg_temp_new_i64(); | |
8115 | read_vec_element(s, tcg_final, rd, is_q ? 1 : 0, MO_64); | |
8116 | ||
8117 | if (round) { | |
8118 | uint64_t round_const = 1ULL << (shift - 1); | |
8119 | tcg_round = tcg_const_i64(round_const); | |
8120 | } else { | |
8121 | TCGV_UNUSED_I64(tcg_round); | |
8122 | } | |
8123 | ||
8124 | for (i = 0; i < elements; i++) { | |
8125 | read_vec_element(s, tcg_rn, rn, i, size+1); | |
8126 | handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round, | |
8127 | false, true, size+1, shift); | |
8128 | ||
8129 | tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize); | |
8130 | } | |
8131 | ||
8132 | if (!is_q) { | |
8133 | clear_vec_high(s, rd); | |
8134 | write_vec_element(s, tcg_final, rd, 0, MO_64); | |
8135 | } else { | |
8136 | write_vec_element(s, tcg_final, rd, 1, MO_64); | |
8137 | } | |
8138 | ||
8139 | if (round) { | |
8140 | tcg_temp_free_i64(tcg_round); | |
8141 | } | |
8142 | tcg_temp_free_i64(tcg_rn); | |
8143 | tcg_temp_free_i64(tcg_rd); | |
8144 | tcg_temp_free_i64(tcg_final); | |
8145 | return; | |
8146 | } | |
8147 | ||
8148 | ||
384b26fb AB |
8149 | /* C3.6.14 AdvSIMD shift by immediate |
8150 | * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0 | |
8151 | * +---+---+---+-------------+------+------+--------+---+------+------+ | |
8152 | * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd | | |
8153 | * +---+---+---+-------------+------+------+--------+---+------+------+ | |
8154 | */ | |
8155 | static void disas_simd_shift_imm(DisasContext *s, uint32_t insn) | |
8156 | { | |
4d1cef84 AB |
8157 | int rd = extract32(insn, 0, 5); |
8158 | int rn = extract32(insn, 5, 5); | |
8159 | int opcode = extract32(insn, 11, 5); | |
8160 | int immb = extract32(insn, 16, 3); | |
8161 | int immh = extract32(insn, 19, 4); | |
8162 | bool is_u = extract32(insn, 29, 1); | |
8163 | bool is_q = extract32(insn, 30, 1); | |
8164 | ||
8165 | switch (opcode) { | |
37a706ad PM |
8166 | case 0x08: /* SRI */ |
8167 | if (!is_u) { | |
8168 | unallocated_encoding(s); | |
8169 | return; | |
8170 | } | |
8171 | /* fall through */ | |
4d1cef84 AB |
8172 | case 0x00: /* SSHR / USHR */ |
8173 | case 0x02: /* SSRA / USRA (accumulate) */ | |
8174 | case 0x04: /* SRSHR / URSHR (rounding) */ | |
8175 | case 0x06: /* SRSRA / URSRA (accum + rounding) */ | |
8176 | handle_vec_simd_shri(s, is_q, is_u, immh, immb, opcode, rn, rd); | |
8177 | break; | |
8178 | case 0x0a: /* SHL / SLI */ | |
8179 | handle_vec_simd_shli(s, is_q, is_u, immh, immb, opcode, rn, rd); | |
8180 | break; | |
c1b876b2 AB |
8181 | case 0x10: /* SHRN */ |
8182 | case 0x11: /* RSHRN / SQRSHRUN */ | |
8183 | if (is_u) { | |
8184 | handle_vec_simd_sqshrn(s, false, is_q, false, true, immh, immb, | |
8185 | opcode, rn, rd); | |
8186 | } else { | |
8187 | handle_vec_simd_shrn(s, is_q, immh, immb, opcode, rn, rd); | |
8188 | } | |
8189 | break; | |
8190 | case 0x12: /* SQSHRN / UQSHRN */ | |
8191 | case 0x13: /* SQRSHRN / UQRSHRN */ | |
8192 | handle_vec_simd_sqshrn(s, false, is_q, is_u, is_u, immh, immb, | |
8193 | opcode, rn, rd); | |
8194 | break; | |
4d1cef84 AB |
8195 | case 0x14: /* SSHLL / USHLL */ |
8196 | handle_vec_simd_wshli(s, is_q, is_u, immh, immb, opcode, rn, rd); | |
8197 | break; | |
10113b69 AB |
8198 | case 0x1c: /* SCVTF / UCVTF */ |
8199 | handle_simd_shift_intfp_conv(s, false, is_q, is_u, immh, immb, | |
8200 | opcode, rn, rd); | |
8201 | break; | |
a566da1b | 8202 | case 0xc: /* SQSHLU */ |
a847f32c PM |
8203 | if (!is_u) { |
8204 | unallocated_encoding(s); | |
8205 | return; | |
8206 | } | |
8207 | handle_simd_qshl(s, false, is_q, false, true, immh, immb, rn, rd); | |
8208 | break; | |
a566da1b | 8209 | case 0xe: /* SQSHL, UQSHL */ |
a847f32c PM |
8210 | handle_simd_qshl(s, false, is_q, is_u, is_u, immh, immb, rn, rd); |
8211 | break; | |
10113b69 | 8212 | case 0x1f: /* FCVTZS/ FCVTZU */ |
2ed3ea11 | 8213 | handle_simd_shift_fpint_conv(s, false, is_q, is_u, immh, immb, rn, rd); |
10113b69 | 8214 | return; |
4d1cef84 | 8215 | default: |
a566da1b | 8216 | unallocated_encoding(s); |
4d1cef84 AB |
8217 | return; |
8218 | } | |
384b26fb AB |
8219 | } |
8220 | ||
70d7f984 PM |
8221 | /* Generate code to do a "long" addition or subtraction, ie one done in |
8222 | * TCGv_i64 on vector lanes twice the width specified by size. | |
8223 | */ | |
8224 | static void gen_neon_addl(int size, bool is_sub, TCGv_i64 tcg_res, | |
8225 | TCGv_i64 tcg_op1, TCGv_i64 tcg_op2) | |
8226 | { | |
8227 | static NeonGenTwo64OpFn * const fns[3][2] = { | |
8228 | { gen_helper_neon_addl_u16, gen_helper_neon_subl_u16 }, | |
8229 | { gen_helper_neon_addl_u32, gen_helper_neon_subl_u32 }, | |
8230 | { tcg_gen_add_i64, tcg_gen_sub_i64 }, | |
8231 | }; | |
8232 | NeonGenTwo64OpFn *genfn; | |
8233 | assert(size < 3); | |
8234 | ||
8235 | genfn = fns[size][is_sub]; | |
8236 | genfn(tcg_res, tcg_op1, tcg_op2); | |
8237 | } | |
8238 | ||
a08582f4 PM |
8239 | static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size, |
8240 | int opcode, int rd, int rn, int rm) | |
8241 | { | |
8242 | /* 3-reg-different widening insns: 64 x 64 -> 128 */ | |
8243 | TCGv_i64 tcg_res[2]; | |
8244 | int pass, accop; | |
8245 | ||
8246 | tcg_res[0] = tcg_temp_new_i64(); | |
8247 | tcg_res[1] = tcg_temp_new_i64(); | |
8248 | ||
8249 | /* Does this op do an adding accumulate, a subtracting accumulate, | |
8250 | * or no accumulate at all? | |
8251 | */ | |
8252 | switch (opcode) { | |
8253 | case 5: | |
8254 | case 8: | |
8255 | case 9: | |
8256 | accop = 1; | |
8257 | break; | |
8258 | case 10: | |
8259 | case 11: | |
8260 | accop = -1; | |
8261 | break; | |
8262 | default: | |
8263 | accop = 0; | |
8264 | break; | |
8265 | } | |
8266 | ||
8267 | if (accop != 0) { | |
8268 | read_vec_element(s, tcg_res[0], rd, 0, MO_64); | |
8269 | read_vec_element(s, tcg_res[1], rd, 1, MO_64); | |
8270 | } | |
8271 | ||
8272 | /* size == 2 means two 32x32->64 operations; this is worth special | |
8273 | * casing because we can generally handle it inline. | |
8274 | */ | |
8275 | if (size == 2) { | |
8276 | for (pass = 0; pass < 2; pass++) { | |
8277 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
8278 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
8279 | TCGv_i64 tcg_passres; | |
8280 | TCGMemOp memop = MO_32 | (is_u ? 0 : MO_SIGN); | |
8281 | ||
8282 | int elt = pass + is_q * 2; | |
8283 | ||
8284 | read_vec_element(s, tcg_op1, rn, elt, memop); | |
8285 | read_vec_element(s, tcg_op2, rm, elt, memop); | |
8286 | ||
8287 | if (accop == 0) { | |
8288 | tcg_passres = tcg_res[pass]; | |
8289 | } else { | |
8290 | tcg_passres = tcg_temp_new_i64(); | |
8291 | } | |
8292 | ||
8293 | switch (opcode) { | |
70d7f984 PM |
8294 | case 0: /* SADDL, SADDL2, UADDL, UADDL2 */ |
8295 | tcg_gen_add_i64(tcg_passres, tcg_op1, tcg_op2); | |
8296 | break; | |
8297 | case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */ | |
8298 | tcg_gen_sub_i64(tcg_passres, tcg_op1, tcg_op2); | |
8299 | break; | |
0ae39320 PM |
8300 | case 5: /* SABAL, SABAL2, UABAL, UABAL2 */ |
8301 | case 7: /* SABDL, SABDL2, UABDL, UABDL2 */ | |
8302 | { | |
8303 | TCGv_i64 tcg_tmp1 = tcg_temp_new_i64(); | |
8304 | TCGv_i64 tcg_tmp2 = tcg_temp_new_i64(); | |
8305 | ||
8306 | tcg_gen_sub_i64(tcg_tmp1, tcg_op1, tcg_op2); | |
8307 | tcg_gen_sub_i64(tcg_tmp2, tcg_op2, tcg_op1); | |
8308 | tcg_gen_movcond_i64(is_u ? TCG_COND_GEU : TCG_COND_GE, | |
8309 | tcg_passres, | |
8310 | tcg_op1, tcg_op2, tcg_tmp1, tcg_tmp2); | |
8311 | tcg_temp_free_i64(tcg_tmp1); | |
8312 | tcg_temp_free_i64(tcg_tmp2); | |
8313 | break; | |
8314 | } | |
a08582f4 PM |
8315 | case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ |
8316 | case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
8317 | case 12: /* UMULL, UMULL2, SMULL, SMULL2 */ | |
8318 | tcg_gen_mul_i64(tcg_passres, tcg_op1, tcg_op2); | |
8319 | break; | |
70d7f984 PM |
8320 | case 9: /* SQDMLAL, SQDMLAL2 */ |
8321 | case 11: /* SQDMLSL, SQDMLSL2 */ | |
8322 | case 13: /* SQDMULL, SQDMULL2 */ | |
8323 | tcg_gen_mul_i64(tcg_passres, tcg_op1, tcg_op2); | |
8324 | gen_helper_neon_addl_saturate_s64(tcg_passres, cpu_env, | |
8325 | tcg_passres, tcg_passres); | |
8326 | break; | |
a08582f4 PM |
8327 | default: |
8328 | g_assert_not_reached(); | |
8329 | } | |
8330 | ||
70d7f984 PM |
8331 | if (opcode == 9 || opcode == 11) { |
8332 | /* saturating accumulate ops */ | |
8333 | if (accop < 0) { | |
8334 | tcg_gen_neg_i64(tcg_passres, tcg_passres); | |
8335 | } | |
8336 | gen_helper_neon_addl_saturate_s64(tcg_res[pass], cpu_env, | |
8337 | tcg_res[pass], tcg_passres); | |
8338 | } else if (accop > 0) { | |
a08582f4 | 8339 | tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_passres); |
a08582f4 PM |
8340 | } else if (accop < 0) { |
8341 | tcg_gen_sub_i64(tcg_res[pass], tcg_res[pass], tcg_passres); | |
70d7f984 PM |
8342 | } |
8343 | ||
8344 | if (accop != 0) { | |
a08582f4 PM |
8345 | tcg_temp_free_i64(tcg_passres); |
8346 | } | |
8347 | ||
8348 | tcg_temp_free_i64(tcg_op1); | |
8349 | tcg_temp_free_i64(tcg_op2); | |
8350 | } | |
8351 | } else { | |
8352 | /* size 0 or 1, generally helper functions */ | |
8353 | for (pass = 0; pass < 2; pass++) { | |
8354 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
8355 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
8356 | TCGv_i64 tcg_passres; | |
8357 | int elt = pass + is_q * 2; | |
8358 | ||
8359 | read_vec_element_i32(s, tcg_op1, rn, elt, MO_32); | |
8360 | read_vec_element_i32(s, tcg_op2, rm, elt, MO_32); | |
8361 | ||
8362 | if (accop == 0) { | |
8363 | tcg_passres = tcg_res[pass]; | |
8364 | } else { | |
8365 | tcg_passres = tcg_temp_new_i64(); | |
8366 | } | |
8367 | ||
8368 | switch (opcode) { | |
70d7f984 PM |
8369 | case 0: /* SADDL, SADDL2, UADDL, UADDL2 */ |
8370 | case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */ | |
8371 | { | |
8372 | TCGv_i64 tcg_op2_64 = tcg_temp_new_i64(); | |
8373 | static NeonGenWidenFn * const widenfns[2][2] = { | |
8374 | { gen_helper_neon_widen_s8, gen_helper_neon_widen_u8 }, | |
8375 | { gen_helper_neon_widen_s16, gen_helper_neon_widen_u16 }, | |
8376 | }; | |
8377 | NeonGenWidenFn *widenfn = widenfns[size][is_u]; | |
8378 | ||
8379 | widenfn(tcg_op2_64, tcg_op2); | |
8380 | widenfn(tcg_passres, tcg_op1); | |
8381 | gen_neon_addl(size, (opcode == 2), tcg_passres, | |
8382 | tcg_passres, tcg_op2_64); | |
8383 | tcg_temp_free_i64(tcg_op2_64); | |
8384 | break; | |
8385 | } | |
0ae39320 PM |
8386 | case 5: /* SABAL, SABAL2, UABAL, UABAL2 */ |
8387 | case 7: /* SABDL, SABDL2, UABDL, UABDL2 */ | |
8388 | if (size == 0) { | |
8389 | if (is_u) { | |
8390 | gen_helper_neon_abdl_u16(tcg_passres, tcg_op1, tcg_op2); | |
8391 | } else { | |
8392 | gen_helper_neon_abdl_s16(tcg_passres, tcg_op1, tcg_op2); | |
8393 | } | |
8394 | } else { | |
8395 | if (is_u) { | |
8396 | gen_helper_neon_abdl_u32(tcg_passres, tcg_op1, tcg_op2); | |
8397 | } else { | |
8398 | gen_helper_neon_abdl_s32(tcg_passres, tcg_op1, tcg_op2); | |
8399 | } | |
8400 | } | |
8401 | break; | |
a08582f4 PM |
8402 | case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ |
8403 | case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
8404 | case 12: /* UMULL, UMULL2, SMULL, SMULL2 */ | |
8405 | if (size == 0) { | |
8406 | if (is_u) { | |
8407 | gen_helper_neon_mull_u8(tcg_passres, tcg_op1, tcg_op2); | |
8408 | } else { | |
8409 | gen_helper_neon_mull_s8(tcg_passres, tcg_op1, tcg_op2); | |
8410 | } | |
8411 | } else { | |
8412 | if (is_u) { | |
8413 | gen_helper_neon_mull_u16(tcg_passres, tcg_op1, tcg_op2); | |
8414 | } else { | |
8415 | gen_helper_neon_mull_s16(tcg_passres, tcg_op1, tcg_op2); | |
8416 | } | |
8417 | } | |
8418 | break; | |
70d7f984 PM |
8419 | case 9: /* SQDMLAL, SQDMLAL2 */ |
8420 | case 11: /* SQDMLSL, SQDMLSL2 */ | |
8421 | case 13: /* SQDMULL, SQDMULL2 */ | |
8422 | assert(size == 1); | |
8423 | gen_helper_neon_mull_s16(tcg_passres, tcg_op1, tcg_op2); | |
8424 | gen_helper_neon_addl_saturate_s32(tcg_passres, cpu_env, | |
8425 | tcg_passres, tcg_passres); | |
8426 | break; | |
a984e42c PM |
8427 | case 14: /* PMULL */ |
8428 | assert(size == 0); | |
8429 | gen_helper_neon_mull_p8(tcg_passres, tcg_op1, tcg_op2); | |
8430 | break; | |
a08582f4 PM |
8431 | default: |
8432 | g_assert_not_reached(); | |
8433 | } | |
8434 | tcg_temp_free_i32(tcg_op1); | |
8435 | tcg_temp_free_i32(tcg_op2); | |
8436 | ||
70d7f984 PM |
8437 | if (accop != 0) { |
8438 | if (opcode == 9 || opcode == 11) { | |
8439 | /* saturating accumulate ops */ | |
8440 | if (accop < 0) { | |
8441 | gen_helper_neon_negl_u32(tcg_passres, tcg_passres); | |
8442 | } | |
8443 | gen_helper_neon_addl_saturate_s32(tcg_res[pass], cpu_env, | |
8444 | tcg_res[pass], | |
8445 | tcg_passres); | |
a08582f4 | 8446 | } else { |
70d7f984 PM |
8447 | gen_neon_addl(size, (accop < 0), tcg_res[pass], |
8448 | tcg_res[pass], tcg_passres); | |
a08582f4 PM |
8449 | } |
8450 | tcg_temp_free_i64(tcg_passres); | |
8451 | } | |
8452 | } | |
8453 | } | |
8454 | ||
8455 | write_vec_element(s, tcg_res[0], rd, 0, MO_64); | |
8456 | write_vec_element(s, tcg_res[1], rd, 1, MO_64); | |
8457 | tcg_temp_free_i64(tcg_res[0]); | |
8458 | tcg_temp_free_i64(tcg_res[1]); | |
8459 | } | |
8460 | ||
dfc15c7c PM |
8461 | static void handle_3rd_wide(DisasContext *s, int is_q, int is_u, int size, |
8462 | int opcode, int rd, int rn, int rm) | |
8463 | { | |
8464 | TCGv_i64 tcg_res[2]; | |
8465 | int part = is_q ? 2 : 0; | |
8466 | int pass; | |
8467 | ||
8468 | for (pass = 0; pass < 2; pass++) { | |
8469 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
8470 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
8471 | TCGv_i64 tcg_op2_wide = tcg_temp_new_i64(); | |
8472 | static NeonGenWidenFn * const widenfns[3][2] = { | |
8473 | { gen_helper_neon_widen_s8, gen_helper_neon_widen_u8 }, | |
8474 | { gen_helper_neon_widen_s16, gen_helper_neon_widen_u16 }, | |
8475 | { tcg_gen_ext_i32_i64, tcg_gen_extu_i32_i64 }, | |
8476 | }; | |
8477 | NeonGenWidenFn *widenfn = widenfns[size][is_u]; | |
8478 | ||
8479 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
8480 | read_vec_element_i32(s, tcg_op2, rm, part + pass, MO_32); | |
8481 | widenfn(tcg_op2_wide, tcg_op2); | |
8482 | tcg_temp_free_i32(tcg_op2); | |
8483 | tcg_res[pass] = tcg_temp_new_i64(); | |
8484 | gen_neon_addl(size, (opcode == 3), | |
8485 | tcg_res[pass], tcg_op1, tcg_op2_wide); | |
8486 | tcg_temp_free_i64(tcg_op1); | |
8487 | tcg_temp_free_i64(tcg_op2_wide); | |
8488 | } | |
8489 | ||
8490 | for (pass = 0; pass < 2; pass++) { | |
8491 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
8492 | tcg_temp_free_i64(tcg_res[pass]); | |
8493 | } | |
8494 | } | |
8495 | ||
e4b998d4 PM |
8496 | static void do_narrow_high_u32(TCGv_i32 res, TCGv_i64 in) |
8497 | { | |
8498 | tcg_gen_shri_i64(in, in, 32); | |
8499 | tcg_gen_trunc_i64_i32(res, in); | |
8500 | } | |
8501 | ||
8502 | static void do_narrow_round_high_u32(TCGv_i32 res, TCGv_i64 in) | |
8503 | { | |
8504 | tcg_gen_addi_i64(in, in, 1U << 31); | |
8505 | do_narrow_high_u32(res, in); | |
8506 | } | |
8507 | ||
8508 | static void handle_3rd_narrowing(DisasContext *s, int is_q, int is_u, int size, | |
8509 | int opcode, int rd, int rn, int rm) | |
8510 | { | |
8511 | TCGv_i32 tcg_res[2]; | |
8512 | int part = is_q ? 2 : 0; | |
8513 | int pass; | |
8514 | ||
8515 | for (pass = 0; pass < 2; pass++) { | |
8516 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
8517 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
8518 | TCGv_i64 tcg_wideres = tcg_temp_new_i64(); | |
8519 | static NeonGenNarrowFn * const narrowfns[3][2] = { | |
8520 | { gen_helper_neon_narrow_high_u8, | |
8521 | gen_helper_neon_narrow_round_high_u8 }, | |
8522 | { gen_helper_neon_narrow_high_u16, | |
8523 | gen_helper_neon_narrow_round_high_u16 }, | |
8524 | { do_narrow_high_u32, do_narrow_round_high_u32 }, | |
8525 | }; | |
8526 | NeonGenNarrowFn *gennarrow = narrowfns[size][is_u]; | |
8527 | ||
8528 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
8529 | read_vec_element(s, tcg_op2, rm, pass, MO_64); | |
8530 | ||
8531 | gen_neon_addl(size, (opcode == 6), tcg_wideres, tcg_op1, tcg_op2); | |
8532 | ||
8533 | tcg_temp_free_i64(tcg_op1); | |
8534 | tcg_temp_free_i64(tcg_op2); | |
8535 | ||
8536 | tcg_res[pass] = tcg_temp_new_i32(); | |
8537 | gennarrow(tcg_res[pass], tcg_wideres); | |
8538 | tcg_temp_free_i64(tcg_wideres); | |
8539 | } | |
8540 | ||
8541 | for (pass = 0; pass < 2; pass++) { | |
8542 | write_vec_element_i32(s, tcg_res[pass], rd, pass + part, MO_32); | |
8543 | tcg_temp_free_i32(tcg_res[pass]); | |
8544 | } | |
8545 | if (!is_q) { | |
8546 | clear_vec_high(s, rd); | |
8547 | } | |
8548 | } | |
8549 | ||
a984e42c PM |
8550 | static void handle_pmull_64(DisasContext *s, int is_q, int rd, int rn, int rm) |
8551 | { | |
8552 | /* PMULL of 64 x 64 -> 128 is an odd special case because it | |
8553 | * is the only three-reg-diff instruction which produces a | |
8554 | * 128-bit wide result from a single operation. However since | |
8555 | * it's possible to calculate the two halves more or less | |
8556 | * separately we just use two helper calls. | |
8557 | */ | |
8558 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
8559 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
8560 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
8561 | ||
8562 | read_vec_element(s, tcg_op1, rn, is_q, MO_64); | |
8563 | read_vec_element(s, tcg_op2, rm, is_q, MO_64); | |
8564 | gen_helper_neon_pmull_64_lo(tcg_res, tcg_op1, tcg_op2); | |
8565 | write_vec_element(s, tcg_res, rd, 0, MO_64); | |
8566 | gen_helper_neon_pmull_64_hi(tcg_res, tcg_op1, tcg_op2); | |
8567 | write_vec_element(s, tcg_res, rd, 1, MO_64); | |
8568 | ||
8569 | tcg_temp_free_i64(tcg_op1); | |
8570 | tcg_temp_free_i64(tcg_op2); | |
8571 | tcg_temp_free_i64(tcg_res); | |
8572 | } | |
8573 | ||
384b26fb AB |
8574 | /* C3.6.15 AdvSIMD three different |
8575 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 | |
8576 | * +---+---+---+-----------+------+---+------+--------+-----+------+------+ | |
8577 | * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd | | |
8578 | * +---+---+---+-----------+------+---+------+--------+-----+------+------+ | |
8579 | */ | |
8580 | static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn) | |
8581 | { | |
a08582f4 PM |
8582 | /* Instructions in this group fall into three basic classes |
8583 | * (in each case with the operation working on each element in | |
8584 | * the input vectors): | |
8585 | * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra | |
8586 | * 128 bit input) | |
8587 | * (2) wide 64 x 128 -> 128 | |
8588 | * (3) narrowing 128 x 128 -> 64 | |
8589 | * Here we do initial decode, catch unallocated cases and | |
8590 | * dispatch to separate functions for each class. | |
8591 | */ | |
8592 | int is_q = extract32(insn, 30, 1); | |
8593 | int is_u = extract32(insn, 29, 1); | |
8594 | int size = extract32(insn, 22, 2); | |
8595 | int opcode = extract32(insn, 12, 4); | |
8596 | int rm = extract32(insn, 16, 5); | |
8597 | int rn = extract32(insn, 5, 5); | |
8598 | int rd = extract32(insn, 0, 5); | |
8599 | ||
8600 | switch (opcode) { | |
8601 | case 1: /* SADDW, SADDW2, UADDW, UADDW2 */ | |
8602 | case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */ | |
8603 | /* 64 x 128 -> 128 */ | |
dfc15c7c PM |
8604 | if (size == 3) { |
8605 | unallocated_encoding(s); | |
8606 | return; | |
8607 | } | |
8c6afa6a PM |
8608 | if (!fp_access_check(s)) { |
8609 | return; | |
8610 | } | |
dfc15c7c | 8611 | handle_3rd_wide(s, is_q, is_u, size, opcode, rd, rn, rm); |
a08582f4 PM |
8612 | break; |
8613 | case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */ | |
8614 | case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */ | |
8615 | /* 128 x 128 -> 64 */ | |
e4b998d4 PM |
8616 | if (size == 3) { |
8617 | unallocated_encoding(s); | |
8618 | return; | |
8619 | } | |
8c6afa6a PM |
8620 | if (!fp_access_check(s)) { |
8621 | return; | |
8622 | } | |
e4b998d4 | 8623 | handle_3rd_narrowing(s, is_q, is_u, size, opcode, rd, rn, rm); |
a08582f4 | 8624 | break; |
70d7f984 PM |
8625 | case 14: /* PMULL, PMULL2 */ |
8626 | if (is_u || size == 1 || size == 2) { | |
8627 | unallocated_encoding(s); | |
8628 | return; | |
8629 | } | |
a984e42c | 8630 | if (size == 3) { |
411bdc78 | 8631 | if (!arm_dc_feature(s, ARM_FEATURE_V8_PMULL)) { |
a984e42c PM |
8632 | unallocated_encoding(s); |
8633 | return; | |
8634 | } | |
8c6afa6a PM |
8635 | if (!fp_access_check(s)) { |
8636 | return; | |
8637 | } | |
a984e42c PM |
8638 | handle_pmull_64(s, is_q, rd, rn, rm); |
8639 | return; | |
8640 | } | |
8641 | goto is_widening; | |
13caf1fd PM |
8642 | case 9: /* SQDMLAL, SQDMLAL2 */ |
8643 | case 11: /* SQDMLSL, SQDMLSL2 */ | |
8644 | case 13: /* SQDMULL, SQDMULL2 */ | |
70d7f984 | 8645 | if (is_u || size == 0) { |
a08582f4 PM |
8646 | unallocated_encoding(s); |
8647 | return; | |
8648 | } | |
8649 | /* fall through */ | |
13caf1fd PM |
8650 | case 0: /* SADDL, SADDL2, UADDL, UADDL2 */ |
8651 | case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */ | |
13caf1fd PM |
8652 | case 5: /* SABAL, SABAL2, UABAL, UABAL2 */ |
8653 | case 7: /* SABDL, SABDL2, UABDL, UABDL2 */ | |
8654 | case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ | |
8655 | case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
8656 | case 12: /* SMULL, SMULL2, UMULL, UMULL2 */ | |
a08582f4 PM |
8657 | /* 64 x 64 -> 128 */ |
8658 | if (size == 3) { | |
8659 | unallocated_encoding(s); | |
8660 | return; | |
8661 | } | |
a984e42c | 8662 | is_widening: |
8c6afa6a PM |
8663 | if (!fp_access_check(s)) { |
8664 | return; | |
8665 | } | |
8666 | ||
a08582f4 PM |
8667 | handle_3rd_widening(s, is_q, is_u, size, opcode, rd, rn, rm); |
8668 | break; | |
8669 | default: | |
8670 | /* opcode 15 not allocated */ | |
8671 | unallocated_encoding(s); | |
8672 | break; | |
8673 | } | |
384b26fb AB |
8674 | } |
8675 | ||
e1cea114 PM |
8676 | /* Logic op (opcode == 3) subgroup of C3.6.16. */ |
8677 | static void disas_simd_3same_logic(DisasContext *s, uint32_t insn) | |
8678 | { | |
956d272e PM |
8679 | int rd = extract32(insn, 0, 5); |
8680 | int rn = extract32(insn, 5, 5); | |
8681 | int rm = extract32(insn, 16, 5); | |
8682 | int size = extract32(insn, 22, 2); | |
8683 | bool is_u = extract32(insn, 29, 1); | |
8684 | bool is_q = extract32(insn, 30, 1); | |
8c6afa6a | 8685 | TCGv_i64 tcg_op1, tcg_op2, tcg_res[2]; |
956d272e PM |
8686 | int pass; |
8687 | ||
8c6afa6a PM |
8688 | if (!fp_access_check(s)) { |
8689 | return; | |
8690 | } | |
8691 | ||
8692 | tcg_op1 = tcg_temp_new_i64(); | |
8693 | tcg_op2 = tcg_temp_new_i64(); | |
956d272e PM |
8694 | tcg_res[0] = tcg_temp_new_i64(); |
8695 | tcg_res[1] = tcg_temp_new_i64(); | |
8696 | ||
8697 | for (pass = 0; pass < (is_q ? 2 : 1); pass++) { | |
8698 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
8699 | read_vec_element(s, tcg_op2, rm, pass, MO_64); | |
8700 | ||
8701 | if (!is_u) { | |
8702 | switch (size) { | |
8703 | case 0: /* AND */ | |
8704 | tcg_gen_and_i64(tcg_res[pass], tcg_op1, tcg_op2); | |
8705 | break; | |
8706 | case 1: /* BIC */ | |
8707 | tcg_gen_andc_i64(tcg_res[pass], tcg_op1, tcg_op2); | |
8708 | break; | |
8709 | case 2: /* ORR */ | |
8710 | tcg_gen_or_i64(tcg_res[pass], tcg_op1, tcg_op2); | |
8711 | break; | |
8712 | case 3: /* ORN */ | |
8713 | tcg_gen_orc_i64(tcg_res[pass], tcg_op1, tcg_op2); | |
8714 | break; | |
8715 | } | |
8716 | } else { | |
8717 | if (size != 0) { | |
8718 | /* B* ops need res loaded to operate on */ | |
8719 | read_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
8720 | } | |
8721 | ||
8722 | switch (size) { | |
8723 | case 0: /* EOR */ | |
8724 | tcg_gen_xor_i64(tcg_res[pass], tcg_op1, tcg_op2); | |
8725 | break; | |
8726 | case 1: /* BSL bitwise select */ | |
8727 | tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_op2); | |
8728 | tcg_gen_and_i64(tcg_op1, tcg_op1, tcg_res[pass]); | |
8729 | tcg_gen_xor_i64(tcg_res[pass], tcg_op2, tcg_op1); | |
8730 | break; | |
8731 | case 2: /* BIT, bitwise insert if true */ | |
8732 | tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_res[pass]); | |
8733 | tcg_gen_and_i64(tcg_op1, tcg_op1, tcg_op2); | |
8734 | tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1); | |
8735 | break; | |
8736 | case 3: /* BIF, bitwise insert if false */ | |
8737 | tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_res[pass]); | |
8738 | tcg_gen_andc_i64(tcg_op1, tcg_op1, tcg_op2); | |
8739 | tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1); | |
8740 | break; | |
8741 | } | |
8742 | } | |
8743 | } | |
8744 | ||
8745 | write_vec_element(s, tcg_res[0], rd, 0, MO_64); | |
8746 | if (!is_q) { | |
8747 | tcg_gen_movi_i64(tcg_res[1], 0); | |
8748 | } | |
8749 | write_vec_element(s, tcg_res[1], rd, 1, MO_64); | |
8750 | ||
8751 | tcg_temp_free_i64(tcg_op1); | |
8752 | tcg_temp_free_i64(tcg_op2); | |
8753 | tcg_temp_free_i64(tcg_res[0]); | |
8754 | tcg_temp_free_i64(tcg_res[1]); | |
e1cea114 PM |
8755 | } |
8756 | ||
8b12a0cf PM |
8757 | /* Helper functions for 32 bit comparisons */ |
8758 | static void gen_max_s32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2) | |
8759 | { | |
8760 | tcg_gen_movcond_i32(TCG_COND_GE, res, op1, op2, op1, op2); | |
8761 | } | |
8762 | ||
8763 | static void gen_max_u32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2) | |
8764 | { | |
8765 | tcg_gen_movcond_i32(TCG_COND_GEU, res, op1, op2, op1, op2); | |
8766 | } | |
8767 | ||
8768 | static void gen_min_s32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2) | |
8769 | { | |
8770 | tcg_gen_movcond_i32(TCG_COND_LE, res, op1, op2, op1, op2); | |
8771 | } | |
8772 | ||
8773 | static void gen_min_u32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2) | |
8774 | { | |
8775 | tcg_gen_movcond_i32(TCG_COND_LEU, res, op1, op2, op1, op2); | |
8776 | } | |
8777 | ||
bc242f9b AB |
8778 | /* Pairwise op subgroup of C3.6.16. |
8779 | * | |
8780 | * This is called directly or via the handle_3same_float for float pairwise | |
8781 | * operations where the opcode and size are calculated differently. | |
8782 | */ | |
8783 | static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode, | |
8784 | int size, int rn, int rm, int rd) | |
e1cea114 | 8785 | { |
bc242f9b | 8786 | TCGv_ptr fpst; |
0173a005 PM |
8787 | int pass; |
8788 | ||
bc242f9b AB |
8789 | /* Floating point operations need fpst */ |
8790 | if (opcode >= 0x58) { | |
8791 | fpst = get_fpstatus_ptr(); | |
8792 | } else { | |
8793 | TCGV_UNUSED_PTR(fpst); | |
0173a005 PM |
8794 | } |
8795 | ||
8c6afa6a PM |
8796 | if (!fp_access_check(s)) { |
8797 | return; | |
8798 | } | |
8799 | ||
0173a005 PM |
8800 | /* These operations work on the concatenated rm:rn, with each pair of |
8801 | * adjacent elements being operated on to produce an element in the result. | |
8802 | */ | |
8803 | if (size == 3) { | |
8804 | TCGv_i64 tcg_res[2]; | |
8805 | ||
8806 | for (pass = 0; pass < 2; pass++) { | |
8807 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
8808 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
8809 | int passreg = (pass == 0) ? rn : rm; | |
8810 | ||
8811 | read_vec_element(s, tcg_op1, passreg, 0, MO_64); | |
8812 | read_vec_element(s, tcg_op2, passreg, 1, MO_64); | |
8813 | tcg_res[pass] = tcg_temp_new_i64(); | |
8814 | ||
bc242f9b AB |
8815 | switch (opcode) { |
8816 | case 0x17: /* ADDP */ | |
8817 | tcg_gen_add_i64(tcg_res[pass], tcg_op1, tcg_op2); | |
8818 | break; | |
8819 | case 0x58: /* FMAXNMP */ | |
8820 | gen_helper_vfp_maxnumd(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
8821 | break; | |
8822 | case 0x5a: /* FADDP */ | |
8823 | gen_helper_vfp_addd(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
8824 | break; | |
8825 | case 0x5e: /* FMAXP */ | |
8826 | gen_helper_vfp_maxd(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
8827 | break; | |
8828 | case 0x78: /* FMINNMP */ | |
8829 | gen_helper_vfp_minnumd(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
8830 | break; | |
8831 | case 0x7e: /* FMINP */ | |
8832 | gen_helper_vfp_mind(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
8833 | break; | |
8834 | default: | |
8835 | g_assert_not_reached(); | |
8836 | } | |
0173a005 PM |
8837 | |
8838 | tcg_temp_free_i64(tcg_op1); | |
8839 | tcg_temp_free_i64(tcg_op2); | |
8840 | } | |
8841 | ||
8842 | for (pass = 0; pass < 2; pass++) { | |
8843 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
8844 | tcg_temp_free_i64(tcg_res[pass]); | |
8845 | } | |
8846 | } else { | |
8847 | int maxpass = is_q ? 4 : 2; | |
8848 | TCGv_i32 tcg_res[4]; | |
8849 | ||
8850 | for (pass = 0; pass < maxpass; pass++) { | |
8851 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
8852 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
bc242f9b | 8853 | NeonGenTwoOpFn *genfn = NULL; |
0173a005 PM |
8854 | int passreg = pass < (maxpass / 2) ? rn : rm; |
8855 | int passelt = (is_q && (pass & 1)) ? 2 : 0; | |
8856 | ||
8857 | read_vec_element_i32(s, tcg_op1, passreg, passelt, MO_32); | |
8858 | read_vec_element_i32(s, tcg_op2, passreg, passelt + 1, MO_32); | |
8859 | tcg_res[pass] = tcg_temp_new_i32(); | |
8860 | ||
8861 | switch (opcode) { | |
8862 | case 0x17: /* ADDP */ | |
8863 | { | |
8864 | static NeonGenTwoOpFn * const fns[3] = { | |
8865 | gen_helper_neon_padd_u8, | |
8866 | gen_helper_neon_padd_u16, | |
8867 | tcg_gen_add_i32, | |
8868 | }; | |
8869 | genfn = fns[size]; | |
8870 | break; | |
8871 | } | |
8872 | case 0x14: /* SMAXP, UMAXP */ | |
8873 | { | |
8874 | static NeonGenTwoOpFn * const fns[3][2] = { | |
8875 | { gen_helper_neon_pmax_s8, gen_helper_neon_pmax_u8 }, | |
8876 | { gen_helper_neon_pmax_s16, gen_helper_neon_pmax_u16 }, | |
8877 | { gen_max_s32, gen_max_u32 }, | |
8878 | }; | |
8879 | genfn = fns[size][u]; | |
8880 | break; | |
8881 | } | |
8882 | case 0x15: /* SMINP, UMINP */ | |
8883 | { | |
8884 | static NeonGenTwoOpFn * const fns[3][2] = { | |
8885 | { gen_helper_neon_pmin_s8, gen_helper_neon_pmin_u8 }, | |
8886 | { gen_helper_neon_pmin_s16, gen_helper_neon_pmin_u16 }, | |
8887 | { gen_min_s32, gen_min_u32 }, | |
8888 | }; | |
8889 | genfn = fns[size][u]; | |
8890 | break; | |
8891 | } | |
bc242f9b AB |
8892 | /* The FP operations are all on single floats (32 bit) */ |
8893 | case 0x58: /* FMAXNMP */ | |
8894 | gen_helper_vfp_maxnums(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
8895 | break; | |
8896 | case 0x5a: /* FADDP */ | |
8897 | gen_helper_vfp_adds(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
8898 | break; | |
8899 | case 0x5e: /* FMAXP */ | |
8900 | gen_helper_vfp_maxs(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
8901 | break; | |
8902 | case 0x78: /* FMINNMP */ | |
8903 | gen_helper_vfp_minnums(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
8904 | break; | |
8905 | case 0x7e: /* FMINP */ | |
8906 | gen_helper_vfp_mins(tcg_res[pass], tcg_op1, tcg_op2, fpst); | |
8907 | break; | |
0173a005 PM |
8908 | default: |
8909 | g_assert_not_reached(); | |
8910 | } | |
8911 | ||
bc242f9b AB |
8912 | /* FP ops called directly, otherwise call now */ |
8913 | if (genfn) { | |
8914 | genfn(tcg_res[pass], tcg_op1, tcg_op2); | |
8915 | } | |
0173a005 PM |
8916 | |
8917 | tcg_temp_free_i32(tcg_op1); | |
8918 | tcg_temp_free_i32(tcg_op2); | |
8919 | } | |
8920 | ||
8921 | for (pass = 0; pass < maxpass; pass++) { | |
8922 | write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32); | |
8923 | tcg_temp_free_i32(tcg_res[pass]); | |
8924 | } | |
8925 | if (!is_q) { | |
8926 | clear_vec_high(s, rd); | |
8927 | } | |
8928 | } | |
bc242f9b AB |
8929 | |
8930 | if (!TCGV_IS_UNUSED_PTR(fpst)) { | |
8931 | tcg_temp_free_ptr(fpst); | |
8932 | } | |
e1cea114 PM |
8933 | } |
8934 | ||
8935 | /* Floating point op subgroup of C3.6.16. */ | |
8936 | static void disas_simd_3same_float(DisasContext *s, uint32_t insn) | |
8937 | { | |
845ea09a PM |
8938 | /* For floating point ops, the U, size[1] and opcode bits |
8939 | * together indicate the operation. size[0] indicates single | |
8940 | * or double. | |
8941 | */ | |
8942 | int fpopcode = extract32(insn, 11, 5) | |
8943 | | (extract32(insn, 23, 1) << 5) | |
8944 | | (extract32(insn, 29, 1) << 6); | |
8945 | int is_q = extract32(insn, 30, 1); | |
8946 | int size = extract32(insn, 22, 1); | |
8947 | int rm = extract32(insn, 16, 5); | |
8948 | int rn = extract32(insn, 5, 5); | |
8949 | int rd = extract32(insn, 0, 5); | |
8950 | ||
8951 | int datasize = is_q ? 128 : 64; | |
8952 | int esize = 32 << size; | |
8953 | int elements = datasize / esize; | |
8954 | ||
8955 | if (size == 1 && !is_q) { | |
8956 | unallocated_encoding(s); | |
8957 | return; | |
8958 | } | |
8959 | ||
8960 | switch (fpopcode) { | |
8961 | case 0x58: /* FMAXNMP */ | |
8962 | case 0x5a: /* FADDP */ | |
8963 | case 0x5e: /* FMAXP */ | |
8964 | case 0x78: /* FMINNMP */ | |
8965 | case 0x7e: /* FMINP */ | |
bc242f9b AB |
8966 | if (size && !is_q) { |
8967 | unallocated_encoding(s); | |
8968 | return; | |
8969 | } | |
8970 | handle_simd_3same_pair(s, is_q, 0, fpopcode, size ? MO_64 : MO_32, | |
8971 | rn, rm, rd); | |
845ea09a PM |
8972 | return; |
8973 | case 0x1b: /* FMULX */ | |
845ea09a PM |
8974 | case 0x1f: /* FRECPS */ |
8975 | case 0x3f: /* FRSQRTS */ | |
845ea09a | 8976 | case 0x5d: /* FACGE */ |
845ea09a PM |
8977 | case 0x7d: /* FACGT */ |
8978 | case 0x19: /* FMLA */ | |
8979 | case 0x39: /* FMLS */ | |
845ea09a PM |
8980 | case 0x18: /* FMAXNM */ |
8981 | case 0x1a: /* FADD */ | |
8908f4d1 | 8982 | case 0x1c: /* FCMEQ */ |
845ea09a PM |
8983 | case 0x1e: /* FMAX */ |
8984 | case 0x38: /* FMINNM */ | |
8985 | case 0x3a: /* FSUB */ | |
8986 | case 0x3e: /* FMIN */ | |
8987 | case 0x5b: /* FMUL */ | |
8908f4d1 | 8988 | case 0x5c: /* FCMGE */ |
845ea09a PM |
8989 | case 0x5f: /* FDIV */ |
8990 | case 0x7a: /* FABD */ | |
8908f4d1 | 8991 | case 0x7c: /* FCMGT */ |
8c6afa6a PM |
8992 | if (!fp_access_check(s)) { |
8993 | return; | |
8994 | } | |
8995 | ||
845ea09a PM |
8996 | handle_3same_float(s, size, elements, fpopcode, rd, rn, rm); |
8997 | return; | |
8998 | default: | |
8999 | unallocated_encoding(s); | |
9000 | return; | |
9001 | } | |
e1cea114 PM |
9002 | } |
9003 | ||
9004 | /* Integer op subgroup of C3.6.16. */ | |
9005 | static void disas_simd_3same_int(DisasContext *s, uint32_t insn) | |
9006 | { | |
1f8a73af PM |
9007 | int is_q = extract32(insn, 30, 1); |
9008 | int u = extract32(insn, 29, 1); | |
9009 | int size = extract32(insn, 22, 2); | |
9010 | int opcode = extract32(insn, 11, 5); | |
9011 | int rm = extract32(insn, 16, 5); | |
9012 | int rn = extract32(insn, 5, 5); | |
9013 | int rd = extract32(insn, 0, 5); | |
9014 | int pass; | |
9015 | ||
9016 | switch (opcode) { | |
9017 | case 0x13: /* MUL, PMUL */ | |
9018 | if (u && size != 0) { | |
9019 | unallocated_encoding(s); | |
9020 | return; | |
9021 | } | |
9022 | /* fall through */ | |
9023 | case 0x0: /* SHADD, UHADD */ | |
9024 | case 0x2: /* SRHADD, URHADD */ | |
9025 | case 0x4: /* SHSUB, UHSUB */ | |
9026 | case 0xc: /* SMAX, UMAX */ | |
9027 | case 0xd: /* SMIN, UMIN */ | |
9028 | case 0xe: /* SABD, UABD */ | |
9029 | case 0xf: /* SABA, UABA */ | |
9030 | case 0x12: /* MLA, MLS */ | |
9031 | if (size == 3) { | |
9032 | unallocated_encoding(s); | |
9033 | return; | |
9034 | } | |
8b12a0cf | 9035 | break; |
1f8a73af PM |
9036 | case 0x16: /* SQDMULH, SQRDMULH */ |
9037 | if (size == 0 || size == 3) { | |
9038 | unallocated_encoding(s); | |
9039 | return; | |
9040 | } | |
8b12a0cf | 9041 | break; |
1f8a73af PM |
9042 | default: |
9043 | if (size == 3 && !is_q) { | |
9044 | unallocated_encoding(s); | |
9045 | return; | |
9046 | } | |
9047 | break; | |
9048 | } | |
9049 | ||
8c6afa6a PM |
9050 | if (!fp_access_check(s)) { |
9051 | return; | |
9052 | } | |
9053 | ||
1f8a73af | 9054 | if (size == 3) { |
220ad4ca PM |
9055 | assert(is_q); |
9056 | for (pass = 0; pass < 2; pass++) { | |
1f8a73af PM |
9057 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); |
9058 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
9059 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
9060 | ||
9061 | read_vec_element(s, tcg_op1, rn, pass, MO_64); | |
9062 | read_vec_element(s, tcg_op2, rm, pass, MO_64); | |
9063 | ||
9064 | handle_3same_64(s, opcode, u, tcg_res, tcg_op1, tcg_op2); | |
9065 | ||
9066 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
9067 | ||
9068 | tcg_temp_free_i64(tcg_res); | |
9069 | tcg_temp_free_i64(tcg_op1); | |
9070 | tcg_temp_free_i64(tcg_op2); | |
9071 | } | |
9072 | } else { | |
9073 | for (pass = 0; pass < (is_q ? 4 : 2); pass++) { | |
9074 | TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | |
9075 | TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | |
9076 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
6d9571f7 PM |
9077 | NeonGenTwoOpFn *genfn = NULL; |
9078 | NeonGenTwoOpEnvFn *genenvfn = NULL; | |
1f8a73af PM |
9079 | |
9080 | read_vec_element_i32(s, tcg_op1, rn, pass, MO_32); | |
9081 | read_vec_element_i32(s, tcg_op2, rm, pass, MO_32); | |
9082 | ||
9083 | switch (opcode) { | |
8b12a0cf PM |
9084 | case 0x0: /* SHADD, UHADD */ |
9085 | { | |
9086 | static NeonGenTwoOpFn * const fns[3][2] = { | |
9087 | { gen_helper_neon_hadd_s8, gen_helper_neon_hadd_u8 }, | |
9088 | { gen_helper_neon_hadd_s16, gen_helper_neon_hadd_u16 }, | |
9089 | { gen_helper_neon_hadd_s32, gen_helper_neon_hadd_u32 }, | |
9090 | }; | |
9091 | genfn = fns[size][u]; | |
9092 | break; | |
9093 | } | |
6d9571f7 PM |
9094 | case 0x1: /* SQADD, UQADD */ |
9095 | { | |
9096 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
9097 | { gen_helper_neon_qadd_s8, gen_helper_neon_qadd_u8 }, | |
9098 | { gen_helper_neon_qadd_s16, gen_helper_neon_qadd_u16 }, | |
9099 | { gen_helper_neon_qadd_s32, gen_helper_neon_qadd_u32 }, | |
9100 | }; | |
9101 | genenvfn = fns[size][u]; | |
9102 | break; | |
9103 | } | |
8b12a0cf PM |
9104 | case 0x2: /* SRHADD, URHADD */ |
9105 | { | |
9106 | static NeonGenTwoOpFn * const fns[3][2] = { | |
9107 | { gen_helper_neon_rhadd_s8, gen_helper_neon_rhadd_u8 }, | |
9108 | { gen_helper_neon_rhadd_s16, gen_helper_neon_rhadd_u16 }, | |
9109 | { gen_helper_neon_rhadd_s32, gen_helper_neon_rhadd_u32 }, | |
9110 | }; | |
9111 | genfn = fns[size][u]; | |
9112 | break; | |
9113 | } | |
9114 | case 0x4: /* SHSUB, UHSUB */ | |
9115 | { | |
9116 | static NeonGenTwoOpFn * const fns[3][2] = { | |
9117 | { gen_helper_neon_hsub_s8, gen_helper_neon_hsub_u8 }, | |
9118 | { gen_helper_neon_hsub_s16, gen_helper_neon_hsub_u16 }, | |
9119 | { gen_helper_neon_hsub_s32, gen_helper_neon_hsub_u32 }, | |
9120 | }; | |
9121 | genfn = fns[size][u]; | |
9122 | break; | |
9123 | } | |
6d9571f7 PM |
9124 | case 0x5: /* SQSUB, UQSUB */ |
9125 | { | |
9126 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
9127 | { gen_helper_neon_qsub_s8, gen_helper_neon_qsub_u8 }, | |
9128 | { gen_helper_neon_qsub_s16, gen_helper_neon_qsub_u16 }, | |
9129 | { gen_helper_neon_qsub_s32, gen_helper_neon_qsub_u32 }, | |
9130 | }; | |
9131 | genenvfn = fns[size][u]; | |
9132 | break; | |
9133 | } | |
1f8a73af PM |
9134 | case 0x6: /* CMGT, CMHI */ |
9135 | { | |
9136 | static NeonGenTwoOpFn * const fns[3][2] = { | |
9137 | { gen_helper_neon_cgt_s8, gen_helper_neon_cgt_u8 }, | |
9138 | { gen_helper_neon_cgt_s16, gen_helper_neon_cgt_u16 }, | |
9139 | { gen_helper_neon_cgt_s32, gen_helper_neon_cgt_u32 }, | |
9140 | }; | |
9141 | genfn = fns[size][u]; | |
9142 | break; | |
9143 | } | |
9144 | case 0x7: /* CMGE, CMHS */ | |
9145 | { | |
9146 | static NeonGenTwoOpFn * const fns[3][2] = { | |
9147 | { gen_helper_neon_cge_s8, gen_helper_neon_cge_u8 }, | |
9148 | { gen_helper_neon_cge_s16, gen_helper_neon_cge_u16 }, | |
9149 | { gen_helper_neon_cge_s32, gen_helper_neon_cge_u32 }, | |
9150 | }; | |
9151 | genfn = fns[size][u]; | |
9152 | break; | |
9153 | } | |
6d9571f7 PM |
9154 | case 0x8: /* SSHL, USHL */ |
9155 | { | |
9156 | static NeonGenTwoOpFn * const fns[3][2] = { | |
9157 | { gen_helper_neon_shl_s8, gen_helper_neon_shl_u8 }, | |
9158 | { gen_helper_neon_shl_s16, gen_helper_neon_shl_u16 }, | |
9159 | { gen_helper_neon_shl_s32, gen_helper_neon_shl_u32 }, | |
9160 | }; | |
9161 | genfn = fns[size][u]; | |
9162 | break; | |
9163 | } | |
9164 | case 0x9: /* SQSHL, UQSHL */ | |
9165 | { | |
9166 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
9167 | { gen_helper_neon_qshl_s8, gen_helper_neon_qshl_u8 }, | |
9168 | { gen_helper_neon_qshl_s16, gen_helper_neon_qshl_u16 }, | |
9169 | { gen_helper_neon_qshl_s32, gen_helper_neon_qshl_u32 }, | |
9170 | }; | |
9171 | genenvfn = fns[size][u]; | |
9172 | break; | |
9173 | } | |
9174 | case 0xa: /* SRSHL, URSHL */ | |
9175 | { | |
9176 | static NeonGenTwoOpFn * const fns[3][2] = { | |
9177 | { gen_helper_neon_rshl_s8, gen_helper_neon_rshl_u8 }, | |
9178 | { gen_helper_neon_rshl_s16, gen_helper_neon_rshl_u16 }, | |
9179 | { gen_helper_neon_rshl_s32, gen_helper_neon_rshl_u32 }, | |
9180 | }; | |
9181 | genfn = fns[size][u]; | |
9182 | break; | |
9183 | } | |
9184 | case 0xb: /* SQRSHL, UQRSHL */ | |
9185 | { | |
9186 | static NeonGenTwoOpEnvFn * const fns[3][2] = { | |
9187 | { gen_helper_neon_qrshl_s8, gen_helper_neon_qrshl_u8 }, | |
9188 | { gen_helper_neon_qrshl_s16, gen_helper_neon_qrshl_u16 }, | |
9189 | { gen_helper_neon_qrshl_s32, gen_helper_neon_qrshl_u32 }, | |
9190 | }; | |
9191 | genenvfn = fns[size][u]; | |
9192 | break; | |
9193 | } | |
8b12a0cf PM |
9194 | case 0xc: /* SMAX, UMAX */ |
9195 | { | |
9196 | static NeonGenTwoOpFn * const fns[3][2] = { | |
9197 | { gen_helper_neon_max_s8, gen_helper_neon_max_u8 }, | |
9198 | { gen_helper_neon_max_s16, gen_helper_neon_max_u16 }, | |
9199 | { gen_max_s32, gen_max_u32 }, | |
9200 | }; | |
9201 | genfn = fns[size][u]; | |
9202 | break; | |
9203 | } | |
9204 | ||
9205 | case 0xd: /* SMIN, UMIN */ | |
9206 | { | |
9207 | static NeonGenTwoOpFn * const fns[3][2] = { | |
9208 | { gen_helper_neon_min_s8, gen_helper_neon_min_u8 }, | |
9209 | { gen_helper_neon_min_s16, gen_helper_neon_min_u16 }, | |
9210 | { gen_min_s32, gen_min_u32 }, | |
9211 | }; | |
9212 | genfn = fns[size][u]; | |
9213 | break; | |
9214 | } | |
9215 | case 0xe: /* SABD, UABD */ | |
9216 | case 0xf: /* SABA, UABA */ | |
9217 | { | |
9218 | static NeonGenTwoOpFn * const fns[3][2] = { | |
9219 | { gen_helper_neon_abd_s8, gen_helper_neon_abd_u8 }, | |
9220 | { gen_helper_neon_abd_s16, gen_helper_neon_abd_u16 }, | |
9221 | { gen_helper_neon_abd_s32, gen_helper_neon_abd_u32 }, | |
9222 | }; | |
9223 | genfn = fns[size][u]; | |
9224 | break; | |
9225 | } | |
1f8a73af PM |
9226 | case 0x10: /* ADD, SUB */ |
9227 | { | |
9228 | static NeonGenTwoOpFn * const fns[3][2] = { | |
9229 | { gen_helper_neon_add_u8, gen_helper_neon_sub_u8 }, | |
9230 | { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 }, | |
9231 | { tcg_gen_add_i32, tcg_gen_sub_i32 }, | |
9232 | }; | |
9233 | genfn = fns[size][u]; | |
9234 | break; | |
9235 | } | |
9236 | case 0x11: /* CMTST, CMEQ */ | |
9237 | { | |
9238 | static NeonGenTwoOpFn * const fns[3][2] = { | |
9239 | { gen_helper_neon_tst_u8, gen_helper_neon_ceq_u8 }, | |
9240 | { gen_helper_neon_tst_u16, gen_helper_neon_ceq_u16 }, | |
9241 | { gen_helper_neon_tst_u32, gen_helper_neon_ceq_u32 }, | |
9242 | }; | |
9243 | genfn = fns[size][u]; | |
9244 | break; | |
9245 | } | |
8b12a0cf PM |
9246 | case 0x13: /* MUL, PMUL */ |
9247 | if (u) { | |
9248 | /* PMUL */ | |
9249 | assert(size == 0); | |
9250 | genfn = gen_helper_neon_mul_p8; | |
9251 | break; | |
9252 | } | |
9253 | /* fall through : MUL */ | |
9254 | case 0x12: /* MLA, MLS */ | |
9255 | { | |
9256 | static NeonGenTwoOpFn * const fns[3] = { | |
9257 | gen_helper_neon_mul_u8, | |
9258 | gen_helper_neon_mul_u16, | |
9259 | tcg_gen_mul_i32, | |
9260 | }; | |
9261 | genfn = fns[size]; | |
9262 | break; | |
9263 | } | |
9264 | case 0x16: /* SQDMULH, SQRDMULH */ | |
9265 | { | |
9266 | static NeonGenTwoOpEnvFn * const fns[2][2] = { | |
9267 | { gen_helper_neon_qdmulh_s16, gen_helper_neon_qrdmulh_s16 }, | |
9268 | { gen_helper_neon_qdmulh_s32, gen_helper_neon_qrdmulh_s32 }, | |
9269 | }; | |
9270 | assert(size == 1 || size == 2); | |
9271 | genenvfn = fns[size - 1][u]; | |
9272 | break; | |
9273 | } | |
1f8a73af PM |
9274 | default: |
9275 | g_assert_not_reached(); | |
9276 | } | |
9277 | ||
6d9571f7 PM |
9278 | if (genenvfn) { |
9279 | genenvfn(tcg_res, cpu_env, tcg_op1, tcg_op2); | |
9280 | } else { | |
9281 | genfn(tcg_res, tcg_op1, tcg_op2); | |
9282 | } | |
1f8a73af | 9283 | |
8b12a0cf PM |
9284 | if (opcode == 0xf || opcode == 0x12) { |
9285 | /* SABA, UABA, MLA, MLS: accumulating ops */ | |
9286 | static NeonGenTwoOpFn * const fns[3][2] = { | |
9287 | { gen_helper_neon_add_u8, gen_helper_neon_sub_u8 }, | |
9288 | { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 }, | |
9289 | { tcg_gen_add_i32, tcg_gen_sub_i32 }, | |
9290 | }; | |
9291 | bool is_sub = (opcode == 0x12 && u); /* MLS */ | |
9292 | ||
9293 | genfn = fns[size][is_sub]; | |
9294 | read_vec_element_i32(s, tcg_op1, rd, pass, MO_32); | |
d108609b | 9295 | genfn(tcg_res, tcg_op1, tcg_res); |
8b12a0cf PM |
9296 | } |
9297 | ||
1f8a73af PM |
9298 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); |
9299 | ||
9300 | tcg_temp_free_i32(tcg_res); | |
9301 | tcg_temp_free_i32(tcg_op1); | |
9302 | tcg_temp_free_i32(tcg_op2); | |
9303 | } | |
9304 | } | |
9305 | ||
9306 | if (!is_q) { | |
9307 | clear_vec_high(s, rd); | |
9308 | } | |
e1cea114 PM |
9309 | } |
9310 | ||
384b26fb AB |
9311 | /* C3.6.16 AdvSIMD three same |
9312 | * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0 | |
9313 | * +---+---+---+-----------+------+---+------+--------+---+------+------+ | |
9314 | * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd | | |
9315 | * +---+---+---+-----------+------+---+------+--------+---+------+------+ | |
9316 | */ | |
9317 | static void disas_simd_three_reg_same(DisasContext *s, uint32_t insn) | |
9318 | { | |
e1cea114 PM |
9319 | int opcode = extract32(insn, 11, 5); |
9320 | ||
9321 | switch (opcode) { | |
9322 | case 0x3: /* logic ops */ | |
9323 | disas_simd_3same_logic(s, insn); | |
9324 | break; | |
9325 | case 0x17: /* ADDP */ | |
9326 | case 0x14: /* SMAXP, UMAXP */ | |
9327 | case 0x15: /* SMINP, UMINP */ | |
bc242f9b | 9328 | { |
e1cea114 | 9329 | /* Pairwise operations */ |
bc242f9b AB |
9330 | int is_q = extract32(insn, 30, 1); |
9331 | int u = extract32(insn, 29, 1); | |
9332 | int size = extract32(insn, 22, 2); | |
9333 | int rm = extract32(insn, 16, 5); | |
9334 | int rn = extract32(insn, 5, 5); | |
9335 | int rd = extract32(insn, 0, 5); | |
9336 | if (opcode == 0x17) { | |
9337 | if (u || (size == 3 && !is_q)) { | |
9338 | unallocated_encoding(s); | |
9339 | return; | |
9340 | } | |
9341 | } else { | |
9342 | if (size == 3) { | |
9343 | unallocated_encoding(s); | |
9344 | return; | |
9345 | } | |
9346 | } | |
9347 | handle_simd_3same_pair(s, is_q, u, opcode, size, rn, rm, rd); | |
e1cea114 | 9348 | break; |
bc242f9b | 9349 | } |
e1cea114 PM |
9350 | case 0x18 ... 0x31: |
9351 | /* floating point ops, sz[1] and U are part of opcode */ | |
9352 | disas_simd_3same_float(s, insn); | |
9353 | break; | |
9354 | default: | |
9355 | disas_simd_3same_int(s, insn); | |
9356 | break; | |
9357 | } | |
384b26fb AB |
9358 | } |
9359 | ||
931c8cc2 PM |
9360 | static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q, |
9361 | int size, int rn, int rd) | |
9362 | { | |
9363 | /* Handle 2-reg-misc ops which are widening (so each size element | |
9364 | * in the source becomes a 2*size element in the destination. | |
9365 | * The only instruction like this is FCVTL. | |
9366 | */ | |
9367 | int pass; | |
9368 | ||
9369 | if (size == 3) { | |
9370 | /* 32 -> 64 bit fp conversion */ | |
9371 | TCGv_i64 tcg_res[2]; | |
9372 | int srcelt = is_q ? 2 : 0; | |
9373 | ||
9374 | for (pass = 0; pass < 2; pass++) { | |
9375 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
9376 | tcg_res[pass] = tcg_temp_new_i64(); | |
9377 | ||
9378 | read_vec_element_i32(s, tcg_op, rn, srcelt + pass, MO_32); | |
9379 | gen_helper_vfp_fcvtds(tcg_res[pass], tcg_op, cpu_env); | |
9380 | tcg_temp_free_i32(tcg_op); | |
9381 | } | |
9382 | for (pass = 0; pass < 2; pass++) { | |
9383 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
9384 | tcg_temp_free_i64(tcg_res[pass]); | |
9385 | } | |
9386 | } else { | |
9387 | /* 16 -> 32 bit fp conversion */ | |
9388 | int srcelt = is_q ? 4 : 0; | |
9389 | TCGv_i32 tcg_res[4]; | |
9390 | ||
9391 | for (pass = 0; pass < 4; pass++) { | |
9392 | tcg_res[pass] = tcg_temp_new_i32(); | |
9393 | ||
9394 | read_vec_element_i32(s, tcg_res[pass], rn, srcelt + pass, MO_16); | |
9395 | gen_helper_vfp_fcvt_f16_to_f32(tcg_res[pass], tcg_res[pass], | |
9396 | cpu_env); | |
9397 | } | |
9398 | for (pass = 0; pass < 4; pass++) { | |
9399 | write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32); | |
9400 | tcg_temp_free_i32(tcg_res[pass]); | |
9401 | } | |
9402 | } | |
9403 | } | |
9404 | ||
39d82118 AB |
9405 | static void handle_rev(DisasContext *s, int opcode, bool u, |
9406 | bool is_q, int size, int rn, int rd) | |
9407 | { | |
9408 | int op = (opcode << 1) | u; | |
9409 | int opsz = op + size; | |
9410 | int grp_size = 3 - opsz; | |
9411 | int dsize = is_q ? 128 : 64; | |
9412 | int i; | |
9413 | ||
9414 | if (opsz >= 3) { | |
9415 | unallocated_encoding(s); | |
9416 | return; | |
9417 | } | |
9418 | ||
8c6afa6a PM |
9419 | if (!fp_access_check(s)) { |
9420 | return; | |
9421 | } | |
9422 | ||
39d82118 AB |
9423 | if (size == 0) { |
9424 | /* Special case bytes, use bswap op on each group of elements */ | |
9425 | int groups = dsize / (8 << grp_size); | |
9426 | ||
9427 | for (i = 0; i < groups; i++) { | |
9428 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
9429 | ||
9430 | read_vec_element(s, tcg_tmp, rn, i, grp_size); | |
9431 | switch (grp_size) { | |
9432 | case MO_16: | |
9433 | tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp); | |
9434 | break; | |
9435 | case MO_32: | |
9436 | tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp); | |
9437 | break; | |
9438 | case MO_64: | |
9439 | tcg_gen_bswap64_i64(tcg_tmp, tcg_tmp); | |
9440 | break; | |
9441 | default: | |
9442 | g_assert_not_reached(); | |
9443 | } | |
9444 | write_vec_element(s, tcg_tmp, rd, i, grp_size); | |
9445 | tcg_temp_free_i64(tcg_tmp); | |
9446 | } | |
9447 | if (!is_q) { | |
9448 | clear_vec_high(s, rd); | |
9449 | } | |
9450 | } else { | |
9451 | int revmask = (1 << grp_size) - 1; | |
9452 | int esize = 8 << size; | |
9453 | int elements = dsize / esize; | |
9454 | TCGv_i64 tcg_rn = tcg_temp_new_i64(); | |
9455 | TCGv_i64 tcg_rd = tcg_const_i64(0); | |
9456 | TCGv_i64 tcg_rd_hi = tcg_const_i64(0); | |
9457 | ||
9458 | for (i = 0; i < elements; i++) { | |
9459 | int e_rev = (i & 0xf) ^ revmask; | |
9460 | int off = e_rev * esize; | |
9461 | read_vec_element(s, tcg_rn, rn, i, size); | |
9462 | if (off >= 64) { | |
9463 | tcg_gen_deposit_i64(tcg_rd_hi, tcg_rd_hi, | |
9464 | tcg_rn, off - 64, esize); | |
9465 | } else { | |
9466 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, off, esize); | |
9467 | } | |
9468 | } | |
9469 | write_vec_element(s, tcg_rd, rd, 0, MO_64); | |
9470 | write_vec_element(s, tcg_rd_hi, rd, 1, MO_64); | |
9471 | ||
9472 | tcg_temp_free_i64(tcg_rd_hi); | |
9473 | tcg_temp_free_i64(tcg_rd); | |
9474 | tcg_temp_free_i64(tcg_rn); | |
9475 | } | |
9476 | } | |
9477 | ||
6781fa11 PM |
9478 | static void handle_2misc_pairwise(DisasContext *s, int opcode, bool u, |
9479 | bool is_q, int size, int rn, int rd) | |
9480 | { | |
9481 | /* Implement the pairwise operations from 2-misc: | |
9482 | * SADDLP, UADDLP, SADALP, UADALP. | |
9483 | * These all add pairs of elements in the input to produce a | |
9484 | * double-width result element in the output (possibly accumulating). | |
9485 | */ | |
9486 | bool accum = (opcode == 0x6); | |
9487 | int maxpass = is_q ? 2 : 1; | |
9488 | int pass; | |
9489 | TCGv_i64 tcg_res[2]; | |
9490 | ||
9491 | if (size == 2) { | |
9492 | /* 32 + 32 -> 64 op */ | |
9493 | TCGMemOp memop = size + (u ? 0 : MO_SIGN); | |
9494 | ||
9495 | for (pass = 0; pass < maxpass; pass++) { | |
9496 | TCGv_i64 tcg_op1 = tcg_temp_new_i64(); | |
9497 | TCGv_i64 tcg_op2 = tcg_temp_new_i64(); | |
9498 | ||
9499 | tcg_res[pass] = tcg_temp_new_i64(); | |
9500 | ||
9501 | read_vec_element(s, tcg_op1, rn, pass * 2, memop); | |
9502 | read_vec_element(s, tcg_op2, rn, pass * 2 + 1, memop); | |
9503 | tcg_gen_add_i64(tcg_res[pass], tcg_op1, tcg_op2); | |
9504 | if (accum) { | |
9505 | read_vec_element(s, tcg_op1, rd, pass, MO_64); | |
9506 | tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_op1); | |
9507 | } | |
9508 | ||
9509 | tcg_temp_free_i64(tcg_op1); | |
9510 | tcg_temp_free_i64(tcg_op2); | |
9511 | } | |
9512 | } else { | |
9513 | for (pass = 0; pass < maxpass; pass++) { | |
9514 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | |
9515 | NeonGenOneOpFn *genfn; | |
9516 | static NeonGenOneOpFn * const fns[2][2] = { | |
9517 | { gen_helper_neon_addlp_s8, gen_helper_neon_addlp_u8 }, | |
9518 | { gen_helper_neon_addlp_s16, gen_helper_neon_addlp_u16 }, | |
9519 | }; | |
9520 | ||
9521 | genfn = fns[size][u]; | |
9522 | ||
9523 | tcg_res[pass] = tcg_temp_new_i64(); | |
9524 | ||
9525 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
9526 | genfn(tcg_res[pass], tcg_op); | |
9527 | ||
9528 | if (accum) { | |
9529 | read_vec_element(s, tcg_op, rd, pass, MO_64); | |
9530 | if (size == 0) { | |
9531 | gen_helper_neon_addl_u16(tcg_res[pass], | |
9532 | tcg_res[pass], tcg_op); | |
9533 | } else { | |
9534 | gen_helper_neon_addl_u32(tcg_res[pass], | |
9535 | tcg_res[pass], tcg_op); | |
9536 | } | |
9537 | } | |
9538 | tcg_temp_free_i64(tcg_op); | |
9539 | } | |
9540 | } | |
9541 | if (!is_q) { | |
9542 | tcg_res[1] = tcg_const_i64(0); | |
9543 | } | |
9544 | for (pass = 0; pass < 2; pass++) { | |
9545 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
9546 | tcg_temp_free_i64(tcg_res[pass]); | |
9547 | } | |
9548 | } | |
9549 | ||
73a81d10 PM |
9550 | static void handle_shll(DisasContext *s, bool is_q, int size, int rn, int rd) |
9551 | { | |
9552 | /* Implement SHLL and SHLL2 */ | |
9553 | int pass; | |
9554 | int part = is_q ? 2 : 0; | |
9555 | TCGv_i64 tcg_res[2]; | |
9556 | ||
9557 | for (pass = 0; pass < 2; pass++) { | |
9558 | static NeonGenWidenFn * const widenfns[3] = { | |
9559 | gen_helper_neon_widen_u8, | |
9560 | gen_helper_neon_widen_u16, | |
9561 | tcg_gen_extu_i32_i64, | |
9562 | }; | |
9563 | NeonGenWidenFn *widenfn = widenfns[size]; | |
9564 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
9565 | ||
9566 | read_vec_element_i32(s, tcg_op, rn, part + pass, MO_32); | |
9567 | tcg_res[pass] = tcg_temp_new_i64(); | |
9568 | widenfn(tcg_res[pass], tcg_op); | |
9569 | tcg_gen_shli_i64(tcg_res[pass], tcg_res[pass], 8 << size); | |
9570 | ||
9571 | tcg_temp_free_i32(tcg_op); | |
9572 | } | |
9573 | ||
9574 | for (pass = 0; pass < 2; pass++) { | |
9575 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
9576 | tcg_temp_free_i64(tcg_res[pass]); | |
9577 | } | |
9578 | } | |
9579 | ||
384b26fb AB |
9580 | /* C3.6.17 AdvSIMD two reg misc |
9581 | * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 | |
9582 | * +---+---+---+-----------+------+-----------+--------+-----+------+------+ | |
9583 | * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd | | |
9584 | * +---+---+---+-----------+------+-----------+--------+-----+------+------+ | |
9585 | */ | |
9586 | static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) | |
9587 | { | |
45aecc6d PM |
9588 | int size = extract32(insn, 22, 2); |
9589 | int opcode = extract32(insn, 12, 5); | |
9590 | bool u = extract32(insn, 29, 1); | |
9591 | bool is_q = extract32(insn, 30, 1); | |
94b6c911 PM |
9592 | int rn = extract32(insn, 5, 5); |
9593 | int rd = extract32(insn, 0, 5); | |
04c7c6c2 PM |
9594 | bool need_fpstatus = false; |
9595 | bool need_rmode = false; | |
9596 | int rmode = -1; | |
9597 | TCGv_i32 tcg_rmode; | |
9598 | TCGv_ptr tcg_fpstatus; | |
45aecc6d PM |
9599 | |
9600 | switch (opcode) { | |
9601 | case 0x0: /* REV64, REV32 */ | |
9602 | case 0x1: /* REV16 */ | |
39d82118 | 9603 | handle_rev(s, opcode, u, is_q, size, rn, rd); |
45aecc6d | 9604 | return; |
86cbc418 PM |
9605 | case 0x5: /* CNT, NOT, RBIT */ |
9606 | if (u && size == 0) { | |
9607 | /* NOT: adjust size so we can use the 64-bits-at-a-time loop. */ | |
9608 | size = 3; | |
9609 | break; | |
9610 | } else if (u && size == 1) { | |
9611 | /* RBIT */ | |
9612 | break; | |
9613 | } else if (!u && size == 0) { | |
9614 | /* CNT */ | |
9615 | break; | |
45aecc6d | 9616 | } |
86cbc418 | 9617 | unallocated_encoding(s); |
45aecc6d | 9618 | return; |
d980fd59 PM |
9619 | case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */ |
9620 | case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */ | |
9621 | if (size == 3) { | |
9622 | unallocated_encoding(s); | |
9623 | return; | |
9624 | } | |
8c6afa6a PM |
9625 | if (!fp_access_check(s)) { |
9626 | return; | |
9627 | } | |
9628 | ||
5201c136 | 9629 | handle_2misc_narrow(s, false, opcode, u, is_q, size, rn, rd); |
d980fd59 | 9630 | return; |
45aecc6d | 9631 | case 0x4: /* CLS, CLZ */ |
b05c3068 AB |
9632 | if (size == 3) { |
9633 | unallocated_encoding(s); | |
9634 | return; | |
9635 | } | |
9636 | break; | |
9637 | case 0x2: /* SADDLP, UADDLP */ | |
45aecc6d | 9638 | case 0x6: /* SADALP, UADALP */ |
45aecc6d PM |
9639 | if (size == 3) { |
9640 | unallocated_encoding(s); | |
9641 | return; | |
9642 | } | |
8c6afa6a PM |
9643 | if (!fp_access_check(s)) { |
9644 | return; | |
9645 | } | |
6781fa11 | 9646 | handle_2misc_pairwise(s, opcode, u, is_q, size, rn, rd); |
45aecc6d PM |
9647 | return; |
9648 | case 0x13: /* SHLL, SHLL2 */ | |
9649 | if (u == 0 || size == 3) { | |
9650 | unallocated_encoding(s); | |
9651 | return; | |
9652 | } | |
8c6afa6a PM |
9653 | if (!fp_access_check(s)) { |
9654 | return; | |
9655 | } | |
73a81d10 | 9656 | handle_shll(s, is_q, size, rn, rd); |
45aecc6d PM |
9657 | return; |
9658 | case 0xa: /* CMLT */ | |
9659 | if (u == 1) { | |
9660 | unallocated_encoding(s); | |
9661 | return; | |
9662 | } | |
9663 | /* fall through */ | |
45aecc6d PM |
9664 | case 0x8: /* CMGT, CMGE */ |
9665 | case 0x9: /* CMEQ, CMLE */ | |
9666 | case 0xb: /* ABS, NEG */ | |
94b6c911 PM |
9667 | if (size == 3 && !is_q) { |
9668 | unallocated_encoding(s); | |
9669 | return; | |
9670 | } | |
9671 | break; | |
9672 | case 0x3: /* SUQADD, USQADD */ | |
09e03735 AB |
9673 | if (size == 3 && !is_q) { |
9674 | unallocated_encoding(s); | |
9675 | return; | |
9676 | } | |
8c6afa6a PM |
9677 | if (!fp_access_check(s)) { |
9678 | return; | |
9679 | } | |
09e03735 AB |
9680 | handle_2misc_satacc(s, false, u, is_q, size, rn, rd); |
9681 | return; | |
94b6c911 | 9682 | case 0x7: /* SQABS, SQNEG */ |
45aecc6d PM |
9683 | if (size == 3 && !is_q) { |
9684 | unallocated_encoding(s); | |
9685 | return; | |
9686 | } | |
0a79bc87 | 9687 | break; |
45aecc6d PM |
9688 | case 0xc ... 0xf: |
9689 | case 0x16 ... 0x1d: | |
9690 | case 0x1f: | |
9691 | { | |
9692 | /* Floating point: U, size[1] and opcode indicate operation; | |
9693 | * size[0] indicates single or double precision. | |
9694 | */ | |
10113b69 | 9695 | int is_double = extract32(size, 0, 1); |
45aecc6d | 9696 | opcode |= (extract32(size, 1, 1) << 5) | (u << 6); |
10113b69 | 9697 | size = is_double ? 3 : 2; |
45aecc6d | 9698 | switch (opcode) { |
f93d0138 PM |
9699 | case 0x2f: /* FABS */ |
9700 | case 0x6f: /* FNEG */ | |
9701 | if (size == 3 && !is_q) { | |
9702 | unallocated_encoding(s); | |
9703 | return; | |
9704 | } | |
9705 | break; | |
10113b69 AB |
9706 | case 0x1d: /* SCVTF */ |
9707 | case 0x5d: /* UCVTF */ | |
9708 | { | |
9709 | bool is_signed = (opcode == 0x1d) ? true : false; | |
9710 | int elements = is_double ? 2 : is_q ? 4 : 2; | |
9711 | if (is_double && !is_q) { | |
9712 | unallocated_encoding(s); | |
9713 | return; | |
9714 | } | |
8c6afa6a PM |
9715 | if (!fp_access_check(s)) { |
9716 | return; | |
9717 | } | |
10113b69 AB |
9718 | handle_simd_intfp_conv(s, rd, rn, elements, is_signed, 0, size); |
9719 | return; | |
9720 | } | |
8908f4d1 AB |
9721 | case 0x2c: /* FCMGT (zero) */ |
9722 | case 0x2d: /* FCMEQ (zero) */ | |
9723 | case 0x2e: /* FCMLT (zero) */ | |
9724 | case 0x6c: /* FCMGE (zero) */ | |
9725 | case 0x6d: /* FCMLE (zero) */ | |
9726 | if (size == 3 && !is_q) { | |
9727 | unallocated_encoding(s); | |
9728 | return; | |
9729 | } | |
9730 | handle_2misc_fcmp_zero(s, opcode, false, u, is_q, size, rn, rd); | |
9731 | return; | |
f612537e AB |
9732 | case 0x7f: /* FSQRT */ |
9733 | if (size == 3 && !is_q) { | |
9734 | unallocated_encoding(s); | |
9735 | return; | |
9736 | } | |
9737 | break; | |
04c7c6c2 PM |
9738 | case 0x1a: /* FCVTNS */ |
9739 | case 0x1b: /* FCVTMS */ | |
9740 | case 0x3a: /* FCVTPS */ | |
9741 | case 0x3b: /* FCVTZS */ | |
9742 | case 0x5a: /* FCVTNU */ | |
9743 | case 0x5b: /* FCVTMU */ | |
9744 | case 0x7a: /* FCVTPU */ | |
9745 | case 0x7b: /* FCVTZU */ | |
9746 | need_fpstatus = true; | |
9747 | need_rmode = true; | |
9748 | rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1); | |
9749 | if (size == 3 && !is_q) { | |
9750 | unallocated_encoding(s); | |
9751 | return; | |
9752 | } | |
9753 | break; | |
9754 | case 0x5c: /* FCVTAU */ | |
9755 | case 0x1c: /* FCVTAS */ | |
9756 | need_fpstatus = true; | |
9757 | need_rmode = true; | |
9758 | rmode = FPROUNDING_TIEAWAY; | |
9759 | if (size == 3 && !is_q) { | |
9760 | unallocated_encoding(s); | |
9761 | return; | |
9762 | } | |
9763 | break; | |
b6d4443a AB |
9764 | case 0x3c: /* URECPE */ |
9765 | if (size == 3) { | |
9766 | unallocated_encoding(s); | |
9767 | return; | |
9768 | } | |
9769 | /* fall through */ | |
9770 | case 0x3d: /* FRECPE */ | |
c2fb418e AB |
9771 | case 0x7d: /* FRSQRTE */ |
9772 | if (size == 3 && !is_q) { | |
9773 | unallocated_encoding(s); | |
9774 | return; | |
9775 | } | |
8c6afa6a PM |
9776 | if (!fp_access_check(s)) { |
9777 | return; | |
9778 | } | |
b6d4443a AB |
9779 | handle_2misc_reciprocal(s, opcode, false, u, is_q, size, rn, rd); |
9780 | return; | |
5553955e PM |
9781 | case 0x56: /* FCVTXN, FCVTXN2 */ |
9782 | if (size == 2) { | |
9783 | unallocated_encoding(s); | |
9784 | return; | |
9785 | } | |
9786 | /* fall through */ | |
45aecc6d | 9787 | case 0x16: /* FCVTN, FCVTN2 */ |
261a5b4d PM |
9788 | /* handle_2misc_narrow does a 2*size -> size operation, but these |
9789 | * instructions encode the source size rather than dest size. | |
9790 | */ | |
8c6afa6a PM |
9791 | if (!fp_access_check(s)) { |
9792 | return; | |
9793 | } | |
5201c136 | 9794 | handle_2misc_narrow(s, false, opcode, 0, is_q, size - 1, rn, rd); |
261a5b4d | 9795 | return; |
45aecc6d | 9796 | case 0x17: /* FCVTL, FCVTL2 */ |
8c6afa6a PM |
9797 | if (!fp_access_check(s)) { |
9798 | return; | |
9799 | } | |
931c8cc2 PM |
9800 | handle_2misc_widening(s, opcode, is_q, size, rn, rd); |
9801 | return; | |
45aecc6d PM |
9802 | case 0x18: /* FRINTN */ |
9803 | case 0x19: /* FRINTM */ | |
45aecc6d PM |
9804 | case 0x38: /* FRINTP */ |
9805 | case 0x39: /* FRINTZ */ | |
03df01ed PM |
9806 | need_rmode = true; |
9807 | rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1); | |
9808 | /* fall through */ | |
9809 | case 0x59: /* FRINTX */ | |
9810 | case 0x79: /* FRINTI */ | |
9811 | need_fpstatus = true; | |
9812 | if (size == 3 && !is_q) { | |
9813 | unallocated_encoding(s); | |
9814 | return; | |
9815 | } | |
9816 | break; | |
9817 | case 0x58: /* FRINTA */ | |
9818 | need_rmode = true; | |
9819 | rmode = FPROUNDING_TIEAWAY; | |
9820 | need_fpstatus = true; | |
9821 | if (size == 3 && !is_q) { | |
9822 | unallocated_encoding(s); | |
9823 | return; | |
9824 | } | |
9825 | break; | |
45aecc6d | 9826 | case 0x7c: /* URSQRTE */ |
c2fb418e AB |
9827 | if (size == 3) { |
9828 | unallocated_encoding(s); | |
9829 | return; | |
9830 | } | |
9831 | need_fpstatus = true; | |
9832 | break; | |
45aecc6d PM |
9833 | default: |
9834 | unallocated_encoding(s); | |
9835 | return; | |
9836 | } | |
9837 | break; | |
9838 | } | |
9839 | default: | |
9840 | unallocated_encoding(s); | |
9841 | return; | |
9842 | } | |
94b6c911 | 9843 | |
8c6afa6a PM |
9844 | if (!fp_access_check(s)) { |
9845 | return; | |
9846 | } | |
9847 | ||
04c7c6c2 PM |
9848 | if (need_fpstatus) { |
9849 | tcg_fpstatus = get_fpstatus_ptr(); | |
9850 | } else { | |
9851 | TCGV_UNUSED_PTR(tcg_fpstatus); | |
9852 | } | |
9853 | if (need_rmode) { | |
9854 | tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); | |
9855 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); | |
9856 | } else { | |
9857 | TCGV_UNUSED_I32(tcg_rmode); | |
9858 | } | |
9859 | ||
94b6c911 PM |
9860 | if (size == 3) { |
9861 | /* All 64-bit element operations can be shared with scalar 2misc */ | |
9862 | int pass; | |
9863 | ||
9864 | for (pass = 0; pass < (is_q ? 2 : 1); pass++) { | |
9865 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | |
9866 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
9867 | ||
9868 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
9869 | ||
04c7c6c2 PM |
9870 | handle_2misc_64(s, opcode, u, tcg_res, tcg_op, |
9871 | tcg_rmode, tcg_fpstatus); | |
94b6c911 PM |
9872 | |
9873 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
9874 | ||
9875 | tcg_temp_free_i64(tcg_res); | |
9876 | tcg_temp_free_i64(tcg_op); | |
9877 | } | |
9878 | } else { | |
9879 | int pass; | |
9880 | ||
9881 | for (pass = 0; pass < (is_q ? 4 : 2); pass++) { | |
9882 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | |
9883 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
9884 | TCGCond cond; | |
9885 | ||
9886 | read_vec_element_i32(s, tcg_op, rn, pass, MO_32); | |
9887 | ||
9888 | if (size == 2) { | |
9889 | /* Special cases for 32 bit elements */ | |
9890 | switch (opcode) { | |
9891 | case 0xa: /* CMLT */ | |
9892 | /* 32 bit integer comparison against zero, result is | |
9893 | * test ? (2^32 - 1) : 0. We implement via setcond(test) | |
9894 | * and inverting. | |
9895 | */ | |
9896 | cond = TCG_COND_LT; | |
9897 | do_cmop: | |
9898 | tcg_gen_setcondi_i32(cond, tcg_res, tcg_op, 0); | |
9899 | tcg_gen_neg_i32(tcg_res, tcg_res); | |
9900 | break; | |
9901 | case 0x8: /* CMGT, CMGE */ | |
9902 | cond = u ? TCG_COND_GE : TCG_COND_GT; | |
9903 | goto do_cmop; | |
9904 | case 0x9: /* CMEQ, CMLE */ | |
9905 | cond = u ? TCG_COND_LE : TCG_COND_EQ; | |
9906 | goto do_cmop; | |
b05c3068 AB |
9907 | case 0x4: /* CLS */ |
9908 | if (u) { | |
9909 | gen_helper_clz32(tcg_res, tcg_op); | |
9910 | } else { | |
9911 | gen_helper_cls32(tcg_res, tcg_op); | |
9912 | } | |
9913 | break; | |
0a79bc87 AB |
9914 | case 0x7: /* SQABS, SQNEG */ |
9915 | if (u) { | |
9916 | gen_helper_neon_qneg_s32(tcg_res, cpu_env, tcg_op); | |
9917 | } else { | |
9918 | gen_helper_neon_qabs_s32(tcg_res, cpu_env, tcg_op); | |
9919 | } | |
9920 | break; | |
94b6c911 PM |
9921 | case 0xb: /* ABS, NEG */ |
9922 | if (u) { | |
9923 | tcg_gen_neg_i32(tcg_res, tcg_op); | |
9924 | } else { | |
9925 | TCGv_i32 tcg_zero = tcg_const_i32(0); | |
9926 | tcg_gen_neg_i32(tcg_res, tcg_op); | |
9927 | tcg_gen_movcond_i32(TCG_COND_GT, tcg_res, tcg_op, | |
9928 | tcg_zero, tcg_op, tcg_res); | |
9929 | tcg_temp_free_i32(tcg_zero); | |
9930 | } | |
9931 | break; | |
f93d0138 PM |
9932 | case 0x2f: /* FABS */ |
9933 | gen_helper_vfp_abss(tcg_res, tcg_op); | |
9934 | break; | |
9935 | case 0x6f: /* FNEG */ | |
9936 | gen_helper_vfp_negs(tcg_res, tcg_op); | |
9937 | break; | |
f612537e AB |
9938 | case 0x7f: /* FSQRT */ |
9939 | gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env); | |
9940 | break; | |
04c7c6c2 PM |
9941 | case 0x1a: /* FCVTNS */ |
9942 | case 0x1b: /* FCVTMS */ | |
9943 | case 0x1c: /* FCVTAS */ | |
9944 | case 0x3a: /* FCVTPS */ | |
9945 | case 0x3b: /* FCVTZS */ | |
9946 | { | |
9947 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
9948 | gen_helper_vfp_tosls(tcg_res, tcg_op, | |
9949 | tcg_shift, tcg_fpstatus); | |
9950 | tcg_temp_free_i32(tcg_shift); | |
9951 | break; | |
9952 | } | |
9953 | case 0x5a: /* FCVTNU */ | |
9954 | case 0x5b: /* FCVTMU */ | |
9955 | case 0x5c: /* FCVTAU */ | |
9956 | case 0x7a: /* FCVTPU */ | |
9957 | case 0x7b: /* FCVTZU */ | |
9958 | { | |
9959 | TCGv_i32 tcg_shift = tcg_const_i32(0); | |
9960 | gen_helper_vfp_touls(tcg_res, tcg_op, | |
9961 | tcg_shift, tcg_fpstatus); | |
9962 | tcg_temp_free_i32(tcg_shift); | |
9963 | break; | |
9964 | } | |
03df01ed PM |
9965 | case 0x18: /* FRINTN */ |
9966 | case 0x19: /* FRINTM */ | |
9967 | case 0x38: /* FRINTP */ | |
9968 | case 0x39: /* FRINTZ */ | |
9969 | case 0x58: /* FRINTA */ | |
9970 | case 0x79: /* FRINTI */ | |
9971 | gen_helper_rints(tcg_res, tcg_op, tcg_fpstatus); | |
9972 | break; | |
9973 | case 0x59: /* FRINTX */ | |
9974 | gen_helper_rints_exact(tcg_res, tcg_op, tcg_fpstatus); | |
9975 | break; | |
c2fb418e AB |
9976 | case 0x7c: /* URSQRTE */ |
9977 | gen_helper_rsqrte_u32(tcg_res, tcg_op, tcg_fpstatus); | |
9978 | break; | |
94b6c911 PM |
9979 | default: |
9980 | g_assert_not_reached(); | |
9981 | } | |
9982 | } else { | |
9983 | /* Use helpers for 8 and 16 bit elements */ | |
9984 | switch (opcode) { | |
86cbc418 PM |
9985 | case 0x5: /* CNT, RBIT */ |
9986 | /* For these two insns size is part of the opcode specifier | |
9987 | * (handled earlier); they always operate on byte elements. | |
9988 | */ | |
9989 | if (u) { | |
9990 | gen_helper_neon_rbit_u8(tcg_res, tcg_op); | |
9991 | } else { | |
9992 | gen_helper_neon_cnt_u8(tcg_res, tcg_op); | |
9993 | } | |
9994 | break; | |
0a79bc87 AB |
9995 | case 0x7: /* SQABS, SQNEG */ |
9996 | { | |
9997 | NeonGenOneOpEnvFn *genfn; | |
9998 | static NeonGenOneOpEnvFn * const fns[2][2] = { | |
9999 | { gen_helper_neon_qabs_s8, gen_helper_neon_qneg_s8 }, | |
10000 | { gen_helper_neon_qabs_s16, gen_helper_neon_qneg_s16 }, | |
10001 | }; | |
10002 | genfn = fns[size][u]; | |
10003 | genfn(tcg_res, cpu_env, tcg_op); | |
10004 | break; | |
10005 | } | |
94b6c911 PM |
10006 | case 0x8: /* CMGT, CMGE */ |
10007 | case 0x9: /* CMEQ, CMLE */ | |
10008 | case 0xa: /* CMLT */ | |
10009 | { | |
10010 | static NeonGenTwoOpFn * const fns[3][2] = { | |
10011 | { gen_helper_neon_cgt_s8, gen_helper_neon_cgt_s16 }, | |
10012 | { gen_helper_neon_cge_s8, gen_helper_neon_cge_s16 }, | |
10013 | { gen_helper_neon_ceq_u8, gen_helper_neon_ceq_u16 }, | |
10014 | }; | |
10015 | NeonGenTwoOpFn *genfn; | |
10016 | int comp; | |
10017 | bool reverse; | |
10018 | TCGv_i32 tcg_zero = tcg_const_i32(0); | |
10019 | ||
10020 | /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */ | |
10021 | comp = (opcode - 0x8) * 2 + u; | |
10022 | /* ...but LE, LT are implemented as reverse GE, GT */ | |
10023 | reverse = (comp > 2); | |
10024 | if (reverse) { | |
10025 | comp = 4 - comp; | |
10026 | } | |
10027 | genfn = fns[comp][size]; | |
10028 | if (reverse) { | |
10029 | genfn(tcg_res, tcg_zero, tcg_op); | |
10030 | } else { | |
10031 | genfn(tcg_res, tcg_op, tcg_zero); | |
10032 | } | |
10033 | tcg_temp_free_i32(tcg_zero); | |
10034 | break; | |
10035 | } | |
10036 | case 0xb: /* ABS, NEG */ | |
10037 | if (u) { | |
10038 | TCGv_i32 tcg_zero = tcg_const_i32(0); | |
10039 | if (size) { | |
10040 | gen_helper_neon_sub_u16(tcg_res, tcg_zero, tcg_op); | |
10041 | } else { | |
10042 | gen_helper_neon_sub_u8(tcg_res, tcg_zero, tcg_op); | |
10043 | } | |
10044 | tcg_temp_free_i32(tcg_zero); | |
10045 | } else { | |
10046 | if (size) { | |
10047 | gen_helper_neon_abs_s16(tcg_res, tcg_op); | |
10048 | } else { | |
10049 | gen_helper_neon_abs_s8(tcg_res, tcg_op); | |
10050 | } | |
10051 | } | |
10052 | break; | |
b05c3068 AB |
10053 | case 0x4: /* CLS, CLZ */ |
10054 | if (u) { | |
10055 | if (size == 0) { | |
10056 | gen_helper_neon_clz_u8(tcg_res, tcg_op); | |
10057 | } else { | |
10058 | gen_helper_neon_clz_u16(tcg_res, tcg_op); | |
10059 | } | |
10060 | } else { | |
10061 | if (size == 0) { | |
10062 | gen_helper_neon_cls_s8(tcg_res, tcg_op); | |
10063 | } else { | |
10064 | gen_helper_neon_cls_s16(tcg_res, tcg_op); | |
10065 | } | |
10066 | } | |
10067 | break; | |
94b6c911 PM |
10068 | default: |
10069 | g_assert_not_reached(); | |
10070 | } | |
10071 | } | |
10072 | ||
10073 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
10074 | ||
10075 | tcg_temp_free_i32(tcg_res); | |
10076 | tcg_temp_free_i32(tcg_op); | |
10077 | } | |
10078 | } | |
10079 | if (!is_q) { | |
10080 | clear_vec_high(s, rd); | |
10081 | } | |
04c7c6c2 PM |
10082 | |
10083 | if (need_rmode) { | |
10084 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); | |
10085 | tcg_temp_free_i32(tcg_rmode); | |
10086 | } | |
10087 | if (need_fpstatus) { | |
10088 | tcg_temp_free_ptr(tcg_fpstatus); | |
10089 | } | |
384b26fb AB |
10090 | } |
10091 | ||
9f82e0ff PM |
10092 | /* C3.6.13 AdvSIMD scalar x indexed element |
10093 | * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0 | |
10094 | * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+ | |
10095 | * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd | | |
10096 | * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+ | |
10097 | * C3.6.18 AdvSIMD vector x indexed element | |
384b26fb AB |
10098 | * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0 |
10099 | * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+ | |
10100 | * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd | | |
10101 | * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+ | |
10102 | */ | |
9f82e0ff | 10103 | static void disas_simd_indexed(DisasContext *s, uint32_t insn) |
384b26fb | 10104 | { |
f5e51e7f PM |
10105 | /* This encoding has two kinds of instruction: |
10106 | * normal, where we perform elt x idxelt => elt for each | |
10107 | * element in the vector | |
10108 | * long, where we perform elt x idxelt and generate a result of | |
10109 | * double the width of the input element | |
10110 | * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs). | |
10111 | */ | |
9f82e0ff | 10112 | bool is_scalar = extract32(insn, 28, 1); |
f5e51e7f PM |
10113 | bool is_q = extract32(insn, 30, 1); |
10114 | bool u = extract32(insn, 29, 1); | |
10115 | int size = extract32(insn, 22, 2); | |
10116 | int l = extract32(insn, 21, 1); | |
10117 | int m = extract32(insn, 20, 1); | |
10118 | /* Note that the Rm field here is only 4 bits, not 5 as it usually is */ | |
10119 | int rm = extract32(insn, 16, 4); | |
10120 | int opcode = extract32(insn, 12, 4); | |
10121 | int h = extract32(insn, 11, 1); | |
10122 | int rn = extract32(insn, 5, 5); | |
10123 | int rd = extract32(insn, 0, 5); | |
10124 | bool is_long = false; | |
10125 | bool is_fp = false; | |
10126 | int index; | |
10127 | TCGv_ptr fpst; | |
10128 | ||
10129 | switch (opcode) { | |
10130 | case 0x0: /* MLA */ | |
10131 | case 0x4: /* MLS */ | |
9f82e0ff | 10132 | if (!u || is_scalar) { |
f5e51e7f PM |
10133 | unallocated_encoding(s); |
10134 | return; | |
10135 | } | |
10136 | break; | |
10137 | case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ | |
10138 | case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
10139 | case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */ | |
9f82e0ff PM |
10140 | if (is_scalar) { |
10141 | unallocated_encoding(s); | |
10142 | return; | |
10143 | } | |
f5e51e7f PM |
10144 | is_long = true; |
10145 | break; | |
10146 | case 0x3: /* SQDMLAL, SQDMLAL2 */ | |
10147 | case 0x7: /* SQDMLSL, SQDMLSL2 */ | |
10148 | case 0xb: /* SQDMULL, SQDMULL2 */ | |
10149 | is_long = true; | |
10150 | /* fall through */ | |
10151 | case 0xc: /* SQDMULH */ | |
10152 | case 0xd: /* SQRDMULH */ | |
f5e51e7f PM |
10153 | if (u) { |
10154 | unallocated_encoding(s); | |
10155 | return; | |
10156 | } | |
10157 | break; | |
9f82e0ff PM |
10158 | case 0x8: /* MUL */ |
10159 | if (u || is_scalar) { | |
10160 | unallocated_encoding(s); | |
10161 | return; | |
10162 | } | |
10163 | break; | |
f5e51e7f PM |
10164 | case 0x1: /* FMLA */ |
10165 | case 0x5: /* FMLS */ | |
10166 | if (u) { | |
10167 | unallocated_encoding(s); | |
10168 | return; | |
10169 | } | |
10170 | /* fall through */ | |
10171 | case 0x9: /* FMUL, FMULX */ | |
10172 | if (!extract32(size, 1, 1)) { | |
10173 | unallocated_encoding(s); | |
10174 | return; | |
10175 | } | |
10176 | is_fp = true; | |
10177 | break; | |
10178 | default: | |
10179 | unallocated_encoding(s); | |
10180 | return; | |
10181 | } | |
10182 | ||
10183 | if (is_fp) { | |
10184 | /* low bit of size indicates single/double */ | |
10185 | size = extract32(size, 0, 1) ? 3 : 2; | |
10186 | if (size == 2) { | |
10187 | index = h << 1 | l; | |
10188 | } else { | |
10189 | if (l || !is_q) { | |
10190 | unallocated_encoding(s); | |
10191 | return; | |
10192 | } | |
10193 | index = h; | |
10194 | } | |
10195 | rm |= (m << 4); | |
10196 | } else { | |
10197 | switch (size) { | |
10198 | case 1: | |
10199 | index = h << 2 | l << 1 | m; | |
10200 | break; | |
10201 | case 2: | |
10202 | index = h << 1 | l; | |
10203 | rm |= (m << 4); | |
10204 | break; | |
10205 | default: | |
10206 | unallocated_encoding(s); | |
10207 | return; | |
10208 | } | |
10209 | } | |
10210 | ||
8c6afa6a PM |
10211 | if (!fp_access_check(s)) { |
10212 | return; | |
10213 | } | |
10214 | ||
f5e51e7f PM |
10215 | if (is_fp) { |
10216 | fpst = get_fpstatus_ptr(); | |
10217 | } else { | |
10218 | TCGV_UNUSED_PTR(fpst); | |
10219 | } | |
10220 | ||
10221 | if (size == 3) { | |
10222 | TCGv_i64 tcg_idx = tcg_temp_new_i64(); | |
10223 | int pass; | |
10224 | ||
10225 | assert(is_fp && is_q && !is_long); | |
10226 | ||
10227 | read_vec_element(s, tcg_idx, rm, index, MO_64); | |
10228 | ||
9f82e0ff | 10229 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { |
f5e51e7f PM |
10230 | TCGv_i64 tcg_op = tcg_temp_new_i64(); |
10231 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | |
10232 | ||
10233 | read_vec_element(s, tcg_op, rn, pass, MO_64); | |
10234 | ||
10235 | switch (opcode) { | |
10236 | case 0x5: /* FMLS */ | |
10237 | /* As usual for ARM, separate negation for fused multiply-add */ | |
10238 | gen_helper_vfp_negd(tcg_op, tcg_op); | |
10239 | /* fall through */ | |
10240 | case 0x1: /* FMLA */ | |
10241 | read_vec_element(s, tcg_res, rd, pass, MO_64); | |
10242 | gen_helper_vfp_muladdd(tcg_res, tcg_op, tcg_idx, tcg_res, fpst); | |
10243 | break; | |
10244 | case 0x9: /* FMUL, FMULX */ | |
10245 | if (u) { | |
10246 | gen_helper_vfp_mulxd(tcg_res, tcg_op, tcg_idx, fpst); | |
10247 | } else { | |
10248 | gen_helper_vfp_muld(tcg_res, tcg_op, tcg_idx, fpst); | |
10249 | } | |
10250 | break; | |
10251 | default: | |
10252 | g_assert_not_reached(); | |
10253 | } | |
10254 | ||
10255 | write_vec_element(s, tcg_res, rd, pass, MO_64); | |
10256 | tcg_temp_free_i64(tcg_op); | |
10257 | tcg_temp_free_i64(tcg_res); | |
10258 | } | |
10259 | ||
9f82e0ff PM |
10260 | if (is_scalar) { |
10261 | clear_vec_high(s, rd); | |
10262 | } | |
10263 | ||
f5e51e7f PM |
10264 | tcg_temp_free_i64(tcg_idx); |
10265 | } else if (!is_long) { | |
9f82e0ff PM |
10266 | /* 32 bit floating point, or 16 or 32 bit integer. |
10267 | * For the 16 bit scalar case we use the usual Neon helpers and | |
10268 | * rely on the fact that 0 op 0 == 0 with no side effects. | |
10269 | */ | |
f5e51e7f | 10270 | TCGv_i32 tcg_idx = tcg_temp_new_i32(); |
9f82e0ff PM |
10271 | int pass, maxpasses; |
10272 | ||
10273 | if (is_scalar) { | |
10274 | maxpasses = 1; | |
10275 | } else { | |
10276 | maxpasses = is_q ? 4 : 2; | |
10277 | } | |
f5e51e7f PM |
10278 | |
10279 | read_vec_element_i32(s, tcg_idx, rm, index, size); | |
10280 | ||
9f82e0ff | 10281 | if (size == 1 && !is_scalar) { |
f5e51e7f PM |
10282 | /* The simplest way to handle the 16x16 indexed ops is to duplicate |
10283 | * the index into both halves of the 32 bit tcg_idx and then use | |
10284 | * the usual Neon helpers. | |
10285 | */ | |
10286 | tcg_gen_deposit_i32(tcg_idx, tcg_idx, tcg_idx, 16, 16); | |
10287 | } | |
10288 | ||
9f82e0ff | 10289 | for (pass = 0; pass < maxpasses; pass++) { |
f5e51e7f PM |
10290 | TCGv_i32 tcg_op = tcg_temp_new_i32(); |
10291 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | |
10292 | ||
9f82e0ff | 10293 | read_vec_element_i32(s, tcg_op, rn, pass, is_scalar ? size : MO_32); |
f5e51e7f PM |
10294 | |
10295 | switch (opcode) { | |
10296 | case 0x0: /* MLA */ | |
10297 | case 0x4: /* MLS */ | |
10298 | case 0x8: /* MUL */ | |
10299 | { | |
10300 | static NeonGenTwoOpFn * const fns[2][2] = { | |
10301 | { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 }, | |
10302 | { tcg_gen_add_i32, tcg_gen_sub_i32 }, | |
10303 | }; | |
10304 | NeonGenTwoOpFn *genfn; | |
10305 | bool is_sub = opcode == 0x4; | |
10306 | ||
10307 | if (size == 1) { | |
10308 | gen_helper_neon_mul_u16(tcg_res, tcg_op, tcg_idx); | |
10309 | } else { | |
10310 | tcg_gen_mul_i32(tcg_res, tcg_op, tcg_idx); | |
10311 | } | |
10312 | if (opcode == 0x8) { | |
10313 | break; | |
10314 | } | |
10315 | read_vec_element_i32(s, tcg_op, rd, pass, MO_32); | |
10316 | genfn = fns[size - 1][is_sub]; | |
10317 | genfn(tcg_res, tcg_op, tcg_res); | |
10318 | break; | |
10319 | } | |
10320 | case 0x5: /* FMLS */ | |
10321 | /* As usual for ARM, separate negation for fused multiply-add */ | |
10322 | gen_helper_vfp_negs(tcg_op, tcg_op); | |
10323 | /* fall through */ | |
10324 | case 0x1: /* FMLA */ | |
10325 | read_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
10326 | gen_helper_vfp_muladds(tcg_res, tcg_op, tcg_idx, tcg_res, fpst); | |
10327 | break; | |
10328 | case 0x9: /* FMUL, FMULX */ | |
10329 | if (u) { | |
10330 | gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst); | |
10331 | } else { | |
10332 | gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst); | |
10333 | } | |
10334 | break; | |
10335 | case 0xc: /* SQDMULH */ | |
10336 | if (size == 1) { | |
10337 | gen_helper_neon_qdmulh_s16(tcg_res, cpu_env, | |
10338 | tcg_op, tcg_idx); | |
10339 | } else { | |
10340 | gen_helper_neon_qdmulh_s32(tcg_res, cpu_env, | |
10341 | tcg_op, tcg_idx); | |
10342 | } | |
10343 | break; | |
10344 | case 0xd: /* SQRDMULH */ | |
10345 | if (size == 1) { | |
10346 | gen_helper_neon_qrdmulh_s16(tcg_res, cpu_env, | |
10347 | tcg_op, tcg_idx); | |
10348 | } else { | |
10349 | gen_helper_neon_qrdmulh_s32(tcg_res, cpu_env, | |
10350 | tcg_op, tcg_idx); | |
10351 | } | |
10352 | break; | |
10353 | default: | |
10354 | g_assert_not_reached(); | |
10355 | } | |
10356 | ||
9f82e0ff PM |
10357 | if (is_scalar) { |
10358 | write_fp_sreg(s, rd, tcg_res); | |
10359 | } else { | |
10360 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); | |
10361 | } | |
10362 | ||
f5e51e7f PM |
10363 | tcg_temp_free_i32(tcg_op); |
10364 | tcg_temp_free_i32(tcg_res); | |
10365 | } | |
10366 | ||
10367 | tcg_temp_free_i32(tcg_idx); | |
10368 | ||
10369 | if (!is_q) { | |
10370 | clear_vec_high(s, rd); | |
10371 | } | |
10372 | } else { | |
10373 | /* long ops: 16x16->32 or 32x32->64 */ | |
c44ad1fd PM |
10374 | TCGv_i64 tcg_res[2]; |
10375 | int pass; | |
10376 | bool satop = extract32(opcode, 0, 1); | |
10377 | TCGMemOp memop = MO_32; | |
10378 | ||
10379 | if (satop || !u) { | |
10380 | memop |= MO_SIGN; | |
10381 | } | |
10382 | ||
10383 | if (size == 2) { | |
10384 | TCGv_i64 tcg_idx = tcg_temp_new_i64(); | |
10385 | ||
10386 | read_vec_element(s, tcg_idx, rm, index, memop); | |
10387 | ||
9f82e0ff | 10388 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { |
c44ad1fd PM |
10389 | TCGv_i64 tcg_op = tcg_temp_new_i64(); |
10390 | TCGv_i64 tcg_passres; | |
9f82e0ff | 10391 | int passelt; |
c44ad1fd | 10392 | |
9f82e0ff PM |
10393 | if (is_scalar) { |
10394 | passelt = 0; | |
10395 | } else { | |
10396 | passelt = pass + (is_q * 2); | |
10397 | } | |
10398 | ||
10399 | read_vec_element(s, tcg_op, rn, passelt, memop); | |
c44ad1fd PM |
10400 | |
10401 | tcg_res[pass] = tcg_temp_new_i64(); | |
10402 | ||
10403 | if (opcode == 0xa || opcode == 0xb) { | |
10404 | /* Non-accumulating ops */ | |
10405 | tcg_passres = tcg_res[pass]; | |
10406 | } else { | |
10407 | tcg_passres = tcg_temp_new_i64(); | |
10408 | } | |
10409 | ||
10410 | tcg_gen_mul_i64(tcg_passres, tcg_op, tcg_idx); | |
10411 | tcg_temp_free_i64(tcg_op); | |
10412 | ||
10413 | if (satop) { | |
10414 | /* saturating, doubling */ | |
10415 | gen_helper_neon_addl_saturate_s64(tcg_passres, cpu_env, | |
10416 | tcg_passres, tcg_passres); | |
10417 | } | |
10418 | ||
10419 | if (opcode == 0xa || opcode == 0xb) { | |
10420 | continue; | |
10421 | } | |
10422 | ||
10423 | /* Accumulating op: handle accumulate step */ | |
10424 | read_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
10425 | ||
10426 | switch (opcode) { | |
10427 | case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ | |
10428 | tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_passres); | |
10429 | break; | |
10430 | case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
10431 | tcg_gen_sub_i64(tcg_res[pass], tcg_res[pass], tcg_passres); | |
10432 | break; | |
10433 | case 0x7: /* SQDMLSL, SQDMLSL2 */ | |
10434 | tcg_gen_neg_i64(tcg_passres, tcg_passres); | |
10435 | /* fall through */ | |
10436 | case 0x3: /* SQDMLAL, SQDMLAL2 */ | |
10437 | gen_helper_neon_addl_saturate_s64(tcg_res[pass], cpu_env, | |
10438 | tcg_res[pass], | |
10439 | tcg_passres); | |
10440 | break; | |
10441 | default: | |
10442 | g_assert_not_reached(); | |
10443 | } | |
10444 | tcg_temp_free_i64(tcg_passres); | |
10445 | } | |
10446 | tcg_temp_free_i64(tcg_idx); | |
9f82e0ff PM |
10447 | |
10448 | if (is_scalar) { | |
10449 | clear_vec_high(s, rd); | |
10450 | } | |
c44ad1fd PM |
10451 | } else { |
10452 | TCGv_i32 tcg_idx = tcg_temp_new_i32(); | |
10453 | ||
10454 | assert(size == 1); | |
10455 | read_vec_element_i32(s, tcg_idx, rm, index, size); | |
10456 | ||
9f82e0ff PM |
10457 | if (!is_scalar) { |
10458 | /* The simplest way to handle the 16x16 indexed ops is to | |
10459 | * duplicate the index into both halves of the 32 bit tcg_idx | |
10460 | * and then use the usual Neon helpers. | |
10461 | */ | |
10462 | tcg_gen_deposit_i32(tcg_idx, tcg_idx, tcg_idx, 16, 16); | |
10463 | } | |
c44ad1fd | 10464 | |
9f82e0ff | 10465 | for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) { |
c44ad1fd PM |
10466 | TCGv_i32 tcg_op = tcg_temp_new_i32(); |
10467 | TCGv_i64 tcg_passres; | |
10468 | ||
9f82e0ff PM |
10469 | if (is_scalar) { |
10470 | read_vec_element_i32(s, tcg_op, rn, pass, size); | |
10471 | } else { | |
10472 | read_vec_element_i32(s, tcg_op, rn, | |
10473 | pass + (is_q * 2), MO_32); | |
10474 | } | |
10475 | ||
c44ad1fd PM |
10476 | tcg_res[pass] = tcg_temp_new_i64(); |
10477 | ||
10478 | if (opcode == 0xa || opcode == 0xb) { | |
10479 | /* Non-accumulating ops */ | |
10480 | tcg_passres = tcg_res[pass]; | |
10481 | } else { | |
10482 | tcg_passres = tcg_temp_new_i64(); | |
10483 | } | |
10484 | ||
10485 | if (memop & MO_SIGN) { | |
10486 | gen_helper_neon_mull_s16(tcg_passres, tcg_op, tcg_idx); | |
10487 | } else { | |
10488 | gen_helper_neon_mull_u16(tcg_passres, tcg_op, tcg_idx); | |
10489 | } | |
10490 | if (satop) { | |
10491 | gen_helper_neon_addl_saturate_s32(tcg_passres, cpu_env, | |
10492 | tcg_passres, tcg_passres); | |
10493 | } | |
10494 | tcg_temp_free_i32(tcg_op); | |
10495 | ||
10496 | if (opcode == 0xa || opcode == 0xb) { | |
10497 | continue; | |
10498 | } | |
10499 | ||
10500 | /* Accumulating op: handle accumulate step */ | |
10501 | read_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
10502 | ||
10503 | switch (opcode) { | |
10504 | case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ | |
10505 | gen_helper_neon_addl_u32(tcg_res[pass], tcg_res[pass], | |
10506 | tcg_passres); | |
10507 | break; | |
10508 | case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ | |
10509 | gen_helper_neon_subl_u32(tcg_res[pass], tcg_res[pass], | |
10510 | tcg_passres); | |
10511 | break; | |
10512 | case 0x7: /* SQDMLSL, SQDMLSL2 */ | |
10513 | gen_helper_neon_negl_u32(tcg_passres, tcg_passres); | |
10514 | /* fall through */ | |
10515 | case 0x3: /* SQDMLAL, SQDMLAL2 */ | |
10516 | gen_helper_neon_addl_saturate_s32(tcg_res[pass], cpu_env, | |
10517 | tcg_res[pass], | |
10518 | tcg_passres); | |
10519 | break; | |
10520 | default: | |
10521 | g_assert_not_reached(); | |
10522 | } | |
10523 | tcg_temp_free_i64(tcg_passres); | |
10524 | } | |
10525 | tcg_temp_free_i32(tcg_idx); | |
9f82e0ff PM |
10526 | |
10527 | if (is_scalar) { | |
10528 | tcg_gen_ext32u_i64(tcg_res[0], tcg_res[0]); | |
10529 | } | |
10530 | } | |
10531 | ||
10532 | if (is_scalar) { | |
10533 | tcg_res[1] = tcg_const_i64(0); | |
c44ad1fd PM |
10534 | } |
10535 | ||
10536 | for (pass = 0; pass < 2; pass++) { | |
10537 | write_vec_element(s, tcg_res[pass], rd, pass, MO_64); | |
10538 | tcg_temp_free_i64(tcg_res[pass]); | |
10539 | } | |
f5e51e7f PM |
10540 | } |
10541 | ||
10542 | if (!TCGV_IS_UNUSED_PTR(fpst)) { | |
10543 | tcg_temp_free_ptr(fpst); | |
10544 | } | |
384b26fb AB |
10545 | } |
10546 | ||
10547 | /* C3.6.19 Crypto AES | |
10548 | * 31 24 23 22 21 17 16 12 11 10 9 5 4 0 | |
10549 | * +-----------------+------+-----------+--------+-----+------+------+ | |
10550 | * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd | | |
10551 | * +-----------------+------+-----------+--------+-----+------+------+ | |
10552 | */ | |
10553 | static void disas_crypto_aes(DisasContext *s, uint32_t insn) | |
10554 | { | |
5acc765c PM |
10555 | int size = extract32(insn, 22, 2); |
10556 | int opcode = extract32(insn, 12, 5); | |
10557 | int rn = extract32(insn, 5, 5); | |
10558 | int rd = extract32(insn, 0, 5); | |
10559 | int decrypt; | |
10560 | TCGv_i32 tcg_rd_regno, tcg_rn_regno, tcg_decrypt; | |
10561 | CryptoThreeOpEnvFn *genfn; | |
10562 | ||
10563 | if (!arm_dc_feature(s, ARM_FEATURE_V8_AES) | |
10564 | || size != 0) { | |
10565 | unallocated_encoding(s); | |
10566 | return; | |
10567 | } | |
10568 | ||
10569 | switch (opcode) { | |
10570 | case 0x4: /* AESE */ | |
10571 | decrypt = 0; | |
10572 | genfn = gen_helper_crypto_aese; | |
10573 | break; | |
10574 | case 0x6: /* AESMC */ | |
10575 | decrypt = 0; | |
10576 | genfn = gen_helper_crypto_aesmc; | |
10577 | break; | |
10578 | case 0x5: /* AESD */ | |
10579 | decrypt = 1; | |
10580 | genfn = gen_helper_crypto_aese; | |
10581 | break; | |
10582 | case 0x7: /* AESIMC */ | |
10583 | decrypt = 1; | |
10584 | genfn = gen_helper_crypto_aesmc; | |
10585 | break; | |
10586 | default: | |
10587 | unallocated_encoding(s); | |
10588 | return; | |
10589 | } | |
10590 | ||
10591 | /* Note that we convert the Vx register indexes into the | |
10592 | * index within the vfp.regs[] array, so we can share the | |
10593 | * helper with the AArch32 instructions. | |
10594 | */ | |
10595 | tcg_rd_regno = tcg_const_i32(rd << 1); | |
10596 | tcg_rn_regno = tcg_const_i32(rn << 1); | |
10597 | tcg_decrypt = tcg_const_i32(decrypt); | |
10598 | ||
10599 | genfn(cpu_env, tcg_rd_regno, tcg_rn_regno, tcg_decrypt); | |
10600 | ||
10601 | tcg_temp_free_i32(tcg_rd_regno); | |
10602 | tcg_temp_free_i32(tcg_rn_regno); | |
10603 | tcg_temp_free_i32(tcg_decrypt); | |
384b26fb AB |
10604 | } |
10605 | ||
10606 | /* C3.6.20 Crypto three-reg SHA | |
10607 | * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0 | |
10608 | * +-----------------+------+---+------+---+--------+-----+------+------+ | |
10609 | * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd | | |
10610 | * +-----------------+------+---+------+---+--------+-----+------+------+ | |
10611 | */ | |
10612 | static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn) | |
10613 | { | |
be56f04e PM |
10614 | int size = extract32(insn, 22, 2); |
10615 | int opcode = extract32(insn, 12, 3); | |
10616 | int rm = extract32(insn, 16, 5); | |
10617 | int rn = extract32(insn, 5, 5); | |
10618 | int rd = extract32(insn, 0, 5); | |
10619 | CryptoThreeOpEnvFn *genfn; | |
10620 | TCGv_i32 tcg_rd_regno, tcg_rn_regno, tcg_rm_regno; | |
10621 | int feature = ARM_FEATURE_V8_SHA256; | |
10622 | ||
10623 | if (size != 0) { | |
10624 | unallocated_encoding(s); | |
10625 | return; | |
10626 | } | |
10627 | ||
10628 | switch (opcode) { | |
10629 | case 0: /* SHA1C */ | |
10630 | case 1: /* SHA1P */ | |
10631 | case 2: /* SHA1M */ | |
10632 | case 3: /* SHA1SU0 */ | |
10633 | genfn = NULL; | |
10634 | feature = ARM_FEATURE_V8_SHA1; | |
10635 | break; | |
10636 | case 4: /* SHA256H */ | |
10637 | genfn = gen_helper_crypto_sha256h; | |
10638 | break; | |
10639 | case 5: /* SHA256H2 */ | |
10640 | genfn = gen_helper_crypto_sha256h2; | |
10641 | break; | |
10642 | case 6: /* SHA256SU1 */ | |
10643 | genfn = gen_helper_crypto_sha256su1; | |
10644 | break; | |
10645 | default: | |
10646 | unallocated_encoding(s); | |
10647 | return; | |
10648 | } | |
10649 | ||
10650 | if (!arm_dc_feature(s, feature)) { | |
10651 | unallocated_encoding(s); | |
10652 | return; | |
10653 | } | |
10654 | ||
10655 | tcg_rd_regno = tcg_const_i32(rd << 1); | |
10656 | tcg_rn_regno = tcg_const_i32(rn << 1); | |
10657 | tcg_rm_regno = tcg_const_i32(rm << 1); | |
10658 | ||
10659 | if (genfn) { | |
10660 | genfn(cpu_env, tcg_rd_regno, tcg_rn_regno, tcg_rm_regno); | |
10661 | } else { | |
10662 | TCGv_i32 tcg_opcode = tcg_const_i32(opcode); | |
10663 | ||
10664 | gen_helper_crypto_sha1_3reg(cpu_env, tcg_rd_regno, | |
10665 | tcg_rn_regno, tcg_rm_regno, tcg_opcode); | |
10666 | tcg_temp_free_i32(tcg_opcode); | |
10667 | } | |
10668 | ||
10669 | tcg_temp_free_i32(tcg_rd_regno); | |
10670 | tcg_temp_free_i32(tcg_rn_regno); | |
10671 | tcg_temp_free_i32(tcg_rm_regno); | |
384b26fb AB |
10672 | } |
10673 | ||
10674 | /* C3.6.21 Crypto two-reg SHA | |
10675 | * 31 24 23 22 21 17 16 12 11 10 9 5 4 0 | |
10676 | * +-----------------+------+-----------+--------+-----+------+------+ | |
10677 | * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd | | |
10678 | * +-----------------+------+-----------+--------+-----+------+------+ | |
10679 | */ | |
10680 | static void disas_crypto_two_reg_sha(DisasContext *s, uint32_t insn) | |
10681 | { | |
f6fe04d5 PM |
10682 | int size = extract32(insn, 22, 2); |
10683 | int opcode = extract32(insn, 12, 5); | |
10684 | int rn = extract32(insn, 5, 5); | |
10685 | int rd = extract32(insn, 0, 5); | |
10686 | CryptoTwoOpEnvFn *genfn; | |
10687 | int feature; | |
10688 | TCGv_i32 tcg_rd_regno, tcg_rn_regno; | |
10689 | ||
10690 | if (size != 0) { | |
10691 | unallocated_encoding(s); | |
10692 | return; | |
10693 | } | |
10694 | ||
10695 | switch (opcode) { | |
10696 | case 0: /* SHA1H */ | |
10697 | feature = ARM_FEATURE_V8_SHA1; | |
10698 | genfn = gen_helper_crypto_sha1h; | |
10699 | break; | |
10700 | case 1: /* SHA1SU1 */ | |
10701 | feature = ARM_FEATURE_V8_SHA1; | |
10702 | genfn = gen_helper_crypto_sha1su1; | |
10703 | break; | |
10704 | case 2: /* SHA256SU0 */ | |
10705 | feature = ARM_FEATURE_V8_SHA256; | |
10706 | genfn = gen_helper_crypto_sha256su0; | |
10707 | break; | |
10708 | default: | |
10709 | unallocated_encoding(s); | |
10710 | return; | |
10711 | } | |
10712 | ||
10713 | if (!arm_dc_feature(s, feature)) { | |
10714 | unallocated_encoding(s); | |
10715 | return; | |
10716 | } | |
10717 | ||
10718 | tcg_rd_regno = tcg_const_i32(rd << 1); | |
10719 | tcg_rn_regno = tcg_const_i32(rn << 1); | |
10720 | ||
10721 | genfn(cpu_env, tcg_rd_regno, tcg_rn_regno); | |
10722 | ||
10723 | tcg_temp_free_i32(tcg_rd_regno); | |
10724 | tcg_temp_free_i32(tcg_rn_regno); | |
384b26fb AB |
10725 | } |
10726 | ||
10727 | /* C3.6 Data processing - SIMD, inc Crypto | |
10728 | * | |
10729 | * As the decode gets a little complex we are using a table based | |
10730 | * approach for this part of the decode. | |
10731 | */ | |
10732 | static const AArch64DecodeTable data_proc_simd[] = { | |
10733 | /* pattern , mask , fn */ | |
10734 | { 0x0e200400, 0x9f200400, disas_simd_three_reg_same }, | |
10735 | { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff }, | |
10736 | { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc }, | |
10737 | { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes }, | |
10738 | { 0x0e000400, 0x9fe08400, disas_simd_copy }, | |
9f82e0ff | 10739 | { 0x0f000000, 0x9f000400, disas_simd_indexed }, /* vector indexed */ |
384b26fb AB |
10740 | /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */ |
10741 | { 0x0f000400, 0x9ff80400, disas_simd_mod_imm }, | |
10742 | { 0x0f000400, 0x9f800400, disas_simd_shift_imm }, | |
10743 | { 0x0e000000, 0xbf208c00, disas_simd_tb }, | |
10744 | { 0x0e000800, 0xbf208c00, disas_simd_zip_trn }, | |
10745 | { 0x2e000000, 0xbf208400, disas_simd_ext }, | |
10746 | { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same }, | |
10747 | { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff }, | |
10748 | { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc }, | |
10749 | { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise }, | |
10750 | { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy }, | |
9f82e0ff | 10751 | { 0x5f000000, 0xdf000400, disas_simd_indexed }, /* scalar indexed */ |
384b26fb AB |
10752 | { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm }, |
10753 | { 0x4e280800, 0xff3e0c00, disas_crypto_aes }, | |
10754 | { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha }, | |
10755 | { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha }, | |
10756 | { 0x00000000, 0x00000000, NULL } | |
10757 | }; | |
10758 | ||
faa0ba46 PM |
10759 | static void disas_data_proc_simd(DisasContext *s, uint32_t insn) |
10760 | { | |
10761 | /* Note that this is called with all non-FP cases from | |
10762 | * table C3-6 so it must UNDEF for entries not specifically | |
10763 | * allocated to instructions in that table. | |
10764 | */ | |
384b26fb AB |
10765 | AArch64DecodeFn *fn = lookup_disas_fn(&data_proc_simd[0], insn); |
10766 | if (fn) { | |
10767 | fn(s, insn); | |
10768 | } else { | |
10769 | unallocated_encoding(s); | |
10770 | } | |
faa0ba46 PM |
10771 | } |
10772 | ||
ad7ee8a2 CF |
10773 | /* C3.6 Data processing - SIMD and floating point */ |
10774 | static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn) | |
10775 | { | |
faa0ba46 PM |
10776 | if (extract32(insn, 28, 1) == 1 && extract32(insn, 30, 1) == 0) { |
10777 | disas_data_proc_fp(s, insn); | |
10778 | } else { | |
10779 | /* SIMD, including crypto */ | |
10780 | disas_data_proc_simd(s, insn); | |
10781 | } | |
ad7ee8a2 CF |
10782 | } |
10783 | ||
10784 | /* C3.1 A64 instruction index by encoding */ | |
40f860cd | 10785 | static void disas_a64_insn(CPUARMState *env, DisasContext *s) |
14ade10f AG |
10786 | { |
10787 | uint32_t insn; | |
10788 | ||
10789 | insn = arm_ldl_code(env, s->pc, s->bswap_code); | |
10790 | s->insn = insn; | |
10791 | s->pc += 4; | |
10792 | ||
90e49638 PM |
10793 | s->fp_access_checked = false; |
10794 | ||
ad7ee8a2 CF |
10795 | switch (extract32(insn, 25, 4)) { |
10796 | case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */ | |
14ade10f AG |
10797 | unallocated_encoding(s); |
10798 | break; | |
ad7ee8a2 CF |
10799 | case 0x8: case 0x9: /* Data processing - immediate */ |
10800 | disas_data_proc_imm(s, insn); | |
10801 | break; | |
10802 | case 0xa: case 0xb: /* Branch, exception generation and system insns */ | |
10803 | disas_b_exc_sys(s, insn); | |
10804 | break; | |
10805 | case 0x4: | |
10806 | case 0x6: | |
10807 | case 0xc: | |
10808 | case 0xe: /* Loads and stores */ | |
10809 | disas_ldst(s, insn); | |
10810 | break; | |
10811 | case 0x5: | |
10812 | case 0xd: /* Data processing - register */ | |
10813 | disas_data_proc_reg(s, insn); | |
10814 | break; | |
10815 | case 0x7: | |
10816 | case 0xf: /* Data processing - SIMD and floating point */ | |
10817 | disas_data_proc_simd_fp(s, insn); | |
10818 | break; | |
10819 | default: | |
10820 | assert(FALSE); /* all 15 cases should be handled above */ | |
10821 | break; | |
14ade10f | 10822 | } |
11e169de AG |
10823 | |
10824 | /* if we allocated any temporaries, free them here */ | |
10825 | free_tmp_a64(s); | |
40f860cd | 10826 | } |
14ade10f | 10827 | |
40f860cd PM |
10828 | void gen_intermediate_code_internal_a64(ARMCPU *cpu, |
10829 | TranslationBlock *tb, | |
10830 | bool search_pc) | |
10831 | { | |
10832 | CPUState *cs = CPU(cpu); | |
10833 | CPUARMState *env = &cpu->env; | |
10834 | DisasContext dc1, *dc = &dc1; | |
10835 | CPUBreakpoint *bp; | |
10836 | uint16_t *gen_opc_end; | |
10837 | int j, lj; | |
10838 | target_ulong pc_start; | |
10839 | target_ulong next_page_start; | |
10840 | int num_insns; | |
10841 | int max_insns; | |
10842 | ||
10843 | pc_start = tb->pc; | |
10844 | ||
10845 | dc->tb = tb; | |
10846 | ||
10847 | gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE; | |
10848 | ||
10849 | dc->is_jmp = DISAS_NEXT; | |
10850 | dc->pc = pc_start; | |
10851 | dc->singlestep_enabled = cs->singlestep_enabled; | |
10852 | dc->condjmp = 0; | |
10853 | ||
10854 | dc->aarch64 = 1; | |
10855 | dc->thumb = 0; | |
10856 | dc->bswap_code = 0; | |
10857 | dc->condexec_mask = 0; | |
10858 | dc->condexec_cond = 0; | |
10859 | #if !defined(CONFIG_USER_ONLY) | |
d9ea7d29 | 10860 | dc->user = (ARM_TBFLAG_AA64_EL(tb->flags) == 0); |
40f860cd | 10861 | #endif |
8c6afa6a | 10862 | dc->cpacr_fpen = ARM_TBFLAG_AA64_FPEN(tb->flags); |
40f860cd PM |
10863 | dc->vec_len = 0; |
10864 | dc->vec_stride = 0; | |
60322b39 PM |
10865 | dc->cp_regs = cpu->cp_regs; |
10866 | dc->current_pl = arm_current_pl(env); | |
a984e42c | 10867 | dc->features = env->features; |
40f860cd | 10868 | |
11e169de AG |
10869 | init_tmp_a64_array(dc); |
10870 | ||
40f860cd PM |
10871 | next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; |
10872 | lj = -1; | |
10873 | num_insns = 0; | |
10874 | max_insns = tb->cflags & CF_COUNT_MASK; | |
10875 | if (max_insns == 0) { | |
10876 | max_insns = CF_COUNT_MASK; | |
10877 | } | |
10878 | ||
10879 | gen_tb_start(); | |
10880 | ||
10881 | tcg_clear_temp_count(); | |
10882 | ||
10883 | do { | |
f0c3c505 AF |
10884 | if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { |
10885 | QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { | |
40f860cd | 10886 | if (bp->pc == dc->pc) { |
d4a2dc67 | 10887 | gen_exception_internal_insn(dc, 0, EXCP_DEBUG); |
40f860cd PM |
10888 | /* Advance PC so that clearing the breakpoint will |
10889 | invalidate this TB. */ | |
10890 | dc->pc += 2; | |
10891 | goto done_generating; | |
10892 | } | |
10893 | } | |
10894 | } | |
10895 | ||
10896 | if (search_pc) { | |
10897 | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; | |
10898 | if (lj < j) { | |
10899 | lj++; | |
10900 | while (lj < j) { | |
10901 | tcg_ctx.gen_opc_instr_start[lj++] = 0; | |
10902 | } | |
10903 | } | |
10904 | tcg_ctx.gen_opc_pc[lj] = dc->pc; | |
10905 | tcg_ctx.gen_opc_instr_start[lj] = 1; | |
10906 | tcg_ctx.gen_opc_icount[lj] = num_insns; | |
10907 | } | |
10908 | ||
10909 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { | |
10910 | gen_io_start(); | |
10911 | } | |
10912 | ||
10913 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { | |
10914 | tcg_gen_debug_insn_start(dc->pc); | |
10915 | } | |
10916 | ||
10917 | disas_a64_insn(env, dc); | |
10918 | ||
10919 | if (tcg_check_temp_count()) { | |
10920 | fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", | |
10921 | dc->pc); | |
10922 | } | |
10923 | ||
10924 | /* Translation stops when a conditional branch is encountered. | |
10925 | * Otherwise the subsequent code could get translated several times. | |
10926 | * Also stop translation when a page boundary is reached. This | |
10927 | * ensures prefetch aborts occur at the right place. | |
10928 | */ | |
10929 | num_insns++; | |
10930 | } while (!dc->is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end && | |
10931 | !cs->singlestep_enabled && | |
10932 | !singlestep && | |
10933 | dc->pc < next_page_start && | |
10934 | num_insns < max_insns); | |
10935 | ||
10936 | if (tb->cflags & CF_LAST_IO) { | |
10937 | gen_io_end(); | |
10938 | } | |
10939 | ||
10940 | if (unlikely(cs->singlestep_enabled) && dc->is_jmp != DISAS_EXC) { | |
10941 | /* Note that this means single stepping WFI doesn't halt the CPU. | |
10942 | * For conditional branch insns this is harmless unreachable code as | |
10943 | * gen_goto_tb() has already handled emitting the debug exception | |
10944 | * (and thus a tb-jump is not possible when singlestepping). | |
10945 | */ | |
10946 | assert(dc->is_jmp != DISAS_TB_JUMP); | |
10947 | if (dc->is_jmp != DISAS_JUMP) { | |
10948 | gen_a64_set_pc_im(dc->pc); | |
10949 | } | |
d4a2dc67 | 10950 | gen_exception_internal(EXCP_DEBUG); |
40f860cd PM |
10951 | } else { |
10952 | switch (dc->is_jmp) { | |
10953 | case DISAS_NEXT: | |
10954 | gen_goto_tb(dc, 1, dc->pc); | |
10955 | break; | |
10956 | default: | |
40f860cd | 10957 | case DISAS_UPDATE: |
fea50522 PM |
10958 | gen_a64_set_pc_im(dc->pc); |
10959 | /* fall through */ | |
10960 | case DISAS_JUMP: | |
40f860cd PM |
10961 | /* indicate that the hash table must be used to find the next TB */ |
10962 | tcg_gen_exit_tb(0); | |
10963 | break; | |
10964 | case DISAS_TB_JUMP: | |
10965 | case DISAS_EXC: | |
10966 | case DISAS_SWI: | |
10967 | break; | |
252ec405 RH |
10968 | case DISAS_WFE: |
10969 | gen_a64_set_pc_im(dc->pc); | |
10970 | gen_helper_wfe(cpu_env); | |
10971 | break; | |
40f860cd PM |
10972 | case DISAS_WFI: |
10973 | /* This is a special case because we don't want to just halt the CPU | |
10974 | * if trying to debug across a WFI. | |
10975 | */ | |
1ed69e82 | 10976 | gen_a64_set_pc_im(dc->pc); |
40f860cd PM |
10977 | gen_helper_wfi(cpu_env); |
10978 | break; | |
10979 | } | |
10980 | } | |
10981 | ||
10982 | done_generating: | |
10983 | gen_tb_end(tb, num_insns); | |
10984 | *tcg_ctx.gen_opc_ptr = INDEX_op_end; | |
10985 | ||
10986 | #ifdef DEBUG_DISAS | |
10987 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { | |
10988 | qemu_log("----------------\n"); | |
10989 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); | |
10990 | log_target_disas(env, pc_start, dc->pc - pc_start, | |
999b53ec | 10991 | 4 | (dc->bswap_code << 1)); |
40f860cd PM |
10992 | qemu_log("\n"); |
10993 | } | |
10994 | #endif | |
10995 | if (search_pc) { | |
10996 | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; | |
10997 | lj++; | |
10998 | while (lj <= j) { | |
10999 | tcg_ctx.gen_opc_instr_start[lj++] = 0; | |
11000 | } | |
11001 | } else { | |
11002 | tb->size = dc->pc - pc_start; | |
11003 | tb->icount = num_insns; | |
14ade10f AG |
11004 | } |
11005 | } |