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14ade10f AG |
1 | /* |
2 | * AArch64 translation | |
3 | * | |
4 | * Copyright (c) 2013 Alexander Graf <agraf@suse.de> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | #include <stdarg.h> | |
20 | #include <stdlib.h> | |
21 | #include <stdio.h> | |
22 | #include <string.h> | |
23 | #include <inttypes.h> | |
24 | ||
25 | #include "cpu.h" | |
26 | #include "tcg-op.h" | |
27 | #include "qemu/log.h" | |
28 | #include "translate.h" | |
29 | #include "qemu/host-utils.h" | |
30 | ||
40f860cd PM |
31 | #include "exec/gen-icount.h" |
32 | ||
14ade10f AG |
33 | #include "helper.h" |
34 | #define GEN_HELPER 1 | |
35 | #include "helper.h" | |
36 | ||
37 | static TCGv_i64 cpu_X[32]; | |
38 | static TCGv_i64 cpu_pc; | |
832ffa1c | 39 | static TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF; |
14ade10f AG |
40 | |
41 | static const char *regnames[] = { | |
42 | "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", | |
43 | "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", | |
44 | "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", | |
45 | "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp" | |
46 | }; | |
47 | ||
832ffa1c AG |
48 | enum a64_shift_type { |
49 | A64_SHIFT_TYPE_LSL = 0, | |
50 | A64_SHIFT_TYPE_LSR = 1, | |
51 | A64_SHIFT_TYPE_ASR = 2, | |
52 | A64_SHIFT_TYPE_ROR = 3 | |
53 | }; | |
54 | ||
14ade10f AG |
55 | /* initialize TCG globals. */ |
56 | void a64_translate_init(void) | |
57 | { | |
58 | int i; | |
59 | ||
60 | cpu_pc = tcg_global_mem_new_i64(TCG_AREG0, | |
61 | offsetof(CPUARMState, pc), | |
62 | "pc"); | |
63 | for (i = 0; i < 32; i++) { | |
64 | cpu_X[i] = tcg_global_mem_new_i64(TCG_AREG0, | |
65 | offsetof(CPUARMState, xregs[i]), | |
66 | regnames[i]); | |
67 | } | |
68 | ||
832ffa1c AG |
69 | cpu_NF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, NF), "NF"); |
70 | cpu_ZF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, ZF), "ZF"); | |
71 | cpu_CF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, CF), "CF"); | |
72 | cpu_VF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, VF), "VF"); | |
14ade10f AG |
73 | } |
74 | ||
75 | void aarch64_cpu_dump_state(CPUState *cs, FILE *f, | |
76 | fprintf_function cpu_fprintf, int flags) | |
77 | { | |
78 | ARMCPU *cpu = ARM_CPU(cs); | |
79 | CPUARMState *env = &cpu->env; | |
d356312f | 80 | uint32_t psr = pstate_read(env); |
14ade10f AG |
81 | int i; |
82 | ||
83 | cpu_fprintf(f, "PC=%016"PRIx64" SP=%016"PRIx64"\n", | |
84 | env->pc, env->xregs[31]); | |
85 | for (i = 0; i < 31; i++) { | |
86 | cpu_fprintf(f, "X%02d=%016"PRIx64, i, env->xregs[i]); | |
87 | if ((i % 4) == 3) { | |
88 | cpu_fprintf(f, "\n"); | |
89 | } else { | |
90 | cpu_fprintf(f, " "); | |
91 | } | |
92 | } | |
d356312f PM |
93 | cpu_fprintf(f, "PSTATE=%08x (flags %c%c%c%c)\n", |
94 | psr, | |
95 | psr & PSTATE_N ? 'N' : '-', | |
96 | psr & PSTATE_Z ? 'Z' : '-', | |
97 | psr & PSTATE_C ? 'C' : '-', | |
98 | psr & PSTATE_V ? 'V' : '-'); | |
14ade10f AG |
99 | cpu_fprintf(f, "\n"); |
100 | } | |
101 | ||
4a08d475 PM |
102 | static int get_mem_index(DisasContext *s) |
103 | { | |
104 | #ifdef CONFIG_USER_ONLY | |
105 | return 1; | |
106 | #else | |
107 | return s->user; | |
108 | #endif | |
109 | } | |
110 | ||
14ade10f AG |
111 | void gen_a64_set_pc_im(uint64_t val) |
112 | { | |
113 | tcg_gen_movi_i64(cpu_pc, val); | |
114 | } | |
115 | ||
116 | static void gen_exception(int excp) | |
117 | { | |
118 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
119 | tcg_gen_movi_i32(tmp, excp); | |
120 | gen_helper_exception(cpu_env, tmp); | |
121 | tcg_temp_free_i32(tmp); | |
122 | } | |
123 | ||
124 | static void gen_exception_insn(DisasContext *s, int offset, int excp) | |
125 | { | |
126 | gen_a64_set_pc_im(s->pc - offset); | |
127 | gen_exception(excp); | |
40f860cd PM |
128 | s->is_jmp = DISAS_EXC; |
129 | } | |
130 | ||
131 | static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest) | |
132 | { | |
133 | /* No direct tb linking with singlestep or deterministic io */ | |
134 | if (s->singlestep_enabled || (s->tb->cflags & CF_LAST_IO)) { | |
135 | return false; | |
136 | } | |
137 | ||
138 | /* Only link tbs from inside the same guest page */ | |
139 | if ((s->tb->pc & TARGET_PAGE_MASK) != (dest & TARGET_PAGE_MASK)) { | |
140 | return false; | |
141 | } | |
142 | ||
143 | return true; | |
144 | } | |
145 | ||
146 | static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest) | |
147 | { | |
148 | TranslationBlock *tb; | |
149 | ||
150 | tb = s->tb; | |
151 | if (use_goto_tb(s, n, dest)) { | |
152 | tcg_gen_goto_tb(n); | |
153 | gen_a64_set_pc_im(dest); | |
154 | tcg_gen_exit_tb((tcg_target_long)tb + n); | |
155 | s->is_jmp = DISAS_TB_JUMP; | |
156 | } else { | |
157 | gen_a64_set_pc_im(dest); | |
158 | if (s->singlestep_enabled) { | |
159 | gen_exception(EXCP_DEBUG); | |
160 | } | |
161 | tcg_gen_exit_tb(0); | |
162 | s->is_jmp = DISAS_JUMP; | |
163 | } | |
14ade10f AG |
164 | } |
165 | ||
ad7ee8a2 | 166 | static void unallocated_encoding(DisasContext *s) |
14ade10f | 167 | { |
14ade10f AG |
168 | gen_exception_insn(s, 4, EXCP_UDEF); |
169 | } | |
170 | ||
ad7ee8a2 CF |
171 | #define unsupported_encoding(s, insn) \ |
172 | do { \ | |
173 | qemu_log_mask(LOG_UNIMP, \ | |
174 | "%s:%d: unsupported instruction encoding 0x%08x " \ | |
175 | "at pc=%016" PRIx64 "\n", \ | |
176 | __FILE__, __LINE__, insn, s->pc - 4); \ | |
177 | unallocated_encoding(s); \ | |
178 | } while (0); | |
14ade10f | 179 | |
11e169de AG |
180 | static void init_tmp_a64_array(DisasContext *s) |
181 | { | |
182 | #ifdef CONFIG_DEBUG_TCG | |
183 | int i; | |
184 | for (i = 0; i < ARRAY_SIZE(s->tmp_a64); i++) { | |
185 | TCGV_UNUSED_I64(s->tmp_a64[i]); | |
186 | } | |
187 | #endif | |
188 | s->tmp_a64_count = 0; | |
189 | } | |
190 | ||
191 | static void free_tmp_a64(DisasContext *s) | |
192 | { | |
193 | int i; | |
194 | for (i = 0; i < s->tmp_a64_count; i++) { | |
195 | tcg_temp_free_i64(s->tmp_a64[i]); | |
196 | } | |
197 | init_tmp_a64_array(s); | |
198 | } | |
199 | ||
200 | static TCGv_i64 new_tmp_a64(DisasContext *s) | |
201 | { | |
202 | assert(s->tmp_a64_count < TMP_A64_MAX); | |
203 | return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_new_i64(); | |
204 | } | |
205 | ||
206 | static TCGv_i64 new_tmp_a64_zero(DisasContext *s) | |
207 | { | |
208 | TCGv_i64 t = new_tmp_a64(s); | |
209 | tcg_gen_movi_i64(t, 0); | |
210 | return t; | |
211 | } | |
212 | ||
71b46089 AG |
213 | /* |
214 | * Register access functions | |
215 | * | |
216 | * These functions are used for directly accessing a register in where | |
217 | * changes to the final register value are likely to be made. If you | |
218 | * need to use a register for temporary calculation (e.g. index type | |
219 | * operations) use the read_* form. | |
220 | * | |
221 | * B1.2.1 Register mappings | |
222 | * | |
223 | * In instruction register encoding 31 can refer to ZR (zero register) or | |
224 | * the SP (stack pointer) depending on context. In QEMU's case we map SP | |
225 | * to cpu_X[31] and ZR accesses to a temporary which can be discarded. | |
226 | * This is the point of the _sp forms. | |
227 | */ | |
11e169de AG |
228 | static TCGv_i64 cpu_reg(DisasContext *s, int reg) |
229 | { | |
230 | if (reg == 31) { | |
231 | return new_tmp_a64_zero(s); | |
232 | } else { | |
233 | return cpu_X[reg]; | |
234 | } | |
235 | } | |
236 | ||
71b46089 AG |
237 | /* register access for when 31 == SP */ |
238 | static TCGv_i64 cpu_reg_sp(DisasContext *s, int reg) | |
239 | { | |
240 | return cpu_X[reg]; | |
241 | } | |
242 | ||
60e53388 AG |
243 | /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64 |
244 | * representing the register contents. This TCGv is an auto-freed | |
245 | * temporary so it need not be explicitly freed, and may be modified. | |
246 | */ | |
247 | static TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf) | |
248 | { | |
249 | TCGv_i64 v = new_tmp_a64(s); | |
250 | if (reg != 31) { | |
251 | if (sf) { | |
252 | tcg_gen_mov_i64(v, cpu_X[reg]); | |
253 | } else { | |
254 | tcg_gen_ext32u_i64(v, cpu_X[reg]); | |
255 | } | |
256 | } else { | |
257 | tcg_gen_movi_i64(v, 0); | |
258 | } | |
259 | return v; | |
260 | } | |
261 | ||
4a08d475 PM |
262 | static TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf) |
263 | { | |
264 | TCGv_i64 v = new_tmp_a64(s); | |
265 | if (sf) { | |
266 | tcg_gen_mov_i64(v, cpu_X[reg]); | |
267 | } else { | |
268 | tcg_gen_ext32u_i64(v, cpu_X[reg]); | |
269 | } | |
270 | return v; | |
271 | } | |
272 | ||
832ffa1c AG |
273 | /* Set ZF and NF based on a 64 bit result. This is alas fiddlier |
274 | * than the 32 bit equivalent. | |
275 | */ | |
276 | static inline void gen_set_NZ64(TCGv_i64 result) | |
277 | { | |
278 | TCGv_i64 flag = tcg_temp_new_i64(); | |
279 | ||
280 | tcg_gen_setcondi_i64(TCG_COND_NE, flag, result, 0); | |
281 | tcg_gen_trunc_i64_i32(cpu_ZF, flag); | |
282 | tcg_gen_shri_i64(flag, result, 32); | |
283 | tcg_gen_trunc_i64_i32(cpu_NF, flag); | |
284 | tcg_temp_free_i64(flag); | |
285 | } | |
286 | ||
287 | /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */ | |
288 | static inline void gen_logic_CC(int sf, TCGv_i64 result) | |
289 | { | |
290 | if (sf) { | |
291 | gen_set_NZ64(result); | |
292 | } else { | |
293 | tcg_gen_trunc_i64_i32(cpu_ZF, result); | |
294 | tcg_gen_trunc_i64_i32(cpu_NF, result); | |
295 | } | |
296 | tcg_gen_movi_i32(cpu_CF, 0); | |
297 | tcg_gen_movi_i32(cpu_VF, 0); | |
298 | } | |
299 | ||
b0ff21b4 AB |
300 | /* dest = T0 + T1; compute C, N, V and Z flags */ |
301 | static void gen_add_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | |
302 | { | |
303 | if (sf) { | |
304 | TCGv_i64 result, flag, tmp; | |
305 | result = tcg_temp_new_i64(); | |
306 | flag = tcg_temp_new_i64(); | |
307 | tmp = tcg_temp_new_i64(); | |
308 | ||
309 | tcg_gen_movi_i64(tmp, 0); | |
310 | tcg_gen_add2_i64(result, flag, t0, tmp, t1, tmp); | |
311 | ||
312 | tcg_gen_trunc_i64_i32(cpu_CF, flag); | |
313 | ||
314 | gen_set_NZ64(result); | |
315 | ||
316 | tcg_gen_xor_i64(flag, result, t0); | |
317 | tcg_gen_xor_i64(tmp, t0, t1); | |
318 | tcg_gen_andc_i64(flag, flag, tmp); | |
319 | tcg_temp_free_i64(tmp); | |
320 | tcg_gen_shri_i64(flag, flag, 32); | |
321 | tcg_gen_trunc_i64_i32(cpu_VF, flag); | |
322 | ||
323 | tcg_gen_mov_i64(dest, result); | |
324 | tcg_temp_free_i64(result); | |
325 | tcg_temp_free_i64(flag); | |
326 | } else { | |
327 | /* 32 bit arithmetic */ | |
328 | TCGv_i32 t0_32 = tcg_temp_new_i32(); | |
329 | TCGv_i32 t1_32 = tcg_temp_new_i32(); | |
330 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
331 | ||
332 | tcg_gen_movi_i32(tmp, 0); | |
333 | tcg_gen_trunc_i64_i32(t0_32, t0); | |
334 | tcg_gen_trunc_i64_i32(t1_32, t1); | |
335 | tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, t1_32, tmp); | |
336 | tcg_gen_mov_i32(cpu_ZF, cpu_NF); | |
337 | tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); | |
338 | tcg_gen_xor_i32(tmp, t0_32, t1_32); | |
339 | tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp); | |
340 | tcg_gen_extu_i32_i64(dest, cpu_NF); | |
341 | ||
342 | tcg_temp_free_i32(tmp); | |
343 | tcg_temp_free_i32(t0_32); | |
344 | tcg_temp_free_i32(t1_32); | |
345 | } | |
346 | } | |
347 | ||
348 | /* dest = T0 - T1; compute C, N, V and Z flags */ | |
349 | static void gen_sub_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) | |
350 | { | |
351 | if (sf) { | |
352 | /* 64 bit arithmetic */ | |
353 | TCGv_i64 result, flag, tmp; | |
354 | ||
355 | result = tcg_temp_new_i64(); | |
356 | flag = tcg_temp_new_i64(); | |
357 | tcg_gen_sub_i64(result, t0, t1); | |
358 | ||
359 | gen_set_NZ64(result); | |
360 | ||
361 | tcg_gen_setcond_i64(TCG_COND_GEU, flag, t0, t1); | |
362 | tcg_gen_trunc_i64_i32(cpu_CF, flag); | |
363 | ||
364 | tcg_gen_xor_i64(flag, result, t0); | |
365 | tmp = tcg_temp_new_i64(); | |
366 | tcg_gen_xor_i64(tmp, t0, t1); | |
367 | tcg_gen_and_i64(flag, flag, tmp); | |
368 | tcg_temp_free_i64(tmp); | |
369 | tcg_gen_shri_i64(flag, flag, 32); | |
370 | tcg_gen_trunc_i64_i32(cpu_VF, flag); | |
371 | tcg_gen_mov_i64(dest, result); | |
372 | tcg_temp_free_i64(flag); | |
373 | tcg_temp_free_i64(result); | |
374 | } else { | |
375 | /* 32 bit arithmetic */ | |
376 | TCGv_i32 t0_32 = tcg_temp_new_i32(); | |
377 | TCGv_i32 t1_32 = tcg_temp_new_i32(); | |
378 | TCGv_i32 tmp; | |
379 | ||
380 | tcg_gen_trunc_i64_i32(t0_32, t0); | |
381 | tcg_gen_trunc_i64_i32(t1_32, t1); | |
382 | tcg_gen_sub_i32(cpu_NF, t0_32, t1_32); | |
383 | tcg_gen_mov_i32(cpu_ZF, cpu_NF); | |
384 | tcg_gen_setcond_i32(TCG_COND_GEU, cpu_CF, t0_32, t1_32); | |
385 | tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); | |
386 | tmp = tcg_temp_new_i32(); | |
387 | tcg_gen_xor_i32(tmp, t0_32, t1_32); | |
388 | tcg_temp_free_i32(t0_32); | |
389 | tcg_temp_free_i32(t1_32); | |
390 | tcg_gen_and_i32(cpu_VF, cpu_VF, tmp); | |
391 | tcg_temp_free_i32(tmp); | |
392 | tcg_gen_extu_i32_i64(dest, cpu_NF); | |
393 | } | |
394 | } | |
395 | ||
4a08d475 PM |
396 | /* |
397 | * Load/Store generators | |
398 | */ | |
399 | ||
400 | /* | |
401 | * Store from GPR register to memory | |
402 | */ | |
403 | static void do_gpr_st(DisasContext *s, TCGv_i64 source, | |
404 | TCGv_i64 tcg_addr, int size) | |
405 | { | |
406 | g_assert(size <= 3); | |
407 | tcg_gen_qemu_st_i64(source, tcg_addr, get_mem_index(s), MO_TE + size); | |
408 | } | |
409 | ||
410 | /* | |
411 | * Load from memory to GPR register | |
412 | */ | |
413 | static void do_gpr_ld(DisasContext *s, TCGv_i64 dest, TCGv_i64 tcg_addr, | |
414 | int size, bool is_signed, bool extend) | |
415 | { | |
416 | TCGMemOp memop = MO_TE + size; | |
417 | ||
418 | g_assert(size <= 3); | |
419 | ||
420 | if (is_signed) { | |
421 | memop += MO_SIGN; | |
422 | } | |
423 | ||
424 | tcg_gen_qemu_ld_i64(dest, tcg_addr, get_mem_index(s), memop); | |
425 | ||
426 | if (extend && is_signed) { | |
427 | g_assert(size < 3); | |
428 | tcg_gen_ext32u_i64(dest, dest); | |
429 | } | |
430 | } | |
431 | ||
432 | /* | |
433 | * Store from FP register to memory | |
434 | */ | |
435 | static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, int size) | |
436 | { | |
437 | /* This writes the bottom N bits of a 128 bit wide vector to memory */ | |
438 | int freg_offs = offsetof(CPUARMState, vfp.regs[srcidx * 2]); | |
439 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
440 | ||
441 | if (size < 4) { | |
442 | switch (size) { | |
443 | case 0: | |
444 | tcg_gen_ld8u_i64(tmp, cpu_env, freg_offs); | |
445 | break; | |
446 | case 1: | |
447 | tcg_gen_ld16u_i64(tmp, cpu_env, freg_offs); | |
448 | break; | |
449 | case 2: | |
450 | tcg_gen_ld32u_i64(tmp, cpu_env, freg_offs); | |
451 | break; | |
452 | case 3: | |
453 | tcg_gen_ld_i64(tmp, cpu_env, freg_offs); | |
454 | break; | |
455 | } | |
456 | tcg_gen_qemu_st_i64(tmp, tcg_addr, get_mem_index(s), MO_TE + size); | |
457 | } else { | |
458 | TCGv_i64 tcg_hiaddr = tcg_temp_new_i64(); | |
459 | tcg_gen_ld_i64(tmp, cpu_env, freg_offs); | |
460 | tcg_gen_qemu_st_i64(tmp, tcg_addr, get_mem_index(s), MO_TEQ); | |
461 | tcg_gen_qemu_st64(tmp, tcg_addr, get_mem_index(s)); | |
462 | tcg_gen_ld_i64(tmp, cpu_env, freg_offs + sizeof(float64)); | |
463 | tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8); | |
464 | tcg_gen_qemu_st_i64(tmp, tcg_hiaddr, get_mem_index(s), MO_TEQ); | |
465 | tcg_temp_free_i64(tcg_hiaddr); | |
466 | } | |
467 | ||
468 | tcg_temp_free_i64(tmp); | |
469 | } | |
470 | ||
471 | /* | |
472 | * Load from memory to FP register | |
473 | */ | |
474 | static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size) | |
475 | { | |
476 | /* This always zero-extends and writes to a full 128 bit wide vector */ | |
477 | int freg_offs = offsetof(CPUARMState, vfp.regs[destidx * 2]); | |
478 | TCGv_i64 tmplo = tcg_temp_new_i64(); | |
479 | TCGv_i64 tmphi; | |
480 | ||
481 | if (size < 4) { | |
482 | TCGMemOp memop = MO_TE + size; | |
483 | tmphi = tcg_const_i64(0); | |
484 | tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), memop); | |
485 | } else { | |
486 | TCGv_i64 tcg_hiaddr; | |
487 | tmphi = tcg_temp_new_i64(); | |
488 | tcg_hiaddr = tcg_temp_new_i64(); | |
489 | ||
490 | tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), MO_TEQ); | |
491 | tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8); | |
492 | tcg_gen_qemu_ld_i64(tmphi, tcg_hiaddr, get_mem_index(s), MO_TEQ); | |
493 | tcg_temp_free_i64(tcg_hiaddr); | |
494 | } | |
495 | ||
496 | tcg_gen_st_i64(tmplo, cpu_env, freg_offs); | |
497 | tcg_gen_st_i64(tmphi, cpu_env, freg_offs + sizeof(float64)); | |
498 | ||
499 | tcg_temp_free_i64(tmplo); | |
500 | tcg_temp_free_i64(tmphi); | |
501 | } | |
502 | ||
229b7a05 AB |
503 | /* |
504 | * This utility function is for doing register extension with an | |
505 | * optional shift. You will likely want to pass a temporary for the | |
506 | * destination register. See DecodeRegExtend() in the ARM ARM. | |
507 | */ | |
508 | static void ext_and_shift_reg(TCGv_i64 tcg_out, TCGv_i64 tcg_in, | |
509 | int option, unsigned int shift) | |
510 | { | |
511 | int extsize = extract32(option, 0, 2); | |
512 | bool is_signed = extract32(option, 2, 1); | |
513 | ||
514 | if (is_signed) { | |
515 | switch (extsize) { | |
516 | case 0: | |
517 | tcg_gen_ext8s_i64(tcg_out, tcg_in); | |
518 | break; | |
519 | case 1: | |
520 | tcg_gen_ext16s_i64(tcg_out, tcg_in); | |
521 | break; | |
522 | case 2: | |
523 | tcg_gen_ext32s_i64(tcg_out, tcg_in); | |
524 | break; | |
525 | case 3: | |
526 | tcg_gen_mov_i64(tcg_out, tcg_in); | |
527 | break; | |
528 | } | |
529 | } else { | |
530 | switch (extsize) { | |
531 | case 0: | |
532 | tcg_gen_ext8u_i64(tcg_out, tcg_in); | |
533 | break; | |
534 | case 1: | |
535 | tcg_gen_ext16u_i64(tcg_out, tcg_in); | |
536 | break; | |
537 | case 2: | |
538 | tcg_gen_ext32u_i64(tcg_out, tcg_in); | |
539 | break; | |
540 | case 3: | |
541 | tcg_gen_mov_i64(tcg_out, tcg_in); | |
542 | break; | |
543 | } | |
544 | } | |
545 | ||
546 | if (shift) { | |
547 | tcg_gen_shli_i64(tcg_out, tcg_out, shift); | |
548 | } | |
549 | } | |
550 | ||
4a08d475 PM |
551 | static inline void gen_check_sp_alignment(DisasContext *s) |
552 | { | |
553 | /* The AArch64 architecture mandates that (if enabled via PSTATE | |
554 | * or SCTLR bits) there is a check that SP is 16-aligned on every | |
555 | * SP-relative load or store (with an exception generated if it is not). | |
556 | * In line with general QEMU practice regarding misaligned accesses, | |
557 | * we omit these checks for the sake of guest program performance. | |
558 | * This function is provided as a hook so we can more easily add these | |
559 | * checks in future (possibly as a "favour catching guest program bugs | |
560 | * over speed" user selectable option). | |
561 | */ | |
562 | } | |
563 | ||
ad7ee8a2 CF |
564 | /* |
565 | * the instruction disassembly implemented here matches | |
566 | * the instruction encoding classifications in chapter 3 (C3) | |
567 | * of the ARM Architecture Reference Manual (DDI0487A_a) | |
568 | */ | |
569 | ||
11e169de AG |
570 | /* C3.2.7 Unconditional branch (immediate) |
571 | * 31 30 26 25 0 | |
572 | * +----+-----------+-------------------------------------+ | |
573 | * | op | 0 0 1 0 1 | imm26 | | |
574 | * +----+-----------+-------------------------------------+ | |
575 | */ | |
ad7ee8a2 CF |
576 | static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) |
577 | { | |
11e169de AG |
578 | uint64_t addr = s->pc + sextract32(insn, 0, 26) * 4 - 4; |
579 | ||
580 | if (insn & (1 << 31)) { | |
581 | /* C5.6.26 BL Branch with link */ | |
582 | tcg_gen_movi_i64(cpu_reg(s, 30), s->pc); | |
583 | } | |
584 | ||
585 | /* C5.6.20 B Branch / C5.6.26 BL Branch with link */ | |
586 | gen_goto_tb(s, 0, addr); | |
ad7ee8a2 CF |
587 | } |
588 | ||
60e53388 AG |
589 | /* C3.2.1 Compare & branch (immediate) |
590 | * 31 30 25 24 23 5 4 0 | |
591 | * +----+-------------+----+---------------------+--------+ | |
592 | * | sf | 0 1 1 0 1 0 | op | imm19 | Rt | | |
593 | * +----+-------------+----+---------------------+--------+ | |
594 | */ | |
ad7ee8a2 CF |
595 | static void disas_comp_b_imm(DisasContext *s, uint32_t insn) |
596 | { | |
60e53388 AG |
597 | unsigned int sf, op, rt; |
598 | uint64_t addr; | |
599 | int label_match; | |
600 | TCGv_i64 tcg_cmp; | |
601 | ||
602 | sf = extract32(insn, 31, 1); | |
603 | op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */ | |
604 | rt = extract32(insn, 0, 5); | |
605 | addr = s->pc + sextract32(insn, 5, 19) * 4 - 4; | |
606 | ||
607 | tcg_cmp = read_cpu_reg(s, rt, sf); | |
608 | label_match = gen_new_label(); | |
609 | ||
610 | tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, | |
611 | tcg_cmp, 0, label_match); | |
612 | ||
613 | gen_goto_tb(s, 0, s->pc); | |
614 | gen_set_label(label_match); | |
615 | gen_goto_tb(s, 1, addr); | |
ad7ee8a2 CF |
616 | } |
617 | ||
db0f7958 AG |
618 | /* C3.2.5 Test & branch (immediate) |
619 | * 31 30 25 24 23 19 18 5 4 0 | |
620 | * +----+-------------+----+-------+-------------+------+ | |
621 | * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt | | |
622 | * +----+-------------+----+-------+-------------+------+ | |
623 | */ | |
ad7ee8a2 CF |
624 | static void disas_test_b_imm(DisasContext *s, uint32_t insn) |
625 | { | |
db0f7958 AG |
626 | unsigned int bit_pos, op, rt; |
627 | uint64_t addr; | |
628 | int label_match; | |
629 | TCGv_i64 tcg_cmp; | |
630 | ||
631 | bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5); | |
632 | op = extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */ | |
633 | addr = s->pc + sextract32(insn, 5, 14) * 4 - 4; | |
634 | rt = extract32(insn, 0, 5); | |
635 | ||
636 | tcg_cmp = tcg_temp_new_i64(); | |
637 | tcg_gen_andi_i64(tcg_cmp, cpu_reg(s, rt), (1ULL << bit_pos)); | |
638 | label_match = gen_new_label(); | |
639 | tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, | |
640 | tcg_cmp, 0, label_match); | |
641 | tcg_temp_free_i64(tcg_cmp); | |
642 | gen_goto_tb(s, 0, s->pc); | |
643 | gen_set_label(label_match); | |
644 | gen_goto_tb(s, 1, addr); | |
ad7ee8a2 CF |
645 | } |
646 | ||
39fb730a AG |
647 | /* C3.2.2 / C5.6.19 Conditional branch (immediate) |
648 | * 31 25 24 23 5 4 3 0 | |
649 | * +---------------+----+---------------------+----+------+ | |
650 | * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond | | |
651 | * +---------------+----+---------------------+----+------+ | |
652 | */ | |
ad7ee8a2 CF |
653 | static void disas_cond_b_imm(DisasContext *s, uint32_t insn) |
654 | { | |
39fb730a AG |
655 | unsigned int cond; |
656 | uint64_t addr; | |
657 | ||
658 | if ((insn & (1 << 4)) || (insn & (1 << 24))) { | |
659 | unallocated_encoding(s); | |
660 | return; | |
661 | } | |
662 | addr = s->pc + sextract32(insn, 5, 19) * 4 - 4; | |
663 | cond = extract32(insn, 0, 4); | |
664 | ||
665 | if (cond < 0x0e) { | |
666 | /* genuinely conditional branches */ | |
667 | int label_match = gen_new_label(); | |
668 | arm_gen_test_cc(cond, label_match); | |
669 | gen_goto_tb(s, 0, s->pc); | |
670 | gen_set_label(label_match); | |
671 | gen_goto_tb(s, 1, addr); | |
672 | } else { | |
673 | /* 0xe and 0xf are both "always" conditions */ | |
674 | gen_goto_tb(s, 0, addr); | |
675 | } | |
ad7ee8a2 CF |
676 | } |
677 | ||
87462e0f CF |
678 | /* C5.6.68 HINT */ |
679 | static void handle_hint(DisasContext *s, uint32_t insn, | |
680 | unsigned int op1, unsigned int op2, unsigned int crm) | |
681 | { | |
682 | unsigned int selector = crm << 3 | op2; | |
683 | ||
684 | if (op1 != 3) { | |
685 | unallocated_encoding(s); | |
686 | return; | |
687 | } | |
688 | ||
689 | switch (selector) { | |
690 | case 0: /* NOP */ | |
691 | return; | |
692 | case 1: /* YIELD */ | |
693 | case 2: /* WFE */ | |
694 | case 3: /* WFI */ | |
695 | case 4: /* SEV */ | |
696 | case 5: /* SEVL */ | |
697 | /* we treat all as NOP at least for now */ | |
698 | return; | |
699 | default: | |
700 | /* default specified as NOP equivalent */ | |
701 | return; | |
702 | } | |
703 | } | |
704 | ||
705 | /* CLREX, DSB, DMB, ISB */ | |
706 | static void handle_sync(DisasContext *s, uint32_t insn, | |
707 | unsigned int op1, unsigned int op2, unsigned int crm) | |
708 | { | |
709 | if (op1 != 3) { | |
710 | unallocated_encoding(s); | |
711 | return; | |
712 | } | |
713 | ||
714 | switch (op2) { | |
715 | case 2: /* CLREX */ | |
716 | unsupported_encoding(s, insn); | |
717 | return; | |
718 | case 4: /* DSB */ | |
719 | case 5: /* DMB */ | |
720 | case 6: /* ISB */ | |
721 | /* We don't emulate caches so barriers are no-ops */ | |
722 | return; | |
723 | default: | |
724 | unallocated_encoding(s); | |
725 | return; | |
726 | } | |
727 | } | |
728 | ||
729 | /* C5.6.130 MSR (immediate) - move immediate to processor state field */ | |
730 | static void handle_msr_i(DisasContext *s, uint32_t insn, | |
731 | unsigned int op1, unsigned int op2, unsigned int crm) | |
732 | { | |
733 | unsupported_encoding(s, insn); | |
734 | } | |
735 | ||
736 | /* C5.6.204 SYS */ | |
737 | static void handle_sys(DisasContext *s, uint32_t insn, unsigned int l, | |
738 | unsigned int op1, unsigned int op2, | |
739 | unsigned int crn, unsigned int crm, unsigned int rt) | |
740 | { | |
741 | unsupported_encoding(s, insn); | |
742 | } | |
743 | ||
744 | /* C5.6.129 MRS - move from system register */ | |
745 | static void handle_mrs(DisasContext *s, uint32_t insn, unsigned int op0, | |
746 | unsigned int op1, unsigned int op2, | |
747 | unsigned int crn, unsigned int crm, unsigned int rt) | |
748 | { | |
749 | unsupported_encoding(s, insn); | |
750 | } | |
751 | ||
752 | /* C5.6.131 MSR (register) - move to system register */ | |
753 | static void handle_msr(DisasContext *s, uint32_t insn, unsigned int op0, | |
754 | unsigned int op1, unsigned int op2, | |
755 | unsigned int crn, unsigned int crm, unsigned int rt) | |
ad7ee8a2 CF |
756 | { |
757 | unsupported_encoding(s, insn); | |
758 | } | |
759 | ||
87462e0f CF |
760 | /* C3.2.4 System |
761 | * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0 | |
762 | * +---------------------+---+-----+-----+-------+-------+-----+------+ | |
763 | * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt | | |
764 | * +---------------------+---+-----+-----+-------+-------+-----+------+ | |
765 | */ | |
766 | static void disas_system(DisasContext *s, uint32_t insn) | |
767 | { | |
768 | unsigned int l, op0, op1, crn, crm, op2, rt; | |
769 | l = extract32(insn, 21, 1); | |
770 | op0 = extract32(insn, 19, 2); | |
771 | op1 = extract32(insn, 16, 3); | |
772 | crn = extract32(insn, 12, 4); | |
773 | crm = extract32(insn, 8, 4); | |
774 | op2 = extract32(insn, 5, 3); | |
775 | rt = extract32(insn, 0, 5); | |
776 | ||
777 | if (op0 == 0) { | |
778 | if (l || rt != 31) { | |
779 | unallocated_encoding(s); | |
780 | return; | |
781 | } | |
782 | switch (crn) { | |
783 | case 2: /* C5.6.68 HINT */ | |
784 | handle_hint(s, insn, op1, op2, crm); | |
785 | break; | |
786 | case 3: /* CLREX, DSB, DMB, ISB */ | |
787 | handle_sync(s, insn, op1, op2, crm); | |
788 | break; | |
789 | case 4: /* C5.6.130 MSR (immediate) */ | |
790 | handle_msr_i(s, insn, op1, op2, crm); | |
791 | break; | |
792 | default: | |
793 | unallocated_encoding(s); | |
794 | break; | |
795 | } | |
796 | return; | |
797 | } | |
798 | ||
799 | if (op0 == 1) { | |
800 | /* C5.6.204 SYS */ | |
801 | handle_sys(s, insn, l, op1, op2, crn, crm, rt); | |
802 | } else if (l) { /* op0 > 1 */ | |
803 | /* C5.6.129 MRS - move from system register */ | |
804 | handle_mrs(s, insn, op0, op1, op2, crn, crm, rt); | |
805 | } else { | |
806 | /* C5.6.131 MSR (register) - move to system register */ | |
807 | handle_msr(s, insn, op0, op1, op2, crn, crm, rt); | |
808 | } | |
809 | } | |
810 | ||
9618e809 AG |
811 | /* C3.2.3 Exception generation |
812 | * | |
813 | * 31 24 23 21 20 5 4 2 1 0 | |
814 | * +-----------------+-----+------------------------+-----+----+ | |
815 | * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL | | |
816 | * +-----------------------+------------------------+----------+ | |
817 | */ | |
ad7ee8a2 CF |
818 | static void disas_exc(DisasContext *s, uint32_t insn) |
819 | { | |
9618e809 AG |
820 | int opc = extract32(insn, 21, 3); |
821 | int op2_ll = extract32(insn, 0, 5); | |
822 | ||
823 | switch (opc) { | |
824 | case 0: | |
825 | /* SVC, HVC, SMC; since we don't support the Virtualization | |
826 | * or TrustZone extensions these all UNDEF except SVC. | |
827 | */ | |
828 | if (op2_ll != 1) { | |
829 | unallocated_encoding(s); | |
830 | break; | |
831 | } | |
832 | gen_exception_insn(s, 0, EXCP_SWI); | |
833 | break; | |
834 | case 1: | |
835 | if (op2_ll != 0) { | |
836 | unallocated_encoding(s); | |
837 | break; | |
838 | } | |
839 | /* BRK */ | |
840 | gen_exception_insn(s, 0, EXCP_BKPT); | |
841 | break; | |
842 | case 2: | |
843 | if (op2_ll != 0) { | |
844 | unallocated_encoding(s); | |
845 | break; | |
846 | } | |
847 | /* HLT */ | |
848 | unsupported_encoding(s, insn); | |
849 | break; | |
850 | case 5: | |
851 | if (op2_ll < 1 || op2_ll > 3) { | |
852 | unallocated_encoding(s); | |
853 | break; | |
854 | } | |
855 | /* DCPS1, DCPS2, DCPS3 */ | |
856 | unsupported_encoding(s, insn); | |
857 | break; | |
858 | default: | |
859 | unallocated_encoding(s); | |
860 | break; | |
861 | } | |
ad7ee8a2 CF |
862 | } |
863 | ||
b001c8c3 AG |
864 | /* C3.2.7 Unconditional branch (register) |
865 | * 31 25 24 21 20 16 15 10 9 5 4 0 | |
866 | * +---------------+-------+-------+-------+------+-------+ | |
867 | * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 | | |
868 | * +---------------+-------+-------+-------+------+-------+ | |
869 | */ | |
ad7ee8a2 CF |
870 | static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) |
871 | { | |
b001c8c3 AG |
872 | unsigned int opc, op2, op3, rn, op4; |
873 | ||
874 | opc = extract32(insn, 21, 4); | |
875 | op2 = extract32(insn, 16, 5); | |
876 | op3 = extract32(insn, 10, 6); | |
877 | rn = extract32(insn, 5, 5); | |
878 | op4 = extract32(insn, 0, 5); | |
879 | ||
880 | if (op4 != 0x0 || op3 != 0x0 || op2 != 0x1f) { | |
881 | unallocated_encoding(s); | |
882 | return; | |
883 | } | |
884 | ||
885 | switch (opc) { | |
886 | case 0: /* BR */ | |
887 | case 2: /* RET */ | |
888 | break; | |
889 | case 1: /* BLR */ | |
890 | tcg_gen_movi_i64(cpu_reg(s, 30), s->pc); | |
891 | break; | |
892 | case 4: /* ERET */ | |
893 | case 5: /* DRPS */ | |
894 | if (rn != 0x1f) { | |
895 | unallocated_encoding(s); | |
896 | } else { | |
897 | unsupported_encoding(s, insn); | |
898 | } | |
899 | return; | |
900 | default: | |
901 | unallocated_encoding(s); | |
902 | return; | |
903 | } | |
904 | ||
905 | tcg_gen_mov_i64(cpu_pc, cpu_reg(s, rn)); | |
906 | s->is_jmp = DISAS_JUMP; | |
ad7ee8a2 CF |
907 | } |
908 | ||
909 | /* C3.2 Branches, exception generating and system instructions */ | |
910 | static void disas_b_exc_sys(DisasContext *s, uint32_t insn) | |
911 | { | |
912 | switch (extract32(insn, 25, 7)) { | |
913 | case 0x0a: case 0x0b: | |
914 | case 0x4a: case 0x4b: /* Unconditional branch (immediate) */ | |
915 | disas_uncond_b_imm(s, insn); | |
916 | break; | |
917 | case 0x1a: case 0x5a: /* Compare & branch (immediate) */ | |
918 | disas_comp_b_imm(s, insn); | |
919 | break; | |
920 | case 0x1b: case 0x5b: /* Test & branch (immediate) */ | |
921 | disas_test_b_imm(s, insn); | |
922 | break; | |
923 | case 0x2a: /* Conditional branch (immediate) */ | |
924 | disas_cond_b_imm(s, insn); | |
925 | break; | |
926 | case 0x6a: /* Exception generation / System */ | |
927 | if (insn & (1 << 24)) { | |
928 | disas_system(s, insn); | |
929 | } else { | |
930 | disas_exc(s, insn); | |
931 | } | |
932 | break; | |
933 | case 0x6b: /* Unconditional branch (register) */ | |
934 | disas_uncond_b_reg(s, insn); | |
935 | break; | |
936 | default: | |
937 | unallocated_encoding(s); | |
938 | break; | |
939 | } | |
940 | } | |
941 | ||
942 | /* Load/store exclusive */ | |
943 | static void disas_ldst_excl(DisasContext *s, uint32_t insn) | |
944 | { | |
945 | unsupported_encoding(s, insn); | |
946 | } | |
947 | ||
948 | /* Load register (literal) */ | |
949 | static void disas_ld_lit(DisasContext *s, uint32_t insn) | |
950 | { | |
951 | unsupported_encoding(s, insn); | |
952 | } | |
953 | ||
4a08d475 PM |
954 | /* |
955 | * C5.6.80 LDNP (Load Pair - non-temporal hint) | |
956 | * C5.6.81 LDP (Load Pair - non vector) | |
957 | * C5.6.82 LDPSW (Load Pair Signed Word - non vector) | |
958 | * C5.6.176 STNP (Store Pair - non-temporal hint) | |
959 | * C5.6.177 STP (Store Pair - non vector) | |
960 | * C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint) | |
961 | * C6.3.165 LDP (Load Pair of SIMD&FP) | |
962 | * C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint) | |
963 | * C6.3.284 STP (Store Pair of SIMD&FP) | |
964 | * | |
965 | * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0 | |
966 | * +-----+-------+---+---+-------+---+-----------------------------+ | |
967 | * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt | | |
968 | * +-----+-------+---+---+-------+---+-------+-------+------+------+ | |
969 | * | |
970 | * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit | |
971 | * LDPSW 01 | |
972 | * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit | |
973 | * V: 0 -> GPR, 1 -> Vector | |
974 | * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index, | |
975 | * 10 -> signed offset, 11 -> pre-index | |
976 | * L: 0 -> Store 1 -> Load | |
977 | * | |
978 | * Rt, Rt2 = GPR or SIMD registers to be stored | |
979 | * Rn = general purpose register containing address | |
980 | * imm7 = signed offset (multiple of 4 or 8 depending on size) | |
981 | */ | |
ad7ee8a2 CF |
982 | static void disas_ldst_pair(DisasContext *s, uint32_t insn) |
983 | { | |
4a08d475 PM |
984 | int rt = extract32(insn, 0, 5); |
985 | int rn = extract32(insn, 5, 5); | |
986 | int rt2 = extract32(insn, 10, 5); | |
987 | int64_t offset = sextract32(insn, 15, 7); | |
988 | int index = extract32(insn, 23, 2); | |
989 | bool is_vector = extract32(insn, 26, 1); | |
990 | bool is_load = extract32(insn, 22, 1); | |
991 | int opc = extract32(insn, 30, 2); | |
992 | ||
993 | bool is_signed = false; | |
994 | bool postindex = false; | |
995 | bool wback = false; | |
996 | ||
997 | TCGv_i64 tcg_addr; /* calculated address */ | |
998 | int size; | |
999 | ||
1000 | if (opc == 3) { | |
1001 | unallocated_encoding(s); | |
1002 | return; | |
1003 | } | |
1004 | ||
1005 | if (is_vector) { | |
1006 | size = 2 + opc; | |
1007 | } else { | |
1008 | size = 2 + extract32(opc, 1, 1); | |
1009 | is_signed = extract32(opc, 0, 1); | |
1010 | if (!is_load && is_signed) { | |
1011 | unallocated_encoding(s); | |
1012 | return; | |
1013 | } | |
1014 | } | |
1015 | ||
1016 | switch (index) { | |
1017 | case 1: /* post-index */ | |
1018 | postindex = true; | |
1019 | wback = true; | |
1020 | break; | |
1021 | case 0: | |
1022 | /* signed offset with "non-temporal" hint. Since we don't emulate | |
1023 | * caches we don't care about hints to the cache system about | |
1024 | * data access patterns, and handle this identically to plain | |
1025 | * signed offset. | |
1026 | */ | |
1027 | if (is_signed) { | |
1028 | /* There is no non-temporal-hint version of LDPSW */ | |
1029 | unallocated_encoding(s); | |
1030 | return; | |
1031 | } | |
1032 | postindex = false; | |
1033 | break; | |
1034 | case 2: /* signed offset, rn not updated */ | |
1035 | postindex = false; | |
1036 | break; | |
1037 | case 3: /* pre-index */ | |
1038 | postindex = false; | |
1039 | wback = true; | |
1040 | break; | |
1041 | } | |
1042 | ||
1043 | offset <<= size; | |
1044 | ||
1045 | if (rn == 31) { | |
1046 | gen_check_sp_alignment(s); | |
1047 | } | |
1048 | ||
1049 | tcg_addr = read_cpu_reg_sp(s, rn, 1); | |
1050 | ||
1051 | if (!postindex) { | |
1052 | tcg_gen_addi_i64(tcg_addr, tcg_addr, offset); | |
1053 | } | |
1054 | ||
1055 | if (is_vector) { | |
1056 | if (is_load) { | |
1057 | do_fp_ld(s, rt, tcg_addr, size); | |
1058 | } else { | |
1059 | do_fp_st(s, rt, tcg_addr, size); | |
1060 | } | |
1061 | } else { | |
1062 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | |
1063 | if (is_load) { | |
1064 | do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false); | |
1065 | } else { | |
1066 | do_gpr_st(s, tcg_rt, tcg_addr, size); | |
1067 | } | |
1068 | } | |
1069 | tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size); | |
1070 | if (is_vector) { | |
1071 | if (is_load) { | |
1072 | do_fp_ld(s, rt2, tcg_addr, size); | |
1073 | } else { | |
1074 | do_fp_st(s, rt2, tcg_addr, size); | |
1075 | } | |
1076 | } else { | |
1077 | TCGv_i64 tcg_rt2 = cpu_reg(s, rt2); | |
1078 | if (is_load) { | |
1079 | do_gpr_ld(s, tcg_rt2, tcg_addr, size, is_signed, false); | |
1080 | } else { | |
1081 | do_gpr_st(s, tcg_rt2, tcg_addr, size); | |
1082 | } | |
1083 | } | |
1084 | ||
1085 | if (wback) { | |
1086 | if (postindex) { | |
1087 | tcg_gen_addi_i64(tcg_addr, tcg_addr, offset - (1 << size)); | |
1088 | } else { | |
1089 | tcg_gen_subi_i64(tcg_addr, tcg_addr, 1 << size); | |
1090 | } | |
1091 | tcg_gen_mov_i64(cpu_reg_sp(s, rn), tcg_addr); | |
1092 | } | |
ad7ee8a2 CF |
1093 | } |
1094 | ||
a5e94a9d AB |
1095 | /* |
1096 | * C3.3.8 Load/store (immediate post-indexed) | |
1097 | * C3.3.9 Load/store (immediate pre-indexed) | |
1098 | * C3.3.12 Load/store (unscaled immediate) | |
1099 | * | |
1100 | * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0 | |
1101 | * +----+-------+---+-----+-----+---+--------+-----+------+------+ | |
1102 | * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt | | |
1103 | * +----+-------+---+-----+-----+---+--------+-----+------+------+ | |
1104 | * | |
1105 | * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback) | |
1106 | * V = 0 -> non-vector | |
1107 | * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit | |
1108 | * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 | |
1109 | */ | |
1110 | static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn) | |
1111 | { | |
1112 | int rt = extract32(insn, 0, 5); | |
1113 | int rn = extract32(insn, 5, 5); | |
1114 | int imm9 = sextract32(insn, 12, 9); | |
1115 | int opc = extract32(insn, 22, 2); | |
1116 | int size = extract32(insn, 30, 2); | |
1117 | int idx = extract32(insn, 10, 2); | |
1118 | bool is_signed = false; | |
1119 | bool is_store = false; | |
1120 | bool is_extended = false; | |
1121 | bool is_vector = extract32(insn, 26, 1); | |
1122 | bool post_index; | |
1123 | bool writeback; | |
1124 | ||
1125 | TCGv_i64 tcg_addr; | |
1126 | ||
1127 | if (is_vector) { | |
1128 | size |= (opc & 2) << 1; | |
1129 | if (size > 4) { | |
1130 | unallocated_encoding(s); | |
1131 | return; | |
1132 | } | |
1133 | is_store = ((opc & 1) == 0); | |
1134 | } else { | |
1135 | if (size == 3 && opc == 2) { | |
1136 | /* PRFM - prefetch */ | |
1137 | return; | |
1138 | } | |
1139 | if (opc == 3 && size > 1) { | |
1140 | unallocated_encoding(s); | |
1141 | return; | |
1142 | } | |
1143 | is_store = (opc == 0); | |
1144 | is_signed = opc & (1<<1); | |
1145 | is_extended = (size < 3) && (opc & 1); | |
1146 | } | |
1147 | ||
1148 | switch (idx) { | |
1149 | case 0: | |
1150 | post_index = false; | |
1151 | writeback = false; | |
1152 | break; | |
1153 | case 1: | |
1154 | post_index = true; | |
1155 | writeback = true; | |
1156 | break; | |
1157 | case 3: | |
1158 | post_index = false; | |
1159 | writeback = true; | |
1160 | break; | |
1161 | case 2: | |
1162 | g_assert(false); | |
1163 | break; | |
1164 | } | |
1165 | ||
1166 | if (rn == 31) { | |
1167 | gen_check_sp_alignment(s); | |
1168 | } | |
1169 | tcg_addr = read_cpu_reg_sp(s, rn, 1); | |
1170 | ||
1171 | if (!post_index) { | |
1172 | tcg_gen_addi_i64(tcg_addr, tcg_addr, imm9); | |
1173 | } | |
1174 | ||
1175 | if (is_vector) { | |
1176 | if (is_store) { | |
1177 | do_fp_st(s, rt, tcg_addr, size); | |
1178 | } else { | |
1179 | do_fp_ld(s, rt, tcg_addr, size); | |
1180 | } | |
1181 | } else { | |
1182 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | |
1183 | if (is_store) { | |
1184 | do_gpr_st(s, tcg_rt, tcg_addr, size); | |
1185 | } else { | |
1186 | do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, is_extended); | |
1187 | } | |
1188 | } | |
1189 | ||
1190 | if (writeback) { | |
1191 | TCGv_i64 tcg_rn = cpu_reg_sp(s, rn); | |
1192 | if (post_index) { | |
1193 | tcg_gen_addi_i64(tcg_addr, tcg_addr, imm9); | |
1194 | } | |
1195 | tcg_gen_mov_i64(tcg_rn, tcg_addr); | |
1196 | } | |
1197 | } | |
1198 | ||
229b7a05 AB |
1199 | /* |
1200 | * C3.3.10 Load/store (register offset) | |
1201 | * | |
1202 | * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0 | |
1203 | * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+ | |
1204 | * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt | | |
1205 | * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+ | |
1206 | * | |
1207 | * For non-vector: | |
1208 | * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit | |
1209 | * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 | |
1210 | * For vector: | |
1211 | * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated | |
1212 | * opc<0>: 0 -> store, 1 -> load | |
1213 | * V: 1 -> vector/simd | |
1214 | * opt: extend encoding (see DecodeRegExtend) | |
1215 | * S: if S=1 then scale (essentially index by sizeof(size)) | |
1216 | * Rt: register to transfer into/out of | |
1217 | * Rn: address register or SP for base | |
1218 | * Rm: offset register or ZR for offset | |
1219 | */ | |
1220 | static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn) | |
1221 | { | |
1222 | int rt = extract32(insn, 0, 5); | |
1223 | int rn = extract32(insn, 5, 5); | |
1224 | int shift = extract32(insn, 12, 1); | |
1225 | int rm = extract32(insn, 16, 5); | |
1226 | int opc = extract32(insn, 22, 2); | |
1227 | int opt = extract32(insn, 13, 3); | |
1228 | int size = extract32(insn, 30, 2); | |
1229 | bool is_signed = false; | |
1230 | bool is_store = false; | |
1231 | bool is_extended = false; | |
1232 | bool is_vector = extract32(insn, 26, 1); | |
1233 | ||
1234 | TCGv_i64 tcg_rm; | |
1235 | TCGv_i64 tcg_addr; | |
1236 | ||
1237 | if (extract32(opt, 1, 1) == 0) { | |
1238 | unallocated_encoding(s); | |
1239 | return; | |
1240 | } | |
1241 | ||
1242 | if (is_vector) { | |
1243 | size |= (opc & 2) << 1; | |
1244 | if (size > 4) { | |
1245 | unallocated_encoding(s); | |
1246 | return; | |
1247 | } | |
1248 | is_store = !extract32(opc, 0, 1); | |
1249 | } else { | |
1250 | if (size == 3 && opc == 2) { | |
1251 | /* PRFM - prefetch */ | |
1252 | return; | |
1253 | } | |
1254 | if (opc == 3 && size > 1) { | |
1255 | unallocated_encoding(s); | |
1256 | return; | |
1257 | } | |
1258 | is_store = (opc == 0); | |
1259 | is_signed = extract32(opc, 1, 1); | |
1260 | is_extended = (size < 3) && extract32(opc, 0, 1); | |
1261 | } | |
1262 | ||
1263 | if (rn == 31) { | |
1264 | gen_check_sp_alignment(s); | |
1265 | } | |
1266 | tcg_addr = read_cpu_reg_sp(s, rn, 1); | |
1267 | ||
1268 | tcg_rm = read_cpu_reg(s, rm, 1); | |
1269 | ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0); | |
1270 | ||
1271 | tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_rm); | |
1272 | ||
1273 | if (is_vector) { | |
1274 | if (is_store) { | |
1275 | do_fp_st(s, rt, tcg_addr, size); | |
1276 | } else { | |
1277 | do_fp_ld(s, rt, tcg_addr, size); | |
1278 | } | |
1279 | } else { | |
1280 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | |
1281 | if (is_store) { | |
1282 | do_gpr_st(s, tcg_rt, tcg_addr, size); | |
1283 | } else { | |
1284 | do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, is_extended); | |
1285 | } | |
1286 | } | |
1287 | } | |
1288 | ||
d5612f10 AB |
1289 | /* |
1290 | * C3.3.13 Load/store (unsigned immediate) | |
1291 | * | |
1292 | * 31 30 29 27 26 25 24 23 22 21 10 9 5 | |
1293 | * +----+-------+---+-----+-----+------------+-------+------+ | |
1294 | * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt | | |
1295 | * +----+-------+---+-----+-----+------------+-------+------+ | |
1296 | * | |
1297 | * For non-vector: | |
1298 | * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit | |
1299 | * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 | |
1300 | * For vector: | |
1301 | * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated | |
1302 | * opc<0>: 0 -> store, 1 -> load | |
1303 | * Rn: base address register (inc SP) | |
1304 | * Rt: target register | |
1305 | */ | |
1306 | static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn) | |
1307 | { | |
1308 | int rt = extract32(insn, 0, 5); | |
1309 | int rn = extract32(insn, 5, 5); | |
1310 | unsigned int imm12 = extract32(insn, 10, 12); | |
1311 | bool is_vector = extract32(insn, 26, 1); | |
1312 | int size = extract32(insn, 30, 2); | |
1313 | int opc = extract32(insn, 22, 2); | |
1314 | unsigned int offset; | |
1315 | ||
1316 | TCGv_i64 tcg_addr; | |
1317 | ||
1318 | bool is_store; | |
1319 | bool is_signed = false; | |
1320 | bool is_extended = false; | |
1321 | ||
1322 | if (is_vector) { | |
1323 | size |= (opc & 2) << 1; | |
1324 | if (size > 4) { | |
1325 | unallocated_encoding(s); | |
1326 | return; | |
1327 | } | |
1328 | is_store = !extract32(opc, 0, 1); | |
1329 | } else { | |
1330 | if (size == 3 && opc == 2) { | |
1331 | /* PRFM - prefetch */ | |
1332 | return; | |
1333 | } | |
1334 | if (opc == 3 && size > 1) { | |
1335 | unallocated_encoding(s); | |
1336 | return; | |
1337 | } | |
1338 | is_store = (opc == 0); | |
1339 | is_signed = extract32(opc, 1, 1); | |
1340 | is_extended = (size < 3) && extract32(opc, 0, 1); | |
1341 | } | |
1342 | ||
1343 | if (rn == 31) { | |
1344 | gen_check_sp_alignment(s); | |
1345 | } | |
1346 | tcg_addr = read_cpu_reg_sp(s, rn, 1); | |
1347 | offset = imm12 << size; | |
1348 | tcg_gen_addi_i64(tcg_addr, tcg_addr, offset); | |
1349 | ||
1350 | if (is_vector) { | |
1351 | if (is_store) { | |
1352 | do_fp_st(s, rt, tcg_addr, size); | |
1353 | } else { | |
1354 | do_fp_ld(s, rt, tcg_addr, size); | |
1355 | } | |
1356 | } else { | |
1357 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | |
1358 | if (is_store) { | |
1359 | do_gpr_st(s, tcg_rt, tcg_addr, size); | |
1360 | } else { | |
1361 | do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, is_extended); | |
1362 | } | |
1363 | } | |
1364 | } | |
1365 | ||
a5e94a9d AB |
1366 | /* Load/store register (immediate forms) */ |
1367 | static void disas_ldst_reg_imm(DisasContext *s, uint32_t insn) | |
1368 | { | |
1369 | switch (extract32(insn, 10, 2)) { | |
1370 | case 0: case 1: case 3: | |
1371 | /* Load/store register (unscaled immediate) */ | |
1372 | /* Load/store immediate pre/post-indexed */ | |
1373 | disas_ldst_reg_imm9(s, insn); | |
1374 | break; | |
1375 | case 2: | |
1376 | /* Load/store register unprivileged */ | |
1377 | unsupported_encoding(s, insn); | |
1378 | break; | |
1379 | default: | |
1380 | unallocated_encoding(s); | |
1381 | break; | |
1382 | } | |
1383 | } | |
1384 | ||
ad7ee8a2 CF |
1385 | /* Load/store register (all forms) */ |
1386 | static void disas_ldst_reg(DisasContext *s, uint32_t insn) | |
1387 | { | |
d5612f10 AB |
1388 | switch (extract32(insn, 24, 2)) { |
1389 | case 0: | |
229b7a05 AB |
1390 | if (extract32(insn, 21, 1) == 1 && extract32(insn, 10, 2) == 2) { |
1391 | disas_ldst_reg_roffset(s, insn); | |
1392 | } else { | |
a5e94a9d | 1393 | disas_ldst_reg_imm(s, insn); |
229b7a05 | 1394 | } |
d5612f10 AB |
1395 | break; |
1396 | case 1: | |
1397 | disas_ldst_reg_unsigned_imm(s, insn); | |
1398 | break; | |
1399 | default: | |
1400 | unallocated_encoding(s); | |
1401 | break; | |
1402 | } | |
ad7ee8a2 CF |
1403 | } |
1404 | ||
1405 | /* AdvSIMD load/store multiple structures */ | |
1406 | static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) | |
1407 | { | |
1408 | unsupported_encoding(s, insn); | |
1409 | } | |
1410 | ||
1411 | /* AdvSIMD load/store single structure */ | |
1412 | static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) | |
1413 | { | |
1414 | unsupported_encoding(s, insn); | |
1415 | } | |
1416 | ||
1417 | /* C3.3 Loads and stores */ | |
1418 | static void disas_ldst(DisasContext *s, uint32_t insn) | |
1419 | { | |
1420 | switch (extract32(insn, 24, 6)) { | |
1421 | case 0x08: /* Load/store exclusive */ | |
1422 | disas_ldst_excl(s, insn); | |
1423 | break; | |
1424 | case 0x18: case 0x1c: /* Load register (literal) */ | |
1425 | disas_ld_lit(s, insn); | |
1426 | break; | |
1427 | case 0x28: case 0x29: | |
1428 | case 0x2c: case 0x2d: /* Load/store pair (all forms) */ | |
1429 | disas_ldst_pair(s, insn); | |
1430 | break; | |
1431 | case 0x38: case 0x39: | |
1432 | case 0x3c: case 0x3d: /* Load/store register (all forms) */ | |
1433 | disas_ldst_reg(s, insn); | |
1434 | break; | |
1435 | case 0x0c: /* AdvSIMD load/store multiple structures */ | |
1436 | disas_ldst_multiple_struct(s, insn); | |
1437 | break; | |
1438 | case 0x0d: /* AdvSIMD load/store single structure */ | |
1439 | disas_ldst_single_struct(s, insn); | |
1440 | break; | |
1441 | default: | |
1442 | unallocated_encoding(s); | |
1443 | break; | |
1444 | } | |
1445 | } | |
1446 | ||
15bfe8b6 AG |
1447 | /* C3.4.6 PC-rel. addressing |
1448 | * 31 30 29 28 24 23 5 4 0 | |
1449 | * +----+-------+-----------+-------------------+------+ | |
1450 | * | op | immlo | 1 0 0 0 0 | immhi | Rd | | |
1451 | * +----+-------+-----------+-------------------+------+ | |
1452 | */ | |
ad7ee8a2 CF |
1453 | static void disas_pc_rel_adr(DisasContext *s, uint32_t insn) |
1454 | { | |
15bfe8b6 AG |
1455 | unsigned int page, rd; |
1456 | uint64_t base; | |
1457 | int64_t offset; | |
1458 | ||
1459 | page = extract32(insn, 31, 1); | |
1460 | /* SignExtend(immhi:immlo) -> offset */ | |
1461 | offset = ((int64_t)sextract32(insn, 5, 19) << 2) | extract32(insn, 29, 2); | |
1462 | rd = extract32(insn, 0, 5); | |
1463 | base = s->pc - 4; | |
1464 | ||
1465 | if (page) { | |
1466 | /* ADRP (page based) */ | |
1467 | base &= ~0xfff; | |
1468 | offset <<= 12; | |
1469 | } | |
1470 | ||
1471 | tcg_gen_movi_i64(cpu_reg(s, rd), base + offset); | |
ad7ee8a2 CF |
1472 | } |
1473 | ||
b0ff21b4 AB |
1474 | /* |
1475 | * C3.4.1 Add/subtract (immediate) | |
1476 | * | |
1477 | * 31 30 29 28 24 23 22 21 10 9 5 4 0 | |
1478 | * +--+--+--+-----------+-----+-------------+-----+-----+ | |
1479 | * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd | | |
1480 | * +--+--+--+-----------+-----+-------------+-----+-----+ | |
1481 | * | |
1482 | * sf: 0 -> 32bit, 1 -> 64bit | |
1483 | * op: 0 -> add , 1 -> sub | |
1484 | * S: 1 -> set flags | |
1485 | * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12 | |
1486 | */ | |
ad7ee8a2 CF |
1487 | static void disas_add_sub_imm(DisasContext *s, uint32_t insn) |
1488 | { | |
b0ff21b4 AB |
1489 | int rd = extract32(insn, 0, 5); |
1490 | int rn = extract32(insn, 5, 5); | |
1491 | uint64_t imm = extract32(insn, 10, 12); | |
1492 | int shift = extract32(insn, 22, 2); | |
1493 | bool setflags = extract32(insn, 29, 1); | |
1494 | bool sub_op = extract32(insn, 30, 1); | |
1495 | bool is_64bit = extract32(insn, 31, 1); | |
1496 | ||
1497 | TCGv_i64 tcg_rn = cpu_reg_sp(s, rn); | |
1498 | TCGv_i64 tcg_rd = setflags ? cpu_reg(s, rd) : cpu_reg_sp(s, rd); | |
1499 | TCGv_i64 tcg_result; | |
1500 | ||
1501 | switch (shift) { | |
1502 | case 0x0: | |
1503 | break; | |
1504 | case 0x1: | |
1505 | imm <<= 12; | |
1506 | break; | |
1507 | default: | |
1508 | unallocated_encoding(s); | |
1509 | return; | |
1510 | } | |
1511 | ||
1512 | tcg_result = tcg_temp_new_i64(); | |
1513 | if (!setflags) { | |
1514 | if (sub_op) { | |
1515 | tcg_gen_subi_i64(tcg_result, tcg_rn, imm); | |
1516 | } else { | |
1517 | tcg_gen_addi_i64(tcg_result, tcg_rn, imm); | |
1518 | } | |
1519 | } else { | |
1520 | TCGv_i64 tcg_imm = tcg_const_i64(imm); | |
1521 | if (sub_op) { | |
1522 | gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); | |
1523 | } else { | |
1524 | gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); | |
1525 | } | |
1526 | tcg_temp_free_i64(tcg_imm); | |
1527 | } | |
1528 | ||
1529 | if (is_64bit) { | |
1530 | tcg_gen_mov_i64(tcg_rd, tcg_result); | |
1531 | } else { | |
1532 | tcg_gen_ext32u_i64(tcg_rd, tcg_result); | |
1533 | } | |
1534 | ||
1535 | tcg_temp_free_i64(tcg_result); | |
ad7ee8a2 CF |
1536 | } |
1537 | ||
71b46089 AG |
1538 | /* The input should be a value in the bottom e bits (with higher |
1539 | * bits zero); returns that value replicated into every element | |
1540 | * of size e in a 64 bit integer. | |
1541 | */ | |
1542 | static uint64_t bitfield_replicate(uint64_t mask, unsigned int e) | |
1543 | { | |
1544 | assert(e != 0); | |
1545 | while (e < 64) { | |
1546 | mask |= mask << e; | |
1547 | e *= 2; | |
1548 | } | |
1549 | return mask; | |
1550 | } | |
1551 | ||
1552 | /* Return a value with the bottom len bits set (where 0 < len <= 64) */ | |
1553 | static inline uint64_t bitmask64(unsigned int length) | |
1554 | { | |
1555 | assert(length > 0 && length <= 64); | |
1556 | return ~0ULL >> (64 - length); | |
1557 | } | |
1558 | ||
1559 | /* Simplified variant of pseudocode DecodeBitMasks() for the case where we | |
1560 | * only require the wmask. Returns false if the imms/immr/immn are a reserved | |
1561 | * value (ie should cause a guest UNDEF exception), and true if they are | |
1562 | * valid, in which case the decoded bit pattern is written to result. | |
1563 | */ | |
1564 | static bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, | |
1565 | unsigned int imms, unsigned int immr) | |
1566 | { | |
1567 | uint64_t mask; | |
1568 | unsigned e, levels, s, r; | |
1569 | int len; | |
1570 | ||
1571 | assert(immn < 2 && imms < 64 && immr < 64); | |
1572 | ||
1573 | /* The bit patterns we create here are 64 bit patterns which | |
1574 | * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or | |
1575 | * 64 bits each. Each element contains the same value: a run | |
1576 | * of between 1 and e-1 non-zero bits, rotated within the | |
1577 | * element by between 0 and e-1 bits. | |
1578 | * | |
1579 | * The element size and run length are encoded into immn (1 bit) | |
1580 | * and imms (6 bits) as follows: | |
1581 | * 64 bit elements: immn = 1, imms = <length of run - 1> | |
1582 | * 32 bit elements: immn = 0, imms = 0 : <length of run - 1> | |
1583 | * 16 bit elements: immn = 0, imms = 10 : <length of run - 1> | |
1584 | * 8 bit elements: immn = 0, imms = 110 : <length of run - 1> | |
1585 | * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1> | |
1586 | * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1> | |
1587 | * Notice that immn = 0, imms = 11111x is the only combination | |
1588 | * not covered by one of the above options; this is reserved. | |
1589 | * Further, <length of run - 1> all-ones is a reserved pattern. | |
1590 | * | |
1591 | * In all cases the rotation is by immr % e (and immr is 6 bits). | |
1592 | */ | |
1593 | ||
1594 | /* First determine the element size */ | |
1595 | len = 31 - clz32((immn << 6) | (~imms & 0x3f)); | |
1596 | if (len < 1) { | |
1597 | /* This is the immn == 0, imms == 0x11111x case */ | |
1598 | return false; | |
1599 | } | |
1600 | e = 1 << len; | |
1601 | ||
1602 | levels = e - 1; | |
1603 | s = imms & levels; | |
1604 | r = immr & levels; | |
1605 | ||
1606 | if (s == levels) { | |
1607 | /* <length of run - 1> mustn't be all-ones. */ | |
1608 | return false; | |
1609 | } | |
1610 | ||
1611 | /* Create the value of one element: s+1 set bits rotated | |
1612 | * by r within the element (which is e bits wide)... | |
1613 | */ | |
1614 | mask = bitmask64(s + 1); | |
1615 | mask = (mask >> r) | (mask << (e - r)); | |
1616 | /* ...then replicate the element over the whole 64 bit value */ | |
1617 | mask = bitfield_replicate(mask, e); | |
1618 | *result = mask; | |
1619 | return true; | |
1620 | } | |
1621 | ||
1622 | /* C3.4.4 Logical (immediate) | |
1623 | * 31 30 29 28 23 22 21 16 15 10 9 5 4 0 | |
1624 | * +----+-----+-------------+---+------+------+------+------+ | |
1625 | * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd | | |
1626 | * +----+-----+-------------+---+------+------+------+------+ | |
1627 | */ | |
ad7ee8a2 CF |
1628 | static void disas_logic_imm(DisasContext *s, uint32_t insn) |
1629 | { | |
71b46089 AG |
1630 | unsigned int sf, opc, is_n, immr, imms, rn, rd; |
1631 | TCGv_i64 tcg_rd, tcg_rn; | |
1632 | uint64_t wmask; | |
1633 | bool is_and = false; | |
1634 | ||
1635 | sf = extract32(insn, 31, 1); | |
1636 | opc = extract32(insn, 29, 2); | |
1637 | is_n = extract32(insn, 22, 1); | |
1638 | immr = extract32(insn, 16, 6); | |
1639 | imms = extract32(insn, 10, 6); | |
1640 | rn = extract32(insn, 5, 5); | |
1641 | rd = extract32(insn, 0, 5); | |
1642 | ||
1643 | if (!sf && is_n) { | |
1644 | unallocated_encoding(s); | |
1645 | return; | |
1646 | } | |
1647 | ||
1648 | if (opc == 0x3) { /* ANDS */ | |
1649 | tcg_rd = cpu_reg(s, rd); | |
1650 | } else { | |
1651 | tcg_rd = cpu_reg_sp(s, rd); | |
1652 | } | |
1653 | tcg_rn = cpu_reg(s, rn); | |
1654 | ||
1655 | if (!logic_imm_decode_wmask(&wmask, is_n, imms, immr)) { | |
1656 | /* some immediate field values are reserved */ | |
1657 | unallocated_encoding(s); | |
1658 | return; | |
1659 | } | |
1660 | ||
1661 | if (!sf) { | |
1662 | wmask &= 0xffffffff; | |
1663 | } | |
1664 | ||
1665 | switch (opc) { | |
1666 | case 0x3: /* ANDS */ | |
1667 | case 0x0: /* AND */ | |
1668 | tcg_gen_andi_i64(tcg_rd, tcg_rn, wmask); | |
1669 | is_and = true; | |
1670 | break; | |
1671 | case 0x1: /* ORR */ | |
1672 | tcg_gen_ori_i64(tcg_rd, tcg_rn, wmask); | |
1673 | break; | |
1674 | case 0x2: /* EOR */ | |
1675 | tcg_gen_xori_i64(tcg_rd, tcg_rn, wmask); | |
1676 | break; | |
1677 | default: | |
1678 | assert(FALSE); /* must handle all above */ | |
1679 | break; | |
1680 | } | |
1681 | ||
1682 | if (!sf && !is_and) { | |
1683 | /* zero extend final result; we know we can skip this for AND | |
1684 | * since the immediate had the high 32 bits clear. | |
1685 | */ | |
1686 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
1687 | } | |
1688 | ||
1689 | if (opc == 3) { /* ANDS */ | |
1690 | gen_logic_CC(sf, tcg_rd); | |
1691 | } | |
ad7ee8a2 CF |
1692 | } |
1693 | ||
ed6ec679 AB |
1694 | /* |
1695 | * C3.4.5 Move wide (immediate) | |
1696 | * | |
1697 | * 31 30 29 28 23 22 21 20 5 4 0 | |
1698 | * +--+-----+-------------+-----+----------------+------+ | |
1699 | * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd | | |
1700 | * +--+-----+-------------+-----+----------------+------+ | |
1701 | * | |
1702 | * sf: 0 -> 32 bit, 1 -> 64 bit | |
1703 | * opc: 00 -> N, 10 -> Z, 11 -> K | |
1704 | * hw: shift/16 (0,16, and sf only 32, 48) | |
1705 | */ | |
ad7ee8a2 CF |
1706 | static void disas_movw_imm(DisasContext *s, uint32_t insn) |
1707 | { | |
ed6ec679 AB |
1708 | int rd = extract32(insn, 0, 5); |
1709 | uint64_t imm = extract32(insn, 5, 16); | |
1710 | int sf = extract32(insn, 31, 1); | |
1711 | int opc = extract32(insn, 29, 2); | |
1712 | int pos = extract32(insn, 21, 2) << 4; | |
1713 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
1714 | TCGv_i64 tcg_imm; | |
1715 | ||
1716 | if (!sf && (pos >= 32)) { | |
1717 | unallocated_encoding(s); | |
1718 | return; | |
1719 | } | |
1720 | ||
1721 | switch (opc) { | |
1722 | case 0: /* MOVN */ | |
1723 | case 2: /* MOVZ */ | |
1724 | imm <<= pos; | |
1725 | if (opc == 0) { | |
1726 | imm = ~imm; | |
1727 | } | |
1728 | if (!sf) { | |
1729 | imm &= 0xffffffffu; | |
1730 | } | |
1731 | tcg_gen_movi_i64(tcg_rd, imm); | |
1732 | break; | |
1733 | case 3: /* MOVK */ | |
1734 | tcg_imm = tcg_const_i64(imm); | |
1735 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_imm, pos, 16); | |
1736 | tcg_temp_free_i64(tcg_imm); | |
1737 | if (!sf) { | |
1738 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
1739 | } | |
1740 | break; | |
1741 | default: | |
1742 | unallocated_encoding(s); | |
1743 | break; | |
1744 | } | |
ad7ee8a2 CF |
1745 | } |
1746 | ||
88077742 CF |
1747 | /* C3.4.2 Bitfield |
1748 | * 31 30 29 28 23 22 21 16 15 10 9 5 4 0 | |
1749 | * +----+-----+-------------+---+------+------+------+------+ | |
1750 | * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd | | |
1751 | * +----+-----+-------------+---+------+------+------+------+ | |
1752 | */ | |
ad7ee8a2 CF |
1753 | static void disas_bitfield(DisasContext *s, uint32_t insn) |
1754 | { | |
88077742 CF |
1755 | unsigned int sf, n, opc, ri, si, rn, rd, bitsize, pos, len; |
1756 | TCGv_i64 tcg_rd, tcg_tmp; | |
1757 | ||
1758 | sf = extract32(insn, 31, 1); | |
1759 | opc = extract32(insn, 29, 2); | |
1760 | n = extract32(insn, 22, 1); | |
1761 | ri = extract32(insn, 16, 6); | |
1762 | si = extract32(insn, 10, 6); | |
1763 | rn = extract32(insn, 5, 5); | |
1764 | rd = extract32(insn, 0, 5); | |
1765 | bitsize = sf ? 64 : 32; | |
1766 | ||
1767 | if (sf != n || ri >= bitsize || si >= bitsize || opc > 2) { | |
1768 | unallocated_encoding(s); | |
1769 | return; | |
1770 | } | |
1771 | ||
1772 | tcg_rd = cpu_reg(s, rd); | |
1773 | tcg_tmp = read_cpu_reg(s, rn, sf); | |
1774 | ||
1775 | /* OPTME: probably worth recognizing common cases of ext{8,16,32}{u,s} */ | |
1776 | ||
1777 | if (opc != 1) { /* SBFM or UBFM */ | |
1778 | tcg_gen_movi_i64(tcg_rd, 0); | |
1779 | } | |
1780 | ||
1781 | /* do the bit move operation */ | |
1782 | if (si >= ri) { | |
1783 | /* Wd<s-r:0> = Wn<s:r> */ | |
1784 | tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri); | |
1785 | pos = 0; | |
1786 | len = (si - ri) + 1; | |
1787 | } else { | |
1788 | /* Wd<32+s-r,32-r> = Wn<s:0> */ | |
1789 | pos = bitsize - ri; | |
1790 | len = si + 1; | |
1791 | } | |
1792 | ||
1793 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len); | |
1794 | ||
1795 | if (opc == 0) { /* SBFM - sign extend the destination field */ | |
1796 | tcg_gen_shli_i64(tcg_rd, tcg_rd, 64 - (pos + len)); | |
1797 | tcg_gen_sari_i64(tcg_rd, tcg_rd, 64 - (pos + len)); | |
1798 | } | |
1799 | ||
1800 | if (!sf) { /* zero extend final result */ | |
1801 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
1802 | } | |
ad7ee8a2 CF |
1803 | } |
1804 | ||
e801de93 AG |
1805 | /* C3.4.3 Extract |
1806 | * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0 | |
1807 | * +----+------+-------------+---+----+------+--------+------+------+ | |
1808 | * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd | | |
1809 | * +----+------+-------------+---+----+------+--------+------+------+ | |
1810 | */ | |
ad7ee8a2 CF |
1811 | static void disas_extract(DisasContext *s, uint32_t insn) |
1812 | { | |
e801de93 AG |
1813 | unsigned int sf, n, rm, imm, rn, rd, bitsize, op21, op0; |
1814 | ||
1815 | sf = extract32(insn, 31, 1); | |
1816 | n = extract32(insn, 22, 1); | |
1817 | rm = extract32(insn, 16, 5); | |
1818 | imm = extract32(insn, 10, 6); | |
1819 | rn = extract32(insn, 5, 5); | |
1820 | rd = extract32(insn, 0, 5); | |
1821 | op21 = extract32(insn, 29, 2); | |
1822 | op0 = extract32(insn, 21, 1); | |
1823 | bitsize = sf ? 64 : 32; | |
1824 | ||
1825 | if (sf != n || op21 || op0 || imm >= bitsize) { | |
1826 | unallocated_encoding(s); | |
1827 | } else { | |
1828 | TCGv_i64 tcg_rd, tcg_rm, tcg_rn; | |
1829 | ||
1830 | tcg_rd = cpu_reg(s, rd); | |
1831 | ||
1832 | if (imm) { | |
1833 | /* OPTME: we can special case rm==rn as a rotate */ | |
1834 | tcg_rm = read_cpu_reg(s, rm, sf); | |
1835 | tcg_rn = read_cpu_reg(s, rn, sf); | |
1836 | tcg_gen_shri_i64(tcg_rm, tcg_rm, imm); | |
1837 | tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm); | |
1838 | tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn); | |
1839 | if (!sf) { | |
1840 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
1841 | } | |
1842 | } else { | |
1843 | /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts, | |
1844 | * so an extract from bit 0 is a special case. | |
1845 | */ | |
1846 | if (sf) { | |
1847 | tcg_gen_mov_i64(tcg_rd, cpu_reg(s, rm)); | |
1848 | } else { | |
1849 | tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm)); | |
1850 | } | |
1851 | } | |
1852 | ||
1853 | } | |
ad7ee8a2 CF |
1854 | } |
1855 | ||
1856 | /* C3.4 Data processing - immediate */ | |
1857 | static void disas_data_proc_imm(DisasContext *s, uint32_t insn) | |
1858 | { | |
1859 | switch (extract32(insn, 23, 6)) { | |
1860 | case 0x20: case 0x21: /* PC-rel. addressing */ | |
1861 | disas_pc_rel_adr(s, insn); | |
1862 | break; | |
1863 | case 0x22: case 0x23: /* Add/subtract (immediate) */ | |
1864 | disas_add_sub_imm(s, insn); | |
1865 | break; | |
1866 | case 0x24: /* Logical (immediate) */ | |
1867 | disas_logic_imm(s, insn); | |
1868 | break; | |
1869 | case 0x25: /* Move wide (immediate) */ | |
1870 | disas_movw_imm(s, insn); | |
1871 | break; | |
1872 | case 0x26: /* Bitfield */ | |
1873 | disas_bitfield(s, insn); | |
1874 | break; | |
1875 | case 0x27: /* Extract */ | |
1876 | disas_extract(s, insn); | |
1877 | break; | |
1878 | default: | |
1879 | unallocated_encoding(s); | |
1880 | break; | |
1881 | } | |
1882 | } | |
1883 | ||
832ffa1c AG |
1884 | /* Shift a TCGv src by TCGv shift_amount, put result in dst. |
1885 | * Note that it is the caller's responsibility to ensure that the | |
1886 | * shift amount is in range (ie 0..31 or 0..63) and provide the ARM | |
1887 | * mandated semantics for out of range shifts. | |
1888 | */ | |
1889 | static void shift_reg(TCGv_i64 dst, TCGv_i64 src, int sf, | |
1890 | enum a64_shift_type shift_type, TCGv_i64 shift_amount) | |
1891 | { | |
1892 | switch (shift_type) { | |
1893 | case A64_SHIFT_TYPE_LSL: | |
1894 | tcg_gen_shl_i64(dst, src, shift_amount); | |
1895 | break; | |
1896 | case A64_SHIFT_TYPE_LSR: | |
1897 | tcg_gen_shr_i64(dst, src, shift_amount); | |
1898 | break; | |
1899 | case A64_SHIFT_TYPE_ASR: | |
1900 | if (!sf) { | |
1901 | tcg_gen_ext32s_i64(dst, src); | |
1902 | } | |
1903 | tcg_gen_sar_i64(dst, sf ? src : dst, shift_amount); | |
1904 | break; | |
1905 | case A64_SHIFT_TYPE_ROR: | |
1906 | if (sf) { | |
1907 | tcg_gen_rotr_i64(dst, src, shift_amount); | |
1908 | } else { | |
1909 | TCGv_i32 t0, t1; | |
1910 | t0 = tcg_temp_new_i32(); | |
1911 | t1 = tcg_temp_new_i32(); | |
1912 | tcg_gen_trunc_i64_i32(t0, src); | |
1913 | tcg_gen_trunc_i64_i32(t1, shift_amount); | |
1914 | tcg_gen_rotr_i32(t0, t0, t1); | |
1915 | tcg_gen_extu_i32_i64(dst, t0); | |
1916 | tcg_temp_free_i32(t0); | |
1917 | tcg_temp_free_i32(t1); | |
1918 | } | |
1919 | break; | |
1920 | default: | |
1921 | assert(FALSE); /* all shift types should be handled */ | |
1922 | break; | |
1923 | } | |
1924 | ||
1925 | if (!sf) { /* zero extend final result */ | |
1926 | tcg_gen_ext32u_i64(dst, dst); | |
1927 | } | |
1928 | } | |
1929 | ||
1930 | /* Shift a TCGv src by immediate, put result in dst. | |
1931 | * The shift amount must be in range (this should always be true as the | |
1932 | * relevant instructions will UNDEF on bad shift immediates). | |
1933 | */ | |
1934 | static void shift_reg_imm(TCGv_i64 dst, TCGv_i64 src, int sf, | |
1935 | enum a64_shift_type shift_type, unsigned int shift_i) | |
1936 | { | |
1937 | assert(shift_i < (sf ? 64 : 32)); | |
1938 | ||
1939 | if (shift_i == 0) { | |
1940 | tcg_gen_mov_i64(dst, src); | |
1941 | } else { | |
1942 | TCGv_i64 shift_const; | |
1943 | ||
1944 | shift_const = tcg_const_i64(shift_i); | |
1945 | shift_reg(dst, src, sf, shift_type, shift_const); | |
1946 | tcg_temp_free_i64(shift_const); | |
1947 | } | |
1948 | } | |
1949 | ||
1950 | /* C3.5.10 Logical (shifted register) | |
1951 | * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0 | |
1952 | * +----+-----+-----------+-------+---+------+--------+------+------+ | |
1953 | * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd | | |
1954 | * +----+-----+-----------+-------+---+------+--------+------+------+ | |
1955 | */ | |
ad7ee8a2 CF |
1956 | static void disas_logic_reg(DisasContext *s, uint32_t insn) |
1957 | { | |
832ffa1c AG |
1958 | TCGv_i64 tcg_rd, tcg_rn, tcg_rm; |
1959 | unsigned int sf, opc, shift_type, invert, rm, shift_amount, rn, rd; | |
1960 | ||
1961 | sf = extract32(insn, 31, 1); | |
1962 | opc = extract32(insn, 29, 2); | |
1963 | shift_type = extract32(insn, 22, 2); | |
1964 | invert = extract32(insn, 21, 1); | |
1965 | rm = extract32(insn, 16, 5); | |
1966 | shift_amount = extract32(insn, 10, 6); | |
1967 | rn = extract32(insn, 5, 5); | |
1968 | rd = extract32(insn, 0, 5); | |
1969 | ||
1970 | if (!sf && (shift_amount & (1 << 5))) { | |
1971 | unallocated_encoding(s); | |
1972 | return; | |
1973 | } | |
1974 | ||
1975 | tcg_rd = cpu_reg(s, rd); | |
1976 | ||
1977 | if (opc == 1 && shift_amount == 0 && shift_type == 0 && rn == 31) { | |
1978 | /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for | |
1979 | * register-register MOV and MVN, so it is worth special casing. | |
1980 | */ | |
1981 | tcg_rm = cpu_reg(s, rm); | |
1982 | if (invert) { | |
1983 | tcg_gen_not_i64(tcg_rd, tcg_rm); | |
1984 | if (!sf) { | |
1985 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
1986 | } | |
1987 | } else { | |
1988 | if (sf) { | |
1989 | tcg_gen_mov_i64(tcg_rd, tcg_rm); | |
1990 | } else { | |
1991 | tcg_gen_ext32u_i64(tcg_rd, tcg_rm); | |
1992 | } | |
1993 | } | |
1994 | return; | |
1995 | } | |
1996 | ||
1997 | tcg_rm = read_cpu_reg(s, rm, sf); | |
1998 | ||
1999 | if (shift_amount) { | |
2000 | shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, shift_amount); | |
2001 | } | |
2002 | ||
2003 | tcg_rn = cpu_reg(s, rn); | |
2004 | ||
2005 | switch (opc | (invert << 2)) { | |
2006 | case 0: /* AND */ | |
2007 | case 3: /* ANDS */ | |
2008 | tcg_gen_and_i64(tcg_rd, tcg_rn, tcg_rm); | |
2009 | break; | |
2010 | case 1: /* ORR */ | |
2011 | tcg_gen_or_i64(tcg_rd, tcg_rn, tcg_rm); | |
2012 | break; | |
2013 | case 2: /* EOR */ | |
2014 | tcg_gen_xor_i64(tcg_rd, tcg_rn, tcg_rm); | |
2015 | break; | |
2016 | case 4: /* BIC */ | |
2017 | case 7: /* BICS */ | |
2018 | tcg_gen_andc_i64(tcg_rd, tcg_rn, tcg_rm); | |
2019 | break; | |
2020 | case 5: /* ORN */ | |
2021 | tcg_gen_orc_i64(tcg_rd, tcg_rn, tcg_rm); | |
2022 | break; | |
2023 | case 6: /* EON */ | |
2024 | tcg_gen_eqv_i64(tcg_rd, tcg_rn, tcg_rm); | |
2025 | break; | |
2026 | default: | |
2027 | assert(FALSE); | |
2028 | break; | |
2029 | } | |
2030 | ||
2031 | if (!sf) { | |
2032 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
2033 | } | |
2034 | ||
2035 | if (opc == 3) { | |
2036 | gen_logic_CC(sf, tcg_rd); | |
2037 | } | |
ad7ee8a2 CF |
2038 | } |
2039 | ||
b0ff21b4 AB |
2040 | /* |
2041 | * C3.5.1 Add/subtract (extended register) | |
2042 | * | |
2043 | * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0| | |
2044 | * +--+--+--+-----------+-----+--+-------+------+------+----+----+ | |
2045 | * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd | | |
2046 | * +--+--+--+-----------+-----+--+-------+------+------+----+----+ | |
2047 | * | |
2048 | * sf: 0 -> 32bit, 1 -> 64bit | |
2049 | * op: 0 -> add , 1 -> sub | |
2050 | * S: 1 -> set flags | |
2051 | * opt: 00 | |
2052 | * option: extension type (see DecodeRegExtend) | |
2053 | * imm3: optional shift to Rm | |
2054 | * | |
2055 | * Rd = Rn + LSL(extend(Rm), amount) | |
2056 | */ | |
ad7ee8a2 CF |
2057 | static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn) |
2058 | { | |
b0ff21b4 AB |
2059 | int rd = extract32(insn, 0, 5); |
2060 | int rn = extract32(insn, 5, 5); | |
2061 | int imm3 = extract32(insn, 10, 3); | |
2062 | int option = extract32(insn, 13, 3); | |
2063 | int rm = extract32(insn, 16, 5); | |
2064 | bool setflags = extract32(insn, 29, 1); | |
2065 | bool sub_op = extract32(insn, 30, 1); | |
2066 | bool sf = extract32(insn, 31, 1); | |
2067 | ||
2068 | TCGv_i64 tcg_rm, tcg_rn; /* temps */ | |
2069 | TCGv_i64 tcg_rd; | |
2070 | TCGv_i64 tcg_result; | |
2071 | ||
2072 | if (imm3 > 4) { | |
2073 | unallocated_encoding(s); | |
2074 | return; | |
2075 | } | |
2076 | ||
2077 | /* non-flag setting ops may use SP */ | |
2078 | if (!setflags) { | |
2079 | tcg_rn = read_cpu_reg_sp(s, rn, sf); | |
2080 | tcg_rd = cpu_reg_sp(s, rd); | |
2081 | } else { | |
2082 | tcg_rn = read_cpu_reg(s, rn, sf); | |
2083 | tcg_rd = cpu_reg(s, rd); | |
2084 | } | |
2085 | ||
2086 | tcg_rm = read_cpu_reg(s, rm, sf); | |
2087 | ext_and_shift_reg(tcg_rm, tcg_rm, option, imm3); | |
2088 | ||
2089 | tcg_result = tcg_temp_new_i64(); | |
2090 | ||
2091 | if (!setflags) { | |
2092 | if (sub_op) { | |
2093 | tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm); | |
2094 | } else { | |
2095 | tcg_gen_add_i64(tcg_result, tcg_rn, tcg_rm); | |
2096 | } | |
2097 | } else { | |
2098 | if (sub_op) { | |
2099 | gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm); | |
2100 | } else { | |
2101 | gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm); | |
2102 | } | |
2103 | } | |
2104 | ||
2105 | if (sf) { | |
2106 | tcg_gen_mov_i64(tcg_rd, tcg_result); | |
2107 | } else { | |
2108 | tcg_gen_ext32u_i64(tcg_rd, tcg_result); | |
2109 | } | |
2110 | ||
2111 | tcg_temp_free_i64(tcg_result); | |
ad7ee8a2 CF |
2112 | } |
2113 | ||
b0ff21b4 AB |
2114 | /* |
2115 | * C3.5.2 Add/subtract (shifted register) | |
2116 | * | |
2117 | * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0 | |
2118 | * +--+--+--+-----------+-----+--+-------+---------+------+------+ | |
2119 | * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd | | |
2120 | * +--+--+--+-----------+-----+--+-------+---------+------+------+ | |
2121 | * | |
2122 | * sf: 0 -> 32bit, 1 -> 64bit | |
2123 | * op: 0 -> add , 1 -> sub | |
2124 | * S: 1 -> set flags | |
2125 | * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED | |
2126 | * imm6: Shift amount to apply to Rm before the add/sub | |
2127 | */ | |
ad7ee8a2 CF |
2128 | static void disas_add_sub_reg(DisasContext *s, uint32_t insn) |
2129 | { | |
b0ff21b4 AB |
2130 | int rd = extract32(insn, 0, 5); |
2131 | int rn = extract32(insn, 5, 5); | |
2132 | int imm6 = extract32(insn, 10, 6); | |
2133 | int rm = extract32(insn, 16, 5); | |
2134 | int shift_type = extract32(insn, 22, 2); | |
2135 | bool setflags = extract32(insn, 29, 1); | |
2136 | bool sub_op = extract32(insn, 30, 1); | |
2137 | bool sf = extract32(insn, 31, 1); | |
2138 | ||
2139 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
2140 | TCGv_i64 tcg_rn, tcg_rm; | |
2141 | TCGv_i64 tcg_result; | |
2142 | ||
2143 | if ((shift_type == 3) || (!sf && (imm6 > 31))) { | |
2144 | unallocated_encoding(s); | |
2145 | return; | |
2146 | } | |
2147 | ||
2148 | tcg_rn = read_cpu_reg(s, rn, sf); | |
2149 | tcg_rm = read_cpu_reg(s, rm, sf); | |
2150 | ||
2151 | shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, imm6); | |
2152 | ||
2153 | tcg_result = tcg_temp_new_i64(); | |
2154 | ||
2155 | if (!setflags) { | |
2156 | if (sub_op) { | |
2157 | tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm); | |
2158 | } else { | |
2159 | tcg_gen_add_i64(tcg_result, tcg_rn, tcg_rm); | |
2160 | } | |
2161 | } else { | |
2162 | if (sub_op) { | |
2163 | gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm); | |
2164 | } else { | |
2165 | gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm); | |
2166 | } | |
2167 | } | |
2168 | ||
2169 | if (sf) { | |
2170 | tcg_gen_mov_i64(tcg_rd, tcg_result); | |
2171 | } else { | |
2172 | tcg_gen_ext32u_i64(tcg_rd, tcg_result); | |
2173 | } | |
2174 | ||
2175 | tcg_temp_free_i64(tcg_result); | |
ad7ee8a2 CF |
2176 | } |
2177 | ||
52c8b9af AG |
2178 | /* C3.5.9 Data-processing (3 source) |
2179 | ||
2180 | 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0 | |
2181 | +--+------+-----------+------+------+----+------+------+------+ | |
2182 | |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd | | |
2183 | +--+------+-----------+------+------+----+------+------+------+ | |
2184 | ||
2185 | */ | |
ad7ee8a2 CF |
2186 | static void disas_data_proc_3src(DisasContext *s, uint32_t insn) |
2187 | { | |
52c8b9af AG |
2188 | int rd = extract32(insn, 0, 5); |
2189 | int rn = extract32(insn, 5, 5); | |
2190 | int ra = extract32(insn, 10, 5); | |
2191 | int rm = extract32(insn, 16, 5); | |
2192 | int op_id = (extract32(insn, 29, 3) << 4) | | |
2193 | (extract32(insn, 21, 3) << 1) | | |
2194 | extract32(insn, 15, 1); | |
2195 | bool sf = extract32(insn, 31, 1); | |
2196 | bool is_sub = extract32(op_id, 0, 1); | |
2197 | bool is_high = extract32(op_id, 2, 1); | |
2198 | bool is_signed = false; | |
2199 | TCGv_i64 tcg_op1; | |
2200 | TCGv_i64 tcg_op2; | |
2201 | TCGv_i64 tcg_tmp; | |
2202 | ||
2203 | /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */ | |
2204 | switch (op_id) { | |
2205 | case 0x42: /* SMADDL */ | |
2206 | case 0x43: /* SMSUBL */ | |
2207 | case 0x44: /* SMULH */ | |
2208 | is_signed = true; | |
2209 | break; | |
2210 | case 0x0: /* MADD (32bit) */ | |
2211 | case 0x1: /* MSUB (32bit) */ | |
2212 | case 0x40: /* MADD (64bit) */ | |
2213 | case 0x41: /* MSUB (64bit) */ | |
2214 | case 0x4a: /* UMADDL */ | |
2215 | case 0x4b: /* UMSUBL */ | |
2216 | case 0x4c: /* UMULH */ | |
2217 | break; | |
2218 | default: | |
2219 | unallocated_encoding(s); | |
2220 | return; | |
2221 | } | |
2222 | ||
2223 | if (is_high) { | |
2224 | TCGv_i64 low_bits = tcg_temp_new_i64(); /* low bits discarded */ | |
2225 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
2226 | TCGv_i64 tcg_rn = cpu_reg(s, rn); | |
2227 | TCGv_i64 tcg_rm = cpu_reg(s, rm); | |
2228 | ||
2229 | if (is_signed) { | |
2230 | tcg_gen_muls2_i64(low_bits, tcg_rd, tcg_rn, tcg_rm); | |
2231 | } else { | |
2232 | tcg_gen_mulu2_i64(low_bits, tcg_rd, tcg_rn, tcg_rm); | |
2233 | } | |
2234 | ||
2235 | tcg_temp_free_i64(low_bits); | |
2236 | return; | |
2237 | } | |
2238 | ||
2239 | tcg_op1 = tcg_temp_new_i64(); | |
2240 | tcg_op2 = tcg_temp_new_i64(); | |
2241 | tcg_tmp = tcg_temp_new_i64(); | |
2242 | ||
2243 | if (op_id < 0x42) { | |
2244 | tcg_gen_mov_i64(tcg_op1, cpu_reg(s, rn)); | |
2245 | tcg_gen_mov_i64(tcg_op2, cpu_reg(s, rm)); | |
2246 | } else { | |
2247 | if (is_signed) { | |
2248 | tcg_gen_ext32s_i64(tcg_op1, cpu_reg(s, rn)); | |
2249 | tcg_gen_ext32s_i64(tcg_op2, cpu_reg(s, rm)); | |
2250 | } else { | |
2251 | tcg_gen_ext32u_i64(tcg_op1, cpu_reg(s, rn)); | |
2252 | tcg_gen_ext32u_i64(tcg_op2, cpu_reg(s, rm)); | |
2253 | } | |
2254 | } | |
2255 | ||
2256 | if (ra == 31 && !is_sub) { | |
2257 | /* Special-case MADD with rA == XZR; it is the standard MUL alias */ | |
2258 | tcg_gen_mul_i64(cpu_reg(s, rd), tcg_op1, tcg_op2); | |
2259 | } else { | |
2260 | tcg_gen_mul_i64(tcg_tmp, tcg_op1, tcg_op2); | |
2261 | if (is_sub) { | |
2262 | tcg_gen_sub_i64(cpu_reg(s, rd), cpu_reg(s, ra), tcg_tmp); | |
2263 | } else { | |
2264 | tcg_gen_add_i64(cpu_reg(s, rd), cpu_reg(s, ra), tcg_tmp); | |
2265 | } | |
2266 | } | |
2267 | ||
2268 | if (!sf) { | |
2269 | tcg_gen_ext32u_i64(cpu_reg(s, rd), cpu_reg(s, rd)); | |
2270 | } | |
2271 | ||
2272 | tcg_temp_free_i64(tcg_op1); | |
2273 | tcg_temp_free_i64(tcg_op2); | |
2274 | tcg_temp_free_i64(tcg_tmp); | |
ad7ee8a2 CF |
2275 | } |
2276 | ||
2277 | /* Add/subtract (with carry) */ | |
2278 | static void disas_adc_sbc(DisasContext *s, uint32_t insn) | |
2279 | { | |
2280 | unsupported_encoding(s, insn); | |
2281 | } | |
2282 | ||
2283 | /* Conditional compare (immediate) */ | |
2284 | static void disas_cc_imm(DisasContext *s, uint32_t insn) | |
2285 | { | |
2286 | unsupported_encoding(s, insn); | |
2287 | } | |
2288 | ||
2289 | /* Conditional compare (register) */ | |
2290 | static void disas_cc_reg(DisasContext *s, uint32_t insn) | |
2291 | { | |
2292 | unsupported_encoding(s, insn); | |
2293 | } | |
2294 | ||
e952d8c7 CF |
2295 | /* C3.5.6 Conditional select |
2296 | * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0 | |
2297 | * +----+----+---+-----------------+------+------+-----+------+------+ | |
2298 | * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd | | |
2299 | * +----+----+---+-----------------+------+------+-----+------+------+ | |
2300 | */ | |
ad7ee8a2 CF |
2301 | static void disas_cond_select(DisasContext *s, uint32_t insn) |
2302 | { | |
e952d8c7 CF |
2303 | unsigned int sf, else_inv, rm, cond, else_inc, rn, rd; |
2304 | TCGv_i64 tcg_rd, tcg_src; | |
2305 | ||
2306 | if (extract32(insn, 29, 1) || extract32(insn, 11, 1)) { | |
2307 | /* S == 1 or op2<1> == 1 */ | |
2308 | unallocated_encoding(s); | |
2309 | return; | |
2310 | } | |
2311 | sf = extract32(insn, 31, 1); | |
2312 | else_inv = extract32(insn, 30, 1); | |
2313 | rm = extract32(insn, 16, 5); | |
2314 | cond = extract32(insn, 12, 4); | |
2315 | else_inc = extract32(insn, 10, 1); | |
2316 | rn = extract32(insn, 5, 5); | |
2317 | rd = extract32(insn, 0, 5); | |
2318 | ||
2319 | if (rd == 31) { | |
2320 | /* silly no-op write; until we use movcond we must special-case | |
2321 | * this to avoid a dead temporary across basic blocks. | |
2322 | */ | |
2323 | return; | |
2324 | } | |
2325 | ||
2326 | tcg_rd = cpu_reg(s, rd); | |
2327 | ||
2328 | if (cond >= 0x0e) { /* condition "always" */ | |
2329 | tcg_src = read_cpu_reg(s, rn, sf); | |
2330 | tcg_gen_mov_i64(tcg_rd, tcg_src); | |
2331 | } else { | |
2332 | /* OPTME: we could use movcond here, at the cost of duplicating | |
2333 | * a lot of the arm_gen_test_cc() logic. | |
2334 | */ | |
2335 | int label_match = gen_new_label(); | |
2336 | int label_continue = gen_new_label(); | |
2337 | ||
2338 | arm_gen_test_cc(cond, label_match); | |
2339 | /* nomatch: */ | |
2340 | tcg_src = cpu_reg(s, rm); | |
2341 | ||
2342 | if (else_inv && else_inc) { | |
2343 | tcg_gen_neg_i64(tcg_rd, tcg_src); | |
2344 | } else if (else_inv) { | |
2345 | tcg_gen_not_i64(tcg_rd, tcg_src); | |
2346 | } else if (else_inc) { | |
2347 | tcg_gen_addi_i64(tcg_rd, tcg_src, 1); | |
2348 | } else { | |
2349 | tcg_gen_mov_i64(tcg_rd, tcg_src); | |
2350 | } | |
2351 | if (!sf) { | |
2352 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
2353 | } | |
2354 | tcg_gen_br(label_continue); | |
2355 | /* match: */ | |
2356 | gen_set_label(label_match); | |
2357 | tcg_src = read_cpu_reg(s, rn, sf); | |
2358 | tcg_gen_mov_i64(tcg_rd, tcg_src); | |
2359 | /* continue: */ | |
2360 | gen_set_label(label_continue); | |
2361 | } | |
ad7ee8a2 CF |
2362 | } |
2363 | ||
680ead21 CF |
2364 | static void handle_clz(DisasContext *s, unsigned int sf, |
2365 | unsigned int rn, unsigned int rd) | |
2366 | { | |
2367 | TCGv_i64 tcg_rd, tcg_rn; | |
2368 | tcg_rd = cpu_reg(s, rd); | |
2369 | tcg_rn = cpu_reg(s, rn); | |
2370 | ||
2371 | if (sf) { | |
2372 | gen_helper_clz64(tcg_rd, tcg_rn); | |
2373 | } else { | |
2374 | TCGv_i32 tcg_tmp32 = tcg_temp_new_i32(); | |
2375 | tcg_gen_trunc_i64_i32(tcg_tmp32, tcg_rn); | |
2376 | gen_helper_clz(tcg_tmp32, tcg_tmp32); | |
2377 | tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); | |
2378 | tcg_temp_free_i32(tcg_tmp32); | |
2379 | } | |
2380 | } | |
2381 | ||
e80c5020 CF |
2382 | static void handle_cls(DisasContext *s, unsigned int sf, |
2383 | unsigned int rn, unsigned int rd) | |
2384 | { | |
2385 | TCGv_i64 tcg_rd, tcg_rn; | |
2386 | tcg_rd = cpu_reg(s, rd); | |
2387 | tcg_rn = cpu_reg(s, rn); | |
2388 | ||
2389 | if (sf) { | |
2390 | gen_helper_cls64(tcg_rd, tcg_rn); | |
2391 | } else { | |
2392 | TCGv_i32 tcg_tmp32 = tcg_temp_new_i32(); | |
2393 | tcg_gen_trunc_i64_i32(tcg_tmp32, tcg_rn); | |
2394 | gen_helper_cls32(tcg_tmp32, tcg_tmp32); | |
2395 | tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); | |
2396 | tcg_temp_free_i32(tcg_tmp32); | |
2397 | } | |
2398 | } | |
2399 | ||
82e14b02 AG |
2400 | static void handle_rbit(DisasContext *s, unsigned int sf, |
2401 | unsigned int rn, unsigned int rd) | |
2402 | { | |
2403 | TCGv_i64 tcg_rd, tcg_rn; | |
2404 | tcg_rd = cpu_reg(s, rd); | |
2405 | tcg_rn = cpu_reg(s, rn); | |
2406 | ||
2407 | if (sf) { | |
2408 | gen_helper_rbit64(tcg_rd, tcg_rn); | |
2409 | } else { | |
2410 | TCGv_i32 tcg_tmp32 = tcg_temp_new_i32(); | |
2411 | tcg_gen_trunc_i64_i32(tcg_tmp32, tcg_rn); | |
2412 | gen_helper_rbit(tcg_tmp32, tcg_tmp32); | |
2413 | tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); | |
2414 | tcg_temp_free_i32(tcg_tmp32); | |
2415 | } | |
2416 | } | |
2417 | ||
45323209 CF |
2418 | /* C5.6.149 REV with sf==1, opcode==3 ("REV64") */ |
2419 | static void handle_rev64(DisasContext *s, unsigned int sf, | |
2420 | unsigned int rn, unsigned int rd) | |
2421 | { | |
2422 | if (!sf) { | |
2423 | unallocated_encoding(s); | |
2424 | return; | |
2425 | } | |
2426 | tcg_gen_bswap64_i64(cpu_reg(s, rd), cpu_reg(s, rn)); | |
2427 | } | |
2428 | ||
2429 | /* C5.6.149 REV with sf==0, opcode==2 | |
2430 | * C5.6.151 REV32 (sf==1, opcode==2) | |
2431 | */ | |
2432 | static void handle_rev32(DisasContext *s, unsigned int sf, | |
2433 | unsigned int rn, unsigned int rd) | |
2434 | { | |
2435 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
2436 | ||
2437 | if (sf) { | |
2438 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
2439 | TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf); | |
2440 | ||
2441 | /* bswap32_i64 requires zero high word */ | |
2442 | tcg_gen_ext32u_i64(tcg_tmp, tcg_rn); | |
2443 | tcg_gen_bswap32_i64(tcg_rd, tcg_tmp); | |
2444 | tcg_gen_shri_i64(tcg_tmp, tcg_rn, 32); | |
2445 | tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp); | |
2446 | tcg_gen_concat32_i64(tcg_rd, tcg_rd, tcg_tmp); | |
2447 | ||
2448 | tcg_temp_free_i64(tcg_tmp); | |
2449 | } else { | |
2450 | tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rn)); | |
2451 | tcg_gen_bswap32_i64(tcg_rd, tcg_rd); | |
2452 | } | |
2453 | } | |
2454 | ||
2455 | /* C5.6.150 REV16 (opcode==1) */ | |
2456 | static void handle_rev16(DisasContext *s, unsigned int sf, | |
2457 | unsigned int rn, unsigned int rd) | |
2458 | { | |
2459 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
2460 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | |
2461 | TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf); | |
2462 | ||
2463 | tcg_gen_andi_i64(tcg_tmp, tcg_rn, 0xffff); | |
2464 | tcg_gen_bswap16_i64(tcg_rd, tcg_tmp); | |
2465 | ||
2466 | tcg_gen_shri_i64(tcg_tmp, tcg_rn, 16); | |
2467 | tcg_gen_andi_i64(tcg_tmp, tcg_tmp, 0xffff); | |
2468 | tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp); | |
2469 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 16, 16); | |
2470 | ||
2471 | if (sf) { | |
2472 | tcg_gen_shri_i64(tcg_tmp, tcg_rn, 32); | |
2473 | tcg_gen_andi_i64(tcg_tmp, tcg_tmp, 0xffff); | |
2474 | tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp); | |
2475 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 32, 16); | |
2476 | ||
2477 | tcg_gen_shri_i64(tcg_tmp, tcg_rn, 48); | |
2478 | tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp); | |
2479 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 48, 16); | |
2480 | } | |
2481 | ||
2482 | tcg_temp_free_i64(tcg_tmp); | |
2483 | } | |
2484 | ||
680ead21 CF |
2485 | /* C3.5.7 Data-processing (1 source) |
2486 | * 31 30 29 28 21 20 16 15 10 9 5 4 0 | |
2487 | * +----+---+---+-----------------+---------+--------+------+------+ | |
2488 | * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd | | |
2489 | * +----+---+---+-----------------+---------+--------+------+------+ | |
2490 | */ | |
ad7ee8a2 CF |
2491 | static void disas_data_proc_1src(DisasContext *s, uint32_t insn) |
2492 | { | |
680ead21 CF |
2493 | unsigned int sf, opcode, rn, rd; |
2494 | ||
2495 | if (extract32(insn, 29, 1) || extract32(insn, 16, 5)) { | |
2496 | unallocated_encoding(s); | |
2497 | return; | |
2498 | } | |
2499 | ||
2500 | sf = extract32(insn, 31, 1); | |
2501 | opcode = extract32(insn, 10, 6); | |
2502 | rn = extract32(insn, 5, 5); | |
2503 | rd = extract32(insn, 0, 5); | |
2504 | ||
2505 | switch (opcode) { | |
2506 | case 0: /* RBIT */ | |
82e14b02 AG |
2507 | handle_rbit(s, sf, rn, rd); |
2508 | break; | |
680ead21 | 2509 | case 1: /* REV16 */ |
45323209 CF |
2510 | handle_rev16(s, sf, rn, rd); |
2511 | break; | |
680ead21 | 2512 | case 2: /* REV32 */ |
45323209 CF |
2513 | handle_rev32(s, sf, rn, rd); |
2514 | break; | |
680ead21 | 2515 | case 3: /* REV64 */ |
45323209 | 2516 | handle_rev64(s, sf, rn, rd); |
680ead21 CF |
2517 | break; |
2518 | case 4: /* CLZ */ | |
2519 | handle_clz(s, sf, rn, rd); | |
2520 | break; | |
2521 | case 5: /* CLS */ | |
e80c5020 | 2522 | handle_cls(s, sf, rn, rd); |
680ead21 CF |
2523 | break; |
2524 | } | |
ad7ee8a2 CF |
2525 | } |
2526 | ||
8220e911 AG |
2527 | static void handle_div(DisasContext *s, bool is_signed, unsigned int sf, |
2528 | unsigned int rm, unsigned int rn, unsigned int rd) | |
2529 | { | |
2530 | TCGv_i64 tcg_n, tcg_m, tcg_rd; | |
2531 | tcg_rd = cpu_reg(s, rd); | |
2532 | ||
2533 | if (!sf && is_signed) { | |
2534 | tcg_n = new_tmp_a64(s); | |
2535 | tcg_m = new_tmp_a64(s); | |
2536 | tcg_gen_ext32s_i64(tcg_n, cpu_reg(s, rn)); | |
2537 | tcg_gen_ext32s_i64(tcg_m, cpu_reg(s, rm)); | |
2538 | } else { | |
2539 | tcg_n = read_cpu_reg(s, rn, sf); | |
2540 | tcg_m = read_cpu_reg(s, rm, sf); | |
2541 | } | |
2542 | ||
2543 | if (is_signed) { | |
2544 | gen_helper_sdiv64(tcg_rd, tcg_n, tcg_m); | |
2545 | } else { | |
2546 | gen_helper_udiv64(tcg_rd, tcg_n, tcg_m); | |
2547 | } | |
2548 | ||
2549 | if (!sf) { /* zero extend final result */ | |
2550 | tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | |
2551 | } | |
2552 | } | |
2553 | ||
6c1adc91 AG |
2554 | /* C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV */ |
2555 | static void handle_shift_reg(DisasContext *s, | |
2556 | enum a64_shift_type shift_type, unsigned int sf, | |
2557 | unsigned int rm, unsigned int rn, unsigned int rd) | |
2558 | { | |
2559 | TCGv_i64 tcg_shift = tcg_temp_new_i64(); | |
2560 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | |
2561 | TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf); | |
2562 | ||
2563 | tcg_gen_andi_i64(tcg_shift, cpu_reg(s, rm), sf ? 63 : 31); | |
2564 | shift_reg(tcg_rd, tcg_rn, sf, shift_type, tcg_shift); | |
2565 | tcg_temp_free_i64(tcg_shift); | |
2566 | } | |
2567 | ||
8220e911 AG |
2568 | /* C3.5.8 Data-processing (2 source) |
2569 | * 31 30 29 28 21 20 16 15 10 9 5 4 0 | |
2570 | * +----+---+---+-----------------+------+--------+------+------+ | |
2571 | * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd | | |
2572 | * +----+---+---+-----------------+------+--------+------+------+ | |
2573 | */ | |
ad7ee8a2 CF |
2574 | static void disas_data_proc_2src(DisasContext *s, uint32_t insn) |
2575 | { | |
8220e911 AG |
2576 | unsigned int sf, rm, opcode, rn, rd; |
2577 | sf = extract32(insn, 31, 1); | |
2578 | rm = extract32(insn, 16, 5); | |
2579 | opcode = extract32(insn, 10, 6); | |
2580 | rn = extract32(insn, 5, 5); | |
2581 | rd = extract32(insn, 0, 5); | |
2582 | ||
2583 | if (extract32(insn, 29, 1)) { | |
2584 | unallocated_encoding(s); | |
2585 | return; | |
2586 | } | |
2587 | ||
2588 | switch (opcode) { | |
2589 | case 2: /* UDIV */ | |
2590 | handle_div(s, false, sf, rm, rn, rd); | |
2591 | break; | |
2592 | case 3: /* SDIV */ | |
2593 | handle_div(s, true, sf, rm, rn, rd); | |
2594 | break; | |
2595 | case 8: /* LSLV */ | |
6c1adc91 AG |
2596 | handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd); |
2597 | break; | |
8220e911 | 2598 | case 9: /* LSRV */ |
6c1adc91 AG |
2599 | handle_shift_reg(s, A64_SHIFT_TYPE_LSR, sf, rm, rn, rd); |
2600 | break; | |
8220e911 | 2601 | case 10: /* ASRV */ |
6c1adc91 AG |
2602 | handle_shift_reg(s, A64_SHIFT_TYPE_ASR, sf, rm, rn, rd); |
2603 | break; | |
8220e911 | 2604 | case 11: /* RORV */ |
6c1adc91 AG |
2605 | handle_shift_reg(s, A64_SHIFT_TYPE_ROR, sf, rm, rn, rd); |
2606 | break; | |
8220e911 AG |
2607 | case 16: |
2608 | case 17: | |
2609 | case 18: | |
2610 | case 19: | |
2611 | case 20: | |
2612 | case 21: | |
2613 | case 22: | |
2614 | case 23: /* CRC32 */ | |
2615 | unsupported_encoding(s, insn); | |
2616 | break; | |
2617 | default: | |
2618 | unallocated_encoding(s); | |
2619 | break; | |
2620 | } | |
ad7ee8a2 CF |
2621 | } |
2622 | ||
2623 | /* C3.5 Data processing - register */ | |
2624 | static void disas_data_proc_reg(DisasContext *s, uint32_t insn) | |
2625 | { | |
2626 | switch (extract32(insn, 24, 5)) { | |
2627 | case 0x0a: /* Logical (shifted register) */ | |
2628 | disas_logic_reg(s, insn); | |
2629 | break; | |
2630 | case 0x0b: /* Add/subtract */ | |
2631 | if (insn & (1 << 21)) { /* (extended register) */ | |
2632 | disas_add_sub_ext_reg(s, insn); | |
2633 | } else { | |
2634 | disas_add_sub_reg(s, insn); | |
2635 | } | |
2636 | break; | |
2637 | case 0x1b: /* Data-processing (3 source) */ | |
2638 | disas_data_proc_3src(s, insn); | |
2639 | break; | |
2640 | case 0x1a: | |
2641 | switch (extract32(insn, 21, 3)) { | |
2642 | case 0x0: /* Add/subtract (with carry) */ | |
2643 | disas_adc_sbc(s, insn); | |
2644 | break; | |
2645 | case 0x2: /* Conditional compare */ | |
2646 | if (insn & (1 << 11)) { /* (immediate) */ | |
2647 | disas_cc_imm(s, insn); | |
2648 | } else { /* (register) */ | |
2649 | disas_cc_reg(s, insn); | |
2650 | } | |
2651 | break; | |
2652 | case 0x4: /* Conditional select */ | |
2653 | disas_cond_select(s, insn); | |
2654 | break; | |
2655 | case 0x6: /* Data-processing */ | |
2656 | if (insn & (1 << 30)) { /* (1 source) */ | |
2657 | disas_data_proc_1src(s, insn); | |
2658 | } else { /* (2 source) */ | |
2659 | disas_data_proc_2src(s, insn); | |
2660 | } | |
2661 | break; | |
2662 | default: | |
2663 | unallocated_encoding(s); | |
2664 | break; | |
2665 | } | |
2666 | break; | |
2667 | default: | |
2668 | unallocated_encoding(s); | |
2669 | break; | |
2670 | } | |
2671 | } | |
2672 | ||
2673 | /* C3.6 Data processing - SIMD and floating point */ | |
2674 | static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn) | |
2675 | { | |
2676 | unsupported_encoding(s, insn); | |
2677 | } | |
2678 | ||
2679 | /* C3.1 A64 instruction index by encoding */ | |
40f860cd | 2680 | static void disas_a64_insn(CPUARMState *env, DisasContext *s) |
14ade10f AG |
2681 | { |
2682 | uint32_t insn; | |
2683 | ||
2684 | insn = arm_ldl_code(env, s->pc, s->bswap_code); | |
2685 | s->insn = insn; | |
2686 | s->pc += 4; | |
2687 | ||
ad7ee8a2 CF |
2688 | switch (extract32(insn, 25, 4)) { |
2689 | case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */ | |
14ade10f AG |
2690 | unallocated_encoding(s); |
2691 | break; | |
ad7ee8a2 CF |
2692 | case 0x8: case 0x9: /* Data processing - immediate */ |
2693 | disas_data_proc_imm(s, insn); | |
2694 | break; | |
2695 | case 0xa: case 0xb: /* Branch, exception generation and system insns */ | |
2696 | disas_b_exc_sys(s, insn); | |
2697 | break; | |
2698 | case 0x4: | |
2699 | case 0x6: | |
2700 | case 0xc: | |
2701 | case 0xe: /* Loads and stores */ | |
2702 | disas_ldst(s, insn); | |
2703 | break; | |
2704 | case 0x5: | |
2705 | case 0xd: /* Data processing - register */ | |
2706 | disas_data_proc_reg(s, insn); | |
2707 | break; | |
2708 | case 0x7: | |
2709 | case 0xf: /* Data processing - SIMD and floating point */ | |
2710 | disas_data_proc_simd_fp(s, insn); | |
2711 | break; | |
2712 | default: | |
2713 | assert(FALSE); /* all 15 cases should be handled above */ | |
2714 | break; | |
14ade10f | 2715 | } |
11e169de AG |
2716 | |
2717 | /* if we allocated any temporaries, free them here */ | |
2718 | free_tmp_a64(s); | |
40f860cd | 2719 | } |
14ade10f | 2720 | |
40f860cd PM |
2721 | void gen_intermediate_code_internal_a64(ARMCPU *cpu, |
2722 | TranslationBlock *tb, | |
2723 | bool search_pc) | |
2724 | { | |
2725 | CPUState *cs = CPU(cpu); | |
2726 | CPUARMState *env = &cpu->env; | |
2727 | DisasContext dc1, *dc = &dc1; | |
2728 | CPUBreakpoint *bp; | |
2729 | uint16_t *gen_opc_end; | |
2730 | int j, lj; | |
2731 | target_ulong pc_start; | |
2732 | target_ulong next_page_start; | |
2733 | int num_insns; | |
2734 | int max_insns; | |
2735 | ||
2736 | pc_start = tb->pc; | |
2737 | ||
2738 | dc->tb = tb; | |
2739 | ||
2740 | gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE; | |
2741 | ||
2742 | dc->is_jmp = DISAS_NEXT; | |
2743 | dc->pc = pc_start; | |
2744 | dc->singlestep_enabled = cs->singlestep_enabled; | |
2745 | dc->condjmp = 0; | |
2746 | ||
2747 | dc->aarch64 = 1; | |
2748 | dc->thumb = 0; | |
2749 | dc->bswap_code = 0; | |
2750 | dc->condexec_mask = 0; | |
2751 | dc->condexec_cond = 0; | |
2752 | #if !defined(CONFIG_USER_ONLY) | |
2753 | dc->user = 0; | |
2754 | #endif | |
2755 | dc->vfp_enabled = 0; | |
2756 | dc->vec_len = 0; | |
2757 | dc->vec_stride = 0; | |
2758 | ||
11e169de AG |
2759 | init_tmp_a64_array(dc); |
2760 | ||
40f860cd PM |
2761 | next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; |
2762 | lj = -1; | |
2763 | num_insns = 0; | |
2764 | max_insns = tb->cflags & CF_COUNT_MASK; | |
2765 | if (max_insns == 0) { | |
2766 | max_insns = CF_COUNT_MASK; | |
2767 | } | |
2768 | ||
2769 | gen_tb_start(); | |
2770 | ||
2771 | tcg_clear_temp_count(); | |
2772 | ||
2773 | do { | |
2774 | if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { | |
2775 | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { | |
2776 | if (bp->pc == dc->pc) { | |
2777 | gen_exception_insn(dc, 0, EXCP_DEBUG); | |
2778 | /* Advance PC so that clearing the breakpoint will | |
2779 | invalidate this TB. */ | |
2780 | dc->pc += 2; | |
2781 | goto done_generating; | |
2782 | } | |
2783 | } | |
2784 | } | |
2785 | ||
2786 | if (search_pc) { | |
2787 | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; | |
2788 | if (lj < j) { | |
2789 | lj++; | |
2790 | while (lj < j) { | |
2791 | tcg_ctx.gen_opc_instr_start[lj++] = 0; | |
2792 | } | |
2793 | } | |
2794 | tcg_ctx.gen_opc_pc[lj] = dc->pc; | |
2795 | tcg_ctx.gen_opc_instr_start[lj] = 1; | |
2796 | tcg_ctx.gen_opc_icount[lj] = num_insns; | |
2797 | } | |
2798 | ||
2799 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { | |
2800 | gen_io_start(); | |
2801 | } | |
2802 | ||
2803 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { | |
2804 | tcg_gen_debug_insn_start(dc->pc); | |
2805 | } | |
2806 | ||
2807 | disas_a64_insn(env, dc); | |
2808 | ||
2809 | if (tcg_check_temp_count()) { | |
2810 | fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", | |
2811 | dc->pc); | |
2812 | } | |
2813 | ||
2814 | /* Translation stops when a conditional branch is encountered. | |
2815 | * Otherwise the subsequent code could get translated several times. | |
2816 | * Also stop translation when a page boundary is reached. This | |
2817 | * ensures prefetch aborts occur at the right place. | |
2818 | */ | |
2819 | num_insns++; | |
2820 | } while (!dc->is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end && | |
2821 | !cs->singlestep_enabled && | |
2822 | !singlestep && | |
2823 | dc->pc < next_page_start && | |
2824 | num_insns < max_insns); | |
2825 | ||
2826 | if (tb->cflags & CF_LAST_IO) { | |
2827 | gen_io_end(); | |
2828 | } | |
2829 | ||
2830 | if (unlikely(cs->singlestep_enabled) && dc->is_jmp != DISAS_EXC) { | |
2831 | /* Note that this means single stepping WFI doesn't halt the CPU. | |
2832 | * For conditional branch insns this is harmless unreachable code as | |
2833 | * gen_goto_tb() has already handled emitting the debug exception | |
2834 | * (and thus a tb-jump is not possible when singlestepping). | |
2835 | */ | |
2836 | assert(dc->is_jmp != DISAS_TB_JUMP); | |
2837 | if (dc->is_jmp != DISAS_JUMP) { | |
2838 | gen_a64_set_pc_im(dc->pc); | |
2839 | } | |
2840 | gen_exception(EXCP_DEBUG); | |
2841 | } else { | |
2842 | switch (dc->is_jmp) { | |
2843 | case DISAS_NEXT: | |
2844 | gen_goto_tb(dc, 1, dc->pc); | |
2845 | break; | |
2846 | default: | |
2847 | case DISAS_JUMP: | |
2848 | case DISAS_UPDATE: | |
2849 | /* indicate that the hash table must be used to find the next TB */ | |
2850 | tcg_gen_exit_tb(0); | |
2851 | break; | |
2852 | case DISAS_TB_JUMP: | |
2853 | case DISAS_EXC: | |
2854 | case DISAS_SWI: | |
2855 | break; | |
2856 | case DISAS_WFI: | |
2857 | /* This is a special case because we don't want to just halt the CPU | |
2858 | * if trying to debug across a WFI. | |
2859 | */ | |
2860 | gen_helper_wfi(cpu_env); | |
2861 | break; | |
2862 | } | |
2863 | } | |
2864 | ||
2865 | done_generating: | |
2866 | gen_tb_end(tb, num_insns); | |
2867 | *tcg_ctx.gen_opc_ptr = INDEX_op_end; | |
2868 | ||
2869 | #ifdef DEBUG_DISAS | |
2870 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { | |
2871 | qemu_log("----------------\n"); | |
2872 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); | |
2873 | log_target_disas(env, pc_start, dc->pc - pc_start, | |
2874 | dc->thumb | (dc->bswap_code << 1)); | |
2875 | qemu_log("\n"); | |
2876 | } | |
2877 | #endif | |
2878 | if (search_pc) { | |
2879 | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; | |
2880 | lj++; | |
2881 | while (lj <= j) { | |
2882 | tcg_ctx.gen_opc_instr_start[lj++] = 0; | |
2883 | } | |
2884 | } else { | |
2885 | tb->size = dc->pc - pc_start; | |
2886 | tb->icount = num_insns; | |
14ade10f AG |
2887 | } |
2888 | } |